drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 /* Intel GPIO access functions */
  38
  39 #define I2C_RISEFALL_TIME 20
  40
  41 static inline struct intel_gmbus *
  42 to_intel_gmbus(struct i2c_adapter *i2c)
  43 {
  44         return container_of(i2c, struct intel_gmbus, adapter);
  45 }
  46
  47 struct intel_gpio {
  48         struct i2c_adapter adapter;
  49         struct i2c_algo_bit_data algo;
  50         struct drm_i915_private *dev_priv;
  51         u32 reg;
  52 };
  53
  54 void
  55 intel_i2c_reset(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         if (HAS_PCH_SPLIT(dev))
  59                 I915_WRITE(PCH_GMBUS0, 0);
  60         else
  61                 I915_WRITE(GMBUS0, 0);
  62 }
  63
  64 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  65 {
  66         u32 val;
  67
  68         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  69         if (!IS_PINEVIEW(dev_priv->dev))
  70                 return;
  71
  72         val = I915_READ(DSPCLK_GATE_D);
  73         if (enable)
  74                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  75         else
  76                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  77         I915_WRITE(DSPCLK_GATE_D, val);
  78 }
  79
  80 static u32 get_reserved(struct intel_gpio *gpio)
  81 {
  82         struct drm_i915_private *dev_priv = gpio->dev_priv;
  83         struct drm_device *dev = dev_priv->dev;
  84         u32 reserved = 0;
  85
  86         /* On most chips, these bits must be preserved in software. */
  87         if (!IS_I830(dev) && !IS_845G(dev))
  88                 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
  89                                                    GPIO_CLOCK_PULLUP_DISABLE);
  90
  91         return reserved;
  92 }
  93
  94 static int get_clock(void *data)
  95 {
  96         struct intel_gpio *gpio = data;
  97         struct drm_i915_private *dev_priv = gpio->dev_priv;
  98         u32 reserved = get_reserved(gpio);
  99         I915_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
 100         I915_WRITE(gpio->reg, reserved);
 101         return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
 102 }
 103
 104 static int get_data(void *data)
 105 {
 106         struct intel_gpio *gpio = data;
 107         struct drm_i915_private *dev_priv = gpio->dev_priv;
 108         u32 reserved = get_reserved(gpio);
 109         I915_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
 110         I915_WRITE(gpio->reg, reserved);
 111         return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
 112 }
 113
 114 static void set_clock(void *data, int state_high)
 115 {
 116         struct intel_gpio *gpio = data;
 117         struct drm_i915_private *dev_priv = gpio->dev_priv;
 118         u32 reserved = get_reserved(gpio);
 119         u32 clock_bits;
 120
 121         if (state_high)
 122                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 123         else
 124                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 125                         GPIO_CLOCK_VAL_MASK;
 126
 127         I915_WRITE(gpio->reg, reserved | clock_bits);
 128         POSTING_READ(gpio->reg);
 129 }
 130
 131 static void set_data(void *data, int state_high)
 132 {
 133         struct intel_gpio *gpio = data;
 134         struct drm_i915_private *dev_priv = gpio->dev_priv;
 135         u32 reserved = get_reserved(gpio);
 136         u32 data_bits;
 137
 138         if (state_high)
 139                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 140         else
 141                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 142                         GPIO_DATA_VAL_MASK;
 143
 144         I915_WRITE(gpio->reg, reserved | data_bits);
 145         POSTING_READ(gpio->reg);
 146 }
 147
 148 static struct i2c_adapter *
 149 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
 150 {
 151         static const int map_pin_to_reg[] = {
 152                 0,
 153                 GPIOB,
 154                 GPIOA,
 155                 GPIOC,
 156                 GPIOD,
 157                 GPIOE,
 158                 GPIOF,
 159         };
 160         struct intel_gpio *gpio;
 161
 162         if (pin < 1 || pin > 7)
 163                 return NULL;
 164
 165         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
 166         if (gpio == NULL)
 167                 return NULL;
 168
 169         gpio->reg = map_pin_to_reg[pin];
 170         if (HAS_PCH_SPLIT(dev_priv->dev))
 171                 gpio->reg += PCH_GPIOA - GPIOA;
 172         gpio->dev_priv = dev_priv;
 173
 174         snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO%c", "?BACDEF?"[pin]);
 175         gpio->adapter.owner = THIS_MODULE;
 176         gpio->adapter.algo_data = &gpio->algo;
 177         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
 178         gpio->algo.setsda = set_data;
 179         gpio->algo.setscl = set_clock;
 180         gpio->algo.getsda = get_data;
 181         gpio->algo.getscl = get_clock;
 182         gpio->algo.udelay = I2C_RISEFALL_TIME;
 183         gpio->algo.timeout = usecs_to_jiffies(2200);
 184         gpio->algo.data = gpio;
 185
 186         if (i2c_bit_add_bus(&gpio->adapter))
 187                 goto out_free;
 188
 189         return &gpio->adapter;
 190
 191 out_free:
 192         kfree(gpio);
 193         return NULL;
 194 }
 195
 196 static int
 197 intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
 198                      struct i2c_adapter *adapter,
 199                      struct i2c_msg *msgs,
 200                      int num)
 201 {
 202         struct intel_gpio *gpio = container_of(adapter,
 203                                                struct intel_gpio,
 204                                                adapter);
 205         int ret;
 206
 207         intel_i2c_reset(dev_priv->dev);
 208
 209         intel_i2c_quirk_set(dev_priv, true);
 210         set_data(gpio, 1);
 211         set_clock(gpio, 1);
 212         udelay(I2C_RISEFALL_TIME);
 213
 214         ret = adapter->algo->master_xfer(adapter, msgs, num);
 215
 216         set_data(gpio, 1);
 217         set_clock(gpio, 1);
 218         intel_i2c_quirk_set(dev_priv, false);
 219
 220         return ret;
 221 }
 222
 223 static int
 224 gmbus_xfer(struct i2c_adapter *adapter,
 225            struct i2c_msg *msgs,
 226            int num)
 227 {
 228         struct intel_gmbus *bus = container_of(adapter,
 229                                                struct intel_gmbus,
 230                                                adapter);
 231         struct drm_i915_private *dev_priv = adapter->algo_data;
 232         int i, reg_offset;
 233
 234         if (bus->force_bit)
 235                 return intel_i2c_quirk_xfer(dev_priv,
 236                                             bus->force_bit, msgs, num);
 237
 238         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
 239
 240         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 241
 242         for (i = 0; i < num; i++) {
 243                 u16 len = msgs[i].len;
 244                 u8 *buf = msgs[i].buf;
 245
 246                 if (msgs[i].flags & I2C_M_RD) {
 247                         I915_WRITE(GMBUS1 + reg_offset,
 248                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
 249                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 250                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 251                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 252                         POSTING_READ(GMBUS2+reg_offset);
 253                         do {
 254                                 u32 val, loop = 0;
 255
 256                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 257                                         goto timeout;
 258                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 259                                         return 0;
 260
 261                                 val = I915_READ(GMBUS3 + reg_offset);
 262                                 do {
 263                                         *buf++ = val & 0xff;
 264                                         val >>= 8;
 265                                 } while (--len && ++loop < 4);
 266                         } while (len);
 267                 } else {
 268                         u32 val, loop;
 269
 270                         val = loop = 0;
 271                         do {
 272                                 val |= *buf++ << (8 * loop);
 273                         } while (--len && ++loop < 4);
 274
 275                         I915_WRITE(GMBUS3 + reg_offset, val);
 276                         I915_WRITE(GMBUS1 + reg_offset,
 277                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
 278                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
 279                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
 280                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 281                         POSTING_READ(GMBUS2+reg_offset);
 282
 283                         while (len) {
 284                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
 285                                         goto timeout;
 286                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 287                                         return 0;
 288
 289                                 val = loop = 0;
 290                                 do {
 291                                         val |= *buf++ << (8 * loop);
 292                                 } while (--len && ++loop < 4);
 293
 294                                 I915_WRITE(GMBUS3 + reg_offset, val);
 295                                 POSTING_READ(GMBUS2+reg_offset);
 296                         }
 297                 }
 298
 299                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
 300                         goto timeout;
 301                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
 302                         return 0;
 303         }
 304
 305         return num;
 306
 307 timeout:
 308         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
 309                  bus->reg0 & 0xff, bus->adapter.name);
 310         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 311         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
 312         if (!bus->force_bit)
 313                 return -ENOMEM;
 314
 315         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
 316 }
 317
 318 static u32 gmbus_func(struct i2c_adapter *adapter)
 319 {
 320         struct intel_gmbus *bus = container_of(adapter,
 321                                                struct intel_gmbus,
 322                                                adapter);
 323
 324         if (bus->force_bit)
 325                 bus->force_bit->algo->functionality(bus->force_bit);
 326
 327         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 328                 /* I2C_FUNC_10BIT_ADDR | */
 329                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 330                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 331 }
 332
 333 static const struct i2c_algorithm gmbus_algorithm = {
 334         .master_xfer    = gmbus_xfer,
 335         .functionality  = gmbus_func
 336 };
 337
 338 /**
 339  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 340  * @dev: DRM device
 341  */
 342 int intel_setup_gmbus(struct drm_device *dev)
 343 {
 344         static const char *names[GMBUS_NUM_PORTS] = {
 345                 "disabled",
 346                 "ssc",
 347                 "vga",
 348                 "panel",
 349                 "dpc",
 350                 "dpb",
 351                 "reserved"
 352                 "dpd",
 353         };
 354         struct drm_i915_private *dev_priv = dev->dev_private;
 355         int ret, i;
 356
 357         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
 358                                   GFP_KERNEL);
 359         if (dev_priv->gmbus == NULL)
 360                 return -ENOMEM;
 361
 362         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 363                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 364
 365                 bus->adapter.owner = THIS_MODULE;
 366                 bus->adapter.class = I2C_CLASS_DDC;
 367                 snprintf(bus->adapter.name,
 368                          I2C_NAME_SIZE,
 369                          "gmbus %s",
 370                          names[i]);
 371
 372                 bus->adapter.dev.parent = &dev->pdev->dev;
 373                 bus->adapter.algo_data  = dev_priv;
 374
 375                 bus->adapter.algo = &gmbus_algorithm;
 376                 ret = i2c_add_adapter(&bus->adapter);
 377                 if (ret)
 378                         goto err;
 379
 380                 /* By default use a conservative clock rate */
 381                 bus->reg0 = i | GMBUS_RATE_100KHZ;
 382         }
 383
 384         intel_i2c_reset(dev_priv->dev);
 385
 386         return 0;
 387
 388 err:
 389         while (--i) {
 390                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 391                 i2c_del_adapter(&bus->adapter);
 392         }
 393         kfree(dev_priv->gmbus);
 394         dev_priv->gmbus = NULL;
 395         return ret;
 396 }
 397
 398 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 399 {
 400         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 401
 402         /* speed:
 403          * 0x0 = 100 KHz
 404          * 0x1 = 50 KHz
 405          * 0x2 = 400 KHz
 406          * 0x3 = 1000 Khz
 407          */
 408         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
 409 }
 410
 411 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 412 {
 413         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 414
 415         if (force_bit) {
 416                 if (bus->force_bit == NULL) {
 417                         struct drm_i915_private *dev_priv = adapter->algo_data;
 418                         bus->force_bit = intel_gpio_create(dev_priv,
 419                                                            bus->reg0 & 0xff);
 420                 }
 421         } else {
 422                 if (bus->force_bit) {
 423                         i2c_del_adapter(bus->force_bit);
 424                         kfree(bus->force_bit);
 425                         bus->force_bit = NULL;
 426                 }
 427         }
 428 }
 429
 430 void intel_teardown_gmbus(struct drm_device *dev)
 431 {
 432         struct drm_i915_private *dev_priv = dev->dev_private;
 433         int i;
 434
 435         if (dev_priv->gmbus == NULL)
 436                 return;
 437
 438         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 439                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 440                 if (bus->force_bit) {
 441                         i2c_del_adapter(bus->force_bit);
 442                         kfree(bus->force_bit);
 443                 }
 444                 i2c_del_adapter(&bus->adapter);
 445         }
 446
 447         kfree(dev_priv->gmbus);
 448         dev_priv->gmbus = NULL;
 449 }