drm: radeon: fix error value sign
[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_i2c.c
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2008,2010 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *      Eric Anholt <eric@anholt.net>
27  *      Chris Wilson <chris@chris-wilson.co.uk>
28  */
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36
37 /* Intel GPIO access functions */
38
39 #define I2C_RISEFALL_TIME 20
40
41 static inline struct intel_gmbus *
42 to_intel_gmbus(struct i2c_adapter *i2c)
43 {
44         return container_of(i2c, struct intel_gmbus, adapter);
45 }
46
47 struct intel_gpio {
48         struct i2c_adapter adapter;
49         struct i2c_algo_bit_data algo;
50         struct drm_i915_private *dev_priv;
51         u32 reg;
52 };
53
54 void
55 intel_i2c_reset(struct drm_device *dev)
56 {
57         struct drm_i915_private *dev_priv = dev->dev_private;
58         if (HAS_PCH_SPLIT(dev))
59                 I915_WRITE(PCH_GMBUS0, 0);
60         else
61                 I915_WRITE(GMBUS0, 0);
62 }
63
64 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
65 {
66         u32 val;
67
68         /* When using bit bashing for I2C, this bit needs to be set to 1 */
69         if (!IS_PINEVIEW(dev_priv->dev))
70                 return;
71
72         val = I915_READ(DSPCLK_GATE_D);
73         if (enable)
74                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
75         else
76                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
77         I915_WRITE(DSPCLK_GATE_D, val);
78 }
79
80 static u32 get_reserved(struct intel_gpio *gpio)
81 {
82         struct drm_i915_private *dev_priv = gpio->dev_priv;
83         struct drm_device *dev = dev_priv->dev;
84         u32 reserved = 0;
85
86         /* On most chips, these bits must be preserved in software. */
87         if (!IS_I830(dev) && !IS_845G(dev))
88                 reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
89                                                    GPIO_CLOCK_PULLUP_DISABLE);
90
91         return reserved;
92 }
93
94 static int get_clock(void *data)
95 {
96         struct intel_gpio *gpio = data;
97         struct drm_i915_private *dev_priv = gpio->dev_priv;
98         u32 reserved = get_reserved(gpio);
99         I915_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
100         I915_WRITE(gpio->reg, reserved);
101         return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
102 }
103
104 static int get_data(void *data)
105 {
106         struct intel_gpio *gpio = data;
107         struct drm_i915_private *dev_priv = gpio->dev_priv;
108         u32 reserved = get_reserved(gpio);
109         I915_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
110         I915_WRITE(gpio->reg, reserved);
111         return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
112 }
113
114 static void set_clock(void *data, int state_high)
115 {
116         struct intel_gpio *gpio = data;
117         struct drm_i915_private *dev_priv = gpio->dev_priv;
118         u32 reserved = get_reserved(gpio);
119         u32 clock_bits;
120
121         if (state_high)
122                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
123         else
124                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
125                         GPIO_CLOCK_VAL_MASK;
126
127         I915_WRITE(gpio->reg, reserved | clock_bits);
128         POSTING_READ(gpio->reg);
129 }
130
131 static void set_data(void *data, int state_high)
132 {
133         struct intel_gpio *gpio = data;
134         struct drm_i915_private *dev_priv = gpio->dev_priv;
135         u32 reserved = get_reserved(gpio);
136         u32 data_bits;
137
138         if (state_high)
139                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
140         else
141                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
142                         GPIO_DATA_VAL_MASK;
143
144         I915_WRITE(gpio->reg, reserved | data_bits);
145         POSTING_READ(gpio->reg);
146 }
147
148 static struct i2c_adapter *
149 intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
150 {
151         static const int map_pin_to_reg[] = {
152                 0,
153                 GPIOB,
154                 GPIOA,
155                 GPIOC,
156                 GPIOD,
157                 GPIOE,
158                 0,
159                 GPIOF,
160         };
161         struct intel_gpio *gpio;
162
163         if (pin < 1 || pin > 7)
164                 return NULL;
165
166         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
167         if (gpio == NULL)
168                 return NULL;
169
170         gpio->reg = map_pin_to_reg[pin];
171         if (HAS_PCH_SPLIT(dev_priv->dev))
172                 gpio->reg += PCH_GPIOA - GPIOA;
173         gpio->dev_priv = dev_priv;
174
175         snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO%c", "?BACDEF?"[pin]);
176         gpio->adapter.owner = THIS_MODULE;
177         gpio->adapter.algo_data = &gpio->algo;
178         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
179         gpio->algo.setsda = set_data;
180         gpio->algo.setscl = set_clock;
181         gpio->algo.getsda = get_data;
182         gpio->algo.getscl = get_clock;
183         gpio->algo.udelay = I2C_RISEFALL_TIME;
184         gpio->algo.timeout = usecs_to_jiffies(2200);
185         gpio->algo.data = gpio;
186
187         if (i2c_bit_add_bus(&gpio->adapter))
188                 goto out_free;
189
190         return &gpio->adapter;
191
192 out_free:
193         kfree(gpio);
194         return NULL;
195 }
196
197 static int
198 intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
199                      struct i2c_adapter *adapter,
200                      struct i2c_msg *msgs,
201                      int num)
202 {
203         struct intel_gpio *gpio = container_of(adapter,
204                                                struct intel_gpio,
205                                                adapter);
206         int ret;
207
208         intel_i2c_reset(dev_priv->dev);
209
210         intel_i2c_quirk_set(dev_priv, true);
211         set_data(gpio, 1);
212         set_clock(gpio, 1);
213         udelay(I2C_RISEFALL_TIME);
214
215         ret = adapter->algo->master_xfer(adapter, msgs, num);
216
217         set_data(gpio, 1);
218         set_clock(gpio, 1);
219         intel_i2c_quirk_set(dev_priv, false);
220
221         return ret;
222 }
223
224 static int
225 gmbus_xfer(struct i2c_adapter *adapter,
226            struct i2c_msg *msgs,
227            int num)
228 {
229         struct intel_gmbus *bus = container_of(adapter,
230                                                struct intel_gmbus,
231                                                adapter);
232         struct drm_i915_private *dev_priv = adapter->algo_data;
233         int i, reg_offset;
234
235         if (bus->force_bit)
236                 return intel_i2c_quirk_xfer(dev_priv,
237                                             bus->force_bit, msgs, num);
238
239         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
240
241         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
242
243         for (i = 0; i < num; i++) {
244                 u16 len = msgs[i].len;
245                 u8 *buf = msgs[i].buf;
246
247                 if (msgs[i].flags & I2C_M_RD) {
248                         I915_WRITE(GMBUS1 + reg_offset,
249                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
250                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
251                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
252                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
253                         POSTING_READ(GMBUS2+reg_offset);
254                         do {
255                                 u32 val, loop = 0;
256
257                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
258                                         goto timeout;
259                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
260                                         return 0;
261
262                                 val = I915_READ(GMBUS3 + reg_offset);
263                                 do {
264                                         *buf++ = val & 0xff;
265                                         val >>= 8;
266                                 } while (--len && ++loop < 4);
267                         } while (len);
268                 } else {
269                         u32 val, loop;
270
271                         val = loop = 0;
272                         do {
273                                 val |= *buf++ << (8 * loop);
274                         } while (--len && ++loop < 4);
275
276                         I915_WRITE(GMBUS3 + reg_offset, val);
277                         I915_WRITE(GMBUS1 + reg_offset,
278                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
279                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
280                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
281                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
282                         POSTING_READ(GMBUS2+reg_offset);
283
284                         while (len) {
285                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
286                                         goto timeout;
287                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
288                                         return 0;
289
290                                 val = loop = 0;
291                                 do {
292                                         val |= *buf++ << (8 * loop);
293                                 } while (--len && ++loop < 4);
294
295                                 I915_WRITE(GMBUS3 + reg_offset, val);
296                                 POSTING_READ(GMBUS2+reg_offset);
297                         }
298                 }
299
300                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
301                         goto timeout;
302                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
303                         return 0;
304         }
305
306         return num;
307
308 timeout:
309         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
310                  bus->reg0 & 0xff, bus->adapter.name);
311         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
312         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
313         if (!bus->force_bit)
314                 return -ENOMEM;
315
316         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
317 }
318
319 static u32 gmbus_func(struct i2c_adapter *adapter)
320 {
321         struct intel_gmbus *bus = container_of(adapter,
322                                                struct intel_gmbus,
323                                                adapter);
324
325         if (bus->force_bit)
326                 bus->force_bit->algo->functionality(bus->force_bit);
327
328         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
329                 /* I2C_FUNC_10BIT_ADDR | */
330                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
331                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
332 }
333
334 static const struct i2c_algorithm gmbus_algorithm = {
335         .master_xfer    = gmbus_xfer,
336         .functionality  = gmbus_func
337 };
338
339 /**
340  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
341  * @dev: DRM device
342  */
343 int intel_setup_gmbus(struct drm_device *dev)
344 {
345         static const char *names[GMBUS_NUM_PORTS] = {
346                 "disabled",
347                 "ssc",
348                 "vga",
349                 "panel",
350                 "dpc",
351                 "dpb",
352                 "reserved"
353                 "dpd",
354         };
355         struct drm_i915_private *dev_priv = dev->dev_private;
356         int ret, i;
357
358         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
359                                   GFP_KERNEL);
360         if (dev_priv->gmbus == NULL)
361                 return -ENOMEM;
362
363         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
364                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
365
366                 bus->adapter.owner = THIS_MODULE;
367                 bus->adapter.class = I2C_CLASS_DDC;
368                 snprintf(bus->adapter.name,
369                          I2C_NAME_SIZE,
370                          "gmbus %s",
371                          names[i]);
372
373                 bus->adapter.dev.parent = &dev->pdev->dev;
374                 bus->adapter.algo_data  = dev_priv;
375
376                 bus->adapter.algo = &gmbus_algorithm;
377                 ret = i2c_add_adapter(&bus->adapter);
378                 if (ret)
379                         goto err;
380
381                 /* By default use a conservative clock rate */
382                 bus->reg0 = i | GMBUS_RATE_100KHZ;
383
384                 /* XXX force bit banging until GMBUS is fully debugged */
385                 bus->force_bit = intel_gpio_create(dev_priv, i);
386         }
387
388         intel_i2c_reset(dev_priv->dev);
389
390         return 0;
391
392 err:
393         while (--i) {
394                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
395                 i2c_del_adapter(&bus->adapter);
396         }
397         kfree(dev_priv->gmbus);
398         dev_priv->gmbus = NULL;
399         return ret;
400 }
401
402 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
403 {
404         struct intel_gmbus *bus = to_intel_gmbus(adapter);
405
406         /* speed:
407          * 0x0 = 100 KHz
408          * 0x1 = 50 KHz
409          * 0x2 = 400 KHz
410          * 0x3 = 1000 Khz
411          */
412         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
413 }
414
415 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
416 {
417         struct intel_gmbus *bus = to_intel_gmbus(adapter);
418
419         if (force_bit) {
420                 if (bus->force_bit == NULL) {
421                         struct drm_i915_private *dev_priv = adapter->algo_data;
422                         bus->force_bit = intel_gpio_create(dev_priv,
423                                                            bus->reg0 & 0xff);
424                 }
425         } else {
426                 if (bus->force_bit) {
427                         i2c_del_adapter(bus->force_bit);
428                         kfree(bus->force_bit);
429                         bus->force_bit = NULL;
430                 }
431         }
432 }
433
434 void intel_teardown_gmbus(struct drm_device *dev)
435 {
436         struct drm_i915_private *dev_priv = dev->dev_private;
437         int i;
438
439         if (dev_priv->gmbus == NULL)
440                 return;
441
442         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
443                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
444                 if (bus->force_bit) {
445                         i2c_del_adapter(bus->force_bit);
446                         kfree(bus->force_bit);
447                 }
448                 i2c_del_adapter(&bus->adapter);
449         }
450
451         kfree(dev_priv->gmbus);
452         dev_priv->gmbus = NULL;
453 }