drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 struct intel_dp {
  46         struct intel_encoder base;
  47         uint32_t output_reg;
  48         uint32_t DP;
  49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  50         bool has_audio;
  51         int force_audio;
  52         int dpms_mode;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[4];
  56         struct i2c_adapter adapter;
  57         struct i2c_algo_dp_aux_data algo;
  58         bool is_pch_edp;
  59         uint8_t train_set[4];
  60         uint8_t link_status[DP_LINK_STATUS_SIZE];
  61
  62         struct drm_property *force_audio_property;
  63 };
  64
  65 /**
  66  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  67  * @intel_dp: DP struct
  68  *
  69  * If a CPU or PCH DP output is attached to an eDP panel, this function
  70  * will return true, and false otherwise.
  71  */
  72 static bool is_edp(struct intel_dp *intel_dp)
  73 {
  74         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  75 }
  76
  77 /**
  78  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  79  * @intel_dp: DP struct
  80  *
  81  * Returns true if the given DP struct corresponds to a PCH DP port attached
  82  * to an eDP panel, false otherwise.  Helpful for determining whether we
  83  * may need FDI resources for a given DP output or not.
  84  */
  85 static bool is_pch_edp(struct intel_dp *intel_dp)
  86 {
  87         return intel_dp->is_pch_edp;
  88 }
  89
  90 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  91 {
  92         return container_of(encoder, struct intel_dp, base.base);
  93 }
  94
  95 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  96 {
  97         return container_of(intel_attached_encoder(connector),
  98                             struct intel_dp, base);
  99 }
 100
 101 /**
 102  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 103  * @encoder: DRM encoder
 104  *
 105  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 106  * by intel_display.c.
 107  */
 108 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 109 {
 110         struct intel_dp *intel_dp;
 111
 112         if (!encoder)
 113                 return false;
 114
 115         intel_dp = enc_to_intel_dp(encoder);
 116
 117         return is_pch_edp(intel_dp);
 118 }
 119
 120 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 121 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 122 static void intel_dp_link_down(struct intel_dp *intel_dp);
 123
 124 void
 125 intel_edp_link_config (struct intel_encoder *intel_encoder,
 126                        int *lane_num, int *link_bw)
 127 {
 128         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 129
 130         *lane_num = intel_dp->lane_count;
 131         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 132                 *link_bw = 162000;
 133         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 134                 *link_bw = 270000;
 135 }
 136
 137 static int
 138 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 139 {
 140         int max_lane_count = 4;
 141
 142         if (intel_dp->dpcd[0] >= 0x11) {
 143                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
 144                 switch (max_lane_count) {
 145                 case 1: case 2: case 4:
 146                         break;
 147                 default:
 148                         max_lane_count = 4;
 149                 }
 150         }
 151         return max_lane_count;
 152 }
 153
 154 static int
 155 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 156 {
 157         int max_link_bw = intel_dp->dpcd[1];
 158
 159         switch (max_link_bw) {
 160         case DP_LINK_BW_1_62:
 161         case DP_LINK_BW_2_7:
 162                 break;
 163         default:
 164                 max_link_bw = DP_LINK_BW_1_62;
 165                 break;
 166         }
 167         return max_link_bw;
 168 }
 169
 170 static int
 171 intel_dp_link_clock(uint8_t link_bw)
 172 {
 173         if (link_bw == DP_LINK_BW_2_7)
 174                 return 270000;
 175         else
 176                 return 162000;
 177 }
 178
 179 /* I think this is a fiction */
 180 static int
 181 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 182 {
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184
 185         if (is_edp(intel_dp))
 186                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
 187         else
 188                 return pixel_clock * 3;
 189 }
 190
 191 static int
 192 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 193 {
 194         return (max_link_clock * max_lanes * 8) / 10;
 195 }
 196
 197 static int
 198 intel_dp_mode_valid(struct drm_connector *connector,
 199                     struct drm_display_mode *mode)
 200 {
 201         struct intel_dp *intel_dp = intel_attached_dp(connector);
 202         struct drm_device *dev = connector->dev;
 203         struct drm_i915_private *dev_priv = dev->dev_private;
 204         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 205         int max_lanes = intel_dp_max_lane_count(intel_dp);
 206
 207         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 208                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 209                         return MODE_PANEL;
 210
 211                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 212                         return MODE_PANEL;
 213         }
 214
 215         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 216            which are outside spec tolerances but somehow work by magic */
 217         if (!is_edp(intel_dp) &&
 218             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 219              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 220                 return MODE_CLOCK_HIGH;
 221
 222         if (mode->clock < 10000)
 223                 return MODE_CLOCK_LOW;
 224
 225         return MODE_OK;
 226 }
 227
 228 static uint32_t
 229 pack_aux(uint8_t *src, int src_bytes)
 230 {
 231         int     i;
 232         uint32_t v = 0;
 233
 234         if (src_bytes > 4)
 235                 src_bytes = 4;
 236         for (i = 0; i < src_bytes; i++)
 237                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 238         return v;
 239 }
 240
 241 static void
 242 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 243 {
 244         int i;
 245         if (dst_bytes > 4)
 246                 dst_bytes = 4;
 247         for (i = 0; i < dst_bytes; i++)
 248                 dst[i] = src >> ((3-i) * 8);
 249 }
 250
 251 /* hrawclock is 1/4 the FSB frequency */
 252 static int
 253 intel_hrawclk(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t clkcfg;
 257
 258         clkcfg = I915_READ(CLKCFG);
 259         switch (clkcfg & CLKCFG_FSB_MASK) {
 260         case CLKCFG_FSB_400:
 261                 return 100;
 262         case CLKCFG_FSB_533:
 263                 return 133;
 264         case CLKCFG_FSB_667:
 265                 return 166;
 266         case CLKCFG_FSB_800:
 267                 return 200;
 268         case CLKCFG_FSB_1067:
 269                 return 266;
 270         case CLKCFG_FSB_1333:
 271                 return 333;
 272         /* these two are just a guess; one of them might be right */
 273         case CLKCFG_FSB_1600:
 274         case CLKCFG_FSB_1600_ALT:
 275                 return 400;
 276         default:
 277                 return 133;
 278         }
 279 }
 280
 281 static int
 282 intel_dp_aux_ch(struct intel_dp *intel_dp,
 283                 uint8_t *send, int send_bytes,
 284                 uint8_t *recv, int recv_size)
 285 {
 286         uint32_t output_reg = intel_dp->output_reg;
 287         struct drm_device *dev = intel_dp->base.base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         uint32_t ch_ctl = output_reg + 0x10;
 290         uint32_t ch_data = ch_ctl + 4;
 291         int i;
 292         int recv_bytes;
 293         uint32_t status;
 294         uint32_t aux_clock_divider;
 295         int try, precharge;
 296
 297         /* The clock divider is based off the hrawclk,
 298          * and would like to run at 2MHz. So, take the
 299          * hrawclk value and divide by 2 and use that
 300          *
 301          * Note that PCH attached eDP panels should use a 125MHz input
 302          * clock divider.
 303          */
 304         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 305                 if (IS_GEN6(dev))
 306                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 307                 else
 308                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 309         } else if (HAS_PCH_SPLIT(dev))
 310                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 311         else
 312                 aux_clock_divider = intel_hrawclk(dev) / 2;
 313
 314         if (IS_GEN6(dev))
 315                 precharge = 3;
 316         else
 317                 precharge = 5;
 318
 319         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 320                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 321                           I915_READ(ch_ctl));
 322                 return -EBUSY;
 323         }
 324
 325         /* Must try at least 3 times according to DP spec */
 326         for (try = 0; try < 5; try++) {
 327                 /* Load the send data into the aux channel data registers */
 328                 for (i = 0; i < send_bytes; i += 4)
 329                         I915_WRITE(ch_data + i,
 330                                    pack_aux(send + i, send_bytes - i));
 331
 332                 /* Send the command and wait for it to complete */
 333                 I915_WRITE(ch_ctl,
 334                            DP_AUX_CH_CTL_SEND_BUSY |
 335                            DP_AUX_CH_CTL_TIME_OUT_400us |
 336                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 337                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 338                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 339                            DP_AUX_CH_CTL_DONE |
 340                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 341                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 342                 for (;;) {
 343                         status = I915_READ(ch_ctl);
 344                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 345                                 break;
 346                         udelay(100);
 347                 }
 348
 349                 /* Clear done status and any errors */
 350                 I915_WRITE(ch_ctl,
 351                            status |
 352                            DP_AUX_CH_CTL_DONE |
 353                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 354                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 355                 if (status & DP_AUX_CH_CTL_DONE)
 356                         break;
 357         }
 358
 359         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 360                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 361                 return -EBUSY;
 362         }
 363
 364         /* Check for timeout or receive error.
 365          * Timeouts occur when the sink is not connected
 366          */
 367         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 368                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 369                 return -EIO;
 370         }
 371
 372         /* Timeouts occur when the device isn't connected, so they're
 373          * "normal" -- don't fill the kernel log with these */
 374         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 375                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 376                 return -ETIMEDOUT;
 377         }
 378
 379         /* Unload any bytes sent back from the other side */
 380         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 381                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 382         if (recv_bytes > recv_size)
 383                 recv_bytes = recv_size;
 384
 385         for (i = 0; i < recv_bytes; i += 4)
 386                 unpack_aux(I915_READ(ch_data + i),
 387                            recv + i, recv_bytes - i);
 388
 389         return recv_bytes;
 390 }
 391
 392 /* Write data to the aux channel in native mode */
 393 static int
 394 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 395                           uint16_t address, uint8_t *send, int send_bytes)
 396 {
 397         int ret;
 398         uint8_t msg[20];
 399         int msg_bytes;
 400         uint8_t ack;
 401
 402         if (send_bytes > 16)
 403                 return -1;
 404         msg[0] = AUX_NATIVE_WRITE << 4;
 405         msg[1] = address >> 8;
 406         msg[2] = address & 0xff;
 407         msg[3] = send_bytes - 1;
 408         memcpy(&msg[4], send, send_bytes);
 409         msg_bytes = send_bytes + 4;
 410         for (;;) {
 411                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 412                 if (ret < 0)
 413                         return ret;
 414                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 415                         break;
 416                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 417                         udelay(100);
 418                 else
 419                         return -EIO;
 420         }
 421         return send_bytes;
 422 }
 423
 424 /* Write a single byte to the aux channel in native mode */
 425 static int
 426 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 427                             uint16_t address, uint8_t byte)
 428 {
 429         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 430 }
 431
 432 /* read bytes from a native aux channel */
 433 static int
 434 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 435                          uint16_t address, uint8_t *recv, int recv_bytes)
 436 {
 437         uint8_t msg[4];
 438         int msg_bytes;
 439         uint8_t reply[20];
 440         int reply_bytes;
 441         uint8_t ack;
 442         int ret;
 443
 444         msg[0] = AUX_NATIVE_READ << 4;
 445         msg[1] = address >> 8;
 446         msg[2] = address & 0xff;
 447         msg[3] = recv_bytes - 1;
 448
 449         msg_bytes = 4;
 450         reply_bytes = recv_bytes + 1;
 451
 452         for (;;) {
 453                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 454                                       reply, reply_bytes);
 455                 if (ret == 0)
 456                         return -EPROTO;
 457                 if (ret < 0)
 458                         return ret;
 459                 ack = reply[0];
 460                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 461                         memcpy(recv, reply + 1, ret - 1);
 462                         return ret - 1;
 463                 }
 464                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 465                         udelay(100);
 466                 else
 467                         return -EIO;
 468         }
 469 }
 470
 471 static int
 472 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 473                     uint8_t write_byte, uint8_t *read_byte)
 474 {
 475         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 476         struct intel_dp *intel_dp = container_of(adapter,
 477                                                 struct intel_dp,
 478                                                 adapter);
 479         uint16_t address = algo_data->address;
 480         uint8_t msg[5];
 481         uint8_t reply[2];
 482         int msg_bytes;
 483         int reply_bytes;
 484         int ret;
 485
 486         /* Set up the command byte */
 487         if (mode & MODE_I2C_READ)
 488                 msg[0] = AUX_I2C_READ << 4;
 489         else
 490                 msg[0] = AUX_I2C_WRITE << 4;
 491
 492         if (!(mode & MODE_I2C_STOP))
 493                 msg[0] |= AUX_I2C_MOT << 4;
 494
 495         msg[1] = address >> 8;
 496         msg[2] = address;
 497
 498         switch (mode) {
 499         case MODE_I2C_WRITE:
 500                 msg[3] = 0;
 501                 msg[4] = write_byte;
 502                 msg_bytes = 5;
 503                 reply_bytes = 1;
 504                 break;
 505         case MODE_I2C_READ:
 506                 msg[3] = 0;
 507                 msg_bytes = 4;
 508                 reply_bytes = 2;
 509                 break;
 510         default:
 511                 msg_bytes = 3;
 512                 reply_bytes = 1;
 513                 break;
 514         }
 515
 516         for (;;) {
 517           ret = intel_dp_aux_ch(intel_dp,
 518                                 msg, msg_bytes,
 519                                 reply, reply_bytes);
 520                 if (ret < 0) {
 521                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 522                         return ret;
 523                 }
 524                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 525                 case AUX_I2C_REPLY_ACK:
 526                         if (mode == MODE_I2C_READ) {
 527                                 *read_byte = reply[1];
 528                         }
 529                         return reply_bytes - 1;
 530                 case AUX_I2C_REPLY_NACK:
 531                         DRM_DEBUG_KMS("aux_ch nack\n");
 532                         return -EREMOTEIO;
 533                 case AUX_I2C_REPLY_DEFER:
 534                         DRM_DEBUG_KMS("aux_ch defer\n");
 535                         udelay(100);
 536                         break;
 537                 default:
 538                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 539                         return -EREMOTEIO;
 540                 }
 541         }
 542 }
 543
 544 static int
 545 intel_dp_i2c_init(struct intel_dp *intel_dp,
 546                   struct intel_connector *intel_connector, const char *name)
 547 {
 548         DRM_DEBUG_KMS("i2c_init %s\n", name);
 549         intel_dp->algo.running = false;
 550         intel_dp->algo.address = 0;
 551         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 552
 553         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 554         intel_dp->adapter.owner = THIS_MODULE;
 555         intel_dp->adapter.class = I2C_CLASS_DDC;
 556         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 557         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 558         intel_dp->adapter.algo_data = &intel_dp->algo;
 559         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 560
 561         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 562 }
 563
 564 static bool
 565 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 566                     struct drm_display_mode *adjusted_mode)
 567 {
 568         struct drm_device *dev = encoder->dev;
 569         struct drm_i915_private *dev_priv = dev->dev_private;
 570         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 571         int lane_count, clock;
 572         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 573         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 574         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 575
 576         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
 577                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 578                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 579                                         mode, adjusted_mode);
 580                 /*
 581                  * the mode->clock is used to calculate the Data&Link M/N
 582                  * of the pipe. For the eDP the fixed clock should be used.
 583                  */
 584                 mode->clock = dev_priv->panel_fixed_mode->clock;
 585         }
 586
 587         /* Just use VBT values for eDP */
 588         if (is_edp(intel_dp)) {
 589                 intel_dp->lane_count = dev_priv->edp.lanes;
 590                 intel_dp->link_bw = dev_priv->edp.rate;
 591                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 592                 DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n",
 593                               intel_dp->link_bw, intel_dp->lane_count,
 594                               adjusted_mode->clock);
 595                 return true;
 596         }
 597
 598         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 599                 for (clock = 0; clock <= max_clock; clock++) {
 600                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 601
 602                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 603                                         <= link_avail) {
 604                                 intel_dp->link_bw = bws[clock];
 605                                 intel_dp->lane_count = lane_count;
 606                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 607                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 608                                                 "count %d clock %d\n",
 609                                        intel_dp->link_bw, intel_dp->lane_count,
 610                                        adjusted_mode->clock);
 611                                 return true;
 612                         }
 613                 }
 614         }
 615
 616         return false;
 617 }
 618
 619 struct intel_dp_m_n {
 620         uint32_t        tu;
 621         uint32_t        gmch_m;
 622         uint32_t        gmch_n;
 623         uint32_t        link_m;
 624         uint32_t        link_n;
 625 };
 626
 627 static void
 628 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 629 {
 630         while (*num > 0xffffff || *den > 0xffffff) {
 631                 *num >>= 1;
 632                 *den >>= 1;
 633         }
 634 }
 635
 636 static void
 637 intel_dp_compute_m_n(int bpp,
 638                      int nlanes,
 639                      int pixel_clock,
 640                      int link_clock,
 641                      struct intel_dp_m_n *m_n)
 642 {
 643         m_n->tu = 64;
 644         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 645         m_n->gmch_n = link_clock * nlanes;
 646         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 647         m_n->link_m = pixel_clock;
 648         m_n->link_n = link_clock;
 649         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 650 }
 651
 652 void
 653 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 654                  struct drm_display_mode *adjusted_mode)
 655 {
 656         struct drm_device *dev = crtc->dev;
 657         struct drm_mode_config *mode_config = &dev->mode_config;
 658         struct drm_encoder *encoder;
 659         struct drm_i915_private *dev_priv = dev->dev_private;
 660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 661         int lane_count = 4, bpp = 24;
 662         struct intel_dp_m_n m_n;
 663
 664         /*
 665          * Find the lane count in the intel_encoder private
 666          */
 667         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 668                 struct intel_dp *intel_dp;
 669
 670                 if (encoder->crtc != crtc)
 671                         continue;
 672
 673                 intel_dp = enc_to_intel_dp(encoder);
 674                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 675                         lane_count = intel_dp->lane_count;
 676                         break;
 677                 } else if (is_edp(intel_dp)) {
 678                         lane_count = dev_priv->edp.lanes;
 679                         bpp = dev_priv->edp.bpp;
 680                         break;
 681                 }
 682         }
 683
 684         /*
 685          * Compute the GMCH and Link ratios. The '3' here is
 686          * the number of bytes_per_pixel post-LUT, which we always
 687          * set up for 8-bits of R/G/B, or 3 bytes total.
 688          */
 689         intel_dp_compute_m_n(bpp, lane_count,
 690                              mode->clock, adjusted_mode->clock, &m_n);
 691
 692         if (HAS_PCH_SPLIT(dev)) {
 693                 if (intel_crtc->pipe == 0) {
 694                         I915_WRITE(TRANSA_DATA_M1,
 695                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 696                                    m_n.gmch_m);
 697                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 698                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 699                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 700                 } else {
 701                         I915_WRITE(TRANSB_DATA_M1,
 702                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 703                                    m_n.gmch_m);
 704                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 705                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 706                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 707                 }
 708         } else {
 709                 if (intel_crtc->pipe == 0) {
 710                         I915_WRITE(PIPEA_GMCH_DATA_M,
 711                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 712                                    m_n.gmch_m);
 713                         I915_WRITE(PIPEA_GMCH_DATA_N,
 714                                    m_n.gmch_n);
 715                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 716                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 717                 } else {
 718                         I915_WRITE(PIPEB_GMCH_DATA_M,
 719                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 720                                    m_n.gmch_m);
 721                         I915_WRITE(PIPEB_GMCH_DATA_N,
 722                                         m_n.gmch_n);
 723                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 724                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 725                 }
 726         }
 727 }
 728
 729 static void
 730 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 731                   struct drm_display_mode *adjusted_mode)
 732 {
 733         struct drm_device *dev = encoder->dev;
 734         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 735         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         intel_dp->DP = (DP_VOLTAGE_0_4 |
 739                        DP_PRE_EMPHASIS_0);
 740
 741         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 742                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 743         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 744                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 745
 746         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
 747                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 748         else
 749                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 750
 751         switch (intel_dp->lane_count) {
 752         case 1:
 753                 intel_dp->DP |= DP_PORT_WIDTH_1;
 754                 break;
 755         case 2:
 756                 intel_dp->DP |= DP_PORT_WIDTH_2;
 757                 break;
 758         case 4:
 759                 intel_dp->DP |= DP_PORT_WIDTH_4;
 760                 break;
 761         }
 762         if (intel_dp->has_audio)
 763                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 764
 765         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 766         intel_dp->link_configuration[0] = intel_dp->link_bw;
 767         intel_dp->link_configuration[1] = intel_dp->lane_count;
 768
 769         /*
 770          * Check for DPCD version > 1.1 and enhanced framing support
 771          */
 772         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 773                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 774                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 775         }
 776
 777         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 778         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 779                 intel_dp->DP |= DP_PIPEB_SELECT;
 780
 781         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
 782                 /* don't miss out required setting for eDP */
 783                 intel_dp->DP |= DP_PLL_ENABLE;
 784                 if (adjusted_mode->clock < 200000)
 785                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 786                 else
 787                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 788         }
 789 }
 790
 791 /* Returns true if the panel was already on when called */
 792 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
 793 {
 794         struct drm_device *dev = intel_dp->base.base.dev;
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
 797
 798         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 799                 return true;
 800
 801         pp = I915_READ(PCH_PP_CONTROL);
 802
 803         /* ILK workaround: disable reset around power sequence */
 804         pp &= ~PANEL_POWER_RESET;
 805         I915_WRITE(PCH_PP_CONTROL, pp);
 806         POSTING_READ(PCH_PP_CONTROL);
 807
 808         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 809         I915_WRITE(PCH_PP_CONTROL, pp);
 810         POSTING_READ(PCH_PP_CONTROL);
 811
 812         /* Ouch. We need to wait here for some panels, like Dell e6510
 813          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 814          */
 815         msleep(300);
 816
 817         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
 818                      5000))
 819                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 820                           I915_READ(PCH_PP_STATUS));
 821
 822         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 823         I915_WRITE(PCH_PP_CONTROL, pp);
 824         POSTING_READ(PCH_PP_CONTROL);
 825
 826         return false;
 827 }
 828
 829 static void ironlake_edp_panel_off (struct drm_device *dev)
 830 {
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
 833                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 834
 835         pp = I915_READ(PCH_PP_CONTROL);
 836
 837         /* ILK workaround: disable reset around power sequence */
 838         pp &= ~PANEL_POWER_RESET;
 839         I915_WRITE(PCH_PP_CONTROL, pp);
 840         POSTING_READ(PCH_PP_CONTROL);
 841
 842         pp &= ~POWER_TARGET_ON;
 843         I915_WRITE(PCH_PP_CONTROL, pp);
 844         POSTING_READ(PCH_PP_CONTROL);
 845
 846         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
 847                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 848                           I915_READ(PCH_PP_STATUS));
 849
 850         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 851         I915_WRITE(PCH_PP_CONTROL, pp);
 852         POSTING_READ(PCH_PP_CONTROL);
 853
 854         /* Ouch. We need to wait here for some panels, like Dell e6510
 855          * https://bugs.freedesktop.org/show_bug.cgi?id=29278i
 856          */
 857         msleep(300);
 858 }
 859
 860 static void ironlake_edp_backlight_on (struct drm_device *dev)
 861 {
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863         u32 pp;
 864
 865         DRM_DEBUG_KMS("\n");
 866         /*
 867          * If we enable the backlight right away following a panel power
 868          * on, we may see slight flicker as the panel syncs with the eDP
 869          * link.  So delay a bit to make sure the image is solid before
 870          * allowing it to appear.
 871          */
 872         msleep(300);
 873         pp = I915_READ(PCH_PP_CONTROL);
 874         pp |= EDP_BLC_ENABLE;
 875         I915_WRITE(PCH_PP_CONTROL, pp);
 876 }
 877
 878 static void ironlake_edp_backlight_off (struct drm_device *dev)
 879 {
 880         struct drm_i915_private *dev_priv = dev->dev_private;
 881         u32 pp;
 882
 883         DRM_DEBUG_KMS("\n");
 884         pp = I915_READ(PCH_PP_CONTROL);
 885         pp &= ~EDP_BLC_ENABLE;
 886         I915_WRITE(PCH_PP_CONTROL, pp);
 887 }
 888
 889 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 890 {
 891         struct drm_device *dev = encoder->dev;
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 dpa_ctl;
 894
 895         DRM_DEBUG_KMS("\n");
 896         dpa_ctl = I915_READ(DP_A);
 897         dpa_ctl |= DP_PLL_ENABLE;
 898         I915_WRITE(DP_A, dpa_ctl);
 899         POSTING_READ(DP_A);
 900         udelay(200);
 901 }
 902
 903 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 904 {
 905         struct drm_device *dev = encoder->dev;
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         u32 dpa_ctl;
 908
 909         dpa_ctl = I915_READ(DP_A);
 910         dpa_ctl &= ~DP_PLL_ENABLE;
 911         I915_WRITE(DP_A, dpa_ctl);
 912         POSTING_READ(DP_A);
 913         udelay(200);
 914 }
 915
 916 static void intel_dp_prepare(struct drm_encoder *encoder)
 917 {
 918         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 919         struct drm_device *dev = encoder->dev;
 920
 921         if (is_edp(intel_dp)) {
 922                 ironlake_edp_backlight_off(dev);
 923                 ironlake_edp_panel_on(intel_dp);
 924                 if (!is_pch_edp(intel_dp))
 925                         ironlake_edp_pll_on(encoder);
 926                 else
 927                         ironlake_edp_pll_off(encoder);
 928         }
 929         intel_dp_link_down(intel_dp);
 930 }
 931
 932 static void intel_dp_commit(struct drm_encoder *encoder)
 933 {
 934         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 935         struct drm_device *dev = encoder->dev;
 936
 937         intel_dp_start_link_train(intel_dp);
 938
 939         if (is_edp(intel_dp))
 940                 ironlake_edp_panel_on(intel_dp);
 941
 942         intel_dp_complete_link_train(intel_dp);
 943
 944         if (is_edp(intel_dp))
 945                 ironlake_edp_backlight_on(dev);
 946 }
 947
 948 static void
 949 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 950 {
 951         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 952         struct drm_device *dev = encoder->dev;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 955
 956         if (mode != DRM_MODE_DPMS_ON) {
 957                 if (is_edp(intel_dp))
 958                         ironlake_edp_backlight_off(dev);
 959                 intel_dp_link_down(intel_dp);
 960                 if (is_edp(intel_dp))
 961                         ironlake_edp_panel_off(dev);
 962                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
 963                         ironlake_edp_pll_off(encoder);
 964         } else {
 965                 if (is_edp(intel_dp))
 966                         ironlake_edp_panel_on(intel_dp);
 967                 if (!(dp_reg & DP_PORT_EN)) {
 968                         intel_dp_start_link_train(intel_dp);
 969                         intel_dp_complete_link_train(intel_dp);
 970                 }
 971                 if (is_edp(intel_dp))
 972                         ironlake_edp_backlight_on(dev);
 973         }
 974         intel_dp->dpms_mode = mode;
 975 }
 976
 977 /*
 978  * Fetch AUX CH registers 0x202 - 0x207 which contain
 979  * link status information
 980  */
 981 static bool
 982 intel_dp_get_link_status(struct intel_dp *intel_dp)
 983 {
 984         int ret;
 985
 986         ret = intel_dp_aux_native_read(intel_dp,
 987                                        DP_LANE0_1_STATUS,
 988                                        intel_dp->link_status, DP_LINK_STATUS_SIZE);
 989         if (ret != DP_LINK_STATUS_SIZE)
 990                 return false;
 991         return true;
 992 }
 993
 994 static uint8_t
 995 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 996                      int r)
 997 {
 998         return link_status[r - DP_LANE0_1_STATUS];
 999 }
1000
1001 static uint8_t
1002 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1003                                  int lane)
1004 {
1005         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1006         int         s = ((lane & 1) ?
1007                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1008                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1009         uint8_t l = intel_dp_link_status(link_status, i);
1010
1011         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1012 }
1013
1014 static uint8_t
1015 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1016                                       int lane)
1017 {
1018         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1019         int         s = ((lane & 1) ?
1020                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1021                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1022         uint8_t l = intel_dp_link_status(link_status, i);
1023
1024         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1025 }
1026
1027
1028 #if 0
1029 static char     *voltage_names[] = {
1030         "0.4V", "0.6V", "0.8V", "1.2V"
1031 };
1032 static char     *pre_emph_names[] = {
1033         "0dB", "3.5dB", "6dB", "9.5dB"
1034 };
1035 static char     *link_train_names[] = {
1036         "pattern 1", "pattern 2", "idle", "off"
1037 };
1038 #endif
1039
1040 /*
1041  * These are source-specific values; current Intel hardware supports
1042  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1043  */
1044 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1045
1046 static uint8_t
1047 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1048 {
1049         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1050         case DP_TRAIN_VOLTAGE_SWING_400:
1051                 return DP_TRAIN_PRE_EMPHASIS_6;
1052         case DP_TRAIN_VOLTAGE_SWING_600:
1053                 return DP_TRAIN_PRE_EMPHASIS_6;
1054         case DP_TRAIN_VOLTAGE_SWING_800:
1055                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1056         case DP_TRAIN_VOLTAGE_SWING_1200:
1057         default:
1058                 return DP_TRAIN_PRE_EMPHASIS_0;
1059         }
1060 }
1061
1062 static void
1063 intel_get_adjust_train(struct intel_dp *intel_dp)
1064 {
1065         uint8_t v = 0;
1066         uint8_t p = 0;
1067         int lane;
1068
1069         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1070                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1071                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1072
1073                 if (this_v > v)
1074                         v = this_v;
1075                 if (this_p > p)
1076                         p = this_p;
1077         }
1078
1079         if (v >= I830_DP_VOLTAGE_MAX)
1080                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1081
1082         if (p >= intel_dp_pre_emphasis_max(v))
1083                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1084
1085         for (lane = 0; lane < 4; lane++)
1086                 intel_dp->train_set[lane] = v | p;
1087 }
1088
1089 static uint32_t
1090 intel_dp_signal_levels(struct intel_dp *intel_dp)
1091 {
1092         struct drm_device *dev = intel_dp->base.base.dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         uint32_t signal_levels = 0;
1095         u8 train_set = intel_dp->train_set[0];
1096         u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK;
1097         u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK;
1098
1099         if (is_edp(intel_dp)) {
1100                 vswing = dev_priv->edp.vswing;
1101                 preemphasis = dev_priv->edp.preemphasis;
1102         }
1103
1104         switch (vswing) {
1105         case DP_TRAIN_VOLTAGE_SWING_400:
1106         default:
1107                 signal_levels |= DP_VOLTAGE_0_4;
1108                 break;
1109         case DP_TRAIN_VOLTAGE_SWING_600:
1110                 signal_levels |= DP_VOLTAGE_0_6;
1111                 break;
1112         case DP_TRAIN_VOLTAGE_SWING_800:
1113                 signal_levels |= DP_VOLTAGE_0_8;
1114                 break;
1115         case DP_TRAIN_VOLTAGE_SWING_1200:
1116                 signal_levels |= DP_VOLTAGE_1_2;
1117                 break;
1118         }
1119         switch (preemphasis) {
1120         case DP_TRAIN_PRE_EMPHASIS_0:
1121         default:
1122                 signal_levels |= DP_PRE_EMPHASIS_0;
1123                 break;
1124         case DP_TRAIN_PRE_EMPHASIS_3_5:
1125                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1126                 break;
1127         case DP_TRAIN_PRE_EMPHASIS_6:
1128                 signal_levels |= DP_PRE_EMPHASIS_6;
1129                 break;
1130         case DP_TRAIN_PRE_EMPHASIS_9_5:
1131                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1132                 break;
1133         }
1134         return signal_levels;
1135 }
1136
1137 /* Gen6's DP voltage swing and pre-emphasis control */
1138 static uint32_t
1139 intel_gen6_edp_signal_levels(uint8_t train_set)
1140 {
1141         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1142         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1143                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1144         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1145                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1146         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1147                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1148         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1149                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1150         default:
1151                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1152                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1153         }
1154 }
1155
1156 static uint8_t
1157 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1158                       int lane)
1159 {
1160         int i = DP_LANE0_1_STATUS + (lane >> 1);
1161         int s = (lane & 1) * 4;
1162         uint8_t l = intel_dp_link_status(link_status, i);
1163
1164         return (l >> s) & 0xf;
1165 }
1166
1167 /* Check for clock recovery is done on all channels */
1168 static bool
1169 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1170 {
1171         int lane;
1172         uint8_t lane_status;
1173
1174         for (lane = 0; lane < lane_count; lane++) {
1175                 lane_status = intel_get_lane_status(link_status, lane);
1176                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1177                         return false;
1178         }
1179         return true;
1180 }
1181
1182 /* Check to see if channel eq is done on all channels */
1183 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1184                          DP_LANE_CHANNEL_EQ_DONE|\
1185                          DP_LANE_SYMBOL_LOCKED)
1186 static bool
1187 intel_channel_eq_ok(struct intel_dp *intel_dp)
1188 {
1189         uint8_t lane_align;
1190         uint8_t lane_status;
1191         int lane;
1192
1193         lane_align = intel_dp_link_status(intel_dp->link_status,
1194                                           DP_LANE_ALIGN_STATUS_UPDATED);
1195         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1196                 return false;
1197         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1198                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1199                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1200                         return false;
1201         }
1202         return true;
1203 }
1204
1205 static bool
1206 intel_dp_aux_handshake_required(struct intel_dp *intel_dp)
1207 {
1208         struct drm_device *dev = intel_dp->base.base.dev;
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210
1211         if (is_edp(intel_dp) && dev_priv->no_aux_handshake)
1212                 return false;
1213
1214         return true;
1215 }
1216
1217 static bool
1218 intel_dp_set_link_train(struct intel_dp *intel_dp,
1219                         uint32_t dp_reg_value,
1220                         uint8_t dp_train_pat)
1221 {
1222         struct drm_device *dev = intel_dp->base.base.dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         int ret;
1225
1226         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1227         POSTING_READ(intel_dp->output_reg);
1228
1229         if (!intel_dp_aux_handshake_required(intel_dp))
1230                 return true;
1231
1232         intel_dp_aux_native_write_1(intel_dp,
1233                                     DP_TRAINING_PATTERN_SET,
1234                                     dp_train_pat);
1235
1236         ret = intel_dp_aux_native_write(intel_dp,
1237                                         DP_TRAINING_LANE0_SET,
1238                                         intel_dp->train_set, 4);
1239         if (ret != 4)
1240                 return false;
1241
1242         return true;
1243 }
1244
1245 /* Enable corresponding port and start training pattern 1 */
1246 static void
1247 intel_dp_start_link_train(struct intel_dp *intel_dp)
1248 {
1249         struct drm_device *dev = intel_dp->base.base.dev;
1250         struct drm_i915_private *dev_priv = dev->dev_private;
1251         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1252         int i;
1253         uint8_t voltage;
1254         bool clock_recovery = false;
1255         int tries;
1256         u32 reg;
1257         uint32_t DP = intel_dp->DP;
1258
1259         /* Enable output, wait for it to become active */
1260         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1261         POSTING_READ(intel_dp->output_reg);
1262         intel_wait_for_vblank(dev, intel_crtc->pipe);
1263
1264         if (intel_dp_aux_handshake_required(intel_dp))
1265                 /* Write the link configuration data */
1266                 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1267                                           intel_dp->link_configuration,
1268                                           DP_LINK_CONFIGURATION_SIZE);
1269
1270         DP |= DP_PORT_EN;
1271         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1272                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1273         else
1274                 DP &= ~DP_LINK_TRAIN_MASK;
1275         memset(intel_dp->train_set, 0, 4);
1276         voltage = 0xff;
1277         tries = 0;
1278         clock_recovery = false;
1279         for (;;) {
1280                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1281                 uint32_t    signal_levels;
1282                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1283                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1284                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1285                 } else {
1286                         signal_levels = intel_dp_signal_levels(intel_dp);
1287                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1288                 }
1289
1290                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1291                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1292                 else
1293                         reg = DP | DP_LINK_TRAIN_PAT_1;
1294
1295                 if (!intel_dp_set_link_train(intel_dp, reg,
1296                                              DP_TRAINING_PATTERN_1))
1297                         break;
1298                 /* Set training pattern 1 */
1299
1300                 udelay(500);
1301                 if (intel_dp_aux_handshake_required(intel_dp)) {
1302                         break;
1303                 } else {
1304                         if (!intel_dp_get_link_status(intel_dp))
1305                                 break;
1306
1307                         if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1308                                 clock_recovery = true;
1309                                 break;
1310                         }
1311
1312                         /* Check to see if we've tried the max voltage */
1313                         for (i = 0; i < intel_dp->lane_count; i++)
1314                                 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1315                                         break;
1316                         if (i == intel_dp->lane_count)
1317                                 break;
1318
1319                         /* Check to see if we've tried the same voltage 5 times */
1320                         if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1321                                 ++tries;
1322                                 if (tries == 5)
1323                                         break;
1324                         } else
1325                                 tries = 0;
1326                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1327
1328                         /* Compute new intel_dp->train_set as requested by target */
1329                         intel_get_adjust_train(intel_dp);
1330                 }
1331         }
1332
1333         intel_dp->DP = DP;
1334 }
1335
1336 static void
1337 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1338 {
1339         struct drm_device *dev = intel_dp->base.base.dev;
1340         struct drm_i915_private *dev_priv = dev->dev_private;
1341         bool channel_eq = false;
1342         int tries;
1343         u32 reg;
1344         uint32_t DP = intel_dp->DP;
1345
1346         /* channel equalization */
1347         tries = 0;
1348         channel_eq = false;
1349         for (;;) {
1350                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1351                 uint32_t    signal_levels;
1352
1353                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1354                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1355                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1356                 } else {
1357                         signal_levels = intel_dp_signal_levels(intel_dp);
1358                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1359                 }
1360
1361                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1362                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1363                 else
1364                         reg = DP | DP_LINK_TRAIN_PAT_2;
1365
1366                 /* channel eq pattern */
1367                 if (!intel_dp_set_link_train(intel_dp, reg,
1368                                              DP_TRAINING_PATTERN_2))
1369                         break;
1370
1371                 udelay(500);
1372
1373                 if (!intel_dp_aux_handshake_required(intel_dp)) {
1374                         break;
1375                 } else {
1376                         if (!intel_dp_get_link_status(intel_dp))
1377                                 break;
1378
1379                         if (intel_channel_eq_ok(intel_dp)) {
1380                                 channel_eq = true;
1381                                 break;
1382                         }
1383
1384                         /* Try 5 times */
1385                         if (tries > 5)
1386                                 break;
1387
1388                         /* Compute new intel_dp->train_set as requested by target */
1389                         intel_get_adjust_train(intel_dp);
1390                         ++tries;
1391                 }
1392         }
1393         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1394                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1395         else
1396                 reg = DP | DP_LINK_TRAIN_OFF;
1397
1398         I915_WRITE(intel_dp->output_reg, reg);
1399         POSTING_READ(intel_dp->output_reg);
1400         intel_dp_aux_native_write_1(intel_dp,
1401                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1402 }
1403
1404 static void
1405 intel_dp_link_down(struct intel_dp *intel_dp)
1406 {
1407         struct drm_device *dev = intel_dp->base.base.dev;
1408         struct drm_i915_private *dev_priv = dev->dev_private;
1409         uint32_t DP = intel_dp->DP;
1410
1411         DRM_DEBUG_KMS("\n");
1412
1413         if (is_edp(intel_dp)) {
1414                 DP &= ~DP_PLL_ENABLE;
1415                 I915_WRITE(intel_dp->output_reg, DP);
1416                 POSTING_READ(intel_dp->output_reg);
1417                 udelay(100);
1418         }
1419
1420         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1421                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1422                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1423         } else {
1424                 DP &= ~DP_LINK_TRAIN_MASK;
1425                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1426         }
1427         POSTING_READ(intel_dp->output_reg);
1428
1429         msleep(17);
1430
1431         if (is_edp(intel_dp))
1432                 DP |= DP_LINK_TRAIN_OFF;
1433         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1434         POSTING_READ(intel_dp->output_reg);
1435 }
1436
1437 /*
1438  * According to DP spec
1439  * 5.1.2:
1440  *  1. Read DPCD
1441  *  2. Configure link according to Receiver Capabilities
1442  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1443  *  4. Check link status on receipt of hot-plug interrupt
1444  */
1445
1446 static void
1447 intel_dp_check_link_status(struct intel_dp *intel_dp)
1448 {
1449         if (!intel_dp->base.base.crtc)
1450                 return;
1451
1452         if (!intel_dp_get_link_status(intel_dp)) {
1453                 intel_dp_link_down(intel_dp);
1454                 return;
1455         }
1456
1457         if (!intel_channel_eq_ok(intel_dp)) {
1458                 intel_dp_start_link_train(intel_dp);
1459                 intel_dp_complete_link_train(intel_dp);
1460         }
1461 }
1462
1463 static enum drm_connector_status
1464 ironlake_dp_detect(struct intel_dp *intel_dp)
1465 {
1466         enum drm_connector_status status;
1467
1468         /* Can't disconnect eDP */
1469         if (is_edp(intel_dp))
1470                 return connector_status_connected;
1471
1472         status = connector_status_disconnected;
1473         if (intel_dp_aux_native_read(intel_dp,
1474                                      0x000, intel_dp->dpcd,
1475                                      sizeof (intel_dp->dpcd))
1476             == sizeof(intel_dp->dpcd)) {
1477                 if (intel_dp->dpcd[0] != 0)
1478                         status = connector_status_connected;
1479         }
1480         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1481                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1482         return status;
1483 }
1484
1485 static enum drm_connector_status
1486 g4x_dp_detect(struct intel_dp *intel_dp)
1487 {
1488         struct drm_device *dev = intel_dp->base.base.dev;
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         enum drm_connector_status status;
1491         uint32_t temp, bit;
1492
1493         switch (intel_dp->output_reg) {
1494         case DP_B:
1495                 bit = DPB_HOTPLUG_INT_STATUS;
1496                 break;
1497         case DP_C:
1498                 bit = DPC_HOTPLUG_INT_STATUS;
1499                 break;
1500         case DP_D:
1501                 bit = DPD_HOTPLUG_INT_STATUS;
1502                 break;
1503         default:
1504                 return connector_status_unknown;
1505         }
1506
1507         temp = I915_READ(PORT_HOTPLUG_STAT);
1508
1509         if ((temp & bit) == 0)
1510                 return connector_status_disconnected;
1511
1512         status = connector_status_disconnected;
1513         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1514                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1515         {
1516                 if (intel_dp->dpcd[0] != 0)
1517                         status = connector_status_connected;
1518         }
1519
1520         return status;
1521 }
1522
1523 /**
1524  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1525  *
1526  * \return true if DP port is connected.
1527  * \return false if DP port is disconnected.
1528  */
1529 static enum drm_connector_status
1530 intel_dp_detect(struct drm_connector *connector, bool force)
1531 {
1532         struct intel_dp *intel_dp = intel_attached_dp(connector);
1533         struct drm_device *dev = intel_dp->base.base.dev;
1534         enum drm_connector_status status;
1535         struct edid *edid = NULL;
1536
1537         intel_dp->has_audio = false;
1538
1539         if (HAS_PCH_SPLIT(dev))
1540                 status = ironlake_dp_detect(intel_dp);
1541         else
1542                 status = g4x_dp_detect(intel_dp);
1543         if (status != connector_status_connected)
1544                 return status;
1545
1546         if (intel_dp->force_audio) {
1547                 intel_dp->has_audio = intel_dp->force_audio > 0;
1548         } else {
1549                 edid = drm_get_edid(connector, &intel_dp->adapter);
1550                 if (edid) {
1551                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1552                         connector->display_info.raw_edid = NULL;
1553                         kfree(edid);
1554                 }
1555         }
1556
1557         return connector_status_connected;
1558 }
1559
1560 static int intel_dp_get_modes(struct drm_connector *connector)
1561 {
1562         struct intel_dp *intel_dp = intel_attached_dp(connector);
1563         struct drm_device *dev = intel_dp->base.base.dev;
1564         struct drm_i915_private *dev_priv = dev->dev_private;
1565         int ret;
1566
1567         /* We should parse the EDID data and find out if it has an audio sink
1568          */
1569
1570         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1571         if (ret) {
1572                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1573                         struct drm_display_mode *newmode;
1574                         list_for_each_entry(newmode, &connector->probed_modes,
1575                                             head) {
1576                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1577                                         dev_priv->panel_fixed_mode =
1578                                                 drm_mode_duplicate(dev, newmode);
1579                                         break;
1580                                 }
1581                         }
1582                 }
1583
1584                 return ret;
1585         }
1586
1587         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1588         if (is_edp(intel_dp)) {
1589                 if (dev_priv->panel_fixed_mode != NULL) {
1590                         struct drm_display_mode *mode;
1591                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1592                         drm_mode_probed_add(connector, mode);
1593                         return 1;
1594                 }
1595         }
1596         return 0;
1597 }
1598
1599 static int
1600 intel_dp_set_property(struct drm_connector *connector,
1601                       struct drm_property *property,
1602                       uint64_t val)
1603 {
1604         struct intel_dp *intel_dp = intel_attached_dp(connector);
1605         int ret;
1606
1607         ret = drm_connector_property_set_value(connector, property, val);
1608         if (ret)
1609                 return ret;
1610
1611         if (property == intel_dp->force_audio_property) {
1612                 if (val == intel_dp->force_audio)
1613                         return 0;
1614
1615                 intel_dp->force_audio = val;
1616
1617                 if (val > 0 && intel_dp->has_audio)
1618                         return 0;
1619                 if (val < 0 && !intel_dp->has_audio)
1620                         return 0;
1621
1622                 intel_dp->has_audio = val > 0;
1623                 goto done;
1624         }
1625
1626         return -EINVAL;
1627
1628 done:
1629         if (intel_dp->base.base.crtc) {
1630                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1631                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1632                                          crtc->x, crtc->y,
1633                                          crtc->fb);
1634         }
1635
1636         return 0;
1637 }
1638
1639 static void
1640 intel_dp_destroy (struct drm_connector *connector)
1641 {
1642         drm_sysfs_connector_remove(connector);
1643         drm_connector_cleanup(connector);
1644         kfree(connector);
1645 }
1646
1647 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1648 {
1649         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1650
1651         i2c_del_adapter(&intel_dp->adapter);
1652         drm_encoder_cleanup(encoder);
1653         kfree(intel_dp);
1654 }
1655
1656 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1657         .dpms = intel_dp_dpms,
1658         .mode_fixup = intel_dp_mode_fixup,
1659         .prepare = intel_dp_prepare,
1660         .mode_set = intel_dp_mode_set,
1661         .commit = intel_dp_commit,
1662 };
1663
1664 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1665         .dpms = drm_helper_connector_dpms,
1666         .detect = intel_dp_detect,
1667         .fill_modes = drm_helper_probe_single_connector_modes,
1668         .set_property = intel_dp_set_property,
1669         .destroy = intel_dp_destroy,
1670 };
1671
1672 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1673         .get_modes = intel_dp_get_modes,
1674         .mode_valid = intel_dp_mode_valid,
1675         .best_encoder = intel_best_encoder,
1676 };
1677
1678 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1679         .destroy = intel_dp_encoder_destroy,
1680 };
1681
1682 static void
1683 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1684 {
1685         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1686
1687         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1688                 intel_dp_check_link_status(intel_dp);
1689 }
1690
1691 /* Return which DP Port should be selected for Transcoder DP control */
1692 int
1693 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1694 {
1695         struct drm_device *dev = crtc->dev;
1696         struct drm_mode_config *mode_config = &dev->mode_config;
1697         struct drm_encoder *encoder;
1698
1699         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1700                 struct intel_dp *intel_dp;
1701
1702                 if (encoder->crtc != crtc)
1703                         continue;
1704
1705                 intel_dp = enc_to_intel_dp(encoder);
1706                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1707                         return intel_dp->output_reg;
1708         }
1709
1710         return -1;
1711 }
1712
1713 /* check the VBT to see whether the eDP is on DP-D port */
1714 bool intel_dpd_is_edp(struct drm_device *dev)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct child_device_config *p_child;
1718         int i;
1719
1720         if (!dev_priv->child_dev_num)
1721                 return false;
1722
1723         for (i = 0; i < dev_priv->child_dev_num; i++) {
1724                 p_child = dev_priv->child_dev + i;
1725
1726                 if (p_child->dvo_port == PORT_IDPD &&
1727                     p_child->device_type == DEVICE_TYPE_eDP)
1728                         return true;
1729         }
1730         return false;
1731 }
1732
1733 static void
1734 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1735 {
1736         struct drm_device *dev = connector->dev;
1737
1738         intel_dp->force_audio_property =
1739                 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
1740         if (intel_dp->force_audio_property) {
1741                 intel_dp->force_audio_property->values[0] = -1;
1742                 intel_dp->force_audio_property->values[1] = 1;
1743                 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0);
1744         }
1745 }
1746
1747 void
1748 intel_dp_init(struct drm_device *dev, int output_reg)
1749 {
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751         struct drm_connector *connector;
1752         struct intel_dp *intel_dp;
1753         struct intel_encoder *intel_encoder;
1754         struct intel_connector *intel_connector;
1755         const char *name = NULL;
1756         int type;
1757
1758         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1759         if (!intel_dp)
1760                 return;
1761
1762         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1763         if (!intel_connector) {
1764                 kfree(intel_dp);
1765                 return;
1766         }
1767         intel_encoder = &intel_dp->base;
1768
1769         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1770                 if (intel_dpd_is_edp(dev))
1771                         intel_dp->is_pch_edp = true;
1772
1773         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1774                 type = DRM_MODE_CONNECTOR_eDP;
1775                 intel_encoder->type = INTEL_OUTPUT_EDP;
1776         } else {
1777                 type = DRM_MODE_CONNECTOR_DisplayPort;
1778                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1779         }
1780
1781         connector = &intel_connector->base;
1782         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1783         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1784
1785         connector->polled = DRM_CONNECTOR_POLL_HPD;
1786
1787         if (output_reg == DP_B || output_reg == PCH_DP_B)
1788                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1789         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1790                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1791         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1792                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1793
1794         if (is_edp(intel_dp))
1795                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1796
1797         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1798         connector->interlace_allowed = true;
1799         connector->doublescan_allowed = 0;
1800
1801         intel_dp->output_reg = output_reg;
1802         intel_dp->has_audio = false;
1803         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1804
1805         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1806                          DRM_MODE_ENCODER_TMDS);
1807         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1808
1809         intel_connector_attach_encoder(intel_connector, intel_encoder);
1810         drm_sysfs_connector_add(connector);
1811
1812         /* Set up the DDC bus. */
1813         switch (output_reg) {
1814                 case DP_A:
1815                         name = "DPDDC-A";
1816                         break;
1817                 case DP_B:
1818                 case PCH_DP_B:
1819                         dev_priv->hotplug_supported_mask |=
1820                                 HDMIB_HOTPLUG_INT_STATUS;
1821                         name = "DPDDC-B";
1822                         break;
1823                 case DP_C:
1824                 case PCH_DP_C:
1825                         dev_priv->hotplug_supported_mask |=
1826                                 HDMIC_HOTPLUG_INT_STATUS;
1827                         name = "DPDDC-C";
1828                         break;
1829                 case DP_D:
1830                 case PCH_DP_D:
1831                         dev_priv->hotplug_supported_mask |=
1832                                 HDMID_HOTPLUG_INT_STATUS;
1833                         name = "DPDDC-D";
1834                         break;
1835         }
1836
1837         intel_dp_i2c_init(intel_dp, intel_connector, name);
1838
1839         /* Cache some DPCD data in the eDP case */
1840         if (is_edp(intel_dp)) {
1841                 int ret;
1842                 bool was_on;
1843
1844                 was_on = ironlake_edp_panel_on(intel_dp);
1845                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1846                                                intel_dp->dpcd,
1847                                                sizeof(intel_dp->dpcd));
1848                 if (ret == sizeof(intel_dp->dpcd)) {
1849                         if (intel_dp->dpcd[0] >= 0x11)
1850                                 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1851                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1852                 } else {
1853                         DRM_ERROR("failed to retrieve link info\n");
1854                 }
1855                 if (!was_on)
1856                         ironlake_edp_panel_off(dev);
1857         }
1858
1859         intel_encoder->hot_plug = intel_dp_hot_plug;
1860
1861         if (is_edp(intel_dp)) {
1862                 /* initialize panel mode from VBT if available for eDP */
1863                 if (dev_priv->lfp_lvds_vbt_mode) {
1864                         dev_priv->panel_fixed_mode =
1865                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1866                         if (dev_priv->panel_fixed_mode) {
1867                                 dev_priv->panel_fixed_mode->type |=
1868                                         DRM_MODE_TYPE_PREFERRED;
1869                         }
1870                 }
1871         }
1872
1873         intel_dp_add_properties(intel_dp, connector);
1874
1875         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1876          * 0xd.  Failure to do so will result in spurious interrupts being
1877          * generated on the port when a cable is not attached.
1878          */
1879         if (IS_G4X(dev) && !IS_GM45(dev)) {
1880                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1881                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1882         }
1883 }