drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp)
 212 {
 213         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 215         int bpp = 24;
 216
 217         if (check_bpp)
 218                 bpp = check_bpp;
 219         else if (intel_crtc)
 220                 bpp = intel_crtc->bpp;
 221
 222         return (pixel_clock * bpp + 9) / 10;
 223 }
 224
 225 static int
 226 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 227 {
 228         return (max_link_clock * max_lanes * 8) / 10;
 229 }
 230
 231 static int
 232 intel_dp_mode_valid(struct drm_connector *connector,
 233                     struct drm_display_mode *mode)
 234 {
 235         struct intel_dp *intel_dp = intel_attached_dp(connector);
 236         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 237         int max_lanes = intel_dp_max_lane_count(intel_dp);
 238         int max_rate, mode_rate;
 239
 240         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 241                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 242                         return MODE_PANEL;
 243
 244                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 245                         return MODE_PANEL;
 246         }
 247
 248         mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0);
 249         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 250
 251         if (mode_rate > max_rate) {
 252                         mode_rate = intel_dp_link_required(intel_dp,
 253                                                            mode->clock, 18);
 254                         if (mode_rate > max_rate)
 255                                 return MODE_CLOCK_HIGH;
 256                         else
 257                                 mode->private_flags |= INTEL_MODE_DP_FORCE_6BPC;
 258         }
 259
 260         if (mode->clock < 10000)
 261                 return MODE_CLOCK_LOW;
 262
 263         return MODE_OK;
 264 }
 265
 266 static uint32_t
 267 pack_aux(uint8_t *src, int src_bytes)
 268 {
 269         int     i;
 270         uint32_t v = 0;
 271
 272         if (src_bytes > 4)
 273                 src_bytes = 4;
 274         for (i = 0; i < src_bytes; i++)
 275                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 276         return v;
 277 }
 278
 279 static void
 280 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 281 {
 282         int i;
 283         if (dst_bytes > 4)
 284                 dst_bytes = 4;
 285         for (i = 0; i < dst_bytes; i++)
 286                 dst[i] = src >> ((3-i) * 8);
 287 }
 288
 289 /* hrawclock is 1/4 the FSB frequency */
 290 static int
 291 intel_hrawclk(struct drm_device *dev)
 292 {
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         uint32_t clkcfg;
 295
 296         clkcfg = I915_READ(CLKCFG);
 297         switch (clkcfg & CLKCFG_FSB_MASK) {
 298         case CLKCFG_FSB_400:
 299                 return 100;
 300         case CLKCFG_FSB_533:
 301                 return 133;
 302         case CLKCFG_FSB_667:
 303                 return 166;
 304         case CLKCFG_FSB_800:
 305                 return 200;
 306         case CLKCFG_FSB_1067:
 307                 return 266;
 308         case CLKCFG_FSB_1333:
 309                 return 333;
 310         /* these two are just a guess; one of them might be right */
 311         case CLKCFG_FSB_1600:
 312         case CLKCFG_FSB_1600_ALT:
 313                 return 400;
 314         default:
 315                 return 133;
 316         }
 317 }
 318
 319 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp->base.base.dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 325 }
 326
 327 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 328 {
 329         struct drm_device *dev = intel_dp->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331
 332         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 333 }
 334
 335 static void
 336 intel_dp_check_edp(struct intel_dp *intel_dp)
 337 {
 338         struct drm_device *dev = intel_dp->base.base.dev;
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (!is_edp(intel_dp))
 342                 return;
 343         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 344                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 345                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 346                               I915_READ(PCH_PP_STATUS),
 347                               I915_READ(PCH_PP_CONTROL));
 348         }
 349 }
 350
 351 static int
 352 intel_dp_aux_ch(struct intel_dp *intel_dp,
 353                 uint8_t *send, int send_bytes,
 354                 uint8_t *recv, int recv_size)
 355 {
 356         uint32_t output_reg = intel_dp->output_reg;
 357         struct drm_device *dev = intel_dp->base.base.dev;
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         uint32_t ch_ctl = output_reg + 0x10;
 360         uint32_t ch_data = ch_ctl + 4;
 361         int i;
 362         int recv_bytes;
 363         uint32_t status;
 364         uint32_t aux_clock_divider;
 365         int try, precharge;
 366
 367         intel_dp_check_edp(intel_dp);
 368         /* The clock divider is based off the hrawclk,
 369          * and would like to run at 2MHz. So, take the
 370          * hrawclk value and divide by 2 and use that
 371          *
 372          * Note that PCH attached eDP panels should use a 125MHz input
 373          * clock divider.
 374          */
 375         if (is_cpu_edp(intel_dp)) {
 376                 if (IS_GEN6(dev) || IS_GEN7(dev))
 377                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 378                 else
 379                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 380         } else if (HAS_PCH_SPLIT(dev))
 381                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 382         else
 383                 aux_clock_divider = intel_hrawclk(dev) / 2;
 384
 385         if (IS_GEN6(dev))
 386                 precharge = 3;
 387         else
 388                 precharge = 5;
 389
 390         /* Try to wait for any previous AUX channel activity */
 391         for (try = 0; try < 3; try++) {
 392                 status = I915_READ(ch_ctl);
 393                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 394                         break;
 395                 msleep(1);
 396         }
 397
 398         if (try == 3) {
 399                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 400                      I915_READ(ch_ctl));
 401                 return -EBUSY;
 402         }
 403
 404         /* Must try at least 3 times according to DP spec */
 405         for (try = 0; try < 5; try++) {
 406                 /* Load the send data into the aux channel data registers */
 407                 for (i = 0; i < send_bytes; i += 4)
 408                         I915_WRITE(ch_data + i,
 409                                    pack_aux(send + i, send_bytes - i));
 410
 411                 /* Send the command and wait for it to complete */
 412                 I915_WRITE(ch_ctl,
 413                            DP_AUX_CH_CTL_SEND_BUSY |
 414                            DP_AUX_CH_CTL_TIME_OUT_400us |
 415                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 416                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 417                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 418                            DP_AUX_CH_CTL_DONE |
 419                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 420                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 421                 for (;;) {
 422                         status = I915_READ(ch_ctl);
 423                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 424                                 break;
 425                         udelay(100);
 426                 }
 427
 428                 /* Clear done status and any errors */
 429                 I915_WRITE(ch_ctl,
 430                            status |
 431                            DP_AUX_CH_CTL_DONE |
 432                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 433                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 434                 if (status & DP_AUX_CH_CTL_DONE)
 435                         break;
 436         }
 437
 438         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 439                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 440                 return -EBUSY;
 441         }
 442
 443         /* Check for timeout or receive error.
 444          * Timeouts occur when the sink is not connected
 445          */
 446         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 447                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 448                 return -EIO;
 449         }
 450
 451         /* Timeouts occur when the device isn't connected, so they're
 452          * "normal" -- don't fill the kernel log with these */
 453         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 454                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 455                 return -ETIMEDOUT;
 456         }
 457
 458         /* Unload any bytes sent back from the other side */
 459         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 460                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 461         if (recv_bytes > recv_size)
 462                 recv_bytes = recv_size;
 463
 464         for (i = 0; i < recv_bytes; i += 4)
 465                 unpack_aux(I915_READ(ch_data + i),
 466                            recv + i, recv_bytes - i);
 467
 468         return recv_bytes;
 469 }
 470
 471 /* Write data to the aux channel in native mode */
 472 static int
 473 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 474                           uint16_t address, uint8_t *send, int send_bytes)
 475 {
 476         int ret;
 477         uint8_t msg[20];
 478         int msg_bytes;
 479         uint8_t ack;
 480
 481         intel_dp_check_edp(intel_dp);
 482         if (send_bytes > 16)
 483                 return -1;
 484         msg[0] = AUX_NATIVE_WRITE << 4;
 485         msg[1] = address >> 8;
 486         msg[2] = address & 0xff;
 487         msg[3] = send_bytes - 1;
 488         memcpy(&msg[4], send, send_bytes);
 489         msg_bytes = send_bytes + 4;
 490         for (;;) {
 491                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 492                 if (ret < 0)
 493                         return ret;
 494                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 495                         break;
 496                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 497                         udelay(100);
 498                 else
 499                         return -EIO;
 500         }
 501         return send_bytes;
 502 }
 503
 504 /* Write a single byte to the aux channel in native mode */
 505 static int
 506 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 507                             uint16_t address, uint8_t byte)
 508 {
 509         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 510 }
 511
 512 /* read bytes from a native aux channel */
 513 static int
 514 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 515                          uint16_t address, uint8_t *recv, int recv_bytes)
 516 {
 517         uint8_t msg[4];
 518         int msg_bytes;
 519         uint8_t reply[20];
 520         int reply_bytes;
 521         uint8_t ack;
 522         int ret;
 523
 524         intel_dp_check_edp(intel_dp);
 525         msg[0] = AUX_NATIVE_READ << 4;
 526         msg[1] = address >> 8;
 527         msg[2] = address & 0xff;
 528         msg[3] = recv_bytes - 1;
 529
 530         msg_bytes = 4;
 531         reply_bytes = recv_bytes + 1;
 532
 533         for (;;) {
 534                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 535                                       reply, reply_bytes);
 536                 if (ret == 0)
 537                         return -EPROTO;
 538                 if (ret < 0)
 539                         return ret;
 540                 ack = reply[0];
 541                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 542                         memcpy(recv, reply + 1, ret - 1);
 543                         return ret - 1;
 544                 }
 545                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 546                         udelay(100);
 547                 else
 548                         return -EIO;
 549         }
 550 }
 551
 552 static int
 553 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 554                     uint8_t write_byte, uint8_t *read_byte)
 555 {
 556         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 557         struct intel_dp *intel_dp = container_of(adapter,
 558                                                 struct intel_dp,
 559                                                 adapter);
 560         uint16_t address = algo_data->address;
 561         uint8_t msg[5];
 562         uint8_t reply[2];
 563         unsigned retry;
 564         int msg_bytes;
 565         int reply_bytes;
 566         int ret;
 567
 568         intel_dp_check_edp(intel_dp);
 569         /* Set up the command byte */
 570         if (mode & MODE_I2C_READ)
 571                 msg[0] = AUX_I2C_READ << 4;
 572         else
 573                 msg[0] = AUX_I2C_WRITE << 4;
 574
 575         if (!(mode & MODE_I2C_STOP))
 576                 msg[0] |= AUX_I2C_MOT << 4;
 577
 578         msg[1] = address >> 8;
 579         msg[2] = address;
 580
 581         switch (mode) {
 582         case MODE_I2C_WRITE:
 583                 msg[3] = 0;
 584                 msg[4] = write_byte;
 585                 msg_bytes = 5;
 586                 reply_bytes = 1;
 587                 break;
 588         case MODE_I2C_READ:
 589                 msg[3] = 0;
 590                 msg_bytes = 4;
 591                 reply_bytes = 2;
 592                 break;
 593         default:
 594                 msg_bytes = 3;
 595                 reply_bytes = 1;
 596                 break;
 597         }
 598
 599         for (retry = 0; retry < 5; retry++) {
 600                 ret = intel_dp_aux_ch(intel_dp,
 601                                       msg, msg_bytes,
 602                                       reply, reply_bytes);
 603                 if (ret < 0) {
 604                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 605                         return ret;
 606                 }
 607
 608                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 609                 case AUX_NATIVE_REPLY_ACK:
 610                         /* I2C-over-AUX Reply field is only valid
 611                          * when paired with AUX ACK.
 612                          */
 613                         break;
 614                 case AUX_NATIVE_REPLY_NACK:
 615                         DRM_DEBUG_KMS("aux_ch native nack\n");
 616                         return -EREMOTEIO;
 617                 case AUX_NATIVE_REPLY_DEFER:
 618                         udelay(100);
 619                         continue;
 620                 default:
 621                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 622                                   reply[0]);
 623                         return -EREMOTEIO;
 624                 }
 625
 626                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 627                 case AUX_I2C_REPLY_ACK:
 628                         if (mode == MODE_I2C_READ) {
 629                                 *read_byte = reply[1];
 630                         }
 631                         return reply_bytes - 1;
 632                 case AUX_I2C_REPLY_NACK:
 633                         DRM_DEBUG_KMS("aux_i2c nack\n");
 634                         return -EREMOTEIO;
 635                 case AUX_I2C_REPLY_DEFER:
 636                         DRM_DEBUG_KMS("aux_i2c defer\n");
 637                         udelay(100);
 638                         break;
 639                 default:
 640                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 641                         return -EREMOTEIO;
 642                 }
 643         }
 644
 645         DRM_ERROR("too many retries, giving up\n");
 646         return -EREMOTEIO;
 647 }
 648
 649 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 650 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 651
 652 static int
 653 intel_dp_i2c_init(struct intel_dp *intel_dp,
 654                   struct intel_connector *intel_connector, const char *name)
 655 {
 656         int     ret;
 657
 658         DRM_DEBUG_KMS("i2c_init %s\n", name);
 659         intel_dp->algo.running = false;
 660         intel_dp->algo.address = 0;
 661         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 662
 663         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 664         intel_dp->adapter.owner = THIS_MODULE;
 665         intel_dp->adapter.class = I2C_CLASS_DDC;
 666         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 667         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 668         intel_dp->adapter.algo_data = &intel_dp->algo;
 669         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 670
 671         ironlake_edp_panel_vdd_on(intel_dp);
 672         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 673         ironlake_edp_panel_vdd_off(intel_dp, false);
 674         return ret;
 675 }
 676
 677 static bool
 678 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 679                     struct drm_display_mode *adjusted_mode)
 680 {
 681         struct drm_device *dev = encoder->dev;
 682         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 683         int lane_count, clock;
 684         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 685         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 686         int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0;
 687         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 688
 689         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 690                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 691                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 692                                         mode, adjusted_mode);
 693                 /*
 694                  * the mode->clock is used to calculate the Data&Link M/N
 695                  * of the pipe. For the eDP the fixed clock should be used.
 696                  */
 697                 mode->clock = intel_dp->panel_fixed_mode->clock;
 698         }
 699
 700         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 701                 for (clock = 0; clock <= max_clock; clock++) {
 702                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 703
 704                         if (intel_dp_link_required(intel_dp, mode->clock, bpp)
 705                                         <= link_avail) {
 706                                 intel_dp->link_bw = bws[clock];
 707                                 intel_dp->lane_count = lane_count;
 708                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 709                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 710                                                 "count %d clock %d\n",
 711                                        intel_dp->link_bw, intel_dp->lane_count,
 712                                        adjusted_mode->clock);
 713                                 return true;
 714                         }
 715                 }
 716         }
 717
 718         return false;
 719 }
 720
 721 struct intel_dp_m_n {
 722         uint32_t        tu;
 723         uint32_t        gmch_m;
 724         uint32_t        gmch_n;
 725         uint32_t        link_m;
 726         uint32_t        link_n;
 727 };
 728
 729 static void
 730 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 731 {
 732         while (*num > 0xffffff || *den > 0xffffff) {
 733                 *num >>= 1;
 734                 *den >>= 1;
 735         }
 736 }
 737
 738 static void
 739 intel_dp_compute_m_n(int bpp,
 740                      int nlanes,
 741                      int pixel_clock,
 742                      int link_clock,
 743                      struct intel_dp_m_n *m_n)
 744 {
 745         m_n->tu = 64;
 746         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 747         m_n->gmch_n = link_clock * nlanes;
 748         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 749         m_n->link_m = pixel_clock;
 750         m_n->link_n = link_clock;
 751         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 752 }
 753
 754 void
 755 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 756                  struct drm_display_mode *adjusted_mode)
 757 {
 758         struct drm_device *dev = crtc->dev;
 759         struct drm_mode_config *mode_config = &dev->mode_config;
 760         struct drm_encoder *encoder;
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 763         int lane_count = 4;
 764         struct intel_dp_m_n m_n;
 765         int pipe = intel_crtc->pipe;
 766
 767         /*
 768          * Find the lane count in the intel_encoder private
 769          */
 770         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 771                 struct intel_dp *intel_dp;
 772
 773                 if (encoder->crtc != crtc)
 774                         continue;
 775
 776                 intel_dp = enc_to_intel_dp(encoder);
 777                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 778                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 779                 {
 780                         lane_count = intel_dp->lane_count;
 781                         break;
 782                 }
 783         }
 784
 785         /*
 786          * Compute the GMCH and Link ratios. The '3' here is
 787          * the number of bytes_per_pixel post-LUT, which we always
 788          * set up for 8-bits of R/G/B, or 3 bytes total.
 789          */
 790         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 791                              mode->clock, adjusted_mode->clock, &m_n);
 792
 793         if (HAS_PCH_SPLIT(dev)) {
 794                 I915_WRITE(TRANSDATA_M1(pipe),
 795                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 796                            m_n.gmch_m);
 797                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 798                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 799                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 800         } else {
 801                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 802                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 803                            m_n.gmch_m);
 804                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 805                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 806                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 807         }
 808 }
 809
 810 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 811 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 812
 813 static void
 814 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 815                   struct drm_display_mode *adjusted_mode)
 816 {
 817         struct drm_device *dev = encoder->dev;
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 820         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 822
 823         /* Turn on the eDP PLL if needed */
 824         if (is_edp(intel_dp)) {
 825                 if (!is_pch_edp(intel_dp))
 826                         ironlake_edp_pll_on(encoder);
 827                 else
 828                         ironlake_edp_pll_off(encoder);
 829         }
 830
 831         /*
 832          * There are four kinds of DP registers:
 833          *
 834          *      IBX PCH
 835          *      SNB CPU
 836          *      IVB CPU
 837          *      CPT PCH
 838          *
 839          * IBX PCH and CPU are the same for almost everything,
 840          * except that the CPU DP PLL is configured in this
 841          * register
 842          *
 843          * CPT PCH is quite different, having many bits moved
 844          * to the TRANS_DP_CTL register instead. That
 845          * configuration happens (oddly) in ironlake_pch_enable
 846          */
 847
 848         /* Preserve the BIOS-computed detected bit. This is
 849          * supposed to be read-only.
 850          */
 851         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 852         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 853
 854         /* Handle DP bits in common between all three register formats */
 855
 856         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 857
 858         switch (intel_dp->lane_count) {
 859         case 1:
 860                 intel_dp->DP |= DP_PORT_WIDTH_1;
 861                 break;
 862         case 2:
 863                 intel_dp->DP |= DP_PORT_WIDTH_2;
 864                 break;
 865         case 4:
 866                 intel_dp->DP |= DP_PORT_WIDTH_4;
 867                 break;
 868         }
 869         if (intel_dp->has_audio) {
 870                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 871                                  pipe_name(intel_crtc->pipe));
 872                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 873                 intel_write_eld(encoder, adjusted_mode);
 874         }
 875         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 876         intel_dp->link_configuration[0] = intel_dp->link_bw;
 877         intel_dp->link_configuration[1] = intel_dp->lane_count;
 878         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 879         /*
 880          * Check for DPCD version > 1.1 and enhanced framing support
 881          */
 882         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 883             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 884                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 885         }
 886
 887         /* Split out the IBX/CPU vs CPT settings */
 888
 889         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 890                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 891                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 892                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 893                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 894                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 895
 896                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 897                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 898
 899                 intel_dp->DP |= intel_crtc->pipe << 29;
 900
 901                 /* don't miss out required setting for eDP */
 902                 intel_dp->DP |= DP_PLL_ENABLE;
 903                 if (adjusted_mode->clock < 200000)
 904                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 905                 else
 906                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 907         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 908                 intel_dp->DP |= intel_dp->color_range;
 909
 910                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 911                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 912                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 913                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 914                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 915
 916                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 917                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 918
 919                 if (intel_crtc->pipe == 1)
 920                         intel_dp->DP |= DP_PIPEB_SELECT;
 921
 922                 if (is_cpu_edp(intel_dp)) {
 923                         /* don't miss out required setting for eDP */
 924                         intel_dp->DP |= DP_PLL_ENABLE;
 925                         if (adjusted_mode->clock < 200000)
 926                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 927                         else
 928                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 929                 }
 930         } else {
 931                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 932         }
 933 }
 934
 935 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 936 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 937
 938 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 939 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 940
 941 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 942 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 943
 944 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 945                                        u32 mask,
 946                                        u32 value)
 947 {
 948         struct drm_device *dev = intel_dp->base.base.dev;
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950
 951         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 952                       mask, value,
 953                       I915_READ(PCH_PP_STATUS),
 954                       I915_READ(PCH_PP_CONTROL));
 955
 956         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 957                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 958                           I915_READ(PCH_PP_STATUS),
 959                           I915_READ(PCH_PP_CONTROL));
 960         }
 961 }
 962
 963 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 964 {
 965         DRM_DEBUG_KMS("Wait for panel power on\n");
 966         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 967 }
 968
 969 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 970 {
 971         DRM_DEBUG_KMS("Wait for panel power off time\n");
 972         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 973 }
 974
 975 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 976 {
 977         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 978         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 979 }
 980
 981
 982 /* Read the current pp_control value, unlocking the register if it
 983  * is locked
 984  */
 985
 986 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 987 {
 988         u32     control = I915_READ(PCH_PP_CONTROL);
 989
 990         control &= ~PANEL_UNLOCK_MASK;
 991         control |= PANEL_UNLOCK_REGS;
 992         return control;
 993 }
 994
 995 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 996 {
 997         struct drm_device *dev = intel_dp->base.base.dev;
 998         struct drm_i915_private *dev_priv = dev->dev_private;
 999         u32 pp;
1000
1001         if (!is_edp(intel_dp))
1002                 return;
1003         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1004
1005         WARN(intel_dp->want_panel_vdd,
1006              "eDP VDD already requested on\n");
1007
1008         intel_dp->want_panel_vdd = true;
1009
1010         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1011                 DRM_DEBUG_KMS("eDP VDD already on\n");
1012                 return;
1013         }
1014
1015         if (!ironlake_edp_have_panel_power(intel_dp))
1016                 ironlake_wait_panel_power_cycle(intel_dp);
1017
1018         pp = ironlake_get_pp_control(dev_priv);
1019         pp |= EDP_FORCE_VDD;
1020         I915_WRITE(PCH_PP_CONTROL, pp);
1021         POSTING_READ(PCH_PP_CONTROL);
1022         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1023                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1024
1025         /*
1026          * If the panel wasn't on, delay before accessing aux channel
1027          */
1028         if (!ironlake_edp_have_panel_power(intel_dp)) {
1029                 DRM_DEBUG_KMS("eDP was not running\n");
1030                 msleep(intel_dp->panel_power_up_delay);
1031         }
1032 }
1033
1034 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1035 {
1036         struct drm_device *dev = intel_dp->base.base.dev;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         u32 pp;
1039
1040         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1041                 pp = ironlake_get_pp_control(dev_priv);
1042                 pp &= ~EDP_FORCE_VDD;
1043                 I915_WRITE(PCH_PP_CONTROL, pp);
1044                 POSTING_READ(PCH_PP_CONTROL);
1045
1046                 /* Make sure sequencer is idle before allowing subsequent activity */
1047                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1048                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1049
1050                 msleep(intel_dp->panel_power_down_delay);
1051         }
1052 }
1053
1054 static void ironlake_panel_vdd_work(struct work_struct *__work)
1055 {
1056         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1057                                                  struct intel_dp, panel_vdd_work);
1058         struct drm_device *dev = intel_dp->base.base.dev;
1059
1060         mutex_lock(&dev->mode_config.mutex);
1061         ironlake_panel_vdd_off_sync(intel_dp);
1062         mutex_unlock(&dev->mode_config.mutex);
1063 }
1064
1065 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1066 {
1067         if (!is_edp(intel_dp))
1068                 return;
1069
1070         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1071         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1072
1073         intel_dp->want_panel_vdd = false;
1074
1075         if (sync) {
1076                 ironlake_panel_vdd_off_sync(intel_dp);
1077         } else {
1078                 /*
1079                  * Queue the timer to fire a long
1080                  * time from now (relative to the power down delay)
1081                  * to keep the panel power up across a sequence of operations
1082                  */
1083                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1084                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1085         }
1086 }
1087
1088 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1089 {
1090         struct drm_device *dev = intel_dp->base.base.dev;
1091         struct drm_i915_private *dev_priv = dev->dev_private;
1092         u32 pp;
1093
1094         if (!is_edp(intel_dp))
1095                 return;
1096
1097         DRM_DEBUG_KMS("Turn eDP power on\n");
1098
1099         if (ironlake_edp_have_panel_power(intel_dp)) {
1100                 DRM_DEBUG_KMS("eDP power already on\n");
1101                 return;
1102         }
1103
1104         ironlake_wait_panel_power_cycle(intel_dp);
1105
1106         pp = ironlake_get_pp_control(dev_priv);
1107         if (IS_GEN5(dev)) {
1108                 /* ILK workaround: disable reset around power sequence */
1109                 pp &= ~PANEL_POWER_RESET;
1110                 I915_WRITE(PCH_PP_CONTROL, pp);
1111                 POSTING_READ(PCH_PP_CONTROL);
1112         }
1113
1114         pp |= POWER_TARGET_ON;
1115         if (!IS_GEN5(dev))
1116                 pp |= PANEL_POWER_RESET;
1117
1118         I915_WRITE(PCH_PP_CONTROL, pp);
1119         POSTING_READ(PCH_PP_CONTROL);
1120
1121         ironlake_wait_panel_on(intel_dp);
1122
1123         if (IS_GEN5(dev)) {
1124                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1125                 I915_WRITE(PCH_PP_CONTROL, pp);
1126                 POSTING_READ(PCH_PP_CONTROL);
1127         }
1128 }
1129
1130 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1131 {
1132         struct drm_device *dev = intel_dp->base.base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         u32 pp;
1135
1136         if (!is_edp(intel_dp))
1137                 return;
1138
1139         DRM_DEBUG_KMS("Turn eDP power off\n");
1140
1141         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1142
1143         pp = ironlake_get_pp_control(dev_priv);
1144         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1145         I915_WRITE(PCH_PP_CONTROL, pp);
1146         POSTING_READ(PCH_PP_CONTROL);
1147
1148         ironlake_wait_panel_off(intel_dp);
1149 }
1150
1151 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1152 {
1153         struct drm_device *dev = intel_dp->base.base.dev;
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155         u32 pp;
1156
1157         if (!is_edp(intel_dp))
1158                 return;
1159
1160         DRM_DEBUG_KMS("\n");
1161         /*
1162          * If we enable the backlight right away following a panel power
1163          * on, we may see slight flicker as the panel syncs with the eDP
1164          * link.  So delay a bit to make sure the image is solid before
1165          * allowing it to appear.
1166          */
1167         msleep(intel_dp->backlight_on_delay);
1168         pp = ironlake_get_pp_control(dev_priv);
1169         pp |= EDP_BLC_ENABLE;
1170         I915_WRITE(PCH_PP_CONTROL, pp);
1171         POSTING_READ(PCH_PP_CONTROL);
1172 }
1173
1174 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1175 {
1176         struct drm_device *dev = intel_dp->base.base.dev;
1177         struct drm_i915_private *dev_priv = dev->dev_private;
1178         u32 pp;
1179
1180         if (!is_edp(intel_dp))
1181                 return;
1182
1183         DRM_DEBUG_KMS("\n");
1184         pp = ironlake_get_pp_control(dev_priv);
1185         pp &= ~EDP_BLC_ENABLE;
1186         I915_WRITE(PCH_PP_CONTROL, pp);
1187         POSTING_READ(PCH_PP_CONTROL);
1188         msleep(intel_dp->backlight_off_delay);
1189 }
1190
1191 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1192 {
1193         struct drm_device *dev = encoder->dev;
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         u32 dpa_ctl;
1196
1197         DRM_DEBUG_KMS("\n");
1198         dpa_ctl = I915_READ(DP_A);
1199         dpa_ctl |= DP_PLL_ENABLE;
1200         I915_WRITE(DP_A, dpa_ctl);
1201         POSTING_READ(DP_A);
1202         udelay(200);
1203 }
1204
1205 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1206 {
1207         struct drm_device *dev = encoder->dev;
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         u32 dpa_ctl;
1210
1211         dpa_ctl = I915_READ(DP_A);
1212         dpa_ctl &= ~DP_PLL_ENABLE;
1213         I915_WRITE(DP_A, dpa_ctl);
1214         POSTING_READ(DP_A);
1215         udelay(200);
1216 }
1217
1218 /* If the sink supports it, try to set the power state appropriately */
1219 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1220 {
1221         int ret, i;
1222
1223         /* Should have a valid DPCD by this point */
1224         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1225                 return;
1226
1227         if (mode != DRM_MODE_DPMS_ON) {
1228                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1229                                                   DP_SET_POWER_D3);
1230                 if (ret != 1)
1231                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1232         } else {
1233                 /*
1234                  * When turning on, we need to retry for 1ms to give the sink
1235                  * time to wake up.
1236                  */
1237                 for (i = 0; i < 3; i++) {
1238                         ret = intel_dp_aux_native_write_1(intel_dp,
1239                                                           DP_SET_POWER,
1240                                                           DP_SET_POWER_D0);
1241                         if (ret == 1)
1242                                 break;
1243                         msleep(1);
1244                 }
1245         }
1246 }
1247
1248 static void intel_dp_prepare(struct drm_encoder *encoder)
1249 {
1250         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1251
1252         ironlake_edp_backlight_off(intel_dp);
1253         ironlake_edp_panel_off(intel_dp);
1254
1255         /* Wake up the sink first */
1256         ironlake_edp_panel_vdd_on(intel_dp);
1257         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1258         intel_dp_link_down(intel_dp);
1259         ironlake_edp_panel_vdd_off(intel_dp, false);
1260
1261         /* Make sure the panel is off before trying to
1262          * change the mode
1263          */
1264 }
1265
1266 static void intel_dp_commit(struct drm_encoder *encoder)
1267 {
1268         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1269         struct drm_device *dev = encoder->dev;
1270         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1271
1272         ironlake_edp_panel_vdd_on(intel_dp);
1273         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1274         intel_dp_start_link_train(intel_dp);
1275         ironlake_edp_panel_on(intel_dp);
1276         ironlake_edp_panel_vdd_off(intel_dp, true);
1277         intel_dp_complete_link_train(intel_dp);
1278         ironlake_edp_backlight_on(intel_dp);
1279
1280         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1281
1282         if (HAS_PCH_CPT(dev))
1283                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1284 }
1285
1286 static void
1287 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1288 {
1289         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1290         struct drm_device *dev = encoder->dev;
1291         struct drm_i915_private *dev_priv = dev->dev_private;
1292         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1293
1294         if (mode != DRM_MODE_DPMS_ON) {
1295                 ironlake_edp_backlight_off(intel_dp);
1296                 ironlake_edp_panel_off(intel_dp);
1297
1298                 ironlake_edp_panel_vdd_on(intel_dp);
1299                 intel_dp_sink_dpms(intel_dp, mode);
1300                 intel_dp_link_down(intel_dp);
1301                 ironlake_edp_panel_vdd_off(intel_dp, false);
1302
1303                 if (is_cpu_edp(intel_dp))
1304                         ironlake_edp_pll_off(encoder);
1305         } else {
1306                 if (is_cpu_edp(intel_dp))
1307                         ironlake_edp_pll_on(encoder);
1308
1309                 ironlake_edp_panel_vdd_on(intel_dp);
1310                 intel_dp_sink_dpms(intel_dp, mode);
1311                 if (!(dp_reg & DP_PORT_EN)) {
1312                         intel_dp_start_link_train(intel_dp);
1313                         ironlake_edp_panel_on(intel_dp);
1314                         ironlake_edp_panel_vdd_off(intel_dp, true);
1315                         intel_dp_complete_link_train(intel_dp);
1316                 } else
1317                         ironlake_edp_panel_vdd_off(intel_dp, false);
1318                 ironlake_edp_backlight_on(intel_dp);
1319         }
1320         intel_dp->dpms_mode = mode;
1321 }
1322
1323 /*
1324  * Native read with retry for link status and receiver capability reads for
1325  * cases where the sink may still be asleep.
1326  */
1327 static bool
1328 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1329                                uint8_t *recv, int recv_bytes)
1330 {
1331         int ret, i;
1332
1333         /*
1334          * Sinks are *supposed* to come up within 1ms from an off state,
1335          * but we're also supposed to retry 3 times per the spec.
1336          */
1337         for (i = 0; i < 3; i++) {
1338                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1339                                                recv_bytes);
1340                 if (ret == recv_bytes)
1341                         return true;
1342                 msleep(1);
1343         }
1344
1345         return false;
1346 }
1347
1348 /*
1349  * Fetch AUX CH registers 0x202 - 0x207 which contain
1350  * link status information
1351  */
1352 static bool
1353 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1354 {
1355         return intel_dp_aux_native_read_retry(intel_dp,
1356                                               DP_LANE0_1_STATUS,
1357                                               link_status,
1358                                               DP_LINK_STATUS_SIZE);
1359 }
1360
1361 static uint8_t
1362 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1363                      int r)
1364 {
1365         return link_status[r - DP_LANE0_1_STATUS];
1366 }
1367
1368 static uint8_t
1369 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1370                                  int lane)
1371 {
1372         int         s = ((lane & 1) ?
1373                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1374                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1375         uint8_t l = adjust_request[lane>>1];
1376
1377         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1378 }
1379
1380 static uint8_t
1381 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1382                                       int lane)
1383 {
1384         int         s = ((lane & 1) ?
1385                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1386                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1387         uint8_t l = adjust_request[lane>>1];
1388
1389         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1390 }
1391
1392
1393 #if 0
1394 static char     *voltage_names[] = {
1395         "0.4V", "0.6V", "0.8V", "1.2V"
1396 };
1397 static char     *pre_emph_names[] = {
1398         "0dB", "3.5dB", "6dB", "9.5dB"
1399 };
1400 static char     *link_train_names[] = {
1401         "pattern 1", "pattern 2", "idle", "off"
1402 };
1403 #endif
1404
1405 /*
1406  * These are source-specific values; current Intel hardware supports
1407  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1408  */
1409
1410 static uint8_t
1411 intel_dp_voltage_max(struct intel_dp *intel_dp)
1412 {
1413         struct drm_device *dev = intel_dp->base.base.dev;
1414
1415         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1416                 return DP_TRAIN_VOLTAGE_SWING_800;
1417         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1418                 return DP_TRAIN_VOLTAGE_SWING_1200;
1419         else
1420                 return DP_TRAIN_VOLTAGE_SWING_800;
1421 }
1422
1423 static uint8_t
1424 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1425 {
1426         struct drm_device *dev = intel_dp->base.base.dev;
1427
1428         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1429                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1430                 case DP_TRAIN_VOLTAGE_SWING_400:
1431                         return DP_TRAIN_PRE_EMPHASIS_6;
1432                 case DP_TRAIN_VOLTAGE_SWING_600:
1433                 case DP_TRAIN_VOLTAGE_SWING_800:
1434                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1435                 default:
1436                         return DP_TRAIN_PRE_EMPHASIS_0;
1437                 }
1438         } else {
1439                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1440                 case DP_TRAIN_VOLTAGE_SWING_400:
1441                         return DP_TRAIN_PRE_EMPHASIS_6;
1442                 case DP_TRAIN_VOLTAGE_SWING_600:
1443                         return DP_TRAIN_PRE_EMPHASIS_6;
1444                 case DP_TRAIN_VOLTAGE_SWING_800:
1445                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1446                 case DP_TRAIN_VOLTAGE_SWING_1200:
1447                 default:
1448                         return DP_TRAIN_PRE_EMPHASIS_0;
1449                 }
1450         }
1451 }
1452
1453 static void
1454 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1455 {
1456         uint8_t v = 0;
1457         uint8_t p = 0;
1458         int lane;
1459         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1460         uint8_t voltage_max;
1461         uint8_t preemph_max;
1462
1463         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1464                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1465                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1466
1467                 if (this_v > v)
1468                         v = this_v;
1469                 if (this_p > p)
1470                         p = this_p;
1471         }
1472
1473         voltage_max = intel_dp_voltage_max(intel_dp);
1474         if (v >= voltage_max)
1475                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1476
1477         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1478         if (p >= preemph_max)
1479                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1480
1481         for (lane = 0; lane < 4; lane++)
1482                 intel_dp->train_set[lane] = v | p;
1483 }
1484
1485 static uint32_t
1486 intel_dp_signal_levels(uint8_t train_set)
1487 {
1488         uint32_t        signal_levels = 0;
1489
1490         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491         case DP_TRAIN_VOLTAGE_SWING_400:
1492         default:
1493                 signal_levels |= DP_VOLTAGE_0_4;
1494                 break;
1495         case DP_TRAIN_VOLTAGE_SWING_600:
1496                 signal_levels |= DP_VOLTAGE_0_6;
1497                 break;
1498         case DP_TRAIN_VOLTAGE_SWING_800:
1499                 signal_levels |= DP_VOLTAGE_0_8;
1500                 break;
1501         case DP_TRAIN_VOLTAGE_SWING_1200:
1502                 signal_levels |= DP_VOLTAGE_1_2;
1503                 break;
1504         }
1505         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1506         case DP_TRAIN_PRE_EMPHASIS_0:
1507         default:
1508                 signal_levels |= DP_PRE_EMPHASIS_0;
1509                 break;
1510         case DP_TRAIN_PRE_EMPHASIS_3_5:
1511                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1512                 break;
1513         case DP_TRAIN_PRE_EMPHASIS_6:
1514                 signal_levels |= DP_PRE_EMPHASIS_6;
1515                 break;
1516         case DP_TRAIN_PRE_EMPHASIS_9_5:
1517                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1518                 break;
1519         }
1520         return signal_levels;
1521 }
1522
1523 /* Gen6's DP voltage swing and pre-emphasis control */
1524 static uint32_t
1525 intel_gen6_edp_signal_levels(uint8_t train_set)
1526 {
1527         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1528                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1529         switch (signal_levels) {
1530         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1531         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1532                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1533         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1534                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1535         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1536         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1537                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1538         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1539         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1540                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1541         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1542         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1543                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1544         default:
1545                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1546                               "0x%x\n", signal_levels);
1547                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1548         }
1549 }
1550
1551 /* Gen7's DP voltage swing and pre-emphasis control */
1552 static uint32_t
1553 intel_gen7_edp_signal_levels(uint8_t train_set)
1554 {
1555         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1556                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1557         switch (signal_levels) {
1558         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1559                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1560         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1561                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1562         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1563                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1564
1565         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1566                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1567         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1568                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1569
1570         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1571                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1572         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1573                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1574
1575         default:
1576                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1577                               "0x%x\n", signal_levels);
1578                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1579         }
1580 }
1581
1582 static uint8_t
1583 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1584                       int lane)
1585 {
1586         int s = (lane & 1) * 4;
1587         uint8_t l = link_status[lane>>1];
1588
1589         return (l >> s) & 0xf;
1590 }
1591
1592 /* Check for clock recovery is done on all channels */
1593 static bool
1594 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1595 {
1596         int lane;
1597         uint8_t lane_status;
1598
1599         for (lane = 0; lane < lane_count; lane++) {
1600                 lane_status = intel_get_lane_status(link_status, lane);
1601                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1602                         return false;
1603         }
1604         return true;
1605 }
1606
1607 /* Check to see if channel eq is done on all channels */
1608 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1609                          DP_LANE_CHANNEL_EQ_DONE|\
1610                          DP_LANE_SYMBOL_LOCKED)
1611 static bool
1612 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1613 {
1614         uint8_t lane_align;
1615         uint8_t lane_status;
1616         int lane;
1617
1618         lane_align = intel_dp_link_status(link_status,
1619                                           DP_LANE_ALIGN_STATUS_UPDATED);
1620         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1621                 return false;
1622         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1623                 lane_status = intel_get_lane_status(link_status, lane);
1624                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1625                         return false;
1626         }
1627         return true;
1628 }
1629
1630 static bool
1631 intel_dp_set_link_train(struct intel_dp *intel_dp,
1632                         uint32_t dp_reg_value,
1633                         uint8_t dp_train_pat)
1634 {
1635         struct drm_device *dev = intel_dp->base.base.dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         int ret;
1638
1639         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1640         POSTING_READ(intel_dp->output_reg);
1641
1642         intel_dp_aux_native_write_1(intel_dp,
1643                                     DP_TRAINING_PATTERN_SET,
1644                                     dp_train_pat);
1645
1646         ret = intel_dp_aux_native_write(intel_dp,
1647                                         DP_TRAINING_LANE0_SET,
1648                                         intel_dp->train_set,
1649                                         intel_dp->lane_count);
1650         if (ret != intel_dp->lane_count)
1651                 return false;
1652
1653         return true;
1654 }
1655
1656 /* Enable corresponding port and start training pattern 1 */
1657 static void
1658 intel_dp_start_link_train(struct intel_dp *intel_dp)
1659 {
1660         struct drm_device *dev = intel_dp->base.base.dev;
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1663         int i;
1664         uint8_t voltage;
1665         bool clock_recovery = false;
1666         int voltage_tries, loop_tries;
1667         u32 reg;
1668         uint32_t DP = intel_dp->DP;
1669
1670         /*
1671          * On CPT we have to enable the port in training pattern 1, which
1672          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1673          * the port and wait for it to become active.
1674          */
1675         if (!HAS_PCH_CPT(dev)) {
1676                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1677                 POSTING_READ(intel_dp->output_reg);
1678                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1679         }
1680
1681         /* Write the link configuration data */
1682         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1683                                   intel_dp->link_configuration,
1684                                   DP_LINK_CONFIGURATION_SIZE);
1685
1686         DP |= DP_PORT_EN;
1687
1688         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1689                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1690         else
1691                 DP &= ~DP_LINK_TRAIN_MASK;
1692         memset(intel_dp->train_set, 0, 4);
1693         voltage = 0xff;
1694         voltage_tries = 0;
1695         loop_tries = 0;
1696         clock_recovery = false;
1697         for (;;) {
1698                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1699                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1700                 uint32_t    signal_levels;
1701
1702
1703                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1704                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1705                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1706                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1707                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1708                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1709                 } else {
1710                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1711                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1712                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1713                 }
1714
1715                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1716                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1717                 else
1718                         reg = DP | DP_LINK_TRAIN_PAT_1;
1719
1720                 if (!intel_dp_set_link_train(intel_dp, reg,
1721                                              DP_TRAINING_PATTERN_1 |
1722                                              DP_LINK_SCRAMBLING_DISABLE))
1723                         break;
1724                 /* Set training pattern 1 */
1725
1726                 udelay(100);
1727                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1728                         DRM_ERROR("failed to get link status\n");
1729                         break;
1730                 }
1731
1732                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1733                         DRM_DEBUG_KMS("clock recovery OK\n");
1734                         clock_recovery = true;
1735                         break;
1736                 }
1737
1738                 /* Check to see if we've tried the max voltage */
1739                 for (i = 0; i < intel_dp->lane_count; i++)
1740                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1741                                 break;
1742                 if (i == intel_dp->lane_count) {
1743                         ++loop_tries;
1744                         if (loop_tries == 5) {
1745                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1746                                 break;
1747                         }
1748                         memset(intel_dp->train_set, 0, 4);
1749                         voltage_tries = 0;
1750                         continue;
1751                 }
1752
1753                 /* Check to see if we've tried the same voltage 5 times */
1754                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1755                         ++voltage_tries;
1756                         if (voltage_tries == 5) {
1757                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1758                                 break;
1759                         }
1760                 } else
1761                         voltage_tries = 0;
1762                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1763
1764                 /* Compute new intel_dp->train_set as requested by target */
1765                 intel_get_adjust_train(intel_dp, link_status);
1766         }
1767
1768         intel_dp->DP = DP;
1769 }
1770
1771 static void
1772 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1773 {
1774         struct drm_device *dev = intel_dp->base.base.dev;
1775         struct drm_i915_private *dev_priv = dev->dev_private;
1776         bool channel_eq = false;
1777         int tries, cr_tries;
1778         u32 reg;
1779         uint32_t DP = intel_dp->DP;
1780
1781         /* channel equalization */
1782         tries = 0;
1783         cr_tries = 0;
1784         channel_eq = false;
1785         for (;;) {
1786                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1787                 uint32_t    signal_levels;
1788                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1789
1790                 if (cr_tries > 5) {
1791                         DRM_ERROR("failed to train DP, aborting\n");
1792                         intel_dp_link_down(intel_dp);
1793                         break;
1794                 }
1795
1796                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1797                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1798                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1799                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1800                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1801                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1802                 } else {
1803                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1804                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1805                 }
1806
1807                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1808                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1809                 else
1810                         reg = DP | DP_LINK_TRAIN_PAT_2;
1811
1812                 /* channel eq pattern */
1813                 if (!intel_dp_set_link_train(intel_dp, reg,
1814                                              DP_TRAINING_PATTERN_2 |
1815                                              DP_LINK_SCRAMBLING_DISABLE))
1816                         break;
1817
1818                 udelay(400);
1819                 if (!intel_dp_get_link_status(intel_dp, link_status))
1820                         break;
1821
1822                 /* Make sure clock is still ok */
1823                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1824                         intel_dp_start_link_train(intel_dp);
1825                         cr_tries++;
1826                         continue;
1827                 }
1828
1829                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1830                         channel_eq = true;
1831                         break;
1832                 }
1833
1834                 /* Try 5 times, then try clock recovery if that fails */
1835                 if (tries > 5) {
1836                         intel_dp_link_down(intel_dp);
1837                         intel_dp_start_link_train(intel_dp);
1838                         tries = 0;
1839                         cr_tries++;
1840                         continue;
1841                 }
1842
1843                 /* Compute new intel_dp->train_set as requested by target */
1844                 intel_get_adjust_train(intel_dp, link_status);
1845                 ++tries;
1846         }
1847
1848         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1849                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1850         else
1851                 reg = DP | DP_LINK_TRAIN_OFF;
1852
1853         I915_WRITE(intel_dp->output_reg, reg);
1854         POSTING_READ(intel_dp->output_reg);
1855         intel_dp_aux_native_write_1(intel_dp,
1856                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1857 }
1858
1859 static void
1860 intel_dp_link_down(struct intel_dp *intel_dp)
1861 {
1862         struct drm_device *dev = intel_dp->base.base.dev;
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         uint32_t DP = intel_dp->DP;
1865
1866         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1867                 return;
1868
1869         DRM_DEBUG_KMS("\n");
1870
1871         if (is_edp(intel_dp)) {
1872                 DP &= ~DP_PLL_ENABLE;
1873                 I915_WRITE(intel_dp->output_reg, DP);
1874                 POSTING_READ(intel_dp->output_reg);
1875                 udelay(100);
1876         }
1877
1878         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1879                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1880                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1881         } else {
1882                 DP &= ~DP_LINK_TRAIN_MASK;
1883                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1884         }
1885         POSTING_READ(intel_dp->output_reg);
1886
1887         msleep(17);
1888
1889         if (is_edp(intel_dp)) {
1890                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1891                         DP |= DP_LINK_TRAIN_OFF_CPT;
1892                 else
1893                         DP |= DP_LINK_TRAIN_OFF;
1894         }
1895
1896         if (!HAS_PCH_CPT(dev) &&
1897             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1898                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1899
1900                 /* Hardware workaround: leaving our transcoder select
1901                  * set to transcoder B while it's off will prevent the
1902                  * corresponding HDMI output on transcoder A.
1903                  *
1904                  * Combine this with another hardware workaround:
1905                  * transcoder select bit can only be cleared while the
1906                  * port is enabled.
1907                  */
1908                 DP &= ~DP_PIPEB_SELECT;
1909                 I915_WRITE(intel_dp->output_reg, DP);
1910
1911                 /* Changes to enable or select take place the vblank
1912                  * after being written.
1913                  */
1914                 if (crtc == NULL) {
1915                         /* We can arrive here never having been attached
1916                          * to a CRTC, for instance, due to inheriting
1917                          * random state from the BIOS.
1918                          *
1919                          * If the pipe is not running, play safe and
1920                          * wait for the clocks to stabilise before
1921                          * continuing.
1922                          */
1923                         POSTING_READ(intel_dp->output_reg);
1924                         msleep(50);
1925                 } else
1926                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1927         }
1928
1929         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1930         POSTING_READ(intel_dp->output_reg);
1931         msleep(intel_dp->panel_power_down_delay);
1932 }
1933
1934 static bool
1935 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1936 {
1937         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1938                                            sizeof(intel_dp->dpcd)) &&
1939             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1940                 return true;
1941         }
1942
1943         return false;
1944 }
1945
1946 static bool
1947 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1948 {
1949         int ret;
1950
1951         ret = intel_dp_aux_native_read_retry(intel_dp,
1952                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1953                                              sink_irq_vector, 1);
1954         if (!ret)
1955                 return false;
1956
1957         return true;
1958 }
1959
1960 static void
1961 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1962 {
1963         /* NAK by default */
1964         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1965 }
1966
1967 /*
1968  * According to DP spec
1969  * 5.1.2:
1970  *  1. Read DPCD
1971  *  2. Configure link according to Receiver Capabilities
1972  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1973  *  4. Check link status on receipt of hot-plug interrupt
1974  */
1975
1976 static void
1977 intel_dp_check_link_status(struct intel_dp *intel_dp)
1978 {
1979         u8 sink_irq_vector;
1980         u8 link_status[DP_LINK_STATUS_SIZE];
1981
1982         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1983                 return;
1984
1985         if (!intel_dp->base.base.crtc)
1986                 return;
1987
1988         /* Try to read receiver status if the link appears to be up */
1989         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1990                 intel_dp_link_down(intel_dp);
1991                 return;
1992         }
1993
1994         /* Now read the DPCD to see if it's actually running */
1995         if (!intel_dp_get_dpcd(intel_dp)) {
1996                 intel_dp_link_down(intel_dp);
1997                 return;
1998         }
1999
2000         /* Try to read the source of the interrupt */
2001         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2002             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2003                 /* Clear interrupt source */
2004                 intel_dp_aux_native_write_1(intel_dp,
2005                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2006                                             sink_irq_vector);
2007
2008                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2009                         intel_dp_handle_test_request(intel_dp);
2010                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2011                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2012         }
2013
2014         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2015                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2016                               drm_get_encoder_name(&intel_dp->base.base));
2017                 intel_dp_start_link_train(intel_dp);
2018                 intel_dp_complete_link_train(intel_dp);
2019         }
2020 }
2021
2022 static enum drm_connector_status
2023 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2024 {
2025         if (intel_dp_get_dpcd(intel_dp))
2026                 return connector_status_connected;
2027         return connector_status_disconnected;
2028 }
2029
2030 static enum drm_connector_status
2031 ironlake_dp_detect(struct intel_dp *intel_dp)
2032 {
2033         enum drm_connector_status status;
2034
2035         /* Can't disconnect eDP, but you can close the lid... */
2036         if (is_edp(intel_dp)) {
2037                 status = intel_panel_detect(intel_dp->base.base.dev);
2038                 if (status == connector_status_unknown)
2039                         status = connector_status_connected;
2040                 return status;
2041         }
2042
2043         return intel_dp_detect_dpcd(intel_dp);
2044 }
2045
2046 static enum drm_connector_status
2047 g4x_dp_detect(struct intel_dp *intel_dp)
2048 {
2049         struct drm_device *dev = intel_dp->base.base.dev;
2050         struct drm_i915_private *dev_priv = dev->dev_private;
2051         uint32_t temp, bit;
2052
2053         switch (intel_dp->output_reg) {
2054         case DP_B:
2055                 bit = DPB_HOTPLUG_INT_STATUS;
2056                 break;
2057         case DP_C:
2058                 bit = DPC_HOTPLUG_INT_STATUS;
2059                 break;
2060         case DP_D:
2061                 bit = DPD_HOTPLUG_INT_STATUS;
2062                 break;
2063         default:
2064                 return connector_status_unknown;
2065         }
2066
2067         temp = I915_READ(PORT_HOTPLUG_STAT);
2068
2069         if ((temp & bit) == 0)
2070                 return connector_status_disconnected;
2071
2072         return intel_dp_detect_dpcd(intel_dp);
2073 }
2074
2075 static struct edid *
2076 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2077 {
2078         struct intel_dp *intel_dp = intel_attached_dp(connector);
2079         struct edid     *edid;
2080
2081         ironlake_edp_panel_vdd_on(intel_dp);
2082         edid = drm_get_edid(connector, adapter);
2083         ironlake_edp_panel_vdd_off(intel_dp, false);
2084         return edid;
2085 }
2086
2087 static int
2088 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2089 {
2090         struct intel_dp *intel_dp = intel_attached_dp(connector);
2091         int     ret;
2092
2093         ironlake_edp_panel_vdd_on(intel_dp);
2094         ret = intel_ddc_get_modes(connector, adapter);
2095         ironlake_edp_panel_vdd_off(intel_dp, false);
2096         return ret;
2097 }
2098
2099
2100 /**
2101  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2102  *
2103  * \return true if DP port is connected.
2104  * \return false if DP port is disconnected.
2105  */
2106 static enum drm_connector_status
2107 intel_dp_detect(struct drm_connector *connector, bool force)
2108 {
2109         struct intel_dp *intel_dp = intel_attached_dp(connector);
2110         struct drm_device *dev = intel_dp->base.base.dev;
2111         enum drm_connector_status status;
2112         struct edid *edid = NULL;
2113
2114         intel_dp->has_audio = false;
2115
2116         if (HAS_PCH_SPLIT(dev))
2117                 status = ironlake_dp_detect(intel_dp);
2118         else
2119                 status = g4x_dp_detect(intel_dp);
2120
2121         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2122                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2123                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2124                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2125
2126         if (status != connector_status_connected)
2127                 return status;
2128
2129         if (intel_dp->force_audio) {
2130                 intel_dp->has_audio = intel_dp->force_audio > 0;
2131         } else {
2132                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2133                 if (edid) {
2134                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2135                         connector->display_info.raw_edid = NULL;
2136                         kfree(edid);
2137                 }
2138         }
2139
2140         return connector_status_connected;
2141 }
2142
2143 static int intel_dp_get_modes(struct drm_connector *connector)
2144 {
2145         struct intel_dp *intel_dp = intel_attached_dp(connector);
2146         struct drm_device *dev = intel_dp->base.base.dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         int ret;
2149
2150         /* We should parse the EDID data and find out if it has an audio sink
2151          */
2152
2153         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2154         if (ret) {
2155                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2156                         struct drm_display_mode *newmode;
2157                         list_for_each_entry(newmode, &connector->probed_modes,
2158                                             head) {
2159                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2160                                         intel_dp->panel_fixed_mode =
2161                                                 drm_mode_duplicate(dev, newmode);
2162                                         break;
2163                                 }
2164                         }
2165                 }
2166                 return ret;
2167         }
2168
2169         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2170         if (is_edp(intel_dp)) {
2171                 /* initialize panel mode from VBT if available for eDP */
2172                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2173                         intel_dp->panel_fixed_mode =
2174                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2175                         if (intel_dp->panel_fixed_mode) {
2176                                 intel_dp->panel_fixed_mode->type |=
2177                                         DRM_MODE_TYPE_PREFERRED;
2178                         }
2179                 }
2180                 if (intel_dp->panel_fixed_mode) {
2181                         struct drm_display_mode *mode;
2182                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2183                         drm_mode_probed_add(connector, mode);
2184                         return 1;
2185                 }
2186         }
2187         return 0;
2188 }
2189
2190 static bool
2191 intel_dp_detect_audio(struct drm_connector *connector)
2192 {
2193         struct intel_dp *intel_dp = intel_attached_dp(connector);
2194         struct edid *edid;
2195         bool has_audio = false;
2196
2197         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2198         if (edid) {
2199                 has_audio = drm_detect_monitor_audio(edid);
2200
2201                 connector->display_info.raw_edid = NULL;
2202                 kfree(edid);
2203         }
2204
2205         return has_audio;
2206 }
2207
2208 static int
2209 intel_dp_set_property(struct drm_connector *connector,
2210                       struct drm_property *property,
2211                       uint64_t val)
2212 {
2213         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2214         struct intel_dp *intel_dp = intel_attached_dp(connector);
2215         int ret;
2216
2217         ret = drm_connector_property_set_value(connector, property, val);
2218         if (ret)
2219                 return ret;
2220
2221         if (property == dev_priv->force_audio_property) {
2222                 int i = val;
2223                 bool has_audio;
2224
2225                 if (i == intel_dp->force_audio)
2226                         return 0;
2227
2228                 intel_dp->force_audio = i;
2229
2230                 if (i == 0)
2231                         has_audio = intel_dp_detect_audio(connector);
2232                 else
2233                         has_audio = i > 0;
2234
2235                 if (has_audio == intel_dp->has_audio)
2236                         return 0;
2237
2238                 intel_dp->has_audio = has_audio;
2239                 goto done;
2240         }
2241
2242         if (property == dev_priv->broadcast_rgb_property) {
2243                 if (val == !!intel_dp->color_range)
2244                         return 0;
2245
2246                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2247                 goto done;
2248         }
2249
2250         return -EINVAL;
2251
2252 done:
2253         if (intel_dp->base.base.crtc) {
2254                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2255                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2256                                          crtc->x, crtc->y,
2257                                          crtc->fb);
2258         }
2259
2260         return 0;
2261 }
2262
2263 static void
2264 intel_dp_destroy(struct drm_connector *connector)
2265 {
2266         struct drm_device *dev = connector->dev;
2267
2268         if (intel_dpd_is_edp(dev))
2269                 intel_panel_destroy_backlight(dev);
2270
2271         drm_sysfs_connector_remove(connector);
2272         drm_connector_cleanup(connector);
2273         kfree(connector);
2274 }
2275
2276 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2277 {
2278         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2279
2280         i2c_del_adapter(&intel_dp->adapter);
2281         drm_encoder_cleanup(encoder);
2282         if (is_edp(intel_dp)) {
2283                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2284                 ironlake_panel_vdd_off_sync(intel_dp);
2285         }
2286         kfree(intel_dp);
2287 }
2288
2289 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2290         .dpms = intel_dp_dpms,
2291         .mode_fixup = intel_dp_mode_fixup,
2292         .prepare = intel_dp_prepare,
2293         .mode_set = intel_dp_mode_set,
2294         .commit = intel_dp_commit,
2295 };
2296
2297 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2298         .dpms = drm_helper_connector_dpms,
2299         .detect = intel_dp_detect,
2300         .fill_modes = drm_helper_probe_single_connector_modes,
2301         .set_property = intel_dp_set_property,
2302         .destroy = intel_dp_destroy,
2303 };
2304
2305 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2306         .get_modes = intel_dp_get_modes,
2307         .mode_valid = intel_dp_mode_valid,
2308         .best_encoder = intel_best_encoder,
2309 };
2310
2311 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2312         .destroy = intel_dp_encoder_destroy,
2313 };
2314
2315 static void
2316 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2317 {
2318         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2319
2320         intel_dp_check_link_status(intel_dp);
2321 }
2322
2323 /* Return which DP Port should be selected for Transcoder DP control */
2324 int
2325 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2326 {
2327         struct drm_device *dev = crtc->dev;
2328         struct drm_mode_config *mode_config = &dev->mode_config;
2329         struct drm_encoder *encoder;
2330
2331         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2332                 struct intel_dp *intel_dp;
2333
2334                 if (encoder->crtc != crtc)
2335                         continue;
2336
2337                 intel_dp = enc_to_intel_dp(encoder);
2338                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2339                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2340                         return intel_dp->output_reg;
2341         }
2342
2343         return -1;
2344 }
2345
2346 /* check the VBT to see whether the eDP is on DP-D port */
2347 bool intel_dpd_is_edp(struct drm_device *dev)
2348 {
2349         struct drm_i915_private *dev_priv = dev->dev_private;
2350         struct child_device_config *p_child;
2351         int i;
2352
2353         if (!dev_priv->child_dev_num)
2354                 return false;
2355
2356         for (i = 0; i < dev_priv->child_dev_num; i++) {
2357                 p_child = dev_priv->child_dev + i;
2358
2359                 if (p_child->dvo_port == PORT_IDPD &&
2360                     p_child->device_type == DEVICE_TYPE_eDP)
2361                         return true;
2362         }
2363         return false;
2364 }
2365
2366 static void
2367 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2368 {
2369         intel_attach_force_audio_property(connector);
2370         intel_attach_broadcast_rgb_property(connector);
2371 }
2372
2373 void
2374 intel_dp_init(struct drm_device *dev, int output_reg)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         struct drm_connector *connector;
2378         struct intel_dp *intel_dp;
2379         struct intel_encoder *intel_encoder;
2380         struct intel_connector *intel_connector;
2381         const char *name = NULL;
2382         int type;
2383
2384         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2385         if (!intel_dp)
2386                 return;
2387
2388         intel_dp->output_reg = output_reg;
2389         intel_dp->dpms_mode = -1;
2390
2391         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2392         if (!intel_connector) {
2393                 kfree(intel_dp);
2394                 return;
2395         }
2396         intel_encoder = &intel_dp->base;
2397
2398         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2399                 if (intel_dpd_is_edp(dev))
2400                         intel_dp->is_pch_edp = true;
2401
2402         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2403                 type = DRM_MODE_CONNECTOR_eDP;
2404                 intel_encoder->type = INTEL_OUTPUT_EDP;
2405         } else {
2406                 type = DRM_MODE_CONNECTOR_DisplayPort;
2407                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2408         }
2409
2410         connector = &intel_connector->base;
2411         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2412         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2413
2414         connector->polled = DRM_CONNECTOR_POLL_HPD;
2415
2416         if (output_reg == DP_B || output_reg == PCH_DP_B)
2417                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2418         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2419                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2420         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2421                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2422
2423         if (is_edp(intel_dp)) {
2424                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2425                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2426                                   ironlake_panel_vdd_work);
2427         }
2428
2429         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2430         connector->interlace_allowed = true;
2431         connector->doublescan_allowed = 0;
2432
2433         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2434                          DRM_MODE_ENCODER_TMDS);
2435         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2436
2437         intel_connector_attach_encoder(intel_connector, intel_encoder);
2438         drm_sysfs_connector_add(connector);
2439
2440         /* Set up the DDC bus. */
2441         switch (output_reg) {
2442                 case DP_A:
2443                         name = "DPDDC-A";
2444                         break;
2445                 case DP_B:
2446                 case PCH_DP_B:
2447                         dev_priv->hotplug_supported_mask |=
2448                                 HDMIB_HOTPLUG_INT_STATUS;
2449                         name = "DPDDC-B";
2450                         break;
2451                 case DP_C:
2452                 case PCH_DP_C:
2453                         dev_priv->hotplug_supported_mask |=
2454                                 HDMIC_HOTPLUG_INT_STATUS;
2455                         name = "DPDDC-C";
2456                         break;
2457                 case DP_D:
2458                 case PCH_DP_D:
2459                         dev_priv->hotplug_supported_mask |=
2460                                 HDMID_HOTPLUG_INT_STATUS;
2461                         name = "DPDDC-D";
2462                         break;
2463         }
2464
2465         /* Cache some DPCD data in the eDP case */
2466         if (is_edp(intel_dp)) {
2467                 bool ret;
2468                 struct edp_power_seq    cur, vbt;
2469                 u32 pp_on, pp_off, pp_div;
2470
2471                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2472                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2473                 pp_div = I915_READ(PCH_PP_DIVISOR);
2474
2475                 /* Pull timing values out of registers */
2476                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2477                         PANEL_POWER_UP_DELAY_SHIFT;
2478
2479                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2480                         PANEL_LIGHT_ON_DELAY_SHIFT;
2481
2482                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2483                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2484
2485                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2486                         PANEL_POWER_DOWN_DELAY_SHIFT;
2487
2488                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2489                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2490
2491                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2492                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2493
2494                 vbt = dev_priv->edp.pps;
2495
2496                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2497                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2498
2499 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2500
2501                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2502                 intel_dp->backlight_on_delay = get_delay(t8);
2503                 intel_dp->backlight_off_delay = get_delay(t9);
2504                 intel_dp->panel_power_down_delay = get_delay(t10);
2505                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2506
2507                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2508                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2509                               intel_dp->panel_power_cycle_delay);
2510
2511                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2512                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2513
2514                 ironlake_edp_panel_vdd_on(intel_dp);
2515                 ret = intel_dp_get_dpcd(intel_dp);
2516                 ironlake_edp_panel_vdd_off(intel_dp, false);
2517
2518                 if (ret) {
2519                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2520                                 dev_priv->no_aux_handshake =
2521                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2522                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2523                 } else {
2524                         /* if this fails, presume the device is a ghost */
2525                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2526                         intel_dp_encoder_destroy(&intel_dp->base.base);
2527                         intel_dp_destroy(&intel_connector->base);
2528                         return;
2529                 }
2530         }
2531
2532         intel_dp_i2c_init(intel_dp, intel_connector, name);
2533
2534         intel_encoder->hot_plug = intel_dp_hot_plug;
2535
2536         if (is_edp(intel_dp)) {
2537                 dev_priv->int_edp_connector = connector;
2538                 intel_panel_setup_backlight(dev);
2539         }
2540
2541         intel_dp_add_properties(intel_dp, connector);
2542
2543         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2544          * 0xd.  Failure to do so will result in spurious interrupts being
2545          * generated on the port when a cable is not attached.
2546          */
2547         if (IS_G4X(dev) && !IS_GM45(dev)) {
2548                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2549                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2550         }
2551 }