drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  46
  47 struct intel_dp_priv {
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int dpms_mode;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[4];
  56         struct intel_encoder *intel_encoder;
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59 };
  60
  61 static void
  62 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  63                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  64
  65 static void
  66 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  67
  68 void
  69 intel_edp_link_config (struct intel_encoder *intel_encoder,
  70                 int *lane_num, int *link_bw)
  71 {
  72         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  73
  74         *lane_num = dp_priv->lane_count;
  75         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  76                 *link_bw = 162000;
  77         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  78                 *link_bw = 270000;
  79 }
  80
  81 static int
  82 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  83 {
  84         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  85         int max_lane_count = 4;
  86
  87         if (dp_priv->dpcd[0] >= 0x11) {
  88                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  89                 switch (max_lane_count) {
  90                 case 1: case 2: case 4:
  91                         break;
  92                 default:
  93                         max_lane_count = 4;
  94                 }
  95         }
  96         return max_lane_count;
  97 }
  98
  99 static int
 100 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 101 {
 102         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 103         int max_link_bw = dp_priv->dpcd[1];
 104
 105         switch (max_link_bw) {
 106         case DP_LINK_BW_1_62:
 107         case DP_LINK_BW_2_7:
 108                 break;
 109         default:
 110                 max_link_bw = DP_LINK_BW_1_62;
 111                 break;
 112         }
 113         return max_link_bw;
 114 }
 115
 116 static int
 117 intel_dp_link_clock(uint8_t link_bw)
 118 {
 119         if (link_bw == DP_LINK_BW_2_7)
 120                 return 270000;
 121         else
 122                 return 162000;
 123 }
 124
 125 /* I think this is a fiction */
 126 static int
 127 intel_dp_link_required(struct drm_device *dev,
 128                        struct intel_encoder *intel_encoder, int pixel_clock)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131
 132         if (IS_eDP(intel_encoder))
 133                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 134         else
 135                 return pixel_clock * 3;
 136 }
 137
 138 static int
 139 intel_dp_mode_valid(struct drm_connector *connector,
 140                     struct drm_display_mode *mode)
 141 {
 142         struct drm_encoder *encoder = intel_attached_encoder(connector);
 143         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 144         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 145         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 146
 147         if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 148                         > max_link_clock * max_lanes)
 149                 return MODE_CLOCK_HIGH;
 150
 151         if (mode->clock < 10000)
 152                 return MODE_CLOCK_LOW;
 153
 154         return MODE_OK;
 155 }
 156
 157 static uint32_t
 158 pack_aux(uint8_t *src, int src_bytes)
 159 {
 160         int     i;
 161         uint32_t v = 0;
 162
 163         if (src_bytes > 4)
 164                 src_bytes = 4;
 165         for (i = 0; i < src_bytes; i++)
 166                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 167         return v;
 168 }
 169
 170 static void
 171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 172 {
 173         int i;
 174         if (dst_bytes > 4)
 175                 dst_bytes = 4;
 176         for (i = 0; i < dst_bytes; i++)
 177                 dst[i] = src >> ((3-i) * 8);
 178 }
 179
 180 /* hrawclock is 1/4 the FSB frequency */
 181 static int
 182 intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         clkcfg = I915_READ(CLKCFG);
 188         switch (clkcfg & CLKCFG_FSB_MASK) {
 189         case CLKCFG_FSB_400:
 190                 return 100;
 191         case CLKCFG_FSB_533:
 192                 return 133;
 193         case CLKCFG_FSB_667:
 194                 return 166;
 195         case CLKCFG_FSB_800:
 196                 return 200;
 197         case CLKCFG_FSB_1067:
 198                 return 266;
 199         case CLKCFG_FSB_1333:
 200                 return 333;
 201         /* these two are just a guess; one of them might be right */
 202         case CLKCFG_FSB_1600:
 203         case CLKCFG_FSB_1600_ALT:
 204                 return 400;
 205         default:
 206                 return 133;
 207         }
 208 }
 209
 210 static int
 211 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 212                 uint8_t *send, int send_bytes,
 213                 uint8_t *recv, int recv_size)
 214 {
 215         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 216         uint32_t output_reg = dp_priv->output_reg;
 217         struct drm_device *dev = intel_encoder->enc.dev;
 218         struct drm_i915_private *dev_priv = dev->dev_private;
 219         uint32_t ch_ctl = output_reg + 0x10;
 220         uint32_t ch_data = ch_ctl + 4;
 221         int i;
 222         int recv_bytes;
 223         uint32_t ctl;
 224         uint32_t status;
 225         uint32_t aux_clock_divider;
 226         int try, precharge;
 227
 228         /* The clock divider is based off the hrawclk,
 229          * and would like to run at 2MHz. So, take the
 230          * hrawclk value and divide by 2 and use that
 231          */
 232         if (IS_eDP(intel_encoder)) {
 233                 if (IS_GEN6(dev))
 234                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 235                 else
 236                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 237         } else if (HAS_PCH_SPLIT(dev))
 238                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 239         else
 240                 aux_clock_divider = intel_hrawclk(dev) / 2;
 241
 242         if (IS_GEN6(dev))
 243                 precharge = 3;
 244         else
 245                 precharge = 5;
 246
 247         /* Must try at least 3 times according to DP spec */
 248         for (try = 0; try < 5; try++) {
 249                 /* Load the send data into the aux channel data registers */
 250                 for (i = 0; i < send_bytes; i += 4) {
 251                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 252
 253                         I915_WRITE(ch_data + i, d);
 254                 }
 255
 256                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 257                        DP_AUX_CH_CTL_TIME_OUT_400us |
 258                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 259                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 260                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 261                        DP_AUX_CH_CTL_DONE |
 262                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 263                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 264
 265                 /* Send the command and wait for it to complete */
 266                 I915_WRITE(ch_ctl, ctl);
 267                 (void) I915_READ(ch_ctl);
 268                 for (;;) {
 269                         udelay(100);
 270                         status = I915_READ(ch_ctl);
 271                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 272                                 break;
 273                 }
 274
 275                 /* Clear done status and any errors */
 276                 I915_WRITE(ch_ctl, (status |
 277                                 DP_AUX_CH_CTL_DONE |
 278                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 279                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 280                 (void) I915_READ(ch_ctl);
 281                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 282                         break;
 283         }
 284
 285         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 286                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 287                 return -EBUSY;
 288         }
 289
 290         /* Check for timeout or receive error.
 291          * Timeouts occur when the sink is not connected
 292          */
 293         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 294                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 295                 return -EIO;
 296         }
 297
 298         /* Timeouts occur when the device isn't connected, so they're
 299          * "normal" -- don't fill the kernel log with these */
 300         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 301                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 302                 return -ETIMEDOUT;
 303         }
 304
 305         /* Unload any bytes sent back from the other side */
 306         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 307                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 308
 309         if (recv_bytes > recv_size)
 310                 recv_bytes = recv_size;
 311
 312         for (i = 0; i < recv_bytes; i += 4) {
 313                 uint32_t    d = I915_READ(ch_data + i);
 314
 315                 unpack_aux(d, recv + i, recv_bytes - i);
 316         }
 317
 318         return recv_bytes;
 319 }
 320
 321 /* Write data to the aux channel in native mode */
 322 static int
 323 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 324                           uint16_t address, uint8_t *send, int send_bytes)
 325 {
 326         int ret;
 327         uint8_t msg[20];
 328         int msg_bytes;
 329         uint8_t ack;
 330
 331         if (send_bytes > 16)
 332                 return -1;
 333         msg[0] = AUX_NATIVE_WRITE << 4;
 334         msg[1] = address >> 8;
 335         msg[2] = address & 0xff;
 336         msg[3] = send_bytes - 1;
 337         memcpy(&msg[4], send, send_bytes);
 338         msg_bytes = send_bytes + 4;
 339         for (;;) {
 340                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 341                 if (ret < 0)
 342                         return ret;
 343                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 344                         break;
 345                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 346                         udelay(100);
 347                 else
 348                         return -EIO;
 349         }
 350         return send_bytes;
 351 }
 352
 353 /* Write a single byte to the aux channel in native mode */
 354 static int
 355 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 356                             uint16_t address, uint8_t byte)
 357 {
 358         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 359 }
 360
 361 /* read bytes from a native aux channel */
 362 static int
 363 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 364                          uint16_t address, uint8_t *recv, int recv_bytes)
 365 {
 366         uint8_t msg[4];
 367         int msg_bytes;
 368         uint8_t reply[20];
 369         int reply_bytes;
 370         uint8_t ack;
 371         int ret;
 372
 373         msg[0] = AUX_NATIVE_READ << 4;
 374         msg[1] = address >> 8;
 375         msg[2] = address & 0xff;
 376         msg[3] = recv_bytes - 1;
 377
 378         msg_bytes = 4;
 379         reply_bytes = recv_bytes + 1;
 380
 381         for (;;) {
 382                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 383                                       reply, reply_bytes);
 384                 if (ret == 0)
 385                         return -EPROTO;
 386                 if (ret < 0)
 387                         return ret;
 388                 ack = reply[0];
 389                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 390                         memcpy(recv, reply + 1, ret - 1);
 391                         return ret - 1;
 392                 }
 393                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 394                         udelay(100);
 395                 else
 396                         return -EIO;
 397         }
 398 }
 399
 400 static int
 401 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 402                     uint8_t write_byte, uint8_t *read_byte)
 403 {
 404         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 405         struct intel_dp_priv *dp_priv = container_of(adapter,
 406                                                      struct intel_dp_priv,
 407                                                      adapter);
 408         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 409         uint16_t address = algo_data->address;
 410         uint8_t msg[5];
 411         uint8_t reply[2];
 412         int msg_bytes;
 413         int reply_bytes;
 414         int ret;
 415
 416         /* Set up the command byte */
 417         if (mode & MODE_I2C_READ)
 418                 msg[0] = AUX_I2C_READ << 4;
 419         else
 420                 msg[0] = AUX_I2C_WRITE << 4;
 421
 422         if (!(mode & MODE_I2C_STOP))
 423                 msg[0] |= AUX_I2C_MOT << 4;
 424
 425         msg[1] = address >> 8;
 426         msg[2] = address;
 427
 428         switch (mode) {
 429         case MODE_I2C_WRITE:
 430                 msg[3] = 0;
 431                 msg[4] = write_byte;
 432                 msg_bytes = 5;
 433                 reply_bytes = 1;
 434                 break;
 435         case MODE_I2C_READ:
 436                 msg[3] = 0;
 437                 msg_bytes = 4;
 438                 reply_bytes = 2;
 439                 break;
 440         default:
 441                 msg_bytes = 3;
 442                 reply_bytes = 1;
 443                 break;
 444         }
 445
 446         for (;;) {
 447           ret = intel_dp_aux_ch(intel_encoder,
 448                                 msg, msg_bytes,
 449                                 reply, reply_bytes);
 450                 if (ret < 0) {
 451                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 452                         return ret;
 453                 }
 454                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 455                 case AUX_I2C_REPLY_ACK:
 456                         if (mode == MODE_I2C_READ) {
 457                                 *read_byte = reply[1];
 458                         }
 459                         return reply_bytes - 1;
 460                 case AUX_I2C_REPLY_NACK:
 461                         DRM_DEBUG_KMS("aux_ch nack\n");
 462                         return -EREMOTEIO;
 463                 case AUX_I2C_REPLY_DEFER:
 464                         DRM_DEBUG_KMS("aux_ch defer\n");
 465                         udelay(100);
 466                         break;
 467                 default:
 468                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 469                         return -EREMOTEIO;
 470                 }
 471         }
 472 }
 473
 474 static int
 475 intel_dp_i2c_init(struct intel_encoder *intel_encoder,
 476                   struct intel_connector *intel_connector, const char *name)
 477 {
 478         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 479
 480         DRM_DEBUG_KMS("i2c_init %s\n", name);
 481         dp_priv->algo.running = false;
 482         dp_priv->algo.address = 0;
 483         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 484
 485         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 486         dp_priv->adapter.owner = THIS_MODULE;
 487         dp_priv->adapter.class = I2C_CLASS_DDC;
 488         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 489         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 490         dp_priv->adapter.algo_data = &dp_priv->algo;
 491         dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
 492
 493         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 494 }
 495
 496 static bool
 497 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 498                     struct drm_display_mode *adjusted_mode)
 499 {
 500         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 501         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 502         int lane_count, clock;
 503         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 504         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 505         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 506
 507         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 508                 for (clock = 0; clock <= max_clock; clock++) {
 509                         int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
 510
 511                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 512                                         <= link_avail) {
 513                                 dp_priv->link_bw = bws[clock];
 514                                 dp_priv->lane_count = lane_count;
 515                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 516                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 517                                                 "count %d clock %d\n",
 518                                        dp_priv->link_bw, dp_priv->lane_count,
 519                                        adjusted_mode->clock);
 520                                 return true;
 521                         }
 522                 }
 523         }
 524         return false;
 525 }
 526
 527 struct intel_dp_m_n {
 528         uint32_t        tu;
 529         uint32_t        gmch_m;
 530         uint32_t        gmch_n;
 531         uint32_t        link_m;
 532         uint32_t        link_n;
 533 };
 534
 535 static void
 536 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 537 {
 538         while (*num > 0xffffff || *den > 0xffffff) {
 539                 *num >>= 1;
 540                 *den >>= 1;
 541         }
 542 }
 543
 544 static void
 545 intel_dp_compute_m_n(int bytes_per_pixel,
 546                      int nlanes,
 547                      int pixel_clock,
 548                      int link_clock,
 549                      struct intel_dp_m_n *m_n)
 550 {
 551         m_n->tu = 64;
 552         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 553         m_n->gmch_n = link_clock * nlanes;
 554         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 555         m_n->link_m = pixel_clock;
 556         m_n->link_n = link_clock;
 557         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 558 }
 559
 560 void
 561 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 562                  struct drm_display_mode *adjusted_mode)
 563 {
 564         struct drm_device *dev = crtc->dev;
 565         struct drm_mode_config *mode_config = &dev->mode_config;
 566         struct drm_encoder *encoder;
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 569         int lane_count = 4;
 570         struct intel_dp_m_n m_n;
 571
 572         /*
 573          * Find the lane count in the intel_encoder private
 574          */
 575         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 576                 struct intel_encoder *intel_encoder;
 577                 struct intel_dp_priv *dp_priv;
 578
 579                 if (!encoder || encoder->crtc != crtc)
 580                         continue;
 581
 582                 intel_encoder = enc_to_intel_encoder(encoder);
 583                 dp_priv = intel_encoder->dev_priv;
 584
 585                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 586                         lane_count = dp_priv->lane_count;
 587                         break;
 588                 }
 589         }
 590
 591         /*
 592          * Compute the GMCH and Link ratios. The '3' here is
 593          * the number of bytes_per_pixel post-LUT, which we always
 594          * set up for 8-bits of R/G/B, or 3 bytes total.
 595          */
 596         intel_dp_compute_m_n(3, lane_count,
 597                              mode->clock, adjusted_mode->clock, &m_n);
 598
 599         if (HAS_PCH_SPLIT(dev)) {
 600                 if (intel_crtc->pipe == 0) {
 601                         I915_WRITE(TRANSA_DATA_M1,
 602                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 603                                    m_n.gmch_m);
 604                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 605                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 606                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 607                 } else {
 608                         I915_WRITE(TRANSB_DATA_M1,
 609                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 610                                    m_n.gmch_m);
 611                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 612                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 613                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 614                 }
 615         } else {
 616                 if (intel_crtc->pipe == 0) {
 617                         I915_WRITE(PIPEA_GMCH_DATA_M,
 618                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 619                                    m_n.gmch_m);
 620                         I915_WRITE(PIPEA_GMCH_DATA_N,
 621                                    m_n.gmch_n);
 622                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 623                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 624                 } else {
 625                         I915_WRITE(PIPEB_GMCH_DATA_M,
 626                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 627                                    m_n.gmch_m);
 628                         I915_WRITE(PIPEB_GMCH_DATA_N,
 629                                         m_n.gmch_n);
 630                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 631                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 632                 }
 633         }
 634 }
 635
 636 static void
 637 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 638                   struct drm_display_mode *adjusted_mode)
 639 {
 640         struct drm_device *dev = encoder->dev;
 641         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 642         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 643         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 645
 646         dp_priv->DP = (DP_VOLTAGE_0_4 |
 647                        DP_PRE_EMPHASIS_0);
 648
 649         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 650                 dp_priv->DP |= DP_SYNC_HS_HIGH;
 651         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 652                 dp_priv->DP |= DP_SYNC_VS_HIGH;
 653
 654         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
 655                 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
 656         else
 657                 dp_priv->DP |= DP_LINK_TRAIN_OFF;
 658
 659         switch (dp_priv->lane_count) {
 660         case 1:
 661                 dp_priv->DP |= DP_PORT_WIDTH_1;
 662                 break;
 663         case 2:
 664                 dp_priv->DP |= DP_PORT_WIDTH_2;
 665                 break;
 666         case 4:
 667                 dp_priv->DP |= DP_PORT_WIDTH_4;
 668                 break;
 669         }
 670         if (dp_priv->has_audio)
 671                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 672
 673         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 674         dp_priv->link_configuration[0] = dp_priv->link_bw;
 675         dp_priv->link_configuration[1] = dp_priv->lane_count;
 676
 677         /*
 678          * Check for DPCD version > 1.1,
 679          * enable enahanced frame stuff in that case
 680          */
 681         if (dp_priv->dpcd[0] >= 0x11) {
 682                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 683                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 684         }
 685
 686         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 687         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 688                 dp_priv->DP |= DP_PIPEB_SELECT;
 689
 690         if (IS_eDP(intel_encoder)) {
 691                 /* don't miss out required setting for eDP */
 692                 dp_priv->DP |= DP_PLL_ENABLE;
 693                 if (adjusted_mode->clock < 200000)
 694                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 695                 else
 696                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 697         }
 698 }
 699
 700 static void ironlake_edp_backlight_on (struct drm_device *dev)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703         u32 pp;
 704
 705         DRM_DEBUG_KMS("\n");
 706         pp = I915_READ(PCH_PP_CONTROL);
 707         pp |= EDP_BLC_ENABLE;
 708         I915_WRITE(PCH_PP_CONTROL, pp);
 709 }
 710
 711 static void ironlake_edp_backlight_off (struct drm_device *dev)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714         u32 pp;
 715
 716         DRM_DEBUG_KMS("\n");
 717         pp = I915_READ(PCH_PP_CONTROL);
 718         pp &= ~EDP_BLC_ENABLE;
 719         I915_WRITE(PCH_PP_CONTROL, pp);
 720 }
 721
 722 static void
 723 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 724 {
 725         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 726         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 727         struct drm_device *dev = encoder->dev;
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 730
 731         if (mode != DRM_MODE_DPMS_ON) {
 732                 if (dp_reg & DP_PORT_EN) {
 733                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 734                         if (IS_eDP(intel_encoder))
 735                                 ironlake_edp_backlight_off(dev);
 736                 }
 737         } else {
 738                 if (!(dp_reg & DP_PORT_EN)) {
 739                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 740                         if (IS_eDP(intel_encoder))
 741                                 ironlake_edp_backlight_on(dev);
 742                 }
 743         }
 744         dp_priv->dpms_mode = mode;
 745 }
 746
 747 /*
 748  * Fetch AUX CH registers 0x202 - 0x207 which contain
 749  * link status information
 750  */
 751 static bool
 752 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 753                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 754 {
 755         int ret;
 756
 757         ret = intel_dp_aux_native_read(intel_encoder,
 758                                        DP_LANE0_1_STATUS,
 759                                        link_status, DP_LINK_STATUS_SIZE);
 760         if (ret != DP_LINK_STATUS_SIZE)
 761                 return false;
 762         return true;
 763 }
 764
 765 static uint8_t
 766 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 767                      int r)
 768 {
 769         return link_status[r - DP_LANE0_1_STATUS];
 770 }
 771
 772 static uint8_t
 773 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 774                                  int lane)
 775 {
 776         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 777         int         s = ((lane & 1) ?
 778                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 779                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 780         uint8_t l = intel_dp_link_status(link_status, i);
 781
 782         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 783 }
 784
 785 static uint8_t
 786 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 787                                       int lane)
 788 {
 789         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 790         int         s = ((lane & 1) ?
 791                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 792                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 793         uint8_t l = intel_dp_link_status(link_status, i);
 794
 795         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 796 }
 797
 798
 799 #if 0
 800 static char     *voltage_names[] = {
 801         "0.4V", "0.6V", "0.8V", "1.2V"
 802 };
 803 static char     *pre_emph_names[] = {
 804         "0dB", "3.5dB", "6dB", "9.5dB"
 805 };
 806 static char     *link_train_names[] = {
 807         "pattern 1", "pattern 2", "idle", "off"
 808 };
 809 #endif
 810
 811 /*
 812  * These are source-specific values; current Intel hardware supports
 813  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 814  */
 815 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 816
 817 static uint8_t
 818 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 819 {
 820         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 821         case DP_TRAIN_VOLTAGE_SWING_400:
 822                 return DP_TRAIN_PRE_EMPHASIS_6;
 823         case DP_TRAIN_VOLTAGE_SWING_600:
 824                 return DP_TRAIN_PRE_EMPHASIS_6;
 825         case DP_TRAIN_VOLTAGE_SWING_800:
 826                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 827         case DP_TRAIN_VOLTAGE_SWING_1200:
 828         default:
 829                 return DP_TRAIN_PRE_EMPHASIS_0;
 830         }
 831 }
 832
 833 static void
 834 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 835                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 836                        int lane_count,
 837                        uint8_t train_set[4])
 838 {
 839         uint8_t v = 0;
 840         uint8_t p = 0;
 841         int lane;
 842
 843         for (lane = 0; lane < lane_count; lane++) {
 844                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 845                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 846
 847                 if (this_v > v)
 848                         v = this_v;
 849                 if (this_p > p)
 850                         p = this_p;
 851         }
 852
 853         if (v >= I830_DP_VOLTAGE_MAX)
 854                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 855
 856         if (p >= intel_dp_pre_emphasis_max(v))
 857                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 858
 859         for (lane = 0; lane < 4; lane++)
 860                 train_set[lane] = v | p;
 861 }
 862
 863 static uint32_t
 864 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 865 {
 866         uint32_t        signal_levels = 0;
 867
 868         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 869         case DP_TRAIN_VOLTAGE_SWING_400:
 870         default:
 871                 signal_levels |= DP_VOLTAGE_0_4;
 872                 break;
 873         case DP_TRAIN_VOLTAGE_SWING_600:
 874                 signal_levels |= DP_VOLTAGE_0_6;
 875                 break;
 876         case DP_TRAIN_VOLTAGE_SWING_800:
 877                 signal_levels |= DP_VOLTAGE_0_8;
 878                 break;
 879         case DP_TRAIN_VOLTAGE_SWING_1200:
 880                 signal_levels |= DP_VOLTAGE_1_2;
 881                 break;
 882         }
 883         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 884         case DP_TRAIN_PRE_EMPHASIS_0:
 885         default:
 886                 signal_levels |= DP_PRE_EMPHASIS_0;
 887                 break;
 888         case DP_TRAIN_PRE_EMPHASIS_3_5:
 889                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 890                 break;
 891         case DP_TRAIN_PRE_EMPHASIS_6:
 892                 signal_levels |= DP_PRE_EMPHASIS_6;
 893                 break;
 894         case DP_TRAIN_PRE_EMPHASIS_9_5:
 895                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 896                 break;
 897         }
 898         return signal_levels;
 899 }
 900
 901 /* Gen6's DP voltage swing and pre-emphasis control */
 902 static uint32_t
 903 intel_gen6_edp_signal_levels(uint8_t train_set)
 904 {
 905         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
 906         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
 907                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 908         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
 909                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
 910         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
 911                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
 912         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
 913                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
 914         default:
 915                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
 916                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 917         }
 918 }
 919
 920 static uint8_t
 921 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 922                       int lane)
 923 {
 924         int i = DP_LANE0_1_STATUS + (lane >> 1);
 925         int s = (lane & 1) * 4;
 926         uint8_t l = intel_dp_link_status(link_status, i);
 927
 928         return (l >> s) & 0xf;
 929 }
 930
 931 /* Check for clock recovery is done on all channels */
 932 static bool
 933 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 934 {
 935         int lane;
 936         uint8_t lane_status;
 937
 938         for (lane = 0; lane < lane_count; lane++) {
 939                 lane_status = intel_get_lane_status(link_status, lane);
 940                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 941                         return false;
 942         }
 943         return true;
 944 }
 945
 946 /* Check to see if channel eq is done on all channels */
 947 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 948                          DP_LANE_CHANNEL_EQ_DONE|\
 949                          DP_LANE_SYMBOL_LOCKED)
 950 static bool
 951 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 952 {
 953         uint8_t lane_align;
 954         uint8_t lane_status;
 955         int lane;
 956
 957         lane_align = intel_dp_link_status(link_status,
 958                                           DP_LANE_ALIGN_STATUS_UPDATED);
 959         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 960                 return false;
 961         for (lane = 0; lane < lane_count; lane++) {
 962                 lane_status = intel_get_lane_status(link_status, lane);
 963                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 964                         return false;
 965         }
 966         return true;
 967 }
 968
 969 static bool
 970 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
 971                         uint32_t dp_reg_value,
 972                         uint8_t dp_train_pat,
 973                         uint8_t train_set[4],
 974                         bool first)
 975 {
 976         struct drm_device *dev = intel_encoder->enc.dev;
 977         struct drm_i915_private *dev_priv = dev->dev_private;
 978         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 979         int ret;
 980
 981         I915_WRITE(dp_priv->output_reg, dp_reg_value);
 982         POSTING_READ(dp_priv->output_reg);
 983         if (first)
 984                 intel_wait_for_vblank(dev);
 985
 986         intel_dp_aux_native_write_1(intel_encoder,
 987                                     DP_TRAINING_PATTERN_SET,
 988                                     dp_train_pat);
 989
 990         ret = intel_dp_aux_native_write(intel_encoder,
 991                                         DP_TRAINING_LANE0_SET, train_set, 4);
 992         if (ret != 4)
 993                 return false;
 994
 995         return true;
 996 }
 997
 998 static void
 999 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1000                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1001 {
1002         struct drm_device *dev = intel_encoder->enc.dev;
1003         struct drm_i915_private *dev_priv = dev->dev_private;
1004         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1005         uint8_t train_set[4];
1006         uint8_t link_status[DP_LINK_STATUS_SIZE];
1007         int i;
1008         uint8_t voltage;
1009         bool clock_recovery = false;
1010         bool channel_eq = false;
1011         bool first = true;
1012         int tries;
1013         u32 reg;
1014
1015         /* Write the link configuration data */
1016         intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
1017                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
1018
1019         DP |= DP_PORT_EN;
1020         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1021                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1022         else
1023                 DP &= ~DP_LINK_TRAIN_MASK;
1024         memset(train_set, 0, 4);
1025         voltage = 0xff;
1026         tries = 0;
1027         clock_recovery = false;
1028         for (;;) {
1029                 /* Use train_set[0] to set the voltage and pre emphasis values */
1030                 uint32_t    signal_levels;
1031                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1032                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1033                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1034                 } else {
1035                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1036                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1037                 }
1038
1039                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1040                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1041                 else
1042                         reg = DP | DP_LINK_TRAIN_PAT_1;
1043
1044                 if (!intel_dp_set_link_train(intel_encoder, reg,
1045                                              DP_TRAINING_PATTERN_1, train_set, first))
1046                         break;
1047                 first = false;
1048                 /* Set training pattern 1 */
1049
1050                 udelay(100);
1051                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1052                         break;
1053
1054                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1055                         clock_recovery = true;
1056                         break;
1057                 }
1058
1059                 /* Check to see if we've tried the max voltage */
1060                 for (i = 0; i < dp_priv->lane_count; i++)
1061                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1062                                 break;
1063                 if (i == dp_priv->lane_count)
1064                         break;
1065
1066                 /* Check to see if we've tried the same voltage 5 times */
1067                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1068                         ++tries;
1069                         if (tries == 5)
1070                                 break;
1071                 } else
1072                         tries = 0;
1073                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1074
1075                 /* Compute new train_set as requested by target */
1076                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1077         }
1078
1079         /* channel equalization */
1080         tries = 0;
1081         channel_eq = false;
1082         for (;;) {
1083                 /* Use train_set[0] to set the voltage and pre emphasis values */
1084                 uint32_t    signal_levels;
1085
1086                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1087                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1088                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1089                 } else {
1090                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1091                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1092                 }
1093
1094                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1095                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1096                 else
1097                         reg = DP | DP_LINK_TRAIN_PAT_2;
1098
1099                 /* channel eq pattern */
1100                 if (!intel_dp_set_link_train(intel_encoder, reg,
1101                                              DP_TRAINING_PATTERN_2, train_set,
1102                                              false))
1103                         break;
1104
1105                 udelay(400);
1106                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1107                         break;
1108
1109                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1110                         channel_eq = true;
1111                         break;
1112                 }
1113
1114                 /* Try 5 times */
1115                 if (tries > 5)
1116                         break;
1117
1118                 /* Compute new train_set as requested by target */
1119                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1120                 ++tries;
1121         }
1122
1123         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1124                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1125         else
1126                 reg = DP | DP_LINK_TRAIN_OFF;
1127
1128         I915_WRITE(dp_priv->output_reg, reg);
1129         POSTING_READ(dp_priv->output_reg);
1130         intel_dp_aux_native_write_1(intel_encoder,
1131                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1132 }
1133
1134 static void
1135 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1136 {
1137         struct drm_device *dev = intel_encoder->enc.dev;
1138         struct drm_i915_private *dev_priv = dev->dev_private;
1139         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1140
1141         DRM_DEBUG_KMS("\n");
1142
1143         if (IS_eDP(intel_encoder)) {
1144                 DP &= ~DP_PLL_ENABLE;
1145                 I915_WRITE(dp_priv->output_reg, DP);
1146                 POSTING_READ(dp_priv->output_reg);
1147                 udelay(100);
1148         }
1149
1150         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1151                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1152                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1153                 POSTING_READ(dp_priv->output_reg);
1154         } else {
1155                 DP &= ~DP_LINK_TRAIN_MASK;
1156                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1157                 POSTING_READ(dp_priv->output_reg);
1158         }
1159
1160         udelay(17000);
1161
1162         if (IS_eDP(intel_encoder))
1163                 DP |= DP_LINK_TRAIN_OFF;
1164         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1165         POSTING_READ(dp_priv->output_reg);
1166 }
1167
1168 /*
1169  * According to DP spec
1170  * 5.1.2:
1171  *  1. Read DPCD
1172  *  2. Configure link according to Receiver Capabilities
1173  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1174  *  4. Check link status on receipt of hot-plug interrupt
1175  */
1176
1177 static void
1178 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1179 {
1180         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1181         uint8_t link_status[DP_LINK_STATUS_SIZE];
1182
1183         if (!intel_encoder->enc.crtc)
1184                 return;
1185
1186         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1187                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1188                 return;
1189         }
1190
1191         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1192                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1193 }
1194
1195 static enum drm_connector_status
1196 ironlake_dp_detect(struct drm_connector *connector)
1197 {
1198         struct drm_encoder *encoder = intel_attached_encoder(connector);
1199         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1200         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1201         enum drm_connector_status status;
1202
1203         status = connector_status_disconnected;
1204         if (intel_dp_aux_native_read(intel_encoder,
1205                                      0x000, dp_priv->dpcd,
1206                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1207         {
1208                 if (dp_priv->dpcd[0] != 0)
1209                         status = connector_status_connected;
1210         }
1211         return status;
1212 }
1213
1214 /**
1215  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1216  *
1217  * \return true if DP port is connected.
1218  * \return false if DP port is disconnected.
1219  */
1220 static enum drm_connector_status
1221 intel_dp_detect(struct drm_connector *connector)
1222 {
1223         struct drm_encoder *encoder = intel_attached_encoder(connector);
1224         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1225         struct drm_device *dev = intel_encoder->enc.dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1228         uint32_t temp, bit;
1229         enum drm_connector_status status;
1230
1231         dp_priv->has_audio = false;
1232
1233         if (HAS_PCH_SPLIT(dev))
1234                 return ironlake_dp_detect(connector);
1235
1236         switch (dp_priv->output_reg) {
1237         case DP_B:
1238                 bit = DPB_HOTPLUG_INT_STATUS;
1239                 break;
1240         case DP_C:
1241                 bit = DPC_HOTPLUG_INT_STATUS;
1242                 break;
1243         case DP_D:
1244                 bit = DPD_HOTPLUG_INT_STATUS;
1245                 break;
1246         default:
1247                 return connector_status_unknown;
1248         }
1249
1250         temp = I915_READ(PORT_HOTPLUG_STAT);
1251
1252         if ((temp & bit) == 0)
1253                 return connector_status_disconnected;
1254
1255         status = connector_status_disconnected;
1256         if (intel_dp_aux_native_read(intel_encoder,
1257                                      0x000, dp_priv->dpcd,
1258                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1259         {
1260                 if (dp_priv->dpcd[0] != 0)
1261                         status = connector_status_connected;
1262         }
1263         return status;
1264 }
1265
1266 static int intel_dp_get_modes(struct drm_connector *connector)
1267 {
1268         struct drm_encoder *encoder = intel_attached_encoder(connector);
1269         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1270         struct drm_device *dev = intel_encoder->enc.dev;
1271         struct drm_i915_private *dev_priv = dev->dev_private;
1272         int ret;
1273
1274         /* We should parse the EDID data and find out if it has an audio sink
1275          */
1276
1277         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1278         if (ret)
1279                 return ret;
1280
1281         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1282         if (IS_eDP(intel_encoder)) {
1283                 if (dev_priv->panel_fixed_mode != NULL) {
1284                         struct drm_display_mode *mode;
1285                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1286                         drm_mode_probed_add(connector, mode);
1287                         return 1;
1288                 }
1289         }
1290         return 0;
1291 }
1292
1293 static void
1294 intel_dp_destroy (struct drm_connector *connector)
1295 {
1296         drm_sysfs_connector_remove(connector);
1297         drm_connector_cleanup(connector);
1298         kfree(connector);
1299 }
1300
1301 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1302         .dpms = intel_dp_dpms,
1303         .mode_fixup = intel_dp_mode_fixup,
1304         .prepare = intel_encoder_prepare,
1305         .mode_set = intel_dp_mode_set,
1306         .commit = intel_encoder_commit,
1307 };
1308
1309 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1310         .dpms = drm_helper_connector_dpms,
1311         .detect = intel_dp_detect,
1312         .fill_modes = drm_helper_probe_single_connector_modes,
1313         .destroy = intel_dp_destroy,
1314 };
1315
1316 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1317         .get_modes = intel_dp_get_modes,
1318         .mode_valid = intel_dp_mode_valid,
1319         .best_encoder = intel_attached_encoder,
1320 };
1321
1322 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1323 {
1324         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1325
1326         if (intel_encoder->i2c_bus)
1327                 intel_i2c_destroy(intel_encoder->i2c_bus);
1328         drm_encoder_cleanup(encoder);
1329         kfree(intel_encoder);
1330 }
1331
1332 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1333         .destroy = intel_dp_enc_destroy,
1334 };
1335
1336 void
1337 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1338 {
1339         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1340
1341         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1342                 intel_dp_check_link_status(intel_encoder);
1343 }
1344
1345 /* Return which DP Port should be selected for Transcoder DP control */
1346 int
1347 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1348 {
1349         struct drm_device *dev = crtc->dev;
1350         struct drm_mode_config *mode_config = &dev->mode_config;
1351         struct drm_encoder *encoder;
1352         struct intel_encoder *intel_encoder = NULL;
1353
1354         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1355                 if (!encoder || encoder->crtc != crtc)
1356                         continue;
1357
1358                 intel_encoder = enc_to_intel_encoder(encoder);
1359                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1360                         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1361                         return dp_priv->output_reg;
1362                 }
1363         }
1364         return -1;
1365 }
1366
1367 void
1368 intel_dp_init(struct drm_device *dev, int output_reg)
1369 {
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         struct drm_connector *connector;
1372         struct intel_encoder *intel_encoder;
1373         struct intel_connector *intel_connector;
1374         struct intel_dp_priv *dp_priv;
1375         const char *name = NULL;
1376
1377         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1378                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1379         if (!intel_encoder)
1380                 return;
1381
1382         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1383         if (!intel_connector) {
1384                 kfree(intel_encoder);
1385                 return;
1386         }
1387
1388         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1389
1390         connector = &intel_connector->base;
1391         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1392                            DRM_MODE_CONNECTOR_DisplayPort);
1393         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1394
1395         connector->polled = DRM_CONNECTOR_POLL_HPD;
1396
1397         if (output_reg == DP_A)
1398                 intel_encoder->type = INTEL_OUTPUT_EDP;
1399         else
1400                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1401
1402         if (output_reg == DP_B || output_reg == PCH_DP_B)
1403                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1404         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1405                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1406         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1407                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1408
1409         if (IS_eDP(intel_encoder))
1410                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1411
1412         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1413         connector->interlace_allowed = true;
1414         connector->doublescan_allowed = 0;
1415
1416         dp_priv->intel_encoder = intel_encoder;
1417         dp_priv->output_reg = output_reg;
1418         dp_priv->has_audio = false;
1419         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1420         intel_encoder->dev_priv = dp_priv;
1421
1422         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1423                          DRM_MODE_ENCODER_TMDS);
1424         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1425
1426         drm_mode_connector_attach_encoder(&intel_connector->base,
1427                                           &intel_encoder->enc);
1428         drm_sysfs_connector_add(connector);
1429
1430         /* Set up the DDC bus. */
1431         switch (output_reg) {
1432                 case DP_A:
1433                         name = "DPDDC-A";
1434                         break;
1435                 case DP_B:
1436                 case PCH_DP_B:
1437                         dev_priv->hotplug_supported_mask |=
1438                                 HDMIB_HOTPLUG_INT_STATUS;
1439                         name = "DPDDC-B";
1440                         break;
1441                 case DP_C:
1442                 case PCH_DP_C:
1443                         dev_priv->hotplug_supported_mask |=
1444                                 HDMIC_HOTPLUG_INT_STATUS;
1445                         name = "DPDDC-C";
1446                         break;
1447                 case DP_D:
1448                 case PCH_DP_D:
1449                         dev_priv->hotplug_supported_mask |=
1450                                 HDMID_HOTPLUG_INT_STATUS;
1451                         name = "DPDDC-D";
1452                         break;
1453         }
1454
1455         intel_dp_i2c_init(intel_encoder, intel_connector, name);
1456
1457         intel_encoder->ddc_bus = &dp_priv->adapter;
1458         intel_encoder->hot_plug = intel_dp_hot_plug;
1459
1460         if (output_reg == DP_A) {
1461                 /* initialize panel mode from VBT if available for eDP */
1462                 if (dev_priv->lfp_lvds_vbt_mode) {
1463                         dev_priv->panel_fixed_mode =
1464                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1465                         if (dev_priv->panel_fixed_mode) {
1466                                 dev_priv->panel_fixed_mode->type |=
1467                                         DRM_MODE_TYPE_PREFERRED;
1468                         }
1469                 }
1470         }
1471
1472         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1473          * 0xd.  Failure to do so will result in spurious interrupts being
1474          * generated on the port when a cable is not attached.
1475          */
1476         if (IS_G4X(dev) && !IS_GM45(dev)) {
1477                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1478                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1479         }
1480 }