drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static const intel_limit_t intel_limits_i8xx_dvo = {
 346         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 347         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 348         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 349         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 350         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 351         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 352         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 353         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 354         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 355                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 356         .find_pll = intel_find_best_PLL,
 357 };
 358
 359 static const intel_limit_t intel_limits_i8xx_lvds = {
 360         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 361         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 362         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 363         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 364         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 365         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 366         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 367         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 368         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 369                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 370         .find_pll = intel_find_best_PLL,
 371 };
 372
 373 static const intel_limit_t intel_limits_i9xx_sdvo = {
 374         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 375         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 376         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 377         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 378         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 379         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 380         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 381         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 382         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 384         .find_pll = intel_find_best_PLL,
 385 };
 386
 387 static const intel_limit_t intel_limits_i9xx_lvds = {
 388         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 389         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 390         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 391         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 392         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 393         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 394         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 395         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 396         /* The single-channel range is 25-112Mhz, and dual-channel
 397          * is 80-224Mhz.  Prefer single channel as much as possible.
 398          */
 399         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 400                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 401         .find_pll = intel_find_best_PLL,
 402 };
 403
 404     /* below parameter and function is for G4X Chipset Family*/
 405 static const intel_limit_t intel_limits_g4x_sdvo = {
 406         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 407         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 408         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 409         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 410         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 411         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 412         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 413         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 414         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 415                  .p2_slow = G4X_P2_SDVO_SLOW,
 416                  .p2_fast = G4X_P2_SDVO_FAST
 417         },
 418         .find_pll = intel_g4x_find_best_PLL,
 419 };
 420
 421 static const intel_limit_t intel_limits_g4x_hdmi = {
 422         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 423         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 424         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 425         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 426         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 427         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 428         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 429         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 430         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 431                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 432                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 433         },
 434         .find_pll = intel_g4x_find_best_PLL,
 435 };
 436
 437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 438         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 440         .vco = { .min = G4X_VCO_MIN,
 441                  .max = G4X_VCO_MAX },
 442         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 444         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 446         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 448         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 450         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 452         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 454         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 455                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 456                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 457         },
 458         .find_pll = intel_g4x_find_best_PLL,
 459 };
 460
 461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 462         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 464         .vco = { .min = G4X_VCO_MIN,
 465                  .max = G4X_VCO_MAX },
 466         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 468         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 470         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 472         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 474         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 476         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 478         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 479                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 480                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 481         },
 482         .find_pll = intel_g4x_find_best_PLL,
 483 };
 484
 485 static const intel_limit_t intel_limits_g4x_display_port = {
 486         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 487                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 488         .vco = { .min = G4X_VCO_MIN,
 489                  .max = G4X_VCO_MAX},
 490         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 491                  .max = G4X_N_DISPLAY_PORT_MAX },
 492         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 493                  .max = G4X_M_DISPLAY_PORT_MAX },
 494         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 495                  .max = G4X_M1_DISPLAY_PORT_MAX },
 496         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 497                  .max = G4X_M2_DISPLAY_PORT_MAX },
 498         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 499                  .max = G4X_P_DISPLAY_PORT_MAX },
 500         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 501                  .max = G4X_P1_DISPLAY_PORT_MAX},
 502         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 503                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 504                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 505         .find_pll = intel_find_pll_g4x_dp,
 506 };
 507
 508 static const intel_limit_t intel_limits_pineview_sdvo = {
 509         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 510         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 511         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 512         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 513         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 514         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 515         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 516         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 517         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 518                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 519         .find_pll = intel_find_best_PLL,
 520 };
 521
 522 static const intel_limit_t intel_limits_pineview_lvds = {
 523         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 524         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 525         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 526         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 527         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 528         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 529         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 530         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 531         /* Pineview only supports single-channel mode. */
 532         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 533                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 534         .find_pll = intel_find_best_PLL,
 535 };
 536
 537 static const intel_limit_t intel_limits_ironlake_dac = {
 538         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 539         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 540         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 541         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 542         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 543         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 544         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 545         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 546         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 547                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 548                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 549         .find_pll = intel_g4x_find_best_PLL,
 550 };
 551
 552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 553         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 554         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 555         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 556         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 557         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 558         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 559         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 560         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 561         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 562                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 563                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 564         .find_pll = intel_g4x_find_best_PLL,
 565 };
 566
 567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 568         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 569         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 570         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 571         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 572         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 573         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 574         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 575         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 576         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 577                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 578                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 579         .find_pll = intel_g4x_find_best_PLL,
 580 };
 581
 582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 583         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 584         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 585         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 586         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 587         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 588         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 589         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 590         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 591         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 592                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 593                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 594         .find_pll = intel_g4x_find_best_PLL,
 595 };
 596
 597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 598         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 599         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 600         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 601         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 602         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 603         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 604         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 605         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 606         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 607                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 608                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 609         .find_pll = intel_g4x_find_best_PLL,
 610 };
 611
 612 static const intel_limit_t intel_limits_ironlake_display_port = {
 613         .dot = { .min = IRONLAKE_DOT_MIN,
 614                  .max = IRONLAKE_DOT_MAX },
 615         .vco = { .min = IRONLAKE_VCO_MIN,
 616                  .max = IRONLAKE_VCO_MAX},
 617         .n   = { .min = IRONLAKE_DP_N_MIN,
 618                  .max = IRONLAKE_DP_N_MAX },
 619         .m   = { .min = IRONLAKE_DP_M_MIN,
 620                  .max = IRONLAKE_DP_M_MAX },
 621         .m1  = { .min = IRONLAKE_M1_MIN,
 622                  .max = IRONLAKE_M1_MAX },
 623         .m2  = { .min = IRONLAKE_M2_MIN,
 624                  .max = IRONLAKE_M2_MAX },
 625         .p   = { .min = IRONLAKE_DP_P_MIN,
 626                  .max = IRONLAKE_DP_P_MAX },
 627         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 628                  .max = IRONLAKE_DP_P1_MAX},
 629         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 630                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 631                  .p2_fast = IRONLAKE_DP_P2_FAST },
 632         .find_pll = intel_find_pll_ironlake_dp,
 633 };
 634
 635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         const intel_limit_t *limit;
 640         int refclk = 120;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 644                         refclk = 100;
 645
 646                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 647                     LVDS_CLKB_POWER_UP) {
 648                         /* LVDS dual channel */
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_dual_lvds;
 653                 } else {
 654                         if (refclk == 100)
 655                                 limit = &intel_limits_ironlake_single_lvds_100m;
 656                         else
 657                                 limit = &intel_limits_ironlake_single_lvds;
 658                 }
 659         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 660                         HAS_eDP)
 661                 limit = &intel_limits_ironlake_display_port;
 662         else
 663                 limit = &intel_limits_ironlake_dac;
 664
 665         return limit;
 666 }
 667
 668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         const intel_limit_t *limit;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 676                     LVDS_CLKB_POWER_UP)
 677                         /* LVDS with dual channel */
 678                         limit = &intel_limits_g4x_dual_channel_lvds;
 679                 else
 680                         /* LVDS with dual channel */
 681                         limit = &intel_limits_g4x_single_channel_lvds;
 682         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 683                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 684                 limit = &intel_limits_g4x_hdmi;
 685         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 686                 limit = &intel_limits_g4x_sdvo;
 687         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 688                 limit = &intel_limits_g4x_display_port;
 689         } else /* The option is for other outputs */
 690                 limit = &intel_limits_i9xx_sdvo;
 691
 692         return limit;
 693 }
 694
 695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 696 {
 697         struct drm_device *dev = crtc->dev;
 698         const intel_limit_t *limit;
 699
 700         if (HAS_PCH_SPLIT(dev))
 701                 limit = intel_ironlake_limit(crtc);
 702         else if (IS_G4X(dev)) {
 703                 limit = intel_g4x_limit(crtc);
 704         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_i9xx_lvds;
 707                 else
 708                         limit = &intel_limits_i9xx_sdvo;
 709         } else if (IS_PINEVIEW(dev)) {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_pineview_lvds;
 712                 else
 713                         limit = &intel_limits_pineview_sdvo;
 714         } else {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_i8xx_lvds;
 717                 else
 718                         limit = &intel_limits_i8xx_dvo;
 719         }
 720         return limit;
 721 }
 722
 723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 724 static void pineview_clock(int refclk, intel_clock_t *clock)
 725 {
 726         clock->m = clock->m2 + 2;
 727         clock->p = clock->p1 * clock->p2;
 728         clock->vco = refclk * clock->m / clock->n;
 729         clock->dot = clock->vco / clock->p;
 730 }
 731
 732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 733 {
 734         if (IS_PINEVIEW(dev)) {
 735                 pineview_clock(refclk, clock);
 736                 return;
 737         }
 738         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 739         clock->p = clock->p1 * clock->p2;
 740         clock->vco = refclk * clock->m / (clock->n + 2);
 741         clock->dot = clock->vco / clock->p;
 742 }
 743
 744 /**
 745  * Returns whether any output on the specified pipe is of the specified type
 746  */
 747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 748 {
 749     struct drm_device *dev = crtc->dev;
 750     struct drm_mode_config *mode_config = &dev->mode_config;
 751     struct drm_encoder *l_entry;
 752
 753     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 754             if (l_entry && l_entry->crtc == crtc) {
 755                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 756                     if (intel_encoder->type == type)
 757                             return true;
 758             }
 759     }
 760     return false;
 761 }
 762
 763 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 764 /**
 765  * Returns whether the given set of divisors are valid for a given refclk with
 766  * the given connectors.
 767  */
 768
 769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 770 {
 771         const intel_limit_t *limit = intel_limit (crtc);
 772         struct drm_device *dev = crtc->dev;
 773
 774         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 775                 INTELPllInvalid ("p1 out of range\n");
 776         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 777                 INTELPllInvalid ("p out of range\n");
 778         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 779                 INTELPllInvalid ("m2 out of range\n");
 780         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 781                 INTELPllInvalid ("m1 out of range\n");
 782         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 783                 INTELPllInvalid ("m1 <= m2\n");
 784         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 785                 INTELPllInvalid ("m out of range\n");
 786         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 787                 INTELPllInvalid ("n out of range\n");
 788         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 789                 INTELPllInvalid ("vco out of range\n");
 790         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 791          * connector, etc., rather than just a single range.
 792          */
 793         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 794                 INTELPllInvalid ("dot out of range\n");
 795
 796         return true;
 797 }
 798
 799 static bool
 800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 801                     int target, int refclk, intel_clock_t *best_clock)
 802
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         intel_clock_t clock;
 807         int err = target;
 808
 809         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 810             (I915_READ(LVDS)) != 0) {
 811                 /*
 812                  * For LVDS, if the panel is on, just rely on its current
 813                  * settings for dual-channel.  We haven't figured out how to
 814                  * reliably set up different single/dual channel state, if we
 815                  * even can.
 816                  */
 817                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 818                     LVDS_CLKB_POWER_UP)
 819                         clock.p2 = limit->p2.p2_fast;
 820                 else
 821                         clock.p2 = limit->p2.p2_slow;
 822         } else {
 823                 if (target < limit->p2.dot_limit)
 824                         clock.p2 = limit->p2.p2_slow;
 825                 else
 826                         clock.p2 = limit->p2.p2_fast;
 827         }
 828
 829         memset (best_clock, 0, sizeof (*best_clock));
 830
 831         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 832              clock.m1++) {
 833                 for (clock.m2 = limit->m2.min;
 834                      clock.m2 <= limit->m2.max; clock.m2++) {
 835                         /* m1 is always 0 in Pineview */
 836                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 837                                 break;
 838                         for (clock.n = limit->n.min;
 839                              clock.n <= limit->n.max; clock.n++) {
 840                                 for (clock.p1 = limit->p1.min;
 841                                         clock.p1 <= limit->p1.max; clock.p1++) {
 842                                         int this_err;
 843
 844                                         intel_clock(dev, refclk, &clock);
 845
 846                                         if (!intel_PLL_is_valid(crtc, &clock))
 847                                                 continue;
 848
 849                                         this_err = abs(clock.dot - target);
 850                                         if (this_err < err) {
 851                                                 *best_clock = clock;
 852                                                 err = this_err;
 853                                         }
 854                                 }
 855                         }
 856                 }
 857         }
 858
 859         return (err != target);
 860 }
 861
 862 static bool
 863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 864                         int target, int refclk, intel_clock_t *best_clock)
 865 {
 866         struct drm_device *dev = crtc->dev;
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         intel_clock_t clock;
 869         int max_n;
 870         bool found;
 871         /* approximately equals target * 0.00585 */
 872         int err_most = (target >> 8) + (target >> 9);
 873         found = false;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 876                 int lvds_reg;
 877
 878                 if (HAS_PCH_SPLIT(dev))
 879                         lvds_reg = PCH_LVDS;
 880                 else
 881                         lvds_reg = LVDS;
 882                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 883                     LVDS_CLKB_POWER_UP)
 884                         clock.p2 = limit->p2.p2_fast;
 885                 else
 886                         clock.p2 = limit->p2.p2_slow;
 887         } else {
 888                 if (target < limit->p2.dot_limit)
 889                         clock.p2 = limit->p2.p2_slow;
 890                 else
 891                         clock.p2 = limit->p2.p2_fast;
 892         }
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895         max_n = limit->n.max;
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 /* based on hardware requirement, prefere larger m1,m2 */
 899                 for (clock.m1 = limit->m1.max;
 900                      clock.m1 >= limit->m1.min; clock.m1--) {
 901                         for (clock.m2 = limit->m2.max;
 902                              clock.m2 >= limit->m2.min; clock.m2--) {
 903                                 for (clock.p1 = limit->p1.max;
 904                                      clock.p1 >= limit->p1.min; clock.p1--) {
 905                                         int this_err;
 906
 907                                         intel_clock(dev, refclk, &clock);
 908                                         if (!intel_PLL_is_valid(crtc, &clock))
 909                                                 continue;
 910                                         this_err = abs(clock.dot - target) ;
 911                                         if (this_err < err_most) {
 912                                                 *best_clock = clock;
 913                                                 err_most = this_err;
 914                                                 max_n = clock.n;
 915                                                 found = true;
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         return found;
 922 }
 923
 924 static bool
 925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 926                            int target, int refclk, intel_clock_t *best_clock)
 927 {
 928         struct drm_device *dev = crtc->dev;
 929         intel_clock_t clock;
 930
 931         /* return directly when it is eDP */
 932         if (HAS_eDP)
 933                 return true;
 934
 935         if (target < 200000) {
 936                 clock.n = 1;
 937                 clock.p1 = 2;
 938                 clock.p2 = 10;
 939                 clock.m1 = 12;
 940                 clock.m2 = 9;
 941         } else {
 942                 clock.n = 2;
 943                 clock.p1 = 1;
 944                 clock.p2 = 10;
 945                 clock.m1 = 14;
 946                 clock.m2 = 8;
 947         }
 948         intel_clock(dev, refclk, &clock);
 949         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 950         return true;
 951 }
 952
 953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 954 static bool
 955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 956                       int target, int refclk, intel_clock_t *best_clock)
 957 {
 958     intel_clock_t clock;
 959     if (target < 200000) {
 960         clock.p1 = 2;
 961         clock.p2 = 10;
 962         clock.n = 2;
 963         clock.m1 = 23;
 964         clock.m2 = 8;
 965     } else {
 966         clock.p1 = 1;
 967         clock.p2 = 10;
 968         clock.n = 1;
 969         clock.m1 = 14;
 970         clock.m2 = 2;
 971     }
 972     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 973     clock.p = (clock.p1 * clock.p2);
 974     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 975     clock.vco = 0;
 976     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 977     return true;
 978 }
 979
 980 /**
 981  * intel_wait_for_vblank - wait for vblank on a given pipe
 982  * @dev: drm device
 983  * @pipe: pipe to wait for
 984  *
 985  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 986  * mode setting code.
 987  */
 988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 992
 993         /* Clear existing vblank status. Note this will clear any other
 994          * sticky status fields as well.
 995          *
 996          * This races with i915_driver_irq_handler() with the result
 997          * that either function could miss a vblank event.  Here it is not
 998          * fatal, as we will either wait upon the next vblank interrupt or
 999          * timeout.  Generally speaking intel_wait_for_vblank() is only
1000          * called during modeset at which time the GPU should be idle and
1001          * should *not* be performing page flips and thus not waiting on
1002          * vblanks...
1003          * Currently, the result of us stealing a vblank from the irq
1004          * handler is that a single frame will be skipped during swapbuffers.
1005          */
1006         I915_WRITE(pipestat_reg,
1007                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009         /* Wait for vblank interrupt bit to set */
1010         if (wait_for((I915_READ(pipestat_reg) &
1011                       PIPE_VBLANK_INTERRUPT_STATUS),
1012                      50, 0))
1013                 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /*
1017  * intel_wait_for_pipe_off - wait for pipe to turn off
1018  * @dev: drm device
1019  * @pipe: pipe to wait for
1020  *
1021  * After disabling a pipe, we can't wait for vblank in the usual way,
1022  * spinning on the vblank interrupt status bit, since we won't actually
1023  * see an interrupt when the pipe is disabled.
1024  *
1025  * On Gen4 and above:
1026  *   wait for the pipe register state bit to turn off
1027  *
1028  * Otherwise:
1029  *   wait for the display line value to settle (it usually
1030  *   ends up stopping at the start of the next frame).
1031  *
1032  */
1033 static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1034 {
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036
1037         if (INTEL_INFO(dev)->gen >= 4) {
1038                 int pipeconf_reg = (pipe == 0 ? PIPEACONF : PIPEBCONF);
1039
1040                 /* Wait for the Pipe State to go off */
1041                 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0,
1042                              100, 0))
1043                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1044         } else {
1045                 u32 last_line;
1046                 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1047                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1048
1049                 /* Wait for the display line to settle */
1050                 do {
1051                         last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1052                         mdelay(5);
1053                 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1054                          time_after(timeout, jiffies));
1055                 if (time_after(jiffies, timeout))
1056                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1057         }
1058 }
1059
1060 /* Parameters have changed, update FBC info */
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 {
1063         struct drm_device *dev = crtc->dev;
1064         struct drm_i915_private *dev_priv = dev->dev_private;
1065         struct drm_framebuffer *fb = crtc->fb;
1066         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069         int plane, i;
1070         u32 fbc_ctl, fbc_ctl2;
1071
1072         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1073
1074         if (fb->pitch < dev_priv->cfb_pitch)
1075                 dev_priv->cfb_pitch = fb->pitch;
1076
1077         /* FBC_CTL wants 64B units */
1078         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1079         dev_priv->cfb_fence = obj_priv->fence_reg;
1080         dev_priv->cfb_plane = intel_crtc->plane;
1081         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1082
1083         /* Clear old tags */
1084         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1085                 I915_WRITE(FBC_TAG + (i * 4), 0);
1086
1087         /* Set it up... */
1088         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1089         if (obj_priv->tiling_mode != I915_TILING_NONE)
1090                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1091         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1092         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1093
1094         /* enable it... */
1095         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1096         if (IS_I945GM(dev))
1097                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1098         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1099         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1100         if (obj_priv->tiling_mode != I915_TILING_NONE)
1101                 fbc_ctl |= dev_priv->cfb_fence;
1102         I915_WRITE(FBC_CONTROL, fbc_ctl);
1103
1104         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1105                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1106 }
1107
1108 void i8xx_disable_fbc(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 fbc_ctl;
1112
1113         if (!I915_HAS_FBC(dev))
1114                 return;
1115
1116         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1117                 return; /* Already off, just return */
1118
1119         /* Disable compression */
1120         fbc_ctl = I915_READ(FBC_CONTROL);
1121         fbc_ctl &= ~FBC_CTL_EN;
1122         I915_WRITE(FBC_CONTROL, fbc_ctl);
1123
1124         /* Wait for compressing bit to clear */
1125         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1126                 DRM_DEBUG_KMS("FBC idle timed out\n");
1127                 return;
1128         }
1129
1130         DRM_DEBUG_KMS("disabled FBC\n");
1131 }
1132
1133 static bool i8xx_fbc_enabled(struct drm_device *dev)
1134 {
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136
1137         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1138 }
1139
1140 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1141 {
1142         struct drm_device *dev = crtc->dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144         struct drm_framebuffer *fb = crtc->fb;
1145         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1146         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1148         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1149                      DPFC_CTL_PLANEB);
1150         unsigned long stall_watermark = 200;
1151         u32 dpfc_ctl;
1152
1153         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1154         dev_priv->cfb_fence = obj_priv->fence_reg;
1155         dev_priv->cfb_plane = intel_crtc->plane;
1156
1157         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1158         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1159                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1160                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1161         } else {
1162                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1163         }
1164
1165         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1166         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1167                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1168                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1169         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1170
1171         /* enable it... */
1172         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1173
1174         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1175 }
1176
1177 void g4x_disable_fbc(struct drm_device *dev)
1178 {
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         u32 dpfc_ctl;
1181
1182         /* Disable compression */
1183         dpfc_ctl = I915_READ(DPFC_CONTROL);
1184         dpfc_ctl &= ~DPFC_CTL_EN;
1185         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1186
1187         DRM_DEBUG_KMS("disabled FBC\n");
1188 }
1189
1190 static bool g4x_fbc_enabled(struct drm_device *dev)
1191 {
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1195 }
1196
1197 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1198 {
1199         struct drm_device *dev = crtc->dev;
1200         struct drm_i915_private *dev_priv = dev->dev_private;
1201         struct drm_framebuffer *fb = crtc->fb;
1202         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1203         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1205         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1206                                                DPFC_CTL_PLANEB;
1207         unsigned long stall_watermark = 200;
1208         u32 dpfc_ctl;
1209
1210         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1211         dev_priv->cfb_fence = obj_priv->fence_reg;
1212         dev_priv->cfb_plane = intel_crtc->plane;
1213
1214         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1215         dpfc_ctl &= DPFC_RESERVED;
1216         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1217         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1218                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1219                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1220         } else {
1221                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1222         }
1223
1224         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1225         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1226                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1227                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1228         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1229         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1230         /* enable it... */
1231         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1232                    DPFC_CTL_EN);
1233
1234         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1235 }
1236
1237 void ironlake_disable_fbc(struct drm_device *dev)
1238 {
1239         struct drm_i915_private *dev_priv = dev->dev_private;
1240         u32 dpfc_ctl;
1241
1242         /* Disable compression */
1243         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1244         dpfc_ctl &= ~DPFC_CTL_EN;
1245         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1246
1247         DRM_DEBUG_KMS("disabled FBC\n");
1248 }
1249
1250 static bool ironlake_fbc_enabled(struct drm_device *dev)
1251 {
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1255 }
1256
1257 bool intel_fbc_enabled(struct drm_device *dev)
1258 {
1259         struct drm_i915_private *dev_priv = dev->dev_private;
1260
1261         if (!dev_priv->display.fbc_enabled)
1262                 return false;
1263
1264         return dev_priv->display.fbc_enabled(dev);
1265 }
1266
1267 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1268 {
1269         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1270
1271         if (!dev_priv->display.enable_fbc)
1272                 return;
1273
1274         dev_priv->display.enable_fbc(crtc, interval);
1275 }
1276
1277 void intel_disable_fbc(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281         if (!dev_priv->display.disable_fbc)
1282                 return;
1283
1284         dev_priv->display.disable_fbc(dev);
1285 }
1286
1287 /**
1288  * intel_update_fbc - enable/disable FBC as needed
1289  * @crtc: CRTC to point the compressor at
1290  * @mode: mode in use
1291  *
1292  * Set up the framebuffer compression hardware at mode set time.  We
1293  * enable it if possible:
1294  *   - plane A only (on pre-965)
1295  *   - no pixel mulitply/line duplication
1296  *   - no alpha buffer discard
1297  *   - no dual wide
1298  *   - framebuffer <= 2048 in width, 1536 in height
1299  *
1300  * We can't assume that any compression will take place (worst case),
1301  * so the compressed buffer has to be the same size as the uncompressed
1302  * one.  It also must reside (along with the line length buffer) in
1303  * stolen memory.
1304  *
1305  * We need to enable/disable FBC on a global basis.
1306  */
1307 static void intel_update_fbc(struct drm_crtc *crtc,
1308                              struct drm_display_mode *mode)
1309 {
1310         struct drm_device *dev = crtc->dev;
1311         struct drm_i915_private *dev_priv = dev->dev_private;
1312         struct drm_framebuffer *fb = crtc->fb;
1313         struct intel_framebuffer *intel_fb;
1314         struct drm_i915_gem_object *obj_priv;
1315         struct drm_crtc *tmp_crtc;
1316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1317         int plane = intel_crtc->plane;
1318         int crtcs_enabled = 0;
1319
1320         DRM_DEBUG_KMS("\n");
1321
1322         if (!i915_powersave)
1323                 return;
1324
1325         if (!I915_HAS_FBC(dev))
1326                 return;
1327
1328         if (!crtc->fb)
1329                 return;
1330
1331         intel_fb = to_intel_framebuffer(fb);
1332         obj_priv = to_intel_bo(intel_fb->obj);
1333
1334         /*
1335          * If FBC is already on, we just have to verify that we can
1336          * keep it that way...
1337          * Need to disable if:
1338          *   - more than one pipe is active
1339          *   - changing FBC params (stride, fence, mode)
1340          *   - new fb is too large to fit in compressed buffer
1341          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1342          */
1343         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1344                 if (tmp_crtc->enabled)
1345                         crtcs_enabled++;
1346         }
1347         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1348         if (crtcs_enabled > 1) {
1349                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1350                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1351                 goto out_disable;
1352         }
1353         if (intel_fb->obj->size > dev_priv->cfb_size) {
1354                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1355                                 "compression\n");
1356                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1357                 goto out_disable;
1358         }
1359         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1360             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1361                 DRM_DEBUG_KMS("mode incompatible with compression, "
1362                                 "disabling\n");
1363                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1364                 goto out_disable;
1365         }
1366         if ((mode->hdisplay > 2048) ||
1367             (mode->vdisplay > 1536)) {
1368                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1369                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1370                 goto out_disable;
1371         }
1372         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1373                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1374                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1375                 goto out_disable;
1376         }
1377         if (obj_priv->tiling_mode != I915_TILING_X) {
1378                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1379                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1380                 goto out_disable;
1381         }
1382
1383         /* If the kernel debugger is active, always disable compression */
1384         if (in_dbg_master())
1385                 goto out_disable;
1386
1387         if (intel_fbc_enabled(dev)) {
1388                 /* We can re-enable it in this case, but need to update pitch */
1389                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1390                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1391                     (plane != dev_priv->cfb_plane))
1392                         intel_disable_fbc(dev);
1393         }
1394
1395         /* Now try to turn it back on if possible */
1396         if (!intel_fbc_enabled(dev))
1397                 intel_enable_fbc(crtc, 500);
1398
1399         return;
1400
1401 out_disable:
1402         /* Multiple disables should be harmless */
1403         if (intel_fbc_enabled(dev)) {
1404                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1405                 intel_disable_fbc(dev);
1406         }
1407 }
1408
1409 int
1410 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1411 {
1412         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1413         u32 alignment;
1414         int ret;
1415
1416         switch (obj_priv->tiling_mode) {
1417         case I915_TILING_NONE:
1418                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1419                         alignment = 128 * 1024;
1420                 else if (IS_I965G(dev))
1421                         alignment = 4 * 1024;
1422                 else
1423                         alignment = 64 * 1024;
1424                 break;
1425         case I915_TILING_X:
1426                 /* pin() will align the object as required by fence */
1427                 alignment = 0;
1428                 break;
1429         case I915_TILING_Y:
1430                 /* FIXME: Is this true? */
1431                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1432                 return -EINVAL;
1433         default:
1434                 BUG();
1435         }
1436
1437         ret = i915_gem_object_pin(obj, alignment);
1438         if (ret != 0)
1439                 return ret;
1440
1441         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1442          * fence, whereas 965+ only requires a fence if using
1443          * framebuffer compression.  For simplicity, we always install
1444          * a fence as the cost is not that onerous.
1445          */
1446         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1447             obj_priv->tiling_mode != I915_TILING_NONE) {
1448                 ret = i915_gem_object_get_fence_reg(obj);
1449                 if (ret != 0) {
1450                         i915_gem_object_unpin(obj);
1451                         return ret;
1452                 }
1453         }
1454
1455         return 0;
1456 }
1457
1458 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1459 static int
1460 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1461                            int x, int y)
1462 {
1463         struct drm_device *dev = crtc->dev;
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1466         struct intel_framebuffer *intel_fb;
1467         struct drm_i915_gem_object *obj_priv;
1468         struct drm_gem_object *obj;
1469         int plane = intel_crtc->plane;
1470         unsigned long Start, Offset;
1471         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1472         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1473         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1474         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1475         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1476         u32 dspcntr;
1477
1478         switch (plane) {
1479         case 0:
1480         case 1:
1481                 break;
1482         default:
1483                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1484                 return -EINVAL;
1485         }
1486
1487         intel_fb = to_intel_framebuffer(fb);
1488         obj = intel_fb->obj;
1489         obj_priv = to_intel_bo(obj);
1490
1491         dspcntr = I915_READ(dspcntr_reg);
1492         /* Mask out pixel format bits in case we change it */
1493         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1494         switch (fb->bits_per_pixel) {
1495         case 8:
1496                 dspcntr |= DISPPLANE_8BPP;
1497                 break;
1498         case 16:
1499                 if (fb->depth == 15)
1500                         dspcntr |= DISPPLANE_15_16BPP;
1501                 else
1502                         dspcntr |= DISPPLANE_16BPP;
1503                 break;
1504         case 24:
1505         case 32:
1506                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1507                 break;
1508         default:
1509                 DRM_ERROR("Unknown color depth\n");
1510                 return -EINVAL;
1511         }
1512         if (IS_I965G(dev)) {
1513                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1514                         dspcntr |= DISPPLANE_TILED;
1515                 else
1516                         dspcntr &= ~DISPPLANE_TILED;
1517         }
1518
1519         if (HAS_PCH_SPLIT(dev))
1520                 /* must disable */
1521                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1522
1523         I915_WRITE(dspcntr_reg, dspcntr);
1524
1525         Start = obj_priv->gtt_offset;
1526         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1527
1528         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1529                       Start, Offset, x, y, fb->pitch);
1530         I915_WRITE(dspstride, fb->pitch);
1531         if (IS_I965G(dev)) {
1532                 I915_WRITE(dspsurf, Start);
1533                 I915_WRITE(dsptileoff, (y << 16) | x);
1534                 I915_WRITE(dspbase, Offset);
1535         } else {
1536                 I915_WRITE(dspbase, Start + Offset);
1537         }
1538         POSTING_READ(dspbase);
1539
1540         if (IS_I965G(dev) || plane == 0)
1541                 intel_update_fbc(crtc, &crtc->mode);
1542
1543         intel_wait_for_vblank(dev, intel_crtc->pipe);
1544         intel_increase_pllclock(crtc, true);
1545
1546         return 0;
1547 }
1548
1549 static int
1550 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1551                     struct drm_framebuffer *old_fb)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_master_private *master_priv;
1555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1556         struct intel_framebuffer *intel_fb;
1557         struct drm_i915_gem_object *obj_priv;
1558         struct drm_gem_object *obj;
1559         int pipe = intel_crtc->pipe;
1560         int plane = intel_crtc->plane;
1561         int ret;
1562
1563         /* no fb bound */
1564         if (!crtc->fb) {
1565                 DRM_DEBUG_KMS("No FB bound\n");
1566                 return 0;
1567         }
1568
1569         switch (plane) {
1570         case 0:
1571         case 1:
1572                 break;
1573         default:
1574                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1575                 return -EINVAL;
1576         }
1577
1578         intel_fb = to_intel_framebuffer(crtc->fb);
1579         obj = intel_fb->obj;
1580         obj_priv = to_intel_bo(obj);
1581
1582         mutex_lock(&dev->struct_mutex);
1583         ret = intel_pin_and_fence_fb_obj(dev, obj);
1584         if (ret != 0) {
1585                 mutex_unlock(&dev->struct_mutex);
1586                 return ret;
1587         }
1588
1589         ret = i915_gem_object_set_to_display_plane(obj);
1590         if (ret != 0) {
1591                 i915_gem_object_unpin(obj);
1592                 mutex_unlock(&dev->struct_mutex);
1593                 return ret;
1594         }
1595
1596         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1597         if (ret) {
1598                 i915_gem_object_unpin(obj);
1599                 mutex_unlock(&dev->struct_mutex);
1600                 return ret;
1601         }
1602
1603         if (old_fb) {
1604                 intel_fb = to_intel_framebuffer(old_fb);
1605                 obj_priv = to_intel_bo(intel_fb->obj);
1606                 i915_gem_object_unpin(intel_fb->obj);
1607         }
1608
1609         mutex_unlock(&dev->struct_mutex);
1610
1611         if (!dev->primary->master)
1612                 return 0;
1613
1614         master_priv = dev->primary->master->driver_priv;
1615         if (!master_priv->sarea_priv)
1616                 return 0;
1617
1618         if (pipe) {
1619                 master_priv->sarea_priv->pipeB_x = x;
1620                 master_priv->sarea_priv->pipeB_y = y;
1621         } else {
1622                 master_priv->sarea_priv->pipeA_x = x;
1623                 master_priv->sarea_priv->pipeA_y = y;
1624         }
1625
1626         return 0;
1627 }
1628
1629 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1630 {
1631         struct drm_device *dev = crtc->dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         u32 dpa_ctl;
1634
1635         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1636         dpa_ctl = I915_READ(DP_A);
1637         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1638
1639         if (clock < 200000) {
1640                 u32 temp;
1641                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1642                 /* workaround for 160Mhz:
1643                    1) program 0x4600c bits 15:0 = 0x8124
1644                    2) program 0x46010 bit 0 = 1
1645                    3) program 0x46034 bit 24 = 1
1646                    4) program 0x64000 bit 14 = 1
1647                    */
1648                 temp = I915_READ(0x4600c);
1649                 temp &= 0xffff0000;
1650                 I915_WRITE(0x4600c, temp | 0x8124);
1651
1652                 temp = I915_READ(0x46010);
1653                 I915_WRITE(0x46010, temp | 1);
1654
1655                 temp = I915_READ(0x46034);
1656                 I915_WRITE(0x46034, temp | (1 << 24));
1657         } else {
1658                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1659         }
1660         I915_WRITE(DP_A, dpa_ctl);
1661
1662         udelay(500);
1663 }
1664
1665 /* The FDI link training functions for ILK/Ibexpeak. */
1666 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1667 {
1668         struct drm_device *dev = crtc->dev;
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1671         int pipe = intel_crtc->pipe;
1672         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1673         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1674         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1675         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1676         u32 temp, tries = 0;
1677
1678         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1679            for train result */
1680         temp = I915_READ(fdi_rx_imr_reg);
1681         temp &= ~FDI_RX_SYMBOL_LOCK;
1682         temp &= ~FDI_RX_BIT_LOCK;
1683         I915_WRITE(fdi_rx_imr_reg, temp);
1684         I915_READ(fdi_rx_imr_reg);
1685         udelay(150);
1686
1687         /* enable CPU FDI TX and PCH FDI RX */
1688         temp = I915_READ(fdi_tx_reg);
1689         temp |= FDI_TX_ENABLE;
1690         temp &= ~(7 << 19);
1691         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1692         temp &= ~FDI_LINK_TRAIN_NONE;
1693         temp |= FDI_LINK_TRAIN_PATTERN_1;
1694         I915_WRITE(fdi_tx_reg, temp);
1695         I915_READ(fdi_tx_reg);
1696
1697         temp = I915_READ(fdi_rx_reg);
1698         temp &= ~FDI_LINK_TRAIN_NONE;
1699         temp |= FDI_LINK_TRAIN_PATTERN_1;
1700         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1701         I915_READ(fdi_rx_reg);
1702         udelay(150);
1703
1704         for (tries = 0; tries < 5; tries++) {
1705                 temp = I915_READ(fdi_rx_iir_reg);
1706                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1707
1708                 if ((temp & FDI_RX_BIT_LOCK)) {
1709                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1710                         I915_WRITE(fdi_rx_iir_reg,
1711                                    temp | FDI_RX_BIT_LOCK);
1712                         break;
1713                 }
1714         }
1715         if (tries == 5)
1716                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1717
1718         /* Train 2 */
1719         temp = I915_READ(fdi_tx_reg);
1720         temp &= ~FDI_LINK_TRAIN_NONE;
1721         temp |= FDI_LINK_TRAIN_PATTERN_2;
1722         I915_WRITE(fdi_tx_reg, temp);
1723
1724         temp = I915_READ(fdi_rx_reg);
1725         temp &= ~FDI_LINK_TRAIN_NONE;
1726         temp |= FDI_LINK_TRAIN_PATTERN_2;
1727         I915_WRITE(fdi_rx_reg, temp);
1728         udelay(150);
1729
1730         tries = 0;
1731
1732         for (tries = 0; tries < 5; tries++) {
1733                 temp = I915_READ(fdi_rx_iir_reg);
1734                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1735
1736                 if (temp & FDI_RX_SYMBOL_LOCK) {
1737                         I915_WRITE(fdi_rx_iir_reg,
1738                                    temp | FDI_RX_SYMBOL_LOCK);
1739                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1740                         break;
1741                 }
1742         }
1743         if (tries == 5)
1744                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1745
1746         DRM_DEBUG_KMS("FDI train done\n");
1747 }
1748
1749 static int snb_b_fdi_train_param [] = {
1750         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1751         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1752         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1753         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1754 };
1755
1756 /* The FDI link training functions for SNB/Cougarpoint. */
1757 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1758 {
1759         struct drm_device *dev = crtc->dev;
1760         struct drm_i915_private *dev_priv = dev->dev_private;
1761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1762         int pipe = intel_crtc->pipe;
1763         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1764         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1765         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1766         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1767         u32 temp, i;
1768
1769         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1770            for train result */
1771         temp = I915_READ(fdi_rx_imr_reg);
1772         temp &= ~FDI_RX_SYMBOL_LOCK;
1773         temp &= ~FDI_RX_BIT_LOCK;
1774         I915_WRITE(fdi_rx_imr_reg, temp);
1775         I915_READ(fdi_rx_imr_reg);
1776         udelay(150);
1777
1778         /* enable CPU FDI TX and PCH FDI RX */
1779         temp = I915_READ(fdi_tx_reg);
1780         temp |= FDI_TX_ENABLE;
1781         temp &= ~(7 << 19);
1782         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1783         temp &= ~FDI_LINK_TRAIN_NONE;
1784         temp |= FDI_LINK_TRAIN_PATTERN_1;
1785         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1786         /* SNB-B */
1787         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1788         I915_WRITE(fdi_tx_reg, temp);
1789         I915_READ(fdi_tx_reg);
1790
1791         temp = I915_READ(fdi_rx_reg);
1792         if (HAS_PCH_CPT(dev)) {
1793                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1794                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1795         } else {
1796                 temp &= ~FDI_LINK_TRAIN_NONE;
1797                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1798         }
1799         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1800         I915_READ(fdi_rx_reg);
1801         udelay(150);
1802
1803         for (i = 0; i < 4; i++ ) {
1804                 temp = I915_READ(fdi_tx_reg);
1805                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1806                 temp |= snb_b_fdi_train_param[i];
1807                 I915_WRITE(fdi_tx_reg, temp);
1808                 udelay(500);
1809
1810                 temp = I915_READ(fdi_rx_iir_reg);
1811                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1812
1813                 if (temp & FDI_RX_BIT_LOCK) {
1814                         I915_WRITE(fdi_rx_iir_reg,
1815                                    temp | FDI_RX_BIT_LOCK);
1816                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1817                         break;
1818                 }
1819         }
1820         if (i == 4)
1821                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1822
1823         /* Train 2 */
1824         temp = I915_READ(fdi_tx_reg);
1825         temp &= ~FDI_LINK_TRAIN_NONE;
1826         temp |= FDI_LINK_TRAIN_PATTERN_2;
1827         if (IS_GEN6(dev)) {
1828                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1829                 /* SNB-B */
1830                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1831         }
1832         I915_WRITE(fdi_tx_reg, temp);
1833
1834         temp = I915_READ(fdi_rx_reg);
1835         if (HAS_PCH_CPT(dev)) {
1836                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1837                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1838         } else {
1839                 temp &= ~FDI_LINK_TRAIN_NONE;
1840                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1841         }
1842         I915_WRITE(fdi_rx_reg, temp);
1843         udelay(150);
1844
1845         for (i = 0; i < 4; i++ ) {
1846                 temp = I915_READ(fdi_tx_reg);
1847                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1848                 temp |= snb_b_fdi_train_param[i];
1849                 I915_WRITE(fdi_tx_reg, temp);
1850                 udelay(500);
1851
1852                 temp = I915_READ(fdi_rx_iir_reg);
1853                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1854
1855                 if (temp & FDI_RX_SYMBOL_LOCK) {
1856                         I915_WRITE(fdi_rx_iir_reg,
1857                                    temp | FDI_RX_SYMBOL_LOCK);
1858                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1859                         break;
1860                 }
1861         }
1862         if (i == 4)
1863                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1864
1865         DRM_DEBUG_KMS("FDI train done.\n");
1866 }
1867
1868 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1869 {
1870         struct drm_device *dev = crtc->dev;
1871         struct drm_i915_private *dev_priv = dev->dev_private;
1872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1873         int pipe = intel_crtc->pipe;
1874         int plane = intel_crtc->plane;
1875         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1876         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1877         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1878         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1879         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1880         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1881         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1882         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1883         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1884         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1885         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1886         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1887         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1888         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1889         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1890         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1891         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1892         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1893         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1894         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1895         u32 temp;
1896         u32 pipe_bpc;
1897
1898         temp = I915_READ(pipeconf_reg);
1899         pipe_bpc = temp & PIPE_BPC_MASK;
1900
1901         /* XXX: When our outputs are all unaware of DPMS modes other than off
1902          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1903          */
1904         switch (mode) {
1905         case DRM_MODE_DPMS_ON:
1906         case DRM_MODE_DPMS_STANDBY:
1907         case DRM_MODE_DPMS_SUSPEND:
1908                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1909
1910                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1911                         temp = I915_READ(PCH_LVDS);
1912                         if ((temp & LVDS_PORT_EN) == 0) {
1913                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1914                                 POSTING_READ(PCH_LVDS);
1915                         }
1916                 }
1917
1918                 if (!HAS_eDP) {
1919
1920                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1921                         temp = I915_READ(fdi_rx_reg);
1922                         /*
1923                          * make the BPC in FDI Rx be consistent with that in
1924                          * pipeconf reg.
1925                          */
1926                         temp &= ~(0x7 << 16);
1927                         temp |= (pipe_bpc << 11);
1928                         temp &= ~(7 << 19);
1929                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1930                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1931                         I915_READ(fdi_rx_reg);
1932                         udelay(200);
1933
1934                         /* Switch from Rawclk to PCDclk */
1935                         temp = I915_READ(fdi_rx_reg);
1936                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1937                         I915_READ(fdi_rx_reg);
1938                         udelay(200);
1939
1940                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1941                         temp = I915_READ(fdi_tx_reg);
1942                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1943                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1944                                 I915_READ(fdi_tx_reg);
1945                                 udelay(100);
1946                         }
1947                 }
1948
1949                 /* Enable panel fitting for LVDS */
1950                 if (dev_priv->pch_pf_size &&
1951                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1952                     || HAS_eDP || intel_pch_has_edp(crtc))) {
1953                         /* Force use of hard-coded filter coefficients
1954                          * as some pre-programmed values are broken,
1955                          * e.g. x201.
1956                          */
1957                         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1958                                    PF_ENABLE | PF_FILTER_MED_3x3);
1959                         I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1960                                    dev_priv->pch_pf_pos);
1961                         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1962                                    dev_priv->pch_pf_size);
1963                 }
1964
1965                 /* Enable CPU pipe */
1966                 temp = I915_READ(pipeconf_reg);
1967                 if ((temp & PIPEACONF_ENABLE) == 0) {
1968                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1969                         I915_READ(pipeconf_reg);
1970                         udelay(100);
1971                 }
1972
1973                 /* configure and enable CPU plane */
1974                 temp = I915_READ(dspcntr_reg);
1975                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1976                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1977                         /* Flush the plane changes */
1978                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1979                 }
1980
1981                 if (!HAS_eDP) {
1982                         /* For PCH output, training FDI link */
1983                         if (IS_GEN6(dev))
1984                                 gen6_fdi_link_train(crtc);
1985                         else
1986                                 ironlake_fdi_link_train(crtc);
1987
1988                         /* enable PCH DPLL */
1989                         temp = I915_READ(pch_dpll_reg);
1990                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1991                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1992                                 I915_READ(pch_dpll_reg);
1993                         }
1994                         udelay(200);
1995
1996                         if (HAS_PCH_CPT(dev)) {
1997                                 /* Be sure PCH DPLL SEL is set */
1998                                 temp = I915_READ(PCH_DPLL_SEL);
1999                                 if (trans_dpll_sel == 0 &&
2000                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2001                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2002                                 else if (trans_dpll_sel == 1 &&
2003                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2004                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2005                                 I915_WRITE(PCH_DPLL_SEL, temp);
2006                                 I915_READ(PCH_DPLL_SEL);
2007                         }
2008
2009                         /* set transcoder timing */
2010                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2011                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2012                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2013
2014                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2015                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2016                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2017
2018                         /* enable normal train */
2019                         temp = I915_READ(fdi_tx_reg);
2020                         temp &= ~FDI_LINK_TRAIN_NONE;
2021                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2022                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2023                         I915_READ(fdi_tx_reg);
2024
2025                         temp = I915_READ(fdi_rx_reg);
2026                         if (HAS_PCH_CPT(dev)) {
2027                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2028                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2029                         } else {
2030                                 temp &= ~FDI_LINK_TRAIN_NONE;
2031                                 temp |= FDI_LINK_TRAIN_NONE;
2032                         }
2033                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2034                         I915_READ(fdi_rx_reg);
2035
2036                         /* wait one idle pattern time */
2037                         udelay(100);
2038
2039                         /* For PCH DP, enable TRANS_DP_CTL */
2040                         if (HAS_PCH_CPT(dev) &&
2041                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2042                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2043                                 int reg;
2044
2045                                 reg = I915_READ(trans_dp_ctl);
2046                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2047                                          TRANS_DP_SYNC_MASK);
2048                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2049                                         TRANS_DP_ENH_FRAMING);
2050
2051                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2052                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2053                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2054                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2055
2056                                 switch (intel_trans_dp_port_sel(crtc)) {
2057                                 case PCH_DP_B:
2058                                         reg |= TRANS_DP_PORT_SEL_B;
2059                                         break;
2060                                 case PCH_DP_C:
2061                                         reg |= TRANS_DP_PORT_SEL_C;
2062                                         break;
2063                                 case PCH_DP_D:
2064                                         reg |= TRANS_DP_PORT_SEL_D;
2065                                         break;
2066                                 default:
2067                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2068                                         reg |= TRANS_DP_PORT_SEL_B;
2069                                         break;
2070                                 }
2071
2072                                 I915_WRITE(trans_dp_ctl, reg);
2073                                 POSTING_READ(trans_dp_ctl);
2074                         }
2075
2076                         /* enable PCH transcoder */
2077                         temp = I915_READ(transconf_reg);
2078                         /*
2079                          * make the BPC in transcoder be consistent with
2080                          * that in pipeconf reg.
2081                          */
2082                         temp &= ~PIPE_BPC_MASK;
2083                         temp |= pipe_bpc;
2084                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2085                         I915_READ(transconf_reg);
2086
2087                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2088                                 DRM_ERROR("failed to enable transcoder\n");
2089                 }
2090
2091                 intel_crtc_load_lut(crtc);
2092
2093                 intel_update_fbc(crtc, &crtc->mode);
2094                 break;
2095
2096         case DRM_MODE_DPMS_OFF:
2097                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2098
2099                 drm_vblank_off(dev, pipe);
2100                 /* Disable display plane */
2101                 temp = I915_READ(dspcntr_reg);
2102                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2103                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2104                         /* Flush the plane changes */
2105                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2106                         I915_READ(dspbase_reg);
2107                 }
2108
2109                 if (dev_priv->cfb_plane == plane &&
2110                     dev_priv->display.disable_fbc)
2111                         dev_priv->display.disable_fbc(dev);
2112
2113                 /* disable cpu pipe, disable after all planes disabled */
2114                 temp = I915_READ(pipeconf_reg);
2115                 if ((temp & PIPEACONF_ENABLE) != 0) {
2116                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2117
2118                         /* wait for cpu pipe off, pipe state */
2119                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2120                                 DRM_ERROR("failed to turn off cpu pipe\n");
2121                 } else
2122                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2123
2124                 udelay(100);
2125
2126                 /* Disable PF */
2127                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2128                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2129
2130                 /* disable CPU FDI tx and PCH FDI rx */
2131                 temp = I915_READ(fdi_tx_reg);
2132                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2133                 I915_READ(fdi_tx_reg);
2134
2135                 temp = I915_READ(fdi_rx_reg);
2136                 /* BPC in FDI rx is consistent with that in pipeconf */
2137                 temp &= ~(0x07 << 16);
2138                 temp |= (pipe_bpc << 11);
2139                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2140                 I915_READ(fdi_rx_reg);
2141
2142                 udelay(100);
2143
2144                 /* still set train pattern 1 */
2145                 temp = I915_READ(fdi_tx_reg);
2146                 temp &= ~FDI_LINK_TRAIN_NONE;
2147                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2148                 I915_WRITE(fdi_tx_reg, temp);
2149                 POSTING_READ(fdi_tx_reg);
2150
2151                 temp = I915_READ(fdi_rx_reg);
2152                 if (HAS_PCH_CPT(dev)) {
2153                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2154                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2155                 } else {
2156                         temp &= ~FDI_LINK_TRAIN_NONE;
2157                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2158                 }
2159                 I915_WRITE(fdi_rx_reg, temp);
2160                 POSTING_READ(fdi_rx_reg);
2161
2162                 udelay(100);
2163
2164                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2165                         temp = I915_READ(PCH_LVDS);
2166                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2167                         I915_READ(PCH_LVDS);
2168                         udelay(100);
2169                 }
2170
2171                 /* disable PCH transcoder */
2172                 temp = I915_READ(transconf_reg);
2173                 if ((temp & TRANS_ENABLE) != 0) {
2174                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2175
2176                         /* wait for PCH transcoder off, transcoder state */
2177                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2178                                 DRM_ERROR("failed to disable transcoder\n");
2179                 }
2180
2181                 temp = I915_READ(transconf_reg);
2182                 /* BPC in transcoder is consistent with that in pipeconf */
2183                 temp &= ~PIPE_BPC_MASK;
2184                 temp |= pipe_bpc;
2185                 I915_WRITE(transconf_reg, temp);
2186                 I915_READ(transconf_reg);
2187                 udelay(100);
2188
2189                 if (HAS_PCH_CPT(dev)) {
2190                         /* disable TRANS_DP_CTL */
2191                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2192                         int reg;
2193
2194                         reg = I915_READ(trans_dp_ctl);
2195                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2196                         I915_WRITE(trans_dp_ctl, reg);
2197                         POSTING_READ(trans_dp_ctl);
2198
2199                         /* disable DPLL_SEL */
2200                         temp = I915_READ(PCH_DPLL_SEL);
2201                         if (trans_dpll_sel == 0)
2202                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2203                         else
2204                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2205                         I915_WRITE(PCH_DPLL_SEL, temp);
2206                         I915_READ(PCH_DPLL_SEL);
2207
2208                 }
2209
2210                 /* disable PCH DPLL */
2211                 temp = I915_READ(pch_dpll_reg);
2212                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2213                 I915_READ(pch_dpll_reg);
2214
2215                 /* Switch from PCDclk to Rawclk */
2216                 temp = I915_READ(fdi_rx_reg);
2217                 temp &= ~FDI_SEL_PCDCLK;
2218                 I915_WRITE(fdi_rx_reg, temp);
2219                 I915_READ(fdi_rx_reg);
2220
2221                 /* Disable CPU FDI TX PLL */
2222                 temp = I915_READ(fdi_tx_reg);
2223                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2224                 I915_READ(fdi_tx_reg);
2225                 udelay(100);
2226
2227                 temp = I915_READ(fdi_rx_reg);
2228                 temp &= ~FDI_RX_PLL_ENABLE;
2229                 I915_WRITE(fdi_rx_reg, temp);
2230                 I915_READ(fdi_rx_reg);
2231
2232                 /* Wait for the clocks to turn off. */
2233                 udelay(100);
2234                 break;
2235         }
2236 }
2237
2238 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2239 {
2240         struct intel_overlay *overlay;
2241         int ret;
2242
2243         if (!enable && intel_crtc->overlay) {
2244                 overlay = intel_crtc->overlay;
2245                 mutex_lock(&overlay->dev->struct_mutex);
2246                 for (;;) {
2247                         ret = intel_overlay_switch_off(overlay);
2248                         if (ret == 0)
2249                                 break;
2250
2251                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2252                         if (ret != 0) {
2253                                 /* overlay doesn't react anymore. Usually
2254                                  * results in a black screen and an unkillable
2255                                  * X server. */
2256                                 BUG();
2257                                 overlay->hw_wedged = HW_WEDGED;
2258                                 break;
2259                         }
2260                 }
2261                 mutex_unlock(&overlay->dev->struct_mutex);
2262         }
2263         /* Let userspace switch the overlay on again. In most cases userspace
2264          * has to recompute where to put it anyway. */
2265
2266         return;
2267 }
2268
2269 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2270 {
2271         struct drm_device *dev = crtc->dev;
2272         struct drm_i915_private *dev_priv = dev->dev_private;
2273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2274         int pipe = intel_crtc->pipe;
2275         int plane = intel_crtc->plane;
2276         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2277         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2278         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2279         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2280         u32 temp;
2281
2282         /* XXX: When our outputs are all unaware of DPMS modes other than off
2283          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2284          */
2285         switch (mode) {
2286         case DRM_MODE_DPMS_ON:
2287         case DRM_MODE_DPMS_STANDBY:
2288         case DRM_MODE_DPMS_SUSPEND:
2289                 /* Enable the DPLL */
2290                 temp = I915_READ(dpll_reg);
2291                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2292                         I915_WRITE(dpll_reg, temp);
2293                         I915_READ(dpll_reg);
2294                         /* Wait for the clocks to stabilize. */
2295                         udelay(150);
2296                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2297                         I915_READ(dpll_reg);
2298                         /* Wait for the clocks to stabilize. */
2299                         udelay(150);
2300                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2301                         I915_READ(dpll_reg);
2302                         /* Wait for the clocks to stabilize. */
2303                         udelay(150);
2304                 }
2305
2306                 /* Enable the pipe */
2307                 temp = I915_READ(pipeconf_reg);
2308                 if ((temp & PIPEACONF_ENABLE) == 0)
2309                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2310
2311                 /* Enable the plane */
2312                 temp = I915_READ(dspcntr_reg);
2313                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2314                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2315                         /* Flush the plane changes */
2316                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2317                 }
2318
2319                 intel_crtc_load_lut(crtc);
2320
2321                 if ((IS_I965G(dev) || plane == 0))
2322                         intel_update_fbc(crtc, &crtc->mode);
2323
2324                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2325                 intel_crtc_dpms_overlay(intel_crtc, true);
2326         break;
2327         case DRM_MODE_DPMS_OFF:
2328                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2329                 intel_crtc_dpms_overlay(intel_crtc, false);
2330                 drm_vblank_off(dev, pipe);
2331
2332                 if (dev_priv->cfb_plane == plane &&
2333                     dev_priv->display.disable_fbc)
2334                         dev_priv->display.disable_fbc(dev);
2335
2336                 /* Disable display plane */
2337                 temp = I915_READ(dspcntr_reg);
2338                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2339                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2340                         /* Flush the plane changes */
2341                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2342                         I915_READ(dspbase_reg);
2343                 }
2344
2345                 /* Don't disable pipe A or pipe A PLLs if needed */
2346                 if (pipeconf_reg == PIPEACONF &&
2347                     (dev_priv->quirks & QUIRK_PIPEA_FORCE)) {
2348                         /* Wait for vblank for the disable to take effect */
2349                         intel_wait_for_vblank(dev, pipe);
2350                         goto skip_pipe_off;
2351                 }
2352
2353                 /* Next, disable display pipes */
2354                 temp = I915_READ(pipeconf_reg);
2355                 if ((temp & PIPEACONF_ENABLE) != 0) {
2356                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2357                         I915_READ(pipeconf_reg);
2358                 }
2359
2360                 /* Wait for the pipe to turn off */
2361                 intel_wait_for_pipe_off(dev, pipe);
2362
2363                 temp = I915_READ(dpll_reg);
2364                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2365                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2366                         I915_READ(dpll_reg);
2367                 }
2368         skip_pipe_off:
2369                 /* Wait for the clocks to turn off. */
2370                 udelay(150);
2371                 break;
2372         }
2373 }
2374
2375 /**
2376  * Sets the power management mode of the pipe and plane.
2377  */
2378 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2379 {
2380         struct drm_device *dev = crtc->dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct drm_i915_master_private *master_priv;
2383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2384         int pipe = intel_crtc->pipe;
2385         bool enabled;
2386
2387         if (intel_crtc->dpms_mode == mode)
2388                 return;
2389
2390         intel_crtc->dpms_mode = mode;
2391         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2392
2393         /* When switching on the display, ensure that SR is disabled
2394          * with multiple pipes prior to enabling to new pipe.
2395          *
2396          * When switching off the display, make sure the cursor is
2397          * properly hidden prior to disabling the pipe.
2398          */
2399         if (mode == DRM_MODE_DPMS_ON)
2400                 intel_update_watermarks(dev);
2401         else
2402                 intel_crtc_update_cursor(crtc);
2403
2404         dev_priv->display.dpms(crtc, mode);
2405
2406         if (mode == DRM_MODE_DPMS_ON)
2407                 intel_crtc_update_cursor(crtc);
2408         else
2409                 intel_update_watermarks(dev);
2410
2411         if (!dev->primary->master)
2412                 return;
2413
2414         master_priv = dev->primary->master->driver_priv;
2415         if (!master_priv->sarea_priv)
2416                 return;
2417
2418         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2419
2420         switch (pipe) {
2421         case 0:
2422                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2423                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2424                 break;
2425         case 1:
2426                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2427                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2428                 break;
2429         default:
2430                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2431                 break;
2432         }
2433 }
2434
2435 static void intel_crtc_prepare (struct drm_crtc *crtc)
2436 {
2437         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2438         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2439 }
2440
2441 static void intel_crtc_commit (struct drm_crtc *crtc)
2442 {
2443         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2444         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2445 }
2446
2447 void intel_encoder_prepare (struct drm_encoder *encoder)
2448 {
2449         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2450         /* lvds has its own version of prepare see intel_lvds_prepare */
2451         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2452 }
2453
2454 void intel_encoder_commit (struct drm_encoder *encoder)
2455 {
2456         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2457         /* lvds has its own version of commit see intel_lvds_commit */
2458         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2459 }
2460
2461 void intel_encoder_destroy(struct drm_encoder *encoder)
2462 {
2463         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2464
2465         if (intel_encoder->ddc_bus)
2466                 intel_i2c_destroy(intel_encoder->ddc_bus);
2467
2468         if (intel_encoder->i2c_bus)
2469                 intel_i2c_destroy(intel_encoder->i2c_bus);
2470
2471         drm_encoder_cleanup(encoder);
2472         kfree(intel_encoder);
2473 }
2474
2475 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2476                                   struct drm_display_mode *mode,
2477                                   struct drm_display_mode *adjusted_mode)
2478 {
2479         struct drm_device *dev = crtc->dev;
2480
2481         if (HAS_PCH_SPLIT(dev)) {
2482                 /* FDI link clock is fixed at 2.7G */
2483                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2484                         return false;
2485         }
2486
2487         /* XXX some encoders set the crtcinfo, others don't.
2488          * Obviously we need some form of conflict resolution here...
2489          */
2490         if (adjusted_mode->crtc_htotal == 0)
2491                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2492
2493         return true;
2494 }
2495
2496 static int i945_get_display_clock_speed(struct drm_device *dev)
2497 {
2498         return 400000;
2499 }
2500
2501 static int i915_get_display_clock_speed(struct drm_device *dev)
2502 {
2503         return 333000;
2504 }
2505
2506 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2507 {
2508         return 200000;
2509 }
2510
2511 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2512 {
2513         u16 gcfgc = 0;
2514
2515         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2516
2517         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2518                 return 133000;
2519         else {
2520                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2521                 case GC_DISPLAY_CLOCK_333_MHZ:
2522                         return 333000;
2523                 default:
2524                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2525                         return 190000;
2526                 }
2527         }
2528 }
2529
2530 static int i865_get_display_clock_speed(struct drm_device *dev)
2531 {
2532         return 266000;
2533 }
2534
2535 static int i855_get_display_clock_speed(struct drm_device *dev)
2536 {
2537         u16 hpllcc = 0;
2538         /* Assume that the hardware is in the high speed state.  This
2539          * should be the default.
2540          */
2541         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2542         case GC_CLOCK_133_200:
2543         case GC_CLOCK_100_200:
2544                 return 200000;
2545         case GC_CLOCK_166_250:
2546                 return 250000;
2547         case GC_CLOCK_100_133:
2548                 return 133000;
2549         }
2550
2551         /* Shouldn't happen */
2552         return 0;
2553 }
2554
2555 static int i830_get_display_clock_speed(struct drm_device *dev)
2556 {
2557         return 133000;
2558 }
2559
2560 /**
2561  * Return the pipe currently connected to the panel fitter,
2562  * or -1 if the panel fitter is not present or not in use
2563  */
2564 int intel_panel_fitter_pipe (struct drm_device *dev)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         u32  pfit_control;
2568
2569         /* i830 doesn't have a panel fitter */
2570         if (IS_I830(dev))
2571                 return -1;
2572
2573         pfit_control = I915_READ(PFIT_CONTROL);
2574
2575         /* See if the panel fitter is in use */
2576         if ((pfit_control & PFIT_ENABLE) == 0)
2577                 return -1;
2578
2579         /* 965 can place panel fitter on either pipe */
2580         if (IS_I965G(dev))
2581                 return (pfit_control >> 29) & 0x3;
2582
2583         /* older chips can only use pipe 1 */
2584         return 1;
2585 }
2586
2587 struct fdi_m_n {
2588         u32        tu;
2589         u32        gmch_m;
2590         u32        gmch_n;
2591         u32        link_m;
2592         u32        link_n;
2593 };
2594
2595 static void
2596 fdi_reduce_ratio(u32 *num, u32 *den)
2597 {
2598         while (*num > 0xffffff || *den > 0xffffff) {
2599                 *num >>= 1;
2600                 *den >>= 1;
2601         }
2602 }
2603
2604 #define DATA_N 0x800000
2605 #define LINK_N 0x80000
2606
2607 static void
2608 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2609                      int link_clock, struct fdi_m_n *m_n)
2610 {
2611         u64 temp;
2612
2613         m_n->tu = 64; /* default size */
2614
2615         temp = (u64) DATA_N * pixel_clock;
2616         temp = div_u64(temp, link_clock);
2617         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2618         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2619         m_n->gmch_n = DATA_N;
2620         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2621
2622         temp = (u64) LINK_N * pixel_clock;
2623         m_n->link_m = div_u64(temp, link_clock);
2624         m_n->link_n = LINK_N;
2625         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2626 }
2627
2628
2629 struct intel_watermark_params {
2630         unsigned long fifo_size;
2631         unsigned long max_wm;
2632         unsigned long default_wm;
2633         unsigned long guard_size;
2634         unsigned long cacheline_size;
2635 };
2636
2637 /* Pineview has different values for various configs */
2638 static struct intel_watermark_params pineview_display_wm = {
2639         PINEVIEW_DISPLAY_FIFO,
2640         PINEVIEW_MAX_WM,
2641         PINEVIEW_DFT_WM,
2642         PINEVIEW_GUARD_WM,
2643         PINEVIEW_FIFO_LINE_SIZE
2644 };
2645 static struct intel_watermark_params pineview_display_hplloff_wm = {
2646         PINEVIEW_DISPLAY_FIFO,
2647         PINEVIEW_MAX_WM,
2648         PINEVIEW_DFT_HPLLOFF_WM,
2649         PINEVIEW_GUARD_WM,
2650         PINEVIEW_FIFO_LINE_SIZE
2651 };
2652 static struct intel_watermark_params pineview_cursor_wm = {
2653         PINEVIEW_CURSOR_FIFO,
2654         PINEVIEW_CURSOR_MAX_WM,
2655         PINEVIEW_CURSOR_DFT_WM,
2656         PINEVIEW_CURSOR_GUARD_WM,
2657         PINEVIEW_FIFO_LINE_SIZE,
2658 };
2659 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2660         PINEVIEW_CURSOR_FIFO,
2661         PINEVIEW_CURSOR_MAX_WM,
2662         PINEVIEW_CURSOR_DFT_WM,
2663         PINEVIEW_CURSOR_GUARD_WM,
2664         PINEVIEW_FIFO_LINE_SIZE
2665 };
2666 static struct intel_watermark_params g4x_wm_info = {
2667         G4X_FIFO_SIZE,
2668         G4X_MAX_WM,
2669         G4X_MAX_WM,
2670         2,
2671         G4X_FIFO_LINE_SIZE,
2672 };
2673 static struct intel_watermark_params g4x_cursor_wm_info = {
2674         I965_CURSOR_FIFO,
2675         I965_CURSOR_MAX_WM,
2676         I965_CURSOR_DFT_WM,
2677         2,
2678         G4X_FIFO_LINE_SIZE,
2679 };
2680 static struct intel_watermark_params i965_cursor_wm_info = {
2681         I965_CURSOR_FIFO,
2682         I965_CURSOR_MAX_WM,
2683         I965_CURSOR_DFT_WM,
2684         2,
2685         I915_FIFO_LINE_SIZE,
2686 };
2687 static struct intel_watermark_params i945_wm_info = {
2688         I945_FIFO_SIZE,
2689         I915_MAX_WM,
2690         1,
2691         2,
2692         I915_FIFO_LINE_SIZE
2693 };
2694 static struct intel_watermark_params i915_wm_info = {
2695         I915_FIFO_SIZE,
2696         I915_MAX_WM,
2697         1,
2698         2,
2699         I915_FIFO_LINE_SIZE
2700 };
2701 static struct intel_watermark_params i855_wm_info = {
2702         I855GM_FIFO_SIZE,
2703         I915_MAX_WM,
2704         1,
2705         2,
2706         I830_FIFO_LINE_SIZE
2707 };
2708 static struct intel_watermark_params i830_wm_info = {
2709         I830_FIFO_SIZE,
2710         I915_MAX_WM,
2711         1,
2712         2,
2713         I830_FIFO_LINE_SIZE
2714 };
2715
2716 static struct intel_watermark_params ironlake_display_wm_info = {
2717         ILK_DISPLAY_FIFO,
2718         ILK_DISPLAY_MAXWM,
2719         ILK_DISPLAY_DFTWM,
2720         2,
2721         ILK_FIFO_LINE_SIZE
2722 };
2723
2724 static struct intel_watermark_params ironlake_cursor_wm_info = {
2725         ILK_CURSOR_FIFO,
2726         ILK_CURSOR_MAXWM,
2727         ILK_CURSOR_DFTWM,
2728         2,
2729         ILK_FIFO_LINE_SIZE
2730 };
2731
2732 static struct intel_watermark_params ironlake_display_srwm_info = {
2733         ILK_DISPLAY_SR_FIFO,
2734         ILK_DISPLAY_MAX_SRWM,
2735         ILK_DISPLAY_DFT_SRWM,
2736         2,
2737         ILK_FIFO_LINE_SIZE
2738 };
2739
2740 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2741         ILK_CURSOR_SR_FIFO,
2742         ILK_CURSOR_MAX_SRWM,
2743         ILK_CURSOR_DFT_SRWM,
2744         2,
2745         ILK_FIFO_LINE_SIZE
2746 };
2747
2748 /**
2749  * intel_calculate_wm - calculate watermark level
2750  * @clock_in_khz: pixel clock
2751  * @wm: chip FIFO params
2752  * @pixel_size: display pixel size
2753  * @latency_ns: memory latency for the platform
2754  *
2755  * Calculate the watermark level (the level at which the display plane will
2756  * start fetching from memory again).  Each chip has a different display
2757  * FIFO size and allocation, so the caller needs to figure that out and pass
2758  * in the correct intel_watermark_params structure.
2759  *
2760  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2761  * on the pixel size.  When it reaches the watermark level, it'll start
2762  * fetching FIFO line sized based chunks from memory until the FIFO fills
2763  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2764  * will occur, and a display engine hang could result.
2765  */
2766 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2767                                         struct intel_watermark_params *wm,
2768                                         int pixel_size,
2769                                         unsigned long latency_ns)
2770 {
2771         long entries_required, wm_size;
2772
2773         /*
2774          * Note: we need to make sure we don't overflow for various clock &
2775          * latency values.
2776          * clocks go from a few thousand to several hundred thousand.
2777          * latency is usually a few thousand
2778          */
2779         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2780                 1000;
2781         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2782
2783         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2784
2785         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2786
2787         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2788
2789         /* Don't promote wm_size to unsigned... */
2790         if (wm_size > (long)wm->max_wm)
2791                 wm_size = wm->max_wm;
2792         if (wm_size <= 0)
2793                 wm_size = wm->default_wm;
2794         return wm_size;
2795 }
2796
2797 struct cxsr_latency {
2798         int is_desktop;
2799         int is_ddr3;
2800         unsigned long fsb_freq;
2801         unsigned long mem_freq;
2802         unsigned long display_sr;
2803         unsigned long display_hpll_disable;
2804         unsigned long cursor_sr;
2805         unsigned long cursor_hpll_disable;
2806 };
2807
2808 static const struct cxsr_latency cxsr_latency_table[] = {
2809         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2810         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2811         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2812         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2813         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2814
2815         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2816         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2817         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2818         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2819         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2820
2821         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2822         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2823         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2824         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2825         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2826
2827         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2828         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2829         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2830         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2831         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2832
2833         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2834         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2835         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2836         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2837         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2838
2839         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2840         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2841         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2842         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2843         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2844 };
2845
2846 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2847                                                          int is_ddr3,
2848                                                          int fsb,
2849                                                          int mem)
2850 {
2851         const struct cxsr_latency *latency;
2852         int i;
2853
2854         if (fsb == 0 || mem == 0)
2855                 return NULL;
2856
2857         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2858                 latency = &cxsr_latency_table[i];
2859                 if (is_desktop == latency->is_desktop &&
2860                     is_ddr3 == latency->is_ddr3 &&
2861                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2862                         return latency;
2863         }
2864
2865         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2866
2867         return NULL;
2868 }
2869
2870 static void pineview_disable_cxsr(struct drm_device *dev)
2871 {
2872         struct drm_i915_private *dev_priv = dev->dev_private;
2873
2874         /* deactivate cxsr */
2875         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2876 }
2877
2878 /*
2879  * Latency for FIFO fetches is dependent on several factors:
2880  *   - memory configuration (speed, channels)
2881  *   - chipset
2882  *   - current MCH state
2883  * It can be fairly high in some situations, so here we assume a fairly
2884  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2885  * set this value too high, the FIFO will fetch frequently to stay full)
2886  * and power consumption (set it too low to save power and we might see
2887  * FIFO underruns and display "flicker").
2888  *
2889  * A value of 5us seems to be a good balance; safe for very low end
2890  * platforms but not overly aggressive on lower latency configs.
2891  */
2892 static const int latency_ns = 5000;
2893
2894 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2895 {
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         uint32_t dsparb = I915_READ(DSPARB);
2898         int size;
2899
2900         size = dsparb & 0x7f;
2901         if (plane)
2902                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2903
2904         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2905                         plane ? "B" : "A", size);
2906
2907         return size;
2908 }
2909
2910 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2911 {
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         uint32_t dsparb = I915_READ(DSPARB);
2914         int size;
2915
2916         size = dsparb & 0x1ff;
2917         if (plane)
2918                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2919         size >>= 1; /* Convert to cachelines */
2920
2921         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2922                         plane ? "B" : "A", size);
2923
2924         return size;
2925 }
2926
2927 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2928 {
2929         struct drm_i915_private *dev_priv = dev->dev_private;
2930         uint32_t dsparb = I915_READ(DSPARB);
2931         int size;
2932
2933         size = dsparb & 0x7f;
2934         size >>= 2; /* Convert to cachelines */
2935
2936         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2937                         plane ? "B" : "A",
2938                   size);
2939
2940         return size;
2941 }
2942
2943 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2944 {
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         uint32_t dsparb = I915_READ(DSPARB);
2947         int size;
2948
2949         size = dsparb & 0x7f;
2950         size >>= 1; /* Convert to cachelines */
2951
2952         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2953                         plane ? "B" : "A", size);
2954
2955         return size;
2956 }
2957
2958 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2959                           int planeb_clock, int sr_hdisplay, int unused,
2960                           int pixel_size)
2961 {
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         const struct cxsr_latency *latency;
2964         u32 reg;
2965         unsigned long wm;
2966         int sr_clock;
2967
2968         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2969                                          dev_priv->fsb_freq, dev_priv->mem_freq);
2970         if (!latency) {
2971                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2972                 pineview_disable_cxsr(dev);
2973                 return;
2974         }
2975
2976         if (!planea_clock || !planeb_clock) {
2977                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2978
2979                 /* Display SR */
2980                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2981                                         pixel_size, latency->display_sr);
2982                 reg = I915_READ(DSPFW1);
2983                 reg &= ~DSPFW_SR_MASK;
2984                 reg |= wm << DSPFW_SR_SHIFT;
2985                 I915_WRITE(DSPFW1, reg);
2986                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2987
2988                 /* cursor SR */
2989                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2990                                         pixel_size, latency->cursor_sr);
2991                 reg = I915_READ(DSPFW3);
2992                 reg &= ~DSPFW_CURSOR_SR_MASK;
2993                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2994                 I915_WRITE(DSPFW3, reg);
2995
2996                 /* Display HPLL off SR */
2997                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2998                                         pixel_size, latency->display_hpll_disable);
2999                 reg = I915_READ(DSPFW3);
3000                 reg &= ~DSPFW_HPLL_SR_MASK;
3001                 reg |= wm & DSPFW_HPLL_SR_MASK;
3002                 I915_WRITE(DSPFW3, reg);
3003
3004                 /* cursor HPLL off SR */
3005                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3006                                         pixel_size, latency->cursor_hpll_disable);
3007                 reg = I915_READ(DSPFW3);
3008                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3009                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3010                 I915_WRITE(DSPFW3, reg);
3011                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3012
3013                 /* activate cxsr */
3014                 I915_WRITE(DSPFW3,
3015                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3016                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3017         } else {
3018                 pineview_disable_cxsr(dev);
3019                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3020         }
3021 }
3022
3023 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3024                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3025                           int pixel_size)
3026 {
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         int total_size, cacheline_size;
3029         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3030         struct intel_watermark_params planea_params, planeb_params;
3031         unsigned long line_time_us;
3032         int sr_clock, sr_entries = 0, entries_required;
3033
3034         /* Create copies of the base settings for each pipe */
3035         planea_params = planeb_params = g4x_wm_info;
3036
3037         /* Grab a couple of global values before we overwrite them */
3038         total_size = planea_params.fifo_size;
3039         cacheline_size = planea_params.cacheline_size;
3040
3041         /*
3042          * Note: we need to make sure we don't overflow for various clock &
3043          * latency values.
3044          * clocks go from a few thousand to several hundred thousand.
3045          * latency is usually a few thousand
3046          */
3047         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3048                 1000;
3049         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3050         planea_wm = entries_required + planea_params.guard_size;
3051
3052         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3053                 1000;
3054         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3055         planeb_wm = entries_required + planeb_params.guard_size;
3056
3057         cursora_wm = cursorb_wm = 16;
3058         cursor_sr = 32;
3059
3060         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3061
3062         /* Calc sr entries for one plane configs */
3063         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3064                 /* self-refresh has much higher latency */
3065                 static const int sr_latency_ns = 12000;
3066
3067                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3068                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3069
3070                 /* Use ns/us then divide to preserve precision */
3071                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3072                               pixel_size * sr_hdisplay;
3073                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3074
3075                 entries_required = (((sr_latency_ns / line_time_us) +
3076                                      1000) / 1000) * pixel_size * 64;
3077                 entries_required = DIV_ROUND_UP(entries_required,
3078                                            g4x_cursor_wm_info.cacheline_size);
3079                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3080
3081                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3082                         cursor_sr = g4x_cursor_wm_info.max_wm;
3083                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3084                               "cursor %d\n", sr_entries, cursor_sr);
3085
3086                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3087         } else {
3088                 /* Turn off self refresh if both pipes are enabled */
3089                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3090                                         & ~FW_BLC_SELF_EN);
3091         }
3092
3093         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3094                   planea_wm, planeb_wm, sr_entries);
3095
3096         planea_wm &= 0x3f;
3097         planeb_wm &= 0x3f;
3098
3099         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3100                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3101                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3102         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3103                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3104         /* HPLL off in SR has some issues on G4x... disable it */
3105         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3106                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3107 }
3108
3109 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3110                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3111                            int pixel_size)
3112 {
3113         struct drm_i915_private *dev_priv = dev->dev_private;
3114         unsigned long line_time_us;
3115         int sr_clock, sr_entries, srwm = 1;
3116         int cursor_sr = 16;
3117
3118         /* Calc sr entries for one plane configs */
3119         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3120                 /* self-refresh has much higher latency */
3121                 static const int sr_latency_ns = 12000;
3122
3123                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3124                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3125
3126                 /* Use ns/us then divide to preserve precision */
3127                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3128                               pixel_size * sr_hdisplay;
3129                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3130                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3131                 srwm = I965_FIFO_SIZE - sr_entries;
3132                 if (srwm < 0)
3133                         srwm = 1;
3134                 srwm &= 0x1ff;
3135
3136                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3137                              pixel_size * 64;
3138                 sr_entries = DIV_ROUND_UP(sr_entries,
3139                                           i965_cursor_wm_info.cacheline_size);
3140                 cursor_sr = i965_cursor_wm_info.fifo_size -
3141                             (sr_entries + i965_cursor_wm_info.guard_size);
3142
3143                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3144                         cursor_sr = i965_cursor_wm_info.max_wm;
3145
3146                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3147                               "cursor %d\n", srwm, cursor_sr);
3148
3149                 if (IS_I965GM(dev))
3150                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3151         } else {
3152                 /* Turn off self refresh if both pipes are enabled */
3153                 if (IS_I965GM(dev))
3154                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3155                                    & ~FW_BLC_SELF_EN);
3156         }
3157
3158         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3159                       srwm);
3160
3161         /* 965 has limitations... */
3162         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3163                    (8 << 0));
3164         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3165         /* update cursor SR watermark */
3166         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3167 }
3168
3169 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3170                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3171                            int pixel_size)
3172 {
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         uint32_t fwater_lo;
3175         uint32_t fwater_hi;
3176         int total_size, cacheline_size, cwm, srwm = 1;
3177         int planea_wm, planeb_wm;
3178         struct intel_watermark_params planea_params, planeb_params;
3179         unsigned long line_time_us;
3180         int sr_clock, sr_entries = 0;
3181
3182         /* Create copies of the base settings for each pipe */
3183         if (IS_I965GM(dev) || IS_I945GM(dev))
3184                 planea_params = planeb_params = i945_wm_info;
3185         else if (IS_I9XX(dev))
3186                 planea_params = planeb_params = i915_wm_info;
3187         else
3188                 planea_params = planeb_params = i855_wm_info;
3189
3190         /* Grab a couple of global values before we overwrite them */
3191         total_size = planea_params.fifo_size;
3192         cacheline_size = planea_params.cacheline_size;
3193
3194         /* Update per-plane FIFO sizes */
3195         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3196         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3197
3198         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3199                                        pixel_size, latency_ns);
3200         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3201                                        pixel_size, latency_ns);
3202         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3203
3204         /*
3205          * Overlay gets an aggressive default since video jitter is bad.
3206          */
3207         cwm = 2;
3208
3209         /* Calc sr entries for one plane configs */
3210         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3211             (!planea_clock || !planeb_clock)) {
3212                 /* self-refresh has much higher latency */
3213                 static const int sr_latency_ns = 6000;
3214
3215                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3216                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3217
3218                 /* Use ns/us then divide to preserve precision */
3219                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3220                               pixel_size * sr_hdisplay;
3221                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3222                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3223                 srwm = total_size - sr_entries;
3224                 if (srwm < 0)
3225                         srwm = 1;
3226
3227                 if (IS_I945G(dev) || IS_I945GM(dev))
3228                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3229                 else if (IS_I915GM(dev)) {
3230                         /* 915M has a smaller SRWM field */
3231                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3232                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3233                 }
3234         } else {
3235                 /* Turn off self refresh if both pipes are enabled */
3236                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3237                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3238                                    & ~FW_BLC_SELF_EN);
3239                 } else if (IS_I915GM(dev)) {
3240                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3241                 }
3242         }
3243
3244         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3245                   planea_wm, planeb_wm, cwm, srwm);
3246
3247         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3248         fwater_hi = (cwm & 0x1f);
3249
3250         /* Set request length to 8 cachelines per fetch */
3251         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3252         fwater_hi = fwater_hi | (1 << 8);
3253
3254         I915_WRITE(FW_BLC, fwater_lo);
3255         I915_WRITE(FW_BLC2, fwater_hi);
3256 }
3257
3258 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3259                            int unused2, int unused3, int pixel_size)
3260 {
3261         struct drm_i915_private *dev_priv = dev->dev_private;
3262         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3263         int planea_wm;
3264
3265         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3266
3267         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3268                                        pixel_size, latency_ns);
3269         fwater_lo |= (3<<8) | planea_wm;
3270
3271         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3272
3273         I915_WRITE(FW_BLC, fwater_lo);
3274 }
3275
3276 #define ILK_LP0_PLANE_LATENCY           700
3277 #define ILK_LP0_CURSOR_LATENCY          1300
3278
3279 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3280                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3281                        int pixel_size)
3282 {
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3285         int sr_wm, cursor_wm;
3286         unsigned long line_time_us;
3287         int sr_clock, entries_required;
3288         u32 reg_value;
3289         int line_count;
3290         int planea_htotal = 0, planeb_htotal = 0;
3291         struct drm_crtc *crtc;
3292
3293         /* Need htotal for all active display plane */
3294         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3295                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3297                         if (intel_crtc->plane == 0)
3298                                 planea_htotal = crtc->mode.htotal;
3299                         else
3300                                 planeb_htotal = crtc->mode.htotal;
3301                 }
3302         }
3303
3304         /* Calculate and update the watermark for plane A */
3305         if (planea_clock) {
3306                 entries_required = ((planea_clock / 1000) * pixel_size *
3307                                      ILK_LP0_PLANE_LATENCY) / 1000;
3308                 entries_required = DIV_ROUND_UP(entries_required,
3309                                                 ironlake_display_wm_info.cacheline_size);
3310                 planea_wm = entries_required +
3311                             ironlake_display_wm_info.guard_size;
3312
3313                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3314                         planea_wm = ironlake_display_wm_info.max_wm;
3315
3316                 /* Use the large buffer method to calculate cursor watermark */
3317                 line_time_us = (planea_htotal * 1000) / planea_clock;
3318
3319                 /* Use ns/us then divide to preserve precision */
3320                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3321
3322                 /* calculate the cursor watermark for cursor A */
3323                 entries_required = line_count * 64 * pixel_size;
3324                 entries_required = DIV_ROUND_UP(entries_required,
3325                                                 ironlake_cursor_wm_info.cacheline_size);
3326                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3327                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3328                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3329
3330                 reg_value = I915_READ(WM0_PIPEA_ILK);
3331                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3332                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3333                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3334                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3335                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3336                                 "cursor: %d\n", planea_wm, cursora_wm);
3337         }
3338         /* Calculate and update the watermark for plane B */
3339         if (planeb_clock) {
3340                 entries_required = ((planeb_clock / 1000) * pixel_size *
3341                                      ILK_LP0_PLANE_LATENCY) / 1000;
3342                 entries_required = DIV_ROUND_UP(entries_required,
3343                                                 ironlake_display_wm_info.cacheline_size);
3344                 planeb_wm = entries_required +
3345                             ironlake_display_wm_info.guard_size;
3346
3347                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3348                         planeb_wm = ironlake_display_wm_info.max_wm;
3349
3350                 /* Use the large buffer method to calculate cursor watermark */
3351                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3352
3353                 /* Use ns/us then divide to preserve precision */
3354                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3355
3356                 /* calculate the cursor watermark for cursor B */
3357                 entries_required = line_count * 64 * pixel_size;
3358                 entries_required = DIV_ROUND_UP(entries_required,
3359                                                 ironlake_cursor_wm_info.cacheline_size);
3360                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3361                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3362                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3363
3364                 reg_value = I915_READ(WM0_PIPEB_ILK);
3365                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3366                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3367                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3368                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3369                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3370                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3371         }
3372
3373         /*
3374          * Calculate and update the self-refresh watermark only when one
3375          * display plane is used.
3376          */
3377         if (!planea_clock || !planeb_clock) {
3378
3379                 /* Read the self-refresh latency. The unit is 0.5us */
3380                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3381
3382                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3383                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3384
3385                 /* Use ns/us then divide to preserve precision */
3386                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3387                                / 1000;
3388
3389                 /* calculate the self-refresh watermark for display plane */
3390                 entries_required = line_count * sr_hdisplay * pixel_size;
3391                 entries_required = DIV_ROUND_UP(entries_required,
3392                                                 ironlake_display_srwm_info.cacheline_size);
3393                 sr_wm = entries_required +
3394                         ironlake_display_srwm_info.guard_size;
3395
3396                 /* calculate the self-refresh watermark for display cursor */
3397                 entries_required = line_count * pixel_size * 64;
3398                 entries_required = DIV_ROUND_UP(entries_required,
3399                                                 ironlake_cursor_srwm_info.cacheline_size);
3400                 cursor_wm = entries_required +
3401                             ironlake_cursor_srwm_info.guard_size;
3402
3403                 /* configure watermark and enable self-refresh */
3404                 reg_value = I915_READ(WM1_LP_ILK);
3405                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3406                                WM1_LP_CURSOR_MASK);
3407                 reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3408                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3409
3410                 I915_WRITE(WM1_LP_ILK, reg_value);
3411                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3412                                 "cursor %d\n", sr_wm, cursor_wm);
3413
3414         } else {
3415                 /* Turn off self refresh if both pipes are enabled */
3416                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3417         }
3418 }
3419 /**
3420  * intel_update_watermarks - update FIFO watermark values based on current modes
3421  *
3422  * Calculate watermark values for the various WM regs based on current mode
3423  * and plane configuration.
3424  *
3425  * There are several cases to deal with here:
3426  *   - normal (i.e. non-self-refresh)
3427  *   - self-refresh (SR) mode
3428  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3429  *   - lines are small relative to FIFO size (buffer can hold more than 2
3430  *     lines), so need to account for TLB latency
3431  *
3432  *   The normal calculation is:
3433  *     watermark = dotclock * bytes per pixel * latency
3434  *   where latency is platform & configuration dependent (we assume pessimal
3435  *   values here).
3436  *
3437  *   The SR calculation is:
3438  *     watermark = (trunc(latency/line time)+1) * surface width *
3439  *       bytes per pixel
3440  *   where
3441  *     line time = htotal / dotclock
3442  *     surface width = hdisplay for normal plane and 64 for cursor
3443  *   and latency is assumed to be high, as above.
3444  *
3445  * The final value programmed to the register should always be rounded up,
3446  * and include an extra 2 entries to account for clock crossings.
3447  *
3448  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3449  * to set the non-SR watermarks to 8.
3450   */
3451 static void intel_update_watermarks(struct drm_device *dev)
3452 {
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         struct drm_crtc *crtc;
3455         int sr_hdisplay = 0;
3456         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3457         int enabled = 0, pixel_size = 0;
3458         int sr_htotal = 0;
3459
3460         if (!dev_priv->display.update_wm)
3461                 return;
3462
3463         /* Get the clock config from both planes */
3464         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3465                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3466                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3467                         enabled++;
3468                         if (intel_crtc->plane == 0) {
3469                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3470                                           intel_crtc->pipe, crtc->mode.clock);
3471                                 planea_clock = crtc->mode.clock;
3472                         } else {
3473                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3474                                           intel_crtc->pipe, crtc->mode.clock);
3475                                 planeb_clock = crtc->mode.clock;
3476                         }
3477                         sr_hdisplay = crtc->mode.hdisplay;
3478                         sr_clock = crtc->mode.clock;
3479                         sr_htotal = crtc->mode.htotal;
3480                         if (crtc->fb)
3481                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3482                         else
3483                                 pixel_size = 4; /* by default */
3484                 }
3485         }
3486
3487         if (enabled <= 0)
3488                 return;
3489
3490         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3491                                     sr_hdisplay, sr_htotal, pixel_size);
3492 }
3493
3494 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3495                                struct drm_display_mode *mode,
3496                                struct drm_display_mode *adjusted_mode,
3497                                int x, int y,
3498                                struct drm_framebuffer *old_fb)
3499 {
3500         struct drm_device *dev = crtc->dev;
3501         struct drm_i915_private *dev_priv = dev->dev_private;
3502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3503         int pipe = intel_crtc->pipe;
3504         int plane = intel_crtc->plane;
3505         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3506         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3507         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3508         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3509         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3510         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3511         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3512         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3513         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3514         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3515         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3516         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3517         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3518         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3519         int refclk, num_connectors = 0;
3520         intel_clock_t clock, reduced_clock;
3521         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3522         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3523         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3524         struct intel_encoder *has_edp_encoder = NULL;
3525         struct drm_mode_config *mode_config = &dev->mode_config;
3526         struct drm_encoder *encoder;
3527         const intel_limit_t *limit;
3528         int ret;
3529         struct fdi_m_n m_n = {0};
3530         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3531         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3532         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3533         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3534         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3535         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3536         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3537         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3538         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3539         int lvds_reg = LVDS;
3540         u32 temp;
3541         int sdvo_pixel_multiply;
3542         int target_clock;
3543
3544         drm_vblank_pre_modeset(dev, pipe);
3545
3546         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3547                 struct intel_encoder *intel_encoder;
3548
3549                 if (encoder->crtc != crtc)
3550                         continue;
3551
3552                 intel_encoder = enc_to_intel_encoder(encoder);
3553                 switch (intel_encoder->type) {
3554                 case INTEL_OUTPUT_LVDS:
3555                         is_lvds = true;
3556                         break;
3557                 case INTEL_OUTPUT_SDVO:
3558                 case INTEL_OUTPUT_HDMI:
3559                         is_sdvo = true;
3560                         if (intel_encoder->needs_tv_clock)
3561                                 is_tv = true;
3562                         break;
3563                 case INTEL_OUTPUT_DVO:
3564                         is_dvo = true;
3565                         break;
3566                 case INTEL_OUTPUT_TVOUT:
3567                         is_tv = true;
3568                         break;
3569                 case INTEL_OUTPUT_ANALOG:
3570                         is_crt = true;
3571                         break;
3572                 case INTEL_OUTPUT_DISPLAYPORT:
3573                         is_dp = true;
3574                         break;
3575                 case INTEL_OUTPUT_EDP:
3576                         has_edp_encoder = intel_encoder;
3577                         break;
3578                 }
3579
3580                 num_connectors++;
3581         }
3582
3583         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3584                 refclk = dev_priv->lvds_ssc_freq * 1000;
3585                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3586                                         refclk / 1000);
3587         } else if (IS_I9XX(dev)) {
3588                 refclk = 96000;
3589                 if (HAS_PCH_SPLIT(dev))
3590                         refclk = 120000; /* 120Mhz refclk */
3591         } else {
3592                 refclk = 48000;
3593         }
3594
3595
3596         /*
3597          * Returns a set of divisors for the desired target clock with the given
3598          * refclk, or FALSE.  The returned values represent the clock equation:
3599          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3600          */
3601         limit = intel_limit(crtc);
3602         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3603         if (!ok) {
3604                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3605                 drm_vblank_post_modeset(dev, pipe);
3606                 return -EINVAL;
3607         }
3608
3609         /* Ensure that the cursor is valid for the new mode before changing... */
3610         intel_crtc_update_cursor(crtc);
3611
3612         if (is_lvds && dev_priv->lvds_downclock_avail) {
3613                 has_reduced_clock = limit->find_pll(limit, crtc,
3614                                                             dev_priv->lvds_downclock,
3615                                                             refclk,
3616                                                             &reduced_clock);
3617                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3618                         /*
3619                          * If the different P is found, it means that we can't
3620                          * switch the display clock by using the FP0/FP1.
3621                          * In such case we will disable the LVDS downclock
3622                          * feature.
3623                          */
3624                         DRM_DEBUG_KMS("Different P is found for "
3625                                                 "LVDS clock/downclock\n");
3626                         has_reduced_clock = 0;
3627                 }
3628         }
3629         /* SDVO TV has fixed PLL values depend on its clock range,
3630            this mirrors vbios setting. */
3631         if (is_sdvo && is_tv) {
3632                 if (adjusted_mode->clock >= 100000
3633                                 && adjusted_mode->clock < 140500) {
3634                         clock.p1 = 2;
3635                         clock.p2 = 10;
3636                         clock.n = 3;
3637                         clock.m1 = 16;
3638                         clock.m2 = 8;
3639                 } else if (adjusted_mode->clock >= 140500
3640                                 && adjusted_mode->clock <= 200000) {
3641                         clock.p1 = 1;
3642                         clock.p2 = 10;
3643                         clock.n = 6;
3644                         clock.m1 = 12;
3645                         clock.m2 = 8;
3646                 }
3647         }
3648
3649         /* FDI link */
3650         if (HAS_PCH_SPLIT(dev)) {
3651                 int lane = 0, link_bw, bpp;
3652                 /* eDP doesn't require FDI link, so just set DP M/N
3653                    according to current link config */
3654                 if (has_edp_encoder) {
3655                         target_clock = mode->clock;
3656                         intel_edp_link_config(has_edp_encoder,
3657                                               &lane, &link_bw);
3658                 } else {
3659                         /* DP over FDI requires target mode clock
3660                            instead of link clock */
3661                         if (is_dp)
3662                                 target_clock = mode->clock;
3663                         else
3664                                 target_clock = adjusted_mode->clock;
3665                         link_bw = 270000;
3666                 }
3667
3668                 /* determine panel color depth */
3669                 temp = I915_READ(pipeconf_reg);
3670                 temp &= ~PIPE_BPC_MASK;
3671                 if (is_lvds) {
3672                         int lvds_reg = I915_READ(PCH_LVDS);
3673                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3674                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3675                                 temp |= PIPE_8BPC;
3676                         else
3677                                 temp |= PIPE_6BPC;
3678                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3679                         switch (dev_priv->edp_bpp/3) {
3680                         case 8:
3681                                 temp |= PIPE_8BPC;
3682                                 break;
3683                         case 10:
3684                                 temp |= PIPE_10BPC;
3685                                 break;
3686                         case 6:
3687                                 temp |= PIPE_6BPC;
3688                                 break;
3689                         case 12:
3690                                 temp |= PIPE_12BPC;
3691                                 break;
3692                         }
3693                 } else
3694                         temp |= PIPE_8BPC;
3695                 I915_WRITE(pipeconf_reg, temp);
3696                 I915_READ(pipeconf_reg);
3697
3698                 switch (temp & PIPE_BPC_MASK) {
3699                 case PIPE_8BPC:
3700                         bpp = 24;
3701                         break;
3702                 case PIPE_10BPC:
3703                         bpp = 30;
3704                         break;
3705                 case PIPE_6BPC:
3706                         bpp = 18;
3707                         break;
3708                 case PIPE_12BPC:
3709                         bpp = 36;
3710                         break;
3711                 default:
3712                         DRM_ERROR("unknown pipe bpc value\n");
3713                         bpp = 24;
3714                 }
3715
3716                 if (!lane) {
3717                         /*
3718                          * Account for spread spectrum to avoid
3719                          * oversubscribing the link. Max center spread
3720                          * is 2.5%; use 5% for safety's sake.
3721                          */
3722                         u32 bps = target_clock * bpp * 21 / 20;
3723                         lane = bps / (link_bw * 8) + 1;
3724                 }
3725
3726                 intel_crtc->fdi_lanes = lane;
3727
3728                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3729         }
3730
3731         /* Ironlake: try to setup display ref clock before DPLL
3732          * enabling. This is only under driver's control after
3733          * PCH B stepping, previous chipset stepping should be
3734          * ignoring this setting.
3735          */
3736         if (HAS_PCH_SPLIT(dev)) {
3737                 temp = I915_READ(PCH_DREF_CONTROL);
3738                 /* Always enable nonspread source */
3739                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3740                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3741                 I915_WRITE(PCH_DREF_CONTROL, temp);
3742                 POSTING_READ(PCH_DREF_CONTROL);
3743
3744                 temp &= ~DREF_SSC_SOURCE_MASK;
3745                 temp |= DREF_SSC_SOURCE_ENABLE;
3746                 I915_WRITE(PCH_DREF_CONTROL, temp);
3747                 POSTING_READ(PCH_DREF_CONTROL);
3748
3749                 udelay(200);
3750
3751                 if (has_edp_encoder) {
3752                         if (dev_priv->lvds_use_ssc) {
3753                                 temp |= DREF_SSC1_ENABLE;
3754                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3755                                 POSTING_READ(PCH_DREF_CONTROL);
3756
3757                                 udelay(200);
3758
3759                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3760                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3761                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3762                                 POSTING_READ(PCH_DREF_CONTROL);
3763                         } else {
3764                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3765                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3766                                 POSTING_READ(PCH_DREF_CONTROL);
3767                         }
3768                 }
3769         }
3770
3771         if (IS_PINEVIEW(dev)) {
3772                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3773                 if (has_reduced_clock)
3774                         fp2 = (1 << reduced_clock.n) << 16 |
3775                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3776         } else {
3777                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3778                 if (has_reduced_clock)
3779                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3780                                 reduced_clock.m2;
3781         }
3782
3783         if (!HAS_PCH_SPLIT(dev))
3784                 dpll = DPLL_VGA_MODE_DIS;
3785
3786         if (IS_I9XX(dev)) {
3787                 if (is_lvds)
3788                         dpll |= DPLLB_MODE_LVDS;
3789                 else
3790                         dpll |= DPLLB_MODE_DAC_SERIAL;
3791                 if (is_sdvo) {
3792                         dpll |= DPLL_DVO_HIGH_SPEED;
3793                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3794                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3795                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3796                         else if (HAS_PCH_SPLIT(dev))
3797                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3798                 }
3799                 if (is_dp)
3800                         dpll |= DPLL_DVO_HIGH_SPEED;
3801
3802                 /* compute bitmask from p1 value */
3803                 if (IS_PINEVIEW(dev))
3804                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3805                 else {
3806                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3807                         /* also FPA1 */
3808                         if (HAS_PCH_SPLIT(dev))
3809                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3810                         if (IS_G4X(dev) && has_reduced_clock)
3811                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3812                 }
3813                 switch (clock.p2) {
3814                 case 5:
3815                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3816                         break;
3817                 case 7:
3818                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3819                         break;
3820                 case 10:
3821                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3822                         break;
3823                 case 14:
3824                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3825                         break;
3826                 }
3827                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3828                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3829         } else {
3830                 if (is_lvds) {
3831                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3832                 } else {
3833                         if (clock.p1 == 2)
3834                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3835                         else
3836                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3837                         if (clock.p2 == 4)
3838                                 dpll |= PLL_P2_DIVIDE_BY_4;
3839                 }
3840         }
3841
3842         if (is_sdvo && is_tv)
3843                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3844         else if (is_tv)
3845                 /* XXX: just matching BIOS for now */
3846                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3847                 dpll |= 3;
3848         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3849                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3850         else
3851                 dpll |= PLL_REF_INPUT_DREFCLK;
3852
3853         /* setup pipeconf */
3854         pipeconf = I915_READ(pipeconf_reg);
3855
3856         /* Set up the display plane register */
3857         dspcntr = DISPPLANE_GAMMA_ENABLE;
3858
3859         /* Ironlake's plane is forced to pipe, bit 24 is to
3860            enable color space conversion */
3861         if (!HAS_PCH_SPLIT(dev)) {
3862                 if (pipe == 0)
3863                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3864                 else
3865                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3866         }
3867
3868         if (pipe == 0 && !IS_I965G(dev)) {
3869                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3870                  * core speed.
3871                  *
3872                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3873                  * pipe == 0 check?
3874                  */
3875                 if (mode->clock >
3876                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3877                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3878                 else
3879                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3880         }
3881
3882         dspcntr |= DISPLAY_PLANE_ENABLE;
3883         pipeconf |= PIPEACONF_ENABLE;
3884         dpll |= DPLL_VCO_ENABLE;
3885
3886
3887         /* Disable the panel fitter if it was on our pipe */
3888         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3889                 I915_WRITE(PFIT_CONTROL, 0);
3890
3891         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3892         drm_mode_debug_printmodeline(mode);
3893
3894         /* assign to Ironlake registers */
3895         if (HAS_PCH_SPLIT(dev)) {
3896                 fp_reg = pch_fp_reg;
3897                 dpll_reg = pch_dpll_reg;
3898         }
3899
3900         if (!has_edp_encoder) {
3901                 I915_WRITE(fp_reg, fp);
3902                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3903                 I915_READ(dpll_reg);
3904                 udelay(150);
3905         }
3906
3907         /* enable transcoder DPLL */
3908         if (HAS_PCH_CPT(dev)) {
3909                 temp = I915_READ(PCH_DPLL_SEL);
3910                 if (trans_dpll_sel == 0)
3911                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3912                 else
3913                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3914                 I915_WRITE(PCH_DPLL_SEL, temp);
3915                 I915_READ(PCH_DPLL_SEL);
3916                 udelay(150);
3917         }
3918
3919         if (HAS_PCH_SPLIT(dev)) {
3920                 pipeconf &= ~PIPE_ENABLE_DITHER;
3921                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3922         }
3923
3924         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3925          * This is an exception to the general rule that mode_set doesn't turn
3926          * things on.
3927          */
3928         if (is_lvds) {
3929                 u32 lvds;
3930
3931                 if (HAS_PCH_SPLIT(dev))
3932                         lvds_reg = PCH_LVDS;
3933
3934                 lvds = I915_READ(lvds_reg);
3935                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3936                 if (pipe == 1) {
3937                         if (HAS_PCH_CPT(dev))
3938                                 lvds |= PORT_TRANS_B_SEL_CPT;
3939                         else
3940                                 lvds |= LVDS_PIPEB_SELECT;
3941                 } else {
3942                         if (HAS_PCH_CPT(dev))
3943                                 lvds &= ~PORT_TRANS_SEL_MASK;
3944                         else
3945                                 lvds &= ~LVDS_PIPEB_SELECT;
3946                 }
3947                 /* set the corresponsding LVDS_BORDER bit */
3948                 lvds |= dev_priv->lvds_border_bits;
3949                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3950                  * set the DPLLs for dual-channel mode or not.
3951                  */
3952                 if (clock.p2 == 7)
3953                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3954                 else
3955                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3956
3957                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3958                  * appropriately here, but we need to look more thoroughly into how
3959                  * panels behave in the two modes.
3960                  */
3961                 /* set the dithering flag */
3962                 if (IS_I965G(dev)) {
3963                         if (dev_priv->lvds_dither) {
3964                                 if (HAS_PCH_SPLIT(dev)) {
3965                                         pipeconf |= PIPE_ENABLE_DITHER;
3966                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
3967                                 } else
3968                                         lvds |= LVDS_ENABLE_DITHER;
3969                         } else {
3970                                 if (!HAS_PCH_SPLIT(dev)) {
3971                                         lvds &= ~LVDS_ENABLE_DITHER;
3972                                 }
3973                         }
3974                 }
3975                 I915_WRITE(lvds_reg, lvds);
3976                 I915_READ(lvds_reg);
3977         }
3978         if (is_dp)
3979                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3980         else if (HAS_PCH_SPLIT(dev)) {
3981                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3982                 if (pipe == 0) {
3983                         I915_WRITE(TRANSA_DATA_M1, 0);
3984                         I915_WRITE(TRANSA_DATA_N1, 0);
3985                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3986                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3987                 } else {
3988                         I915_WRITE(TRANSB_DATA_M1, 0);
3989                         I915_WRITE(TRANSB_DATA_N1, 0);
3990                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3991                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3992                 }
3993         }
3994
3995         if (!has_edp_encoder) {
3996                 I915_WRITE(fp_reg, fp);
3997                 I915_WRITE(dpll_reg, dpll);
3998                 I915_READ(dpll_reg);
3999                 /* Wait for the clocks to stabilize. */
4000                 udelay(150);
4001
4002                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4003                         if (is_sdvo) {
4004                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4005                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4006                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4007                         } else
4008                                 I915_WRITE(dpll_md_reg, 0);
4009                 } else {
4010                         /* write it again -- the BIOS does, after all */
4011                         I915_WRITE(dpll_reg, dpll);
4012                 }
4013                 I915_READ(dpll_reg);
4014                 /* Wait for the clocks to stabilize. */
4015                 udelay(150);
4016         }
4017
4018         if (is_lvds && has_reduced_clock && i915_powersave) {
4019                 I915_WRITE(fp_reg + 4, fp2);
4020                 intel_crtc->lowfreq_avail = true;
4021                 if (HAS_PIPE_CXSR(dev)) {
4022                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4023                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4024                 }
4025         } else {
4026                 I915_WRITE(fp_reg + 4, fp);
4027                 intel_crtc->lowfreq_avail = false;
4028                 if (HAS_PIPE_CXSR(dev)) {
4029                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4030                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4031                 }
4032         }
4033
4034         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4035                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4036                 /* the chip adds 2 halflines automatically */
4037                 adjusted_mode->crtc_vdisplay -= 1;
4038                 adjusted_mode->crtc_vtotal -= 1;
4039                 adjusted_mode->crtc_vblank_start -= 1;
4040                 adjusted_mode->crtc_vblank_end -= 1;
4041                 adjusted_mode->crtc_vsync_end -= 1;
4042                 adjusted_mode->crtc_vsync_start -= 1;
4043         } else
4044                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4045
4046         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4047                    ((adjusted_mode->crtc_htotal - 1) << 16));
4048         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4049                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4050         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4051                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4052         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4053                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4054         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4055                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4056         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4057                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4058         /* pipesrc and dspsize control the size that is scaled from, which should
4059          * always be the user's requested size.
4060          */
4061         if (!HAS_PCH_SPLIT(dev)) {
4062                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4063                                 (mode->hdisplay - 1));
4064                 I915_WRITE(dsppos_reg, 0);
4065         }
4066         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4067
4068         if (HAS_PCH_SPLIT(dev)) {
4069                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4070                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4071                 I915_WRITE(link_m1_reg, m_n.link_m);
4072                 I915_WRITE(link_n1_reg, m_n.link_n);
4073
4074                 if (has_edp_encoder) {
4075                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4076                 } else {
4077                         /* enable FDI RX PLL too */
4078                         temp = I915_READ(fdi_rx_reg);
4079                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4080                         I915_READ(fdi_rx_reg);
4081                         udelay(200);
4082
4083                         /* enable FDI TX PLL too */
4084                         temp = I915_READ(fdi_tx_reg);
4085                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4086                         I915_READ(fdi_tx_reg);
4087
4088                         /* enable FDI RX PCDCLK */
4089                         temp = I915_READ(fdi_rx_reg);
4090                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4091                         I915_READ(fdi_rx_reg);
4092                         udelay(200);
4093                 }
4094         }
4095
4096         I915_WRITE(pipeconf_reg, pipeconf);
4097         I915_READ(pipeconf_reg);
4098
4099         intel_wait_for_vblank(dev, pipe);
4100
4101         if (IS_IRONLAKE(dev)) {
4102                 /* enable address swizzle for tiling buffer */
4103                 temp = I915_READ(DISP_ARB_CTL);
4104                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4105         }
4106
4107         I915_WRITE(dspcntr_reg, dspcntr);
4108
4109         /* Flush the plane changes */
4110         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4111
4112         intel_update_watermarks(dev);
4113
4114         drm_vblank_post_modeset(dev, pipe);
4115
4116         return ret;
4117 }
4118
4119 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4120 void intel_crtc_load_lut(struct drm_crtc *crtc)
4121 {
4122         struct drm_device *dev = crtc->dev;
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4126         int i;
4127
4128         /* The clocks have to be on to load the palette. */
4129         if (!crtc->enabled)
4130                 return;
4131
4132         /* use legacy palette for Ironlake */
4133         if (HAS_PCH_SPLIT(dev))
4134                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4135                                                    LGC_PALETTE_B;
4136
4137         for (i = 0; i < 256; i++) {
4138                 I915_WRITE(palreg + 4 * i,
4139                            (intel_crtc->lut_r[i] << 16) |
4140                            (intel_crtc->lut_g[i] << 8) |
4141                            intel_crtc->lut_b[i]);
4142         }
4143 }
4144
4145 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4146 {
4147         struct drm_device *dev = crtc->dev;
4148         struct drm_i915_private *dev_priv = dev->dev_private;
4149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150         bool visible = base != 0;
4151         u32 cntl;
4152
4153         if (intel_crtc->cursor_visible == visible)
4154                 return;
4155
4156         cntl = I915_READ(CURACNTR);
4157         if (visible) {
4158                 /* On these chipsets we can only modify the base whilst
4159                  * the cursor is disabled.
4160                  */
4161                 I915_WRITE(CURABASE, base);
4162
4163                 cntl &= ~(CURSOR_FORMAT_MASK);
4164                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4165                 cntl |= CURSOR_ENABLE |
4166                         CURSOR_GAMMA_ENABLE |
4167                         CURSOR_FORMAT_ARGB;
4168         } else
4169                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4170         I915_WRITE(CURACNTR, cntl);
4171
4172         intel_crtc->cursor_visible = visible;
4173 }
4174
4175 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4176 {
4177         struct drm_device *dev = crtc->dev;
4178         struct drm_i915_private *dev_priv = dev->dev_private;
4179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180         int pipe = intel_crtc->pipe;
4181         bool visible = base != 0;
4182
4183         if (intel_crtc->cursor_visible != visible) {
4184                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4185                 if (base) {
4186                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4187                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4188                         cntl |= pipe << 28; /* Connect to correct pipe */
4189                 } else {
4190                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4191                         cntl |= CURSOR_MODE_DISABLE;
4192                 }
4193                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4194
4195                 intel_crtc->cursor_visible = visible;
4196         }
4197         /* and commit changes on next vblank */
4198         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4199 }
4200
4201 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4202 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4203 {
4204         struct drm_device *dev = crtc->dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207         int pipe = intel_crtc->pipe;
4208         int x = intel_crtc->cursor_x;
4209         int y = intel_crtc->cursor_y;
4210         u32 base, pos;
4211         bool visible;
4212
4213         pos = 0;
4214
4215         if (intel_crtc->cursor_on && crtc->fb) {
4216                 base = intel_crtc->cursor_addr;
4217                 if (x > (int) crtc->fb->width)
4218                         base = 0;
4219
4220                 if (y > (int) crtc->fb->height)
4221                         base = 0;
4222         } else
4223                 base = 0;
4224
4225         if (x < 0) {
4226                 if (x + intel_crtc->cursor_width < 0)
4227                         base = 0;
4228
4229                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4230                 x = -x;
4231         }
4232         pos |= x << CURSOR_X_SHIFT;
4233
4234         if (y < 0) {
4235                 if (y + intel_crtc->cursor_height < 0)
4236                         base = 0;
4237
4238                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4239                 y = -y;
4240         }
4241         pos |= y << CURSOR_Y_SHIFT;
4242
4243         visible = base != 0;
4244         if (!visible && !intel_crtc->cursor_visible)
4245                 return;
4246
4247         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4248         if (IS_845G(dev) || IS_I865G(dev))
4249                 i845_update_cursor(crtc, base);
4250         else
4251                 i9xx_update_cursor(crtc, base);
4252
4253         if (visible)
4254                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4255 }
4256
4257 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4258                                  struct drm_file *file_priv,
4259                                  uint32_t handle,
4260                                  uint32_t width, uint32_t height)
4261 {
4262         struct drm_device *dev = crtc->dev;
4263         struct drm_i915_private *dev_priv = dev->dev_private;
4264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265         struct drm_gem_object *bo;
4266         struct drm_i915_gem_object *obj_priv;
4267         uint32_t addr;
4268         int ret;
4269
4270         DRM_DEBUG_KMS("\n");
4271
4272         /* if we want to turn off the cursor ignore width and height */
4273         if (!handle) {
4274                 DRM_DEBUG_KMS("cursor off\n");
4275                 addr = 0;
4276                 bo = NULL;
4277                 mutex_lock(&dev->struct_mutex);
4278                 goto finish;
4279         }
4280
4281         /* Currently we only support 64x64 cursors */
4282         if (width != 64 || height != 64) {
4283                 DRM_ERROR("we currently only support 64x64 cursors\n");
4284                 return -EINVAL;
4285         }
4286
4287         bo = drm_gem_object_lookup(dev, file_priv, handle);
4288         if (!bo)
4289                 return -ENOENT;
4290
4291         obj_priv = to_intel_bo(bo);
4292
4293         if (bo->size < width * height * 4) {
4294                 DRM_ERROR("buffer is to small\n");
4295                 ret = -ENOMEM;
4296                 goto fail;
4297         }
4298
4299         /* we only need to pin inside GTT if cursor is non-phy */
4300         mutex_lock(&dev->struct_mutex);
4301         if (!dev_priv->info->cursor_needs_physical) {
4302                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4303                 if (ret) {
4304                         DRM_ERROR("failed to pin cursor bo\n");
4305                         goto fail_locked;
4306                 }
4307
4308                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4309                 if (ret) {
4310                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4311                         goto fail_unpin;
4312                 }
4313
4314                 addr = obj_priv->gtt_offset;
4315         } else {
4316                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4317                 ret = i915_gem_attach_phys_object(dev, bo,
4318                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4319                                                   align);
4320                 if (ret) {
4321                         DRM_ERROR("failed to attach phys object\n");
4322                         goto fail_locked;
4323                 }
4324                 addr = obj_priv->phys_obj->handle->busaddr;
4325         }
4326
4327         if (!IS_I9XX(dev))
4328                 I915_WRITE(CURSIZE, (height << 12) | width);
4329
4330  finish:
4331         if (intel_crtc->cursor_bo) {
4332                 if (dev_priv->info->cursor_needs_physical) {
4333                         if (intel_crtc->cursor_bo != bo)
4334                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4335                 } else
4336                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4337                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4338         }
4339
4340         mutex_unlock(&dev->struct_mutex);
4341
4342         intel_crtc->cursor_addr = addr;
4343         intel_crtc->cursor_bo = bo;
4344         intel_crtc->cursor_width = width;
4345         intel_crtc->cursor_height = height;
4346
4347         intel_crtc_update_cursor(crtc);
4348
4349         return 0;
4350 fail_unpin:
4351         i915_gem_object_unpin(bo);
4352 fail_locked:
4353         mutex_unlock(&dev->struct_mutex);
4354 fail:
4355         drm_gem_object_unreference_unlocked(bo);
4356         return ret;
4357 }
4358
4359 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4360 {
4361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4362
4363         intel_crtc->cursor_x = x;
4364         intel_crtc->cursor_y = y;
4365
4366         intel_crtc_update_cursor(crtc);
4367
4368         return 0;
4369 }
4370
4371 /** Sets the color ramps on behalf of RandR */
4372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4373                                  u16 blue, int regno)
4374 {
4375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4376
4377         intel_crtc->lut_r[regno] = red >> 8;
4378         intel_crtc->lut_g[regno] = green >> 8;
4379         intel_crtc->lut_b[regno] = blue >> 8;
4380 }
4381
4382 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4383                              u16 *blue, int regno)
4384 {
4385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386
4387         *red = intel_crtc->lut_r[regno] << 8;
4388         *green = intel_crtc->lut_g[regno] << 8;
4389         *blue = intel_crtc->lut_b[regno] << 8;
4390 }
4391
4392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4393                                  u16 *blue, uint32_t start, uint32_t size)
4394 {
4395         int end = (start + size > 256) ? 256 : start + size, i;
4396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4397
4398         for (i = start; i < end; i++) {
4399                 intel_crtc->lut_r[i] = red[i] >> 8;
4400                 intel_crtc->lut_g[i] = green[i] >> 8;
4401                 intel_crtc->lut_b[i] = blue[i] >> 8;
4402         }
4403
4404         intel_crtc_load_lut(crtc);
4405 }
4406
4407 /**
4408  * Get a pipe with a simple mode set on it for doing load-based monitor
4409  * detection.
4410  *
4411  * It will be up to the load-detect code to adjust the pipe as appropriate for
4412  * its requirements.  The pipe will be connected to no other encoders.
4413  *
4414  * Currently this code will only succeed if there is a pipe with no encoders
4415  * configured for it.  In the future, it could choose to temporarily disable
4416  * some outputs to free up a pipe for its use.
4417  *
4418  * \return crtc, or NULL if no pipes are available.
4419  */
4420
4421 /* VESA 640x480x72Hz mode to set on the pipe */
4422 static struct drm_display_mode load_detect_mode = {
4423         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4424                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4425 };
4426
4427 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4428                                             struct drm_connector *connector,
4429                                             struct drm_display_mode *mode,
4430                                             int *dpms_mode)
4431 {
4432         struct intel_crtc *intel_crtc;
4433         struct drm_crtc *possible_crtc;
4434         struct drm_crtc *supported_crtc =NULL;
4435         struct drm_encoder *encoder = &intel_encoder->enc;
4436         struct drm_crtc *crtc = NULL;
4437         struct drm_device *dev = encoder->dev;
4438         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4439         struct drm_crtc_helper_funcs *crtc_funcs;
4440         int i = -1;
4441
4442         /*
4443          * Algorithm gets a little messy:
4444          *   - if the connector already has an assigned crtc, use it (but make
4445          *     sure it's on first)
4446          *   - try to find the first unused crtc that can drive this connector,
4447          *     and use that if we find one
4448          *   - if there are no unused crtcs available, try to use the first
4449          *     one we found that supports the connector
4450          */
4451
4452         /* See if we already have a CRTC for this connector */
4453         if (encoder->crtc) {
4454                 crtc = encoder->crtc;
4455                 /* Make sure the crtc and connector are running */
4456                 intel_crtc = to_intel_crtc(crtc);
4457                 *dpms_mode = intel_crtc->dpms_mode;
4458                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4459                         crtc_funcs = crtc->helper_private;
4460                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4461                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4462                 }
4463                 return crtc;
4464         }
4465
4466         /* Find an unused one (if possible) */
4467         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4468                 i++;
4469                 if (!(encoder->possible_crtcs & (1 << i)))
4470                         continue;
4471                 if (!possible_crtc->enabled) {
4472                         crtc = possible_crtc;
4473                         break;
4474                 }
4475                 if (!supported_crtc)
4476                         supported_crtc = possible_crtc;
4477         }
4478
4479         /*
4480          * If we didn't find an unused CRTC, don't use any.
4481          */
4482         if (!crtc) {
4483                 return NULL;
4484         }
4485
4486         encoder->crtc = crtc;
4487         connector->encoder = encoder;
4488         intel_encoder->load_detect_temp = true;
4489
4490         intel_crtc = to_intel_crtc(crtc);
4491         *dpms_mode = intel_crtc->dpms_mode;
4492
4493         if (!crtc->enabled) {
4494                 if (!mode)
4495                         mode = &load_detect_mode;
4496                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4497         } else {
4498                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4499                         crtc_funcs = crtc->helper_private;
4500                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4501                 }
4502
4503                 /* Add this connector to the crtc */
4504                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4505                 encoder_funcs->commit(encoder);
4506         }
4507         /* let the connector get through one full cycle before testing */
4508         intel_wait_for_vblank(dev, intel_crtc->pipe);
4509
4510         return crtc;
4511 }
4512
4513 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4514                                     struct drm_connector *connector, int dpms_mode)
4515 {
4516         struct drm_encoder *encoder = &intel_encoder->enc;
4517         struct drm_device *dev = encoder->dev;
4518         struct drm_crtc *crtc = encoder->crtc;
4519         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4520         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4521
4522         if (intel_encoder->load_detect_temp) {
4523                 encoder->crtc = NULL;
4524                 connector->encoder = NULL;
4525                 intel_encoder->load_detect_temp = false;
4526                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4527                 drm_helper_disable_unused_functions(dev);
4528         }
4529
4530         /* Switch crtc and encoder back off if necessary */
4531         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4532                 if (encoder->crtc == crtc)
4533                         encoder_funcs->dpms(encoder, dpms_mode);
4534                 crtc_funcs->dpms(crtc, dpms_mode);
4535         }
4536 }
4537
4538 /* Returns the clock of the currently programmed mode of the given pipe. */
4539 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4540 {
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4543         int pipe = intel_crtc->pipe;
4544         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4545         u32 fp;
4546         intel_clock_t clock;
4547
4548         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4549                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4550         else
4551                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4552
4553         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4554         if (IS_PINEVIEW(dev)) {
4555                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4556                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4557         } else {
4558                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4559                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4560         }
4561
4562         if (IS_I9XX(dev)) {
4563                 if (IS_PINEVIEW(dev))
4564                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4565                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4566                 else
4567                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4568                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4569
4570                 switch (dpll & DPLL_MODE_MASK) {
4571                 case DPLLB_MODE_DAC_SERIAL:
4572                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4573                                 5 : 10;
4574                         break;
4575                 case DPLLB_MODE_LVDS:
4576                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4577                                 7 : 14;
4578                         break;
4579                 default:
4580                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4581                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4582                         return 0;
4583                 }
4584
4585                 /* XXX: Handle the 100Mhz refclk */
4586                 intel_clock(dev, 96000, &clock);
4587         } else {
4588                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4589
4590                 if (is_lvds) {
4591                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4592                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4593                         clock.p2 = 14;
4594
4595                         if ((dpll & PLL_REF_INPUT_MASK) ==
4596                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4597                                 /* XXX: might not be 66MHz */
4598                                 intel_clock(dev, 66000, &clock);
4599                         } else
4600                                 intel_clock(dev, 48000, &clock);
4601                 } else {
4602                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4603                                 clock.p1 = 2;
4604                         else {
4605                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4606                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4607                         }
4608                         if (dpll & PLL_P2_DIVIDE_BY_4)
4609                                 clock.p2 = 4;
4610                         else
4611                                 clock.p2 = 2;
4612
4613                         intel_clock(dev, 48000, &clock);
4614                 }
4615         }
4616
4617         /* XXX: It would be nice to validate the clocks, but we can't reuse
4618          * i830PllIsValid() because it relies on the xf86_config connector
4619          * configuration being accurate, which it isn't necessarily.
4620          */
4621
4622         return clock.dot;
4623 }
4624
4625 /** Returns the currently programmed mode of the given pipe. */
4626 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4627                                              struct drm_crtc *crtc)
4628 {
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4631         int pipe = intel_crtc->pipe;
4632         struct drm_display_mode *mode;
4633         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4634         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4635         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4636         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4637
4638         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4639         if (!mode)
4640                 return NULL;
4641
4642         mode->clock = intel_crtc_clock_get(dev, crtc);
4643         mode->hdisplay = (htot & 0xffff) + 1;
4644         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4645         mode->hsync_start = (hsync & 0xffff) + 1;
4646         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4647         mode->vdisplay = (vtot & 0xffff) + 1;
4648         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4649         mode->vsync_start = (vsync & 0xffff) + 1;
4650         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4651
4652         drm_mode_set_name(mode);
4653         drm_mode_set_crtcinfo(mode, 0);
4654
4655         return mode;
4656 }
4657
4658 #define GPU_IDLE_TIMEOUT 500 /* ms */
4659
4660 /* When this timer fires, we've been idle for awhile */
4661 static void intel_gpu_idle_timer(unsigned long arg)
4662 {
4663         struct drm_device *dev = (struct drm_device *)arg;
4664         drm_i915_private_t *dev_priv = dev->dev_private;
4665
4666         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4667
4668         dev_priv->busy = false;
4669
4670         queue_work(dev_priv->wq, &dev_priv->idle_work);
4671 }
4672
4673 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4674
4675 static void intel_crtc_idle_timer(unsigned long arg)
4676 {
4677         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4678         struct drm_crtc *crtc = &intel_crtc->base;
4679         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4680
4681         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4682
4683         intel_crtc->busy = false;
4684
4685         queue_work(dev_priv->wq, &dev_priv->idle_work);
4686 }
4687
4688 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4689 {
4690         struct drm_device *dev = crtc->dev;
4691         drm_i915_private_t *dev_priv = dev->dev_private;
4692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693         int pipe = intel_crtc->pipe;
4694         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4695         int dpll = I915_READ(dpll_reg);
4696
4697         if (HAS_PCH_SPLIT(dev))
4698                 return;
4699
4700         if (!dev_priv->lvds_downclock_avail)
4701                 return;
4702
4703         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4704                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4705
4706                 /* Unlock panel regs */
4707                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4708                            PANEL_UNLOCK_REGS);
4709
4710                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4711                 I915_WRITE(dpll_reg, dpll);
4712                 dpll = I915_READ(dpll_reg);
4713                 intel_wait_for_vblank(dev, pipe);
4714                 dpll = I915_READ(dpll_reg);
4715                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4716                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4717
4718                 /* ...and lock them again */
4719                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4720         }
4721
4722         /* Schedule downclock */
4723         if (schedule)
4724                 mod_timer(&intel_crtc->idle_timer, jiffies +
4725                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4726 }
4727
4728 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4729 {
4730         struct drm_device *dev = crtc->dev;
4731         drm_i915_private_t *dev_priv = dev->dev_private;
4732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733         int pipe = intel_crtc->pipe;
4734         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4735         int dpll = I915_READ(dpll_reg);
4736
4737         if (HAS_PCH_SPLIT(dev))
4738                 return;
4739
4740         if (!dev_priv->lvds_downclock_avail)
4741                 return;
4742
4743         /*
4744          * Since this is called by a timer, we should never get here in
4745          * the manual case.
4746          */
4747         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4748                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4749
4750                 /* Unlock panel regs */
4751                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4752                            PANEL_UNLOCK_REGS);
4753
4754                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4755                 I915_WRITE(dpll_reg, dpll);
4756                 dpll = I915_READ(dpll_reg);
4757                 intel_wait_for_vblank(dev, pipe);
4758                 dpll = I915_READ(dpll_reg);
4759                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4760                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4761
4762                 /* ...and lock them again */
4763                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4764         }
4765
4766 }
4767
4768 /**
4769  * intel_idle_update - adjust clocks for idleness
4770  * @work: work struct
4771  *
4772  * Either the GPU or display (or both) went idle.  Check the busy status
4773  * here and adjust the CRTC and GPU clocks as necessary.
4774  */
4775 static void intel_idle_update(struct work_struct *work)
4776 {
4777         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4778                                                     idle_work);
4779         struct drm_device *dev = dev_priv->dev;
4780         struct drm_crtc *crtc;
4781         struct intel_crtc *intel_crtc;
4782         int enabled = 0;
4783
4784         if (!i915_powersave)
4785                 return;
4786
4787         mutex_lock(&dev->struct_mutex);
4788
4789         i915_update_gfx_val(dev_priv);
4790
4791         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4792                 /* Skip inactive CRTCs */
4793                 if (!crtc->fb)
4794                         continue;
4795
4796                 enabled++;
4797                 intel_crtc = to_intel_crtc(crtc);
4798                 if (!intel_crtc->busy)
4799                         intel_decrease_pllclock(crtc);
4800         }
4801
4802         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4803                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4804                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4805         }
4806
4807         mutex_unlock(&dev->struct_mutex);
4808 }
4809
4810 /**
4811  * intel_mark_busy - mark the GPU and possibly the display busy
4812  * @dev: drm device
4813  * @obj: object we're operating on
4814  *
4815  * Callers can use this function to indicate that the GPU is busy processing
4816  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4817  * buffer), we'll also mark the display as busy, so we know to increase its
4818  * clock frequency.
4819  */
4820 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4821 {
4822         drm_i915_private_t *dev_priv = dev->dev_private;
4823         struct drm_crtc *crtc = NULL;
4824         struct intel_framebuffer *intel_fb;
4825         struct intel_crtc *intel_crtc;
4826
4827         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4828                 return;
4829
4830         if (!dev_priv->busy) {
4831                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4832                         u32 fw_blc_self;
4833
4834                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4835                         fw_blc_self = I915_READ(FW_BLC_SELF);
4836                         fw_blc_self &= ~FW_BLC_SELF_EN;
4837                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4838                 }
4839                 dev_priv->busy = true;
4840         } else
4841                 mod_timer(&dev_priv->idle_timer, jiffies +
4842                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4843
4844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4845                 if (!crtc->fb)
4846                         continue;
4847
4848                 intel_crtc = to_intel_crtc(crtc);
4849                 intel_fb = to_intel_framebuffer(crtc->fb);
4850                 if (intel_fb->obj == obj) {
4851                         if (!intel_crtc->busy) {
4852                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4853                                         u32 fw_blc_self;
4854
4855                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4856                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4857                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4858                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4859                                 }
4860                                 /* Non-busy -> busy, upclock */
4861                                 intel_increase_pllclock(crtc, true);
4862                                 intel_crtc->busy = true;
4863                         } else {
4864                                 /* Busy -> busy, put off timer */
4865                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4866                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4867                         }
4868                 }
4869         }
4870 }
4871
4872 static void intel_crtc_destroy(struct drm_crtc *crtc)
4873 {
4874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875
4876         drm_crtc_cleanup(crtc);
4877         kfree(intel_crtc);
4878 }
4879
4880 static void intel_unpin_work_fn(struct work_struct *__work)
4881 {
4882         struct intel_unpin_work *work =
4883                 container_of(__work, struct intel_unpin_work, work);
4884
4885         mutex_lock(&work->dev->struct_mutex);
4886         i915_gem_object_unpin(work->old_fb_obj);
4887         drm_gem_object_unreference(work->pending_flip_obj);
4888         drm_gem_object_unreference(work->old_fb_obj);
4889         mutex_unlock(&work->dev->struct_mutex);
4890         kfree(work);
4891 }
4892
4893 static void do_intel_finish_page_flip(struct drm_device *dev,
4894                                       struct drm_crtc *crtc)
4895 {
4896         drm_i915_private_t *dev_priv = dev->dev_private;
4897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898         struct intel_unpin_work *work;
4899         struct drm_i915_gem_object *obj_priv;
4900         struct drm_pending_vblank_event *e;
4901         struct timeval now;
4902         unsigned long flags;
4903
4904         /* Ignore early vblank irqs */
4905         if (intel_crtc == NULL)
4906                 return;
4907
4908         spin_lock_irqsave(&dev->event_lock, flags);
4909         work = intel_crtc->unpin_work;
4910         if (work == NULL || !work->pending) {
4911                 spin_unlock_irqrestore(&dev->event_lock, flags);
4912                 return;
4913         }
4914
4915         intel_crtc->unpin_work = NULL;
4916         drm_vblank_put(dev, intel_crtc->pipe);
4917
4918         if (work->event) {
4919                 e = work->event;
4920                 do_gettimeofday(&now);
4921                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4922                 e->event.tv_sec = now.tv_sec;
4923                 e->event.tv_usec = now.tv_usec;
4924                 list_add_tail(&e->base.link,
4925                               &e->base.file_priv->event_list);
4926                 wake_up_interruptible(&e->base.file_priv->event_wait);
4927         }
4928
4929         spin_unlock_irqrestore(&dev->event_lock, flags);
4930
4931         obj_priv = to_intel_bo(work->pending_flip_obj);
4932
4933         /* Initial scanout buffer will have a 0 pending flip count */
4934         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4935             atomic_dec_and_test(&obj_priv->pending_flip))
4936                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4937         schedule_work(&work->work);
4938
4939         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4940 }
4941
4942 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4943 {
4944         drm_i915_private_t *dev_priv = dev->dev_private;
4945         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4946
4947         do_intel_finish_page_flip(dev, crtc);
4948 }
4949
4950 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4951 {
4952         drm_i915_private_t *dev_priv = dev->dev_private;
4953         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4954
4955         do_intel_finish_page_flip(dev, crtc);
4956 }
4957
4958 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4959 {
4960         drm_i915_private_t *dev_priv = dev->dev_private;
4961         struct intel_crtc *intel_crtc =
4962                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4963         unsigned long flags;
4964
4965         spin_lock_irqsave(&dev->event_lock, flags);
4966         if (intel_crtc->unpin_work) {
4967                 if ((++intel_crtc->unpin_work->pending) > 1)
4968                         DRM_ERROR("Prepared flip multiple times\n");
4969         } else {
4970                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4971         }
4972         spin_unlock_irqrestore(&dev->event_lock, flags);
4973 }
4974
4975 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4976                                 struct drm_framebuffer *fb,
4977                                 struct drm_pending_vblank_event *event)
4978 {
4979         struct drm_device *dev = crtc->dev;
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         struct intel_framebuffer *intel_fb;
4982         struct drm_i915_gem_object *obj_priv;
4983         struct drm_gem_object *obj;
4984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4985         struct intel_unpin_work *work;
4986         unsigned long flags, offset;
4987         int pipe = intel_crtc->pipe;
4988         u32 pf, pipesrc;
4989         int ret;
4990
4991         work = kzalloc(sizeof *work, GFP_KERNEL);
4992         if (work == NULL)
4993                 return -ENOMEM;
4994
4995         work->event = event;
4996         work->dev = crtc->dev;
4997         intel_fb = to_intel_framebuffer(crtc->fb);
4998         work->old_fb_obj = intel_fb->obj;
4999         INIT_WORK(&work->work, intel_unpin_work_fn);
5000
5001         /* We borrow the event spin lock for protecting unpin_work */
5002         spin_lock_irqsave(&dev->event_lock, flags);
5003         if (intel_crtc->unpin_work) {
5004                 spin_unlock_irqrestore(&dev->event_lock, flags);
5005                 kfree(work);
5006
5007                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5008                 return -EBUSY;
5009         }
5010         intel_crtc->unpin_work = work;
5011         spin_unlock_irqrestore(&dev->event_lock, flags);
5012
5013         intel_fb = to_intel_framebuffer(fb);
5014         obj = intel_fb->obj;
5015
5016         mutex_lock(&dev->struct_mutex);
5017         ret = intel_pin_and_fence_fb_obj(dev, obj);
5018         if (ret)
5019                 goto cleanup_work;
5020
5021         /* Reference the objects for the scheduled work. */
5022         drm_gem_object_reference(work->old_fb_obj);
5023         drm_gem_object_reference(obj);
5024
5025         crtc->fb = fb;
5026         ret = i915_gem_object_flush_write_domain(obj);
5027         if (ret)
5028                 goto cleanup_objs;
5029
5030         ret = drm_vblank_get(dev, intel_crtc->pipe);
5031         if (ret)
5032                 goto cleanup_objs;
5033
5034         obj_priv = to_intel_bo(obj);
5035         atomic_inc(&obj_priv->pending_flip);
5036         work->pending_flip_obj = obj;
5037
5038         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5039                 u32 flip_mask;
5040
5041                 if (intel_crtc->plane)
5042                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5043                 else
5044                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5045
5046                 BEGIN_LP_RING(2);
5047                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5048                 OUT_RING(0);
5049                 ADVANCE_LP_RING();
5050         }
5051
5052         work->enable_stall_check = true;
5053
5054         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5055         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5056
5057         BEGIN_LP_RING(4);
5058         switch(INTEL_INFO(dev)->gen) {
5059         case 2:
5060                 OUT_RING(MI_DISPLAY_FLIP |
5061                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5062                 OUT_RING(fb->pitch);
5063                 OUT_RING(obj_priv->gtt_offset + offset);
5064                 OUT_RING(MI_NOOP);
5065                 break;
5066
5067         case 3:
5068                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5069                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5070                 OUT_RING(fb->pitch);
5071                 OUT_RING(obj_priv->gtt_offset + offset);
5072                 OUT_RING(MI_NOOP);
5073                 break;
5074
5075         case 4:
5076         case 5:
5077                 /* i965+ uses the linear or tiled offsets from the
5078                  * Display Registers (which do not change across a page-flip)
5079                  * so we need only reprogram the base address.
5080                  */
5081                 OUT_RING(MI_DISPLAY_FLIP |
5082                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5083                 OUT_RING(fb->pitch);
5084                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5085
5086                 /* XXX Enabling the panel-fitter across page-flip is so far
5087                  * untested on non-native modes, so ignore it for now.
5088                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5089                  */
5090                 pf = 0;
5091                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5092                 OUT_RING(pf | pipesrc);
5093                 break;
5094
5095         case 6:
5096                 OUT_RING(MI_DISPLAY_FLIP |
5097                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5098                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5099                 OUT_RING(obj_priv->gtt_offset);
5100
5101                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5102                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5103                 OUT_RING(pf | pipesrc);
5104                 break;
5105         }
5106         ADVANCE_LP_RING();
5107
5108         mutex_unlock(&dev->struct_mutex);
5109
5110         trace_i915_flip_request(intel_crtc->plane, obj);
5111
5112         return 0;
5113
5114 cleanup_objs:
5115         drm_gem_object_unreference(work->old_fb_obj);
5116         drm_gem_object_unreference(obj);
5117 cleanup_work:
5118         mutex_unlock(&dev->struct_mutex);
5119
5120         spin_lock_irqsave(&dev->event_lock, flags);
5121         intel_crtc->unpin_work = NULL;
5122         spin_unlock_irqrestore(&dev->event_lock, flags);
5123
5124         kfree(work);
5125
5126         return ret;
5127 }
5128
5129 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5130         .dpms = intel_crtc_dpms,
5131         .mode_fixup = intel_crtc_mode_fixup,
5132         .mode_set = intel_crtc_mode_set,
5133         .mode_set_base = intel_pipe_set_base,
5134         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5135         .prepare = intel_crtc_prepare,
5136         .commit = intel_crtc_commit,
5137         .load_lut = intel_crtc_load_lut,
5138 };
5139
5140 static const struct drm_crtc_funcs intel_crtc_funcs = {
5141         .cursor_set = intel_crtc_cursor_set,
5142         .cursor_move = intel_crtc_cursor_move,
5143         .gamma_set = intel_crtc_gamma_set,
5144         .set_config = drm_crtc_helper_set_config,
5145         .destroy = intel_crtc_destroy,
5146         .page_flip = intel_crtc_page_flip,
5147 };
5148
5149
5150 static void intel_crtc_init(struct drm_device *dev, int pipe)
5151 {
5152         drm_i915_private_t *dev_priv = dev->dev_private;
5153         struct intel_crtc *intel_crtc;
5154         int i;
5155
5156         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5157         if (intel_crtc == NULL)
5158                 return;
5159
5160         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5161
5162         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5163         intel_crtc->pipe = pipe;
5164         intel_crtc->plane = pipe;
5165         for (i = 0; i < 256; i++) {
5166                 intel_crtc->lut_r[i] = i;
5167                 intel_crtc->lut_g[i] = i;
5168                 intel_crtc->lut_b[i] = i;
5169         }
5170
5171         /* Swap pipes & planes for FBC on pre-965 */
5172         intel_crtc->pipe = pipe;
5173         intel_crtc->plane = pipe;
5174         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5175                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5176                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5177         }
5178
5179         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5180                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5181         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5182         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5183
5184         intel_crtc->cursor_addr = 0;
5185         intel_crtc->dpms_mode = -1;
5186         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5187
5188         intel_crtc->busy = false;
5189
5190         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5191                     (unsigned long)intel_crtc);
5192 }
5193
5194 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5195                                 struct drm_file *file_priv)
5196 {
5197         drm_i915_private_t *dev_priv = dev->dev_private;
5198         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5199         struct drm_mode_object *drmmode_obj;
5200         struct intel_crtc *crtc;
5201
5202         if (!dev_priv) {
5203                 DRM_ERROR("called with no initialization\n");
5204                 return -EINVAL;
5205         }
5206
5207         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5208                         DRM_MODE_OBJECT_CRTC);
5209
5210         if (!drmmode_obj) {
5211                 DRM_ERROR("no such CRTC id\n");
5212                 return -EINVAL;
5213         }
5214
5215         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5216         pipe_from_crtc_id->pipe = crtc->pipe;
5217
5218         return 0;
5219 }
5220
5221 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5222 {
5223         struct drm_crtc *crtc = NULL;
5224
5225         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5226                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5227                 if (intel_crtc->pipe == pipe)
5228                         break;
5229         }
5230         return crtc;
5231 }
5232
5233 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5234 {
5235         int index_mask = 0;
5236         struct drm_encoder *encoder;
5237         int entry = 0;
5238
5239         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5240                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5241                 if (type_mask & intel_encoder->clone_mask)
5242                         index_mask |= (1 << entry);
5243                 entry++;
5244         }
5245         return index_mask;
5246 }
5247
5248
5249 static void intel_setup_outputs(struct drm_device *dev)
5250 {
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         struct drm_encoder *encoder;
5253         bool dpd_is_edp = false;
5254
5255         if (IS_MOBILE(dev) && !IS_I830(dev))
5256                 intel_lvds_init(dev);
5257
5258         if (HAS_PCH_SPLIT(dev)) {
5259                 dpd_is_edp = intel_dpd_is_edp(dev);
5260
5261                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5262                         intel_dp_init(dev, DP_A);
5263
5264                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5265                         intel_dp_init(dev, PCH_DP_D);
5266         }
5267
5268         intel_crt_init(dev);
5269
5270         if (HAS_PCH_SPLIT(dev)) {
5271                 int found;
5272
5273                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5274                         /* PCH SDVOB multiplex with HDMIB */
5275                         found = intel_sdvo_init(dev, PCH_SDVOB);
5276                         if (!found)
5277                                 intel_hdmi_init(dev, HDMIB);
5278                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5279                                 intel_dp_init(dev, PCH_DP_B);
5280                 }
5281
5282                 if (I915_READ(HDMIC) & PORT_DETECTED)
5283                         intel_hdmi_init(dev, HDMIC);
5284
5285                 if (I915_READ(HDMID) & PORT_DETECTED)
5286                         intel_hdmi_init(dev, HDMID);
5287
5288                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5289                         intel_dp_init(dev, PCH_DP_C);
5290
5291                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5292                         intel_dp_init(dev, PCH_DP_D);
5293
5294         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5295                 bool found = false;
5296
5297                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5298                         DRM_DEBUG_KMS("probing SDVOB\n");
5299                         found = intel_sdvo_init(dev, SDVOB);
5300                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5301                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5302                                 intel_hdmi_init(dev, SDVOB);
5303                         }
5304
5305                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5306                                 DRM_DEBUG_KMS("probing DP_B\n");
5307                                 intel_dp_init(dev, DP_B);
5308                         }
5309                 }
5310
5311                 /* Before G4X SDVOC doesn't have its own detect register */
5312
5313                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5314                         DRM_DEBUG_KMS("probing SDVOC\n");
5315                         found = intel_sdvo_init(dev, SDVOC);
5316                 }
5317
5318                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5319
5320                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5321                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5322                                 intel_hdmi_init(dev, SDVOC);
5323                         }
5324                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5325                                 DRM_DEBUG_KMS("probing DP_C\n");
5326                                 intel_dp_init(dev, DP_C);
5327                         }
5328                 }
5329
5330                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5331                     (I915_READ(DP_D) & DP_DETECTED)) {
5332                         DRM_DEBUG_KMS("probing DP_D\n");
5333                         intel_dp_init(dev, DP_D);
5334                 }
5335         } else if (IS_GEN2(dev))
5336                 intel_dvo_init(dev);
5337
5338         if (SUPPORTS_TV(dev))
5339                 intel_tv_init(dev);
5340
5341         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5342                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5343
5344                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5345                 encoder->possible_clones = intel_encoder_clones(dev,
5346                                                 intel_encoder->clone_mask);
5347         }
5348 }
5349
5350 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5351 {
5352         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5353
5354         drm_framebuffer_cleanup(fb);
5355         drm_gem_object_unreference_unlocked(intel_fb->obj);
5356
5357         kfree(intel_fb);
5358 }
5359
5360 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5361                                                 struct drm_file *file_priv,
5362                                                 unsigned int *handle)
5363 {
5364         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5365         struct drm_gem_object *object = intel_fb->obj;
5366
5367         return drm_gem_handle_create(file_priv, object, handle);
5368 }
5369
5370 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5371         .destroy = intel_user_framebuffer_destroy,
5372         .create_handle = intel_user_framebuffer_create_handle,
5373 };
5374
5375 int intel_framebuffer_init(struct drm_device *dev,
5376                            struct intel_framebuffer *intel_fb,
5377                            struct drm_mode_fb_cmd *mode_cmd,
5378                            struct drm_gem_object *obj)
5379 {
5380         int ret;
5381
5382         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5383         if (ret) {
5384                 DRM_ERROR("framebuffer init failed %d\n", ret);
5385                 return ret;
5386         }
5387
5388         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5389         intel_fb->obj = obj;
5390         return 0;
5391 }
5392
5393 static struct drm_framebuffer *
5394 intel_user_framebuffer_create(struct drm_device *dev,
5395                               struct drm_file *filp,
5396                               struct drm_mode_fb_cmd *mode_cmd)
5397 {
5398         struct drm_gem_object *obj;
5399         struct intel_framebuffer *intel_fb;
5400         int ret;
5401
5402         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5403         if (!obj)
5404                 return ERR_PTR(-ENOENT);
5405
5406         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5407         if (!intel_fb)
5408                 return ERR_PTR(-ENOMEM);
5409
5410         ret = intel_framebuffer_init(dev, intel_fb,
5411                                      mode_cmd, obj);
5412         if (ret) {
5413                 drm_gem_object_unreference_unlocked(obj);
5414                 kfree(intel_fb);
5415                 return ERR_PTR(ret);
5416         }
5417
5418         return &intel_fb->base;
5419 }
5420
5421 static const struct drm_mode_config_funcs intel_mode_funcs = {
5422         .fb_create = intel_user_framebuffer_create,
5423         .output_poll_changed = intel_fb_output_poll_changed,
5424 };
5425
5426 static struct drm_gem_object *
5427 intel_alloc_context_page(struct drm_device *dev)
5428 {
5429         struct drm_gem_object *ctx;
5430         int ret;
5431
5432         ctx = i915_gem_alloc_object(dev, 4096);
5433         if (!ctx) {
5434                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5435                 return NULL;
5436         }
5437
5438         mutex_lock(&dev->struct_mutex);
5439         ret = i915_gem_object_pin(ctx, 4096);
5440         if (ret) {
5441                 DRM_ERROR("failed to pin power context: %d\n", ret);
5442                 goto err_unref;
5443         }
5444
5445         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5446         if (ret) {
5447                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5448                 goto err_unpin;
5449         }
5450         mutex_unlock(&dev->struct_mutex);
5451
5452         return ctx;
5453
5454 err_unpin:
5455         i915_gem_object_unpin(ctx);
5456 err_unref:
5457         drm_gem_object_unreference(ctx);
5458         mutex_unlock(&dev->struct_mutex);
5459         return NULL;
5460 }
5461
5462 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5463 {
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         u16 rgvswctl;
5466
5467         rgvswctl = I915_READ16(MEMSWCTL);
5468         if (rgvswctl & MEMCTL_CMD_STS) {
5469                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5470                 return false; /* still busy with another command */
5471         }
5472
5473         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5474                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5475         I915_WRITE16(MEMSWCTL, rgvswctl);
5476         POSTING_READ16(MEMSWCTL);
5477
5478         rgvswctl |= MEMCTL_CMD_STS;
5479         I915_WRITE16(MEMSWCTL, rgvswctl);
5480
5481         return true;
5482 }
5483
5484 void ironlake_enable_drps(struct drm_device *dev)
5485 {
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487         u32 rgvmodectl = I915_READ(MEMMODECTL);
5488         u8 fmax, fmin, fstart, vstart;
5489
5490         /* 100ms RC evaluation intervals */
5491         I915_WRITE(RCUPEI, 100000);
5492         I915_WRITE(RCDNEI, 100000);
5493
5494         /* Set max/min thresholds to 90ms and 80ms respectively */
5495         I915_WRITE(RCBMAXAVG, 90000);
5496         I915_WRITE(RCBMINAVG, 80000);
5497
5498         I915_WRITE(MEMIHYST, 1);
5499
5500         /* Set up min, max, and cur for interrupt handling */
5501         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5502         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5503         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5504                 MEMMODE_FSTART_SHIFT;
5505         fstart = fmax;
5506
5507         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5508                 PXVFREQ_PX_SHIFT;
5509
5510         dev_priv->fmax = fstart; /* IPS callback will increase this */
5511         dev_priv->fstart = fstart;
5512
5513         dev_priv->max_delay = fmax;
5514         dev_priv->min_delay = fmin;
5515         dev_priv->cur_delay = fstart;
5516
5517         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5518                          fstart);
5519
5520         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5521
5522         /*
5523          * Interrupts will be enabled in ironlake_irq_postinstall
5524          */
5525
5526         I915_WRITE(VIDSTART, vstart);
5527         POSTING_READ(VIDSTART);
5528
5529         rgvmodectl |= MEMMODE_SWMODE_EN;
5530         I915_WRITE(MEMMODECTL, rgvmodectl);
5531
5532         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5533                 DRM_ERROR("stuck trying to change perf mode\n");
5534         msleep(1);
5535
5536         ironlake_set_drps(dev, fstart);
5537
5538         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5539                 I915_READ(0x112e0);
5540         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5541         dev_priv->last_count2 = I915_READ(0x112f4);
5542         getrawmonotonic(&dev_priv->last_time2);
5543 }
5544
5545 void ironlake_disable_drps(struct drm_device *dev)
5546 {
5547         struct drm_i915_private *dev_priv = dev->dev_private;
5548         u16 rgvswctl = I915_READ16(MEMSWCTL);
5549
5550         /* Ack interrupts, disable EFC interrupt */
5551         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5552         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5553         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5554         I915_WRITE(DEIIR, DE_PCU_EVENT);
5555         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5556
5557         /* Go back to the starting frequency */
5558         ironlake_set_drps(dev, dev_priv->fstart);
5559         msleep(1);
5560         rgvswctl |= MEMCTL_CMD_STS;
5561         I915_WRITE(MEMSWCTL, rgvswctl);
5562         msleep(1);
5563
5564 }
5565
5566 static unsigned long intel_pxfreq(u32 vidfreq)
5567 {
5568         unsigned long freq;
5569         int div = (vidfreq & 0x3f0000) >> 16;
5570         int post = (vidfreq & 0x3000) >> 12;
5571         int pre = (vidfreq & 0x7);
5572
5573         if (!pre)
5574                 return 0;
5575
5576         freq = ((div * 133333) / ((1<<post) * pre));
5577
5578         return freq;
5579 }
5580
5581 void intel_init_emon(struct drm_device *dev)
5582 {
5583         struct drm_i915_private *dev_priv = dev->dev_private;
5584         u32 lcfuse;
5585         u8 pxw[16];
5586         int i;
5587
5588         /* Disable to program */
5589         I915_WRITE(ECR, 0);
5590         POSTING_READ(ECR);
5591
5592         /* Program energy weights for various events */
5593         I915_WRITE(SDEW, 0x15040d00);
5594         I915_WRITE(CSIEW0, 0x007f0000);
5595         I915_WRITE(CSIEW1, 0x1e220004);
5596         I915_WRITE(CSIEW2, 0x04000004);
5597
5598         for (i = 0; i < 5; i++)
5599                 I915_WRITE(PEW + (i * 4), 0);
5600         for (i = 0; i < 3; i++)
5601                 I915_WRITE(DEW + (i * 4), 0);
5602
5603         /* Program P-state weights to account for frequency power adjustment */
5604         for (i = 0; i < 16; i++) {
5605                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5606                 unsigned long freq = intel_pxfreq(pxvidfreq);
5607                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5608                         PXVFREQ_PX_SHIFT;
5609                 unsigned long val;
5610
5611                 val = vid * vid;
5612                 val *= (freq / 1000);
5613                 val *= 255;
5614                 val /= (127*127*900);
5615                 if (val > 0xff)
5616                         DRM_ERROR("bad pxval: %ld\n", val);
5617                 pxw[i] = val;
5618         }
5619         /* Render standby states get 0 weight */
5620         pxw[14] = 0;
5621         pxw[15] = 0;
5622
5623         for (i = 0; i < 4; i++) {
5624                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5625                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5626                 I915_WRITE(PXW + (i * 4), val);
5627         }
5628
5629         /* Adjust magic regs to magic values (more experimental results) */
5630         I915_WRITE(OGW0, 0);
5631         I915_WRITE(OGW1, 0);
5632         I915_WRITE(EG0, 0x00007f00);
5633         I915_WRITE(EG1, 0x0000000e);
5634         I915_WRITE(EG2, 0x000e0000);
5635         I915_WRITE(EG3, 0x68000300);
5636         I915_WRITE(EG4, 0x42000000);
5637         I915_WRITE(EG5, 0x00140031);
5638         I915_WRITE(EG6, 0);
5639         I915_WRITE(EG7, 0);
5640
5641         for (i = 0; i < 8; i++)
5642                 I915_WRITE(PXWL + (i * 4), 0);
5643
5644         /* Enable PMON + select events */
5645         I915_WRITE(ECR, 0x80000019);
5646
5647         lcfuse = I915_READ(LCFUSE02);
5648
5649         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5650 }
5651
5652 void intel_init_clock_gating(struct drm_device *dev)
5653 {
5654         struct drm_i915_private *dev_priv = dev->dev_private;
5655
5656         /*
5657          * Disable clock gating reported to work incorrectly according to the
5658          * specs, but enable as much else as we can.
5659          */
5660         if (HAS_PCH_SPLIT(dev)) {
5661                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5662
5663                 if (IS_IRONLAKE(dev)) {
5664                         /* Required for FBC */
5665                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5666                         /* Required for CxSR */
5667                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5668
5669                         I915_WRITE(PCH_3DCGDIS0,
5670                                    MARIUNIT_CLOCK_GATE_DISABLE |
5671                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5672                 }
5673
5674                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5675
5676                 /*
5677                  * According to the spec the following bits should be set in
5678                  * order to enable memory self-refresh
5679                  * The bit 22/21 of 0x42004
5680                  * The bit 5 of 0x42020
5681                  * The bit 15 of 0x45000
5682                  */
5683                 if (IS_IRONLAKE(dev)) {
5684                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5685                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5686                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5687                         I915_WRITE(ILK_DSPCLK_GATE,
5688                                         (I915_READ(ILK_DSPCLK_GATE) |
5689                                                 ILK_DPARB_CLK_GATE));
5690                         I915_WRITE(DISP_ARB_CTL,
5691                                         (I915_READ(DISP_ARB_CTL) |
5692                                                 DISP_FBC_WM_DIS));
5693                 I915_WRITE(WM3_LP_ILK, 0);
5694                 I915_WRITE(WM2_LP_ILK, 0);
5695                 I915_WRITE(WM1_LP_ILK, 0);
5696                 }
5697                 /*
5698                  * Based on the document from hardware guys the following bits
5699                  * should be set unconditionally in order to enable FBC.
5700                  * The bit 22 of 0x42000
5701                  * The bit 22 of 0x42004
5702                  * The bit 7,8,9 of 0x42020.
5703                  */
5704                 if (IS_IRONLAKE_M(dev)) {
5705                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5706                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5707                                    ILK_FBCQ_DIS);
5708                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5709                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5710                                    ILK_DPARB_GATE);
5711                         I915_WRITE(ILK_DSPCLK_GATE,
5712                                    I915_READ(ILK_DSPCLK_GATE) |
5713                                    ILK_DPFC_DIS1 |
5714                                    ILK_DPFC_DIS2 |
5715                                    ILK_CLK_FBC);
5716                 }
5717                 return;
5718         } else if (IS_G4X(dev)) {
5719                 uint32_t dspclk_gate;
5720                 I915_WRITE(RENCLK_GATE_D1, 0);
5721                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5722                        GS_UNIT_CLOCK_GATE_DISABLE |
5723                        CL_UNIT_CLOCK_GATE_DISABLE);
5724                 I915_WRITE(RAMCLK_GATE_D, 0);
5725                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5726                         OVRUNIT_CLOCK_GATE_DISABLE |
5727                         OVCUNIT_CLOCK_GATE_DISABLE;
5728                 if (IS_GM45(dev))
5729                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5730                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5731         } else if (IS_I965GM(dev)) {
5732                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5733                 I915_WRITE(RENCLK_GATE_D2, 0);
5734                 I915_WRITE(DSPCLK_GATE_D, 0);
5735                 I915_WRITE(RAMCLK_GATE_D, 0);
5736                 I915_WRITE16(DEUC, 0);
5737         } else if (IS_I965G(dev)) {
5738                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5739                        I965_RCC_CLOCK_GATE_DISABLE |
5740                        I965_RCPB_CLOCK_GATE_DISABLE |
5741                        I965_ISC_CLOCK_GATE_DISABLE |
5742                        I965_FBC_CLOCK_GATE_DISABLE);
5743                 I915_WRITE(RENCLK_GATE_D2, 0);
5744         } else if (IS_I9XX(dev)) {
5745                 u32 dstate = I915_READ(D_STATE);
5746
5747                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5748                         DSTATE_DOT_CLOCK_GATING;
5749                 I915_WRITE(D_STATE, dstate);
5750         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5751                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5752         } else if (IS_I830(dev)) {
5753                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5754         }
5755
5756         /*
5757          * GPU can automatically power down the render unit if given a page
5758          * to save state.
5759          */
5760         if (IS_IRONLAKE_M(dev)) {
5761                 if (dev_priv->renderctx == NULL)
5762                         dev_priv->renderctx = intel_alloc_context_page(dev);
5763                 if (dev_priv->renderctx) {
5764                         struct drm_i915_gem_object *obj_priv;
5765                         obj_priv = to_intel_bo(dev_priv->renderctx);
5766                         if (obj_priv) {
5767                                 BEGIN_LP_RING(4);
5768                                 OUT_RING(MI_SET_CONTEXT);
5769                                 OUT_RING(obj_priv->gtt_offset |
5770                                                 MI_MM_SPACE_GTT |
5771                                                 MI_SAVE_EXT_STATE_EN |
5772                                                 MI_RESTORE_EXT_STATE_EN |
5773                                                 MI_RESTORE_INHIBIT);
5774                                 OUT_RING(MI_NOOP);
5775                                 OUT_RING(MI_FLUSH);
5776                                 ADVANCE_LP_RING();
5777                         }
5778                 } else
5779                         DRM_DEBUG_KMS("Failed to allocate render context."
5780                                        "Disable RC6\n");
5781         }
5782
5783         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5784                 struct drm_i915_gem_object *obj_priv = NULL;
5785
5786                 if (dev_priv->pwrctx) {
5787                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5788                 } else {
5789                         struct drm_gem_object *pwrctx;
5790
5791                         pwrctx = intel_alloc_context_page(dev);
5792                         if (pwrctx) {
5793                                 dev_priv->pwrctx = pwrctx;
5794                                 obj_priv = to_intel_bo(pwrctx);
5795                         }
5796                 }
5797
5798                 if (obj_priv) {
5799                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5800                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5801                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5802                 }
5803         }
5804 }
5805
5806 /* Set up chip specific display functions */
5807 static void intel_init_display(struct drm_device *dev)
5808 {
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810
5811         /* We always want a DPMS function */
5812         if (HAS_PCH_SPLIT(dev))
5813                 dev_priv->display.dpms = ironlake_crtc_dpms;
5814         else
5815                 dev_priv->display.dpms = i9xx_crtc_dpms;
5816
5817         if (I915_HAS_FBC(dev)) {
5818                 if (IS_IRONLAKE_M(dev)) {
5819                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5820                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5821                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5822                 } else if (IS_GM45(dev)) {
5823                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5824                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5825                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5826                 } else if (IS_I965GM(dev)) {
5827                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5828                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5829                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5830                 }
5831                 /* 855GM needs testing */
5832         }
5833
5834         /* Returns the core display clock speed */
5835         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5836                 dev_priv->display.get_display_clock_speed =
5837                         i945_get_display_clock_speed;
5838         else if (IS_I915G(dev))
5839                 dev_priv->display.get_display_clock_speed =
5840                         i915_get_display_clock_speed;
5841         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5842                 dev_priv->display.get_display_clock_speed =
5843                         i9xx_misc_get_display_clock_speed;
5844         else if (IS_I915GM(dev))
5845                 dev_priv->display.get_display_clock_speed =
5846                         i915gm_get_display_clock_speed;
5847         else if (IS_I865G(dev))
5848                 dev_priv->display.get_display_clock_speed =
5849                         i865_get_display_clock_speed;
5850         else if (IS_I85X(dev))
5851                 dev_priv->display.get_display_clock_speed =
5852                         i855_get_display_clock_speed;
5853         else /* 852, 830 */
5854                 dev_priv->display.get_display_clock_speed =
5855                         i830_get_display_clock_speed;
5856
5857         /* For FIFO watermark updates */
5858         if (HAS_PCH_SPLIT(dev)) {
5859                 if (IS_IRONLAKE(dev)) {
5860                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5861                                 dev_priv->display.update_wm = ironlake_update_wm;
5862                         else {
5863                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5864                                               "Disable CxSR\n");
5865                                 dev_priv->display.update_wm = NULL;
5866                         }
5867                 } else
5868                         dev_priv->display.update_wm = NULL;
5869         } else if (IS_PINEVIEW(dev)) {
5870                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5871                                             dev_priv->is_ddr3,
5872                                             dev_priv->fsb_freq,
5873                                             dev_priv->mem_freq)) {
5874                         DRM_INFO("failed to find known CxSR latency "
5875                                  "(found ddr%s fsb freq %d, mem freq %d), "
5876                                  "disabling CxSR\n",
5877                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5878                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5879                         /* Disable CxSR and never update its watermark again */
5880                         pineview_disable_cxsr(dev);
5881                         dev_priv->display.update_wm = NULL;
5882                 } else
5883                         dev_priv->display.update_wm = pineview_update_wm;
5884         } else if (IS_G4X(dev))
5885                 dev_priv->display.update_wm = g4x_update_wm;
5886         else if (IS_I965G(dev))
5887                 dev_priv->display.update_wm = i965_update_wm;
5888         else if (IS_I9XX(dev)) {
5889                 dev_priv->display.update_wm = i9xx_update_wm;
5890                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5891         } else if (IS_I85X(dev)) {
5892                 dev_priv->display.update_wm = i9xx_update_wm;
5893                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5894         } else {
5895                 dev_priv->display.update_wm = i830_update_wm;
5896                 if (IS_845G(dev))
5897                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5898                 else
5899                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5900         }
5901 }
5902
5903 /*
5904  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5905  * resume, or other times.  This quirk makes sure that's the case for
5906  * affected systems.
5907  */
5908 static void quirk_pipea_force (struct drm_device *dev)
5909 {
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911
5912         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5913         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5914 }
5915
5916 struct intel_quirk {
5917         int device;
5918         int subsystem_vendor;
5919         int subsystem_device;
5920         void (*hook)(struct drm_device *dev);
5921 };
5922
5923 struct intel_quirk intel_quirks[] = {
5924         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5925         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5926         /* HP Mini needs pipe A force quirk (LP: #322104) */
5927         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5928
5929         /* Thinkpad R31 needs pipe A force quirk */
5930         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5931         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5932         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5933
5934         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5935         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5936         /* ThinkPad X40 needs pipe A force quirk */
5937
5938         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5939         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5940
5941         /* 855 & before need to leave pipe A & dpll A up */
5942         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5943         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5944 };
5945
5946 static void intel_init_quirks(struct drm_device *dev)
5947 {
5948         struct pci_dev *d = dev->pdev;
5949         int i;
5950
5951         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5952                 struct intel_quirk *q = &intel_quirks[i];
5953
5954                 if (d->device == q->device &&
5955                     (d->subsystem_vendor == q->subsystem_vendor ||
5956                      q->subsystem_vendor == PCI_ANY_ID) &&
5957                     (d->subsystem_device == q->subsystem_device ||
5958                      q->subsystem_device == PCI_ANY_ID))
5959                         q->hook(dev);
5960         }
5961 }
5962
5963 /* Disable the VGA plane that we never use */
5964 static void i915_disable_vga(struct drm_device *dev)
5965 {
5966         struct drm_i915_private *dev_priv = dev->dev_private;
5967         u8 sr1;
5968         u32 vga_reg;
5969
5970         if (HAS_PCH_SPLIT(dev))
5971                 vga_reg = CPU_VGACNTRL;
5972         else
5973                 vga_reg = VGACNTRL;
5974
5975         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5976         outb(1, VGA_SR_INDEX);
5977         sr1 = inb(VGA_SR_DATA);
5978         outb(sr1 | 1<<5, VGA_SR_DATA);
5979         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5980         udelay(300);
5981
5982         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5983         POSTING_READ(vga_reg);
5984 }
5985
5986 void intel_modeset_init(struct drm_device *dev)
5987 {
5988         struct drm_i915_private *dev_priv = dev->dev_private;
5989         int i;
5990
5991         drm_mode_config_init(dev);
5992
5993         dev->mode_config.min_width = 0;
5994         dev->mode_config.min_height = 0;
5995
5996         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5997
5998         intel_init_quirks(dev);
5999
6000         intel_init_display(dev);
6001
6002         if (IS_I965G(dev)) {
6003                 dev->mode_config.max_width = 8192;
6004                 dev->mode_config.max_height = 8192;
6005         } else if (IS_I9XX(dev)) {
6006                 dev->mode_config.max_width = 4096;
6007                 dev->mode_config.max_height = 4096;
6008         } else {
6009                 dev->mode_config.max_width = 2048;
6010                 dev->mode_config.max_height = 2048;
6011         }
6012
6013         /* set memory base */
6014         if (IS_I9XX(dev))
6015                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6016         else
6017                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6018
6019         if (IS_MOBILE(dev) || IS_I9XX(dev))
6020                 dev_priv->num_pipe = 2;
6021         else
6022                 dev_priv->num_pipe = 1;
6023         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6024                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6025
6026         for (i = 0; i < dev_priv->num_pipe; i++) {
6027                 intel_crtc_init(dev, i);
6028         }
6029
6030         intel_setup_outputs(dev);
6031
6032         intel_init_clock_gating(dev);
6033
6034         /* Just disable it once at startup */
6035         i915_disable_vga(dev);
6036
6037         if (IS_IRONLAKE_M(dev)) {
6038                 ironlake_enable_drps(dev);
6039                 intel_init_emon(dev);
6040         }
6041
6042         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6043         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6044                     (unsigned long)dev);
6045
6046         intel_setup_overlay(dev);
6047 }
6048
6049 void intel_modeset_cleanup(struct drm_device *dev)
6050 {
6051         struct drm_i915_private *dev_priv = dev->dev_private;
6052         struct drm_crtc *crtc;
6053         struct intel_crtc *intel_crtc;
6054
6055         mutex_lock(&dev->struct_mutex);
6056
6057         drm_kms_helper_poll_fini(dev);
6058         intel_fbdev_fini(dev);
6059
6060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6061                 /* Skip inactive CRTCs */
6062                 if (!crtc->fb)
6063                         continue;
6064
6065                 intel_crtc = to_intel_crtc(crtc);
6066                 intel_increase_pllclock(crtc, false);
6067                 del_timer_sync(&intel_crtc->idle_timer);
6068         }
6069
6070         del_timer_sync(&dev_priv->idle_timer);
6071
6072         if (dev_priv->display.disable_fbc)
6073                 dev_priv->display.disable_fbc(dev);
6074
6075         if (dev_priv->renderctx) {
6076                 struct drm_i915_gem_object *obj_priv;
6077
6078                 obj_priv = to_intel_bo(dev_priv->renderctx);
6079                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6080                 I915_READ(CCID);
6081                 i915_gem_object_unpin(dev_priv->renderctx);
6082                 drm_gem_object_unreference(dev_priv->renderctx);
6083         }
6084
6085         if (dev_priv->pwrctx) {
6086                 struct drm_i915_gem_object *obj_priv;
6087
6088                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6089                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6090                 I915_READ(PWRCTXA);
6091                 i915_gem_object_unpin(dev_priv->pwrctx);
6092                 drm_gem_object_unreference(dev_priv->pwrctx);
6093         }
6094
6095         if (IS_IRONLAKE_M(dev))
6096                 ironlake_disable_drps(dev);
6097
6098         mutex_unlock(&dev->struct_mutex);
6099
6100         drm_mode_config_cleanup(dev);
6101 }
6102
6103
6104 /*
6105  * Return which encoder is currently attached for connector.
6106  */
6107 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6108 {
6109         struct drm_mode_object *obj;
6110         struct drm_encoder *encoder;
6111         int i;
6112
6113         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6114                 if (connector->encoder_ids[i] == 0)
6115                         break;
6116
6117                 obj = drm_mode_object_find(connector->dev,
6118                                            connector->encoder_ids[i],
6119                                            DRM_MODE_OBJECT_ENCODER);
6120                 if (!obj)
6121                         continue;
6122
6123                 encoder = obj_to_encoder(obj);
6124                 return encoder;
6125         }
6126         return NULL;
6127 }
6128
6129 /*
6130  * set vga decode state - true == enable VGA decode
6131  */
6132 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6133 {
6134         struct drm_i915_private *dev_priv = dev->dev_private;
6135         u16 gmch_ctrl;
6136
6137         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6138         if (state)
6139                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6140         else
6141                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6142         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6143         return 0;
6144 }