drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         if (IS_GEN5(dev)) {
 349                 struct drm_i915_private *dev_priv = dev->dev_private;
 350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 351         } else
 352                 return 27;
 353 }
 354
 355 static const intel_limit_t intel_limits_i8xx_dvo = {
 356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 366         .find_pll = intel_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_i8xx_lvds = {
 370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 380         .find_pll = intel_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_i9xx_sdvo = {
 384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397 static const intel_limit_t intel_limits_i9xx_lvds = {
 398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 406         /* The single-channel range is 25-112Mhz, and dual-channel
 407          * is 80-224Mhz.  Prefer single channel as much as possible.
 408          */
 409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 411         .find_pll = intel_find_best_PLL,
 412 };
 413
 414     /* below parameter and function is for G4X Chipset Family*/
 415 static const intel_limit_t intel_limits_g4x_sdvo = {
 416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 425                  .p2_slow = G4X_P2_SDVO_SLOW,
 426                  .p2_fast = G4X_P2_SDVO_FAST
 427         },
 428         .find_pll = intel_g4x_find_best_PLL,
 429 };
 430
 431 static const intel_limit_t intel_limits_g4x_hdmi = {
 432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 443         },
 444         .find_pll = intel_g4x_find_best_PLL,
 445 };
 446
 447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 450         .vco = { .min = G4X_VCO_MIN,
 451                  .max = G4X_VCO_MAX },
 452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 467         },
 468         .find_pll = intel_g4x_find_best_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 474         .vco = { .min = G4X_VCO_MIN,
 475                  .max = G4X_VCO_MAX },
 476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 491         },
 492         .find_pll = intel_g4x_find_best_PLL,
 493 };
 494
 495 static const intel_limit_t intel_limits_g4x_display_port = {
 496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 498         .vco = { .min = G4X_VCO_MIN,
 499                  .max = G4X_VCO_MAX},
 500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 501                  .max = G4X_N_DISPLAY_PORT_MAX },
 502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 503                  .max = G4X_M_DISPLAY_PORT_MAX },
 504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 505                  .max = G4X_M1_DISPLAY_PORT_MAX },
 506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 507                  .max = G4X_M2_DISPLAY_PORT_MAX },
 508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 509                  .max = G4X_P_DISPLAY_PORT_MAX },
 510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 511                  .max = G4X_P1_DISPLAY_PORT_MAX},
 512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 515         .find_pll = intel_find_pll_g4x_dp,
 516 };
 517
 518 static const intel_limit_t intel_limits_pineview_sdvo = {
 519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 529         .find_pll = intel_find_best_PLL,
 530 };
 531
 532 static const intel_limit_t intel_limits_pineview_lvds = {
 533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 541         /* Pineview only supports single-channel mode. */
 542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 544         .find_pll = intel_find_best_PLL,
 545 };
 546
 547 static const intel_limit_t intel_limits_ironlake_dac = {
 548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 559         .find_pll = intel_g4x_find_best_PLL,
 560 };
 561
 562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 574         .find_pll = intel_g4x_find_best_PLL,
 575 };
 576
 577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 589         .find_pll = intel_g4x_find_best_PLL,
 590 };
 591
 592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 604         .find_pll = intel_g4x_find_best_PLL,
 605 };
 606
 607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 619         .find_pll = intel_g4x_find_best_PLL,
 620 };
 621
 622 static const intel_limit_t intel_limits_ironlake_display_port = {
 623         .dot = { .min = IRONLAKE_DOT_MIN,
 624                  .max = IRONLAKE_DOT_MAX },
 625         .vco = { .min = IRONLAKE_VCO_MIN,
 626                  .max = IRONLAKE_VCO_MAX},
 627         .n   = { .min = IRONLAKE_DP_N_MIN,
 628                  .max = IRONLAKE_DP_N_MAX },
 629         .m   = { .min = IRONLAKE_DP_M_MIN,
 630                  .max = IRONLAKE_DP_M_MAX },
 631         .m1  = { .min = IRONLAKE_M1_MIN,
 632                  .max = IRONLAKE_M1_MAX },
 633         .m2  = { .min = IRONLAKE_M2_MIN,
 634                  .max = IRONLAKE_M2_MAX },
 635         .p   = { .min = IRONLAKE_DP_P_MIN,
 636                  .max = IRONLAKE_DP_P_MAX },
 637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 638                  .max = IRONLAKE_DP_P1_MAX},
 639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 641                  .p2_fast = IRONLAKE_DP_P2_FAST },
 642         .find_pll = intel_find_pll_ironlake_dp,
 643 };
 644
 645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         struct drm_i915_private *dev_priv = dev->dev_private;
 649         const intel_limit_t *limit;
 650         int refclk = 120;
 651
 652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 654                         refclk = 100;
 655
 656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 657                     LVDS_CLKB_POWER_UP) {
 658                         /* LVDS dual channel */
 659                         if (refclk == 100)
 660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 661                         else
 662                                 limit = &intel_limits_ironlake_dual_lvds;
 663                 } else {
 664                         if (refclk == 100)
 665                                 limit = &intel_limits_ironlake_single_lvds_100m;
 666                         else
 667                                 limit = &intel_limits_ironlake_single_lvds;
 668                 }
 669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 670                         HAS_eDP)
 671                 limit = &intel_limits_ironlake_display_port;
 672         else
 673                 limit = &intel_limits_ironlake_dac;
 674
 675         return limit;
 676 }
 677
 678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         const intel_limit_t *limit;
 683
 684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 686                     LVDS_CLKB_POWER_UP)
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_dual_channel_lvds;
 689                 else
 690                         /* LVDS with dual channel */
 691                         limit = &intel_limits_g4x_single_channel_lvds;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 694                 limit = &intel_limits_g4x_hdmi;
 695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 696                 limit = &intel_limits_g4x_sdvo;
 697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 698                 limit = &intel_limits_g4x_display_port;
 699         } else /* The option is for other outputs */
 700                 limit = &intel_limits_i9xx_sdvo;
 701
 702         return limit;
 703 }
 704
 705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 706 {
 707         struct drm_device *dev = crtc->dev;
 708         const intel_limit_t *limit;
 709
 710         if (HAS_PCH_SPLIT(dev))
 711                 limit = intel_ironlake_limit(crtc);
 712         else if (IS_G4X(dev)) {
 713                 limit = intel_g4x_limit(crtc);
 714         } else if (IS_PINEVIEW(dev)) {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_pineview_lvds;
 717                 else
 718                         limit = &intel_limits_pineview_sdvo;
 719         } else if (!IS_GEN2(dev)) {
 720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 721                         limit = &intel_limits_i9xx_lvds;
 722                 else
 723                         limit = &intel_limits_i9xx_sdvo;
 724         } else {
 725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 726                         limit = &intel_limits_i8xx_lvds;
 727                 else
 728                         limit = &intel_limits_i8xx_dvo;
 729         }
 730         return limit;
 731 }
 732
 733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 734 static void pineview_clock(int refclk, intel_clock_t *clock)
 735 {
 736         clock->m = clock->m2 + 2;
 737         clock->p = clock->p1 * clock->p2;
 738         clock->vco = refclk * clock->m / clock->n;
 739         clock->dot = clock->vco / clock->p;
 740 }
 741
 742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 743 {
 744         if (IS_PINEVIEW(dev)) {
 745                 pineview_clock(refclk, clock);
 746                 return;
 747         }
 748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 749         clock->p = clock->p1 * clock->p2;
 750         clock->vco = refclk * clock->m / (clock->n + 2);
 751         clock->dot = clock->vco / clock->p;
 752 }
 753
 754 /**
 755  * Returns whether any output on the specified pipe is of the specified type
 756  */
 757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         struct drm_mode_config *mode_config = &dev->mode_config;
 761         struct intel_encoder *encoder;
 762
 763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 764                 if (encoder->base.crtc == crtc && encoder->type == type)
 765                         return true;
 766
 767         return false;
 768 }
 769
 770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 771 /**
 772  * Returns whether the given set of divisors are valid for a given refclk with
 773  * the given connectors.
 774  */
 775
 776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 777 {
 778         const intel_limit_t *limit = intel_limit (crtc);
 779         struct drm_device *dev = crtc->dev;
 780
 781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 782                 INTELPllInvalid ("p1 out of range\n");
 783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 784                 INTELPllInvalid ("p out of range\n");
 785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 786                 INTELPllInvalid ("m2 out of range\n");
 787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 788                 INTELPllInvalid ("m1 out of range\n");
 789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 790                 INTELPllInvalid ("m1 <= m2\n");
 791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 792                 INTELPllInvalid ("m out of range\n");
 793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 794                 INTELPllInvalid ("n out of range\n");
 795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 796                 INTELPllInvalid ("vco out of range\n");
 797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 798          * connector, etc., rather than just a single range.
 799          */
 800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 801                 INTELPllInvalid ("dot out of range\n");
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 808                     int target, int refclk, intel_clock_t *best_clock)
 809
 810 {
 811         struct drm_device *dev = crtc->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         intel_clock_t clock;
 814         int err = target;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 817             (I915_READ(LVDS)) != 0) {
 818                 /*
 819                  * For LVDS, if the panel is on, just rely on its current
 820                  * settings for dual-channel.  We haven't figured out how to
 821                  * reliably set up different single/dual channel state, if we
 822                  * even can.
 823                  */
 824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 825                     LVDS_CLKB_POWER_UP)
 826                         clock.p2 = limit->p2.p2_fast;
 827                 else
 828                         clock.p2 = limit->p2.p2_slow;
 829         } else {
 830                 if (target < limit->p2.dot_limit)
 831                         clock.p2 = limit->p2.p2_slow;
 832                 else
 833                         clock.p2 = limit->p2.p2_fast;
 834         }
 835
 836         memset (best_clock, 0, sizeof (*best_clock));
 837
 838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 839              clock.m1++) {
 840                 for (clock.m2 = limit->m2.min;
 841                      clock.m2 <= limit->m2.max; clock.m2++) {
 842                         /* m1 is always 0 in Pineview */
 843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 844                                 break;
 845                         for (clock.n = limit->n.min;
 846                              clock.n <= limit->n.max; clock.n++) {
 847                                 for (clock.p1 = limit->p1.min;
 848                                         clock.p1 <= limit->p1.max; clock.p1++) {
 849                                         int this_err;
 850
 851                                         intel_clock(dev, refclk, &clock);
 852
 853                                         if (!intel_PLL_is_valid(crtc, &clock))
 854                                                 continue;
 855
 856                                         this_err = abs(clock.dot - target);
 857                                         if (this_err < err) {
 858                                                 *best_clock = clock;
 859                                                 err = this_err;
 860                                         }
 861                                 }
 862                         }
 863                 }
 864         }
 865
 866         return (err != target);
 867 }
 868
 869 static bool
 870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *best_clock)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         intel_clock_t clock;
 876         int max_n;
 877         bool found;
 878         /* approximately equals target * 0.00585 */
 879         int err_most = (target >> 8) + (target >> 9);
 880         found = false;
 881
 882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 883                 int lvds_reg;
 884
 885                 if (HAS_PCH_SPLIT(dev))
 886                         lvds_reg = PCH_LVDS;
 887                 else
 888                         lvds_reg = LVDS;
 889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 890                     LVDS_CLKB_POWER_UP)
 891                         clock.p2 = limit->p2.p2_fast;
 892                 else
 893                         clock.p2 = limit->p2.p2_slow;
 894         } else {
 895                 if (target < limit->p2.dot_limit)
 896                         clock.p2 = limit->p2.p2_slow;
 897                 else
 898                         clock.p2 = limit->p2.p2_fast;
 899         }
 900
 901         memset(best_clock, 0, sizeof(*best_clock));
 902         max_n = limit->n.max;
 903         /* based on hardware requirement, prefer smaller n to precision */
 904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 905                 /* based on hardware requirement, prefere larger m1,m2 */
 906                 for (clock.m1 = limit->m1.max;
 907                      clock.m1 >= limit->m1.min; clock.m1--) {
 908                         for (clock.m2 = limit->m2.max;
 909                              clock.m2 >= limit->m2.min; clock.m2--) {
 910                                 for (clock.p1 = limit->p1.max;
 911                                      clock.p1 >= limit->p1.min; clock.p1--) {
 912                                         int this_err;
 913
 914                                         intel_clock(dev, refclk, &clock);
 915                                         if (!intel_PLL_is_valid(crtc, &clock))
 916                                                 continue;
 917                                         this_err = abs(clock.dot - target) ;
 918                                         if (this_err < err_most) {
 919                                                 *best_clock = clock;
 920                                                 err_most = this_err;
 921                                                 max_n = clock.n;
 922                                                 found = true;
 923                                         }
 924                                 }
 925                         }
 926                 }
 927         }
 928         return found;
 929 }
 930
 931 static bool
 932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 933                            int target, int refclk, intel_clock_t *best_clock)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         intel_clock_t clock;
 937
 938         if (target < 200000) {
 939                 clock.n = 1;
 940                 clock.p1 = 2;
 941                 clock.p2 = 10;
 942                 clock.m1 = 12;
 943                 clock.m2 = 9;
 944         } else {
 945                 clock.n = 2;
 946                 clock.p1 = 1;
 947                 clock.p2 = 10;
 948                 clock.m1 = 14;
 949                 clock.m2 = 8;
 950         }
 951         intel_clock(dev, refclk, &clock);
 952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 953         return true;
 954 }
 955
 956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 957 static bool
 958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 959                       int target, int refclk, intel_clock_t *best_clock)
 960 {
 961         intel_clock_t clock;
 962         if (target < 200000) {
 963                 clock.p1 = 2;
 964                 clock.p2 = 10;
 965                 clock.n = 2;
 966                 clock.m1 = 23;
 967                 clock.m2 = 8;
 968         } else {
 969                 clock.p1 = 1;
 970                 clock.p2 = 10;
 971                 clock.n = 1;
 972                 clock.m1 = 14;
 973                 clock.m2 = 2;
 974         }
 975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 976         clock.p = (clock.p1 * clock.p2);
 977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 978         clock.vco = 0;
 979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 980         return true;
 981 }
 982
 983 /**
 984  * intel_wait_for_vblank - wait for vblank on a given pipe
 985  * @dev: drm device
 986  * @pipe: pipe to wait for
 987  *
 988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 989  * mode setting code.
 990  */
 991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 995
 996         /* Clear existing vblank status. Note this will clear any other
 997          * sticky status fields as well.
 998          *
 999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment);
1465         if (ret)
1466                 return ret;
1467
1468         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469         if (ret)
1470                 goto err_unpin;
1471
1472         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473          * fence, whereas 965+ only requires a fence if using
1474          * framebuffer compression.  For simplicity, we always install
1475          * a fence as the cost is not that onerous.
1476          */
1477         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478             obj_priv->tiling_mode != I915_TILING_NONE) {
1479                 ret = i915_gem_object_get_fence_reg(obj, false);
1480                 if (ret)
1481                         goto err_unpin;
1482         }
1483
1484         return 0;
1485
1486 err_unpin:
1487         i915_gem_object_unpin(obj);
1488         return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494                            int x, int y, enum mode_set_atomic state)
1495 {
1496         struct drm_device *dev = crtc->dev;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499         struct intel_framebuffer *intel_fb;
1500         struct drm_i915_gem_object *obj_priv;
1501         struct drm_gem_object *obj;
1502         int plane = intel_crtc->plane;
1503         unsigned long Start, Offset;
1504         u32 dspcntr;
1505         u32 reg;
1506
1507         switch (plane) {
1508         case 0:
1509         case 1:
1510                 break;
1511         default:
1512                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513                 return -EINVAL;
1514         }
1515
1516         intel_fb = to_intel_framebuffer(fb);
1517         obj = intel_fb->obj;
1518         obj_priv = to_intel_bo(obj);
1519
1520         reg = DSPCNTR(plane);
1521         dspcntr = I915_READ(reg);
1522         /* Mask out pixel format bits in case we change it */
1523         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524         switch (fb->bits_per_pixel) {
1525         case 8:
1526                 dspcntr |= DISPPLANE_8BPP;
1527                 break;
1528         case 16:
1529                 if (fb->depth == 15)
1530                         dspcntr |= DISPPLANE_15_16BPP;
1531                 else
1532                         dspcntr |= DISPPLANE_16BPP;
1533                 break;
1534         case 24:
1535         case 32:
1536                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537                 break;
1538         default:
1539                 DRM_ERROR("Unknown color depth\n");
1540                 return -EINVAL;
1541         }
1542         if (INTEL_INFO(dev)->gen >= 4) {
1543                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544                         dspcntr |= DISPPLANE_TILED;
1545                 else
1546                         dspcntr &= ~DISPPLANE_TILED;
1547         }
1548
1549         if (HAS_PCH_SPLIT(dev))
1550                 /* must disable */
1551                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553         I915_WRITE(reg, dspcntr);
1554
1555         Start = obj_priv->gtt_offset;
1556         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559                       Start, Offset, x, y, fb->pitch);
1560         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561         if (INTEL_INFO(dev)->gen >= 4) {
1562                 I915_WRITE(DSPSURF(plane), Start);
1563                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564                 I915_WRITE(DSPADDR(plane), Offset);
1565         } else
1566                 I915_WRITE(DSPADDR(plane), Start + Offset);
1567         POSTING_READ(reg);
1568
1569         intel_update_fbc(dev);
1570         intel_increase_pllclock(crtc);
1571
1572         return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577                     struct drm_framebuffer *old_fb)
1578 {
1579         struct drm_device *dev = crtc->dev;
1580         struct drm_i915_master_private *master_priv;
1581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582         int ret;
1583
1584         /* no fb bound */
1585         if (!crtc->fb) {
1586                 DRM_DEBUG_KMS("No FB bound\n");
1587                 return 0;
1588         }
1589
1590         switch (intel_crtc->plane) {
1591         case 0:
1592         case 1:
1593                 break;
1594         default:
1595                 return -EINVAL;
1596         }
1597
1598         mutex_lock(&dev->struct_mutex);
1599         ret = intel_pin_and_fence_fb_obj(dev,
1600                                          to_intel_framebuffer(crtc->fb)->obj,
1601                                          false);
1602         if (ret != 0) {
1603                 mutex_unlock(&dev->struct_mutex);
1604                 return ret;
1605         }
1606
1607         if (old_fb) {
1608                 struct drm_i915_private *dev_priv = dev->dev_private;
1609                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612                 wait_event(dev_priv->pending_flip_queue,
1613                            atomic_read(&obj_priv->pending_flip) == 0);
1614         }
1615
1616         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1617                                          LEAVE_ATOMIC_MODE_SET);
1618         if (ret) {
1619                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1620                 mutex_unlock(&dev->struct_mutex);
1621                 return ret;
1622         }
1623
1624         if (old_fb)
1625                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1626
1627         mutex_unlock(&dev->struct_mutex);
1628
1629         if (!dev->primary->master)
1630                 return 0;
1631
1632         master_priv = dev->primary->master->driver_priv;
1633         if (!master_priv->sarea_priv)
1634                 return 0;
1635
1636         if (intel_crtc->pipe) {
1637                 master_priv->sarea_priv->pipeB_x = x;
1638                 master_priv->sarea_priv->pipeB_y = y;
1639         } else {
1640                 master_priv->sarea_priv->pipeA_x = x;
1641                 master_priv->sarea_priv->pipeA_y = y;
1642         }
1643
1644         return 0;
1645 }
1646
1647 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1648 {
1649         struct drm_device *dev = crtc->dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         u32 dpa_ctl;
1652
1653         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1654         dpa_ctl = I915_READ(DP_A);
1655         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1656
1657         if (clock < 200000) {
1658                 u32 temp;
1659                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1660                 /* workaround for 160Mhz:
1661                    1) program 0x4600c bits 15:0 = 0x8124
1662                    2) program 0x46010 bit 0 = 1
1663                    3) program 0x46034 bit 24 = 1
1664                    4) program 0x64000 bit 14 = 1
1665                    */
1666                 temp = I915_READ(0x4600c);
1667                 temp &= 0xffff0000;
1668                 I915_WRITE(0x4600c, temp | 0x8124);
1669
1670                 temp = I915_READ(0x46010);
1671                 I915_WRITE(0x46010, temp | 1);
1672
1673                 temp = I915_READ(0x46034);
1674                 I915_WRITE(0x46034, temp | (1 << 24));
1675         } else {
1676                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1677         }
1678         I915_WRITE(DP_A, dpa_ctl);
1679
1680         POSTING_READ(DP_A);
1681         udelay(500);
1682 }
1683
1684 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1689         int pipe = intel_crtc->pipe;
1690         u32 reg, temp;
1691
1692         /* enable normal train */
1693         reg = FDI_TX_CTL(pipe);
1694         temp = I915_READ(reg);
1695         temp &= ~FDI_LINK_TRAIN_NONE;
1696         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1697         I915_WRITE(reg, temp);
1698
1699         reg = FDI_RX_CTL(pipe);
1700         temp = I915_READ(reg);
1701         if (HAS_PCH_CPT(dev)) {
1702                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1703                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1704         } else {
1705                 temp &= ~FDI_LINK_TRAIN_NONE;
1706                 temp |= FDI_LINK_TRAIN_NONE;
1707         }
1708         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1709
1710         /* wait one idle pattern time */
1711         POSTING_READ(reg);
1712         udelay(1000);
1713 }
1714
1715 /* The FDI link training functions for ILK/Ibexpeak. */
1716 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1717 {
1718         struct drm_device *dev = crtc->dev;
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1721         int pipe = intel_crtc->pipe;
1722         u32 reg, temp, tries;
1723
1724         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1725            for train result */
1726         reg = FDI_RX_IMR(pipe);
1727         temp = I915_READ(reg);
1728         temp &= ~FDI_RX_SYMBOL_LOCK;
1729         temp &= ~FDI_RX_BIT_LOCK;
1730         I915_WRITE(reg, temp);
1731         I915_READ(reg);
1732         udelay(150);
1733
1734         /* enable CPU FDI TX and PCH FDI RX */
1735         reg = FDI_TX_CTL(pipe);
1736         temp = I915_READ(reg);
1737         temp &= ~(7 << 19);
1738         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1739         temp &= ~FDI_LINK_TRAIN_NONE;
1740         temp |= FDI_LINK_TRAIN_PATTERN_1;
1741         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1742
1743         reg = FDI_RX_CTL(pipe);
1744         temp = I915_READ(reg);
1745         temp &= ~FDI_LINK_TRAIN_NONE;
1746         temp |= FDI_LINK_TRAIN_PATTERN_1;
1747         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1748
1749         POSTING_READ(reg);
1750         udelay(150);
1751
1752         /* Ironlake workaround, enable clock pointer after FDI enable*/
1753         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1754
1755         reg = FDI_RX_IIR(pipe);
1756         for (tries = 0; tries < 5; tries++) {
1757                 temp = I915_READ(reg);
1758                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1759
1760                 if ((temp & FDI_RX_BIT_LOCK)) {
1761                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1762                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1763                         break;
1764                 }
1765         }
1766         if (tries == 5)
1767                 DRM_ERROR("FDI train 1 fail!\n");
1768
1769         /* Train 2 */
1770         reg = FDI_TX_CTL(pipe);
1771         temp = I915_READ(reg);
1772         temp &= ~FDI_LINK_TRAIN_NONE;
1773         temp |= FDI_LINK_TRAIN_PATTERN_2;
1774         I915_WRITE(reg, temp);
1775
1776         reg = FDI_RX_CTL(pipe);
1777         temp = I915_READ(reg);
1778         temp &= ~FDI_LINK_TRAIN_NONE;
1779         temp |= FDI_LINK_TRAIN_PATTERN_2;
1780         I915_WRITE(reg, temp);
1781
1782         POSTING_READ(reg);
1783         udelay(150);
1784
1785         reg = FDI_RX_IIR(pipe);
1786         for (tries = 0; tries < 5; tries++) {
1787                 temp = I915_READ(reg);
1788                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1789
1790                 if (temp & FDI_RX_SYMBOL_LOCK) {
1791                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1792                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1793                         break;
1794                 }
1795         }
1796         if (tries == 5)
1797                 DRM_ERROR("FDI train 2 fail!\n");
1798
1799         DRM_DEBUG_KMS("FDI train done\n");
1800
1801 }
1802
1803 static const int const snb_b_fdi_train_param [] = {
1804         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1805         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1806         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1807         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1808 };
1809
1810 /* The FDI link training functions for SNB/Cougarpoint. */
1811 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1812 {
1813         struct drm_device *dev = crtc->dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1816         int pipe = intel_crtc->pipe;
1817         u32 reg, temp, i;
1818
1819         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1820            for train result */
1821         reg = FDI_RX_IMR(pipe);
1822         temp = I915_READ(reg);
1823         temp &= ~FDI_RX_SYMBOL_LOCK;
1824         temp &= ~FDI_RX_BIT_LOCK;
1825         I915_WRITE(reg, temp);
1826
1827         POSTING_READ(reg);
1828         udelay(150);
1829
1830         /* enable CPU FDI TX and PCH FDI RX */
1831         reg = FDI_TX_CTL(pipe);
1832         temp = I915_READ(reg);
1833         temp &= ~(7 << 19);
1834         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1835         temp &= ~FDI_LINK_TRAIN_NONE;
1836         temp |= FDI_LINK_TRAIN_PATTERN_1;
1837         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838         /* SNB-B */
1839         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1840         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1841
1842         reg = FDI_RX_CTL(pipe);
1843         temp = I915_READ(reg);
1844         if (HAS_PCH_CPT(dev)) {
1845                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1846                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1847         } else {
1848                 temp &= ~FDI_LINK_TRAIN_NONE;
1849                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1850         }
1851         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1852
1853         POSTING_READ(reg);
1854         udelay(150);
1855
1856         for (i = 0; i < 4; i++ ) {
1857                 reg = FDI_TX_CTL(pipe);
1858                 temp = I915_READ(reg);
1859                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1860                 temp |= snb_b_fdi_train_param[i];
1861                 I915_WRITE(reg, temp);
1862
1863                 POSTING_READ(reg);
1864                 udelay(500);
1865
1866                 reg = FDI_RX_IIR(pipe);
1867                 temp = I915_READ(reg);
1868                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1869
1870                 if (temp & FDI_RX_BIT_LOCK) {
1871                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1872                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1873                         break;
1874                 }
1875         }
1876         if (i == 4)
1877                 DRM_ERROR("FDI train 1 fail!\n");
1878
1879         /* Train 2 */
1880         reg = FDI_TX_CTL(pipe);
1881         temp = I915_READ(reg);
1882         temp &= ~FDI_LINK_TRAIN_NONE;
1883         temp |= FDI_LINK_TRAIN_PATTERN_2;
1884         if (IS_GEN6(dev)) {
1885                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1886                 /* SNB-B */
1887                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1888         }
1889         I915_WRITE(reg, temp);
1890
1891         reg = FDI_RX_CTL(pipe);
1892         temp = I915_READ(reg);
1893         if (HAS_PCH_CPT(dev)) {
1894                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1895                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1896         } else {
1897                 temp &= ~FDI_LINK_TRAIN_NONE;
1898                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1899         }
1900         I915_WRITE(reg, temp);
1901
1902         POSTING_READ(reg);
1903         udelay(150);
1904
1905         for (i = 0; i < 4; i++ ) {
1906                 reg = FDI_TX_CTL(pipe);
1907                 temp = I915_READ(reg);
1908                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1909                 temp |= snb_b_fdi_train_param[i];
1910                 I915_WRITE(reg, temp);
1911
1912                 POSTING_READ(reg);
1913                 udelay(500);
1914
1915                 reg = FDI_RX_IIR(pipe);
1916                 temp = I915_READ(reg);
1917                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1918
1919                 if (temp & FDI_RX_SYMBOL_LOCK) {
1920                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1921                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1922                         break;
1923                 }
1924         }
1925         if (i == 4)
1926                 DRM_ERROR("FDI train 2 fail!\n");
1927
1928         DRM_DEBUG_KMS("FDI train done.\n");
1929 }
1930
1931 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1932 {
1933         struct drm_device *dev = crtc->dev;
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1936         int pipe = intel_crtc->pipe;
1937         u32 reg, temp;
1938
1939         /* Write the TU size bits so error detection works */
1940         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1941                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1942
1943         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1944         reg = FDI_RX_CTL(pipe);
1945         temp = I915_READ(reg);
1946         temp &= ~((0x7 << 19) | (0x7 << 16));
1947         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1948         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1949         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1950
1951         POSTING_READ(reg);
1952         udelay(200);
1953
1954         /* Switch from Rawclk to PCDclk */
1955         temp = I915_READ(reg);
1956         I915_WRITE(reg, temp | FDI_PCDCLK);
1957
1958         POSTING_READ(reg);
1959         udelay(200);
1960
1961         /* Enable CPU FDI TX PLL, always on for Ironlake */
1962         reg = FDI_TX_CTL(pipe);
1963         temp = I915_READ(reg);
1964         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1965                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1966
1967                 POSTING_READ(reg);
1968                 udelay(100);
1969         }
1970 }
1971
1972 static void intel_flush_display_plane(struct drm_device *dev,
1973                                       int plane)
1974 {
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         u32 reg = DSPADDR(plane);
1977         I915_WRITE(reg, I915_READ(reg));
1978 }
1979
1980 /*
1981  * When we disable a pipe, we need to clear any pending scanline wait events
1982  * to avoid hanging the ring, which we assume we are waiting on.
1983  */
1984 static void intel_clear_scanline_wait(struct drm_device *dev)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 tmp;
1988
1989         if (IS_GEN2(dev))
1990                 /* Can't break the hang on i8xx */
1991                 return;
1992
1993         tmp = I915_READ(PRB0_CTL);
1994         if (tmp & RING_WAIT) {
1995                 I915_WRITE(PRB0_CTL, tmp);
1996                 POSTING_READ(PRB0_CTL);
1997         }
1998 }
1999
2000 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2001 {
2002         struct drm_i915_gem_object *obj_priv;
2003         struct drm_i915_private *dev_priv;
2004
2005         if (crtc->fb == NULL)
2006                 return;
2007
2008         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2009         dev_priv = crtc->dev->dev_private;
2010         wait_event(dev_priv->pending_flip_queue,
2011                    atomic_read(&obj_priv->pending_flip) == 0);
2012 }
2013
2014 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2015 {
2016         struct drm_device *dev = crtc->dev;
2017         struct drm_i915_private *dev_priv = dev->dev_private;
2018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2019         int pipe = intel_crtc->pipe;
2020         int plane = intel_crtc->plane;
2021         u32 reg, temp;
2022
2023         if (intel_crtc->active)
2024                 return;
2025
2026         intel_crtc->active = true;
2027         intel_update_watermarks(dev);
2028
2029         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2030                 temp = I915_READ(PCH_LVDS);
2031                 if ((temp & LVDS_PORT_EN) == 0)
2032                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2033         }
2034
2035         ironlake_fdi_enable(crtc);
2036
2037         /* Enable panel fitting for LVDS */
2038         if (dev_priv->pch_pf_size &&
2039             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2040                 /* Force use of hard-coded filter coefficients
2041                  * as some pre-programmed values are broken,
2042                  * e.g. x201.
2043                  */
2044                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2045                            PF_ENABLE | PF_FILTER_MED_3x3);
2046                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2047                            dev_priv->pch_pf_pos);
2048                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2049                            dev_priv->pch_pf_size);
2050         }
2051
2052         /* Enable CPU pipe */
2053         reg = PIPECONF(pipe);
2054         temp = I915_READ(reg);
2055         if ((temp & PIPECONF_ENABLE) == 0) {
2056                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2057                 POSTING_READ(reg);
2058                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2059         }
2060
2061         /* configure and enable CPU plane */
2062         reg = DSPCNTR(plane);
2063         temp = I915_READ(reg);
2064         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2065                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2066                 intel_flush_display_plane(dev, plane);
2067         }
2068
2069         /* For PCH output, training FDI link */
2070         if (IS_GEN6(dev))
2071                 gen6_fdi_link_train(crtc);
2072         else
2073                 ironlake_fdi_link_train(crtc);
2074
2075         /* enable PCH DPLL */
2076         reg = PCH_DPLL(pipe);
2077         temp = I915_READ(reg);
2078         if ((temp & DPLL_VCO_ENABLE) == 0) {
2079                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2080                 POSTING_READ(reg);
2081                 udelay(200);
2082         }
2083
2084         if (HAS_PCH_CPT(dev)) {
2085                 /* Be sure PCH DPLL SEL is set */
2086                 temp = I915_READ(PCH_DPLL_SEL);
2087                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2088                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2089                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2090                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2091                 I915_WRITE(PCH_DPLL_SEL, temp);
2092         }
2093
2094         /* set transcoder timing */
2095         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2096         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2097         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2098
2099         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2100         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2101         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2102
2103         intel_fdi_normal_train(crtc);
2104
2105         /* For PCH DP, enable TRANS_DP_CTL */
2106         if (HAS_PCH_CPT(dev) &&
2107             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2108                 reg = TRANS_DP_CTL(pipe);
2109                 temp = I915_READ(reg);
2110                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2111                           TRANS_DP_SYNC_MASK);
2112                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2113                          TRANS_DP_ENH_FRAMING);
2114
2115                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2116                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2117                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2118                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2119
2120                 switch (intel_trans_dp_port_sel(crtc)) {
2121                 case PCH_DP_B:
2122                         temp |= TRANS_DP_PORT_SEL_B;
2123                         break;
2124                 case PCH_DP_C:
2125                         temp |= TRANS_DP_PORT_SEL_C;
2126                         break;
2127                 case PCH_DP_D:
2128                         temp |= TRANS_DP_PORT_SEL_D;
2129                         break;
2130                 default:
2131                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2132                         temp |= TRANS_DP_PORT_SEL_B;
2133                         break;
2134                 }
2135
2136                 I915_WRITE(reg, temp);
2137         }
2138
2139         /* enable PCH transcoder */
2140         reg = TRANSCONF(pipe);
2141         temp = I915_READ(reg);
2142         /*
2143          * make the BPC in transcoder be consistent with
2144          * that in pipeconf reg.
2145          */
2146         temp &= ~PIPE_BPC_MASK;
2147         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2148         I915_WRITE(reg, temp | TRANS_ENABLE);
2149         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2150                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2151
2152         intel_crtc_load_lut(crtc);
2153         intel_update_fbc(dev);
2154         intel_crtc_update_cursor(crtc, true);
2155 }
2156
2157 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         int pipe = intel_crtc->pipe;
2163         int plane = intel_crtc->plane;
2164         u32 reg, temp;
2165
2166         if (!intel_crtc->active)
2167                 return;
2168
2169         intel_crtc_wait_for_pending_flips(crtc);
2170         drm_vblank_off(dev, pipe);
2171         intel_crtc_update_cursor(crtc, false);
2172
2173         /* Disable display plane */
2174         reg = DSPCNTR(plane);
2175         temp = I915_READ(reg);
2176         if (temp & DISPLAY_PLANE_ENABLE) {
2177                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2178                 intel_flush_display_plane(dev, plane);
2179         }
2180
2181         if (dev_priv->cfb_plane == plane &&
2182             dev_priv->display.disable_fbc)
2183                 dev_priv->display.disable_fbc(dev);
2184
2185         /* disable cpu pipe, disable after all planes disabled */
2186         reg = PIPECONF(pipe);
2187         temp = I915_READ(reg);
2188         if (temp & PIPECONF_ENABLE) {
2189                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2190                 POSTING_READ(reg);
2191                 /* wait for cpu pipe off, pipe state */
2192                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2193         }
2194
2195         /* Disable PF */
2196         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2197         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2198
2199         /* disable CPU FDI tx and PCH FDI rx */
2200         reg = FDI_TX_CTL(pipe);
2201         temp = I915_READ(reg);
2202         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2203         POSTING_READ(reg);
2204
2205         reg = FDI_RX_CTL(pipe);
2206         temp = I915_READ(reg);
2207         temp &= ~(0x7 << 16);
2208         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2209         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2210
2211         POSTING_READ(reg);
2212         udelay(100);
2213
2214         /* Ironlake workaround, disable clock pointer after downing FDI */
2215         if (HAS_PCH_IBX(dev))
2216                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2217                            I915_READ(FDI_RX_CHICKEN(pipe) &
2218                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2219
2220         /* still set train pattern 1 */
2221         reg = FDI_TX_CTL(pipe);
2222         temp = I915_READ(reg);
2223         temp &= ~FDI_LINK_TRAIN_NONE;
2224         temp |= FDI_LINK_TRAIN_PATTERN_1;
2225         I915_WRITE(reg, temp);
2226
2227         reg = FDI_RX_CTL(pipe);
2228         temp = I915_READ(reg);
2229         if (HAS_PCH_CPT(dev)) {
2230                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2231                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2232         } else {
2233                 temp &= ~FDI_LINK_TRAIN_NONE;
2234                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2235         }
2236         /* BPC in FDI rx is consistent with that in PIPECONF */
2237         temp &= ~(0x07 << 16);
2238         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2239         I915_WRITE(reg, temp);
2240
2241         POSTING_READ(reg);
2242         udelay(100);
2243
2244         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2245                 temp = I915_READ(PCH_LVDS);
2246                 if (temp & LVDS_PORT_EN) {
2247                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2248                         POSTING_READ(PCH_LVDS);
2249                         udelay(100);
2250                 }
2251         }
2252
2253         /* disable PCH transcoder */
2254         reg = TRANSCONF(plane);
2255         temp = I915_READ(reg);
2256         if (temp & TRANS_ENABLE) {
2257                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2258                 /* wait for PCH transcoder off, transcoder state */
2259                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2260                         DRM_ERROR("failed to disable transcoder\n");
2261         }
2262
2263         if (HAS_PCH_CPT(dev)) {
2264                 /* disable TRANS_DP_CTL */
2265                 reg = TRANS_DP_CTL(pipe);
2266                 temp = I915_READ(reg);
2267                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2268                 I915_WRITE(reg, temp);
2269
2270                 /* disable DPLL_SEL */
2271                 temp = I915_READ(PCH_DPLL_SEL);
2272                 if (pipe == 0)
2273                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2274                 else
2275                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2276                 I915_WRITE(PCH_DPLL_SEL, temp);
2277         }
2278
2279         /* disable PCH DPLL */
2280         reg = PCH_DPLL(pipe);
2281         temp = I915_READ(reg);
2282         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2283
2284         /* Switch from PCDclk to Rawclk */
2285         reg = FDI_RX_CTL(pipe);
2286         temp = I915_READ(reg);
2287         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2288
2289         /* Disable CPU FDI TX PLL */
2290         reg = FDI_TX_CTL(pipe);
2291         temp = I915_READ(reg);
2292         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2293
2294         POSTING_READ(reg);
2295         udelay(100);
2296
2297         reg = FDI_RX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2300
2301         /* Wait for the clocks to turn off. */
2302         POSTING_READ(reg);
2303         udelay(100);
2304
2305         intel_crtc->active = false;
2306         intel_update_watermarks(dev);
2307         intel_update_fbc(dev);
2308         intel_clear_scanline_wait(dev);
2309 }
2310
2311 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2312 {
2313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314         int pipe = intel_crtc->pipe;
2315         int plane = intel_crtc->plane;
2316
2317         /* XXX: When our outputs are all unaware of DPMS modes other than off
2318          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2319          */
2320         switch (mode) {
2321         case DRM_MODE_DPMS_ON:
2322         case DRM_MODE_DPMS_STANDBY:
2323         case DRM_MODE_DPMS_SUSPEND:
2324                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2325                 ironlake_crtc_enable(crtc);
2326                 break;
2327
2328         case DRM_MODE_DPMS_OFF:
2329                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2330                 ironlake_crtc_disable(crtc);
2331                 break;
2332         }
2333 }
2334
2335 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2336 {
2337         if (!enable && intel_crtc->overlay) {
2338                 struct drm_device *dev = intel_crtc->base.dev;
2339
2340                 mutex_lock(&dev->struct_mutex);
2341                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2342                 mutex_unlock(&dev->struct_mutex);
2343         }
2344
2345         /* Let userspace switch the overlay on again. In most cases userspace
2346          * has to recompute where to put it anyway.
2347          */
2348 }
2349
2350 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2351 {
2352         struct drm_device *dev = crtc->dev;
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355         int pipe = intel_crtc->pipe;
2356         int plane = intel_crtc->plane;
2357         u32 reg, temp;
2358
2359         if (intel_crtc->active)
2360                 return;
2361
2362         intel_crtc->active = true;
2363         intel_update_watermarks(dev);
2364
2365         /* Enable the DPLL */
2366         reg = DPLL(pipe);
2367         temp = I915_READ(reg);
2368         if ((temp & DPLL_VCO_ENABLE) == 0) {
2369                 I915_WRITE(reg, temp);
2370
2371                 /* Wait for the clocks to stabilize. */
2372                 POSTING_READ(reg);
2373                 udelay(150);
2374
2375                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2376
2377                 /* Wait for the clocks to stabilize. */
2378                 POSTING_READ(reg);
2379                 udelay(150);
2380
2381                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2382
2383                 /* Wait for the clocks to stabilize. */
2384                 POSTING_READ(reg);
2385                 udelay(150);
2386         }
2387
2388         /* Enable the pipe */
2389         reg = PIPECONF(pipe);
2390         temp = I915_READ(reg);
2391         if ((temp & PIPECONF_ENABLE) == 0)
2392                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2393
2394         /* Enable the plane */
2395         reg = DSPCNTR(plane);
2396         temp = I915_READ(reg);
2397         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2398                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2399                 intel_flush_display_plane(dev, plane);
2400         }
2401
2402         intel_crtc_load_lut(crtc);
2403         intel_update_fbc(dev);
2404
2405         /* Give the overlay scaler a chance to enable if it's on this pipe */
2406         intel_crtc_dpms_overlay(intel_crtc, true);
2407         intel_crtc_update_cursor(crtc, true);
2408 }
2409
2410 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2411 {
2412         struct drm_device *dev = crtc->dev;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415         int pipe = intel_crtc->pipe;
2416         int plane = intel_crtc->plane;
2417         u32 reg, temp;
2418
2419         if (!intel_crtc->active)
2420                 return;
2421
2422         /* Give the overlay scaler a chance to disable if it's on this pipe */
2423         intel_crtc_wait_for_pending_flips(crtc);
2424         drm_vblank_off(dev, pipe);
2425         intel_crtc_dpms_overlay(intel_crtc, false);
2426         intel_crtc_update_cursor(crtc, false);
2427
2428         if (dev_priv->cfb_plane == plane &&
2429             dev_priv->display.disable_fbc)
2430                 dev_priv->display.disable_fbc(dev);
2431
2432         /* Disable display plane */
2433         reg = DSPCNTR(plane);
2434         temp = I915_READ(reg);
2435         if (temp & DISPLAY_PLANE_ENABLE) {
2436                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2437                 /* Flush the plane changes */
2438                 intel_flush_display_plane(dev, plane);
2439
2440                 /* Wait for vblank for the disable to take effect */
2441                 if (IS_GEN2(dev))
2442                         intel_wait_for_vblank(dev, pipe);
2443         }
2444
2445         /* Don't disable pipe A or pipe A PLLs if needed */
2446         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2447                 goto done;
2448
2449         /* Next, disable display pipes */
2450         reg = PIPECONF(pipe);
2451         temp = I915_READ(reg);
2452         if (temp & PIPECONF_ENABLE) {
2453                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2454
2455                 /* Wait for the pipe to turn off */
2456                 POSTING_READ(reg);
2457                 intel_wait_for_pipe_off(dev, pipe);
2458         }
2459
2460         reg = DPLL(pipe);
2461         temp = I915_READ(reg);
2462         if (temp & DPLL_VCO_ENABLE) {
2463                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2464
2465                 /* Wait for the clocks to turn off. */
2466                 POSTING_READ(reg);
2467                 udelay(150);
2468         }
2469
2470 done:
2471         intel_crtc->active = false;
2472         intel_update_fbc(dev);
2473         intel_update_watermarks(dev);
2474         intel_clear_scanline_wait(dev);
2475 }
2476
2477 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2478 {
2479         /* XXX: When our outputs are all unaware of DPMS modes other than off
2480          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2481          */
2482         switch (mode) {
2483         case DRM_MODE_DPMS_ON:
2484         case DRM_MODE_DPMS_STANDBY:
2485         case DRM_MODE_DPMS_SUSPEND:
2486                 i9xx_crtc_enable(crtc);
2487                 break;
2488         case DRM_MODE_DPMS_OFF:
2489                 i9xx_crtc_disable(crtc);
2490                 break;
2491         }
2492 }
2493
2494 /**
2495  * Sets the power management mode of the pipe and plane.
2496  */
2497 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2498 {
2499         struct drm_device *dev = crtc->dev;
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501         struct drm_i915_master_private *master_priv;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         int pipe = intel_crtc->pipe;
2504         bool enabled;
2505
2506         if (intel_crtc->dpms_mode == mode)
2507                 return;
2508
2509         intel_crtc->dpms_mode = mode;
2510
2511         dev_priv->display.dpms(crtc, mode);
2512
2513         if (!dev->primary->master)
2514                 return;
2515
2516         master_priv = dev->primary->master->driver_priv;
2517         if (!master_priv->sarea_priv)
2518                 return;
2519
2520         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2521
2522         switch (pipe) {
2523         case 0:
2524                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2525                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2526                 break;
2527         case 1:
2528                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2529                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2530                 break;
2531         default:
2532                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2533                 break;
2534         }
2535 }
2536
2537 static void intel_crtc_disable(struct drm_crtc *crtc)
2538 {
2539         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2540         struct drm_device *dev = crtc->dev;
2541
2542         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2543
2544         if (crtc->fb) {
2545                 mutex_lock(&dev->struct_mutex);
2546                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2547                 mutex_unlock(&dev->struct_mutex);
2548         }
2549 }
2550
2551 /* Prepare for a mode set.
2552  *
2553  * Note we could be a lot smarter here.  We need to figure out which outputs
2554  * will be enabled, which disabled (in short, how the config will changes)
2555  * and perform the minimum necessary steps to accomplish that, e.g. updating
2556  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2557  * panel fitting is in the proper state, etc.
2558  */
2559 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2560 {
2561         i9xx_crtc_disable(crtc);
2562 }
2563
2564 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2565 {
2566         i9xx_crtc_enable(crtc);
2567 }
2568
2569 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2570 {
2571         ironlake_crtc_disable(crtc);
2572 }
2573
2574 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2575 {
2576         ironlake_crtc_enable(crtc);
2577 }
2578
2579 void intel_encoder_prepare (struct drm_encoder *encoder)
2580 {
2581         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2582         /* lvds has its own version of prepare see intel_lvds_prepare */
2583         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2584 }
2585
2586 void intel_encoder_commit (struct drm_encoder *encoder)
2587 {
2588         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2589         /* lvds has its own version of commit see intel_lvds_commit */
2590         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2591 }
2592
2593 void intel_encoder_destroy(struct drm_encoder *encoder)
2594 {
2595         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2596
2597         drm_encoder_cleanup(encoder);
2598         kfree(intel_encoder);
2599 }
2600
2601 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2602                                   struct drm_display_mode *mode,
2603                                   struct drm_display_mode *adjusted_mode)
2604 {
2605         struct drm_device *dev = crtc->dev;
2606
2607         if (HAS_PCH_SPLIT(dev)) {
2608                 /* FDI link clock is fixed at 2.7G */
2609                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2610                         return false;
2611         }
2612
2613         /* XXX some encoders set the crtcinfo, others don't.
2614          * Obviously we need some form of conflict resolution here...
2615          */
2616         if (adjusted_mode->crtc_htotal == 0)
2617                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2618
2619         return true;
2620 }
2621
2622 static int i945_get_display_clock_speed(struct drm_device *dev)
2623 {
2624         return 400000;
2625 }
2626
2627 static int i915_get_display_clock_speed(struct drm_device *dev)
2628 {
2629         return 333000;
2630 }
2631
2632 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2633 {
2634         return 200000;
2635 }
2636
2637 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2638 {
2639         u16 gcfgc = 0;
2640
2641         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2642
2643         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2644                 return 133000;
2645         else {
2646                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2647                 case GC_DISPLAY_CLOCK_333_MHZ:
2648                         return 333000;
2649                 default:
2650                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2651                         return 190000;
2652                 }
2653         }
2654 }
2655
2656 static int i865_get_display_clock_speed(struct drm_device *dev)
2657 {
2658         return 266000;
2659 }
2660
2661 static int i855_get_display_clock_speed(struct drm_device *dev)
2662 {
2663         u16 hpllcc = 0;
2664         /* Assume that the hardware is in the high speed state.  This
2665          * should be the default.
2666          */
2667         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2668         case GC_CLOCK_133_200:
2669         case GC_CLOCK_100_200:
2670                 return 200000;
2671         case GC_CLOCK_166_250:
2672                 return 250000;
2673         case GC_CLOCK_100_133:
2674                 return 133000;
2675         }
2676
2677         /* Shouldn't happen */
2678         return 0;
2679 }
2680
2681 static int i830_get_display_clock_speed(struct drm_device *dev)
2682 {
2683         return 133000;
2684 }
2685
2686 struct fdi_m_n {
2687         u32        tu;
2688         u32        gmch_m;
2689         u32        gmch_n;
2690         u32        link_m;
2691         u32        link_n;
2692 };
2693
2694 static void
2695 fdi_reduce_ratio(u32 *num, u32 *den)
2696 {
2697         while (*num > 0xffffff || *den > 0xffffff) {
2698                 *num >>= 1;
2699                 *den >>= 1;
2700         }
2701 }
2702
2703 #define DATA_N 0x800000
2704 #define LINK_N 0x80000
2705
2706 static void
2707 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2708                      int link_clock, struct fdi_m_n *m_n)
2709 {
2710         u64 temp;
2711
2712         m_n->tu = 64; /* default size */
2713
2714         temp = (u64) DATA_N * pixel_clock;
2715         temp = div_u64(temp, link_clock);
2716         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2717         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2718         m_n->gmch_n = DATA_N;
2719         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2720
2721         temp = (u64) LINK_N * pixel_clock;
2722         m_n->link_m = div_u64(temp, link_clock);
2723         m_n->link_n = LINK_N;
2724         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2725 }
2726
2727
2728 struct intel_watermark_params {
2729         unsigned long fifo_size;
2730         unsigned long max_wm;
2731         unsigned long default_wm;
2732         unsigned long guard_size;
2733         unsigned long cacheline_size;
2734 };
2735
2736 /* Pineview has different values for various configs */
2737 static struct intel_watermark_params pineview_display_wm = {
2738         PINEVIEW_DISPLAY_FIFO,
2739         PINEVIEW_MAX_WM,
2740         PINEVIEW_DFT_WM,
2741         PINEVIEW_GUARD_WM,
2742         PINEVIEW_FIFO_LINE_SIZE
2743 };
2744 static struct intel_watermark_params pineview_display_hplloff_wm = {
2745         PINEVIEW_DISPLAY_FIFO,
2746         PINEVIEW_MAX_WM,
2747         PINEVIEW_DFT_HPLLOFF_WM,
2748         PINEVIEW_GUARD_WM,
2749         PINEVIEW_FIFO_LINE_SIZE
2750 };
2751 static struct intel_watermark_params pineview_cursor_wm = {
2752         PINEVIEW_CURSOR_FIFO,
2753         PINEVIEW_CURSOR_MAX_WM,
2754         PINEVIEW_CURSOR_DFT_WM,
2755         PINEVIEW_CURSOR_GUARD_WM,
2756         PINEVIEW_FIFO_LINE_SIZE,
2757 };
2758 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2759         PINEVIEW_CURSOR_FIFO,
2760         PINEVIEW_CURSOR_MAX_WM,
2761         PINEVIEW_CURSOR_DFT_WM,
2762         PINEVIEW_CURSOR_GUARD_WM,
2763         PINEVIEW_FIFO_LINE_SIZE
2764 };
2765 static struct intel_watermark_params g4x_wm_info = {
2766         G4X_FIFO_SIZE,
2767         G4X_MAX_WM,
2768         G4X_MAX_WM,
2769         2,
2770         G4X_FIFO_LINE_SIZE,
2771 };
2772 static struct intel_watermark_params g4x_cursor_wm_info = {
2773         I965_CURSOR_FIFO,
2774         I965_CURSOR_MAX_WM,
2775         I965_CURSOR_DFT_WM,
2776         2,
2777         G4X_FIFO_LINE_SIZE,
2778 };
2779 static struct intel_watermark_params i965_cursor_wm_info = {
2780         I965_CURSOR_FIFO,
2781         I965_CURSOR_MAX_WM,
2782         I965_CURSOR_DFT_WM,
2783         2,
2784         I915_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params i945_wm_info = {
2787         I945_FIFO_SIZE,
2788         I915_MAX_WM,
2789         1,
2790         2,
2791         I915_FIFO_LINE_SIZE
2792 };
2793 static struct intel_watermark_params i915_wm_info = {
2794         I915_FIFO_SIZE,
2795         I915_MAX_WM,
2796         1,
2797         2,
2798         I915_FIFO_LINE_SIZE
2799 };
2800 static struct intel_watermark_params i855_wm_info = {
2801         I855GM_FIFO_SIZE,
2802         I915_MAX_WM,
2803         1,
2804         2,
2805         I830_FIFO_LINE_SIZE
2806 };
2807 static struct intel_watermark_params i830_wm_info = {
2808         I830_FIFO_SIZE,
2809         I915_MAX_WM,
2810         1,
2811         2,
2812         I830_FIFO_LINE_SIZE
2813 };
2814
2815 static struct intel_watermark_params ironlake_display_wm_info = {
2816         ILK_DISPLAY_FIFO,
2817         ILK_DISPLAY_MAXWM,
2818         ILK_DISPLAY_DFTWM,
2819         2,
2820         ILK_FIFO_LINE_SIZE
2821 };
2822
2823 static struct intel_watermark_params ironlake_cursor_wm_info = {
2824         ILK_CURSOR_FIFO,
2825         ILK_CURSOR_MAXWM,
2826         ILK_CURSOR_DFTWM,
2827         2,
2828         ILK_FIFO_LINE_SIZE
2829 };
2830
2831 static struct intel_watermark_params ironlake_display_srwm_info = {
2832         ILK_DISPLAY_SR_FIFO,
2833         ILK_DISPLAY_MAX_SRWM,
2834         ILK_DISPLAY_DFT_SRWM,
2835         2,
2836         ILK_FIFO_LINE_SIZE
2837 };
2838
2839 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2840         ILK_CURSOR_SR_FIFO,
2841         ILK_CURSOR_MAX_SRWM,
2842         ILK_CURSOR_DFT_SRWM,
2843         2,
2844         ILK_FIFO_LINE_SIZE
2845 };
2846
2847 /**
2848  * intel_calculate_wm - calculate watermark level
2849  * @clock_in_khz: pixel clock
2850  * @wm: chip FIFO params
2851  * @pixel_size: display pixel size
2852  * @latency_ns: memory latency for the platform
2853  *
2854  * Calculate the watermark level (the level at which the display plane will
2855  * start fetching from memory again).  Each chip has a different display
2856  * FIFO size and allocation, so the caller needs to figure that out and pass
2857  * in the correct intel_watermark_params structure.
2858  *
2859  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2860  * on the pixel size.  When it reaches the watermark level, it'll start
2861  * fetching FIFO line sized based chunks from memory until the FIFO fills
2862  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2863  * will occur, and a display engine hang could result.
2864  */
2865 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2866                                         struct intel_watermark_params *wm,
2867                                         int pixel_size,
2868                                         unsigned long latency_ns)
2869 {
2870         long entries_required, wm_size;
2871
2872         /*
2873          * Note: we need to make sure we don't overflow for various clock &
2874          * latency values.
2875          * clocks go from a few thousand to several hundred thousand.
2876          * latency is usually a few thousand
2877          */
2878         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2879                 1000;
2880         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2881
2882         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2883
2884         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2885
2886         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2887
2888         /* Don't promote wm_size to unsigned... */
2889         if (wm_size > (long)wm->max_wm)
2890                 wm_size = wm->max_wm;
2891         if (wm_size <= 0)
2892                 wm_size = wm->default_wm;
2893         return wm_size;
2894 }
2895
2896 struct cxsr_latency {
2897         int is_desktop;
2898         int is_ddr3;
2899         unsigned long fsb_freq;
2900         unsigned long mem_freq;
2901         unsigned long display_sr;
2902         unsigned long display_hpll_disable;
2903         unsigned long cursor_sr;
2904         unsigned long cursor_hpll_disable;
2905 };
2906
2907 static const struct cxsr_latency cxsr_latency_table[] = {
2908         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2909         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2910         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2911         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2912         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2913
2914         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2915         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2916         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2917         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2918         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2919
2920         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2921         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2922         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2923         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2924         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2925
2926         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2927         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2928         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2929         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2930         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2931
2932         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2933         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2934         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2935         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2936         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2937
2938         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2939         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2940         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2941         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2942         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2943 };
2944
2945 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2946                                                          int is_ddr3,
2947                                                          int fsb,
2948                                                          int mem)
2949 {
2950         const struct cxsr_latency *latency;
2951         int i;
2952
2953         if (fsb == 0 || mem == 0)
2954                 return NULL;
2955
2956         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2957                 latency = &cxsr_latency_table[i];
2958                 if (is_desktop == latency->is_desktop &&
2959                     is_ddr3 == latency->is_ddr3 &&
2960                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2961                         return latency;
2962         }
2963
2964         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2965
2966         return NULL;
2967 }
2968
2969 static void pineview_disable_cxsr(struct drm_device *dev)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972
2973         /* deactivate cxsr */
2974         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2975 }
2976
2977 /*
2978  * Latency for FIFO fetches is dependent on several factors:
2979  *   - memory configuration (speed, channels)
2980  *   - chipset
2981  *   - current MCH state
2982  * It can be fairly high in some situations, so here we assume a fairly
2983  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2984  * set this value too high, the FIFO will fetch frequently to stay full)
2985  * and power consumption (set it too low to save power and we might see
2986  * FIFO underruns and display "flicker").
2987  *
2988  * A value of 5us seems to be a good balance; safe for very low end
2989  * platforms but not overly aggressive on lower latency configs.
2990  */
2991 static const int latency_ns = 5000;
2992
2993 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         uint32_t dsparb = I915_READ(DSPARB);
2997         int size;
2998
2999         size = dsparb & 0x7f;
3000         if (plane)
3001                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3002
3003         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3004                       plane ? "B" : "A", size);
3005
3006         return size;
3007 }
3008
3009 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3010 {
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         uint32_t dsparb = I915_READ(DSPARB);
3013         int size;
3014
3015         size = dsparb & 0x1ff;
3016         if (plane)
3017                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3018         size >>= 1; /* Convert to cachelines */
3019
3020         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3021                       plane ? "B" : "A", size);
3022
3023         return size;
3024 }
3025
3026 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3027 {
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         uint32_t dsparb = I915_READ(DSPARB);
3030         int size;
3031
3032         size = dsparb & 0x7f;
3033         size >>= 2; /* Convert to cachelines */
3034
3035         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3036                       plane ? "B" : "A",
3037                       size);
3038
3039         return size;
3040 }
3041
3042 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3043 {
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         uint32_t dsparb = I915_READ(DSPARB);
3046         int size;
3047
3048         size = dsparb & 0x7f;
3049         size >>= 1; /* Convert to cachelines */
3050
3051         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3052                       plane ? "B" : "A", size);
3053
3054         return size;
3055 }
3056
3057 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3058                                int planeb_clock, int sr_hdisplay, int unused,
3059                                int pixel_size)
3060 {
3061         struct drm_i915_private *dev_priv = dev->dev_private;
3062         const struct cxsr_latency *latency;
3063         u32 reg;
3064         unsigned long wm;
3065         int sr_clock;
3066
3067         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3068                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3069         if (!latency) {
3070                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3071                 pineview_disable_cxsr(dev);
3072                 return;
3073         }
3074
3075         if (!planea_clock || !planeb_clock) {
3076                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3077
3078                 /* Display SR */
3079                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3080                                         pixel_size, latency->display_sr);
3081                 reg = I915_READ(DSPFW1);
3082                 reg &= ~DSPFW_SR_MASK;
3083                 reg |= wm << DSPFW_SR_SHIFT;
3084                 I915_WRITE(DSPFW1, reg);
3085                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3086
3087                 /* cursor SR */
3088                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3089                                         pixel_size, latency->cursor_sr);
3090                 reg = I915_READ(DSPFW3);
3091                 reg &= ~DSPFW_CURSOR_SR_MASK;
3092                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3093                 I915_WRITE(DSPFW3, reg);
3094
3095                 /* Display HPLL off SR */
3096                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3097                                         pixel_size, latency->display_hpll_disable);
3098                 reg = I915_READ(DSPFW3);
3099                 reg &= ~DSPFW_HPLL_SR_MASK;
3100                 reg |= wm & DSPFW_HPLL_SR_MASK;
3101                 I915_WRITE(DSPFW3, reg);
3102
3103                 /* cursor HPLL off SR */
3104                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3105                                         pixel_size, latency->cursor_hpll_disable);
3106                 reg = I915_READ(DSPFW3);
3107                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3108                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3109                 I915_WRITE(DSPFW3, reg);
3110                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3111
3112                 /* activate cxsr */
3113                 I915_WRITE(DSPFW3,
3114                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3115                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3116         } else {
3117                 pineview_disable_cxsr(dev);
3118                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3119         }
3120 }
3121
3122 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3123                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3124                           int pixel_size)
3125 {
3126         struct drm_i915_private *dev_priv = dev->dev_private;
3127         int total_size, cacheline_size;
3128         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3129         struct intel_watermark_params planea_params, planeb_params;
3130         unsigned long line_time_us;
3131         int sr_clock, sr_entries = 0, entries_required;
3132
3133         /* Create copies of the base settings for each pipe */
3134         planea_params = planeb_params = g4x_wm_info;
3135
3136         /* Grab a couple of global values before we overwrite them */
3137         total_size = planea_params.fifo_size;
3138         cacheline_size = planea_params.cacheline_size;
3139
3140         /*
3141          * Note: we need to make sure we don't overflow for various clock &
3142          * latency values.
3143          * clocks go from a few thousand to several hundred thousand.
3144          * latency is usually a few thousand
3145          */
3146         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3147                 1000;
3148         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3149         planea_wm = entries_required + planea_params.guard_size;
3150
3151         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3152                 1000;
3153         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3154         planeb_wm = entries_required + planeb_params.guard_size;
3155
3156         cursora_wm = cursorb_wm = 16;
3157         cursor_sr = 32;
3158
3159         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3160
3161         /* Calc sr entries for one plane configs */
3162         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3163                 /* self-refresh has much higher latency */
3164                 static const int sr_latency_ns = 12000;
3165
3166                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3167                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3168
3169                 /* Use ns/us then divide to preserve precision */
3170                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3171                         pixel_size * sr_hdisplay;
3172                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3173
3174                 entries_required = (((sr_latency_ns / line_time_us) +
3175                                      1000) / 1000) * pixel_size * 64;
3176                 entries_required = DIV_ROUND_UP(entries_required,
3177                                                 g4x_cursor_wm_info.cacheline_size);
3178                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3179
3180                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3181                         cursor_sr = g4x_cursor_wm_info.max_wm;
3182                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3183                               "cursor %d\n", sr_entries, cursor_sr);
3184
3185                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3186         } else {
3187                 /* Turn off self refresh if both pipes are enabled */
3188                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3189                            & ~FW_BLC_SELF_EN);
3190         }
3191
3192         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3193                   planea_wm, planeb_wm, sr_entries);
3194
3195         planea_wm &= 0x3f;
3196         planeb_wm &= 0x3f;
3197
3198         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3199                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3200                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3201         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3202                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3203         /* HPLL off in SR has some issues on G4x... disable it */
3204         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3205                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3206 }
3207
3208 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3209                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3210                            int pixel_size)
3211 {
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         unsigned long line_time_us;
3214         int sr_clock, sr_entries, srwm = 1;
3215         int cursor_sr = 16;
3216
3217         /* Calc sr entries for one plane configs */
3218         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3219                 /* self-refresh has much higher latency */
3220                 static const int sr_latency_ns = 12000;
3221
3222                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3223                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3224
3225                 /* Use ns/us then divide to preserve precision */
3226                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3227                         pixel_size * sr_hdisplay;
3228                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3229                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3230                 srwm = I965_FIFO_SIZE - sr_entries;
3231                 if (srwm < 0)
3232                         srwm = 1;
3233                 srwm &= 0x1ff;
3234
3235                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3236                         pixel_size * 64;
3237                 sr_entries = DIV_ROUND_UP(sr_entries,
3238                                           i965_cursor_wm_info.cacheline_size);
3239                 cursor_sr = i965_cursor_wm_info.fifo_size -
3240                         (sr_entries + i965_cursor_wm_info.guard_size);
3241
3242                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3243                         cursor_sr = i965_cursor_wm_info.max_wm;
3244
3245                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3246                               "cursor %d\n", srwm, cursor_sr);
3247
3248                 if (IS_CRESTLINE(dev))
3249                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3250         } else {
3251                 /* Turn off self refresh if both pipes are enabled */
3252                 if (IS_CRESTLINE(dev))
3253                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3254                                    & ~FW_BLC_SELF_EN);
3255         }
3256
3257         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3258                       srwm);
3259
3260         /* 965 has limitations... */
3261         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3262                    (8 << 0));
3263         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3264         /* update cursor SR watermark */
3265         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3266 }
3267
3268 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3269                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3270                            int pixel_size)
3271 {
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273         uint32_t fwater_lo;
3274         uint32_t fwater_hi;
3275         int total_size, cacheline_size, cwm, srwm = 1;
3276         int planea_wm, planeb_wm;
3277         struct intel_watermark_params planea_params, planeb_params;
3278         unsigned long line_time_us;
3279         int sr_clock, sr_entries = 0;
3280
3281         /* Create copies of the base settings for each pipe */
3282         if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3283                 planea_params = planeb_params = i945_wm_info;
3284         else if (!IS_GEN2(dev))
3285                 planea_params = planeb_params = i915_wm_info;
3286         else
3287                 planea_params = planeb_params = i855_wm_info;
3288
3289         /* Grab a couple of global values before we overwrite them */
3290         total_size = planea_params.fifo_size;
3291         cacheline_size = planea_params.cacheline_size;
3292
3293         /* Update per-plane FIFO sizes */
3294         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3295         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3296
3297         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3298                                        pixel_size, latency_ns);
3299         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3300                                        pixel_size, latency_ns);
3301         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3302
3303         /*
3304          * Overlay gets an aggressive default since video jitter is bad.
3305          */
3306         cwm = 2;
3307
3308         /* Calc sr entries for one plane configs */
3309         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3310             (!planea_clock || !planeb_clock)) {
3311                 /* self-refresh has much higher latency */
3312                 static const int sr_latency_ns = 6000;
3313
3314                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3315                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3316
3317                 /* Use ns/us then divide to preserve precision */
3318                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3319                         pixel_size * sr_hdisplay;
3320                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3321                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3322                 srwm = total_size - sr_entries;
3323                 if (srwm < 0)
3324                         srwm = 1;
3325
3326                 if (IS_I945G(dev) || IS_I945GM(dev))
3327                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3328                 else if (IS_I915GM(dev)) {
3329                         /* 915M has a smaller SRWM field */
3330                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3331                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3332                 }
3333         } else {
3334                 /* Turn off self refresh if both pipes are enabled */
3335                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3336                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3337                                    & ~FW_BLC_SELF_EN);
3338                 } else if (IS_I915GM(dev)) {
3339                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3340                 }
3341         }
3342
3343         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3344                       planea_wm, planeb_wm, cwm, srwm);
3345
3346         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3347         fwater_hi = (cwm & 0x1f);
3348
3349         /* Set request length to 8 cachelines per fetch */
3350         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3351         fwater_hi = fwater_hi | (1 << 8);
3352
3353         I915_WRITE(FW_BLC, fwater_lo);
3354         I915_WRITE(FW_BLC2, fwater_hi);
3355 }
3356
3357 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3358                            int unused2, int unused3, int pixel_size)
3359 {
3360         struct drm_i915_private *dev_priv = dev->dev_private;
3361         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3362         int planea_wm;
3363
3364         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3365
3366         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3367                                        pixel_size, latency_ns);
3368         fwater_lo |= (3<<8) | planea_wm;
3369
3370         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3371
3372         I915_WRITE(FW_BLC, fwater_lo);
3373 }
3374
3375 #define ILK_LP0_PLANE_LATENCY           700
3376 #define ILK_LP0_CURSOR_LATENCY          1300
3377
3378 static bool ironlake_compute_wm0(struct drm_device *dev,
3379                                  int pipe,
3380                                  int *plane_wm,
3381                                  int *cursor_wm)
3382 {
3383         struct drm_crtc *crtc;
3384         int htotal, hdisplay, clock, pixel_size = 0;
3385         int line_time_us, line_count, entries;
3386
3387         crtc = intel_get_crtc_for_pipe(dev, pipe);
3388         if (crtc->fb == NULL || !crtc->enabled)
3389                 return false;
3390
3391         htotal = crtc->mode.htotal;
3392         hdisplay = crtc->mode.hdisplay;
3393         clock = crtc->mode.clock;
3394         pixel_size = crtc->fb->bits_per_pixel / 8;
3395
3396         /* Use the small buffer method to calculate plane watermark */
3397         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3398         entries = DIV_ROUND_UP(entries,
3399                                ironlake_display_wm_info.cacheline_size);
3400         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3401         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3402                 *plane_wm = ironlake_display_wm_info.max_wm;
3403
3404         /* Use the large buffer method to calculate cursor watermark */
3405         line_time_us = ((htotal * 1000) / clock);
3406         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3407         entries = line_count * 64 * pixel_size;
3408         entries = DIV_ROUND_UP(entries,
3409                                ironlake_cursor_wm_info.cacheline_size);
3410         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3411         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3412                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3413
3414         return true;
3415 }
3416
3417 static void ironlake_update_wm(struct drm_device *dev,
3418                                int planea_clock, int planeb_clock,
3419                                int sr_hdisplay, int sr_htotal,
3420                                int pixel_size)
3421 {
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         int plane_wm, cursor_wm, enabled;
3424         int tmp;
3425
3426         enabled = 0;
3427         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3428                 I915_WRITE(WM0_PIPEA_ILK,
3429                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3430                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3431                               " plane %d, " "cursor: %d\n",
3432                               plane_wm, cursor_wm);
3433                 enabled++;
3434         }
3435
3436         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3437                 I915_WRITE(WM0_PIPEB_ILK,
3438                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3439                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3440                               " plane %d, cursor: %d\n",
3441                               plane_wm, cursor_wm);
3442                 enabled++;
3443         }
3444
3445         /*
3446          * Calculate and update the self-refresh watermark only when one
3447          * display plane is used.
3448          */
3449         tmp = 0;
3450         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3451                 unsigned long line_time_us;
3452                 int small, large, plane_fbc;
3453                 int sr_clock, entries;
3454                 int line_count, line_size;
3455                 /* Read the self-refresh latency. The unit is 0.5us */
3456                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3457
3458                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3459                 line_time_us = (sr_htotal * 1000) / sr_clock;
3460
3461                 /* Use ns/us then divide to preserve precision */
3462                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3463                         / 1000;
3464                 line_size = sr_hdisplay * pixel_size;
3465
3466                 /* Use the minimum of the small and large buffer method for primary */
3467                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3468                 large = line_count * line_size;
3469
3470                 entries = DIV_ROUND_UP(min(small, large),
3471                                        ironlake_display_srwm_info.cacheline_size);
3472
3473                 plane_fbc = entries * 64;
3474                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3475
3476                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3477                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3478                         plane_wm = ironlake_display_srwm_info.max_wm;
3479
3480                 /* calculate the self-refresh watermark for display cursor */
3481                 entries = line_count * pixel_size * 64;
3482                 entries = DIV_ROUND_UP(entries,
3483                                        ironlake_cursor_srwm_info.cacheline_size);
3484
3485                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3486                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3487                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3488
3489                 /* configure watermark and enable self-refresh */
3490                 tmp = (WM1_LP_SR_EN |
3491                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3492                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3493                        (plane_wm << WM1_LP_SR_SHIFT) |
3494                        cursor_wm);
3495                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3496                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3497         }
3498         I915_WRITE(WM1_LP_ILK, tmp);
3499         /* XXX setup WM2 and WM3 */
3500 }
3501
3502 /**
3503  * intel_update_watermarks - update FIFO watermark values based on current modes
3504  *
3505  * Calculate watermark values for the various WM regs based on current mode
3506  * and plane configuration.
3507  *
3508  * There are several cases to deal with here:
3509  *   - normal (i.e. non-self-refresh)
3510  *   - self-refresh (SR) mode
3511  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3512  *   - lines are small relative to FIFO size (buffer can hold more than 2
3513  *     lines), so need to account for TLB latency
3514  *
3515  *   The normal calculation is:
3516  *     watermark = dotclock * bytes per pixel * latency
3517  *   where latency is platform & configuration dependent (we assume pessimal
3518  *   values here).
3519  *
3520  *   The SR calculation is:
3521  *     watermark = (trunc(latency/line time)+1) * surface width *
3522  *       bytes per pixel
3523  *   where
3524  *     line time = htotal / dotclock
3525  *     surface width = hdisplay for normal plane and 64 for cursor
3526  *   and latency is assumed to be high, as above.
3527  *
3528  * The final value programmed to the register should always be rounded up,
3529  * and include an extra 2 entries to account for clock crossings.
3530  *
3531  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3532  * to set the non-SR watermarks to 8.
3533  */
3534 static void intel_update_watermarks(struct drm_device *dev)
3535 {
3536         struct drm_i915_private *dev_priv = dev->dev_private;
3537         struct drm_crtc *crtc;
3538         int sr_hdisplay = 0;
3539         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3540         int enabled = 0, pixel_size = 0;
3541         int sr_htotal = 0;
3542
3543         if (!dev_priv->display.update_wm)
3544                 return;
3545
3546         /* Get the clock config from both planes */
3547         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3548                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3549                 if (intel_crtc->active) {
3550                         enabled++;
3551                         if (intel_crtc->plane == 0) {
3552                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3553                                               intel_crtc->pipe, crtc->mode.clock);
3554                                 planea_clock = crtc->mode.clock;
3555                         } else {
3556                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3557                                               intel_crtc->pipe, crtc->mode.clock);
3558                                 planeb_clock = crtc->mode.clock;
3559                         }
3560                         sr_hdisplay = crtc->mode.hdisplay;
3561                         sr_clock = crtc->mode.clock;
3562                         sr_htotal = crtc->mode.htotal;
3563                         if (crtc->fb)
3564                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3565                         else
3566                                 pixel_size = 4; /* by default */
3567                 }
3568         }
3569
3570         if (enabled <= 0)
3571                 return;
3572
3573         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3574                                     sr_hdisplay, sr_htotal, pixel_size);
3575 }
3576
3577 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3578                                struct drm_display_mode *mode,
3579                                struct drm_display_mode *adjusted_mode,
3580                                int x, int y,
3581                                struct drm_framebuffer *old_fb)
3582 {
3583         struct drm_device *dev = crtc->dev;
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586         int pipe = intel_crtc->pipe;
3587         int plane = intel_crtc->plane;
3588         u32 fp_reg, dpll_reg;
3589         int refclk, num_connectors = 0;
3590         intel_clock_t clock, reduced_clock;
3591         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3592         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3593         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3594         struct intel_encoder *has_edp_encoder = NULL;
3595         struct drm_mode_config *mode_config = &dev->mode_config;
3596         struct intel_encoder *encoder;
3597         const intel_limit_t *limit;
3598         int ret;
3599         struct fdi_m_n m_n = {0};
3600         u32 reg, temp;
3601         int target_clock;
3602
3603         drm_vblank_pre_modeset(dev, pipe);
3604
3605         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3606                 if (encoder->base.crtc != crtc)
3607                         continue;
3608
3609                 switch (encoder->type) {
3610                 case INTEL_OUTPUT_LVDS:
3611                         is_lvds = true;
3612                         break;
3613                 case INTEL_OUTPUT_SDVO:
3614                 case INTEL_OUTPUT_HDMI:
3615                         is_sdvo = true;
3616                         if (encoder->needs_tv_clock)
3617                                 is_tv = true;
3618                         break;
3619                 case INTEL_OUTPUT_DVO:
3620                         is_dvo = true;
3621                         break;
3622                 case INTEL_OUTPUT_TVOUT:
3623                         is_tv = true;
3624                         break;
3625                 case INTEL_OUTPUT_ANALOG:
3626                         is_crt = true;
3627                         break;
3628                 case INTEL_OUTPUT_DISPLAYPORT:
3629                         is_dp = true;
3630                         break;
3631                 case INTEL_OUTPUT_EDP:
3632                         has_edp_encoder = encoder;
3633                         break;
3634                 }
3635
3636                 num_connectors++;
3637         }
3638
3639         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3640                 refclk = dev_priv->lvds_ssc_freq * 1000;
3641                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3642                               refclk / 1000);
3643         } else if (!IS_GEN2(dev)) {
3644                 refclk = 96000;
3645                 if (HAS_PCH_SPLIT(dev) &&
3646                     (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3647                         refclk = 120000; /* 120Mhz refclk */
3648         } else {
3649                 refclk = 48000;
3650         }
3651
3652         /*
3653          * Returns a set of divisors for the desired target clock with the given
3654          * refclk, or FALSE.  The returned values represent the clock equation:
3655          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3656          */
3657         limit = intel_limit(crtc);
3658         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3659         if (!ok) {
3660                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3661                 drm_vblank_post_modeset(dev, pipe);
3662                 return -EINVAL;
3663         }
3664
3665         /* Ensure that the cursor is valid for the new mode before changing... */
3666         intel_crtc_update_cursor(crtc, true);
3667
3668         if (is_lvds && dev_priv->lvds_downclock_avail) {
3669                 has_reduced_clock = limit->find_pll(limit, crtc,
3670                                                     dev_priv->lvds_downclock,
3671                                                     refclk,
3672                                                     &reduced_clock);
3673                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3674                         /*
3675                          * If the different P is found, it means that we can't
3676                          * switch the display clock by using the FP0/FP1.
3677                          * In such case we will disable the LVDS downclock
3678                          * feature.
3679                          */
3680                         DRM_DEBUG_KMS("Different P is found for "
3681                                       "LVDS clock/downclock\n");
3682                         has_reduced_clock = 0;
3683                 }
3684         }
3685         /* SDVO TV has fixed PLL values depend on its clock range,
3686            this mirrors vbios setting. */
3687         if (is_sdvo && is_tv) {
3688                 if (adjusted_mode->clock >= 100000
3689                     && adjusted_mode->clock < 140500) {
3690                         clock.p1 = 2;
3691                         clock.p2 = 10;
3692                         clock.n = 3;
3693                         clock.m1 = 16;
3694                         clock.m2 = 8;
3695                 } else if (adjusted_mode->clock >= 140500
3696                            && adjusted_mode->clock <= 200000) {
3697                         clock.p1 = 1;
3698                         clock.p2 = 10;
3699                         clock.n = 6;
3700                         clock.m1 = 12;
3701                         clock.m2 = 8;
3702                 }
3703         }
3704
3705         /* FDI link */
3706         if (HAS_PCH_SPLIT(dev)) {
3707                 int lane = 0, link_bw, bpp;
3708                 /* CPU eDP doesn't require FDI link, so just set DP M/N
3709                    according to current link config */
3710                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3711                         target_clock = mode->clock;
3712                         intel_edp_link_config(has_edp_encoder,
3713                                               &lane, &link_bw);
3714                 } else {
3715                         /* [e]DP over FDI requires target mode clock
3716                            instead of link clock */
3717                         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3718                                 target_clock = mode->clock;
3719                         else
3720                                 target_clock = adjusted_mode->clock;
3721
3722                         /* FDI is a binary signal running at ~2.7GHz, encoding
3723                          * each output octet as 10 bits. The actual frequency
3724                          * is stored as a divider into a 100MHz clock, and the
3725                          * mode pixel clock is stored in units of 1KHz.
3726                          * Hence the bw of each lane in terms of the mode signal
3727                          * is:
3728                          */
3729                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3730                 }
3731
3732                 /* determine panel color depth */
3733                 temp = I915_READ(PIPECONF(pipe));
3734                 temp &= ~PIPE_BPC_MASK;
3735                 if (is_lvds) {
3736                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3737                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3738                                 temp |= PIPE_8BPC;
3739                         else
3740                                 temp |= PIPE_6BPC;
3741                 } else if (has_edp_encoder) {
3742                         switch (dev_priv->edp.bpp/3) {
3743                         case 8:
3744                                 temp |= PIPE_8BPC;
3745                                 break;
3746                         case 10:
3747                                 temp |= PIPE_10BPC;
3748                                 break;
3749                         case 6:
3750                                 temp |= PIPE_6BPC;
3751                                 break;
3752                         case 12:
3753                                 temp |= PIPE_12BPC;
3754                                 break;
3755                         }
3756                 } else
3757                         temp |= PIPE_8BPC;
3758                 I915_WRITE(PIPECONF(pipe), temp);
3759
3760                 switch (temp & PIPE_BPC_MASK) {
3761                 case PIPE_8BPC:
3762                         bpp = 24;
3763                         break;
3764                 case PIPE_10BPC:
3765                         bpp = 30;
3766                         break;
3767                 case PIPE_6BPC:
3768                         bpp = 18;
3769                         break;
3770                 case PIPE_12BPC:
3771                         bpp = 36;
3772                         break;
3773                 default:
3774                         DRM_ERROR("unknown pipe bpc value\n");
3775                         bpp = 24;
3776                 }
3777
3778                 if (!lane) {
3779                         /*
3780                          * Account for spread spectrum to avoid
3781                          * oversubscribing the link. Max center spread
3782                          * is 2.5%; use 5% for safety's sake.
3783                          */
3784                         u32 bps = target_clock * bpp * 21 / 20;
3785                         lane = bps / (link_bw * 8) + 1;
3786                 }
3787
3788                 intel_crtc->fdi_lanes = lane;
3789
3790                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3791         }
3792
3793         /* Ironlake: try to setup display ref clock before DPLL
3794          * enabling. This is only under driver's control after
3795          * PCH B stepping, previous chipset stepping should be
3796          * ignoring this setting.
3797          */
3798         if (HAS_PCH_SPLIT(dev)) {
3799                 temp = I915_READ(PCH_DREF_CONTROL);
3800                 /* Always enable nonspread source */
3801                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3802                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3803                 temp &= ~DREF_SSC_SOURCE_MASK;
3804                 temp |= DREF_SSC_SOURCE_ENABLE;
3805                 I915_WRITE(PCH_DREF_CONTROL, temp);
3806
3807                 POSTING_READ(PCH_DREF_CONTROL);
3808                 udelay(200);
3809
3810                 if (has_edp_encoder) {
3811                         if (dev_priv->lvds_use_ssc) {
3812                                 temp |= DREF_SSC1_ENABLE;
3813                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3814
3815                                 POSTING_READ(PCH_DREF_CONTROL);
3816                                 udelay(200);
3817                         }
3818                         temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3819
3820                         /* Enable CPU source on CPU attached eDP */
3821                         if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3822                                 if (dev_priv->lvds_use_ssc)
3823                                         temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3824                                 else
3825                                         temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3826                         } else {
3827                                 /* Enable SSC on PCH eDP if needed */
3828                                 if (dev_priv->lvds_use_ssc) {
3829                                         DRM_ERROR("enabling SSC on PCH\n");
3830                                         temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3831                                 }
3832                         }
3833                         I915_WRITE(PCH_DREF_CONTROL, temp);
3834                         POSTING_READ(PCH_DREF_CONTROL);
3835                         udelay(200);
3836                 }
3837         }
3838
3839         if (IS_PINEVIEW(dev)) {
3840                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3841                 if (has_reduced_clock)
3842                         fp2 = (1 << reduced_clock.n) << 16 |
3843                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3844         } else {
3845                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3846                 if (has_reduced_clock)
3847                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3848                                 reduced_clock.m2;
3849         }
3850
3851         dpll = 0;
3852         if (!HAS_PCH_SPLIT(dev))
3853                 dpll = DPLL_VGA_MODE_DIS;
3854
3855         if (!IS_GEN2(dev)) {
3856                 if (is_lvds)
3857                         dpll |= DPLLB_MODE_LVDS;
3858                 else
3859                         dpll |= DPLLB_MODE_DAC_SERIAL;
3860                 if (is_sdvo) {
3861                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3862                         if (pixel_multiplier > 1) {
3863                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3864                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3865                                 else if (HAS_PCH_SPLIT(dev))
3866                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3867                         }
3868                         dpll |= DPLL_DVO_HIGH_SPEED;
3869                 }
3870                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3871                         dpll |= DPLL_DVO_HIGH_SPEED;
3872
3873                 /* compute bitmask from p1 value */
3874                 if (IS_PINEVIEW(dev))
3875                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3876                 else {
3877                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3878                         /* also FPA1 */
3879                         if (HAS_PCH_SPLIT(dev))
3880                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3881                         if (IS_G4X(dev) && has_reduced_clock)
3882                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3883                 }
3884                 switch (clock.p2) {
3885                 case 5:
3886                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3887                         break;
3888                 case 7:
3889                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3890                         break;
3891                 case 10:
3892                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3893                         break;
3894                 case 14:
3895                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3896                         break;
3897                 }
3898                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3899                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3900         } else {
3901                 if (is_lvds) {
3902                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3903                 } else {
3904                         if (clock.p1 == 2)
3905                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3906                         else
3907                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3908                         if (clock.p2 == 4)
3909                                 dpll |= PLL_P2_DIVIDE_BY_4;
3910                 }
3911         }
3912
3913         if (is_sdvo && is_tv)
3914                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3915         else if (is_tv)
3916                 /* XXX: just matching BIOS for now */
3917                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3918                 dpll |= 3;
3919         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3920                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3921         else
3922                 dpll |= PLL_REF_INPUT_DREFCLK;
3923
3924         /* setup pipeconf */
3925         pipeconf = I915_READ(PIPECONF(pipe));
3926
3927         /* Set up the display plane register */
3928         dspcntr = DISPPLANE_GAMMA_ENABLE;
3929
3930         /* Ironlake's plane is forced to pipe, bit 24 is to
3931            enable color space conversion */
3932         if (!HAS_PCH_SPLIT(dev)) {
3933                 if (pipe == 0)
3934                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3935                 else
3936                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3937         }
3938
3939         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3940                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3941                  * core speed.
3942                  *
3943                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3944                  * pipe == 0 check?
3945                  */
3946                 if (mode->clock >
3947                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3948                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3949                 else
3950                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3951         }
3952
3953         dspcntr |= DISPLAY_PLANE_ENABLE;
3954         pipeconf |= PIPECONF_ENABLE;
3955         dpll |= DPLL_VCO_ENABLE;
3956
3957         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3958         drm_mode_debug_printmodeline(mode);
3959
3960         /* assign to Ironlake registers */
3961         if (HAS_PCH_SPLIT(dev)) {
3962                 fp_reg = PCH_FP0(pipe);
3963                 dpll_reg = PCH_DPLL(pipe);
3964         } else {
3965                 fp_reg = FP0(pipe);
3966                 dpll_reg = DPLL(pipe);
3967         }
3968
3969         /* PCH eDP needs FDI, but CPU eDP does not */
3970         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3971                 I915_WRITE(fp_reg, fp);
3972                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3973
3974                 POSTING_READ(dpll_reg);
3975                 udelay(150);
3976         }
3977
3978         /* enable transcoder DPLL */
3979         if (HAS_PCH_CPT(dev)) {
3980                 temp = I915_READ(PCH_DPLL_SEL);
3981                 if (pipe == 0)
3982                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3983                 else
3984                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3985                 I915_WRITE(PCH_DPLL_SEL, temp);
3986
3987                 POSTING_READ(PCH_DPLL_SEL);
3988                 udelay(150);
3989         }
3990
3991         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3992          * This is an exception to the general rule that mode_set doesn't turn
3993          * things on.
3994          */
3995         if (is_lvds) {
3996                 reg = LVDS;
3997                 if (HAS_PCH_SPLIT(dev))
3998                         reg = PCH_LVDS;
3999
4000                 temp = I915_READ(reg);
4001                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4002                 if (pipe == 1) {
4003                         if (HAS_PCH_CPT(dev))
4004                                 temp |= PORT_TRANS_B_SEL_CPT;
4005                         else
4006                                 temp |= LVDS_PIPEB_SELECT;
4007                 } else {
4008                         if (HAS_PCH_CPT(dev))
4009                                 temp &= ~PORT_TRANS_SEL_MASK;
4010                         else
4011                                 temp &= ~LVDS_PIPEB_SELECT;
4012                 }
4013                 /* set the corresponsding LVDS_BORDER bit */
4014                 temp |= dev_priv->lvds_border_bits;
4015                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4016                  * set the DPLLs for dual-channel mode or not.
4017                  */
4018                 if (clock.p2 == 7)
4019                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4020                 else
4021                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4022
4023                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4024                  * appropriately here, but we need to look more thoroughly into how
4025                  * panels behave in the two modes.
4026                  */
4027                 /* set the dithering flag on non-PCH LVDS as needed */
4028                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4029                         if (dev_priv->lvds_dither)
4030                                 temp |= LVDS_ENABLE_DITHER;
4031                         else
4032                                 temp &= ~LVDS_ENABLE_DITHER;
4033                 }
4034                 I915_WRITE(reg, temp);
4035         }
4036
4037         /* set the dithering flag and clear for anything other than a panel. */
4038         if (HAS_PCH_SPLIT(dev)) {
4039                 pipeconf &= ~PIPECONF_DITHER_EN;
4040                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4041                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4042                         pipeconf |= PIPECONF_DITHER_EN;
4043                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4044                 }
4045         }
4046
4047         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4048                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4049         } else if (HAS_PCH_SPLIT(dev)) {
4050                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4051                 if (pipe == 0) {
4052                         I915_WRITE(TRANSA_DATA_M1, 0);
4053                         I915_WRITE(TRANSA_DATA_N1, 0);
4054                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4055                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4056                 } else {
4057                         I915_WRITE(TRANSB_DATA_M1, 0);
4058                         I915_WRITE(TRANSB_DATA_N1, 0);
4059                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4060                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4061                 }
4062         }
4063
4064         if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4065                 I915_WRITE(fp_reg, fp);
4066                 I915_WRITE(dpll_reg, dpll);
4067
4068                 /* Wait for the clocks to stabilize. */
4069                 POSTING_READ(dpll_reg);
4070                 udelay(150);
4071
4072                 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4073                         temp = 0;
4074                         if (is_sdvo) {
4075                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4076                                 if (temp > 1)
4077                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4078                                 else
4079                                         temp = 0;
4080                         }
4081                         I915_WRITE(DPLL_MD(pipe), temp);
4082                 } else {
4083                         /* write it again -- the BIOS does, after all */
4084                         I915_WRITE(dpll_reg, dpll);
4085                 }
4086
4087                 /* Wait for the clocks to stabilize. */
4088                 POSTING_READ(dpll_reg);
4089                 udelay(150);
4090         }
4091
4092         intel_crtc->lowfreq_avail = false;
4093         if (is_lvds && has_reduced_clock && i915_powersave) {
4094                 I915_WRITE(fp_reg + 4, fp2);
4095                 intel_crtc->lowfreq_avail = true;
4096                 if (HAS_PIPE_CXSR(dev)) {
4097                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4098                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4099                 }
4100         } else {
4101                 I915_WRITE(fp_reg + 4, fp);
4102                 if (HAS_PIPE_CXSR(dev)) {
4103                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4104                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4105                 }
4106         }
4107
4108         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4109                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4110                 /* the chip adds 2 halflines automatically */
4111                 adjusted_mode->crtc_vdisplay -= 1;
4112                 adjusted_mode->crtc_vtotal -= 1;
4113                 adjusted_mode->crtc_vblank_start -= 1;
4114                 adjusted_mode->crtc_vblank_end -= 1;
4115                 adjusted_mode->crtc_vsync_end -= 1;
4116                 adjusted_mode->crtc_vsync_start -= 1;
4117         } else
4118                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4119
4120         I915_WRITE(HTOTAL(pipe),
4121                    (adjusted_mode->crtc_hdisplay - 1) |
4122                    ((adjusted_mode->crtc_htotal - 1) << 16));
4123         I915_WRITE(HBLANK(pipe),
4124                    (adjusted_mode->crtc_hblank_start - 1) |
4125                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4126         I915_WRITE(HSYNC(pipe),
4127                    (adjusted_mode->crtc_hsync_start - 1) |
4128                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4129
4130         I915_WRITE(VTOTAL(pipe),
4131                    (adjusted_mode->crtc_vdisplay - 1) |
4132                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4133         I915_WRITE(VBLANK(pipe),
4134                    (adjusted_mode->crtc_vblank_start - 1) |
4135                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4136         I915_WRITE(VSYNC(pipe),
4137                    (adjusted_mode->crtc_vsync_start - 1) |
4138                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4139
4140         /* pipesrc and dspsize control the size that is scaled from,
4141          * which should always be the user's requested size.
4142          */
4143         if (!HAS_PCH_SPLIT(dev)) {
4144                 I915_WRITE(DSPSIZE(plane),
4145                            ((mode->vdisplay - 1) << 16) |
4146                            (mode->hdisplay - 1));
4147                 I915_WRITE(DSPPOS(plane), 0);
4148         }
4149         I915_WRITE(PIPESRC(pipe),
4150                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4151
4152         if (HAS_PCH_SPLIT(dev)) {
4153                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4154                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4155                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4156                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4157
4158                 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4159                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4160                 }
4161         }
4162
4163         I915_WRITE(PIPECONF(pipe), pipeconf);
4164         POSTING_READ(PIPECONF(pipe));
4165
4166         intel_wait_for_vblank(dev, pipe);
4167
4168         if (IS_GEN5(dev)) {
4169                 /* enable address swizzle for tiling buffer */
4170                 temp = I915_READ(DISP_ARB_CTL);
4171                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4172         }
4173
4174         I915_WRITE(DSPCNTR(plane), dspcntr);
4175
4176         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4177
4178         intel_update_watermarks(dev);
4179
4180         drm_vblank_post_modeset(dev, pipe);
4181
4182         return ret;
4183 }
4184
4185 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4186 void intel_crtc_load_lut(struct drm_crtc *crtc)
4187 {
4188         struct drm_device *dev = crtc->dev;
4189         struct drm_i915_private *dev_priv = dev->dev_private;
4190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4191         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4192         int i;
4193
4194         /* The clocks have to be on to load the palette. */
4195         if (!crtc->enabled)
4196                 return;
4197
4198         /* use legacy palette for Ironlake */
4199         if (HAS_PCH_SPLIT(dev))
4200                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4201                                                    LGC_PALETTE_B;
4202
4203         for (i = 0; i < 256; i++) {
4204                 I915_WRITE(palreg + 4 * i,
4205                            (intel_crtc->lut_r[i] << 16) |
4206                            (intel_crtc->lut_g[i] << 8) |
4207                            intel_crtc->lut_b[i]);
4208         }
4209 }
4210
4211 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4212 {
4213         struct drm_device *dev = crtc->dev;
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216         bool visible = base != 0;
4217         u32 cntl;
4218
4219         if (intel_crtc->cursor_visible == visible)
4220                 return;
4221
4222         cntl = I915_READ(CURACNTR);
4223         if (visible) {
4224                 /* On these chipsets we can only modify the base whilst
4225                  * the cursor is disabled.
4226                  */
4227                 I915_WRITE(CURABASE, base);
4228
4229                 cntl &= ~(CURSOR_FORMAT_MASK);
4230                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4231                 cntl |= CURSOR_ENABLE |
4232                         CURSOR_GAMMA_ENABLE |
4233                         CURSOR_FORMAT_ARGB;
4234         } else
4235                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4236         I915_WRITE(CURACNTR, cntl);
4237
4238         intel_crtc->cursor_visible = visible;
4239 }
4240
4241 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4242 {
4243         struct drm_device *dev = crtc->dev;
4244         struct drm_i915_private *dev_priv = dev->dev_private;
4245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4246         int pipe = intel_crtc->pipe;
4247         bool visible = base != 0;
4248
4249         if (intel_crtc->cursor_visible != visible) {
4250                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4251                 if (base) {
4252                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4253                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4254                         cntl |= pipe << 28; /* Connect to correct pipe */
4255                 } else {
4256                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4257                         cntl |= CURSOR_MODE_DISABLE;
4258                 }
4259                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4260
4261                 intel_crtc->cursor_visible = visible;
4262         }
4263         /* and commit changes on next vblank */
4264         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4265 }
4266
4267 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4268 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4269                                      bool on)
4270 {
4271         struct drm_device *dev = crtc->dev;
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4274         int pipe = intel_crtc->pipe;
4275         int x = intel_crtc->cursor_x;
4276         int y = intel_crtc->cursor_y;
4277         u32 base, pos;
4278         bool visible;
4279
4280         pos = 0;
4281
4282         if (on && crtc->enabled && crtc->fb) {
4283                 base = intel_crtc->cursor_addr;
4284                 if (x > (int) crtc->fb->width)
4285                         base = 0;
4286
4287                 if (y > (int) crtc->fb->height)
4288                         base = 0;
4289         } else
4290                 base = 0;
4291
4292         if (x < 0) {
4293                 if (x + intel_crtc->cursor_width < 0)
4294                         base = 0;
4295
4296                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4297                 x = -x;
4298         }
4299         pos |= x << CURSOR_X_SHIFT;
4300
4301         if (y < 0) {
4302                 if (y + intel_crtc->cursor_height < 0)
4303                         base = 0;
4304
4305                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4306                 y = -y;
4307         }
4308         pos |= y << CURSOR_Y_SHIFT;
4309
4310         visible = base != 0;
4311         if (!visible && !intel_crtc->cursor_visible)
4312                 return;
4313
4314         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4315         if (IS_845G(dev) || IS_I865G(dev))
4316                 i845_update_cursor(crtc, base);
4317         else
4318                 i9xx_update_cursor(crtc, base);
4319
4320         if (visible)
4321                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4322 }
4323
4324 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4325                                  struct drm_file *file_priv,
4326                                  uint32_t handle,
4327                                  uint32_t width, uint32_t height)
4328 {
4329         struct drm_device *dev = crtc->dev;
4330         struct drm_i915_private *dev_priv = dev->dev_private;
4331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332         struct drm_gem_object *bo;
4333         struct drm_i915_gem_object *obj_priv;
4334         uint32_t addr;
4335         int ret;
4336
4337         DRM_DEBUG_KMS("\n");
4338
4339         /* if we want to turn off the cursor ignore width and height */
4340         if (!handle) {
4341                 DRM_DEBUG_KMS("cursor off\n");
4342                 addr = 0;
4343                 bo = NULL;
4344                 mutex_lock(&dev->struct_mutex);
4345                 goto finish;
4346         }
4347
4348         /* Currently we only support 64x64 cursors */
4349         if (width != 64 || height != 64) {
4350                 DRM_ERROR("we currently only support 64x64 cursors\n");
4351                 return -EINVAL;
4352         }
4353
4354         bo = drm_gem_object_lookup(dev, file_priv, handle);
4355         if (!bo)
4356                 return -ENOENT;
4357
4358         obj_priv = to_intel_bo(bo);
4359
4360         if (bo->size < width * height * 4) {
4361                 DRM_ERROR("buffer is to small\n");
4362                 ret = -ENOMEM;
4363                 goto fail;
4364         }
4365
4366         /* we only need to pin inside GTT if cursor is non-phy */
4367         mutex_lock(&dev->struct_mutex);
4368         if (!dev_priv->info->cursor_needs_physical) {
4369                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4370                 if (ret) {
4371                         DRM_ERROR("failed to pin cursor bo\n");
4372                         goto fail_locked;
4373                 }
4374
4375                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4376                 if (ret) {
4377                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4378                         goto fail_unpin;
4379                 }
4380
4381                 addr = obj_priv->gtt_offset;
4382         } else {
4383                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4384                 ret = i915_gem_attach_phys_object(dev, bo,
4385                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4386                                                   align);
4387                 if (ret) {
4388                         DRM_ERROR("failed to attach phys object\n");
4389                         goto fail_locked;
4390                 }
4391                 addr = obj_priv->phys_obj->handle->busaddr;
4392         }
4393
4394         if (IS_GEN2(dev))
4395                 I915_WRITE(CURSIZE, (height << 12) | width);
4396
4397  finish:
4398         if (intel_crtc->cursor_bo) {
4399                 if (dev_priv->info->cursor_needs_physical) {
4400                         if (intel_crtc->cursor_bo != bo)
4401                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4402                 } else
4403                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4404                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4405         }
4406
4407         mutex_unlock(&dev->struct_mutex);
4408
4409         intel_crtc->cursor_addr = addr;
4410         intel_crtc->cursor_bo = bo;
4411         intel_crtc->cursor_width = width;
4412         intel_crtc->cursor_height = height;
4413
4414         intel_crtc_update_cursor(crtc, true);
4415
4416         return 0;
4417 fail_unpin:
4418         i915_gem_object_unpin(bo);
4419 fail_locked:
4420         mutex_unlock(&dev->struct_mutex);
4421 fail:
4422         drm_gem_object_unreference_unlocked(bo);
4423         return ret;
4424 }
4425
4426 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4427 {
4428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4429
4430         intel_crtc->cursor_x = x;
4431         intel_crtc->cursor_y = y;
4432
4433         intel_crtc_update_cursor(crtc, true);
4434
4435         return 0;
4436 }
4437
4438 /** Sets the color ramps on behalf of RandR */
4439 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4440                                  u16 blue, int regno)
4441 {
4442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443
4444         intel_crtc->lut_r[regno] = red >> 8;
4445         intel_crtc->lut_g[regno] = green >> 8;
4446         intel_crtc->lut_b[regno] = blue >> 8;
4447 }
4448
4449 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4450                              u16 *blue, int regno)
4451 {
4452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4453
4454         *red = intel_crtc->lut_r[regno] << 8;
4455         *green = intel_crtc->lut_g[regno] << 8;
4456         *blue = intel_crtc->lut_b[regno] << 8;
4457 }
4458
4459 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4460                                  u16 *blue, uint32_t start, uint32_t size)
4461 {
4462         int end = (start + size > 256) ? 256 : start + size, i;
4463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4464
4465         for (i = start; i < end; i++) {
4466                 intel_crtc->lut_r[i] = red[i] >> 8;
4467                 intel_crtc->lut_g[i] = green[i] >> 8;
4468                 intel_crtc->lut_b[i] = blue[i] >> 8;
4469         }
4470
4471         intel_crtc_load_lut(crtc);
4472 }
4473
4474 /**
4475  * Get a pipe with a simple mode set on it for doing load-based monitor
4476  * detection.
4477  *
4478  * It will be up to the load-detect code to adjust the pipe as appropriate for
4479  * its requirements.  The pipe will be connected to no other encoders.
4480  *
4481  * Currently this code will only succeed if there is a pipe with no encoders
4482  * configured for it.  In the future, it could choose to temporarily disable
4483  * some outputs to free up a pipe for its use.
4484  *
4485  * \return crtc, or NULL if no pipes are available.
4486  */
4487
4488 /* VESA 640x480x72Hz mode to set on the pipe */
4489 static struct drm_display_mode load_detect_mode = {
4490         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4491                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4492 };
4493
4494 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4495                                             struct drm_connector *connector,
4496                                             struct drm_display_mode *mode,
4497                                             int *dpms_mode)
4498 {
4499         struct intel_crtc *intel_crtc;
4500         struct drm_crtc *possible_crtc;
4501         struct drm_crtc *supported_crtc =NULL;
4502         struct drm_encoder *encoder = &intel_encoder->base;
4503         struct drm_crtc *crtc = NULL;
4504         struct drm_device *dev = encoder->dev;
4505         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4506         struct drm_crtc_helper_funcs *crtc_funcs;
4507         int i = -1;
4508
4509         /*
4510          * Algorithm gets a little messy:
4511          *   - if the connector already has an assigned crtc, use it (but make
4512          *     sure it's on first)
4513          *   - try to find the first unused crtc that can drive this connector,
4514          *     and use that if we find one
4515          *   - if there are no unused crtcs available, try to use the first
4516          *     one we found that supports the connector
4517          */
4518
4519         /* See if we already have a CRTC for this connector */
4520         if (encoder->crtc) {
4521                 crtc = encoder->crtc;
4522                 /* Make sure the crtc and connector are running */
4523                 intel_crtc = to_intel_crtc(crtc);
4524                 *dpms_mode = intel_crtc->dpms_mode;
4525                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4526                         crtc_funcs = crtc->helper_private;
4527                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4528                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4529                 }
4530                 return crtc;
4531         }
4532
4533         /* Find an unused one (if possible) */
4534         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4535                 i++;
4536                 if (!(encoder->possible_crtcs & (1 << i)))
4537                         continue;
4538                 if (!possible_crtc->enabled) {
4539                         crtc = possible_crtc;
4540                         break;
4541                 }
4542                 if (!supported_crtc)
4543                         supported_crtc = possible_crtc;
4544         }
4545
4546         /*
4547          * If we didn't find an unused CRTC, don't use any.
4548          */
4549         if (!crtc) {
4550                 return NULL;
4551         }
4552
4553         encoder->crtc = crtc;
4554         connector->encoder = encoder;
4555         intel_encoder->load_detect_temp = true;
4556
4557         intel_crtc = to_intel_crtc(crtc);
4558         *dpms_mode = intel_crtc->dpms_mode;
4559
4560         if (!crtc->enabled) {
4561                 if (!mode)
4562                         mode = &load_detect_mode;
4563                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4564         } else {
4565                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4566                         crtc_funcs = crtc->helper_private;
4567                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4568                 }
4569
4570                 /* Add this connector to the crtc */
4571                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4572                 encoder_funcs->commit(encoder);
4573         }
4574         /* let the connector get through one full cycle before testing */
4575         intel_wait_for_vblank(dev, intel_crtc->pipe);
4576
4577         return crtc;
4578 }
4579
4580 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4581                                     struct drm_connector *connector, int dpms_mode)
4582 {
4583         struct drm_encoder *encoder = &intel_encoder->base;
4584         struct drm_device *dev = encoder->dev;
4585         struct drm_crtc *crtc = encoder->crtc;
4586         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4587         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4588
4589         if (intel_encoder->load_detect_temp) {
4590                 encoder->crtc = NULL;
4591                 connector->encoder = NULL;
4592                 intel_encoder->load_detect_temp = false;
4593                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4594                 drm_helper_disable_unused_functions(dev);
4595         }
4596
4597         /* Switch crtc and encoder back off if necessary */
4598         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4599                 if (encoder->crtc == crtc)
4600                         encoder_funcs->dpms(encoder, dpms_mode);
4601                 crtc_funcs->dpms(crtc, dpms_mode);
4602         }
4603 }
4604
4605 /* Returns the clock of the currently programmed mode of the given pipe. */
4606 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4607 {
4608         struct drm_i915_private *dev_priv = dev->dev_private;
4609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4610         int pipe = intel_crtc->pipe;
4611         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4612         u32 fp;
4613         intel_clock_t clock;
4614
4615         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4616                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4617         else
4618                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4619
4620         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4621         if (IS_PINEVIEW(dev)) {
4622                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4623                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4624         } else {
4625                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4626                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4627         }
4628
4629         if (!IS_GEN2(dev)) {
4630                 if (IS_PINEVIEW(dev))
4631                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4632                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4633                 else
4634                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4635                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4636
4637                 switch (dpll & DPLL_MODE_MASK) {
4638                 case DPLLB_MODE_DAC_SERIAL:
4639                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4640                                 5 : 10;
4641                         break;
4642                 case DPLLB_MODE_LVDS:
4643                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4644                                 7 : 14;
4645                         break;
4646                 default:
4647                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4648                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4649                         return 0;
4650                 }
4651
4652                 /* XXX: Handle the 100Mhz refclk */
4653                 intel_clock(dev, 96000, &clock);
4654         } else {
4655                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4656
4657                 if (is_lvds) {
4658                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4659                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4660                         clock.p2 = 14;
4661
4662                         if ((dpll & PLL_REF_INPUT_MASK) ==
4663                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4664                                 /* XXX: might not be 66MHz */
4665                                 intel_clock(dev, 66000, &clock);
4666                         } else
4667                                 intel_clock(dev, 48000, &clock);
4668                 } else {
4669                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4670                                 clock.p1 = 2;
4671                         else {
4672                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4673                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4674                         }
4675                         if (dpll & PLL_P2_DIVIDE_BY_4)
4676                                 clock.p2 = 4;
4677                         else
4678                                 clock.p2 = 2;
4679
4680                         intel_clock(dev, 48000, &clock);
4681                 }
4682         }
4683
4684         /* XXX: It would be nice to validate the clocks, but we can't reuse
4685          * i830PllIsValid() because it relies on the xf86_config connector
4686          * configuration being accurate, which it isn't necessarily.
4687          */
4688
4689         return clock.dot;
4690 }
4691
4692 /** Returns the currently programmed mode of the given pipe. */
4693 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4694                                              struct drm_crtc *crtc)
4695 {
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698         int pipe = intel_crtc->pipe;
4699         struct drm_display_mode *mode;
4700         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4701         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4702         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4703         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4704
4705         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4706         if (!mode)
4707                 return NULL;
4708
4709         mode->clock = intel_crtc_clock_get(dev, crtc);
4710         mode->hdisplay = (htot & 0xffff) + 1;
4711         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4712         mode->hsync_start = (hsync & 0xffff) + 1;
4713         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4714         mode->vdisplay = (vtot & 0xffff) + 1;
4715         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4716         mode->vsync_start = (vsync & 0xffff) + 1;
4717         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4718
4719         drm_mode_set_name(mode);
4720         drm_mode_set_crtcinfo(mode, 0);
4721
4722         return mode;
4723 }
4724
4725 #define GPU_IDLE_TIMEOUT 500 /* ms */
4726
4727 /* When this timer fires, we've been idle for awhile */
4728 static void intel_gpu_idle_timer(unsigned long arg)
4729 {
4730         struct drm_device *dev = (struct drm_device *)arg;
4731         drm_i915_private_t *dev_priv = dev->dev_private;
4732
4733         dev_priv->busy = false;
4734
4735         queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4739
4740 static void intel_crtc_idle_timer(unsigned long arg)
4741 {
4742         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4743         struct drm_crtc *crtc = &intel_crtc->base;
4744         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4745
4746         intel_crtc->busy = false;
4747
4748         queue_work(dev_priv->wq, &dev_priv->idle_work);
4749 }
4750
4751 static void intel_increase_pllclock(struct drm_crtc *crtc)
4752 {
4753         struct drm_device *dev = crtc->dev;
4754         drm_i915_private_t *dev_priv = dev->dev_private;
4755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756         int pipe = intel_crtc->pipe;
4757         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4758         int dpll = I915_READ(dpll_reg);
4759
4760         if (HAS_PCH_SPLIT(dev))
4761                 return;
4762
4763         if (!dev_priv->lvds_downclock_avail)
4764                 return;
4765
4766         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4767                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4768
4769                 /* Unlock panel regs */
4770                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4771                            PANEL_UNLOCK_REGS);
4772
4773                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4774                 I915_WRITE(dpll_reg, dpll);
4775                 dpll = I915_READ(dpll_reg);
4776                 intel_wait_for_vblank(dev, pipe);
4777                 dpll = I915_READ(dpll_reg);
4778                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4779                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4780
4781                 /* ...and lock them again */
4782                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4783         }
4784
4785         /* Schedule downclock */
4786         mod_timer(&intel_crtc->idle_timer, jiffies +
4787                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4788 }
4789
4790 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4791 {
4792         struct drm_device *dev = crtc->dev;
4793         drm_i915_private_t *dev_priv = dev->dev_private;
4794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795         int pipe = intel_crtc->pipe;
4796         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4797         int dpll = I915_READ(dpll_reg);
4798
4799         if (HAS_PCH_SPLIT(dev))
4800                 return;
4801
4802         if (!dev_priv->lvds_downclock_avail)
4803                 return;
4804
4805         /*
4806          * Since this is called by a timer, we should never get here in
4807          * the manual case.
4808          */
4809         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4810                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4811
4812                 /* Unlock panel regs */
4813                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4814                            PANEL_UNLOCK_REGS);
4815
4816                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4817                 I915_WRITE(dpll_reg, dpll);
4818                 dpll = I915_READ(dpll_reg);
4819                 intel_wait_for_vblank(dev, pipe);
4820                 dpll = I915_READ(dpll_reg);
4821                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4822                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4823
4824                 /* ...and lock them again */
4825                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4826         }
4827
4828 }
4829
4830 /**
4831  * intel_idle_update - adjust clocks for idleness
4832  * @work: work struct
4833  *
4834  * Either the GPU or display (or both) went idle.  Check the busy status
4835  * here and adjust the CRTC and GPU clocks as necessary.
4836  */
4837 static void intel_idle_update(struct work_struct *work)
4838 {
4839         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4840                                                     idle_work);
4841         struct drm_device *dev = dev_priv->dev;
4842         struct drm_crtc *crtc;
4843         struct intel_crtc *intel_crtc;
4844         int enabled = 0;
4845
4846         if (!i915_powersave)
4847                 return;
4848
4849         mutex_lock(&dev->struct_mutex);
4850
4851         i915_update_gfx_val(dev_priv);
4852
4853         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4854                 /* Skip inactive CRTCs */
4855                 if (!crtc->fb)
4856                         continue;
4857
4858                 enabled++;
4859                 intel_crtc = to_intel_crtc(crtc);
4860                 if (!intel_crtc->busy)
4861                         intel_decrease_pllclock(crtc);
4862         }
4863
4864         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4865                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4866                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4867         }
4868
4869         mutex_unlock(&dev->struct_mutex);
4870 }
4871
4872 /**
4873  * intel_mark_busy - mark the GPU and possibly the display busy
4874  * @dev: drm device
4875  * @obj: object we're operating on
4876  *
4877  * Callers can use this function to indicate that the GPU is busy processing
4878  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4879  * buffer), we'll also mark the display as busy, so we know to increase its
4880  * clock frequency.
4881  */
4882 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4883 {
4884         drm_i915_private_t *dev_priv = dev->dev_private;
4885         struct drm_crtc *crtc = NULL;
4886         struct intel_framebuffer *intel_fb;
4887         struct intel_crtc *intel_crtc;
4888
4889         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4890                 return;
4891
4892         if (!dev_priv->busy) {
4893                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4894                         u32 fw_blc_self;
4895
4896                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4897                         fw_blc_self = I915_READ(FW_BLC_SELF);
4898                         fw_blc_self &= ~FW_BLC_SELF_EN;
4899                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4900                 }
4901                 dev_priv->busy = true;
4902         } else
4903                 mod_timer(&dev_priv->idle_timer, jiffies +
4904                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4905
4906         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4907                 if (!crtc->fb)
4908                         continue;
4909
4910                 intel_crtc = to_intel_crtc(crtc);
4911                 intel_fb = to_intel_framebuffer(crtc->fb);
4912                 if (intel_fb->obj == obj) {
4913                         if (!intel_crtc->busy) {
4914                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4915                                         u32 fw_blc_self;
4916
4917                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4918                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4919                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4920                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4921                                 }
4922                                 /* Non-busy -> busy, upclock */
4923                                 intel_increase_pllclock(crtc);
4924                                 intel_crtc->busy = true;
4925                         } else {
4926                                 /* Busy -> busy, put off timer */
4927                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4928                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4929                         }
4930                 }
4931         }
4932 }
4933
4934 static void intel_crtc_destroy(struct drm_crtc *crtc)
4935 {
4936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937         struct drm_device *dev = crtc->dev;
4938         struct intel_unpin_work *work;
4939         unsigned long flags;
4940
4941         spin_lock_irqsave(&dev->event_lock, flags);
4942         work = intel_crtc->unpin_work;
4943         intel_crtc->unpin_work = NULL;
4944         spin_unlock_irqrestore(&dev->event_lock, flags);
4945
4946         if (work) {
4947                 cancel_work_sync(&work->work);
4948                 kfree(work);
4949         }
4950
4951         drm_crtc_cleanup(crtc);
4952
4953         kfree(intel_crtc);
4954 }
4955
4956 static void intel_unpin_work_fn(struct work_struct *__work)
4957 {
4958         struct intel_unpin_work *work =
4959                 container_of(__work, struct intel_unpin_work, work);
4960
4961         mutex_lock(&work->dev->struct_mutex);
4962         i915_gem_object_unpin(work->old_fb_obj);
4963         drm_gem_object_unreference(work->pending_flip_obj);
4964         drm_gem_object_unreference(work->old_fb_obj);
4965         mutex_unlock(&work->dev->struct_mutex);
4966         kfree(work);
4967 }
4968
4969 static void do_intel_finish_page_flip(struct drm_device *dev,
4970                                       struct drm_crtc *crtc)
4971 {
4972         drm_i915_private_t *dev_priv = dev->dev_private;
4973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974         struct intel_unpin_work *work;
4975         struct drm_i915_gem_object *obj_priv;
4976         struct drm_pending_vblank_event *e;
4977         struct timeval now;
4978         unsigned long flags;
4979
4980         /* Ignore early vblank irqs */
4981         if (intel_crtc == NULL)
4982                 return;
4983
4984         spin_lock_irqsave(&dev->event_lock, flags);
4985         work = intel_crtc->unpin_work;
4986         if (work == NULL || !work->pending) {
4987                 spin_unlock_irqrestore(&dev->event_lock, flags);
4988                 return;
4989         }
4990
4991         intel_crtc->unpin_work = NULL;
4992         drm_vblank_put(dev, intel_crtc->pipe);
4993
4994         if (work->event) {
4995                 e = work->event;
4996                 do_gettimeofday(&now);
4997                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4998                 e->event.tv_sec = now.tv_sec;
4999                 e->event.tv_usec = now.tv_usec;
5000                 list_add_tail(&e->base.link,
5001                               &e->base.file_priv->event_list);
5002                 wake_up_interruptible(&e->base.file_priv->event_wait);
5003         }
5004
5005         spin_unlock_irqrestore(&dev->event_lock, flags);
5006
5007         obj_priv = to_intel_bo(work->old_fb_obj);
5008         atomic_clear_mask(1 << intel_crtc->plane,
5009                           &obj_priv->pending_flip.counter);
5010         if (atomic_read(&obj_priv->pending_flip) == 0)
5011                 wake_up(&dev_priv->pending_flip_queue);
5012         schedule_work(&work->work);
5013
5014         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5015 }
5016
5017 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5018 {
5019         drm_i915_private_t *dev_priv = dev->dev_private;
5020         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5021
5022         do_intel_finish_page_flip(dev, crtc);
5023 }
5024
5025 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5026 {
5027         drm_i915_private_t *dev_priv = dev->dev_private;
5028         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5029
5030         do_intel_finish_page_flip(dev, crtc);
5031 }
5032
5033 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5034 {
5035         drm_i915_private_t *dev_priv = dev->dev_private;
5036         struct intel_crtc *intel_crtc =
5037                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5038         unsigned long flags;
5039
5040         spin_lock_irqsave(&dev->event_lock, flags);
5041         if (intel_crtc->unpin_work) {
5042                 if ((++intel_crtc->unpin_work->pending) > 1)
5043                         DRM_ERROR("Prepared flip multiple times\n");
5044         } else {
5045                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5046         }
5047         spin_unlock_irqrestore(&dev->event_lock, flags);
5048 }
5049
5050 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5051                                 struct drm_framebuffer *fb,
5052                                 struct drm_pending_vblank_event *event)
5053 {
5054         struct drm_device *dev = crtc->dev;
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056         struct intel_framebuffer *intel_fb;
5057         struct drm_i915_gem_object *obj_priv;
5058         struct drm_gem_object *obj;
5059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5060         struct intel_unpin_work *work;
5061         unsigned long flags, offset;
5062         int pipe = intel_crtc->pipe;
5063         u32 pf, pipesrc;
5064         int ret;
5065
5066         work = kzalloc(sizeof *work, GFP_KERNEL);
5067         if (work == NULL)
5068                 return -ENOMEM;
5069
5070         work->event = event;
5071         work->dev = crtc->dev;
5072         intel_fb = to_intel_framebuffer(crtc->fb);
5073         work->old_fb_obj = intel_fb->obj;
5074         INIT_WORK(&work->work, intel_unpin_work_fn);
5075
5076         /* We borrow the event spin lock for protecting unpin_work */
5077         spin_lock_irqsave(&dev->event_lock, flags);
5078         if (intel_crtc->unpin_work) {
5079                 spin_unlock_irqrestore(&dev->event_lock, flags);
5080                 kfree(work);
5081
5082                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5083                 return -EBUSY;
5084         }
5085         intel_crtc->unpin_work = work;
5086         spin_unlock_irqrestore(&dev->event_lock, flags);
5087
5088         intel_fb = to_intel_framebuffer(fb);
5089         obj = intel_fb->obj;
5090
5091         mutex_lock(&dev->struct_mutex);
5092         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5093         if (ret)
5094                 goto cleanup_work;
5095
5096         /* Reference the objects for the scheduled work. */
5097         drm_gem_object_reference(work->old_fb_obj);
5098         drm_gem_object_reference(obj);
5099
5100         crtc->fb = fb;
5101
5102         ret = drm_vblank_get(dev, intel_crtc->pipe);
5103         if (ret)
5104                 goto cleanup_objs;
5105
5106         /* Block clients from rendering to the new back buffer until
5107          * the flip occurs and the object is no longer visible.
5108          */
5109         atomic_add(1 << intel_crtc->plane,
5110                    &to_intel_bo(work->old_fb_obj)->pending_flip);
5111
5112         work->pending_flip_obj = obj;
5113         obj_priv = to_intel_bo(obj);
5114
5115         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5116                 u32 flip_mask;
5117
5118                 /* Can't queue multiple flips, so wait for the previous
5119                  * one to finish before executing the next.
5120                  */
5121                 BEGIN_LP_RING(2);
5122                 if (intel_crtc->plane)
5123                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5124                 else
5125                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5126                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5127                 OUT_RING(MI_NOOP);
5128                 ADVANCE_LP_RING();
5129         }
5130
5131         work->enable_stall_check = true;
5132
5133         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5134         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5135
5136         BEGIN_LP_RING(4);
5137         switch(INTEL_INFO(dev)->gen) {
5138         case 2:
5139                 OUT_RING(MI_DISPLAY_FLIP |
5140                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5141                 OUT_RING(fb->pitch);
5142                 OUT_RING(obj_priv->gtt_offset + offset);
5143                 OUT_RING(MI_NOOP);
5144                 break;
5145
5146         case 3:
5147                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5148                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5149                 OUT_RING(fb->pitch);
5150                 OUT_RING(obj_priv->gtt_offset + offset);
5151                 OUT_RING(MI_NOOP);
5152                 break;
5153
5154         case 4:
5155         case 5:
5156                 /* i965+ uses the linear or tiled offsets from the
5157                  * Display Registers (which do not change across a page-flip)
5158                  * so we need only reprogram the base address.
5159                  */
5160                 OUT_RING(MI_DISPLAY_FLIP |
5161                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5162                 OUT_RING(fb->pitch);
5163                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5164
5165                 /* XXX Enabling the panel-fitter across page-flip is so far
5166                  * untested on non-native modes, so ignore it for now.
5167                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5168                  */
5169                 pf = 0;
5170                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5171                 OUT_RING(pf | pipesrc);
5172                 break;
5173
5174         case 6:
5175                 OUT_RING(MI_DISPLAY_FLIP |
5176                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5177                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5178                 OUT_RING(obj_priv->gtt_offset);
5179
5180                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5181                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5182                 OUT_RING(pf | pipesrc);
5183                 break;
5184         }
5185         ADVANCE_LP_RING();
5186
5187         mutex_unlock(&dev->struct_mutex);
5188
5189         trace_i915_flip_request(intel_crtc->plane, obj);
5190
5191         return 0;
5192
5193 cleanup_objs:
5194         drm_gem_object_unreference(work->old_fb_obj);
5195         drm_gem_object_unreference(obj);
5196 cleanup_work:
5197         mutex_unlock(&dev->struct_mutex);
5198
5199         spin_lock_irqsave(&dev->event_lock, flags);
5200         intel_crtc->unpin_work = NULL;
5201         spin_unlock_irqrestore(&dev->event_lock, flags);
5202
5203         kfree(work);
5204
5205         return ret;
5206 }
5207
5208 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5209         .dpms = intel_crtc_dpms,
5210         .mode_fixup = intel_crtc_mode_fixup,
5211         .mode_set = intel_crtc_mode_set,
5212         .mode_set_base = intel_pipe_set_base,
5213         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5214         .load_lut = intel_crtc_load_lut,
5215         .disable = intel_crtc_disable,
5216 };
5217
5218 static const struct drm_crtc_funcs intel_crtc_funcs = {
5219         .cursor_set = intel_crtc_cursor_set,
5220         .cursor_move = intel_crtc_cursor_move,
5221         .gamma_set = intel_crtc_gamma_set,
5222         .set_config = drm_crtc_helper_set_config,
5223         .destroy = intel_crtc_destroy,
5224         .page_flip = intel_crtc_page_flip,
5225 };
5226
5227
5228 static void intel_crtc_init(struct drm_device *dev, int pipe)
5229 {
5230         drm_i915_private_t *dev_priv = dev->dev_private;
5231         struct intel_crtc *intel_crtc;
5232         int i;
5233
5234         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5235         if (intel_crtc == NULL)
5236                 return;
5237
5238         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5239
5240         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5241         for (i = 0; i < 256; i++) {
5242                 intel_crtc->lut_r[i] = i;
5243                 intel_crtc->lut_g[i] = i;
5244                 intel_crtc->lut_b[i] = i;
5245         }
5246
5247         /* Swap pipes & planes for FBC on pre-965 */
5248         intel_crtc->pipe = pipe;
5249         intel_crtc->plane = pipe;
5250         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5251                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5252                 intel_crtc->plane = !pipe;
5253         }
5254
5255         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5256                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5257         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5258         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5259
5260         intel_crtc->cursor_addr = 0;
5261         intel_crtc->dpms_mode = -1;
5262         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5263
5264         if (HAS_PCH_SPLIT(dev)) {
5265                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5266                 intel_helper_funcs.commit = ironlake_crtc_commit;
5267         } else {
5268                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5269                 intel_helper_funcs.commit = i9xx_crtc_commit;
5270         }
5271
5272         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5273
5274         intel_crtc->busy = false;
5275
5276         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5277                     (unsigned long)intel_crtc);
5278 }
5279
5280 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5281                                 struct drm_file *file_priv)
5282 {
5283         drm_i915_private_t *dev_priv = dev->dev_private;
5284         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5285         struct drm_mode_object *drmmode_obj;
5286         struct intel_crtc *crtc;
5287
5288         if (!dev_priv) {
5289                 DRM_ERROR("called with no initialization\n");
5290                 return -EINVAL;
5291         }
5292
5293         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5294                         DRM_MODE_OBJECT_CRTC);
5295
5296         if (!drmmode_obj) {
5297                 DRM_ERROR("no such CRTC id\n");
5298                 return -EINVAL;
5299         }
5300
5301         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5302         pipe_from_crtc_id->pipe = crtc->pipe;
5303
5304         return 0;
5305 }
5306
5307 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5308 {
5309         struct intel_encoder *encoder;
5310         int index_mask = 0;
5311         int entry = 0;
5312
5313         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5314                 if (type_mask & encoder->clone_mask)
5315                         index_mask |= (1 << entry);
5316                 entry++;
5317         }
5318
5319         return index_mask;
5320 }
5321
5322 static void intel_setup_outputs(struct drm_device *dev)
5323 {
5324         struct drm_i915_private *dev_priv = dev->dev_private;
5325         struct intel_encoder *encoder;
5326         bool dpd_is_edp = false;
5327
5328         if (IS_MOBILE(dev) && !IS_I830(dev))
5329                 intel_lvds_init(dev);
5330
5331         if (HAS_PCH_SPLIT(dev)) {
5332                 dpd_is_edp = intel_dpd_is_edp(dev);
5333
5334                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5335                         intel_dp_init(dev, DP_A);
5336
5337                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5338                         intel_dp_init(dev, PCH_DP_D);
5339         }
5340
5341         intel_crt_init(dev);
5342
5343         if (HAS_PCH_SPLIT(dev)) {
5344                 int found;
5345
5346                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5347                         /* PCH SDVOB multiplex with HDMIB */
5348                         found = intel_sdvo_init(dev, PCH_SDVOB);
5349                         if (!found)
5350                                 intel_hdmi_init(dev, HDMIB);
5351                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5352                                 intel_dp_init(dev, PCH_DP_B);
5353                 }
5354
5355                 if (I915_READ(HDMIC) & PORT_DETECTED)
5356                         intel_hdmi_init(dev, HDMIC);
5357
5358                 if (I915_READ(HDMID) & PORT_DETECTED)
5359                         intel_hdmi_init(dev, HDMID);
5360
5361                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5362                         intel_dp_init(dev, PCH_DP_C);
5363
5364                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5365                         intel_dp_init(dev, PCH_DP_D);
5366
5367         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5368                 bool found = false;
5369
5370                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5371                         DRM_DEBUG_KMS("probing SDVOB\n");
5372                         found = intel_sdvo_init(dev, SDVOB);
5373                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5374                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5375                                 intel_hdmi_init(dev, SDVOB);
5376                         }
5377
5378                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5379                                 DRM_DEBUG_KMS("probing DP_B\n");
5380                                 intel_dp_init(dev, DP_B);
5381                         }
5382                 }
5383
5384                 /* Before G4X SDVOC doesn't have its own detect register */
5385
5386                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5387                         DRM_DEBUG_KMS("probing SDVOC\n");
5388                         found = intel_sdvo_init(dev, SDVOC);
5389                 }
5390
5391                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5392
5393                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5394                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5395                                 intel_hdmi_init(dev, SDVOC);
5396                         }
5397                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5398                                 DRM_DEBUG_KMS("probing DP_C\n");
5399                                 intel_dp_init(dev, DP_C);
5400                         }
5401                 }
5402
5403                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5404                     (I915_READ(DP_D) & DP_DETECTED)) {
5405                         DRM_DEBUG_KMS("probing DP_D\n");
5406                         intel_dp_init(dev, DP_D);
5407                 }
5408         } else if (IS_GEN2(dev))
5409                 intel_dvo_init(dev);
5410
5411         if (SUPPORTS_TV(dev))
5412                 intel_tv_init(dev);
5413
5414         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5415                 encoder->base.possible_crtcs = encoder->crtc_mask;
5416                 encoder->base.possible_clones =
5417                         intel_encoder_clones(dev, encoder->clone_mask);
5418         }
5419 }
5420
5421 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5422 {
5423         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5424
5425         drm_framebuffer_cleanup(fb);
5426         drm_gem_object_unreference_unlocked(intel_fb->obj);
5427
5428         kfree(intel_fb);
5429 }
5430
5431 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5432                                                 struct drm_file *file_priv,
5433                                                 unsigned int *handle)
5434 {
5435         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5436         struct drm_gem_object *object = intel_fb->obj;
5437
5438         return drm_gem_handle_create(file_priv, object, handle);
5439 }
5440
5441 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5442         .destroy = intel_user_framebuffer_destroy,
5443         .create_handle = intel_user_framebuffer_create_handle,
5444 };
5445
5446 int intel_framebuffer_init(struct drm_device *dev,
5447                            struct intel_framebuffer *intel_fb,
5448                            struct drm_mode_fb_cmd *mode_cmd,
5449                            struct drm_gem_object *obj)
5450 {
5451         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5452         int ret;
5453
5454         if (obj_priv->tiling_mode == I915_TILING_Y)
5455                 return -EINVAL;
5456
5457         if (mode_cmd->pitch & 63)
5458                 return -EINVAL;
5459
5460         switch (mode_cmd->bpp) {
5461         case 8:
5462         case 16:
5463         case 24:
5464         case 32:
5465                 break;
5466         default:
5467                 return -EINVAL;
5468         }
5469
5470         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5471         if (ret) {
5472                 DRM_ERROR("framebuffer init failed %d\n", ret);
5473                 return ret;
5474         }
5475
5476         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5477         intel_fb->obj = obj;
5478         return 0;
5479 }
5480
5481 static struct drm_framebuffer *
5482 intel_user_framebuffer_create(struct drm_device *dev,
5483                               struct drm_file *filp,
5484                               struct drm_mode_fb_cmd *mode_cmd)
5485 {
5486         struct drm_gem_object *obj;
5487         struct intel_framebuffer *intel_fb;
5488         int ret;
5489
5490         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5491         if (!obj)
5492                 return ERR_PTR(-ENOENT);
5493
5494         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5495         if (!intel_fb)
5496                 return ERR_PTR(-ENOMEM);
5497
5498         ret = intel_framebuffer_init(dev, intel_fb,
5499                                      mode_cmd, obj);
5500         if (ret) {
5501                 drm_gem_object_unreference_unlocked(obj);
5502                 kfree(intel_fb);
5503                 return ERR_PTR(ret);
5504         }
5505
5506         return &intel_fb->base;
5507 }
5508
5509 static const struct drm_mode_config_funcs intel_mode_funcs = {
5510         .fb_create = intel_user_framebuffer_create,
5511         .output_poll_changed = intel_fb_output_poll_changed,
5512 };
5513
5514 static struct drm_gem_object *
5515 intel_alloc_context_page(struct drm_device *dev)
5516 {
5517         struct drm_gem_object *ctx;
5518         int ret;
5519
5520         ctx = i915_gem_alloc_object(dev, 4096);
5521         if (!ctx) {
5522                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5523                 return NULL;
5524         }
5525
5526         mutex_lock(&dev->struct_mutex);
5527         ret = i915_gem_object_pin(ctx, 4096);
5528         if (ret) {
5529                 DRM_ERROR("failed to pin power context: %d\n", ret);
5530                 goto err_unref;
5531         }
5532
5533         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5534         if (ret) {
5535                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5536                 goto err_unpin;
5537         }
5538         mutex_unlock(&dev->struct_mutex);
5539
5540         return ctx;
5541
5542 err_unpin:
5543         i915_gem_object_unpin(ctx);
5544 err_unref:
5545         drm_gem_object_unreference(ctx);
5546         mutex_unlock(&dev->struct_mutex);
5547         return NULL;
5548 }
5549
5550 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553         u16 rgvswctl;
5554
5555         rgvswctl = I915_READ16(MEMSWCTL);
5556         if (rgvswctl & MEMCTL_CMD_STS) {
5557                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5558                 return false; /* still busy with another command */
5559         }
5560
5561         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5562                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5563         I915_WRITE16(MEMSWCTL, rgvswctl);
5564         POSTING_READ16(MEMSWCTL);
5565
5566         rgvswctl |= MEMCTL_CMD_STS;
5567         I915_WRITE16(MEMSWCTL, rgvswctl);
5568
5569         return true;
5570 }
5571
5572 void ironlake_enable_drps(struct drm_device *dev)
5573 {
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         u32 rgvmodectl = I915_READ(MEMMODECTL);
5576         u8 fmax, fmin, fstart, vstart;
5577
5578         /* Enable temp reporting */
5579         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5580         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5581
5582         /* 100ms RC evaluation intervals */
5583         I915_WRITE(RCUPEI, 100000);
5584         I915_WRITE(RCDNEI, 100000);
5585
5586         /* Set max/min thresholds to 90ms and 80ms respectively */
5587         I915_WRITE(RCBMAXAVG, 90000);
5588         I915_WRITE(RCBMINAVG, 80000);
5589
5590         I915_WRITE(MEMIHYST, 1);
5591
5592         /* Set up min, max, and cur for interrupt handling */
5593         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5594         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5595         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5596                 MEMMODE_FSTART_SHIFT;
5597
5598         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5599                 PXVFREQ_PX_SHIFT;
5600
5601         dev_priv->fmax = fmax; /* IPS callback will increase this */
5602         dev_priv->fstart = fstart;
5603
5604         dev_priv->max_delay = fstart;
5605         dev_priv->min_delay = fmin;
5606         dev_priv->cur_delay = fstart;
5607
5608         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5609                          fmax, fmin, fstart);
5610
5611         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5612
5613         /*
5614          * Interrupts will be enabled in ironlake_irq_postinstall
5615          */
5616
5617         I915_WRITE(VIDSTART, vstart);
5618         POSTING_READ(VIDSTART);
5619
5620         rgvmodectl |= MEMMODE_SWMODE_EN;
5621         I915_WRITE(MEMMODECTL, rgvmodectl);
5622
5623         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5624                 DRM_ERROR("stuck trying to change perf mode\n");
5625         msleep(1);
5626
5627         ironlake_set_drps(dev, fstart);
5628
5629         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5630                 I915_READ(0x112e0);
5631         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5632         dev_priv->last_count2 = I915_READ(0x112f4);
5633         getrawmonotonic(&dev_priv->last_time2);
5634 }
5635
5636 void ironlake_disable_drps(struct drm_device *dev)
5637 {
5638         struct drm_i915_private *dev_priv = dev->dev_private;
5639         u16 rgvswctl = I915_READ16(MEMSWCTL);
5640
5641         /* Ack interrupts, disable EFC interrupt */
5642         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5643         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5644         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5645         I915_WRITE(DEIIR, DE_PCU_EVENT);
5646         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5647
5648         /* Go back to the starting frequency */
5649         ironlake_set_drps(dev, dev_priv->fstart);
5650         msleep(1);
5651         rgvswctl |= MEMCTL_CMD_STS;
5652         I915_WRITE(MEMSWCTL, rgvswctl);
5653         msleep(1);
5654
5655 }
5656
5657 static unsigned long intel_pxfreq(u32 vidfreq)
5658 {
5659         unsigned long freq;
5660         int div = (vidfreq & 0x3f0000) >> 16;
5661         int post = (vidfreq & 0x3000) >> 12;
5662         int pre = (vidfreq & 0x7);
5663
5664         if (!pre)
5665                 return 0;
5666
5667         freq = ((div * 133333) / ((1<<post) * pre));
5668
5669         return freq;
5670 }
5671
5672 void intel_init_emon(struct drm_device *dev)
5673 {
5674         struct drm_i915_private *dev_priv = dev->dev_private;
5675         u32 lcfuse;
5676         u8 pxw[16];
5677         int i;
5678
5679         /* Disable to program */
5680         I915_WRITE(ECR, 0);
5681         POSTING_READ(ECR);
5682
5683         /* Program energy weights for various events */
5684         I915_WRITE(SDEW, 0x15040d00);
5685         I915_WRITE(CSIEW0, 0x007f0000);
5686         I915_WRITE(CSIEW1, 0x1e220004);
5687         I915_WRITE(CSIEW2, 0x04000004);
5688
5689         for (i = 0; i < 5; i++)
5690                 I915_WRITE(PEW + (i * 4), 0);
5691         for (i = 0; i < 3; i++)
5692                 I915_WRITE(DEW + (i * 4), 0);
5693
5694         /* Program P-state weights to account for frequency power adjustment */
5695         for (i = 0; i < 16; i++) {
5696                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5697                 unsigned long freq = intel_pxfreq(pxvidfreq);
5698                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5699                         PXVFREQ_PX_SHIFT;
5700                 unsigned long val;
5701
5702                 val = vid * vid;
5703                 val *= (freq / 1000);
5704                 val *= 255;
5705                 val /= (127*127*900);
5706                 if (val > 0xff)
5707                         DRM_ERROR("bad pxval: %ld\n", val);
5708                 pxw[i] = val;
5709         }
5710         /* Render standby states get 0 weight */
5711         pxw[14] = 0;
5712         pxw[15] = 0;
5713
5714         for (i = 0; i < 4; i++) {
5715                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5716                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5717                 I915_WRITE(PXW + (i * 4), val);
5718         }
5719
5720         /* Adjust magic regs to magic values (more experimental results) */
5721         I915_WRITE(OGW0, 0);
5722         I915_WRITE(OGW1, 0);
5723         I915_WRITE(EG0, 0x00007f00);
5724         I915_WRITE(EG1, 0x0000000e);
5725         I915_WRITE(EG2, 0x000e0000);
5726         I915_WRITE(EG3, 0x68000300);
5727         I915_WRITE(EG4, 0x42000000);
5728         I915_WRITE(EG5, 0x00140031);
5729         I915_WRITE(EG6, 0);
5730         I915_WRITE(EG7, 0);
5731
5732         for (i = 0; i < 8; i++)
5733                 I915_WRITE(PXWL + (i * 4), 0);
5734
5735         /* Enable PMON + select events */
5736         I915_WRITE(ECR, 0x80000019);
5737
5738         lcfuse = I915_READ(LCFUSE02);
5739
5740         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5741 }
5742
5743 void intel_init_clock_gating(struct drm_device *dev)
5744 {
5745         struct drm_i915_private *dev_priv = dev->dev_private;
5746
5747         /*
5748          * Disable clock gating reported to work incorrectly according to the
5749          * specs, but enable as much else as we can.
5750          */
5751         if (HAS_PCH_SPLIT(dev)) {
5752                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5753
5754                 if (IS_GEN5(dev)) {
5755                         /* Required for FBC */
5756                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5757                         /* Required for CxSR */
5758                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5759
5760                         I915_WRITE(PCH_3DCGDIS0,
5761                                    MARIUNIT_CLOCK_GATE_DISABLE |
5762                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5763                 }
5764
5765                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5766
5767                 /*
5768                  * On Ibex Peak and Cougar Point, we need to disable clock
5769                  * gating for the panel power sequencer or it will fail to
5770                  * start up when no ports are active.
5771                  */
5772                 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5773
5774                 /*
5775                  * According to the spec the following bits should be set in
5776                  * order to enable memory self-refresh
5777                  * The bit 22/21 of 0x42004
5778                  * The bit 5 of 0x42020
5779                  * The bit 15 of 0x45000
5780                  */
5781                 if (IS_GEN5(dev)) {
5782                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5783                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5784                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5785                         I915_WRITE(ILK_DSPCLK_GATE,
5786                                         (I915_READ(ILK_DSPCLK_GATE) |
5787                                                 ILK_DPARB_CLK_GATE));
5788                         I915_WRITE(DISP_ARB_CTL,
5789                                         (I915_READ(DISP_ARB_CTL) |
5790                                                 DISP_FBC_WM_DIS));
5791                 I915_WRITE(WM3_LP_ILK, 0);
5792                 I915_WRITE(WM2_LP_ILK, 0);
5793                 I915_WRITE(WM1_LP_ILK, 0);
5794                 }
5795                 /*
5796                  * Based on the document from hardware guys the following bits
5797                  * should be set unconditionally in order to enable FBC.
5798                  * The bit 22 of 0x42000
5799                  * The bit 22 of 0x42004
5800                  * The bit 7,8,9 of 0x42020.
5801                  */
5802                 if (IS_IRONLAKE_M(dev)) {
5803                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5804                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5805                                    ILK_FBCQ_DIS);
5806                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5807                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5808                                    ILK_DPARB_GATE);
5809                         I915_WRITE(ILK_DSPCLK_GATE,
5810                                    I915_READ(ILK_DSPCLK_GATE) |
5811                                    ILK_DPFC_DIS1 |
5812                                    ILK_DPFC_DIS2 |
5813                                    ILK_CLK_FBC);
5814                 }
5815                 return;
5816         } else if (IS_G4X(dev)) {
5817                 uint32_t dspclk_gate;
5818                 I915_WRITE(RENCLK_GATE_D1, 0);
5819                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5820                        GS_UNIT_CLOCK_GATE_DISABLE |
5821                        CL_UNIT_CLOCK_GATE_DISABLE);
5822                 I915_WRITE(RAMCLK_GATE_D, 0);
5823                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5824                         OVRUNIT_CLOCK_GATE_DISABLE |
5825                         OVCUNIT_CLOCK_GATE_DISABLE;
5826                 if (IS_GM45(dev))
5827                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5828                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5829         } else if (IS_CRESTLINE(dev)) {
5830                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5831                 I915_WRITE(RENCLK_GATE_D2, 0);
5832                 I915_WRITE(DSPCLK_GATE_D, 0);
5833                 I915_WRITE(RAMCLK_GATE_D, 0);
5834                 I915_WRITE16(DEUC, 0);
5835         } else if (IS_BROADWATER(dev)) {
5836                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5837                        I965_RCC_CLOCK_GATE_DISABLE |
5838                        I965_RCPB_CLOCK_GATE_DISABLE |
5839                        I965_ISC_CLOCK_GATE_DISABLE |
5840                        I965_FBC_CLOCK_GATE_DISABLE);
5841                 I915_WRITE(RENCLK_GATE_D2, 0);
5842         } else if (IS_GEN3(dev)) {
5843                 u32 dstate = I915_READ(D_STATE);
5844
5845                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5846                         DSTATE_DOT_CLOCK_GATING;
5847                 I915_WRITE(D_STATE, dstate);
5848         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5849                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5850         } else if (IS_I830(dev)) {
5851                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5852         }
5853
5854         /*
5855          * GPU can automatically power down the render unit if given a page
5856          * to save state.
5857          */
5858         if (IS_IRONLAKE_M(dev)) {
5859                 if (dev_priv->renderctx == NULL)
5860                         dev_priv->renderctx = intel_alloc_context_page(dev);
5861                 if (dev_priv->renderctx) {
5862                         struct drm_i915_gem_object *obj_priv;
5863                         obj_priv = to_intel_bo(dev_priv->renderctx);
5864                         if (obj_priv) {
5865                                 BEGIN_LP_RING(4);
5866                                 OUT_RING(MI_SET_CONTEXT);
5867                                 OUT_RING(obj_priv->gtt_offset |
5868                                                 MI_MM_SPACE_GTT |
5869                                                 MI_SAVE_EXT_STATE_EN |
5870                                                 MI_RESTORE_EXT_STATE_EN |
5871                                                 MI_RESTORE_INHIBIT);
5872                                 OUT_RING(MI_NOOP);
5873                                 OUT_RING(MI_FLUSH);
5874                                 ADVANCE_LP_RING();
5875                         }
5876                 } else
5877                         DRM_DEBUG_KMS("Failed to allocate render context."
5878                                        "Disable RC6\n");
5879         }
5880
5881         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5882                 struct drm_i915_gem_object *obj_priv = NULL;
5883
5884                 if (dev_priv->pwrctx) {
5885                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5886                 } else {
5887                         struct drm_gem_object *pwrctx;
5888
5889                         pwrctx = intel_alloc_context_page(dev);
5890                         if (pwrctx) {
5891                                 dev_priv->pwrctx = pwrctx;
5892                                 obj_priv = to_intel_bo(pwrctx);
5893                         }
5894                 }
5895
5896                 if (obj_priv) {
5897                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5898                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5899                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5900                 }
5901         }
5902 }
5903
5904 /* Set up chip specific display functions */
5905 static void intel_init_display(struct drm_device *dev)
5906 {
5907         struct drm_i915_private *dev_priv = dev->dev_private;
5908
5909         /* We always want a DPMS function */
5910         if (HAS_PCH_SPLIT(dev))
5911                 dev_priv->display.dpms = ironlake_crtc_dpms;
5912         else
5913                 dev_priv->display.dpms = i9xx_crtc_dpms;
5914
5915         if (I915_HAS_FBC(dev)) {
5916                 if (IS_IRONLAKE_M(dev)) {
5917                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5918                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5919                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5920                 } else if (IS_GM45(dev)) {
5921                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5922                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5923                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5924                 } else if (IS_CRESTLINE(dev)) {
5925                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5926                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5927                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5928                 }
5929                 /* 855GM needs testing */
5930         }
5931
5932         /* Returns the core display clock speed */
5933         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5934                 dev_priv->display.get_display_clock_speed =
5935                         i945_get_display_clock_speed;
5936         else if (IS_I915G(dev))
5937                 dev_priv->display.get_display_clock_speed =
5938                         i915_get_display_clock_speed;
5939         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5940                 dev_priv->display.get_display_clock_speed =
5941                         i9xx_misc_get_display_clock_speed;
5942         else if (IS_I915GM(dev))
5943                 dev_priv->display.get_display_clock_speed =
5944                         i915gm_get_display_clock_speed;
5945         else if (IS_I865G(dev))
5946                 dev_priv->display.get_display_clock_speed =
5947                         i865_get_display_clock_speed;
5948         else if (IS_I85X(dev))
5949                 dev_priv->display.get_display_clock_speed =
5950                         i855_get_display_clock_speed;
5951         else /* 852, 830 */
5952                 dev_priv->display.get_display_clock_speed =
5953                         i830_get_display_clock_speed;
5954
5955         /* For FIFO watermark updates */
5956         if (HAS_PCH_SPLIT(dev)) {
5957                 if (IS_GEN5(dev)) {
5958                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5959                                 dev_priv->display.update_wm = ironlake_update_wm;
5960                         else {
5961                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5962                                               "Disable CxSR\n");
5963                                 dev_priv->display.update_wm = NULL;
5964                         }
5965                 } else
5966                         dev_priv->display.update_wm = NULL;
5967         } else if (IS_PINEVIEW(dev)) {
5968                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5969                                             dev_priv->is_ddr3,
5970                                             dev_priv->fsb_freq,
5971                                             dev_priv->mem_freq)) {
5972                         DRM_INFO("failed to find known CxSR latency "
5973                                  "(found ddr%s fsb freq %d, mem freq %d), "
5974                                  "disabling CxSR\n",
5975                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5976                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5977                         /* Disable CxSR and never update its watermark again */
5978                         pineview_disable_cxsr(dev);
5979                         dev_priv->display.update_wm = NULL;
5980                 } else
5981                         dev_priv->display.update_wm = pineview_update_wm;
5982         } else if (IS_G4X(dev))
5983                 dev_priv->display.update_wm = g4x_update_wm;
5984         else if (IS_GEN4(dev))
5985                 dev_priv->display.update_wm = i965_update_wm;
5986         else if (IS_GEN3(dev)) {
5987                 dev_priv->display.update_wm = i9xx_update_wm;
5988                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5989         } else if (IS_I85X(dev)) {
5990                 dev_priv->display.update_wm = i9xx_update_wm;
5991                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5992         } else {
5993                 dev_priv->display.update_wm = i830_update_wm;
5994                 if (IS_845G(dev))
5995                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5996                 else
5997                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5998         }
5999 }
6000
6001 /*
6002  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6003  * resume, or other times.  This quirk makes sure that's the case for
6004  * affected systems.
6005  */
6006 static void quirk_pipea_force (struct drm_device *dev)
6007 {
6008         struct drm_i915_private *dev_priv = dev->dev_private;
6009
6010         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6011         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6012 }
6013
6014 struct intel_quirk {
6015         int device;
6016         int subsystem_vendor;
6017         int subsystem_device;
6018         void (*hook)(struct drm_device *dev);
6019 };
6020
6021 struct intel_quirk intel_quirks[] = {
6022         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6023         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6024         /* HP Mini needs pipe A force quirk (LP: #322104) */
6025         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6026
6027         /* Thinkpad R31 needs pipe A force quirk */
6028         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6029         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6030         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6031
6032         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6033         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
6034         /* ThinkPad X40 needs pipe A force quirk */
6035
6036         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6037         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6038
6039         /* 855 & before need to leave pipe A & dpll A up */
6040         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6041         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6042 };
6043
6044 static void intel_init_quirks(struct drm_device *dev)
6045 {
6046         struct pci_dev *d = dev->pdev;
6047         int i;
6048
6049         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6050                 struct intel_quirk *q = &intel_quirks[i];
6051
6052                 if (d->device == q->device &&
6053                     (d->subsystem_vendor == q->subsystem_vendor ||
6054                      q->subsystem_vendor == PCI_ANY_ID) &&
6055                     (d->subsystem_device == q->subsystem_device ||
6056                      q->subsystem_device == PCI_ANY_ID))
6057                         q->hook(dev);
6058         }
6059 }
6060
6061 /* Disable the VGA plane that we never use */
6062 static void i915_disable_vga(struct drm_device *dev)
6063 {
6064         struct drm_i915_private *dev_priv = dev->dev_private;
6065         u8 sr1;
6066         u32 vga_reg;
6067
6068         if (HAS_PCH_SPLIT(dev))
6069                 vga_reg = CPU_VGACNTRL;
6070         else
6071                 vga_reg = VGACNTRL;
6072
6073         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6074         outb(1, VGA_SR_INDEX);
6075         sr1 = inb(VGA_SR_DATA);
6076         outb(sr1 | 1<<5, VGA_SR_DATA);
6077         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6078         udelay(300);
6079
6080         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6081         POSTING_READ(vga_reg);
6082 }
6083
6084 void intel_modeset_init(struct drm_device *dev)
6085 {
6086         struct drm_i915_private *dev_priv = dev->dev_private;
6087         int i;
6088
6089         drm_mode_config_init(dev);
6090
6091         dev->mode_config.min_width = 0;
6092         dev->mode_config.min_height = 0;
6093
6094         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6095
6096         intel_init_quirks(dev);
6097
6098         intel_init_display(dev);
6099
6100         if (IS_GEN2(dev)) {
6101                 dev->mode_config.max_width = 2048;
6102                 dev->mode_config.max_height = 2048;
6103         } else if (IS_GEN3(dev)) {
6104                 dev->mode_config.max_width = 4096;
6105                 dev->mode_config.max_height = 4096;
6106         } else {
6107                 dev->mode_config.max_width = 8192;
6108                 dev->mode_config.max_height = 8192;
6109         }
6110
6111         /* set memory base */
6112         if (IS_GEN2(dev))
6113                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6114         else
6115                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6116
6117         if (IS_MOBILE(dev) || !IS_GEN2(dev))
6118                 dev_priv->num_pipe = 2;
6119         else
6120                 dev_priv->num_pipe = 1;
6121         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6122                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6123
6124         for (i = 0; i < dev_priv->num_pipe; i++) {
6125                 intel_crtc_init(dev, i);
6126         }
6127
6128         intel_setup_outputs(dev);
6129
6130         intel_init_clock_gating(dev);
6131
6132         /* Just disable it once at startup */
6133         i915_disable_vga(dev);
6134
6135         if (IS_IRONLAKE_M(dev)) {
6136                 ironlake_enable_drps(dev);
6137                 intel_init_emon(dev);
6138         }
6139
6140         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6141         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6142                     (unsigned long)dev);
6143
6144         intel_setup_overlay(dev);
6145 }
6146
6147 void intel_modeset_cleanup(struct drm_device *dev)
6148 {
6149         struct drm_i915_private *dev_priv = dev->dev_private;
6150         struct drm_crtc *crtc;
6151         struct intel_crtc *intel_crtc;
6152
6153         drm_kms_helper_poll_fini(dev);
6154         mutex_lock(&dev->struct_mutex);
6155
6156         intel_unregister_dsm_handler();
6157
6158
6159         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6160                 /* Skip inactive CRTCs */
6161                 if (!crtc->fb)
6162                         continue;
6163
6164                 intel_crtc = to_intel_crtc(crtc);
6165                 intel_increase_pllclock(crtc);
6166         }
6167
6168         if (dev_priv->display.disable_fbc)
6169                 dev_priv->display.disable_fbc(dev);
6170
6171         if (dev_priv->renderctx) {
6172                 struct drm_i915_gem_object *obj_priv;
6173
6174                 obj_priv = to_intel_bo(dev_priv->renderctx);
6175                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6176                 I915_READ(CCID);
6177                 i915_gem_object_unpin(dev_priv->renderctx);
6178                 drm_gem_object_unreference(dev_priv->renderctx);
6179         }
6180
6181         if (dev_priv->pwrctx) {
6182                 struct drm_i915_gem_object *obj_priv;
6183
6184                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6185                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6186                 I915_READ(PWRCTXA);
6187                 i915_gem_object_unpin(dev_priv->pwrctx);
6188                 drm_gem_object_unreference(dev_priv->pwrctx);
6189         }
6190
6191         if (IS_IRONLAKE_M(dev))
6192                 ironlake_disable_drps(dev);
6193
6194         mutex_unlock(&dev->struct_mutex);
6195
6196         /* Disable the irq before mode object teardown, for the irq might
6197          * enqueue unpin/hotplug work. */
6198         drm_irq_uninstall(dev);
6199         cancel_work_sync(&dev_priv->hotplug_work);
6200
6201         /* Shut off idle work before the crtcs get freed. */
6202         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6203                 intel_crtc = to_intel_crtc(crtc);
6204                 del_timer_sync(&intel_crtc->idle_timer);
6205         }
6206         del_timer_sync(&dev_priv->idle_timer);
6207         cancel_work_sync(&dev_priv->idle_work);
6208
6209         drm_mode_config_cleanup(dev);
6210 }
6211
6212 /*
6213  * Return which encoder is currently attached for connector.
6214  */
6215 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6216 {
6217         return &intel_attached_encoder(connector)->base;
6218 }
6219
6220 void intel_connector_attach_encoder(struct intel_connector *connector,
6221                                     struct intel_encoder *encoder)
6222 {
6223         connector->encoder = encoder;
6224         drm_mode_connector_attach_encoder(&connector->base,
6225                                           &encoder->base);
6226 }
6227
6228 /*
6229  * set vga decode state - true == enable VGA decode
6230  */
6231 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6232 {
6233         struct drm_i915_private *dev_priv = dev->dev_private;
6234         u16 gmch_ctrl;
6235
6236         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6237         if (state)
6238                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6239         else
6240                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6241         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6242         return 0;
6243 }