drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake / Sandybridge */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (HAS_PCH_SPLIT(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_connector *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 747             if (l_entry->encoder &&
 748                 l_entry->encoder->crtc == crtc) {
 749                     struct intel_output *intel_output = to_intel_output(l_entry);
 750                     if (intel_output->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 struct drm_connector *
 758 intel_pipe_get_output (struct drm_crtc *crtc)
 759 {
 760     struct drm_device *dev = crtc->dev;
 761     struct drm_mode_config *mode_config = &dev->mode_config;
 762     struct drm_connector *l_entry, *ret = NULL;
 763
 764     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 765             if (l_entry->encoder &&
 766                 l_entry->encoder->crtc == crtc) {
 767                     ret = l_entry;
 768                     break;
 769             }
 770     }
 771     return ret;
 772 }
 773
 774 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 775 /**
 776  * Returns whether the given set of divisors are valid for a given refclk with
 777  * the given connectors.
 778  */
 779
 780 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 781 {
 782         const intel_limit_t *limit = intel_limit (crtc);
 783         struct drm_device *dev = crtc->dev;
 784
 785         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 786                 INTELPllInvalid ("p1 out of range\n");
 787         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 788                 INTELPllInvalid ("p out of range\n");
 789         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 790                 INTELPllInvalid ("m2 out of range\n");
 791         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 792                 INTELPllInvalid ("m1 out of range\n");
 793         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 794                 INTELPllInvalid ("m1 <= m2\n");
 795         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 796                 INTELPllInvalid ("m out of range\n");
 797         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 798                 INTELPllInvalid ("n out of range\n");
 799         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 800                 INTELPllInvalid ("vco out of range\n");
 801         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 802          * connector, etc., rather than just a single range.
 803          */
 804         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 805                 INTELPllInvalid ("dot out of range\n");
 806
 807         return true;
 808 }
 809
 810 static bool
 811 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 812                     int target, int refclk, intel_clock_t *best_clock)
 813
 814 {
 815         struct drm_device *dev = crtc->dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         intel_clock_t clock;
 818         int err = target;
 819
 820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 821             (I915_READ(LVDS)) != 0) {
 822                 /*
 823                  * For LVDS, if the panel is on, just rely on its current
 824                  * settings for dual-channel.  We haven't figured out how to
 825                  * reliably set up different single/dual channel state, if we
 826                  * even can.
 827                  */
 828                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 829                     LVDS_CLKB_POWER_UP)
 830                         clock.p2 = limit->p2.p2_fast;
 831                 else
 832                         clock.p2 = limit->p2.p2_slow;
 833         } else {
 834                 if (target < limit->p2.dot_limit)
 835                         clock.p2 = limit->p2.p2_slow;
 836                 else
 837                         clock.p2 = limit->p2.p2_fast;
 838         }
 839
 840         memset (best_clock, 0, sizeof (*best_clock));
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         /* m1 is always 0 in Pineview */
 847                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 848                                 break;
 849                         for (clock.n = limit->n.min;
 850                              clock.n <= limit->n.max; clock.n++) {
 851                                 for (clock.p1 = limit->p1.min;
 852                                         clock.p1 <= limit->p1.max; clock.p1++) {
 853                                         int this_err;
 854
 855                                         intel_clock(dev, refclk, &clock);
 856
 857                                         if (!intel_PLL_is_valid(crtc, &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 875                         int target, int refclk, intel_clock_t *best_clock)
 876 {
 877         struct drm_device *dev = crtc->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         intel_clock_t clock;
 880         int max_n;
 881         bool found;
 882         /* approximately equals target * 0.00488 */
 883         int err_most = (target >> 8) + (target >> 10);
 884         found = false;
 885
 886         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 887                 int lvds_reg;
 888
 889                 if (HAS_PCH_SPLIT(dev))
 890                         lvds_reg = PCH_LVDS;
 891                 else
 892                         lvds_reg = LVDS;
 893                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 894                     LVDS_CLKB_POWER_UP)
 895                         clock.p2 = limit->p2.p2_fast;
 896                 else
 897                         clock.p2 = limit->p2.p2_slow;
 898         } else {
 899                 if (target < limit->p2.dot_limit)
 900                         clock.p2 = limit->p2.p2_slow;
 901                 else
 902                         clock.p2 = limit->p2.p2_fast;
 903         }
 904
 905         memset(best_clock, 0, sizeof(*best_clock));
 906         max_n = limit->n.max;
 907         /* based on hardware requriment prefer smaller n to precision */
 908         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 909                 /* based on hardware requirment prefere larger m1,m2 */
 910                 for (clock.m1 = limit->m1.max;
 911                      clock.m1 >= limit->m1.min; clock.m1--) {
 912                         for (clock.m2 = limit->m2.max;
 913                              clock.m2 >= limit->m2.min; clock.m2--) {
 914                                 for (clock.p1 = limit->p1.max;
 915                                      clock.p1 >= limit->p1.min; clock.p1--) {
 916                                         int this_err;
 917
 918                                         intel_clock(dev, refclk, &clock);
 919                                         if (!intel_PLL_is_valid(crtc, &clock))
 920                                                 continue;
 921                                         this_err = abs(clock.dot - target) ;
 922                                         if (this_err < err_most) {
 923                                                 *best_clock = clock;
 924                                                 err_most = this_err;
 925                                                 max_n = clock.n;
 926                                                 found = true;
 927                                         }
 928                                 }
 929                         }
 930                 }
 931         }
 932         return found;
 933 }
 934
 935 static bool
 936 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 937                            int target, int refclk, intel_clock_t *best_clock)
 938 {
 939         struct drm_device *dev = crtc->dev;
 940         intel_clock_t clock;
 941
 942         /* return directly when it is eDP */
 943         if (HAS_eDP)
 944                 return true;
 945
 946         if (target < 200000) {
 947                 clock.n = 1;
 948                 clock.p1 = 2;
 949                 clock.p2 = 10;
 950                 clock.m1 = 12;
 951                 clock.m2 = 9;
 952         } else {
 953                 clock.n = 2;
 954                 clock.p1 = 1;
 955                 clock.p2 = 10;
 956                 clock.m1 = 14;
 957                 clock.m2 = 8;
 958         }
 959         intel_clock(dev, refclk, &clock);
 960         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 961         return true;
 962 }
 963
 964 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 965 static bool
 966 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 967                       int target, int refclk, intel_clock_t *best_clock)
 968 {
 969     intel_clock_t clock;
 970     if (target < 200000) {
 971         clock.p1 = 2;
 972         clock.p2 = 10;
 973         clock.n = 2;
 974         clock.m1 = 23;
 975         clock.m2 = 8;
 976     } else {
 977         clock.p1 = 1;
 978         clock.p2 = 10;
 979         clock.n = 1;
 980         clock.m1 = 14;
 981         clock.m2 = 2;
 982     }
 983     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 984     clock.p = (clock.p1 * clock.p2);
 985     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 986     clock.vco = 0;
 987     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 988     return true;
 989 }
 990
 991 void
 992 intel_wait_for_vblank(struct drm_device *dev)
 993 {
 994         /* Wait for 20ms, i.e. one cycle at 50hz. */
 995         msleep(20);
 996 }
 997
 998 /* Parameters have changed, update FBC info */
 999 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1000 {
1001         struct drm_device *dev = crtc->dev;
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         struct drm_framebuffer *fb = crtc->fb;
1004         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1005         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007         int plane, i;
1008         u32 fbc_ctl, fbc_ctl2;
1009
1010         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1011
1012         if (fb->pitch < dev_priv->cfb_pitch)
1013                 dev_priv->cfb_pitch = fb->pitch;
1014
1015         /* FBC_CTL wants 64B units */
1016         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1017         dev_priv->cfb_fence = obj_priv->fence_reg;
1018         dev_priv->cfb_plane = intel_crtc->plane;
1019         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1020
1021         /* Clear old tags */
1022         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1023                 I915_WRITE(FBC_TAG + (i * 4), 0);
1024
1025         /* Set it up... */
1026         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1027         if (obj_priv->tiling_mode != I915_TILING_NONE)
1028                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1029         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1030         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1031
1032         /* enable it... */
1033         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034         if (IS_I945GM(dev))
1035                 fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
1036         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1037         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1038         if (obj_priv->tiling_mode != I915_TILING_NONE)
1039                 fbc_ctl |= dev_priv->cfb_fence;
1040         I915_WRITE(FBC_CONTROL, fbc_ctl);
1041
1042         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1043                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1044 }
1045
1046 void i8xx_disable_fbc(struct drm_device *dev)
1047 {
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         u32 fbc_ctl;
1050
1051         if (!I915_HAS_FBC(dev))
1052                 return;
1053
1054         /* Disable compression */
1055         fbc_ctl = I915_READ(FBC_CONTROL);
1056         fbc_ctl &= ~FBC_CTL_EN;
1057         I915_WRITE(FBC_CONTROL, fbc_ctl);
1058
1059         /* Wait for compressing bit to clear */
1060         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1061                 ; /* nothing */
1062
1063         intel_wait_for_vblank(dev);
1064
1065         DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1069 {
1070         struct drm_device *dev = crtc->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072
1073         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1074 }
1075
1076 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1077 {
1078         struct drm_device *dev = crtc->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         struct drm_framebuffer *fb = crtc->fb;
1081         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1082         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1084         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1085                      DPFC_CTL_PLANEB);
1086         unsigned long stall_watermark = 200;
1087         u32 dpfc_ctl;
1088
1089         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1090         dev_priv->cfb_fence = obj_priv->fence_reg;
1091         dev_priv->cfb_plane = intel_crtc->plane;
1092
1093         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1094         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1095                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1096                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1097         } else {
1098                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1099         }
1100
1101         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1102         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1103                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1104                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1105         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1106
1107         /* enable it... */
1108         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1109
1110         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1111 }
1112
1113 void g4x_disable_fbc(struct drm_device *dev)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         u32 dpfc_ctl;
1117
1118         /* Disable compression */
1119         dpfc_ctl = I915_READ(DPFC_CONTROL);
1120         dpfc_ctl &= ~DPFC_CTL_EN;
1121         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1122         intel_wait_for_vblank(dev);
1123
1124         DRM_DEBUG_KMS("disabled FBC\n");
1125 }
1126
1127 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1128 {
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1133 }
1134
1135 /**
1136  * intel_update_fbc - enable/disable FBC as needed
1137  * @crtc: CRTC to point the compressor at
1138  * @mode: mode in use
1139  *
1140  * Set up the framebuffer compression hardware at mode set time.  We
1141  * enable it if possible:
1142  *   - plane A only (on pre-965)
1143  *   - no pixel mulitply/line duplication
1144  *   - no alpha buffer discard
1145  *   - no dual wide
1146  *   - framebuffer <= 2048 in width, 1536 in height
1147  *
1148  * We can't assume that any compression will take place (worst case),
1149  * so the compressed buffer has to be the same size as the uncompressed
1150  * one.  It also must reside (along with the line length buffer) in
1151  * stolen memory.
1152  *
1153  * We need to enable/disable FBC on a global basis.
1154  */
1155 static void intel_update_fbc(struct drm_crtc *crtc,
1156                              struct drm_display_mode *mode)
1157 {
1158         struct drm_device *dev = crtc->dev;
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160         struct drm_framebuffer *fb = crtc->fb;
1161         struct intel_framebuffer *intel_fb;
1162         struct drm_i915_gem_object *obj_priv;
1163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1164         int plane = intel_crtc->plane;
1165
1166         if (!i915_powersave)
1167                 return;
1168
1169         if (!dev_priv->display.fbc_enabled ||
1170             !dev_priv->display.enable_fbc ||
1171             !dev_priv->display.disable_fbc)
1172                 return;
1173
1174         if (!crtc->fb)
1175                 return;
1176
1177         intel_fb = to_intel_framebuffer(fb);
1178         obj_priv = intel_fb->obj->driver_private;
1179
1180         /*
1181          * If FBC is already on, we just have to verify that we can
1182          * keep it that way...
1183          * Need to disable if:
1184          *   - changing FBC params (stride, fence, mode)
1185          *   - new fb is too large to fit in compressed buffer
1186          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1187          */
1188         if (intel_fb->obj->size > dev_priv->cfb_size) {
1189                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1190                                 "compression\n");
1191                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1192                 goto out_disable;
1193         }
1194         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1195             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1196                 DRM_DEBUG_KMS("mode incompatible with compression, "
1197                                 "disabling\n");
1198                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1199                 goto out_disable;
1200         }
1201         if ((mode->hdisplay > 2048) ||
1202             (mode->vdisplay > 1536)) {
1203                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1204                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1205                 goto out_disable;
1206         }
1207         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1208                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1209                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1210                 goto out_disable;
1211         }
1212         if (obj_priv->tiling_mode != I915_TILING_X) {
1213                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1214                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1215                 goto out_disable;
1216         }
1217
1218         if (dev_priv->display.fbc_enabled(crtc)) {
1219                 /* We can re-enable it in this case, but need to update pitch */
1220                 if (fb->pitch > dev_priv->cfb_pitch)
1221                         dev_priv->display.disable_fbc(dev);
1222                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1223                         dev_priv->display.disable_fbc(dev);
1224                 if (plane != dev_priv->cfb_plane)
1225                         dev_priv->display.disable_fbc(dev);
1226         }
1227
1228         if (!dev_priv->display.fbc_enabled(crtc)) {
1229                 /* Now try to turn it back on if possible */
1230                 dev_priv->display.enable_fbc(crtc, 500);
1231         }
1232
1233         return;
1234
1235 out_disable:
1236         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1237         /* Multiple disables should be harmless */
1238         if (dev_priv->display.fbc_enabled(crtc))
1239                 dev_priv->display.disable_fbc(dev);
1240 }
1241
1242 static int
1243 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1244 {
1245         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1246         u32 alignment;
1247         int ret;
1248
1249         switch (obj_priv->tiling_mode) {
1250         case I915_TILING_NONE:
1251                 alignment = 64 * 1024;
1252                 break;
1253         case I915_TILING_X:
1254                 /* pin() will align the object as required by fence */
1255                 alignment = 0;
1256                 break;
1257         case I915_TILING_Y:
1258                 /* FIXME: Is this true? */
1259                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1260                 return -EINVAL;
1261         default:
1262                 BUG();
1263         }
1264
1265         ret = i915_gem_object_pin(obj, alignment);
1266         if (ret != 0)
1267                 return ret;
1268
1269         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1270          * fence, whereas 965+ only requires a fence if using
1271          * framebuffer compression.  For simplicity, we always install
1272          * a fence as the cost is not that onerous.
1273          */
1274         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1275             obj_priv->tiling_mode != I915_TILING_NONE) {
1276                 ret = i915_gem_object_get_fence_reg(obj);
1277                 if (ret != 0) {
1278                         i915_gem_object_unpin(obj);
1279                         return ret;
1280                 }
1281         }
1282
1283         return 0;
1284 }
1285
1286 static int
1287 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1288                     struct drm_framebuffer *old_fb)
1289 {
1290         struct drm_device *dev = crtc->dev;
1291         struct drm_i915_private *dev_priv = dev->dev_private;
1292         struct drm_i915_master_private *master_priv;
1293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1294         struct intel_framebuffer *intel_fb;
1295         struct drm_i915_gem_object *obj_priv;
1296         struct drm_gem_object *obj;
1297         int pipe = intel_crtc->pipe;
1298         int plane = intel_crtc->plane;
1299         unsigned long Start, Offset;
1300         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1301         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1302         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1303         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1304         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1305         u32 dspcntr;
1306         int ret;
1307
1308         /* no fb bound */
1309         if (!crtc->fb) {
1310                 DRM_DEBUG_KMS("No FB bound\n");
1311                 return 0;
1312         }
1313
1314         switch (plane) {
1315         case 0:
1316         case 1:
1317                 break;
1318         default:
1319                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1320                 return -EINVAL;
1321         }
1322
1323         intel_fb = to_intel_framebuffer(crtc->fb);
1324         obj = intel_fb->obj;
1325         obj_priv = obj->driver_private;
1326
1327         mutex_lock(&dev->struct_mutex);
1328         ret = intel_pin_and_fence_fb_obj(dev, obj);
1329         if (ret != 0) {
1330                 mutex_unlock(&dev->struct_mutex);
1331                 return ret;
1332         }
1333
1334         ret = i915_gem_object_set_to_display_plane(obj);
1335         if (ret != 0) {
1336                 i915_gem_object_unpin(obj);
1337                 mutex_unlock(&dev->struct_mutex);
1338                 return ret;
1339         }
1340
1341         dspcntr = I915_READ(dspcntr_reg);
1342         /* Mask out pixel format bits in case we change it */
1343         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1344         switch (crtc->fb->bits_per_pixel) {
1345         case 8:
1346                 dspcntr |= DISPPLANE_8BPP;
1347                 break;
1348         case 16:
1349                 if (crtc->fb->depth == 15)
1350                         dspcntr |= DISPPLANE_15_16BPP;
1351                 else
1352                         dspcntr |= DISPPLANE_16BPP;
1353                 break;
1354         case 24:
1355         case 32:
1356                 if (crtc->fb->depth == 30)
1357                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1358                 else
1359                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1360                 break;
1361         default:
1362                 DRM_ERROR("Unknown color depth\n");
1363                 i915_gem_object_unpin(obj);
1364                 mutex_unlock(&dev->struct_mutex);
1365                 return -EINVAL;
1366         }
1367         if (IS_I965G(dev)) {
1368                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1369                         dspcntr |= DISPPLANE_TILED;
1370                 else
1371                         dspcntr &= ~DISPPLANE_TILED;
1372         }
1373
1374         if (HAS_PCH_SPLIT(dev))
1375                 /* must disable */
1376                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1377
1378         I915_WRITE(dspcntr_reg, dspcntr);
1379
1380         Start = obj_priv->gtt_offset;
1381         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1382
1383         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1384         I915_WRITE(dspstride, crtc->fb->pitch);
1385         if (IS_I965G(dev)) {
1386                 I915_WRITE(dspbase, Offset);
1387                 I915_READ(dspbase);
1388                 I915_WRITE(dspsurf, Start);
1389                 I915_READ(dspsurf);
1390                 I915_WRITE(dsptileoff, (y << 16) | x);
1391         } else {
1392                 I915_WRITE(dspbase, Start + Offset);
1393                 I915_READ(dspbase);
1394         }
1395
1396         if ((IS_I965G(dev) || plane == 0))
1397                 intel_update_fbc(crtc, &crtc->mode);
1398
1399         intel_wait_for_vblank(dev);
1400
1401         if (old_fb) {
1402                 intel_fb = to_intel_framebuffer(old_fb);
1403                 obj_priv = intel_fb->obj->driver_private;
1404                 i915_gem_object_unpin(intel_fb->obj);
1405         }
1406         intel_increase_pllclock(crtc, true);
1407
1408         mutex_unlock(&dev->struct_mutex);
1409
1410         if (!dev->primary->master)
1411                 return 0;
1412
1413         master_priv = dev->primary->master->driver_priv;
1414         if (!master_priv->sarea_priv)
1415                 return 0;
1416
1417         if (pipe) {
1418                 master_priv->sarea_priv->pipeB_x = x;
1419                 master_priv->sarea_priv->pipeB_y = y;
1420         } else {
1421                 master_priv->sarea_priv->pipeA_x = x;
1422                 master_priv->sarea_priv->pipeA_y = y;
1423         }
1424
1425         return 0;
1426 }
1427
1428 /* Disable the VGA plane that we never use */
1429 static void i915_disable_vga (struct drm_device *dev)
1430 {
1431         struct drm_i915_private *dev_priv = dev->dev_private;
1432         u8 sr1;
1433         u32 vga_reg;
1434
1435         if (HAS_PCH_SPLIT(dev))
1436                 vga_reg = CPU_VGACNTRL;
1437         else
1438                 vga_reg = VGACNTRL;
1439
1440         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1441                 return;
1442
1443         I915_WRITE8(VGA_SR_INDEX, 1);
1444         sr1 = I915_READ8(VGA_SR_DATA);
1445         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1446         udelay(100);
1447
1448         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1449 }
1450
1451 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1452 {
1453         struct drm_device *dev = crtc->dev;
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455         u32 dpa_ctl;
1456
1457         DRM_DEBUG_KMS("\n");
1458         dpa_ctl = I915_READ(DP_A);
1459         dpa_ctl &= ~DP_PLL_ENABLE;
1460         I915_WRITE(DP_A, dpa_ctl);
1461 }
1462
1463 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1464 {
1465         struct drm_device *dev = crtc->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467         u32 dpa_ctl;
1468
1469         dpa_ctl = I915_READ(DP_A);
1470         dpa_ctl |= DP_PLL_ENABLE;
1471         I915_WRITE(DP_A, dpa_ctl);
1472         udelay(200);
1473 }
1474
1475
1476 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1477 {
1478         struct drm_device *dev = crtc->dev;
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480         u32 dpa_ctl;
1481
1482         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1483         dpa_ctl = I915_READ(DP_A);
1484         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1485
1486         if (clock < 200000) {
1487                 u32 temp;
1488                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1489                 /* workaround for 160Mhz:
1490                    1) program 0x4600c bits 15:0 = 0x8124
1491                    2) program 0x46010 bit 0 = 1
1492                    3) program 0x46034 bit 24 = 1
1493                    4) program 0x64000 bit 14 = 1
1494                    */
1495                 temp = I915_READ(0x4600c);
1496                 temp &= 0xffff0000;
1497                 I915_WRITE(0x4600c, temp | 0x8124);
1498
1499                 temp = I915_READ(0x46010);
1500                 I915_WRITE(0x46010, temp | 1);
1501
1502                 temp = I915_READ(0x46034);
1503                 I915_WRITE(0x46034, temp | (1 << 24));
1504         } else {
1505                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1506         }
1507         I915_WRITE(DP_A, dpa_ctl);
1508
1509         udelay(500);
1510 }
1511
1512 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1513 {
1514         struct drm_device *dev = crtc->dev;
1515         struct drm_i915_private *dev_priv = dev->dev_private;
1516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1517         int pipe = intel_crtc->pipe;
1518         int plane = intel_crtc->plane;
1519         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1520         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1521         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1522         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1523         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1524         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1525         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1526         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1527         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1528         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1529         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1530         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1531         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1532         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1533         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1534         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1535         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1536         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1537         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1538         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1539         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1540         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1541         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1542         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1543         u32 temp;
1544         int tries = 5, j, n;
1545         u32 pipe_bpc;
1546
1547         temp = I915_READ(pipeconf_reg);
1548         pipe_bpc = temp & PIPE_BPC_MASK;
1549
1550         /* XXX: When our outputs are all unaware of DPMS modes other than off
1551          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1552          */
1553         switch (mode) {
1554         case DRM_MODE_DPMS_ON:
1555         case DRM_MODE_DPMS_STANDBY:
1556         case DRM_MODE_DPMS_SUSPEND:
1557                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1558
1559                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1560                         temp = I915_READ(PCH_LVDS);
1561                         if ((temp & LVDS_PORT_EN) == 0) {
1562                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1563                                 POSTING_READ(PCH_LVDS);
1564                         }
1565                 }
1566
1567                 if (HAS_eDP) {
1568                         /* enable eDP PLL */
1569                         ironlake_enable_pll_edp(crtc);
1570                 } else {
1571                         /* enable PCH DPLL */
1572                         temp = I915_READ(pch_dpll_reg);
1573                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1574                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1575                                 I915_READ(pch_dpll_reg);
1576                         }
1577
1578                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1579                         temp = I915_READ(fdi_rx_reg);
1580                         /*
1581                          * make the BPC in FDI Rx be consistent with that in
1582                          * pipeconf reg.
1583                          */
1584                         temp &= ~(0x7 << 16);
1585                         temp |= (pipe_bpc << 11);
1586                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1587                                         FDI_SEL_PCDCLK |
1588                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1589                         I915_READ(fdi_rx_reg);
1590                         udelay(200);
1591
1592                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1593                         temp = I915_READ(fdi_tx_reg);
1594                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1595                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1596                                 I915_READ(fdi_tx_reg);
1597                                 udelay(100);
1598                         }
1599                 }
1600
1601                 /* Enable panel fitting for LVDS */
1602                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1603                         temp = I915_READ(pf_ctl_reg);
1604                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1605
1606                         /* currently full aspect */
1607                         I915_WRITE(pf_win_pos, 0);
1608
1609                         I915_WRITE(pf_win_size,
1610                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1611                                    (dev_priv->panel_fixed_mode->vdisplay));
1612                 }
1613
1614                 /* Enable CPU pipe */
1615                 temp = I915_READ(pipeconf_reg);
1616                 if ((temp & PIPEACONF_ENABLE) == 0) {
1617                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1618                         I915_READ(pipeconf_reg);
1619                         udelay(100);
1620                 }
1621
1622                 /* configure and enable CPU plane */
1623                 temp = I915_READ(dspcntr_reg);
1624                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1625                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1626                         /* Flush the plane changes */
1627                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1628                 }
1629
1630                 if (!HAS_eDP) {
1631                         /* enable CPU FDI TX and PCH FDI RX */
1632                         temp = I915_READ(fdi_tx_reg);
1633                         temp |= FDI_TX_ENABLE;
1634                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1635                         temp &= ~FDI_LINK_TRAIN_NONE;
1636                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1637                         I915_WRITE(fdi_tx_reg, temp);
1638                         I915_READ(fdi_tx_reg);
1639
1640                         temp = I915_READ(fdi_rx_reg);
1641                         temp &= ~FDI_LINK_TRAIN_NONE;
1642                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1643                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1644                         I915_READ(fdi_rx_reg);
1645
1646                         udelay(150);
1647
1648                         /* Train FDI. */
1649                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1650                            for train result */
1651                         temp = I915_READ(fdi_rx_imr_reg);
1652                         temp &= ~FDI_RX_SYMBOL_LOCK;
1653                         temp &= ~FDI_RX_BIT_LOCK;
1654                         I915_WRITE(fdi_rx_imr_reg, temp);
1655                         I915_READ(fdi_rx_imr_reg);
1656                         udelay(150);
1657
1658                         temp = I915_READ(fdi_rx_iir_reg);
1659                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1660
1661                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1662                                 for (j = 0; j < tries; j++) {
1663                                         temp = I915_READ(fdi_rx_iir_reg);
1664                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1665                                                                 temp);
1666                                         if (temp & FDI_RX_BIT_LOCK)
1667                                                 break;
1668                                         udelay(200);
1669                                 }
1670                                 if (j != tries)
1671                                         I915_WRITE(fdi_rx_iir_reg,
1672                                                         temp | FDI_RX_BIT_LOCK);
1673                                 else
1674                                         DRM_DEBUG_KMS("train 1 fail\n");
1675                         } else {
1676                                 I915_WRITE(fdi_rx_iir_reg,
1677                                                 temp | FDI_RX_BIT_LOCK);
1678                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1679                         }
1680                         temp = I915_READ(fdi_tx_reg);
1681                         temp &= ~FDI_LINK_TRAIN_NONE;
1682                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1683                         I915_WRITE(fdi_tx_reg, temp);
1684
1685                         temp = I915_READ(fdi_rx_reg);
1686                         temp &= ~FDI_LINK_TRAIN_NONE;
1687                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1688                         I915_WRITE(fdi_rx_reg, temp);
1689
1690                         udelay(150);
1691
1692                         temp = I915_READ(fdi_rx_iir_reg);
1693                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1694
1695                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1696                                 for (j = 0; j < tries; j++) {
1697                                         temp = I915_READ(fdi_rx_iir_reg);
1698                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1699                                                                 temp);
1700                                         if (temp & FDI_RX_SYMBOL_LOCK)
1701                                                 break;
1702                                         udelay(200);
1703                                 }
1704                                 if (j != tries) {
1705                                         I915_WRITE(fdi_rx_iir_reg,
1706                                                         temp | FDI_RX_SYMBOL_LOCK);
1707                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1708                                 } else
1709                                         DRM_DEBUG_KMS("train 2 fail\n");
1710                         } else {
1711                                 I915_WRITE(fdi_rx_iir_reg,
1712                                                 temp | FDI_RX_SYMBOL_LOCK);
1713                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1714                         }
1715                         DRM_DEBUG_KMS("train done\n");
1716
1717                         /* set transcoder timing */
1718                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1719                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1720                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1721
1722                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1723                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1724                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1725
1726                         /* enable PCH transcoder */
1727                         temp = I915_READ(transconf_reg);
1728                         /*
1729                          * make the BPC in transcoder be consistent with
1730                          * that in pipeconf reg.
1731                          */
1732                         temp &= ~PIPE_BPC_MASK;
1733                         temp |= pipe_bpc;
1734                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1735                         I915_READ(transconf_reg);
1736
1737                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1738                                 ;
1739
1740                         /* enable normal */
1741
1742                         temp = I915_READ(fdi_tx_reg);
1743                         temp &= ~FDI_LINK_TRAIN_NONE;
1744                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1745                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1746                         I915_READ(fdi_tx_reg);
1747
1748                         temp = I915_READ(fdi_rx_reg);
1749                         temp &= ~FDI_LINK_TRAIN_NONE;
1750                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1751                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1752                         I915_READ(fdi_rx_reg);
1753
1754                         /* wait one idle pattern time */
1755                         udelay(100);
1756
1757                 }
1758
1759                 intel_crtc_load_lut(crtc);
1760
1761         break;
1762         case DRM_MODE_DPMS_OFF:
1763                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1764
1765                 drm_vblank_off(dev, pipe);
1766                 /* Disable display plane */
1767                 temp = I915_READ(dspcntr_reg);
1768                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1769                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1770                         /* Flush the plane changes */
1771                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1772                         I915_READ(dspbase_reg);
1773                 }
1774
1775                 i915_disable_vga(dev);
1776
1777                 /* disable cpu pipe, disable after all planes disabled */
1778                 temp = I915_READ(pipeconf_reg);
1779                 if ((temp & PIPEACONF_ENABLE) != 0) {
1780                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1781                         I915_READ(pipeconf_reg);
1782                         n = 0;
1783                         /* wait for cpu pipe off, pipe state */
1784                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1785                                 n++;
1786                                 if (n < 60) {
1787                                         udelay(500);
1788                                         continue;
1789                                 } else {
1790                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1791                                                                 pipe);
1792                                         break;
1793                                 }
1794                         }
1795                 } else
1796                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1797
1798                 udelay(100);
1799
1800                 /* Disable PF */
1801                 temp = I915_READ(pf_ctl_reg);
1802                 if ((temp & PF_ENABLE) != 0) {
1803                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1804                         I915_READ(pf_ctl_reg);
1805                 }
1806                 I915_WRITE(pf_win_size, 0);
1807
1808                 /* disable CPU FDI tx and PCH FDI rx */
1809                 temp = I915_READ(fdi_tx_reg);
1810                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1811                 I915_READ(fdi_tx_reg);
1812
1813                 temp = I915_READ(fdi_rx_reg);
1814                 /* BPC in FDI rx is consistent with that in pipeconf */
1815                 temp &= ~(0x07 << 16);
1816                 temp |= (pipe_bpc << 11);
1817                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1818                 I915_READ(fdi_rx_reg);
1819
1820                 udelay(100);
1821
1822                 /* still set train pattern 1 */
1823                 temp = I915_READ(fdi_tx_reg);
1824                 temp &= ~FDI_LINK_TRAIN_NONE;
1825                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1826                 I915_WRITE(fdi_tx_reg, temp);
1827
1828                 temp = I915_READ(fdi_rx_reg);
1829                 temp &= ~FDI_LINK_TRAIN_NONE;
1830                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1831                 I915_WRITE(fdi_rx_reg, temp);
1832
1833                 udelay(100);
1834
1835                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1836                         temp = I915_READ(PCH_LVDS);
1837                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1838                         I915_READ(PCH_LVDS);
1839                         udelay(100);
1840                 }
1841
1842                 /* disable PCH transcoder */
1843                 temp = I915_READ(transconf_reg);
1844                 if ((temp & TRANS_ENABLE) != 0) {
1845                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1846                         I915_READ(transconf_reg);
1847                         n = 0;
1848                         /* wait for PCH transcoder off, transcoder state */
1849                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1850                                 n++;
1851                                 if (n < 60) {
1852                                         udelay(500);
1853                                         continue;
1854                                 } else {
1855                                         DRM_DEBUG_KMS("transcoder %d off "
1856                                                         "delay\n", pipe);
1857                                         break;
1858                                 }
1859                         }
1860                 }
1861                 temp = I915_READ(transconf_reg);
1862                 /* BPC in transcoder is consistent with that in pipeconf */
1863                 temp &= ~PIPE_BPC_MASK;
1864                 temp |= pipe_bpc;
1865                 I915_WRITE(transconf_reg, temp);
1866                 I915_READ(transconf_reg);
1867                 udelay(100);
1868
1869                 /* disable PCH DPLL */
1870                 temp = I915_READ(pch_dpll_reg);
1871                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1872                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1873                         I915_READ(pch_dpll_reg);
1874                 }
1875
1876                 if (HAS_eDP) {
1877                         ironlake_disable_pll_edp(crtc);
1878                 }
1879
1880                 temp = I915_READ(fdi_rx_reg);
1881                 temp &= ~FDI_SEL_PCDCLK;
1882                 I915_WRITE(fdi_rx_reg, temp);
1883                 I915_READ(fdi_rx_reg);
1884
1885                 temp = I915_READ(fdi_rx_reg);
1886                 temp &= ~FDI_RX_PLL_ENABLE;
1887                 I915_WRITE(fdi_rx_reg, temp);
1888                 I915_READ(fdi_rx_reg);
1889
1890                 /* Disable CPU FDI TX PLL */
1891                 temp = I915_READ(fdi_tx_reg);
1892                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1893                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1894                         I915_READ(fdi_tx_reg);
1895                         udelay(100);
1896                 }
1897
1898                 /* Wait for the clocks to turn off. */
1899                 udelay(100);
1900                 break;
1901         }
1902 }
1903
1904 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1905 {
1906         struct intel_overlay *overlay;
1907         int ret;
1908
1909         if (!enable && intel_crtc->overlay) {
1910                 overlay = intel_crtc->overlay;
1911                 mutex_lock(&overlay->dev->struct_mutex);
1912                 for (;;) {
1913                         ret = intel_overlay_switch_off(overlay);
1914                         if (ret == 0)
1915                                 break;
1916
1917                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1918                         if (ret != 0) {
1919                                 /* overlay doesn't react anymore. Usually
1920                                  * results in a black screen and an unkillable
1921                                  * X server. */
1922                                 BUG();
1923                                 overlay->hw_wedged = HW_WEDGED;
1924                                 break;
1925                         }
1926                 }
1927                 mutex_unlock(&overlay->dev->struct_mutex);
1928         }
1929         /* Let userspace switch the overlay on again. In most cases userspace
1930          * has to recompute where to put it anyway. */
1931
1932         return;
1933 }
1934
1935 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1936 {
1937         struct drm_device *dev = crtc->dev;
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1940         int pipe = intel_crtc->pipe;
1941         int plane = intel_crtc->plane;
1942         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1943         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1944         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1945         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1946         u32 temp;
1947
1948         /* XXX: When our outputs are all unaware of DPMS modes other than off
1949          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1950          */
1951         switch (mode) {
1952         case DRM_MODE_DPMS_ON:
1953         case DRM_MODE_DPMS_STANDBY:
1954         case DRM_MODE_DPMS_SUSPEND:
1955                 intel_update_watermarks(dev);
1956
1957                 /* Enable the DPLL */
1958                 temp = I915_READ(dpll_reg);
1959                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1960                         I915_WRITE(dpll_reg, temp);
1961                         I915_READ(dpll_reg);
1962                         /* Wait for the clocks to stabilize. */
1963                         udelay(150);
1964                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1965                         I915_READ(dpll_reg);
1966                         /* Wait for the clocks to stabilize. */
1967                         udelay(150);
1968                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1969                         I915_READ(dpll_reg);
1970                         /* Wait for the clocks to stabilize. */
1971                         udelay(150);
1972                 }
1973
1974                 /* Enable the pipe */
1975                 temp = I915_READ(pipeconf_reg);
1976                 if ((temp & PIPEACONF_ENABLE) == 0)
1977                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1978
1979                 /* Enable the plane */
1980                 temp = I915_READ(dspcntr_reg);
1981                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1982                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1983                         /* Flush the plane changes */
1984                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1985                 }
1986
1987                 intel_crtc_load_lut(crtc);
1988
1989                 if ((IS_I965G(dev) || plane == 0))
1990                         intel_update_fbc(crtc, &crtc->mode);
1991
1992                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1993                 intel_crtc_dpms_overlay(intel_crtc, true);
1994         break;
1995         case DRM_MODE_DPMS_OFF:
1996                 intel_update_watermarks(dev);
1997
1998                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1999                 intel_crtc_dpms_overlay(intel_crtc, false);
2000                 drm_vblank_off(dev, pipe);
2001
2002                 if (dev_priv->cfb_plane == plane &&
2003                     dev_priv->display.disable_fbc)
2004                         dev_priv->display.disable_fbc(dev);
2005
2006                 /* Disable the VGA plane that we never use */
2007                 i915_disable_vga(dev);
2008
2009                 /* Disable display plane */
2010                 temp = I915_READ(dspcntr_reg);
2011                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2012                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2013                         /* Flush the plane changes */
2014                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2015                         I915_READ(dspbase_reg);
2016                 }
2017
2018                 if (!IS_I9XX(dev)) {
2019                         /* Wait for vblank for the disable to take effect */
2020                         intel_wait_for_vblank(dev);
2021                 }
2022
2023                 /* Next, disable display pipes */
2024                 temp = I915_READ(pipeconf_reg);
2025                 if ((temp & PIPEACONF_ENABLE) != 0) {
2026                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2027                         I915_READ(pipeconf_reg);
2028                 }
2029
2030                 /* Wait for vblank for the disable to take effect. */
2031                 intel_wait_for_vblank(dev);
2032
2033                 temp = I915_READ(dpll_reg);
2034                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2035                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2036                         I915_READ(dpll_reg);
2037                 }
2038
2039                 /* Wait for the clocks to turn off. */
2040                 udelay(150);
2041                 break;
2042         }
2043 }
2044
2045 /**
2046  * Sets the power management mode of the pipe and plane.
2047  *
2048  * This code should probably grow support for turning the cursor off and back
2049  * on appropriately at the same time as we're turning the pipe off/on.
2050  */
2051 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2052 {
2053         struct drm_device *dev = crtc->dev;
2054         struct drm_i915_private *dev_priv = dev->dev_private;
2055         struct drm_i915_master_private *master_priv;
2056         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2057         int pipe = intel_crtc->pipe;
2058         bool enabled;
2059
2060         dev_priv->display.dpms(crtc, mode);
2061
2062         intel_crtc->dpms_mode = mode;
2063
2064         if (!dev->primary->master)
2065                 return;
2066
2067         master_priv = dev->primary->master->driver_priv;
2068         if (!master_priv->sarea_priv)
2069                 return;
2070
2071         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2072
2073         switch (pipe) {
2074         case 0:
2075                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2076                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2077                 break;
2078         case 1:
2079                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2080                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2081                 break;
2082         default:
2083                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2084                 break;
2085         }
2086 }
2087
2088 static void intel_crtc_prepare (struct drm_crtc *crtc)
2089 {
2090         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2091         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2092 }
2093
2094 static void intel_crtc_commit (struct drm_crtc *crtc)
2095 {
2096         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2097         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2098 }
2099
2100 void intel_encoder_prepare (struct drm_encoder *encoder)
2101 {
2102         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2103         /* lvds has its own version of prepare see intel_lvds_prepare */
2104         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2105 }
2106
2107 void intel_encoder_commit (struct drm_encoder *encoder)
2108 {
2109         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2110         /* lvds has its own version of commit see intel_lvds_commit */
2111         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2112 }
2113
2114 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2115                                   struct drm_display_mode *mode,
2116                                   struct drm_display_mode *adjusted_mode)
2117 {
2118         struct drm_device *dev = crtc->dev;
2119         if (HAS_PCH_SPLIT(dev)) {
2120                 /* FDI link clock is fixed at 2.7G */
2121                 if (mode->clock * 3 > 27000 * 4)
2122                         return MODE_CLOCK_HIGH;
2123         }
2124         return true;
2125 }
2126
2127 static int i945_get_display_clock_speed(struct drm_device *dev)
2128 {
2129         return 400000;
2130 }
2131
2132 static int i915_get_display_clock_speed(struct drm_device *dev)
2133 {
2134         return 333000;
2135 }
2136
2137 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2138 {
2139         return 200000;
2140 }
2141
2142 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2143 {
2144         u16 gcfgc = 0;
2145
2146         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2147
2148         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2149                 return 133000;
2150         else {
2151                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2152                 case GC_DISPLAY_CLOCK_333_MHZ:
2153                         return 333000;
2154                 default:
2155                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2156                         return 190000;
2157                 }
2158         }
2159 }
2160
2161 static int i865_get_display_clock_speed(struct drm_device *dev)
2162 {
2163         return 266000;
2164 }
2165
2166 static int i855_get_display_clock_speed(struct drm_device *dev)
2167 {
2168         u16 hpllcc = 0;
2169         /* Assume that the hardware is in the high speed state.  This
2170          * should be the default.
2171          */
2172         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2173         case GC_CLOCK_133_200:
2174         case GC_CLOCK_100_200:
2175                 return 200000;
2176         case GC_CLOCK_166_250:
2177                 return 250000;
2178         case GC_CLOCK_100_133:
2179                 return 133000;
2180         }
2181
2182         /* Shouldn't happen */
2183         return 0;
2184 }
2185
2186 static int i830_get_display_clock_speed(struct drm_device *dev)
2187 {
2188         return 133000;
2189 }
2190
2191 /**
2192  * Return the pipe currently connected to the panel fitter,
2193  * or -1 if the panel fitter is not present or not in use
2194  */
2195 int intel_panel_fitter_pipe (struct drm_device *dev)
2196 {
2197         struct drm_i915_private *dev_priv = dev->dev_private;
2198         u32  pfit_control;
2199
2200         /* i830 doesn't have a panel fitter */
2201         if (IS_I830(dev))
2202                 return -1;
2203
2204         pfit_control = I915_READ(PFIT_CONTROL);
2205
2206         /* See if the panel fitter is in use */
2207         if ((pfit_control & PFIT_ENABLE) == 0)
2208                 return -1;
2209
2210         /* 965 can place panel fitter on either pipe */
2211         if (IS_I965G(dev))
2212                 return (pfit_control >> 29) & 0x3;
2213
2214         /* older chips can only use pipe 1 */
2215         return 1;
2216 }
2217
2218 struct fdi_m_n {
2219         u32        tu;
2220         u32        gmch_m;
2221         u32        gmch_n;
2222         u32        link_m;
2223         u32        link_n;
2224 };
2225
2226 static void
2227 fdi_reduce_ratio(u32 *num, u32 *den)
2228 {
2229         while (*num > 0xffffff || *den > 0xffffff) {
2230                 *num >>= 1;
2231                 *den >>= 1;
2232         }
2233 }
2234
2235 #define DATA_N 0x800000
2236 #define LINK_N 0x80000
2237
2238 static void
2239 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2240                      int link_clock, struct fdi_m_n *m_n)
2241 {
2242         u64 temp;
2243
2244         m_n->tu = 64; /* default size */
2245
2246         temp = (u64) DATA_N * pixel_clock;
2247         temp = div_u64(temp, link_clock);
2248         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2249         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2250         m_n->gmch_n = DATA_N;
2251         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2252
2253         temp = (u64) LINK_N * pixel_clock;
2254         m_n->link_m = div_u64(temp, link_clock);
2255         m_n->link_n = LINK_N;
2256         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2257 }
2258
2259
2260 struct intel_watermark_params {
2261         unsigned long fifo_size;
2262         unsigned long max_wm;
2263         unsigned long default_wm;
2264         unsigned long guard_size;
2265         unsigned long cacheline_size;
2266 };
2267
2268 /* Pineview has different values for various configs */
2269 static struct intel_watermark_params pineview_display_wm = {
2270         PINEVIEW_DISPLAY_FIFO,
2271         PINEVIEW_MAX_WM,
2272         PINEVIEW_DFT_WM,
2273         PINEVIEW_GUARD_WM,
2274         PINEVIEW_FIFO_LINE_SIZE
2275 };
2276 static struct intel_watermark_params pineview_display_hplloff_wm = {
2277         PINEVIEW_DISPLAY_FIFO,
2278         PINEVIEW_MAX_WM,
2279         PINEVIEW_DFT_HPLLOFF_WM,
2280         PINEVIEW_GUARD_WM,
2281         PINEVIEW_FIFO_LINE_SIZE
2282 };
2283 static struct intel_watermark_params pineview_cursor_wm = {
2284         PINEVIEW_CURSOR_FIFO,
2285         PINEVIEW_CURSOR_MAX_WM,
2286         PINEVIEW_CURSOR_DFT_WM,
2287         PINEVIEW_CURSOR_GUARD_WM,
2288         PINEVIEW_FIFO_LINE_SIZE,
2289 };
2290 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2291         PINEVIEW_CURSOR_FIFO,
2292         PINEVIEW_CURSOR_MAX_WM,
2293         PINEVIEW_CURSOR_DFT_WM,
2294         PINEVIEW_CURSOR_GUARD_WM,
2295         PINEVIEW_FIFO_LINE_SIZE
2296 };
2297 static struct intel_watermark_params g4x_wm_info = {
2298         G4X_FIFO_SIZE,
2299         G4X_MAX_WM,
2300         G4X_MAX_WM,
2301         2,
2302         G4X_FIFO_LINE_SIZE,
2303 };
2304 static struct intel_watermark_params i945_wm_info = {
2305         I945_FIFO_SIZE,
2306         I915_MAX_WM,
2307         1,
2308         2,
2309         I915_FIFO_LINE_SIZE
2310 };
2311 static struct intel_watermark_params i915_wm_info = {
2312         I915_FIFO_SIZE,
2313         I915_MAX_WM,
2314         1,
2315         2,
2316         I915_FIFO_LINE_SIZE
2317 };
2318 static struct intel_watermark_params i855_wm_info = {
2319         I855GM_FIFO_SIZE,
2320         I915_MAX_WM,
2321         1,
2322         2,
2323         I830_FIFO_LINE_SIZE
2324 };
2325 static struct intel_watermark_params i830_wm_info = {
2326         I830_FIFO_SIZE,
2327         I915_MAX_WM,
2328         1,
2329         2,
2330         I830_FIFO_LINE_SIZE
2331 };
2332
2333 /**
2334  * intel_calculate_wm - calculate watermark level
2335  * @clock_in_khz: pixel clock
2336  * @wm: chip FIFO params
2337  * @pixel_size: display pixel size
2338  * @latency_ns: memory latency for the platform
2339  *
2340  * Calculate the watermark level (the level at which the display plane will
2341  * start fetching from memory again).  Each chip has a different display
2342  * FIFO size and allocation, so the caller needs to figure that out and pass
2343  * in the correct intel_watermark_params structure.
2344  *
2345  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2346  * on the pixel size.  When it reaches the watermark level, it'll start
2347  * fetching FIFO line sized based chunks from memory until the FIFO fills
2348  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2349  * will occur, and a display engine hang could result.
2350  */
2351 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2352                                         struct intel_watermark_params *wm,
2353                                         int pixel_size,
2354                                         unsigned long latency_ns)
2355 {
2356         long entries_required, wm_size;
2357
2358         /*
2359          * Note: we need to make sure we don't overflow for various clock &
2360          * latency values.
2361          * clocks go from a few thousand to several hundred thousand.
2362          * latency is usually a few thousand
2363          */
2364         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2365                 1000;
2366         entries_required /= wm->cacheline_size;
2367
2368         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2369
2370         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2371
2372         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2373
2374         /* Don't promote wm_size to unsigned... */
2375         if (wm_size > (long)wm->max_wm)
2376                 wm_size = wm->max_wm;
2377         if (wm_size <= 0)
2378                 wm_size = wm->default_wm;
2379         return wm_size;
2380 }
2381
2382 struct cxsr_latency {
2383         int is_desktop;
2384         unsigned long fsb_freq;
2385         unsigned long mem_freq;
2386         unsigned long display_sr;
2387         unsigned long display_hpll_disable;
2388         unsigned long cursor_sr;
2389         unsigned long cursor_hpll_disable;
2390 };
2391
2392 static struct cxsr_latency cxsr_latency_table[] = {
2393         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2394         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2395         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2396
2397         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2398         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2399         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2400
2401         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2402         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2403         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2404
2405         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2406         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2407         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2408
2409         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2410         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2411         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2412
2413         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2414         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2415         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2416 };
2417
2418 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2419                                                    int mem)
2420 {
2421         int i;
2422         struct cxsr_latency *latency;
2423
2424         if (fsb == 0 || mem == 0)
2425                 return NULL;
2426
2427         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2428                 latency = &cxsr_latency_table[i];
2429                 if (is_desktop == latency->is_desktop &&
2430                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2431                         return latency;
2432         }
2433
2434         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2435
2436         return NULL;
2437 }
2438
2439 static void pineview_disable_cxsr(struct drm_device *dev)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         u32 reg;
2443
2444         /* deactivate cxsr */
2445         reg = I915_READ(DSPFW3);
2446         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2447         I915_WRITE(DSPFW3, reg);
2448         DRM_INFO("Big FIFO is disabled\n");
2449 }
2450
2451 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2452                                  int pixel_size)
2453 {
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         u32 reg;
2456         unsigned long wm;
2457         struct cxsr_latency *latency;
2458
2459         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2460                 dev_priv->mem_freq);
2461         if (!latency) {
2462                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2463                 pineview_disable_cxsr(dev);
2464                 return;
2465         }
2466
2467         /* Display SR */
2468         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2469                                 latency->display_sr);
2470         reg = I915_READ(DSPFW1);
2471         reg &= 0x7fffff;
2472         reg |= wm << 23;
2473         I915_WRITE(DSPFW1, reg);
2474         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2475
2476         /* cursor SR */
2477         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2478                                 latency->cursor_sr);
2479         reg = I915_READ(DSPFW3);
2480         reg &= ~(0x3f << 24);
2481         reg |= (wm & 0x3f) << 24;
2482         I915_WRITE(DSPFW3, reg);
2483
2484         /* Display HPLL off SR */
2485         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2486                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2487         reg = I915_READ(DSPFW3);
2488         reg &= 0xfffffe00;
2489         reg |= wm & 0x1ff;
2490         I915_WRITE(DSPFW3, reg);
2491
2492         /* cursor HPLL off SR */
2493         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2494                                 latency->cursor_hpll_disable);
2495         reg = I915_READ(DSPFW3);
2496         reg &= ~(0x3f << 16);
2497         reg |= (wm & 0x3f) << 16;
2498         I915_WRITE(DSPFW3, reg);
2499         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2500
2501         /* activate cxsr */
2502         reg = I915_READ(DSPFW3);
2503         reg |= PINEVIEW_SELF_REFRESH_EN;
2504         I915_WRITE(DSPFW3, reg);
2505
2506         DRM_INFO("Big FIFO is enabled\n");
2507
2508         return;
2509 }
2510
2511 /*
2512  * Latency for FIFO fetches is dependent on several factors:
2513  *   - memory configuration (speed, channels)
2514  *   - chipset
2515  *   - current MCH state
2516  * It can be fairly high in some situations, so here we assume a fairly
2517  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2518  * set this value too high, the FIFO will fetch frequently to stay full)
2519  * and power consumption (set it too low to save power and we might see
2520  * FIFO underruns and display "flicker").
2521  *
2522  * A value of 5us seems to be a good balance; safe for very low end
2523  * platforms but not overly aggressive on lower latency configs.
2524  */
2525 static const int latency_ns = 5000;
2526
2527 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         uint32_t dsparb = I915_READ(DSPARB);
2531         int size;
2532
2533         if (plane == 0)
2534                 size = dsparb & 0x7f;
2535         else
2536                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2537                         (dsparb & 0x7f);
2538
2539         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2540                         plane ? "B" : "A", size);
2541
2542         return size;
2543 }
2544
2545 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2546 {
2547         struct drm_i915_private *dev_priv = dev->dev_private;
2548         uint32_t dsparb = I915_READ(DSPARB);
2549         int size;
2550
2551         if (plane == 0)
2552                 size = dsparb & 0x1ff;
2553         else
2554                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2555                         (dsparb & 0x1ff);
2556         size >>= 1; /* Convert to cachelines */
2557
2558         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2559                         plane ? "B" : "A", size);
2560
2561         return size;
2562 }
2563
2564 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         uint32_t dsparb = I915_READ(DSPARB);
2568         int size;
2569
2570         size = dsparb & 0x7f;
2571         size >>= 2; /* Convert to cachelines */
2572
2573         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2574                         plane ? "B" : "A",
2575                   size);
2576
2577         return size;
2578 }
2579
2580 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2581 {
2582         struct drm_i915_private *dev_priv = dev->dev_private;
2583         uint32_t dsparb = I915_READ(DSPARB);
2584         int size;
2585
2586         size = dsparb & 0x7f;
2587         size >>= 1; /* Convert to cachelines */
2588
2589         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2590                         plane ? "B" : "A", size);
2591
2592         return size;
2593 }
2594
2595 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2596                           int planeb_clock, int sr_hdisplay, int pixel_size)
2597 {
2598         struct drm_i915_private *dev_priv = dev->dev_private;
2599         int total_size, cacheline_size;
2600         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2601         struct intel_watermark_params planea_params, planeb_params;
2602         unsigned long line_time_us;
2603         int sr_clock, sr_entries = 0, entries_required;
2604
2605         /* Create copies of the base settings for each pipe */
2606         planea_params = planeb_params = g4x_wm_info;
2607
2608         /* Grab a couple of global values before we overwrite them */
2609         total_size = planea_params.fifo_size;
2610         cacheline_size = planea_params.cacheline_size;
2611
2612         /*
2613          * Note: we need to make sure we don't overflow for various clock &
2614          * latency values.
2615          * clocks go from a few thousand to several hundred thousand.
2616          * latency is usually a few thousand
2617          */
2618         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2619                 1000;
2620         entries_required /= G4X_FIFO_LINE_SIZE;
2621         planea_wm = entries_required + planea_params.guard_size;
2622
2623         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2624                 1000;
2625         entries_required /= G4X_FIFO_LINE_SIZE;
2626         planeb_wm = entries_required + planeb_params.guard_size;
2627
2628         cursora_wm = cursorb_wm = 16;
2629         cursor_sr = 32;
2630
2631         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2632
2633         /* Calc sr entries for one plane configs */
2634         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2635                 /* self-refresh has much higher latency */
2636                 static const int sr_latency_ns = 12000;
2637
2638                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2639                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2640
2641                 /* Use ns/us then divide to preserve precision */
2642                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2643                               pixel_size * sr_hdisplay) / 1000;
2644                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2645                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2646                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2647         } else {
2648                 /* Turn off self refresh if both pipes are enabled */
2649                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2650                                         & ~FW_BLC_SELF_EN);
2651         }
2652
2653         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2654                   planea_wm, planeb_wm, sr_entries);
2655
2656         planea_wm &= 0x3f;
2657         planeb_wm &= 0x3f;
2658
2659         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2660                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2661                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2662         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2663                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2664         /* HPLL off in SR has some issues on G4x... disable it */
2665         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2666                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2667 }
2668
2669 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2670                            int planeb_clock, int sr_hdisplay, int pixel_size)
2671 {
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         unsigned long line_time_us;
2674         int sr_clock, sr_entries, srwm = 1;
2675
2676         /* Calc sr entries for one plane configs */
2677         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2678                 /* self-refresh has much higher latency */
2679                 static const int sr_latency_ns = 12000;
2680
2681                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2682                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2683
2684                 /* Use ns/us then divide to preserve precision */
2685                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2686                               pixel_size * sr_hdisplay) / 1000;
2687                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2688                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2689                 srwm = I945_FIFO_SIZE - sr_entries;
2690                 if (srwm < 0)
2691                         srwm = 1;
2692                 srwm &= 0x3f;
2693                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2694         } else {
2695                 /* Turn off self refresh if both pipes are enabled */
2696                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2697                                         & ~FW_BLC_SELF_EN);
2698         }
2699
2700         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2701                       srwm);
2702
2703         /* 965 has limitations... */
2704         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2705                    (8 << 0));
2706         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2707 }
2708
2709 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2710                            int planeb_clock, int sr_hdisplay, int pixel_size)
2711 {
2712         struct drm_i915_private *dev_priv = dev->dev_private;
2713         uint32_t fwater_lo;
2714         uint32_t fwater_hi;
2715         int total_size, cacheline_size, cwm, srwm = 1;
2716         int planea_wm, planeb_wm;
2717         struct intel_watermark_params planea_params, planeb_params;
2718         unsigned long line_time_us;
2719         int sr_clock, sr_entries = 0;
2720
2721         /* Create copies of the base settings for each pipe */
2722         if (IS_I965GM(dev) || IS_I945GM(dev))
2723                 planea_params = planeb_params = i945_wm_info;
2724         else if (IS_I9XX(dev))
2725                 planea_params = planeb_params = i915_wm_info;
2726         else
2727                 planea_params = planeb_params = i855_wm_info;
2728
2729         /* Grab a couple of global values before we overwrite them */
2730         total_size = planea_params.fifo_size;
2731         cacheline_size = planea_params.cacheline_size;
2732
2733         /* Update per-plane FIFO sizes */
2734         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2735         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2736
2737         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2738                                        pixel_size, latency_ns);
2739         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2740                                        pixel_size, latency_ns);
2741         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2742
2743         /*
2744          * Overlay gets an aggressive default since video jitter is bad.
2745          */
2746         cwm = 2;
2747
2748         /* Calc sr entries for one plane configs */
2749         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2750             (!planea_clock || !planeb_clock)) {
2751                 /* self-refresh has much higher latency */
2752                 static const int sr_latency_ns = 6000;
2753
2754                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2755                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2756
2757                 /* Use ns/us then divide to preserve precision */
2758                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2759                               pixel_size * sr_hdisplay) / 1000;
2760                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2761                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2762                 srwm = total_size - sr_entries;
2763                 if (srwm < 0)
2764                         srwm = 1;
2765
2766                 if (IS_I945G(dev) || IS_I945GM(dev))
2767                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2768                 else if (IS_I915GM(dev)) {
2769                         /* 915M has a smaller SRWM field */
2770                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2771                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2772                 }
2773         } else {
2774                 /* Turn off self refresh if both pipes are enabled */
2775                 if (IS_I945G(dev) || IS_I945GM(dev)) {
2776                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2777                                    & ~FW_BLC_SELF_EN);
2778                 } else if (IS_I915GM(dev)) {
2779                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2780                 }
2781         }
2782
2783         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2784                   planea_wm, planeb_wm, cwm, srwm);
2785
2786         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2787         fwater_hi = (cwm & 0x1f);
2788
2789         /* Set request length to 8 cachelines per fetch */
2790         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2791         fwater_hi = fwater_hi | (1 << 8);
2792
2793         I915_WRITE(FW_BLC, fwater_lo);
2794         I915_WRITE(FW_BLC2, fwater_hi);
2795 }
2796
2797 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2798                            int unused2, int pixel_size)
2799 {
2800         struct drm_i915_private *dev_priv = dev->dev_private;
2801         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2802         int planea_wm;
2803
2804         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2805
2806         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2807                                        pixel_size, latency_ns);
2808         fwater_lo |= (3<<8) | planea_wm;
2809
2810         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2811
2812         I915_WRITE(FW_BLC, fwater_lo);
2813 }
2814
2815 /**
2816  * intel_update_watermarks - update FIFO watermark values based on current modes
2817  *
2818  * Calculate watermark values for the various WM regs based on current mode
2819  * and plane configuration.
2820  *
2821  * There are several cases to deal with here:
2822  *   - normal (i.e. non-self-refresh)
2823  *   - self-refresh (SR) mode
2824  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2825  *   - lines are small relative to FIFO size (buffer can hold more than 2
2826  *     lines), so need to account for TLB latency
2827  *
2828  *   The normal calculation is:
2829  *     watermark = dotclock * bytes per pixel * latency
2830  *   where latency is platform & configuration dependent (we assume pessimal
2831  *   values here).
2832  *
2833  *   The SR calculation is:
2834  *     watermark = (trunc(latency/line time)+1) * surface width *
2835  *       bytes per pixel
2836  *   where
2837  *     line time = htotal / dotclock
2838  *   and latency is assumed to be high, as above.
2839  *
2840  * The final value programmed to the register should always be rounded up,
2841  * and include an extra 2 entries to account for clock crossings.
2842  *
2843  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2844  * to set the non-SR watermarks to 8.
2845   */
2846 static void intel_update_watermarks(struct drm_device *dev)
2847 {
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct drm_crtc *crtc;
2850         struct intel_crtc *intel_crtc;
2851         int sr_hdisplay = 0;
2852         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2853         int enabled = 0, pixel_size = 0;
2854
2855         if (!dev_priv->display.update_wm)
2856                 return;
2857
2858         /* Get the clock config from both planes */
2859         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2860                 intel_crtc = to_intel_crtc(crtc);
2861                 if (crtc->enabled) {
2862                         enabled++;
2863                         if (intel_crtc->plane == 0) {
2864                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2865                                           intel_crtc->pipe, crtc->mode.clock);
2866                                 planea_clock = crtc->mode.clock;
2867                         } else {
2868                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2869                                           intel_crtc->pipe, crtc->mode.clock);
2870                                 planeb_clock = crtc->mode.clock;
2871                         }
2872                         sr_hdisplay = crtc->mode.hdisplay;
2873                         sr_clock = crtc->mode.clock;
2874                         if (crtc->fb)
2875                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2876                         else
2877                                 pixel_size = 4; /* by default */
2878                 }
2879         }
2880
2881         if (enabled <= 0)
2882                 return;
2883
2884         /* Single plane configs can enable self refresh */
2885         if (enabled == 1 && IS_PINEVIEW(dev))
2886                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2887         else if (IS_PINEVIEW(dev))
2888                 pineview_disable_cxsr(dev);
2889
2890         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2891                                     sr_hdisplay, pixel_size);
2892 }
2893
2894 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2895                                struct drm_display_mode *mode,
2896                                struct drm_display_mode *adjusted_mode,
2897                                int x, int y,
2898                                struct drm_framebuffer *old_fb)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         int plane = intel_crtc->plane;
2905         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2906         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2907         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2908         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2909         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2910         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2911         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2912         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2913         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2914         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2915         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2916         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2917         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2918         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2919         int refclk, num_outputs = 0;
2920         intel_clock_t clock, reduced_clock;
2921         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2922         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2923         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2924         bool is_edp = false;
2925         struct drm_mode_config *mode_config = &dev->mode_config;
2926         struct drm_connector *connector;
2927         const intel_limit_t *limit;
2928         int ret;
2929         struct fdi_m_n m_n = {0};
2930         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2931         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2932         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2933         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2934         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2935         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2936         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2937         int lvds_reg = LVDS;
2938         u32 temp;
2939         int sdvo_pixel_multiply;
2940         int target_clock;
2941
2942         drm_vblank_pre_modeset(dev, pipe);
2943
2944         list_for_each_entry(connector, &mode_config->connector_list, head) {
2945                 struct intel_output *intel_output = to_intel_output(connector);
2946
2947                 if (!connector->encoder || connector->encoder->crtc != crtc)
2948                         continue;
2949
2950                 switch (intel_output->type) {
2951                 case INTEL_OUTPUT_LVDS:
2952                         is_lvds = true;
2953                         break;
2954                 case INTEL_OUTPUT_SDVO:
2955                 case INTEL_OUTPUT_HDMI:
2956                         is_sdvo = true;
2957                         if (intel_output->needs_tv_clock)
2958                                 is_tv = true;
2959                         break;
2960                 case INTEL_OUTPUT_DVO:
2961                         is_dvo = true;
2962                         break;
2963                 case INTEL_OUTPUT_TVOUT:
2964                         is_tv = true;
2965                         break;
2966                 case INTEL_OUTPUT_ANALOG:
2967                         is_crt = true;
2968                         break;
2969                 case INTEL_OUTPUT_DISPLAYPORT:
2970                         is_dp = true;
2971                         break;
2972                 case INTEL_OUTPUT_EDP:
2973                         is_edp = true;
2974                         break;
2975                 }
2976
2977                 num_outputs++;
2978         }
2979
2980         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2981                 refclk = dev_priv->lvds_ssc_freq * 1000;
2982                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2983                                         refclk / 1000);
2984         } else if (IS_I9XX(dev)) {
2985                 refclk = 96000;
2986                 if (HAS_PCH_SPLIT(dev))
2987                         refclk = 120000; /* 120Mhz refclk */
2988         } else {
2989                 refclk = 48000;
2990         }
2991
2992
2993         /*
2994          * Returns a set of divisors for the desired target clock with the given
2995          * refclk, or FALSE.  The returned values represent the clock equation:
2996          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2997          */
2998         limit = intel_limit(crtc);
2999         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3000         if (!ok) {
3001                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3002                 drm_vblank_post_modeset(dev, pipe);
3003                 return -EINVAL;
3004         }
3005
3006         if (is_lvds && dev_priv->lvds_downclock_avail) {
3007                 has_reduced_clock = limit->find_pll(limit, crtc,
3008                                                             dev_priv->lvds_downclock,
3009                                                             refclk,
3010                                                             &reduced_clock);
3011                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3012                         /*
3013                          * If the different P is found, it means that we can't
3014                          * switch the display clock by using the FP0/FP1.
3015                          * In such case we will disable the LVDS downclock
3016                          * feature.
3017                          */
3018                         DRM_DEBUG_KMS("Different P is found for "
3019                                                 "LVDS clock/downclock\n");
3020                         has_reduced_clock = 0;
3021                 }
3022         }
3023         /* SDVO TV has fixed PLL values depend on its clock range,
3024            this mirrors vbios setting. */
3025         if (is_sdvo && is_tv) {
3026                 if (adjusted_mode->clock >= 100000
3027                                 && adjusted_mode->clock < 140500) {
3028                         clock.p1 = 2;
3029                         clock.p2 = 10;
3030                         clock.n = 3;
3031                         clock.m1 = 16;
3032                         clock.m2 = 8;
3033                 } else if (adjusted_mode->clock >= 140500
3034                                 && adjusted_mode->clock <= 200000) {
3035                         clock.p1 = 1;
3036                         clock.p2 = 10;
3037                         clock.n = 6;
3038                         clock.m1 = 12;
3039                         clock.m2 = 8;
3040                 }
3041         }
3042
3043         /* FDI link */
3044         if (HAS_PCH_SPLIT(dev)) {
3045                 int lane, link_bw, bpp;
3046                 /* eDP doesn't require FDI link, so just set DP M/N
3047                    according to current link config */
3048                 if (is_edp) {
3049                         struct drm_connector *edp;
3050                         target_clock = mode->clock;
3051                         edp = intel_pipe_get_output(crtc);
3052                         intel_edp_link_config(to_intel_output(edp),
3053                                         &lane, &link_bw);
3054                 } else {
3055                         /* DP over FDI requires target mode clock
3056                            instead of link clock */
3057                         if (is_dp)
3058                                 target_clock = mode->clock;
3059                         else
3060                                 target_clock = adjusted_mode->clock;
3061                         lane = 4;
3062                         link_bw = 270000;
3063                 }
3064
3065                 /* determine panel color depth */
3066                 temp = I915_READ(pipeconf_reg);
3067                 temp &= ~PIPE_BPC_MASK;
3068                 if (is_lvds) {
3069                         int lvds_reg = I915_READ(PCH_LVDS);
3070                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3071                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3072                                 temp |= PIPE_8BPC;
3073                         else
3074                                 temp |= PIPE_6BPC;
3075                 } else if (is_edp) {
3076                         switch (dev_priv->edp_bpp/3) {
3077                         case 8:
3078                                 temp |= PIPE_8BPC;
3079                                 break;
3080                         case 10:
3081                                 temp |= PIPE_10BPC;
3082                                 break;
3083                         case 6:
3084                                 temp |= PIPE_6BPC;
3085                                 break;
3086                         case 12:
3087                                 temp |= PIPE_12BPC;
3088                                 break;
3089                         }
3090                 } else
3091                         temp |= PIPE_8BPC;
3092                 I915_WRITE(pipeconf_reg, temp);
3093                 I915_READ(pipeconf_reg);
3094
3095                 switch (temp & PIPE_BPC_MASK) {
3096                 case PIPE_8BPC:
3097                         bpp = 24;
3098                         break;
3099                 case PIPE_10BPC:
3100                         bpp = 30;
3101                         break;
3102                 case PIPE_6BPC:
3103                         bpp = 18;
3104                         break;
3105                 case PIPE_12BPC:
3106                         bpp = 36;
3107                         break;
3108                 default:
3109                         DRM_ERROR("unknown pipe bpc value\n");
3110                         bpp = 24;
3111                 }
3112
3113                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3114         }
3115
3116         /* Ironlake: try to setup display ref clock before DPLL
3117          * enabling. This is only under driver's control after
3118          * PCH B stepping, previous chipset stepping should be
3119          * ignoring this setting.
3120          */
3121         if (HAS_PCH_SPLIT(dev)) {
3122                 temp = I915_READ(PCH_DREF_CONTROL);
3123                 /* Always enable nonspread source */
3124                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3125                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3126                 I915_WRITE(PCH_DREF_CONTROL, temp);
3127                 POSTING_READ(PCH_DREF_CONTROL);
3128
3129                 temp &= ~DREF_SSC_SOURCE_MASK;
3130                 temp |= DREF_SSC_SOURCE_ENABLE;
3131                 I915_WRITE(PCH_DREF_CONTROL, temp);
3132                 POSTING_READ(PCH_DREF_CONTROL);
3133
3134                 udelay(200);
3135
3136                 if (is_edp) {
3137                         if (dev_priv->lvds_use_ssc) {
3138                                 temp |= DREF_SSC1_ENABLE;
3139                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3140                                 POSTING_READ(PCH_DREF_CONTROL);
3141
3142                                 udelay(200);
3143
3144                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3145                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3146                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3147                                 POSTING_READ(PCH_DREF_CONTROL);
3148                         } else {
3149                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3150                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3151                                 POSTING_READ(PCH_DREF_CONTROL);
3152                         }
3153                 }
3154         }
3155
3156         if (IS_PINEVIEW(dev)) {
3157                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3158                 if (has_reduced_clock)
3159                         fp2 = (1 << reduced_clock.n) << 16 |
3160                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3161         } else {
3162                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3163                 if (has_reduced_clock)
3164                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3165                                 reduced_clock.m2;
3166         }
3167
3168         if (!HAS_PCH_SPLIT(dev))
3169                 dpll = DPLL_VGA_MODE_DIS;
3170
3171         if (IS_I9XX(dev)) {
3172                 if (is_lvds)
3173                         dpll |= DPLLB_MODE_LVDS;
3174                 else
3175                         dpll |= DPLLB_MODE_DAC_SERIAL;
3176                 if (is_sdvo) {
3177                         dpll |= DPLL_DVO_HIGH_SPEED;
3178                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3179                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3180                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3181                         else if (HAS_PCH_SPLIT(dev))
3182                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3183                 }
3184                 if (is_dp)
3185                         dpll |= DPLL_DVO_HIGH_SPEED;
3186
3187                 /* compute bitmask from p1 value */
3188                 if (IS_PINEVIEW(dev))
3189                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3190                 else {
3191                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3192                         /* also FPA1 */
3193                         if (HAS_PCH_SPLIT(dev))
3194                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3195                         if (IS_G4X(dev) && has_reduced_clock)
3196                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3197                 }
3198                 switch (clock.p2) {
3199                 case 5:
3200                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3201                         break;
3202                 case 7:
3203                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3204                         break;
3205                 case 10:
3206                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3207                         break;
3208                 case 14:
3209                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3210                         break;
3211                 }
3212                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3213                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3214         } else {
3215                 if (is_lvds) {
3216                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3217                 } else {
3218                         if (clock.p1 == 2)
3219                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3220                         else
3221                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3222                         if (clock.p2 == 4)
3223                                 dpll |= PLL_P2_DIVIDE_BY_4;
3224                 }
3225         }
3226
3227         if (is_sdvo && is_tv)
3228                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3229         else if (is_tv)
3230                 /* XXX: just matching BIOS for now */
3231                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3232                 dpll |= 3;
3233         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3234                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3235         else
3236                 dpll |= PLL_REF_INPUT_DREFCLK;
3237
3238         /* setup pipeconf */
3239         pipeconf = I915_READ(pipeconf_reg);
3240
3241         /* Set up the display plane register */
3242         dspcntr = DISPPLANE_GAMMA_ENABLE;
3243
3244         /* Ironlake's plane is forced to pipe, bit 24 is to
3245            enable color space conversion */
3246         if (!HAS_PCH_SPLIT(dev)) {
3247                 if (pipe == 0)
3248                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3249                 else
3250                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3251         }
3252
3253         if (pipe == 0 && !IS_I965G(dev)) {
3254                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3255                  * core speed.
3256                  *
3257                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3258                  * pipe == 0 check?
3259                  */
3260                 if (mode->clock >
3261                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3262                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3263                 else
3264                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3265         }
3266
3267         dspcntr |= DISPLAY_PLANE_ENABLE;
3268         pipeconf |= PIPEACONF_ENABLE;
3269         dpll |= DPLL_VCO_ENABLE;
3270
3271
3272         /* Disable the panel fitter if it was on our pipe */
3273         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3274                 I915_WRITE(PFIT_CONTROL, 0);
3275
3276         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3277         drm_mode_debug_printmodeline(mode);
3278
3279         /* assign to Ironlake registers */
3280         if (HAS_PCH_SPLIT(dev)) {
3281                 fp_reg = pch_fp_reg;
3282                 dpll_reg = pch_dpll_reg;
3283         }
3284
3285         if (is_edp) {
3286                 ironlake_disable_pll_edp(crtc);
3287         } else if ((dpll & DPLL_VCO_ENABLE)) {
3288                 I915_WRITE(fp_reg, fp);
3289                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3290                 I915_READ(dpll_reg);
3291                 udelay(150);
3292         }
3293
3294         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3295          * This is an exception to the general rule that mode_set doesn't turn
3296          * things on.
3297          */
3298         if (is_lvds) {
3299                 u32 lvds;
3300
3301                 if (HAS_PCH_SPLIT(dev))
3302                         lvds_reg = PCH_LVDS;
3303
3304                 lvds = I915_READ(lvds_reg);
3305                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3306                 /* set the corresponsding LVDS_BORDER bit */
3307                 lvds |= dev_priv->lvds_border_bits;
3308                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3309                  * set the DPLLs for dual-channel mode or not.
3310                  */
3311                 if (clock.p2 == 7)
3312                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3313                 else
3314                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3315
3316                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3317                  * appropriately here, but we need to look more thoroughly into how
3318                  * panels behave in the two modes.
3319                  */
3320                 /* set the dithering flag */
3321                 if (IS_I965G(dev)) {
3322                         if (dev_priv->lvds_dither) {
3323                                 if (HAS_PCH_SPLIT(dev))
3324                                         pipeconf |= PIPE_ENABLE_DITHER;
3325                                 else
3326                                         lvds |= LVDS_ENABLE_DITHER;
3327                         } else {
3328                                 if (HAS_PCH_SPLIT(dev))
3329                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3330                                 else
3331                                         lvds &= ~LVDS_ENABLE_DITHER;
3332                         }
3333                 }
3334                 I915_WRITE(lvds_reg, lvds);
3335                 I915_READ(lvds_reg);
3336         }
3337         if (is_dp)
3338                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3339
3340         if (!is_edp) {
3341                 I915_WRITE(fp_reg, fp);
3342                 I915_WRITE(dpll_reg, dpll);
3343                 I915_READ(dpll_reg);
3344                 /* Wait for the clocks to stabilize. */
3345                 udelay(150);
3346
3347                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3348                         if (is_sdvo) {
3349                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3350                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3351                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3352                         } else
3353                                 I915_WRITE(dpll_md_reg, 0);
3354                 } else {
3355                         /* write it again -- the BIOS does, after all */
3356                         I915_WRITE(dpll_reg, dpll);
3357                 }
3358                 I915_READ(dpll_reg);
3359                 /* Wait for the clocks to stabilize. */
3360                 udelay(150);
3361         }
3362
3363         if (is_lvds && has_reduced_clock && i915_powersave) {
3364                 I915_WRITE(fp_reg + 4, fp2);
3365                 intel_crtc->lowfreq_avail = true;
3366                 if (HAS_PIPE_CXSR(dev)) {
3367                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3368                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3369                 }
3370         } else {
3371                 I915_WRITE(fp_reg + 4, fp);
3372                 intel_crtc->lowfreq_avail = false;
3373                 if (HAS_PIPE_CXSR(dev)) {
3374                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3375                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3376                 }
3377         }
3378
3379         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3380                    ((adjusted_mode->crtc_htotal - 1) << 16));
3381         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3382                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3383         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3384                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3385         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3386                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3387         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3388                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3389         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3390                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3391         /* pipesrc and dspsize control the size that is scaled from, which should
3392          * always be the user's requested size.
3393          */
3394         if (!HAS_PCH_SPLIT(dev)) {
3395                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3396                                 (mode->hdisplay - 1));
3397                 I915_WRITE(dsppos_reg, 0);
3398         }
3399         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3400
3401         if (HAS_PCH_SPLIT(dev)) {
3402                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3403                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3404                 I915_WRITE(link_m1_reg, m_n.link_m);
3405                 I915_WRITE(link_n1_reg, m_n.link_n);
3406
3407                 if (is_edp) {
3408                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3409                 } else {
3410                         /* enable FDI RX PLL too */
3411                         temp = I915_READ(fdi_rx_reg);
3412                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3413                         udelay(200);
3414                 }
3415         }
3416
3417         I915_WRITE(pipeconf_reg, pipeconf);
3418         I915_READ(pipeconf_reg);
3419
3420         intel_wait_for_vblank(dev);
3421
3422         if (IS_IRONLAKE(dev)) {
3423                 /* enable address swizzle for tiling buffer */
3424                 temp = I915_READ(DISP_ARB_CTL);
3425                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3426         }
3427
3428         I915_WRITE(dspcntr_reg, dspcntr);
3429
3430         /* Flush the plane changes */
3431         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3432
3433         if ((IS_I965G(dev) || plane == 0))
3434                 intel_update_fbc(crtc, &crtc->mode);
3435
3436         intel_update_watermarks(dev);
3437
3438         drm_vblank_post_modeset(dev, pipe);
3439
3440         return ret;
3441 }
3442
3443 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3444 void intel_crtc_load_lut(struct drm_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447         struct drm_i915_private *dev_priv = dev->dev_private;
3448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3450         int i;
3451
3452         /* The clocks have to be on to load the palette. */
3453         if (!crtc->enabled)
3454                 return;
3455
3456         /* use legacy palette for Ironlake */
3457         if (HAS_PCH_SPLIT(dev))
3458                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3459                                                    LGC_PALETTE_B;
3460
3461         for (i = 0; i < 256; i++) {
3462                 I915_WRITE(palreg + 4 * i,
3463                            (intel_crtc->lut_r[i] << 16) |
3464                            (intel_crtc->lut_g[i] << 8) |
3465                            intel_crtc->lut_b[i]);
3466         }
3467 }
3468
3469 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3470                                  struct drm_file *file_priv,
3471                                  uint32_t handle,
3472                                  uint32_t width, uint32_t height)
3473 {
3474         struct drm_device *dev = crtc->dev;
3475         struct drm_i915_private *dev_priv = dev->dev_private;
3476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477         struct drm_gem_object *bo;
3478         struct drm_i915_gem_object *obj_priv;
3479         int pipe = intel_crtc->pipe;
3480         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3481         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3482         uint32_t temp = I915_READ(control);
3483         size_t addr;
3484         int ret;
3485
3486         DRM_DEBUG_KMS("\n");
3487
3488         /* if we want to turn off the cursor ignore width and height */
3489         if (!handle) {
3490                 DRM_DEBUG_KMS("cursor off\n");
3491                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3492                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3493                         temp |= CURSOR_MODE_DISABLE;
3494                 } else {
3495                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3496                 }
3497                 addr = 0;
3498                 bo = NULL;
3499                 mutex_lock(&dev->struct_mutex);
3500                 goto finish;
3501         }
3502
3503         /* Currently we only support 64x64 cursors */
3504         if (width != 64 || height != 64) {
3505                 DRM_ERROR("we currently only support 64x64 cursors\n");
3506                 return -EINVAL;
3507         }
3508
3509         bo = drm_gem_object_lookup(dev, file_priv, handle);
3510         if (!bo)
3511                 return -ENOENT;
3512
3513         obj_priv = bo->driver_private;
3514
3515         if (bo->size < width * height * 4) {
3516                 DRM_ERROR("buffer is to small\n");
3517                 ret = -ENOMEM;
3518                 goto fail;
3519         }
3520
3521         /* we only need to pin inside GTT if cursor is non-phy */
3522         mutex_lock(&dev->struct_mutex);
3523         if (!dev_priv->info->cursor_needs_physical) {
3524                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3525                 if (ret) {
3526                         DRM_ERROR("failed to pin cursor bo\n");
3527                         goto fail_locked;
3528                 }
3529                 addr = obj_priv->gtt_offset;
3530         } else {
3531                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3532                 if (ret) {
3533                         DRM_ERROR("failed to attach phys object\n");
3534                         goto fail_locked;
3535                 }
3536                 addr = obj_priv->phys_obj->handle->busaddr;
3537         }
3538
3539         if (!IS_I9XX(dev))
3540                 I915_WRITE(CURSIZE, (height << 12) | width);
3541
3542         /* Hooray for CUR*CNTR differences */
3543         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3544                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3545                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3546                 temp |= (pipe << 28); /* Connect to correct pipe */
3547         } else {
3548                 temp &= ~(CURSOR_FORMAT_MASK);
3549                 temp |= CURSOR_ENABLE;
3550                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3551         }
3552
3553  finish:
3554         I915_WRITE(control, temp);
3555         I915_WRITE(base, addr);
3556
3557         if (intel_crtc->cursor_bo) {
3558                 if (dev_priv->info->cursor_needs_physical) {
3559                         if (intel_crtc->cursor_bo != bo)
3560                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3561                 } else
3562                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3563                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3564         }
3565
3566         mutex_unlock(&dev->struct_mutex);
3567
3568         intel_crtc->cursor_addr = addr;
3569         intel_crtc->cursor_bo = bo;
3570
3571         return 0;
3572 fail_locked:
3573         mutex_unlock(&dev->struct_mutex);
3574 fail:
3575         drm_gem_object_unreference_unlocked(bo);
3576         return ret;
3577 }
3578
3579 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3580 {
3581         struct drm_device *dev = crtc->dev;
3582         struct drm_i915_private *dev_priv = dev->dev_private;
3583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584         struct intel_framebuffer *intel_fb;
3585         int pipe = intel_crtc->pipe;
3586         uint32_t temp = 0;
3587         uint32_t adder;
3588
3589         if (crtc->fb) {
3590                 intel_fb = to_intel_framebuffer(crtc->fb);
3591                 intel_mark_busy(dev, intel_fb->obj);
3592         }
3593
3594         if (x < 0) {
3595                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3596                 x = -x;
3597         }
3598         if (y < 0) {
3599                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3600                 y = -y;
3601         }
3602
3603         temp |= x << CURSOR_X_SHIFT;
3604         temp |= y << CURSOR_Y_SHIFT;
3605
3606         adder = intel_crtc->cursor_addr;
3607         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3608         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3609
3610         return 0;
3611 }
3612
3613 /** Sets the color ramps on behalf of RandR */
3614 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3615                                  u16 blue, int regno)
3616 {
3617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618
3619         intel_crtc->lut_r[regno] = red >> 8;
3620         intel_crtc->lut_g[regno] = green >> 8;
3621         intel_crtc->lut_b[regno] = blue >> 8;
3622 }
3623
3624 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3625                              u16 *blue, int regno)
3626 {
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628
3629         *red = intel_crtc->lut_r[regno] << 8;
3630         *green = intel_crtc->lut_g[regno] << 8;
3631         *blue = intel_crtc->lut_b[regno] << 8;
3632 }
3633
3634 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3635                                  u16 *blue, uint32_t size)
3636 {
3637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638         int i;
3639
3640         if (size != 256)
3641                 return;
3642
3643         for (i = 0; i < 256; i++) {
3644                 intel_crtc->lut_r[i] = red[i] >> 8;
3645                 intel_crtc->lut_g[i] = green[i] >> 8;
3646                 intel_crtc->lut_b[i] = blue[i] >> 8;
3647         }
3648
3649         intel_crtc_load_lut(crtc);
3650 }
3651
3652 /**
3653  * Get a pipe with a simple mode set on it for doing load-based monitor
3654  * detection.
3655  *
3656  * It will be up to the load-detect code to adjust the pipe as appropriate for
3657  * its requirements.  The pipe will be connected to no other outputs.
3658  *
3659  * Currently this code will only succeed if there is a pipe with no outputs
3660  * configured for it.  In the future, it could choose to temporarily disable
3661  * some outputs to free up a pipe for its use.
3662  *
3663  * \return crtc, or NULL if no pipes are available.
3664  */
3665
3666 /* VESA 640x480x72Hz mode to set on the pipe */
3667 static struct drm_display_mode load_detect_mode = {
3668         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3669                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3670 };
3671
3672 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3673                                             struct drm_display_mode *mode,
3674                                             int *dpms_mode)
3675 {
3676         struct intel_crtc *intel_crtc;
3677         struct drm_crtc *possible_crtc;
3678         struct drm_crtc *supported_crtc =NULL;
3679         struct drm_encoder *encoder = &intel_output->enc;
3680         struct drm_crtc *crtc = NULL;
3681         struct drm_device *dev = encoder->dev;
3682         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3683         struct drm_crtc_helper_funcs *crtc_funcs;
3684         int i = -1;
3685
3686         /*
3687          * Algorithm gets a little messy:
3688          *   - if the connector already has an assigned crtc, use it (but make
3689          *     sure it's on first)
3690          *   - try to find the first unused crtc that can drive this connector,
3691          *     and use that if we find one
3692          *   - if there are no unused crtcs available, try to use the first
3693          *     one we found that supports the connector
3694          */
3695
3696         /* See if we already have a CRTC for this connector */
3697         if (encoder->crtc) {
3698                 crtc = encoder->crtc;
3699                 /* Make sure the crtc and connector are running */
3700                 intel_crtc = to_intel_crtc(crtc);
3701                 *dpms_mode = intel_crtc->dpms_mode;
3702                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3703                         crtc_funcs = crtc->helper_private;
3704                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3705                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3706                 }
3707                 return crtc;
3708         }
3709
3710         /* Find an unused one (if possible) */
3711         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3712                 i++;
3713                 if (!(encoder->possible_crtcs & (1 << i)))
3714                         continue;
3715                 if (!possible_crtc->enabled) {
3716                         crtc = possible_crtc;
3717                         break;
3718                 }
3719                 if (!supported_crtc)
3720                         supported_crtc = possible_crtc;
3721         }
3722
3723         /*
3724          * If we didn't find an unused CRTC, don't use any.
3725          */
3726         if (!crtc) {
3727                 return NULL;
3728         }
3729
3730         encoder->crtc = crtc;
3731         intel_output->base.encoder = encoder;
3732         intel_output->load_detect_temp = true;
3733
3734         intel_crtc = to_intel_crtc(crtc);
3735         *dpms_mode = intel_crtc->dpms_mode;
3736
3737         if (!crtc->enabled) {
3738                 if (!mode)
3739                         mode = &load_detect_mode;
3740                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3741         } else {
3742                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3743                         crtc_funcs = crtc->helper_private;
3744                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3745                 }
3746
3747                 /* Add this connector to the crtc */
3748                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3749                 encoder_funcs->commit(encoder);
3750         }
3751         /* let the connector get through one full cycle before testing */
3752         intel_wait_for_vblank(dev);
3753
3754         return crtc;
3755 }
3756
3757 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3758 {
3759         struct drm_encoder *encoder = &intel_output->enc;
3760         struct drm_device *dev = encoder->dev;
3761         struct drm_crtc *crtc = encoder->crtc;
3762         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3763         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3764
3765         if (intel_output->load_detect_temp) {
3766                 encoder->crtc = NULL;
3767                 intel_output->base.encoder = NULL;
3768                 intel_output->load_detect_temp = false;
3769                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3770                 drm_helper_disable_unused_functions(dev);
3771         }
3772
3773         /* Switch crtc and output back off if necessary */
3774         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3775                 if (encoder->crtc == crtc)
3776                         encoder_funcs->dpms(encoder, dpms_mode);
3777                 crtc_funcs->dpms(crtc, dpms_mode);
3778         }
3779 }
3780
3781 /* Returns the clock of the currently programmed mode of the given pipe. */
3782 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3783 {
3784         struct drm_i915_private *dev_priv = dev->dev_private;
3785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3786         int pipe = intel_crtc->pipe;
3787         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3788         u32 fp;
3789         intel_clock_t clock;
3790
3791         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3792                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3793         else
3794                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3795
3796         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3797         if (IS_PINEVIEW(dev)) {
3798                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3799                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3800         } else {
3801                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3802                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3803         }
3804
3805         if (IS_I9XX(dev)) {
3806                 if (IS_PINEVIEW(dev))
3807                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3808                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3809                 else
3810                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3811                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3812
3813                 switch (dpll & DPLL_MODE_MASK) {
3814                 case DPLLB_MODE_DAC_SERIAL:
3815                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3816                                 5 : 10;
3817                         break;
3818                 case DPLLB_MODE_LVDS:
3819                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3820                                 7 : 14;
3821                         break;
3822                 default:
3823                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3824                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3825                         return 0;
3826                 }
3827
3828                 /* XXX: Handle the 100Mhz refclk */
3829                 intel_clock(dev, 96000, &clock);
3830         } else {
3831                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3832
3833                 if (is_lvds) {
3834                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3835                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3836                         clock.p2 = 14;
3837
3838                         if ((dpll & PLL_REF_INPUT_MASK) ==
3839                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3840                                 /* XXX: might not be 66MHz */
3841                                 intel_clock(dev, 66000, &clock);
3842                         } else
3843                                 intel_clock(dev, 48000, &clock);
3844                 } else {
3845                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3846                                 clock.p1 = 2;
3847                         else {
3848                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3849                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3850                         }
3851                         if (dpll & PLL_P2_DIVIDE_BY_4)
3852                                 clock.p2 = 4;
3853                         else
3854                                 clock.p2 = 2;
3855
3856                         intel_clock(dev, 48000, &clock);
3857                 }
3858         }
3859
3860         /* XXX: It would be nice to validate the clocks, but we can't reuse
3861          * i830PllIsValid() because it relies on the xf86_config connector
3862          * configuration being accurate, which it isn't necessarily.
3863          */
3864
3865         return clock.dot;
3866 }
3867
3868 /** Returns the currently programmed mode of the given pipe. */
3869 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3870                                              struct drm_crtc *crtc)
3871 {
3872         struct drm_i915_private *dev_priv = dev->dev_private;
3873         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3874         int pipe = intel_crtc->pipe;
3875         struct drm_display_mode *mode;
3876         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3877         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3878         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3879         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3880
3881         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3882         if (!mode)
3883                 return NULL;
3884
3885         mode->clock = intel_crtc_clock_get(dev, crtc);
3886         mode->hdisplay = (htot & 0xffff) + 1;
3887         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3888         mode->hsync_start = (hsync & 0xffff) + 1;
3889         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3890         mode->vdisplay = (vtot & 0xffff) + 1;
3891         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3892         mode->vsync_start = (vsync & 0xffff) + 1;
3893         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3894
3895         drm_mode_set_name(mode);
3896         drm_mode_set_crtcinfo(mode, 0);
3897
3898         return mode;
3899 }
3900
3901 #define GPU_IDLE_TIMEOUT 500 /* ms */
3902
3903 /* When this timer fires, we've been idle for awhile */
3904 static void intel_gpu_idle_timer(unsigned long arg)
3905 {
3906         struct drm_device *dev = (struct drm_device *)arg;
3907         drm_i915_private_t *dev_priv = dev->dev_private;
3908
3909         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3910
3911         dev_priv->busy = false;
3912
3913         queue_work(dev_priv->wq, &dev_priv->idle_work);
3914 }
3915
3916 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3917
3918 static void intel_crtc_idle_timer(unsigned long arg)
3919 {
3920         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3921         struct drm_crtc *crtc = &intel_crtc->base;
3922         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3923
3924         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3925
3926         intel_crtc->busy = false;
3927
3928         queue_work(dev_priv->wq, &dev_priv->idle_work);
3929 }
3930
3931 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3932 {
3933         struct drm_device *dev = crtc->dev;
3934         drm_i915_private_t *dev_priv = dev->dev_private;
3935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3936         int pipe = intel_crtc->pipe;
3937         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3938         int dpll = I915_READ(dpll_reg);
3939
3940         if (HAS_PCH_SPLIT(dev))
3941                 return;
3942
3943         if (!dev_priv->lvds_downclock_avail)
3944                 return;
3945
3946         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3947                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3948
3949                 /* Unlock panel regs */
3950                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3951
3952                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3953                 I915_WRITE(dpll_reg, dpll);
3954                 dpll = I915_READ(dpll_reg);
3955                 intel_wait_for_vblank(dev);
3956                 dpll = I915_READ(dpll_reg);
3957                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3958                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3959
3960                 /* ...and lock them again */
3961                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3962         }
3963
3964         /* Schedule downclock */
3965         if (schedule)
3966                 mod_timer(&intel_crtc->idle_timer, jiffies +
3967                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3968 }
3969
3970 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3971 {
3972         struct drm_device *dev = crtc->dev;
3973         drm_i915_private_t *dev_priv = dev->dev_private;
3974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975         int pipe = intel_crtc->pipe;
3976         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3977         int dpll = I915_READ(dpll_reg);
3978
3979         if (HAS_PCH_SPLIT(dev))
3980                 return;
3981
3982         if (!dev_priv->lvds_downclock_avail)
3983                 return;
3984
3985         /*
3986          * Since this is called by a timer, we should never get here in
3987          * the manual case.
3988          */
3989         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3990                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3991
3992                 /* Unlock panel regs */
3993                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3994
3995                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3996                 I915_WRITE(dpll_reg, dpll);
3997                 dpll = I915_READ(dpll_reg);
3998                 intel_wait_for_vblank(dev);
3999                 dpll = I915_READ(dpll_reg);
4000                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4001                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4002
4003                 /* ...and lock them again */
4004                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4005         }
4006
4007 }
4008
4009 /**
4010  * intel_idle_update - adjust clocks for idleness
4011  * @work: work struct
4012  *
4013  * Either the GPU or display (or both) went idle.  Check the busy status
4014  * here and adjust the CRTC and GPU clocks as necessary.
4015  */
4016 static void intel_idle_update(struct work_struct *work)
4017 {
4018         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4019                                                     idle_work);
4020         struct drm_device *dev = dev_priv->dev;
4021         struct drm_crtc *crtc;
4022         struct intel_crtc *intel_crtc;
4023
4024         if (!i915_powersave)
4025                 return;
4026
4027         mutex_lock(&dev->struct_mutex);
4028
4029         if (IS_I945G(dev) || IS_I945GM(dev)) {
4030                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4031                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4032         }
4033
4034         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4035                 /* Skip inactive CRTCs */
4036                 if (!crtc->fb)
4037                         continue;
4038
4039                 intel_crtc = to_intel_crtc(crtc);
4040                 if (!intel_crtc->busy)
4041                         intel_decrease_pllclock(crtc);
4042         }
4043
4044         mutex_unlock(&dev->struct_mutex);
4045 }
4046
4047 /**
4048  * intel_mark_busy - mark the GPU and possibly the display busy
4049  * @dev: drm device
4050  * @obj: object we're operating on
4051  *
4052  * Callers can use this function to indicate that the GPU is busy processing
4053  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4054  * buffer), we'll also mark the display as busy, so we know to increase its
4055  * clock frequency.
4056  */
4057 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4058 {
4059         drm_i915_private_t *dev_priv = dev->dev_private;
4060         struct drm_crtc *crtc = NULL;
4061         struct intel_framebuffer *intel_fb;
4062         struct intel_crtc *intel_crtc;
4063
4064         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4065                 return;
4066
4067         if (!dev_priv->busy) {
4068                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4069                         u32 fw_blc_self;
4070
4071                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4072                         fw_blc_self = I915_READ(FW_BLC_SELF);
4073                         fw_blc_self &= ~FW_BLC_SELF_EN;
4074                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4075                 }
4076                 dev_priv->busy = true;
4077         } else
4078                 mod_timer(&dev_priv->idle_timer, jiffies +
4079                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4080
4081         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4082                 if (!crtc->fb)
4083                         continue;
4084
4085                 intel_crtc = to_intel_crtc(crtc);
4086                 intel_fb = to_intel_framebuffer(crtc->fb);
4087                 if (intel_fb->obj == obj) {
4088                         if (!intel_crtc->busy) {
4089                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4090                                         u32 fw_blc_self;
4091
4092                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4093                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4094                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4095                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4096                                 }
4097                                 /* Non-busy -> busy, upclock */
4098                                 intel_increase_pllclock(crtc, true);
4099                                 intel_crtc->busy = true;
4100                         } else {
4101                                 /* Busy -> busy, put off timer */
4102                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4103                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4104                         }
4105                 }
4106         }
4107 }
4108
4109 static void intel_crtc_destroy(struct drm_crtc *crtc)
4110 {
4111         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4112
4113         drm_crtc_cleanup(crtc);
4114         kfree(intel_crtc);
4115 }
4116
4117 struct intel_unpin_work {
4118         struct work_struct work;
4119         struct drm_device *dev;
4120         struct drm_gem_object *old_fb_obj;
4121         struct drm_gem_object *pending_flip_obj;
4122         struct drm_pending_vblank_event *event;
4123         int pending;
4124 };
4125
4126 static void intel_unpin_work_fn(struct work_struct *__work)
4127 {
4128         struct intel_unpin_work *work =
4129                 container_of(__work, struct intel_unpin_work, work);
4130
4131         mutex_lock(&work->dev->struct_mutex);
4132         i915_gem_object_unpin(work->old_fb_obj);
4133         drm_gem_object_unreference(work->pending_flip_obj);
4134         drm_gem_object_unreference(work->old_fb_obj);
4135         mutex_unlock(&work->dev->struct_mutex);
4136         kfree(work);
4137 }
4138
4139 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4140 {
4141         drm_i915_private_t *dev_priv = dev->dev_private;
4142         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144         struct intel_unpin_work *work;
4145         struct drm_i915_gem_object *obj_priv;
4146         struct drm_pending_vblank_event *e;
4147         struct timeval now;
4148         unsigned long flags;
4149
4150         /* Ignore early vblank irqs */
4151         if (intel_crtc == NULL)
4152                 return;
4153
4154         spin_lock_irqsave(&dev->event_lock, flags);
4155         work = intel_crtc->unpin_work;
4156         if (work == NULL || !work->pending) {
4157                 if (work && !work->pending) {
4158                         obj_priv = work->pending_flip_obj->driver_private;
4159                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4160                                          obj_priv,
4161                                          atomic_read(&obj_priv->pending_flip));
4162                 }
4163                 spin_unlock_irqrestore(&dev->event_lock, flags);
4164                 return;
4165         }
4166
4167         intel_crtc->unpin_work = NULL;
4168         drm_vblank_put(dev, intel_crtc->pipe);
4169
4170         if (work->event) {
4171                 e = work->event;
4172                 do_gettimeofday(&now);
4173                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4174                 e->event.tv_sec = now.tv_sec;
4175                 e->event.tv_usec = now.tv_usec;
4176                 list_add_tail(&e->base.link,
4177                               &e->base.file_priv->event_list);
4178                 wake_up_interruptible(&e->base.file_priv->event_wait);
4179         }
4180
4181         spin_unlock_irqrestore(&dev->event_lock, flags);
4182
4183         obj_priv = work->pending_flip_obj->driver_private;
4184
4185         /* Initial scanout buffer will have a 0 pending flip count */
4186         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4187             atomic_dec_and_test(&obj_priv->pending_flip))
4188                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4189         schedule_work(&work->work);
4190 }
4191
4192 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4193 {
4194         drm_i915_private_t *dev_priv = dev->dev_private;
4195         struct intel_crtc *intel_crtc =
4196                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4197         unsigned long flags;
4198
4199         spin_lock_irqsave(&dev->event_lock, flags);
4200         if (intel_crtc->unpin_work) {
4201                 intel_crtc->unpin_work->pending = 1;
4202         } else {
4203                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4204         }
4205         spin_unlock_irqrestore(&dev->event_lock, flags);
4206 }
4207
4208 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4209                                 struct drm_framebuffer *fb,
4210                                 struct drm_pending_vblank_event *event)
4211 {
4212         struct drm_device *dev = crtc->dev;
4213         struct drm_i915_private *dev_priv = dev->dev_private;
4214         struct intel_framebuffer *intel_fb;
4215         struct drm_i915_gem_object *obj_priv;
4216         struct drm_gem_object *obj;
4217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4218         struct intel_unpin_work *work;
4219         unsigned long flags;
4220         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4221         int ret, pipesrc;
4222         RING_LOCALS;
4223
4224         work = kzalloc(sizeof *work, GFP_KERNEL);
4225         if (work == NULL)
4226                 return -ENOMEM;
4227
4228         mutex_lock(&dev->struct_mutex);
4229
4230         work->event = event;
4231         work->dev = crtc->dev;
4232         intel_fb = to_intel_framebuffer(crtc->fb);
4233         work->old_fb_obj = intel_fb->obj;
4234         INIT_WORK(&work->work, intel_unpin_work_fn);
4235
4236         /* We borrow the event spin lock for protecting unpin_work */
4237         spin_lock_irqsave(&dev->event_lock, flags);
4238         if (intel_crtc->unpin_work) {
4239                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4240                 spin_unlock_irqrestore(&dev->event_lock, flags);
4241                 kfree(work);
4242                 mutex_unlock(&dev->struct_mutex);
4243                 return -EBUSY;
4244         }
4245         intel_crtc->unpin_work = work;
4246         spin_unlock_irqrestore(&dev->event_lock, flags);
4247
4248         intel_fb = to_intel_framebuffer(fb);
4249         obj = intel_fb->obj;
4250
4251         ret = intel_pin_and_fence_fb_obj(dev, obj);
4252         if (ret != 0) {
4253                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4254                           obj->driver_private);
4255                 kfree(work);
4256                 intel_crtc->unpin_work = NULL;
4257                 mutex_unlock(&dev->struct_mutex);
4258                 return ret;
4259         }
4260
4261         /* Reference the objects for the scheduled work. */
4262         drm_gem_object_reference(work->old_fb_obj);
4263         drm_gem_object_reference(obj);
4264
4265         crtc->fb = fb;
4266         i915_gem_object_flush_write_domain(obj);
4267         drm_vblank_get(dev, intel_crtc->pipe);
4268         obj_priv = obj->driver_private;
4269         atomic_inc(&obj_priv->pending_flip);
4270         work->pending_flip_obj = obj;
4271
4272         BEGIN_LP_RING(4);
4273         OUT_RING(MI_DISPLAY_FLIP |
4274                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4275         OUT_RING(fb->pitch);
4276         if (IS_I965G(dev)) {
4277                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4278                 pipesrc = I915_READ(pipesrc_reg);
4279                 OUT_RING(pipesrc & 0x0fff0fff);
4280         } else {
4281                 OUT_RING(obj_priv->gtt_offset);
4282                 OUT_RING(MI_NOOP);
4283         }
4284         ADVANCE_LP_RING();
4285
4286         mutex_unlock(&dev->struct_mutex);
4287
4288         return 0;
4289 }
4290
4291 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4292         .dpms = intel_crtc_dpms,
4293         .mode_fixup = intel_crtc_mode_fixup,
4294         .mode_set = intel_crtc_mode_set,
4295         .mode_set_base = intel_pipe_set_base,
4296         .prepare = intel_crtc_prepare,
4297         .commit = intel_crtc_commit,
4298         .load_lut = intel_crtc_load_lut,
4299 };
4300
4301 static const struct drm_crtc_funcs intel_crtc_funcs = {
4302         .cursor_set = intel_crtc_cursor_set,
4303         .cursor_move = intel_crtc_cursor_move,
4304         .gamma_set = intel_crtc_gamma_set,
4305         .set_config = drm_crtc_helper_set_config,
4306         .destroy = intel_crtc_destroy,
4307         .page_flip = intel_crtc_page_flip,
4308 };
4309
4310
4311 static void intel_crtc_init(struct drm_device *dev, int pipe)
4312 {
4313         drm_i915_private_t *dev_priv = dev->dev_private;
4314         struct intel_crtc *intel_crtc;
4315         int i;
4316
4317         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4318         if (intel_crtc == NULL)
4319                 return;
4320
4321         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4322
4323         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4324         intel_crtc->pipe = pipe;
4325         intel_crtc->plane = pipe;
4326         for (i = 0; i < 256; i++) {
4327                 intel_crtc->lut_r[i] = i;
4328                 intel_crtc->lut_g[i] = i;
4329                 intel_crtc->lut_b[i] = i;
4330         }
4331
4332         /* Swap pipes & planes for FBC on pre-965 */
4333         intel_crtc->pipe = pipe;
4334         intel_crtc->plane = pipe;
4335         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4336                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4337                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4338         }
4339
4340         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4341                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4342         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4343         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4344
4345         intel_crtc->cursor_addr = 0;
4346         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4347         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4348
4349         intel_crtc->busy = false;
4350
4351         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4352                     (unsigned long)intel_crtc);
4353 }
4354
4355 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4356                                 struct drm_file *file_priv)
4357 {
4358         drm_i915_private_t *dev_priv = dev->dev_private;
4359         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4360         struct drm_mode_object *drmmode_obj;
4361         struct intel_crtc *crtc;
4362
4363         if (!dev_priv) {
4364                 DRM_ERROR("called with no initialization\n");
4365                 return -EINVAL;
4366         }
4367
4368         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4369                         DRM_MODE_OBJECT_CRTC);
4370
4371         if (!drmmode_obj) {
4372                 DRM_ERROR("no such CRTC id\n");
4373                 return -EINVAL;
4374         }
4375
4376         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4377         pipe_from_crtc_id->pipe = crtc->pipe;
4378
4379         return 0;
4380 }
4381
4382 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4383 {
4384         struct drm_crtc *crtc = NULL;
4385
4386         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4387                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4388                 if (intel_crtc->pipe == pipe)
4389                         break;
4390         }
4391         return crtc;
4392 }
4393
4394 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4395 {
4396         int index_mask = 0;
4397         struct drm_connector *connector;
4398         int entry = 0;
4399
4400         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4401                 struct intel_output *intel_output = to_intel_output(connector);
4402                 if (type_mask & intel_output->clone_mask)
4403                         index_mask |= (1 << entry);
4404                 entry++;
4405         }
4406         return index_mask;
4407 }
4408
4409
4410 static void intel_setup_outputs(struct drm_device *dev)
4411 {
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         struct drm_connector *connector;
4414
4415         intel_crt_init(dev);
4416
4417         /* Set up integrated LVDS */
4418         if (IS_MOBILE(dev) && !IS_I830(dev))
4419                 intel_lvds_init(dev);
4420
4421         if (HAS_PCH_SPLIT(dev)) {
4422                 int found;
4423
4424                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4425                         intel_dp_init(dev, DP_A);
4426
4427                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4428                         /* check SDVOB */
4429                         /* found = intel_sdvo_init(dev, HDMIB); */
4430                         found = 0;
4431                         if (!found)
4432                                 intel_hdmi_init(dev, HDMIB);
4433                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4434                                 intel_dp_init(dev, PCH_DP_B);
4435                 }
4436
4437                 if (I915_READ(HDMIC) & PORT_DETECTED)
4438                         intel_hdmi_init(dev, HDMIC);
4439
4440                 if (I915_READ(HDMID) & PORT_DETECTED)
4441                         intel_hdmi_init(dev, HDMID);
4442
4443                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4444                         intel_dp_init(dev, PCH_DP_C);
4445
4446                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4447                         intel_dp_init(dev, PCH_DP_D);
4448
4449         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4450                 bool found = false;
4451
4452                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4453                         DRM_DEBUG_KMS("probing SDVOB\n");
4454                         found = intel_sdvo_init(dev, SDVOB);
4455                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4456                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4457                                 intel_hdmi_init(dev, SDVOB);
4458                         }
4459
4460                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4461                                 DRM_DEBUG_KMS("probing DP_B\n");
4462                                 intel_dp_init(dev, DP_B);
4463                         }
4464                 }
4465
4466                 /* Before G4X SDVOC doesn't have its own detect register */
4467
4468                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4469                         DRM_DEBUG_KMS("probing SDVOC\n");
4470                         found = intel_sdvo_init(dev, SDVOC);
4471                 }
4472
4473                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4474
4475                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4476                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4477                                 intel_hdmi_init(dev, SDVOC);
4478                         }
4479                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4480                                 DRM_DEBUG_KMS("probing DP_C\n");
4481                                 intel_dp_init(dev, DP_C);
4482                         }
4483                 }
4484
4485                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4486                     (I915_READ(DP_D) & DP_DETECTED)) {
4487                         DRM_DEBUG_KMS("probing DP_D\n");
4488                         intel_dp_init(dev, DP_D);
4489                 }
4490         } else if (IS_GEN2(dev))
4491                 intel_dvo_init(dev);
4492
4493         if (SUPPORTS_TV(dev))
4494                 intel_tv_init(dev);
4495
4496         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4497                 struct intel_output *intel_output = to_intel_output(connector);
4498                 struct drm_encoder *encoder = &intel_output->enc;
4499
4500                 encoder->possible_crtcs = intel_output->crtc_mask;
4501                 encoder->possible_clones = intel_connector_clones(dev,
4502                                                 intel_output->clone_mask);
4503         }
4504 }
4505
4506 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4507 {
4508         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4509         struct drm_device *dev = fb->dev;
4510
4511         if (fb->fbdev)
4512                 intelfb_remove(dev, fb);
4513
4514         drm_framebuffer_cleanup(fb);
4515         drm_gem_object_unreference_unlocked(intel_fb->obj);
4516
4517         kfree(intel_fb);
4518 }
4519
4520 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4521                                                 struct drm_file *file_priv,
4522                                                 unsigned int *handle)
4523 {
4524         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4525         struct drm_gem_object *object = intel_fb->obj;
4526
4527         return drm_gem_handle_create(file_priv, object, handle);
4528 }
4529
4530 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4531         .destroy = intel_user_framebuffer_destroy,
4532         .create_handle = intel_user_framebuffer_create_handle,
4533 };
4534
4535 int intel_framebuffer_create(struct drm_device *dev,
4536                              struct drm_mode_fb_cmd *mode_cmd,
4537                              struct drm_framebuffer **fb,
4538                              struct drm_gem_object *obj)
4539 {
4540         struct intel_framebuffer *intel_fb;
4541         int ret;
4542
4543         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4544         if (!intel_fb)
4545                 return -ENOMEM;
4546
4547         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4548         if (ret) {
4549                 DRM_ERROR("framebuffer init failed %d\n", ret);
4550                 return ret;
4551         }
4552
4553         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4554
4555         intel_fb->obj = obj;
4556
4557         *fb = &intel_fb->base;
4558
4559         return 0;
4560 }
4561
4562
4563 static struct drm_framebuffer *
4564 intel_user_framebuffer_create(struct drm_device *dev,
4565                               struct drm_file *filp,
4566                               struct drm_mode_fb_cmd *mode_cmd)
4567 {
4568         struct drm_gem_object *obj;
4569         struct drm_framebuffer *fb;
4570         int ret;
4571
4572         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4573         if (!obj)
4574                 return NULL;
4575
4576         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4577         if (ret) {
4578                 drm_gem_object_unreference_unlocked(obj);
4579                 return NULL;
4580         }
4581
4582         return fb;
4583 }
4584
4585 static const struct drm_mode_config_funcs intel_mode_funcs = {
4586         .fb_create = intel_user_framebuffer_create,
4587         .fb_changed = intelfb_probe,
4588 };
4589
4590 static struct drm_gem_object *
4591 intel_alloc_power_context(struct drm_device *dev)
4592 {
4593         struct drm_gem_object *pwrctx;
4594         int ret;
4595
4596         pwrctx = drm_gem_object_alloc(dev, 4096);
4597         if (!pwrctx) {
4598                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4599                 return NULL;
4600         }
4601
4602         mutex_lock(&dev->struct_mutex);
4603         ret = i915_gem_object_pin(pwrctx, 4096);
4604         if (ret) {
4605                 DRM_ERROR("failed to pin power context: %d\n", ret);
4606                 goto err_unref;
4607         }
4608
4609         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4610         if (ret) {
4611                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4612                 goto err_unpin;
4613         }
4614         mutex_unlock(&dev->struct_mutex);
4615
4616         return pwrctx;
4617
4618 err_unpin:
4619         i915_gem_object_unpin(pwrctx);
4620 err_unref:
4621         drm_gem_object_unreference(pwrctx);
4622         mutex_unlock(&dev->struct_mutex);
4623         return NULL;
4624 }
4625
4626 void ironlake_enable_drps(struct drm_device *dev)
4627 {
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4630         u8 fmax, fmin, fstart, vstart;
4631         int i = 0;
4632
4633         /* 100ms RC evaluation intervals */
4634         I915_WRITE(RCUPEI, 100000);
4635         I915_WRITE(RCDNEI, 100000);
4636
4637         /* Set max/min thresholds to 90ms and 80ms respectively */
4638         I915_WRITE(RCBMAXAVG, 90000);
4639         I915_WRITE(RCBMINAVG, 80000);
4640
4641         I915_WRITE(MEMIHYST, 1);
4642
4643         /* Set up min, max, and cur for interrupt handling */
4644         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4645         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4646         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4647                 MEMMODE_FSTART_SHIFT;
4648         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4649                 PXVFREQ_PX_SHIFT;
4650
4651         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4652         dev_priv->min_delay = fmin;
4653         dev_priv->cur_delay = fstart;
4654
4655         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4656
4657         /*
4658          * Interrupts will be enabled in ironlake_irq_postinstall
4659          */
4660
4661         I915_WRITE(VIDSTART, vstart);
4662         POSTING_READ(VIDSTART);
4663
4664         rgvmodectl |= MEMMODE_SWMODE_EN;
4665         I915_WRITE(MEMMODECTL, rgvmodectl);
4666
4667         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4668                 if (i++ > 100) {
4669                         DRM_ERROR("stuck trying to change perf mode\n");
4670                         break;
4671                 }
4672                 msleep(1);
4673         }
4674         msleep(1);
4675
4676         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4677                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4678         I915_WRITE(MEMSWCTL, rgvswctl);
4679         POSTING_READ(MEMSWCTL);
4680
4681         rgvswctl |= MEMCTL_CMD_STS;
4682         I915_WRITE(MEMSWCTL, rgvswctl);
4683 }
4684
4685 void ironlake_disable_drps(struct drm_device *dev)
4686 {
4687         struct drm_i915_private *dev_priv = dev->dev_private;
4688         u32 rgvswctl;
4689         u8 fstart;
4690
4691         /* Ack interrupts, disable EFC interrupt */
4692         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4693         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4694         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4695         I915_WRITE(DEIIR, DE_PCU_EVENT);
4696         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4697
4698         /* Go back to the starting frequency */
4699         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4700                 MEMMODE_FSTART_SHIFT;
4701         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4702                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4703         I915_WRITE(MEMSWCTL, rgvswctl);
4704         msleep(1);
4705         rgvswctl |= MEMCTL_CMD_STS;
4706         I915_WRITE(MEMSWCTL, rgvswctl);
4707         msleep(1);
4708
4709 }
4710
4711 void intel_init_clock_gating(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714
4715         /*
4716          * Disable clock gating reported to work incorrectly according to the
4717          * specs, but enable as much else as we can.
4718          */
4719         if (HAS_PCH_SPLIT(dev)) {
4720                 return;
4721         } else if (IS_G4X(dev)) {
4722                 uint32_t dspclk_gate;
4723                 I915_WRITE(RENCLK_GATE_D1, 0);
4724                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4725                        GS_UNIT_CLOCK_GATE_DISABLE |
4726                        CL_UNIT_CLOCK_GATE_DISABLE);
4727                 I915_WRITE(RAMCLK_GATE_D, 0);
4728                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4729                         OVRUNIT_CLOCK_GATE_DISABLE |
4730                         OVCUNIT_CLOCK_GATE_DISABLE;
4731                 if (IS_GM45(dev))
4732                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4733                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4734         } else if (IS_I965GM(dev)) {
4735                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4736                 I915_WRITE(RENCLK_GATE_D2, 0);
4737                 I915_WRITE(DSPCLK_GATE_D, 0);
4738                 I915_WRITE(RAMCLK_GATE_D, 0);
4739                 I915_WRITE16(DEUC, 0);
4740         } else if (IS_I965G(dev)) {
4741                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4742                        I965_RCC_CLOCK_GATE_DISABLE |
4743                        I965_RCPB_CLOCK_GATE_DISABLE |
4744                        I965_ISC_CLOCK_GATE_DISABLE |
4745                        I965_FBC_CLOCK_GATE_DISABLE);
4746                 I915_WRITE(RENCLK_GATE_D2, 0);
4747         } else if (IS_I9XX(dev)) {
4748                 u32 dstate = I915_READ(D_STATE);
4749
4750                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4751                         DSTATE_DOT_CLOCK_GATING;
4752                 I915_WRITE(D_STATE, dstate);
4753         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4754                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4755         } else if (IS_I830(dev)) {
4756                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4757         }
4758
4759         /*
4760          * GPU can automatically power down the render unit if given a page
4761          * to save state.
4762          */
4763         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4764                 struct drm_i915_gem_object *obj_priv = NULL;
4765
4766                 if (dev_priv->pwrctx) {
4767                         obj_priv = dev_priv->pwrctx->driver_private;
4768                 } else {
4769                         struct drm_gem_object *pwrctx;
4770
4771                         pwrctx = intel_alloc_power_context(dev);
4772                         if (pwrctx) {
4773                                 dev_priv->pwrctx = pwrctx;
4774                                 obj_priv = pwrctx->driver_private;
4775                         }
4776                 }
4777
4778                 if (obj_priv) {
4779                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4780                         I915_WRITE(MCHBAR_RENDER_STANDBY,
4781                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4782                 }
4783         }
4784 }
4785
4786 /* Set up chip specific display functions */
4787 static void intel_init_display(struct drm_device *dev)
4788 {
4789         struct drm_i915_private *dev_priv = dev->dev_private;
4790
4791         /* We always want a DPMS function */
4792         if (HAS_PCH_SPLIT(dev))
4793                 dev_priv->display.dpms = ironlake_crtc_dpms;
4794         else
4795                 dev_priv->display.dpms = i9xx_crtc_dpms;
4796
4797         /* Only mobile has FBC, leave pointers NULL for other chips */
4798         if (IS_MOBILE(dev)) {
4799                 if (IS_GM45(dev)) {
4800                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4801                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4802                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4803                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4804                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4805                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4806                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4807                 }
4808                 /* 855GM needs testing */
4809         }
4810
4811         /* Returns the core display clock speed */
4812         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4813                 dev_priv->display.get_display_clock_speed =
4814                         i945_get_display_clock_speed;
4815         else if (IS_I915G(dev))
4816                 dev_priv->display.get_display_clock_speed =
4817                         i915_get_display_clock_speed;
4818         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4819                 dev_priv->display.get_display_clock_speed =
4820                         i9xx_misc_get_display_clock_speed;
4821         else if (IS_I915GM(dev))
4822                 dev_priv->display.get_display_clock_speed =
4823                         i915gm_get_display_clock_speed;
4824         else if (IS_I865G(dev))
4825                 dev_priv->display.get_display_clock_speed =
4826                         i865_get_display_clock_speed;
4827         else if (IS_I85X(dev))
4828                 dev_priv->display.get_display_clock_speed =
4829                         i855_get_display_clock_speed;
4830         else /* 852, 830 */
4831                 dev_priv->display.get_display_clock_speed =
4832                         i830_get_display_clock_speed;
4833
4834         /* For FIFO watermark updates */
4835         if (HAS_PCH_SPLIT(dev))
4836                 dev_priv->display.update_wm = NULL;
4837         else if (IS_G4X(dev))
4838                 dev_priv->display.update_wm = g4x_update_wm;
4839         else if (IS_I965G(dev))
4840                 dev_priv->display.update_wm = i965_update_wm;
4841         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4842                 dev_priv->display.update_wm = i9xx_update_wm;
4843                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4844         } else {
4845                 if (IS_I85X(dev))
4846                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4847                 else if (IS_845G(dev))
4848                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4849                 else
4850                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4851                 dev_priv->display.update_wm = i830_update_wm;
4852         }
4853 }
4854
4855 void intel_modeset_init(struct drm_device *dev)
4856 {
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         int num_pipe;
4859         int i;
4860
4861         drm_mode_config_init(dev);
4862
4863         dev->mode_config.min_width = 0;
4864         dev->mode_config.min_height = 0;
4865
4866         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4867
4868         intel_init_display(dev);
4869
4870         if (IS_I965G(dev)) {
4871                 dev->mode_config.max_width = 8192;
4872                 dev->mode_config.max_height = 8192;
4873         } else if (IS_I9XX(dev)) {
4874                 dev->mode_config.max_width = 4096;
4875                 dev->mode_config.max_height = 4096;
4876         } else {
4877                 dev->mode_config.max_width = 2048;
4878                 dev->mode_config.max_height = 2048;
4879         }
4880
4881         /* set memory base */
4882         if (IS_I9XX(dev))
4883                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4884         else
4885                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4886
4887         if (IS_MOBILE(dev) || IS_I9XX(dev))
4888                 num_pipe = 2;
4889         else
4890                 num_pipe = 1;
4891         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4892                   num_pipe, num_pipe > 1 ? "s" : "");
4893
4894         for (i = 0; i < num_pipe; i++) {
4895                 intel_crtc_init(dev, i);
4896         }
4897
4898         intel_setup_outputs(dev);
4899
4900         intel_init_clock_gating(dev);
4901
4902         if (IS_IRONLAKE_M(dev))
4903                 ironlake_enable_drps(dev);
4904
4905         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4906         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4907                     (unsigned long)dev);
4908
4909         intel_setup_overlay(dev);
4910
4911         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4912                                                         dev_priv->fsb_freq,
4913                                                         dev_priv->mem_freq))
4914                 DRM_INFO("failed to find known CxSR latency "
4915                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4916                          dev_priv->fsb_freq, dev_priv->mem_freq);
4917 }
4918
4919 void intel_modeset_cleanup(struct drm_device *dev)
4920 {
4921         struct drm_i915_private *dev_priv = dev->dev_private;
4922         struct drm_crtc *crtc;
4923         struct intel_crtc *intel_crtc;
4924
4925         mutex_lock(&dev->struct_mutex);
4926
4927         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4928                 /* Skip inactive CRTCs */
4929                 if (!crtc->fb)
4930                         continue;
4931
4932                 intel_crtc = to_intel_crtc(crtc);
4933                 intel_increase_pllclock(crtc, false);
4934                 del_timer_sync(&intel_crtc->idle_timer);
4935         }
4936
4937         del_timer_sync(&dev_priv->idle_timer);
4938
4939         if (dev_priv->display.disable_fbc)
4940                 dev_priv->display.disable_fbc(dev);
4941
4942         if (dev_priv->pwrctx) {
4943                 struct drm_i915_gem_object *obj_priv;
4944
4945                 obj_priv = dev_priv->pwrctx->driver_private;
4946                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4947                 I915_READ(PWRCTXA);
4948                 i915_gem_object_unpin(dev_priv->pwrctx);
4949                 drm_gem_object_unreference(dev_priv->pwrctx);
4950         }
4951
4952         if (IS_IRONLAKE_M(dev))
4953                 ironlake_disable_drps(dev);
4954
4955         mutex_unlock(&dev->struct_mutex);
4956
4957         drm_mode_config_cleanup(dev);
4958 }
4959
4960
4961 /* current intel driver doesn't take advantage of encoders
4962    always give back the encoder for the connector
4963 */
4964 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4965 {
4966         struct intel_output *intel_output = to_intel_output(connector);
4967
4968         return &intel_output->enc;
4969 }
4970
4971 /*
4972  * set vga decode state - true == enable VGA decode
4973  */
4974 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4975 {
4976         struct drm_i915_private *dev_priv = dev->dev_private;
4977         u16 gmch_ctrl;
4978
4979         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4980         if (state)
4981                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4982         else
4983                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4984         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4985         return 0;
4986 }