drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/cpufreq.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41
  42 #include "drm_crtc_helper.h"
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_update_watermarks(struct drm_device *dev);
  48 static void intel_increase_pllclock(struct drm_crtc *crtc);
  49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  50
  51 typedef struct {
  52         /* given values */
  53         int n;
  54         int m1, m2;
  55         int p1, p2;
  56         /* derived values */
  57         int     dot;
  58         int     vco;
  59         int     m;
  60         int     p;
  61 } intel_clock_t;
  62
  63 typedef struct {
  64         int     min, max;
  65 } intel_range_t;
  66
  67 typedef struct {
  68         int     dot_limit;
  69         int     p2_slow, p2_fast;
  70 } intel_p2_t;
  71
  72 #define INTEL_P2_NUM                  2
  73 typedef struct intel_limit intel_limit_t;
  74 struct intel_limit {
  75         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  76         intel_p2_t          p2;
  77         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  78                         int, int, intel_clock_t *);
  79 };
  80
  81 /* FDI */
  82 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  83
  84 static bool
  85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86                     int target, int refclk, intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *best_clock);
  90
  91 static bool
  92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  93                       int target, int refclk, intel_clock_t *best_clock);
  94 static bool
  95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  96                            int target, int refclk, intel_clock_t *best_clock);
  97
  98 static inline u32 /* units of 100MHz */
  99 intel_fdi_link_freq(struct drm_device *dev)
 100 {
 101         if (IS_GEN5(dev)) {
 102                 struct drm_i915_private *dev_priv = dev->dev_private;
 103                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 104         } else
 105                 return 27;
 106 }
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 2 },
 119         .find_pll = intel_find_best_PLL,
 120 };
 121
 122 static const intel_limit_t intel_limits_i8xx_lvds = {
 123         .dot = { .min = 25000, .max = 350000 },
 124         .vco = { .min = 930000, .max = 1400000 },
 125         .n = { .min = 3, .max = 16 },
 126         .m = { .min = 96, .max = 140 },
 127         .m1 = { .min = 18, .max = 26 },
 128         .m2 = { .min = 6, .max = 16 },
 129         .p = { .min = 4, .max = 128 },
 130         .p1 = { .min = 1, .max = 6 },
 131         .p2 = { .dot_limit = 165000,
 132                 .p2_slow = 14, .p2_fast = 7 },
 133         .find_pll = intel_find_best_PLL,
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 10, .max = 22 },
 142         .m2 = { .min = 5, .max = 9 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147         .find_pll = intel_find_best_PLL,
 148 };
 149
 150 static const intel_limit_t intel_limits_i9xx_lvds = {
 151         .dot = { .min = 20000, .max = 400000 },
 152         .vco = { .min = 1400000, .max = 2800000 },
 153         .n = { .min = 1, .max = 6 },
 154         .m = { .min = 70, .max = 120 },
 155         .m1 = { .min = 10, .max = 22 },
 156         .m2 = { .min = 5, .max = 9 },
 157         .p = { .min = 7, .max = 98 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 112000,
 160                 .p2_slow = 14, .p2_fast = 7 },
 161         .find_pll = intel_find_best_PLL,
 162 };
 163
 164
 165 static const intel_limit_t intel_limits_g4x_sdvo = {
 166         .dot = { .min = 25000, .max = 270000 },
 167         .vco = { .min = 1750000, .max = 3500000},
 168         .n = { .min = 1, .max = 4 },
 169         .m = { .min = 104, .max = 138 },
 170         .m1 = { .min = 17, .max = 23 },
 171         .m2 = { .min = 5, .max = 11 },
 172         .p = { .min = 10, .max = 30 },
 173         .p1 = { .min = 1, .max = 3},
 174         .p2 = { .dot_limit = 270000,
 175                 .p2_slow = 10,
 176                 .p2_fast = 10
 177         },
 178         .find_pll = intel_g4x_find_best_PLL,
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192         .find_pll = intel_g4x_find_best_PLL,
 193 };
 194
 195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 196         .dot = { .min = 20000, .max = 115000 },
 197         .vco = { .min = 1750000, .max = 3500000 },
 198         .n = { .min = 1, .max = 3 },
 199         .m = { .min = 104, .max = 138 },
 200         .m1 = { .min = 17, .max = 23 },
 201         .m2 = { .min = 5, .max = 11 },
 202         .p = { .min = 28, .max = 112 },
 203         .p1 = { .min = 2, .max = 8 },
 204         .p2 = { .dot_limit = 0,
 205                 .p2_slow = 14, .p2_fast = 14
 206         },
 207         .find_pll = intel_g4x_find_best_PLL,
 208 };
 209
 210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 211         .dot = { .min = 80000, .max = 224000 },
 212         .vco = { .min = 1750000, .max = 3500000 },
 213         .n = { .min = 1, .max = 3 },
 214         .m = { .min = 104, .max = 138 },
 215         .m1 = { .min = 17, .max = 23 },
 216         .m2 = { .min = 5, .max = 11 },
 217         .p = { .min = 14, .max = 42 },
 218         .p1 = { .min = 2, .max = 6 },
 219         .p2 = { .dot_limit = 0,
 220                 .p2_slow = 7, .p2_fast = 7
 221         },
 222         .find_pll = intel_g4x_find_best_PLL,
 223 };
 224
 225 static const intel_limit_t intel_limits_g4x_display_port = {
 226         .dot = { .min = 161670, .max = 227000 },
 227         .vco = { .min = 1750000, .max = 3500000},
 228         .n = { .min = 1, .max = 2 },
 229         .m = { .min = 97, .max = 108 },
 230         .m1 = { .min = 0x10, .max = 0x12 },
 231         .m2 = { .min = 0x05, .max = 0x06 },
 232         .p = { .min = 10, .max = 20 },
 233         .p1 = { .min = 1, .max = 2},
 234         .p2 = { .dot_limit = 0,
 235                 .p2_slow = 10, .p2_fast = 10 },
 236         .find_pll = intel_find_pll_g4x_dp,
 237 };
 238
 239 static const intel_limit_t intel_limits_pineview_sdvo = {
 240         .dot = { .min = 20000, .max = 400000},
 241         .vco = { .min = 1700000, .max = 3500000 },
 242         /* Pineview's Ncounter is a ring counter */
 243         .n = { .min = 3, .max = 6 },
 244         .m = { .min = 2, .max = 256 },
 245         /* Pineview only has one combined m divider, which we treat as m2. */
 246         .m1 = { .min = 0, .max = 0 },
 247         .m2 = { .min = 0, .max = 254 },
 248         .p = { .min = 5, .max = 80 },
 249         .p1 = { .min = 1, .max = 8 },
 250         .p2 = { .dot_limit = 200000,
 251                 .p2_slow = 10, .p2_fast = 5 },
 252         .find_pll = intel_find_best_PLL,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         .n = { .min = 3, .max = 6 },
 259         .m = { .min = 2, .max = 256 },
 260         .m1 = { .min = 0, .max = 0 },
 261         .m2 = { .min = 0, .max = 254 },
 262         .p = { .min = 7, .max = 112 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 14 },
 266         .find_pll = intel_find_best_PLL,
 267 };
 268
 269 /* Ironlake / Sandybridge
 270  *
 271  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 272  * the range value for them is (actual_value - 2).
 273  */
 274 static const intel_limit_t intel_limits_ironlake_dac = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 5 },
 278         .m = { .min = 79, .max = 127 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285         .find_pll = intel_g4x_find_best_PLL,
 286 };
 287
 288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 289         .dot = { .min = 25000, .max = 350000 },
 290         .vco = { .min = 1760000, .max = 3510000 },
 291         .n = { .min = 1, .max = 3 },
 292         .m = { .min = 79, .max = 118 },
 293         .m1 = { .min = 12, .max = 22 },
 294         .m2 = { .min = 5, .max = 9 },
 295         .p = { .min = 28, .max = 112 },
 296         .p1 = { .min = 2, .max = 8 },
 297         .p2 = { .dot_limit = 225000,
 298                 .p2_slow = 14, .p2_fast = 14 },
 299         .find_pll = intel_g4x_find_best_PLL,
 300 };
 301
 302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 303         .dot = { .min = 25000, .max = 350000 },
 304         .vco = { .min = 1760000, .max = 3510000 },
 305         .n = { .min = 1, .max = 3 },
 306         .m = { .min = 79, .max = 127 },
 307         .m1 = { .min = 12, .max = 22 },
 308         .m2 = { .min = 5, .max = 9 },
 309         .p = { .min = 14, .max = 56 },
 310         .p1 = { .min = 2, .max = 8 },
 311         .p2 = { .dot_limit = 225000,
 312                 .p2_slow = 7, .p2_fast = 7 },
 313         .find_pll = intel_g4x_find_best_PLL,
 314 };
 315
 316 /* LVDS 100mhz refclk limits. */
 317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 318         .dot = { .min = 25000, .max = 350000 },
 319         .vco = { .min = 1760000, .max = 3510000 },
 320         .n = { .min = 1, .max = 2 },
 321         .m = { .min = 79, .max = 126 },
 322         .m1 = { .min = 12, .max = 22 },
 323         .m2 = { .min = 5, .max = 9 },
 324         .p = { .min = 28, .max = 112 },
 325         .p1 = { .min = 2, .max = 8 },
 326         .p2 = { .dot_limit = 225000,
 327                 .p2_slow = 14, .p2_fast = 14 },
 328         .find_pll = intel_g4x_find_best_PLL,
 329 };
 330
 331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 332         .dot = { .min = 25000, .max = 350000 },
 333         .vco = { .min = 1760000, .max = 3510000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 79, .max = 126 },
 336         .m1 = { .min = 12, .max = 22 },
 337         .m2 = { .min = 5, .max = 9 },
 338         .p = { .min = 14, .max = 42 },
 339         .p1 = { .min = 2, .max = 6 },
 340         .p2 = { .dot_limit = 225000,
 341                 .p2_slow = 7, .p2_fast = 7 },
 342         .find_pll = intel_g4x_find_best_PLL,
 343 };
 344
 345 static const intel_limit_t intel_limits_ironlake_display_port = {
 346         .dot = { .min = 25000, .max = 350000 },
 347         .vco = { .min = 1760000, .max = 3510000},
 348         .n = { .min = 1, .max = 2 },
 349         .m = { .min = 81, .max = 90 },
 350         .m1 = { .min = 12, .max = 22 },
 351         .m2 = { .min = 5, .max = 9 },
 352         .p = { .min = 10, .max = 20 },
 353         .p1 = { .min = 1, .max = 2},
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 10, .p2_fast = 10 },
 356         .find_pll = intel_find_pll_ironlake_dp,
 357 };
 358
 359 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 360                                                 int refclk)
 361 {
 362         struct drm_device *dev = crtc->dev;
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         const intel_limit_t *limit;
 365
 366         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 367                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 368                     LVDS_CLKB_POWER_UP) {
 369                         /* LVDS dual channel */
 370                         if (refclk == 100000)
 371                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 372                         else
 373                                 limit = &intel_limits_ironlake_dual_lvds;
 374                 } else {
 375                         if (refclk == 100000)
 376                                 limit = &intel_limits_ironlake_single_lvds_100m;
 377                         else
 378                                 limit = &intel_limits_ironlake_single_lvds;
 379                 }
 380         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 381                         HAS_eDP)
 382                 limit = &intel_limits_ironlake_display_port;
 383         else
 384                 limit = &intel_limits_ironlake_dac;
 385
 386         return limit;
 387 }
 388
 389 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 390 {
 391         struct drm_device *dev = crtc->dev;
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         const intel_limit_t *limit;
 394
 395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 396                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 397                     LVDS_CLKB_POWER_UP)
 398                         /* LVDS with dual channel */
 399                         limit = &intel_limits_g4x_dual_channel_lvds;
 400                 else
 401                         /* LVDS with dual channel */
 402                         limit = &intel_limits_g4x_single_channel_lvds;
 403         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 404                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 405                 limit = &intel_limits_g4x_hdmi;
 406         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 407                 limit = &intel_limits_g4x_sdvo;
 408         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 409                 limit = &intel_limits_g4x_display_port;
 410         } else /* The option is for other outputs */
 411                 limit = &intel_limits_i9xx_sdvo;
 412
 413         return limit;
 414 }
 415
 416 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 417 {
 418         struct drm_device *dev = crtc->dev;
 419         const intel_limit_t *limit;
 420
 421         if (HAS_PCH_SPLIT(dev))
 422                 limit = intel_ironlake_limit(crtc, refclk);
 423         else if (IS_G4X(dev)) {
 424                 limit = intel_g4x_limit(crtc);
 425         } else if (IS_PINEVIEW(dev)) {
 426                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 427                         limit = &intel_limits_pineview_lvds;
 428                 else
 429                         limit = &intel_limits_pineview_sdvo;
 430         } else if (!IS_GEN2(dev)) {
 431                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 432                         limit = &intel_limits_i9xx_lvds;
 433                 else
 434                         limit = &intel_limits_i9xx_sdvo;
 435         } else {
 436                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 437                         limit = &intel_limits_i8xx_lvds;
 438                 else
 439                         limit = &intel_limits_i8xx_dvo;
 440         }
 441         return limit;
 442 }
 443
 444 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 445 static void pineview_clock(int refclk, intel_clock_t *clock)
 446 {
 447         clock->m = clock->m2 + 2;
 448         clock->p = clock->p1 * clock->p2;
 449         clock->vco = refclk * clock->m / clock->n;
 450         clock->dot = clock->vco / clock->p;
 451 }
 452
 453 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 454 {
 455         if (IS_PINEVIEW(dev)) {
 456                 pineview_clock(refclk, clock);
 457                 return;
 458         }
 459         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 460         clock->p = clock->p1 * clock->p2;
 461         clock->vco = refclk * clock->m / (clock->n + 2);
 462         clock->dot = clock->vco / clock->p;
 463 }
 464
 465 /**
 466  * Returns whether any output on the specified pipe is of the specified type
 467  */
 468 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 469 {
 470         struct drm_device *dev = crtc->dev;
 471         struct drm_mode_config *mode_config = &dev->mode_config;
 472         struct intel_encoder *encoder;
 473
 474         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 475                 if (encoder->base.crtc == crtc && encoder->type == type)
 476                         return true;
 477
 478         return false;
 479 }
 480
 481 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 482 /**
 483  * Returns whether the given set of divisors are valid for a given refclk with
 484  * the given connectors.
 485  */
 486
 487 static bool intel_PLL_is_valid(struct drm_device *dev,
 488                                const intel_limit_t *limit,
 489                                const intel_clock_t *clock)
 490 {
 491         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 492                 INTELPllInvalid("p1 out of range\n");
 493         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 494                 INTELPllInvalid("p out of range\n");
 495         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 496                 INTELPllInvalid("m2 out of range\n");
 497         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 498                 INTELPllInvalid("m1 out of range\n");
 499         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 500                 INTELPllInvalid("m1 <= m2\n");
 501         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 502                 INTELPllInvalid("m out of range\n");
 503         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 504                 INTELPllInvalid("n out of range\n");
 505         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 506                 INTELPllInvalid("vco out of range\n");
 507         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 508          * connector, etc., rather than just a single range.
 509          */
 510         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 511                 INTELPllInvalid("dot out of range\n");
 512
 513         return true;
 514 }
 515
 516 static bool
 517 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 518                     int target, int refclk, intel_clock_t *best_clock)
 519
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         intel_clock_t clock;
 524         int err = target;
 525
 526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 527             (I915_READ(LVDS)) != 0) {
 528                 /*
 529                  * For LVDS, if the panel is on, just rely on its current
 530                  * settings for dual-channel.  We haven't figured out how to
 531                  * reliably set up different single/dual channel state, if we
 532                  * even can.
 533                  */
 534                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 535                     LVDS_CLKB_POWER_UP)
 536                         clock.p2 = limit->p2.p2_fast;
 537                 else
 538                         clock.p2 = limit->p2.p2_slow;
 539         } else {
 540                 if (target < limit->p2.dot_limit)
 541                         clock.p2 = limit->p2.p2_slow;
 542                 else
 543                         clock.p2 = limit->p2.p2_fast;
 544         }
 545
 546         memset(best_clock, 0, sizeof(*best_clock));
 547
 548         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 549              clock.m1++) {
 550                 for (clock.m2 = limit->m2.min;
 551                      clock.m2 <= limit->m2.max; clock.m2++) {
 552                         /* m1 is always 0 in Pineview */
 553                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 554                                 break;
 555                         for (clock.n = limit->n.min;
 556                              clock.n <= limit->n.max; clock.n++) {
 557                                 for (clock.p1 = limit->p1.min;
 558                                         clock.p1 <= limit->p1.max; clock.p1++) {
 559                                         int this_err;
 560
 561                                         intel_clock(dev, refclk, &clock);
 562                                         if (!intel_PLL_is_valid(dev, limit,
 563                                                                 &clock))
 564                                                 continue;
 565
 566                                         this_err = abs(clock.dot - target);
 567                                         if (this_err < err) {
 568                                                 *best_clock = clock;
 569                                                 err = this_err;
 570                                         }
 571                                 }
 572                         }
 573                 }
 574         }
 575
 576         return (err != target);
 577 }
 578
 579 static bool
 580 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 581                         int target, int refclk, intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         intel_clock_t clock;
 586         int max_n;
 587         bool found;
 588         /* approximately equals target * 0.00585 */
 589         int err_most = (target >> 8) + (target >> 9);
 590         found = false;
 591
 592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 593                 int lvds_reg;
 594
 595                 if (HAS_PCH_SPLIT(dev))
 596                         lvds_reg = PCH_LVDS;
 597                 else
 598                         lvds_reg = LVDS;
 599                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 600                     LVDS_CLKB_POWER_UP)
 601                         clock.p2 = limit->p2.p2_fast;
 602                 else
 603                         clock.p2 = limit->p2.p2_slow;
 604         } else {
 605                 if (target < limit->p2.dot_limit)
 606                         clock.p2 = limit->p2.p2_slow;
 607                 else
 608                         clock.p2 = limit->p2.p2_fast;
 609         }
 610
 611         memset(best_clock, 0, sizeof(*best_clock));
 612         max_n = limit->n.max;
 613         /* based on hardware requirement, prefer smaller n to precision */
 614         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 615                 /* based on hardware requirement, prefere larger m1,m2 */
 616                 for (clock.m1 = limit->m1.max;
 617                      clock.m1 >= limit->m1.min; clock.m1--) {
 618                         for (clock.m2 = limit->m2.max;
 619                              clock.m2 >= limit->m2.min; clock.m2--) {
 620                                 for (clock.p1 = limit->p1.max;
 621                                      clock.p1 >= limit->p1.min; clock.p1--) {
 622                                         int this_err;
 623
 624                                         intel_clock(dev, refclk, &clock);
 625                                         if (!intel_PLL_is_valid(dev, limit,
 626                                                                 &clock))
 627                                                 continue;
 628
 629                                         this_err = abs(clock.dot - target);
 630                                         if (this_err < err_most) {
 631                                                 *best_clock = clock;
 632                                                 err_most = this_err;
 633                                                 max_n = clock.n;
 634                                                 found = true;
 635                                         }
 636                                 }
 637                         }
 638                 }
 639         }
 640         return found;
 641 }
 642
 643 static bool
 644 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 645                            int target, int refclk, intel_clock_t *best_clock)
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         intel_clock_t clock;
 649
 650         if (target < 200000) {
 651                 clock.n = 1;
 652                 clock.p1 = 2;
 653                 clock.p2 = 10;
 654                 clock.m1 = 12;
 655                 clock.m2 = 9;
 656         } else {
 657                 clock.n = 2;
 658                 clock.p1 = 1;
 659                 clock.p2 = 10;
 660                 clock.m1 = 14;
 661                 clock.m2 = 8;
 662         }
 663         intel_clock(dev, refclk, &clock);
 664         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 665         return true;
 666 }
 667
 668 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 669 static bool
 670 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 671                       int target, int refclk, intel_clock_t *best_clock)
 672 {
 673         intel_clock_t clock;
 674         if (target < 200000) {
 675                 clock.p1 = 2;
 676                 clock.p2 = 10;
 677                 clock.n = 2;
 678                 clock.m1 = 23;
 679                 clock.m2 = 8;
 680         } else {
 681                 clock.p1 = 1;
 682                 clock.p2 = 10;
 683                 clock.n = 1;
 684                 clock.m1 = 14;
 685                 clock.m2 = 2;
 686         }
 687         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 688         clock.p = (clock.p1 * clock.p2);
 689         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 690         clock.vco = 0;
 691         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 692         return true;
 693 }
 694
 695 /**
 696  * intel_wait_for_vblank - wait for vblank on a given pipe
 697  * @dev: drm device
 698  * @pipe: pipe to wait for
 699  *
 700  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 701  * mode setting code.
 702  */
 703 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         int pipestat_reg = PIPESTAT(pipe);
 707
 708         /* Clear existing vblank status. Note this will clear any other
 709          * sticky status fields as well.
 710          *
 711          * This races with i915_driver_irq_handler() with the result
 712          * that either function could miss a vblank event.  Here it is not
 713          * fatal, as we will either wait upon the next vblank interrupt or
 714          * timeout.  Generally speaking intel_wait_for_vblank() is only
 715          * called during modeset at which time the GPU should be idle and
 716          * should *not* be performing page flips and thus not waiting on
 717          * vblanks...
 718          * Currently, the result of us stealing a vblank from the irq
 719          * handler is that a single frame will be skipped during swapbuffers.
 720          */
 721         I915_WRITE(pipestat_reg,
 722                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 723
 724         /* Wait for vblank interrupt bit to set */
 725         if (wait_for(I915_READ(pipestat_reg) &
 726                      PIPE_VBLANK_INTERRUPT_STATUS,
 727                      50))
 728                 DRM_DEBUG_KMS("vblank wait timed out\n");
 729 }
 730
 731 /*
 732  * intel_wait_for_pipe_off - wait for pipe to turn off
 733  * @dev: drm device
 734  * @pipe: pipe to wait for
 735  *
 736  * After disabling a pipe, we can't wait for vblank in the usual way,
 737  * spinning on the vblank interrupt status bit, since we won't actually
 738  * see an interrupt when the pipe is disabled.
 739  *
 740  * On Gen4 and above:
 741  *   wait for the pipe register state bit to turn off
 742  *
 743  * Otherwise:
 744  *   wait for the display line value to settle (it usually
 745  *   ends up stopping at the start of the next frame).
 746  *
 747  */
 748 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751
 752         if (INTEL_INFO(dev)->gen >= 4) {
 753                 int reg = PIPECONF(pipe);
 754
 755                 /* Wait for the Pipe State to go off */
 756                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 757                              100))
 758                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 759         } else {
 760                 u32 last_line;
 761                 int reg = PIPEDSL(pipe);
 762                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 763
 764                 /* Wait for the display line to settle */
 765                 do {
 766                         last_line = I915_READ(reg) & DSL_LINEMASK;
 767                         mdelay(5);
 768                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
 769                          time_after(timeout, jiffies));
 770                 if (time_after(jiffies, timeout))
 771                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
 772         }
 773 }
 774
 775 static const char *state_string(bool enabled)
 776 {
 777         return enabled ? "on" : "off";
 778 }
 779
 780 /* Only for pre-ILK configs */
 781 static void assert_pll(struct drm_i915_private *dev_priv,
 782                        enum pipe pipe, bool state)
 783 {
 784         int reg;
 785         u32 val;
 786         bool cur_state;
 787
 788         reg = DPLL(pipe);
 789         val = I915_READ(reg);
 790         cur_state = !!(val & DPLL_VCO_ENABLE);
 791         WARN(cur_state != state,
 792              "PLL state assertion failure (expected %s, current %s)\n",
 793              state_string(state), state_string(cur_state));
 794 }
 795 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 796 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 797
 798 /* For ILK+ */
 799 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 800                            enum pipe pipe, bool state)
 801 {
 802         int reg;
 803         u32 val;
 804         bool cur_state;
 805
 806         if (HAS_PCH_CPT(dev_priv->dev)) {
 807                 u32 pch_dpll;
 808
 809                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 810
 811                 /* Make sure the selected PLL is enabled to the transcoder */
 812                 WARN(!((pch_dpll >> (4 * pipe)) & 8),
 813                      "transcoder %d PLL not enabled\n", pipe);
 814
 815                 /* Convert the transcoder pipe number to a pll pipe number */
 816                 pipe = (pch_dpll >> (4 * pipe)) & 1;
 817         }
 818
 819         reg = PCH_DPLL(pipe);
 820         val = I915_READ(reg);
 821         cur_state = !!(val & DPLL_VCO_ENABLE);
 822         WARN(cur_state != state,
 823              "PCH PLL state assertion failure (expected %s, current %s)\n",
 824              state_string(state), state_string(cur_state));
 825 }
 826 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
 827 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
 828
 829 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 830                           enum pipe pipe, bool state)
 831 {
 832         int reg;
 833         u32 val;
 834         bool cur_state;
 835
 836         reg = FDI_TX_CTL(pipe);
 837         val = I915_READ(reg);
 838         cur_state = !!(val & FDI_TX_ENABLE);
 839         WARN(cur_state != state,
 840              "FDI TX state assertion failure (expected %s, current %s)\n",
 841              state_string(state), state_string(cur_state));
 842 }
 843 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 844 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 845
 846 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 847                           enum pipe pipe, bool state)
 848 {
 849         int reg;
 850         u32 val;
 851         bool cur_state;
 852
 853         reg = FDI_RX_CTL(pipe);
 854         val = I915_READ(reg);
 855         cur_state = !!(val & FDI_RX_ENABLE);
 856         WARN(cur_state != state,
 857              "FDI RX state assertion failure (expected %s, current %s)\n",
 858              state_string(state), state_string(cur_state));
 859 }
 860 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 861 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 862
 863 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 864                                       enum pipe pipe)
 865 {
 866         int reg;
 867         u32 val;
 868
 869         /* ILK FDI PLL is always enabled */
 870         if (dev_priv->info->gen == 5)
 871                 return;
 872
 873         reg = FDI_TX_CTL(pipe);
 874         val = I915_READ(reg);
 875         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 876 }
 877
 878 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 879                                       enum pipe pipe)
 880 {
 881         int reg;
 882         u32 val;
 883
 884         reg = FDI_RX_CTL(pipe);
 885         val = I915_READ(reg);
 886         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
 887 }
 888
 889 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 890                                   enum pipe pipe)
 891 {
 892         int pp_reg, lvds_reg;
 893         u32 val;
 894         enum pipe panel_pipe = PIPE_A;
 895         bool locked = true;
 896
 897         if (HAS_PCH_SPLIT(dev_priv->dev)) {
 898                 pp_reg = PCH_PP_CONTROL;
 899                 lvds_reg = PCH_LVDS;
 900         } else {
 901                 pp_reg = PP_CONTROL;
 902                 lvds_reg = LVDS;
 903         }
 904
 905         val = I915_READ(pp_reg);
 906         if (!(val & PANEL_POWER_ON) ||
 907             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
 908                 locked = false;
 909
 910         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
 911                 panel_pipe = PIPE_B;
 912
 913         WARN(panel_pipe == pipe && locked,
 914              "panel assertion failure, pipe %c regs locked\n",
 915              pipe_name(pipe));
 916 }
 917
 918 static void assert_pipe(struct drm_i915_private *dev_priv,
 919                         enum pipe pipe, bool state)
 920 {
 921         int reg;
 922         u32 val;
 923         bool cur_state;
 924
 925         reg = PIPECONF(pipe);
 926         val = I915_READ(reg);
 927         cur_state = !!(val & PIPECONF_ENABLE);
 928         WARN(cur_state != state,
 929              "pipe %c assertion failure (expected %s, current %s)\n",
 930              pipe_name(pipe), state_string(state), state_string(cur_state));
 931 }
 932 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 933 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 934
 935 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
 936                                  enum plane plane)
 937 {
 938         int reg;
 939         u32 val;
 940
 941         reg = DSPCNTR(plane);
 942         val = I915_READ(reg);
 943         WARN(!(val & DISPLAY_PLANE_ENABLE),
 944              "plane %c assertion failure, should be active but is disabled\n",
 945              plane_name(plane));
 946 }
 947
 948 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 949                                    enum pipe pipe)
 950 {
 951         int reg, i;
 952         u32 val;
 953         int cur_pipe;
 954
 955         /* Planes are fixed to pipes on ILK+ */
 956         if (HAS_PCH_SPLIT(dev_priv->dev))
 957                 return;
 958
 959         /* Need to check both planes against the pipe */
 960         for (i = 0; i < 2; i++) {
 961                 reg = DSPCNTR(i);
 962                 val = I915_READ(reg);
 963                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 964                         DISPPLANE_SEL_PIPE_SHIFT;
 965                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 966                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
 967                      plane_name(i), pipe_name(pipe));
 968         }
 969 }
 970
 971 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 972 {
 973         u32 val;
 974         bool enabled;
 975
 976         val = I915_READ(PCH_DREF_CONTROL);
 977         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 978                             DREF_SUPERSPREAD_SOURCE_MASK));
 979         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 980 }
 981
 982 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
 983                                        enum pipe pipe)
 984 {
 985         int reg;
 986         u32 val;
 987         bool enabled;
 988
 989         reg = TRANSCONF(pipe);
 990         val = I915_READ(reg);
 991         enabled = !!(val & TRANS_ENABLE);
 992         WARN(enabled,
 993              "transcoder assertion failed, should be off on pipe %c but is still active\n",
 994              pipe_name(pipe));
 995 }
 996
 997 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
 998                             enum pipe pipe, u32 port_sel, u32 val)
 999 {
1000         if ((val & DP_PORT_EN) == 0)
1001                 return false;
1002
1003         if (HAS_PCH_CPT(dev_priv->dev)) {
1004                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007                         return false;
1008         } else {
1009                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010                         return false;
1011         }
1012         return true;
1013 }
1014
1015 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016                               enum pipe pipe, u32 val)
1017 {
1018         if ((val & PORT_ENABLE) == 0)
1019                 return false;
1020
1021         if (HAS_PCH_CPT(dev_priv->dev)) {
1022                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023                         return false;
1024         } else {
1025                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026                         return false;
1027         }
1028         return true;
1029 }
1030
1031 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032                               enum pipe pipe, u32 val)
1033 {
1034         if ((val & LVDS_PORT_EN) == 0)
1035                 return false;
1036
1037         if (HAS_PCH_CPT(dev_priv->dev)) {
1038                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039                         return false;
1040         } else {
1041                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042                         return false;
1043         }
1044         return true;
1045 }
1046
1047 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048                               enum pipe pipe, u32 val)
1049 {
1050         if ((val & ADPA_DAC_ENABLE) == 0)
1051                 return false;
1052         if (HAS_PCH_CPT(dev_priv->dev)) {
1053                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054                         return false;
1055         } else {
1056                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057                         return false;
1058         }
1059         return true;
1060 }
1061
1062 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1063                                    enum pipe pipe, int reg, u32 port_sel)
1064 {
1065         u32 val = I915_READ(reg);
1066         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1067              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1068              reg, pipe_name(pipe));
1069 }
1070
1071 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072                                      enum pipe pipe, int reg)
1073 {
1074         u32 val = I915_READ(reg);
1075         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1076              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1077              reg, pipe_name(pipe));
1078 }
1079
1080 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081                                       enum pipe pipe)
1082 {
1083         int reg;
1084         u32 val;
1085
1086         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1089
1090         reg = PCH_ADPA;
1091         val = I915_READ(reg);
1092         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1093              "PCH VGA enabled on transcoder %c, should be disabled\n",
1094              pipe_name(pipe));
1095
1096         reg = PCH_LVDS;
1097         val = I915_READ(reg);
1098         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1099              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1100              pipe_name(pipe));
1101
1102         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105 }
1106
1107 /**
1108  * intel_enable_pll - enable a PLL
1109  * @dev_priv: i915 private structure
1110  * @pipe: pipe PLL to enable
1111  *
1112  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1113  * make sure the PLL reg is writable first though, since the panel write
1114  * protect mechanism may be enabled.
1115  *
1116  * Note!  This is for pre-ILK only.
1117  */
1118 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119 {
1120         int reg;
1121         u32 val;
1122
1123         /* No really, not for ILK+ */
1124         BUG_ON(dev_priv->info->gen >= 5);
1125
1126         /* PLL is protected by panel, make sure we can write it */
1127         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128                 assert_panel_unlocked(dev_priv, pipe);
1129
1130         reg = DPLL(pipe);
1131         val = I915_READ(reg);
1132         val |= DPLL_VCO_ENABLE;
1133
1134         /* We do this three times for luck */
1135         I915_WRITE(reg, val);
1136         POSTING_READ(reg);
1137         udelay(150); /* wait for warmup */
1138         I915_WRITE(reg, val);
1139         POSTING_READ(reg);
1140         udelay(150); /* wait for warmup */
1141         I915_WRITE(reg, val);
1142         POSTING_READ(reg);
1143         udelay(150); /* wait for warmup */
1144 }
1145
1146 /**
1147  * intel_disable_pll - disable a PLL
1148  * @dev_priv: i915 private structure
1149  * @pipe: pipe PLL to disable
1150  *
1151  * Disable the PLL for @pipe, making sure the pipe is off first.
1152  *
1153  * Note!  This is for pre-ILK only.
1154  */
1155 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         int reg;
1158         u32 val;
1159
1160         /* Don't disable pipe A or pipe A PLLs if needed */
1161         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162                 return;
1163
1164         /* Make sure the pipe isn't still relying on us */
1165         assert_pipe_disabled(dev_priv, pipe);
1166
1167         reg = DPLL(pipe);
1168         val = I915_READ(reg);
1169         val &= ~DPLL_VCO_ENABLE;
1170         I915_WRITE(reg, val);
1171         POSTING_READ(reg);
1172 }
1173
1174 /**
1175  * intel_enable_pch_pll - enable PCH PLL
1176  * @dev_priv: i915 private structure
1177  * @pipe: pipe PLL to enable
1178  *
1179  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180  * drives the transcoder clock.
1181  */
1182 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183                                  enum pipe pipe)
1184 {
1185         int reg;
1186         u32 val;
1187
1188         if (pipe > 1)
1189                 return;
1190
1191         /* PCH only available on ILK+ */
1192         BUG_ON(dev_priv->info->gen < 5);
1193
1194         /* PCH refclock must be enabled first */
1195         assert_pch_refclk_enabled(dev_priv);
1196
1197         reg = PCH_DPLL(pipe);
1198         val = I915_READ(reg);
1199         val |= DPLL_VCO_ENABLE;
1200         I915_WRITE(reg, val);
1201         POSTING_READ(reg);
1202         udelay(200);
1203 }
1204
1205 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206                                   enum pipe pipe)
1207 {
1208         int reg;
1209         u32 val;
1210
1211         if (pipe > 1)
1212                 return;
1213
1214         /* PCH only available on ILK+ */
1215         BUG_ON(dev_priv->info->gen < 5);
1216
1217         /* Make sure transcoder isn't still depending on us */
1218         assert_transcoder_disabled(dev_priv, pipe);
1219
1220         reg = PCH_DPLL(pipe);
1221         val = I915_READ(reg);
1222         val &= ~DPLL_VCO_ENABLE;
1223         I915_WRITE(reg, val);
1224         POSTING_READ(reg);
1225         udelay(200);
1226 }
1227
1228 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229                                     enum pipe pipe)
1230 {
1231         int reg;
1232         u32 val;
1233
1234         /* PCH only available on ILK+ */
1235         BUG_ON(dev_priv->info->gen < 5);
1236
1237         /* Make sure PCH DPLL is enabled */
1238         assert_pch_pll_enabled(dev_priv, pipe);
1239
1240         /* FDI must be feeding us bits for PCH ports */
1241         assert_fdi_tx_enabled(dev_priv, pipe);
1242         assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244         reg = TRANSCONF(pipe);
1245         val = I915_READ(reg);
1246
1247         if (HAS_PCH_IBX(dev_priv->dev)) {
1248                 /*
1249                  * make the BPC in transcoder be consistent with
1250                  * that in pipeconf reg.
1251                  */
1252                 val &= ~PIPE_BPC_MASK;
1253                 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254         }
1255         I915_WRITE(reg, val | TRANS_ENABLE);
1256         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258 }
1259
1260 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261                                      enum pipe pipe)
1262 {
1263         int reg;
1264         u32 val;
1265
1266         /* FDI relies on the transcoder */
1267         assert_fdi_tx_disabled(dev_priv, pipe);
1268         assert_fdi_rx_disabled(dev_priv, pipe);
1269
1270         /* Ports must be off as well */
1271         assert_pch_ports_disabled(dev_priv, pipe);
1272
1273         reg = TRANSCONF(pipe);
1274         val = I915_READ(reg);
1275         val &= ~TRANS_ENABLE;
1276         I915_WRITE(reg, val);
1277         /* wait for PCH transcoder off, transcoder state */
1278         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1280 }
1281
1282 /**
1283  * intel_enable_pipe - enable a pipe, asserting requirements
1284  * @dev_priv: i915 private structure
1285  * @pipe: pipe to enable
1286  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1287  *
1288  * Enable @pipe, making sure that various hardware specific requirements
1289  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290  *
1291  * @pipe should be %PIPE_A or %PIPE_B.
1292  *
1293  * Will wait until the pipe is actually running (i.e. first vblank) before
1294  * returning.
1295  */
1296 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297                               bool pch_port)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         /*
1303          * A pipe without a PLL won't actually be able to drive bits from
1304          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1305          * need the check.
1306          */
1307         if (!HAS_PCH_SPLIT(dev_priv->dev))
1308                 assert_pll_enabled(dev_priv, pipe);
1309         else {
1310                 if (pch_port) {
1311                         /* if driving the PCH, we need FDI enabled */
1312                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314                 }
1315                 /* FIXME: assert CPU port conditions for SNB+ */
1316         }
1317
1318         reg = PIPECONF(pipe);
1319         val = I915_READ(reg);
1320         if (val & PIPECONF_ENABLE)
1321                 return;
1322
1323         I915_WRITE(reg, val | PIPECONF_ENABLE);
1324         intel_wait_for_vblank(dev_priv->dev, pipe);
1325 }
1326
1327 /**
1328  * intel_disable_pipe - disable a pipe, asserting requirements
1329  * @dev_priv: i915 private structure
1330  * @pipe: pipe to disable
1331  *
1332  * Disable @pipe, making sure that various hardware specific requirements
1333  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334  *
1335  * @pipe should be %PIPE_A or %PIPE_B.
1336  *
1337  * Will wait until the pipe has shut down before returning.
1338  */
1339 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340                                enum pipe pipe)
1341 {
1342         int reg;
1343         u32 val;
1344
1345         /*
1346          * Make sure planes won't keep trying to pump pixels to us,
1347          * or we might hang the display.
1348          */
1349         assert_planes_disabled(dev_priv, pipe);
1350
1351         /* Don't disable pipe A or pipe A PLLs if needed */
1352         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353                 return;
1354
1355         reg = PIPECONF(pipe);
1356         val = I915_READ(reg);
1357         if ((val & PIPECONF_ENABLE) == 0)
1358                 return;
1359
1360         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1361         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362 }
1363
1364 /*
1365  * Plane regs are double buffered, going from enabled->disabled needs a
1366  * trigger in order to latch.  The display address reg provides this.
1367  */
1368 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369                                       enum plane plane)
1370 {
1371         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373 }
1374
1375 /**
1376  * intel_enable_plane - enable a display plane on a given pipe
1377  * @dev_priv: i915 private structure
1378  * @plane: plane to enable
1379  * @pipe: pipe being fed
1380  *
1381  * Enable @plane on @pipe, making sure that @pipe is running first.
1382  */
1383 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384                                enum plane plane, enum pipe pipe)
1385 {
1386         int reg;
1387         u32 val;
1388
1389         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390         assert_pipe_enabled(dev_priv, pipe);
1391
1392         reg = DSPCNTR(plane);
1393         val = I915_READ(reg);
1394         if (val & DISPLAY_PLANE_ENABLE)
1395                 return;
1396
1397         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1398         intel_flush_display_plane(dev_priv, plane);
1399         intel_wait_for_vblank(dev_priv->dev, pipe);
1400 }
1401
1402 /**
1403  * intel_disable_plane - disable a display plane
1404  * @dev_priv: i915 private structure
1405  * @plane: plane to disable
1406  * @pipe: pipe consuming the data
1407  *
1408  * Disable @plane; should be an independent operation.
1409  */
1410 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411                                 enum plane plane, enum pipe pipe)
1412 {
1413         int reg;
1414         u32 val;
1415
1416         reg = DSPCNTR(plane);
1417         val = I915_READ(reg);
1418         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419                 return;
1420
1421         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1422         intel_flush_display_plane(dev_priv, plane);
1423         intel_wait_for_vblank(dev_priv->dev, pipe);
1424 }
1425
1426 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1427                            enum pipe pipe, int reg, u32 port_sel)
1428 {
1429         u32 val = I915_READ(reg);
1430         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1431                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1432                 I915_WRITE(reg, val & ~DP_PORT_EN);
1433         }
1434 }
1435
1436 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437                              enum pipe pipe, int reg)
1438 {
1439         u32 val = I915_READ(reg);
1440         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1441                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442                               reg, pipe);
1443                 I915_WRITE(reg, val & ~PORT_ENABLE);
1444         }
1445 }
1446
1447 /* Disable any ports connected to this transcoder */
1448 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449                                     enum pipe pipe)
1450 {
1451         u32 reg, val;
1452
1453         val = I915_READ(PCH_PP_CONTROL);
1454         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
1456         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1459
1460         reg = PCH_ADPA;
1461         val = I915_READ(reg);
1462         if (adpa_pipe_enabled(dev_priv, val, pipe))
1463                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465         reg = PCH_LVDS;
1466         val = I915_READ(reg);
1467         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1469                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470                 POSTING_READ(reg);
1471                 udelay(100);
1472         }
1473
1474         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476         disable_pch_hdmi(dev_priv, pipe, HDMID);
1477 }
1478
1479 static void i8xx_disable_fbc(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         u32 fbc_ctl;
1483
1484         /* Disable compression */
1485         fbc_ctl = I915_READ(FBC_CONTROL);
1486         if ((fbc_ctl & FBC_CTL_EN) == 0)
1487                 return;
1488
1489         fbc_ctl &= ~FBC_CTL_EN;
1490         I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492         /* Wait for compressing bit to clear */
1493         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494                 DRM_DEBUG_KMS("FBC idle timed out\n");
1495                 return;
1496         }
1497
1498         DRM_DEBUG_KMS("disabled FBC\n");
1499 }
1500
1501 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502 {
1503         struct drm_device *dev = crtc->dev;
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct drm_framebuffer *fb = crtc->fb;
1506         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1507         struct drm_i915_gem_object *obj = intel_fb->obj;
1508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509         int cfb_pitch;
1510         int plane, i;
1511         u32 fbc_ctl, fbc_ctl2;
1512
1513         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514         if (fb->pitch < cfb_pitch)
1515                 cfb_pitch = fb->pitch;
1516
1517         /* FBC_CTL wants 64B units */
1518         cfb_pitch = (cfb_pitch / 64) - 1;
1519         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1520
1521         /* Clear old tags */
1522         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523                 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525         /* Set it up... */
1526         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527         fbc_ctl2 |= plane;
1528         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531         /* enable it... */
1532         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1533         if (IS_I945GM(dev))
1534                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1535         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1536         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1537         fbc_ctl |= obj->fence_reg;
1538         I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
1540         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541                       cfb_pitch, crtc->y, intel_crtc->plane);
1542 }
1543
1544 static bool i8xx_fbc_enabled(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549 }
1550
1551 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552 {
1553         struct drm_device *dev = crtc->dev;
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct drm_framebuffer *fb = crtc->fb;
1556         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1557         struct drm_i915_gem_object *obj = intel_fb->obj;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1560         unsigned long stall_watermark = 200;
1561         u32 dpfc_ctl;
1562
1563         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1564         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1565         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1566
1567         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572         /* enable it... */
1573         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
1575         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1576 }
1577
1578 static void g4x_disable_fbc(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 dpfc_ctl;
1582
1583         /* Disable compression */
1584         dpfc_ctl = I915_READ(DPFC_CONTROL);
1585         if (dpfc_ctl & DPFC_CTL_EN) {
1586                 dpfc_ctl &= ~DPFC_CTL_EN;
1587                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1588
1589                 DRM_DEBUG_KMS("disabled FBC\n");
1590         }
1591 }
1592
1593 static bool g4x_fbc_enabled(struct drm_device *dev)
1594 {
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598 }
1599
1600 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601 {
1602         struct drm_i915_private *dev_priv = dev->dev_private;
1603         u32 blt_ecoskpd;
1604
1605         /* Make sure blitter notifies FBC of writes */
1606         gen6_gt_force_wake_get(dev_priv);
1607         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609                 GEN6_BLITTER_LOCK_SHIFT;
1610         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614                          GEN6_BLITTER_LOCK_SHIFT);
1615         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616         POSTING_READ(GEN6_BLITTER_ECOSKPD);
1617         gen6_gt_force_wake_put(dev_priv);
1618 }
1619
1620 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621 {
1622         struct drm_device *dev = crtc->dev;
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624         struct drm_framebuffer *fb = crtc->fb;
1625         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1626         struct drm_i915_gem_object *obj = intel_fb->obj;
1627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1628         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1629         unsigned long stall_watermark = 200;
1630         u32 dpfc_ctl;
1631
1632         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1633         dpfc_ctl &= DPFC_RESERVED;
1634         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1635         /* Set persistent mode for front-buffer rendering, ala X. */
1636         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1637         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1638         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1639
1640         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1644         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1645         /* enable it... */
1646         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1647
1648         if (IS_GEN6(dev)) {
1649                 I915_WRITE(SNB_DPFC_CTL_SA,
1650                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1651                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1652                 sandybridge_blit_fbc_update(dev);
1653         }
1654
1655         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656 }
1657
1658 static void ironlake_disable_fbc(struct drm_device *dev)
1659 {
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         u32 dpfc_ctl;
1662
1663         /* Disable compression */
1664         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1665         if (dpfc_ctl & DPFC_CTL_EN) {
1666                 dpfc_ctl &= ~DPFC_CTL_EN;
1667                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1668
1669                 DRM_DEBUG_KMS("disabled FBC\n");
1670         }
1671 }
1672
1673 static bool ironlake_fbc_enabled(struct drm_device *dev)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678 }
1679
1680 bool intel_fbc_enabled(struct drm_device *dev)
1681 {
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684         if (!dev_priv->display.fbc_enabled)
1685                 return false;
1686
1687         return dev_priv->display.fbc_enabled(dev);
1688 }
1689
1690 static void intel_fbc_work_fn(struct work_struct *__work)
1691 {
1692         struct intel_fbc_work *work =
1693                 container_of(to_delayed_work(__work),
1694                              struct intel_fbc_work, work);
1695         struct drm_device *dev = work->crtc->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698         mutex_lock(&dev->struct_mutex);
1699         if (work == dev_priv->fbc_work) {
1700                 /* Double check that we haven't switched fb without cancelling
1701                  * the prior work.
1702                  */
1703                 if (work->crtc->fb == work->fb) {
1704                         dev_priv->display.enable_fbc(work->crtc,
1705                                                      work->interval);
1706
1707                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708                         dev_priv->cfb_fb = work->crtc->fb->base.id;
1709                         dev_priv->cfb_y = work->crtc->y;
1710                 }
1711
1712                 dev_priv->fbc_work = NULL;
1713         }
1714         mutex_unlock(&dev->struct_mutex);
1715
1716         kfree(work);
1717 }
1718
1719 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720 {
1721         if (dev_priv->fbc_work == NULL)
1722                 return;
1723
1724         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726         /* Synchronisation is provided by struct_mutex and checking of
1727          * dev_priv->fbc_work, so we can perform the cancellation
1728          * entirely asynchronously.
1729          */
1730         if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731                 /* tasklet was killed before being run, clean up */
1732                 kfree(dev_priv->fbc_work);
1733
1734         /* Mark the work as no longer wanted so that if it does
1735          * wake-up (because the work was already running and waiting
1736          * for our mutex), it will discover that is no longer
1737          * necessary to run.
1738          */
1739         dev_priv->fbc_work = NULL;
1740 }
1741
1742 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1743 {
1744         struct intel_fbc_work *work;
1745         struct drm_device *dev = crtc->dev;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         if (!dev_priv->display.enable_fbc)
1749                 return;
1750
1751         intel_cancel_fbc_work(dev_priv);
1752
1753         work = kzalloc(sizeof *work, GFP_KERNEL);
1754         if (work == NULL) {
1755                 dev_priv->display.enable_fbc(crtc, interval);
1756                 return;
1757         }
1758
1759         work->crtc = crtc;
1760         work->fb = crtc->fb;
1761         work->interval = interval;
1762         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764         dev_priv->fbc_work = work;
1765
1766         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768         /* Delay the actual enabling to let pageflipping cease and the
1769          * display to settle before starting the compression. Note that
1770          * this delay also serves a second purpose: it allows for a
1771          * vblank to pass after disabling the FBC before we attempt
1772          * to modify the control registers.
1773          *
1774          * A more complicated solution would involve tracking vblanks
1775          * following the termination of the page-flipping sequence
1776          * and indeed performing the enable as a co-routine and not
1777          * waiting synchronously upon the vblank.
1778          */
1779         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1780 }
1781
1782 void intel_disable_fbc(struct drm_device *dev)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785
1786         intel_cancel_fbc_work(dev_priv);
1787
1788         if (!dev_priv->display.disable_fbc)
1789                 return;
1790
1791         dev_priv->display.disable_fbc(dev);
1792         dev_priv->cfb_plane = -1;
1793 }
1794
1795 /**
1796  * intel_update_fbc - enable/disable FBC as needed
1797  * @dev: the drm_device
1798  *
1799  * Set up the framebuffer compression hardware at mode set time.  We
1800  * enable it if possible:
1801  *   - plane A only (on pre-965)
1802  *   - no pixel mulitply/line duplication
1803  *   - no alpha buffer discard
1804  *   - no dual wide
1805  *   - framebuffer <= 2048 in width, 1536 in height
1806  *
1807  * We can't assume that any compression will take place (worst case),
1808  * so the compressed buffer has to be the same size as the uncompressed
1809  * one.  It also must reside (along with the line length buffer) in
1810  * stolen memory.
1811  *
1812  * We need to enable/disable FBC on a global basis.
1813  */
1814 static void intel_update_fbc(struct drm_device *dev)
1815 {
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         struct drm_crtc *crtc = NULL, *tmp_crtc;
1818         struct intel_crtc *intel_crtc;
1819         struct drm_framebuffer *fb;
1820         struct intel_framebuffer *intel_fb;
1821         struct drm_i915_gem_object *obj;
1822         int enable_fbc;
1823
1824         DRM_DEBUG_KMS("\n");
1825
1826         if (!i915_powersave)
1827                 return;
1828
1829         if (!I915_HAS_FBC(dev))
1830                 return;
1831
1832         /*
1833          * If FBC is already on, we just have to verify that we can
1834          * keep it that way...
1835          * Need to disable if:
1836          *   - more than one pipe is active
1837          *   - changing FBC params (stride, fence, mode)
1838          *   - new fb is too large to fit in compressed buffer
1839          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1840          */
1841         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1842                 if (tmp_crtc->enabled && tmp_crtc->fb) {
1843                         if (crtc) {
1844                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846                                 goto out_disable;
1847                         }
1848                         crtc = tmp_crtc;
1849                 }
1850         }
1851
1852         if (!crtc || crtc->fb == NULL) {
1853                 DRM_DEBUG_KMS("no output, disabling\n");
1854                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1855                 goto out_disable;
1856         }
1857
1858         intel_crtc = to_intel_crtc(crtc);
1859         fb = crtc->fb;
1860         intel_fb = to_intel_framebuffer(fb);
1861         obj = intel_fb->obj;
1862
1863         enable_fbc = i915_enable_fbc;
1864         if (enable_fbc < 0) {
1865                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866                 enable_fbc = 1;
1867                 if (INTEL_INFO(dev)->gen <= 5)
1868                         enable_fbc = 0;
1869         }
1870         if (!enable_fbc) {
1871                 DRM_DEBUG_KMS("fbc disabled per module param\n");
1872                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873                 goto out_disable;
1874         }
1875         if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1876                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1877                               "compression\n");
1878                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1879                 goto out_disable;
1880         }
1881         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1883                 DRM_DEBUG_KMS("mode incompatible with compression, "
1884                               "disabling\n");
1885                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1886                 goto out_disable;
1887         }
1888         if ((crtc->mode.hdisplay > 2048) ||
1889             (crtc->mode.vdisplay > 1536)) {
1890                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1891                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1892                 goto out_disable;
1893         }
1894         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1895                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1896                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1897                 goto out_disable;
1898         }
1899
1900         /* The use of a CPU fence is mandatory in order to detect writes
1901          * by the CPU to the scanout and trigger updates to the FBC.
1902          */
1903         if (obj->tiling_mode != I915_TILING_X ||
1904             obj->fence_reg == I915_FENCE_REG_NONE) {
1905                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1906                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1907                 goto out_disable;
1908         }
1909
1910         /* If the kernel debugger is active, always disable compression */
1911         if (in_dbg_master())
1912                 goto out_disable;
1913
1914         /* If the scanout has not changed, don't modify the FBC settings.
1915          * Note that we make the fundamental assumption that the fb->obj
1916          * cannot be unpinned (and have its GTT offset and fence revoked)
1917          * without first being decoupled from the scanout and FBC disabled.
1918          */
1919         if (dev_priv->cfb_plane == intel_crtc->plane &&
1920             dev_priv->cfb_fb == fb->base.id &&
1921             dev_priv->cfb_y == crtc->y)
1922                 return;
1923
1924         if (intel_fbc_enabled(dev)) {
1925                 /* We update FBC along two paths, after changing fb/crtc
1926                  * configuration (modeswitching) and after page-flipping
1927                  * finishes. For the latter, we know that not only did
1928                  * we disable the FBC at the start of the page-flip
1929                  * sequence, but also more than one vblank has passed.
1930                  *
1931                  * For the former case of modeswitching, it is possible
1932                  * to switch between two FBC valid configurations
1933                  * instantaneously so we do need to disable the FBC
1934                  * before we can modify its control registers. We also
1935                  * have to wait for the next vblank for that to take
1936                  * effect. However, since we delay enabling FBC we can
1937                  * assume that a vblank has passed since disabling and
1938                  * that we can safely alter the registers in the deferred
1939                  * callback.
1940                  *
1941                  * In the scenario that we go from a valid to invalid
1942                  * and then back to valid FBC configuration we have
1943                  * no strict enforcement that a vblank occurred since
1944                  * disabling the FBC. However, along all current pipe
1945                  * disabling paths we do need to wait for a vblank at
1946                  * some point. And we wait before enabling FBC anyway.
1947                  */
1948                 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949                 intel_disable_fbc(dev);
1950         }
1951
1952         intel_enable_fbc(crtc, 500);
1953         return;
1954
1955 out_disable:
1956         /* Multiple disables should be harmless */
1957         if (intel_fbc_enabled(dev)) {
1958                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1959                 intel_disable_fbc(dev);
1960         }
1961 }
1962
1963 int
1964 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1965                            struct drm_i915_gem_object *obj,
1966                            struct intel_ring_buffer *pipelined)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         u32 alignment;
1970         int ret;
1971
1972         switch (obj->tiling_mode) {
1973         case I915_TILING_NONE:
1974                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975                         alignment = 128 * 1024;
1976                 else if (INTEL_INFO(dev)->gen >= 4)
1977                         alignment = 4 * 1024;
1978                 else
1979                         alignment = 64 * 1024;
1980                 break;
1981         case I915_TILING_X:
1982                 /* pin() will align the object as required by fence */
1983                 alignment = 0;
1984                 break;
1985         case I915_TILING_Y:
1986                 /* FIXME: Is this true? */
1987                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988                 return -EINVAL;
1989         default:
1990                 BUG();
1991         }
1992
1993         dev_priv->mm.interruptible = false;
1994         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1995         if (ret)
1996                 goto err_interruptible;
1997
1998         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999          * fence, whereas 965+ only requires a fence if using
2000          * framebuffer compression.  For simplicity, we always install
2001          * a fence as the cost is not that onerous.
2002          */
2003         if (obj->tiling_mode != I915_TILING_NONE) {
2004                 ret = i915_gem_object_get_fence(obj, pipelined);
2005                 if (ret)
2006                         goto err_unpin;
2007         }
2008
2009         dev_priv->mm.interruptible = true;
2010         return 0;
2011
2012 err_unpin:
2013         i915_gem_object_unpin(obj);
2014 err_interruptible:
2015         dev_priv->mm.interruptible = true;
2016         return ret;
2017 }
2018
2019 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020                              int x, int y)
2021 {
2022         struct drm_device *dev = crtc->dev;
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025         struct intel_framebuffer *intel_fb;
2026         struct drm_i915_gem_object *obj;
2027         int plane = intel_crtc->plane;
2028         unsigned long Start, Offset;
2029         u32 dspcntr;
2030         u32 reg;
2031
2032         switch (plane) {
2033         case 0:
2034         case 1:
2035                 break;
2036         default:
2037                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038                 return -EINVAL;
2039         }
2040
2041         intel_fb = to_intel_framebuffer(fb);
2042         obj = intel_fb->obj;
2043
2044         reg = DSPCNTR(plane);
2045         dspcntr = I915_READ(reg);
2046         /* Mask out pixel format bits in case we change it */
2047         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048         switch (fb->bits_per_pixel) {
2049         case 8:
2050                 dspcntr |= DISPPLANE_8BPP;
2051                 break;
2052         case 16:
2053                 if (fb->depth == 15)
2054                         dspcntr |= DISPPLANE_15_16BPP;
2055                 else
2056                         dspcntr |= DISPPLANE_16BPP;
2057                 break;
2058         case 24:
2059         case 32:
2060                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061                 break;
2062         default:
2063                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2064                 return -EINVAL;
2065         }
2066         if (INTEL_INFO(dev)->gen >= 4) {
2067                 if (obj->tiling_mode != I915_TILING_NONE)
2068                         dspcntr |= DISPPLANE_TILED;
2069                 else
2070                         dspcntr &= ~DISPPLANE_TILED;
2071         }
2072
2073         I915_WRITE(reg, dspcntr);
2074
2075         Start = obj->gtt_offset;
2076         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
2078         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079                       Start, Offset, x, y, fb->pitch);
2080         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2081         if (INTEL_INFO(dev)->gen >= 4) {
2082                 I915_WRITE(DSPSURF(plane), Start);
2083                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084                 I915_WRITE(DSPADDR(plane), Offset);
2085         } else
2086                 I915_WRITE(DSPADDR(plane), Start + Offset);
2087         POSTING_READ(reg);
2088
2089         return 0;
2090 }
2091
2092 static int ironlake_update_plane(struct drm_crtc *crtc,
2093                                  struct drm_framebuffer *fb, int x, int y)
2094 {
2095         struct drm_device *dev = crtc->dev;
2096         struct drm_i915_private *dev_priv = dev->dev_private;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098         struct intel_framebuffer *intel_fb;
2099         struct drm_i915_gem_object *obj;
2100         int plane = intel_crtc->plane;
2101         unsigned long Start, Offset;
2102         u32 dspcntr;
2103         u32 reg;
2104
2105         switch (plane) {
2106         case 0:
2107         case 1:
2108         case 2:
2109                 break;
2110         default:
2111                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112                 return -EINVAL;
2113         }
2114
2115         intel_fb = to_intel_framebuffer(fb);
2116         obj = intel_fb->obj;
2117
2118         reg = DSPCNTR(plane);
2119         dspcntr = I915_READ(reg);
2120         /* Mask out pixel format bits in case we change it */
2121         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122         switch (fb->bits_per_pixel) {
2123         case 8:
2124                 dspcntr |= DISPPLANE_8BPP;
2125                 break;
2126         case 16:
2127                 if (fb->depth != 16)
2128                         return -EINVAL;
2129
2130                 dspcntr |= DISPPLANE_16BPP;
2131                 break;
2132         case 24:
2133         case 32:
2134                 if (fb->depth == 24)
2135                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136                 else if (fb->depth == 30)
2137                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138                 else
2139                         return -EINVAL;
2140                 break;
2141         default:
2142                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143                 return -EINVAL;
2144         }
2145
2146         if (obj->tiling_mode != I915_TILING_NONE)
2147                 dspcntr |= DISPPLANE_TILED;
2148         else
2149                 dspcntr &= ~DISPPLANE_TILED;
2150
2151         /* must disable */
2152         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154         I915_WRITE(reg, dspcntr);
2155
2156         Start = obj->gtt_offset;
2157         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160                       Start, Offset, x, y, fb->pitch);
2161         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162         I915_WRITE(DSPSURF(plane), Start);
2163         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164         I915_WRITE(DSPADDR(plane), Offset);
2165         POSTING_READ(reg);
2166
2167         return 0;
2168 }
2169
2170 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 static int
2172 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173                            int x, int y, enum mode_set_atomic state)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         int ret;
2178
2179         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180         if (ret)
2181                 return ret;
2182
2183         intel_update_fbc(dev);
2184         intel_increase_pllclock(crtc);
2185
2186         return 0;
2187 }
2188
2189 static int
2190 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191                     struct drm_framebuffer *old_fb)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_master_private *master_priv;
2195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2196         int ret;
2197
2198         /* no fb bound */
2199         if (!crtc->fb) {
2200                 DRM_ERROR("No FB bound\n");
2201                 return 0;
2202         }
2203
2204         switch (intel_crtc->plane) {
2205         case 0:
2206         case 1:
2207                 break;
2208         case 2:
2209                 if (IS_IVYBRIDGE(dev))
2210                         break;
2211                 /* fall through otherwise */
2212         default:
2213                 DRM_ERROR("no plane for crtc\n");
2214                 return -EINVAL;
2215         }
2216
2217         mutex_lock(&dev->struct_mutex);
2218         ret = intel_pin_and_fence_fb_obj(dev,
2219                                          to_intel_framebuffer(crtc->fb)->obj,
2220                                          NULL);
2221         if (ret != 0) {
2222                 mutex_unlock(&dev->struct_mutex);
2223                 DRM_ERROR("pin & fence failed\n");
2224                 return ret;
2225         }
2226
2227         if (old_fb) {
2228                 struct drm_i915_private *dev_priv = dev->dev_private;
2229                 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2230
2231                 wait_event(dev_priv->pending_flip_queue,
2232                            atomic_read(&dev_priv->mm.wedged) ||
2233                            atomic_read(&obj->pending_flip) == 0);
2234
2235                 /* Big Hammer, we also need to ensure that any pending
2236                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237                  * current scanout is retired before unpinning the old
2238                  * framebuffer.
2239                  *
2240                  * This should only fail upon a hung GPU, in which case we
2241                  * can safely continue.
2242                  */
2243                 ret = i915_gem_object_finish_gpu(obj);
2244                 (void) ret;
2245         }
2246
2247         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248                                          LEAVE_ATOMIC_MODE_SET);
2249         if (ret) {
2250                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2251                 mutex_unlock(&dev->struct_mutex);
2252                 DRM_ERROR("failed to update base address\n");
2253                 return ret;
2254         }
2255
2256         if (old_fb) {
2257                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2258                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2259         }
2260
2261         mutex_unlock(&dev->struct_mutex);
2262
2263         if (!dev->primary->master)
2264                 return 0;
2265
2266         master_priv = dev->primary->master->driver_priv;
2267         if (!master_priv->sarea_priv)
2268                 return 0;
2269
2270         if (intel_crtc->pipe) {
2271                 master_priv->sarea_priv->pipeB_x = x;
2272                 master_priv->sarea_priv->pipeB_y = y;
2273         } else {
2274                 master_priv->sarea_priv->pipeA_x = x;
2275                 master_priv->sarea_priv->pipeA_y = y;
2276         }
2277
2278         return 0;
2279 }
2280
2281 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2282 {
2283         struct drm_device *dev = crtc->dev;
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         u32 dpa_ctl;
2286
2287         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2288         dpa_ctl = I915_READ(DP_A);
2289         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291         if (clock < 200000) {
2292                 u32 temp;
2293                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294                 /* workaround for 160Mhz:
2295                    1) program 0x4600c bits 15:0 = 0x8124
2296                    2) program 0x46010 bit 0 = 1
2297                    3) program 0x46034 bit 24 = 1
2298                    4) program 0x64000 bit 14 = 1
2299                    */
2300                 temp = I915_READ(0x4600c);
2301                 temp &= 0xffff0000;
2302                 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304                 temp = I915_READ(0x46010);
2305                 I915_WRITE(0x46010, temp | 1);
2306
2307                 temp = I915_READ(0x46034);
2308                 I915_WRITE(0x46034, temp | (1 << 24));
2309         } else {
2310                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311         }
2312         I915_WRITE(DP_A, dpa_ctl);
2313
2314         POSTING_READ(DP_A);
2315         udelay(500);
2316 }
2317
2318 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         u32 reg, temp;
2325
2326         /* enable normal train */
2327         reg = FDI_TX_CTL(pipe);
2328         temp = I915_READ(reg);
2329         if (IS_IVYBRIDGE(dev)) {
2330                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2332         } else {
2333                 temp &= ~FDI_LINK_TRAIN_NONE;
2334                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2335         }
2336         I915_WRITE(reg, temp);
2337
2338         reg = FDI_RX_CTL(pipe);
2339         temp = I915_READ(reg);
2340         if (HAS_PCH_CPT(dev)) {
2341                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343         } else {
2344                 temp &= ~FDI_LINK_TRAIN_NONE;
2345                 temp |= FDI_LINK_TRAIN_NONE;
2346         }
2347         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349         /* wait one idle pattern time */
2350         POSTING_READ(reg);
2351         udelay(1000);
2352
2353         /* IVB wants error correction enabled */
2354         if (IS_IVYBRIDGE(dev))
2355                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356                            FDI_FE_ERRC_ENABLE);
2357 }
2358
2359 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360 {
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364         flags |= FDI_PHASE_SYNC_OVR(pipe);
2365         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366         flags |= FDI_PHASE_SYNC_EN(pipe);
2367         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368         POSTING_READ(SOUTH_CHICKEN1);
2369 }
2370
2371 /* The FDI link training functions for ILK/Ibexpeak. */
2372 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373 {
2374         struct drm_device *dev = crtc->dev;
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377         int pipe = intel_crtc->pipe;
2378         int plane = intel_crtc->plane;
2379         u32 reg, temp, tries;
2380
2381         /* FDI needs bits from pipe & plane first */
2382         assert_pipe_enabled(dev_priv, pipe);
2383         assert_plane_enabled(dev_priv, plane);
2384
2385         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386            for train result */
2387         reg = FDI_RX_IMR(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_RX_SYMBOL_LOCK;
2390         temp &= ~FDI_RX_BIT_LOCK;
2391         I915_WRITE(reg, temp);
2392         I915_READ(reg);
2393         udelay(150);
2394
2395         /* enable CPU FDI TX and PCH FDI RX */
2396         reg = FDI_TX_CTL(pipe);
2397         temp = I915_READ(reg);
2398         temp &= ~(7 << 19);
2399         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2400         temp &= ~FDI_LINK_TRAIN_NONE;
2401         temp |= FDI_LINK_TRAIN_PATTERN_1;
2402         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2403
2404         reg = FDI_RX_CTL(pipe);
2405         temp = I915_READ(reg);
2406         temp &= ~FDI_LINK_TRAIN_NONE;
2407         temp |= FDI_LINK_TRAIN_PATTERN_1;
2408         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410         POSTING_READ(reg);
2411         udelay(150);
2412
2413         /* Ironlake workaround, enable clock pointer after FDI enable*/
2414         if (HAS_PCH_IBX(dev)) {
2415                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417                            FDI_RX_PHASE_SYNC_POINTER_EN);
2418         }
2419
2420         reg = FDI_RX_IIR(pipe);
2421         for (tries = 0; tries < 5; tries++) {
2422                 temp = I915_READ(reg);
2423                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425                 if ((temp & FDI_RX_BIT_LOCK)) {
2426                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2427                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2428                         break;
2429                 }
2430         }
2431         if (tries == 5)
2432                 DRM_ERROR("FDI train 1 fail!\n");
2433
2434         /* Train 2 */
2435         reg = FDI_TX_CTL(pipe);
2436         temp = I915_READ(reg);
2437         temp &= ~FDI_LINK_TRAIN_NONE;
2438         temp |= FDI_LINK_TRAIN_PATTERN_2;
2439         I915_WRITE(reg, temp);
2440
2441         reg = FDI_RX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_LINK_TRAIN_NONE;
2444         temp |= FDI_LINK_TRAIN_PATTERN_2;
2445         I915_WRITE(reg, temp);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if (temp & FDI_RX_SYMBOL_LOCK) {
2456                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2457                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 2 fail!\n");
2463
2464         DRM_DEBUG_KMS("FDI train done\n");
2465
2466 }
2467
2468 static const int snb_b_fdi_train_param[] = {
2469         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473 };
2474
2475 /* The FDI link training functions for SNB/Cougarpoint. */
2476 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477 {
2478         struct drm_device *dev = crtc->dev;
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481         int pipe = intel_crtc->pipe;
2482         u32 reg, temp, i;
2483
2484         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485            for train result */
2486         reg = FDI_RX_IMR(pipe);
2487         temp = I915_READ(reg);
2488         temp &= ~FDI_RX_SYMBOL_LOCK;
2489         temp &= ~FDI_RX_BIT_LOCK;
2490         I915_WRITE(reg, temp);
2491
2492         POSTING_READ(reg);
2493         udelay(150);
2494
2495         /* enable CPU FDI TX and PCH FDI RX */
2496         reg = FDI_TX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         temp &= ~(7 << 19);
2499         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503         /* SNB-B */
2504         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2506
2507         reg = FDI_RX_CTL(pipe);
2508         temp = I915_READ(reg);
2509         if (HAS_PCH_CPT(dev)) {
2510                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512         } else {
2513                 temp &= ~FDI_LINK_TRAIN_NONE;
2514                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515         }
2516         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518         POSTING_READ(reg);
2519         udelay(150);
2520
2521         if (HAS_PCH_CPT(dev))
2522                 cpt_phase_pointer_enable(dev, pipe);
2523
2524         for (i = 0; i < 4; i++) {
2525                 reg = FDI_TX_CTL(pipe);
2526                 temp = I915_READ(reg);
2527                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528                 temp |= snb_b_fdi_train_param[i];
2529                 I915_WRITE(reg, temp);
2530
2531                 POSTING_READ(reg);
2532                 udelay(500);
2533
2534                 reg = FDI_RX_IIR(pipe);
2535                 temp = I915_READ(reg);
2536                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538                 if (temp & FDI_RX_BIT_LOCK) {
2539                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2540                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2541                         break;
2542                 }
2543         }
2544         if (i == 4)
2545                 DRM_ERROR("FDI train 1 fail!\n");
2546
2547         /* Train 2 */
2548         reg = FDI_TX_CTL(pipe);
2549         temp = I915_READ(reg);
2550         temp &= ~FDI_LINK_TRAIN_NONE;
2551         temp |= FDI_LINK_TRAIN_PATTERN_2;
2552         if (IS_GEN6(dev)) {
2553                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554                 /* SNB-B */
2555                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556         }
2557         I915_WRITE(reg, temp);
2558
2559         reg = FDI_RX_CTL(pipe);
2560         temp = I915_READ(reg);
2561         if (HAS_PCH_CPT(dev)) {
2562                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564         } else {
2565                 temp &= ~FDI_LINK_TRAIN_NONE;
2566                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567         }
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         for (i = 0; i < 4; i++) {
2574                 reg = FDI_TX_CTL(pipe);
2575                 temp = I915_READ(reg);
2576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577                 temp |= snb_b_fdi_train_param[i];
2578                 I915_WRITE(reg, temp);
2579
2580                 POSTING_READ(reg);
2581                 udelay(500);
2582
2583                 reg = FDI_RX_IIR(pipe);
2584                 temp = I915_READ(reg);
2585                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587                 if (temp & FDI_RX_SYMBOL_LOCK) {
2588                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2589                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2590                         break;
2591                 }
2592         }
2593         if (i == 4)
2594                 DRM_ERROR("FDI train 2 fail!\n");
2595
2596         DRM_DEBUG_KMS("FDI train done.\n");
2597 }
2598
2599 /* Manual link training for Ivy Bridge A0 parts */
2600 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601 {
2602         struct drm_device *dev = crtc->dev;
2603         struct drm_i915_private *dev_priv = dev->dev_private;
2604         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605         int pipe = intel_crtc->pipe;
2606         u32 reg, temp, i;
2607
2608         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609            for train result */
2610         reg = FDI_RX_IMR(pipe);
2611         temp = I915_READ(reg);
2612         temp &= ~FDI_RX_SYMBOL_LOCK;
2613         temp &= ~FDI_RX_BIT_LOCK;
2614         I915_WRITE(reg, temp);
2615
2616         POSTING_READ(reg);
2617         udelay(150);
2618
2619         /* enable CPU FDI TX and PCH FDI RX */
2620         reg = FDI_TX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~(7 << 19);
2623         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628         temp |= FDI_COMPOSITE_SYNC;
2629         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_AUTO;
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636         temp |= FDI_COMPOSITE_SYNC;
2637         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639         POSTING_READ(reg);
2640         udelay(150);
2641
2642         if (HAS_PCH_CPT(dev))
2643                 cpt_phase_pointer_enable(dev, pipe);
2644
2645         for (i = 0; i < 4; i++) {
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 temp |= snb_b_fdi_train_param[i];
2650                 I915_WRITE(reg, temp);
2651
2652                 POSTING_READ(reg);
2653                 udelay(500);
2654
2655                 reg = FDI_RX_IIR(pipe);
2656                 temp = I915_READ(reg);
2657                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659                 if (temp & FDI_RX_BIT_LOCK ||
2660                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2663                         break;
2664                 }
2665         }
2666         if (i == 4)
2667                 DRM_ERROR("FDI train 1 fail!\n");
2668
2669         /* Train 2 */
2670         reg = FDI_TX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676         I915_WRITE(reg, temp);
2677
2678         reg = FDI_RX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682         I915_WRITE(reg, temp);
2683
2684         POSTING_READ(reg);
2685         udelay(150);
2686
2687         for (i = 0; i < 4; i++) {
2688                 reg = FDI_TX_CTL(pipe);
2689                 temp = I915_READ(reg);
2690                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691                 temp |= snb_b_fdi_train_param[i];
2692                 I915_WRITE(reg, temp);
2693
2694                 POSTING_READ(reg);
2695                 udelay(500);
2696
2697                 reg = FDI_RX_IIR(pipe);
2698                 temp = I915_READ(reg);
2699                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701                 if (temp & FDI_RX_SYMBOL_LOCK) {
2702                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2704                         break;
2705                 }
2706         }
2707         if (i == 4)
2708                 DRM_ERROR("FDI train 2 fail!\n");
2709
2710         DRM_DEBUG_KMS("FDI train done.\n");
2711 }
2712
2713 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2714 {
2715         struct drm_device *dev = crtc->dev;
2716         struct drm_i915_private *dev_priv = dev->dev_private;
2717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718         int pipe = intel_crtc->pipe;
2719         u32 reg, temp;
2720
2721         /* Write the TU size bits so error detection works */
2722         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2724
2725         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2726         reg = FDI_RX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         temp &= ~((0x7 << 19) | (0x7 << 16));
2729         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2730         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733         POSTING_READ(reg);
2734         udelay(200);
2735
2736         /* Switch from Rawclk to PCDclk */
2737         temp = I915_READ(reg);
2738         I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740         POSTING_READ(reg);
2741         udelay(200);
2742
2743         /* Enable CPU FDI TX PLL, always on for Ironlake */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749                 POSTING_READ(reg);
2750                 udelay(100);
2751         }
2752 }
2753
2754 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755 {
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763         POSTING_READ(SOUTH_CHICKEN1);
2764 }
2765 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766 {
2767         struct drm_device *dev = crtc->dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770         int pipe = intel_crtc->pipe;
2771         u32 reg, temp;
2772
2773         /* disable CPU FDI tx and PCH FDI rx */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777         POSTING_READ(reg);
2778
2779         reg = FDI_RX_CTL(pipe);
2780         temp = I915_READ(reg);
2781         temp &= ~(0x7 << 16);
2782         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785         POSTING_READ(reg);
2786         udelay(100);
2787
2788         /* Ironlake workaround, disable clock pointer after downing FDI */
2789         if (HAS_PCH_IBX(dev)) {
2790                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2791                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792                            I915_READ(FDI_RX_CHICKEN(pipe) &
2793                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2794         } else if (HAS_PCH_CPT(dev)) {
2795                 cpt_phase_pointer_disable(dev, pipe);
2796         }
2797
2798         /* still set train pattern 1 */
2799         reg = FDI_TX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         temp &= ~FDI_LINK_TRAIN_NONE;
2802         temp |= FDI_LINK_TRAIN_PATTERN_1;
2803         I915_WRITE(reg, temp);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         if (HAS_PCH_CPT(dev)) {
2808                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810         } else {
2811                 temp &= ~FDI_LINK_TRAIN_NONE;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813         }
2814         /* BPC in FDI rx is consistent with that in PIPECONF */
2815         temp &= ~(0x07 << 16);
2816         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817         I915_WRITE(reg, temp);
2818
2819         POSTING_READ(reg);
2820         udelay(100);
2821 }
2822
2823 /*
2824  * When we disable a pipe, we need to clear any pending scanline wait events
2825  * to avoid hanging the ring, which we assume we are waiting on.
2826  */
2827 static void intel_clear_scanline_wait(struct drm_device *dev)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_ring_buffer *ring;
2831         u32 tmp;
2832
2833         if (IS_GEN2(dev))
2834                 /* Can't break the hang on i8xx */
2835                 return;
2836
2837         ring = LP_RING(dev_priv);
2838         tmp = I915_READ_CTL(ring);
2839         if (tmp & RING_WAIT)
2840                 I915_WRITE_CTL(ring, tmp);
2841 }
2842
2843 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844 {
2845         struct drm_i915_gem_object *obj;
2846         struct drm_i915_private *dev_priv;
2847
2848         if (crtc->fb == NULL)
2849                 return;
2850
2851         obj = to_intel_framebuffer(crtc->fb)->obj;
2852         dev_priv = crtc->dev->dev_private;
2853         wait_event(dev_priv->pending_flip_queue,
2854                    atomic_read(&obj->pending_flip) == 0);
2855 }
2856
2857 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858 {
2859         struct drm_device *dev = crtc->dev;
2860         struct drm_mode_config *mode_config = &dev->mode_config;
2861         struct intel_encoder *encoder;
2862
2863         /*
2864          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865          * must be driven by its own crtc; no sharing is possible.
2866          */
2867         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868                 if (encoder->base.crtc != crtc)
2869                         continue;
2870
2871                 switch (encoder->type) {
2872                 case INTEL_OUTPUT_EDP:
2873                         if (!intel_encoder_is_pch_edp(&encoder->base))
2874                                 return false;
2875                         continue;
2876                 }
2877         }
2878
2879         return true;
2880 }
2881
2882 /*
2883  * Enable PCH resources required for PCH ports:
2884  *   - PCH PLLs
2885  *   - FDI training & RX/TX
2886  *   - update transcoder timings
2887  *   - DP transcoding bits
2888  *   - transcoder
2889  */
2890 static void ironlake_pch_enable(struct drm_crtc *crtc)
2891 {
2892         struct drm_device *dev = crtc->dev;
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895         int pipe = intel_crtc->pipe;
2896         u32 reg, temp, transc_sel;
2897
2898         /* For PCH output, training FDI link */
2899         dev_priv->display.fdi_link_train(crtc);
2900
2901         intel_enable_pch_pll(dev_priv, pipe);
2902
2903         if (HAS_PCH_CPT(dev)) {
2904                 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2905                         TRANSC_DPLLB_SEL;
2906
2907                 /* Be sure PCH DPLL SEL is set */
2908                 temp = I915_READ(PCH_DPLL_SEL);
2909                 if (pipe == 0) {
2910                         temp &= ~(TRANSA_DPLLB_SEL);
2911                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2912                 } else if (pipe == 1) {
2913                         temp &= ~(TRANSB_DPLLB_SEL);
2914                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2915                 } else if (pipe == 2) {
2916                         temp &= ~(TRANSC_DPLLB_SEL);
2917                         temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2918                 }
2919                 I915_WRITE(PCH_DPLL_SEL, temp);
2920         }
2921
2922         /* set transcoder timing, panel must allow it */
2923         assert_panel_unlocked(dev_priv, pipe);
2924         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2925         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2926         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2927
2928         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2929         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2930         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2931
2932         intel_fdi_normal_train(crtc);
2933
2934         /* For PCH DP, enable TRANS_DP_CTL */
2935         if (HAS_PCH_CPT(dev) &&
2936             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2937              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2938                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2939                 reg = TRANS_DP_CTL(pipe);
2940                 temp = I915_READ(reg);
2941                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2942                           TRANS_DP_SYNC_MASK |
2943                           TRANS_DP_BPC_MASK);
2944                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2945                          TRANS_DP_ENH_FRAMING);
2946                 temp |= bpc << 9; /* same format but at 11:9 */
2947
2948                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2949                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2950                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2951                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2952
2953                 switch (intel_trans_dp_port_sel(crtc)) {
2954                 case PCH_DP_B:
2955                         temp |= TRANS_DP_PORT_SEL_B;
2956                         break;
2957                 case PCH_DP_C:
2958                         temp |= TRANS_DP_PORT_SEL_C;
2959                         break;
2960                 case PCH_DP_D:
2961                         temp |= TRANS_DP_PORT_SEL_D;
2962                         break;
2963                 default:
2964                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2965                         temp |= TRANS_DP_PORT_SEL_B;
2966                         break;
2967                 }
2968
2969                 I915_WRITE(reg, temp);
2970         }
2971
2972         intel_enable_transcoder(dev_priv, pipe);
2973 }
2974
2975 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2979         u32 temp;
2980
2981         temp = I915_READ(dslreg);
2982         udelay(500);
2983         if (wait_for(I915_READ(dslreg) != temp, 5)) {
2984                 /* Without this, mode sets may fail silently on FDI */
2985                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2986                 udelay(250);
2987                 I915_WRITE(tc2reg, 0);
2988                 if (wait_for(I915_READ(dslreg) != temp, 5))
2989                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2990         }
2991 }
2992
2993 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2994 {
2995         struct drm_device *dev = crtc->dev;
2996         struct drm_i915_private *dev_priv = dev->dev_private;
2997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998         int pipe = intel_crtc->pipe;
2999         int plane = intel_crtc->plane;
3000         u32 temp;
3001         bool is_pch_port;
3002
3003         if (intel_crtc->active)
3004                 return;
3005
3006         intel_crtc->active = true;
3007         intel_update_watermarks(dev);
3008
3009         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3010                 temp = I915_READ(PCH_LVDS);
3011                 if ((temp & LVDS_PORT_EN) == 0)
3012                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3013         }
3014
3015         is_pch_port = intel_crtc_driving_pch(crtc);
3016
3017         if (is_pch_port)
3018                 ironlake_fdi_pll_enable(crtc);
3019         else
3020                 ironlake_fdi_disable(crtc);
3021
3022         /* Enable panel fitting for LVDS */
3023         if (dev_priv->pch_pf_size &&
3024             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3025                 /* Force use of hard-coded filter coefficients
3026                  * as some pre-programmed values are broken,
3027                  * e.g. x201.
3028                  */
3029                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3030                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3031                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3032         }
3033
3034         /*
3035          * On ILK+ LUT must be loaded before the pipe is running but with
3036          * clocks enabled
3037          */
3038         intel_crtc_load_lut(crtc);
3039
3040         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3041         intel_enable_plane(dev_priv, plane, pipe);
3042
3043         if (is_pch_port)
3044                 ironlake_pch_enable(crtc);
3045
3046         mutex_lock(&dev->struct_mutex);
3047         intel_update_fbc(dev);
3048         mutex_unlock(&dev->struct_mutex);
3049
3050         intel_crtc_update_cursor(crtc, true);
3051 }
3052
3053 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3054 {
3055         struct drm_device *dev = crtc->dev;
3056         struct drm_i915_private *dev_priv = dev->dev_private;
3057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058         int pipe = intel_crtc->pipe;
3059         int plane = intel_crtc->plane;
3060         u32 reg, temp;
3061
3062         if (!intel_crtc->active)
3063                 return;
3064
3065         intel_crtc_wait_for_pending_flips(crtc);
3066         drm_vblank_off(dev, pipe);
3067         intel_crtc_update_cursor(crtc, false);
3068
3069         intel_disable_plane(dev_priv, plane, pipe);
3070
3071         if (dev_priv->cfb_plane == plane)
3072                 intel_disable_fbc(dev);
3073
3074         intel_disable_pipe(dev_priv, pipe);
3075
3076         /* Disable PF */
3077         I915_WRITE(PF_CTL(pipe), 0);
3078         I915_WRITE(PF_WIN_SZ(pipe), 0);
3079
3080         ironlake_fdi_disable(crtc);
3081
3082         /* This is a horrible layering violation; we should be doing this in
3083          * the connector/encoder ->prepare instead, but we don't always have
3084          * enough information there about the config to know whether it will
3085          * actually be necessary or just cause undesired flicker.
3086          */
3087         intel_disable_pch_ports(dev_priv, pipe);
3088
3089         intel_disable_transcoder(dev_priv, pipe);
3090
3091         if (HAS_PCH_CPT(dev)) {
3092                 /* disable TRANS_DP_CTL */
3093                 reg = TRANS_DP_CTL(pipe);
3094                 temp = I915_READ(reg);
3095                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3096                 temp |= TRANS_DP_PORT_SEL_NONE;
3097                 I915_WRITE(reg, temp);
3098
3099                 /* disable DPLL_SEL */
3100                 temp = I915_READ(PCH_DPLL_SEL);
3101                 switch (pipe) {
3102                 case 0:
3103                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3104                         break;
3105                 case 1:
3106                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3107                         break;
3108                 case 2:
3109                         /* C shares PLL A or B */
3110                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3111                         break;
3112                 default:
3113                         BUG(); /* wtf */
3114                 }
3115                 I915_WRITE(PCH_DPLL_SEL, temp);
3116         }
3117
3118         /* disable PCH DPLL */
3119         if (!intel_crtc->no_pll)
3120                 intel_disable_pch_pll(dev_priv, pipe);
3121
3122         /* Switch from PCDclk to Rawclk */
3123         reg = FDI_RX_CTL(pipe);
3124         temp = I915_READ(reg);
3125         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3126
3127         /* Disable CPU FDI TX PLL */
3128         reg = FDI_TX_CTL(pipe);
3129         temp = I915_READ(reg);
3130         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3131
3132         POSTING_READ(reg);
3133         udelay(100);
3134
3135         reg = FDI_RX_CTL(pipe);
3136         temp = I915_READ(reg);
3137         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3138
3139         /* Wait for the clocks to turn off. */
3140         POSTING_READ(reg);
3141         udelay(100);
3142
3143         intel_crtc->active = false;
3144         intel_update_watermarks(dev);
3145
3146         mutex_lock(&dev->struct_mutex);
3147         intel_update_fbc(dev);
3148         intel_clear_scanline_wait(dev);
3149         mutex_unlock(&dev->struct_mutex);
3150 }
3151
3152 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3153 {
3154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3155         int pipe = intel_crtc->pipe;
3156         int plane = intel_crtc->plane;
3157
3158         /* XXX: When our outputs are all unaware of DPMS modes other than off
3159          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3160          */
3161         switch (mode) {
3162         case DRM_MODE_DPMS_ON:
3163         case DRM_MODE_DPMS_STANDBY:
3164         case DRM_MODE_DPMS_SUSPEND:
3165                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3166                 ironlake_crtc_enable(crtc);
3167                 break;
3168
3169         case DRM_MODE_DPMS_OFF:
3170                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3171                 ironlake_crtc_disable(crtc);
3172                 break;
3173         }
3174 }
3175
3176 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3177 {
3178         if (!enable && intel_crtc->overlay) {
3179                 struct drm_device *dev = intel_crtc->base.dev;
3180                 struct drm_i915_private *dev_priv = dev->dev_private;
3181
3182                 mutex_lock(&dev->struct_mutex);
3183                 dev_priv->mm.interruptible = false;
3184                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3185                 dev_priv->mm.interruptible = true;
3186                 mutex_unlock(&dev->struct_mutex);
3187         }
3188
3189         /* Let userspace switch the overlay on again. In most cases userspace
3190          * has to recompute where to put it anyway.
3191          */
3192 }
3193
3194 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3195 {
3196         struct drm_device *dev = crtc->dev;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3199         int pipe = intel_crtc->pipe;
3200         int plane = intel_crtc->plane;
3201
3202         if (intel_crtc->active)
3203                 return;
3204
3205         intel_crtc->active = true;
3206         intel_update_watermarks(dev);
3207
3208         intel_enable_pll(dev_priv, pipe);
3209         intel_enable_pipe(dev_priv, pipe, false);
3210         intel_enable_plane(dev_priv, plane, pipe);
3211
3212         intel_crtc_load_lut(crtc);
3213         intel_update_fbc(dev);
3214
3215         /* Give the overlay scaler a chance to enable if it's on this pipe */
3216         intel_crtc_dpms_overlay(intel_crtc, true);
3217         intel_crtc_update_cursor(crtc, true);
3218 }
3219
3220 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3221 {
3222         struct drm_device *dev = crtc->dev;
3223         struct drm_i915_private *dev_priv = dev->dev_private;
3224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3225         int pipe = intel_crtc->pipe;
3226         int plane = intel_crtc->plane;
3227
3228         if (!intel_crtc->active)
3229                 return;
3230
3231         /* Give the overlay scaler a chance to disable if it's on this pipe */
3232         intel_crtc_wait_for_pending_flips(crtc);
3233         drm_vblank_off(dev, pipe);
3234         intel_crtc_dpms_overlay(intel_crtc, false);
3235         intel_crtc_update_cursor(crtc, false);
3236
3237         if (dev_priv->cfb_plane == plane)
3238                 intel_disable_fbc(dev);
3239
3240         intel_disable_plane(dev_priv, plane, pipe);
3241         intel_disable_pipe(dev_priv, pipe);
3242         intel_disable_pll(dev_priv, pipe);
3243
3244         intel_crtc->active = false;
3245         intel_update_fbc(dev);
3246         intel_update_watermarks(dev);
3247         intel_clear_scanline_wait(dev);
3248 }
3249
3250 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3251 {
3252         /* XXX: When our outputs are all unaware of DPMS modes other than off
3253          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3254          */
3255         switch (mode) {
3256         case DRM_MODE_DPMS_ON:
3257         case DRM_MODE_DPMS_STANDBY:
3258         case DRM_MODE_DPMS_SUSPEND:
3259                 i9xx_crtc_enable(crtc);
3260                 break;
3261         case DRM_MODE_DPMS_OFF:
3262                 i9xx_crtc_disable(crtc);
3263                 break;
3264         }
3265 }
3266
3267 /**
3268  * Sets the power management mode of the pipe and plane.
3269  */
3270 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3271 {
3272         struct drm_device *dev = crtc->dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274         struct drm_i915_master_private *master_priv;
3275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276         int pipe = intel_crtc->pipe;
3277         bool enabled;
3278
3279         if (intel_crtc->dpms_mode == mode)
3280                 return;
3281
3282         intel_crtc->dpms_mode = mode;
3283
3284         dev_priv->display.dpms(crtc, mode);
3285
3286         if (!dev->primary->master)
3287                 return;
3288
3289         master_priv = dev->primary->master->driver_priv;
3290         if (!master_priv->sarea_priv)
3291                 return;
3292
3293         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3294
3295         switch (pipe) {
3296         case 0:
3297                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3298                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3299                 break;
3300         case 1:
3301                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3302                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3303                 break;
3304         default:
3305                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3306                 break;
3307         }
3308 }
3309
3310 static void intel_crtc_disable(struct drm_crtc *crtc)
3311 {
3312         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3313         struct drm_device *dev = crtc->dev;
3314
3315         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3316
3317         if (crtc->fb) {
3318                 mutex_lock(&dev->struct_mutex);
3319                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3320                 mutex_unlock(&dev->struct_mutex);
3321         }
3322 }
3323
3324 /* Prepare for a mode set.
3325  *
3326  * Note we could be a lot smarter here.  We need to figure out which outputs
3327  * will be enabled, which disabled (in short, how the config will changes)
3328  * and perform the minimum necessary steps to accomplish that, e.g. updating
3329  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3330  * panel fitting is in the proper state, etc.
3331  */
3332 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3333 {
3334         i9xx_crtc_disable(crtc);
3335 }
3336
3337 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3338 {
3339         i9xx_crtc_enable(crtc);
3340 }
3341
3342 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3343 {
3344         ironlake_crtc_disable(crtc);
3345 }
3346
3347 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3348 {
3349         ironlake_crtc_enable(crtc);
3350 }
3351
3352 void intel_encoder_prepare(struct drm_encoder *encoder)
3353 {
3354         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3355         /* lvds has its own version of prepare see intel_lvds_prepare */
3356         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3357 }
3358
3359 void intel_encoder_commit(struct drm_encoder *encoder)
3360 {
3361         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3362         struct drm_device *dev = encoder->dev;
3363         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3364         struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3365
3366         /* lvds has its own version of commit see intel_lvds_commit */
3367         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3368
3369         if (HAS_PCH_CPT(dev))
3370                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3371 }
3372
3373 void intel_encoder_destroy(struct drm_encoder *encoder)
3374 {
3375         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3376
3377         drm_encoder_cleanup(encoder);
3378         kfree(intel_encoder);
3379 }
3380
3381 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3382                                   struct drm_display_mode *mode,
3383                                   struct drm_display_mode *adjusted_mode)
3384 {
3385         struct drm_device *dev = crtc->dev;
3386
3387         if (HAS_PCH_SPLIT(dev)) {
3388                 /* FDI link clock is fixed at 2.7G */
3389                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3390                         return false;
3391         }
3392
3393         /* XXX some encoders set the crtcinfo, others don't.
3394          * Obviously we need some form of conflict resolution here...
3395          */
3396         if (adjusted_mode->crtc_htotal == 0)
3397                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3398
3399         return true;
3400 }
3401
3402 static int i945_get_display_clock_speed(struct drm_device *dev)
3403 {
3404         return 400000;
3405 }
3406
3407 static int i915_get_display_clock_speed(struct drm_device *dev)
3408 {
3409         return 333000;
3410 }
3411
3412 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3413 {
3414         return 200000;
3415 }
3416
3417 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3418 {
3419         u16 gcfgc = 0;
3420
3421         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3422
3423         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3424                 return 133000;
3425         else {
3426                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3427                 case GC_DISPLAY_CLOCK_333_MHZ:
3428                         return 333000;
3429                 default:
3430                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3431                         return 190000;
3432                 }
3433         }
3434 }
3435
3436 static int i865_get_display_clock_speed(struct drm_device *dev)
3437 {
3438         return 266000;
3439 }
3440
3441 static int i855_get_display_clock_speed(struct drm_device *dev)
3442 {
3443         u16 hpllcc = 0;
3444         /* Assume that the hardware is in the high speed state.  This
3445          * should be the default.
3446          */
3447         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3448         case GC_CLOCK_133_200:
3449         case GC_CLOCK_100_200:
3450                 return 200000;
3451         case GC_CLOCK_166_250:
3452                 return 250000;
3453         case GC_CLOCK_100_133:
3454                 return 133000;
3455         }
3456
3457         /* Shouldn't happen */
3458         return 0;
3459 }
3460
3461 static int i830_get_display_clock_speed(struct drm_device *dev)
3462 {
3463         return 133000;
3464 }
3465
3466 struct fdi_m_n {
3467         u32        tu;
3468         u32        gmch_m;
3469         u32        gmch_n;
3470         u32        link_m;
3471         u32        link_n;
3472 };
3473
3474 static void
3475 fdi_reduce_ratio(u32 *num, u32 *den)
3476 {
3477         while (*num > 0xffffff || *den > 0xffffff) {
3478                 *num >>= 1;
3479                 *den >>= 1;
3480         }
3481 }
3482
3483 static void
3484 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3485                      int link_clock, struct fdi_m_n *m_n)
3486 {
3487         m_n->tu = 64; /* default size */
3488
3489         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3490         m_n->gmch_m = bits_per_pixel * pixel_clock;
3491         m_n->gmch_n = link_clock * nlanes * 8;
3492         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3493
3494         m_n->link_m = pixel_clock;
3495         m_n->link_n = link_clock;
3496         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3497 }
3498
3499
3500 struct intel_watermark_params {
3501         unsigned long fifo_size;
3502         unsigned long max_wm;
3503         unsigned long default_wm;
3504         unsigned long guard_size;
3505         unsigned long cacheline_size;
3506 };
3507
3508 /* Pineview has different values for various configs */
3509 static const struct intel_watermark_params pineview_display_wm = {
3510         PINEVIEW_DISPLAY_FIFO,
3511         PINEVIEW_MAX_WM,
3512         PINEVIEW_DFT_WM,
3513         PINEVIEW_GUARD_WM,
3514         PINEVIEW_FIFO_LINE_SIZE
3515 };
3516 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3517         PINEVIEW_DISPLAY_FIFO,
3518         PINEVIEW_MAX_WM,
3519         PINEVIEW_DFT_HPLLOFF_WM,
3520         PINEVIEW_GUARD_WM,
3521         PINEVIEW_FIFO_LINE_SIZE
3522 };
3523 static const struct intel_watermark_params pineview_cursor_wm = {
3524         PINEVIEW_CURSOR_FIFO,
3525         PINEVIEW_CURSOR_MAX_WM,
3526         PINEVIEW_CURSOR_DFT_WM,
3527         PINEVIEW_CURSOR_GUARD_WM,
3528         PINEVIEW_FIFO_LINE_SIZE,
3529 };
3530 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3531         PINEVIEW_CURSOR_FIFO,
3532         PINEVIEW_CURSOR_MAX_WM,
3533         PINEVIEW_CURSOR_DFT_WM,
3534         PINEVIEW_CURSOR_GUARD_WM,
3535         PINEVIEW_FIFO_LINE_SIZE
3536 };
3537 static const struct intel_watermark_params g4x_wm_info = {
3538         G4X_FIFO_SIZE,
3539         G4X_MAX_WM,
3540         G4X_MAX_WM,
3541         2,
3542         G4X_FIFO_LINE_SIZE,
3543 };
3544 static const struct intel_watermark_params g4x_cursor_wm_info = {
3545         I965_CURSOR_FIFO,
3546         I965_CURSOR_MAX_WM,
3547         I965_CURSOR_DFT_WM,
3548         2,
3549         G4X_FIFO_LINE_SIZE,
3550 };
3551 static const struct intel_watermark_params i965_cursor_wm_info = {
3552         I965_CURSOR_FIFO,
3553         I965_CURSOR_MAX_WM,
3554         I965_CURSOR_DFT_WM,
3555         2,
3556         I915_FIFO_LINE_SIZE,
3557 };
3558 static const struct intel_watermark_params i945_wm_info = {
3559         I945_FIFO_SIZE,
3560         I915_MAX_WM,
3561         1,
3562         2,
3563         I915_FIFO_LINE_SIZE
3564 };
3565 static const struct intel_watermark_params i915_wm_info = {
3566         I915_FIFO_SIZE,
3567         I915_MAX_WM,
3568         1,
3569         2,
3570         I915_FIFO_LINE_SIZE
3571 };
3572 static const struct intel_watermark_params i855_wm_info = {
3573         I855GM_FIFO_SIZE,
3574         I915_MAX_WM,
3575         1,
3576         2,
3577         I830_FIFO_LINE_SIZE
3578 };
3579 static const struct intel_watermark_params i830_wm_info = {
3580         I830_FIFO_SIZE,
3581         I915_MAX_WM,
3582         1,
3583         2,
3584         I830_FIFO_LINE_SIZE
3585 };
3586
3587 static const struct intel_watermark_params ironlake_display_wm_info = {
3588         ILK_DISPLAY_FIFO,
3589         ILK_DISPLAY_MAXWM,
3590         ILK_DISPLAY_DFTWM,
3591         2,
3592         ILK_FIFO_LINE_SIZE
3593 };
3594 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3595         ILK_CURSOR_FIFO,
3596         ILK_CURSOR_MAXWM,
3597         ILK_CURSOR_DFTWM,
3598         2,
3599         ILK_FIFO_LINE_SIZE
3600 };
3601 static const struct intel_watermark_params ironlake_display_srwm_info = {
3602         ILK_DISPLAY_SR_FIFO,
3603         ILK_DISPLAY_MAX_SRWM,
3604         ILK_DISPLAY_DFT_SRWM,
3605         2,
3606         ILK_FIFO_LINE_SIZE
3607 };
3608 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3609         ILK_CURSOR_SR_FIFO,
3610         ILK_CURSOR_MAX_SRWM,
3611         ILK_CURSOR_DFT_SRWM,
3612         2,
3613         ILK_FIFO_LINE_SIZE
3614 };
3615
3616 static const struct intel_watermark_params sandybridge_display_wm_info = {
3617         SNB_DISPLAY_FIFO,
3618         SNB_DISPLAY_MAXWM,
3619         SNB_DISPLAY_DFTWM,
3620         2,
3621         SNB_FIFO_LINE_SIZE
3622 };
3623 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3624         SNB_CURSOR_FIFO,
3625         SNB_CURSOR_MAXWM,
3626         SNB_CURSOR_DFTWM,
3627         2,
3628         SNB_FIFO_LINE_SIZE
3629 };
3630 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3631         SNB_DISPLAY_SR_FIFO,
3632         SNB_DISPLAY_MAX_SRWM,
3633         SNB_DISPLAY_DFT_SRWM,
3634         2,
3635         SNB_FIFO_LINE_SIZE
3636 };
3637 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3638         SNB_CURSOR_SR_FIFO,
3639         SNB_CURSOR_MAX_SRWM,
3640         SNB_CURSOR_DFT_SRWM,
3641         2,
3642         SNB_FIFO_LINE_SIZE
3643 };
3644
3645
3646 /**
3647  * intel_calculate_wm - calculate watermark level
3648  * @clock_in_khz: pixel clock
3649  * @wm: chip FIFO params
3650  * @pixel_size: display pixel size
3651  * @latency_ns: memory latency for the platform
3652  *
3653  * Calculate the watermark level (the level at which the display plane will
3654  * start fetching from memory again).  Each chip has a different display
3655  * FIFO size and allocation, so the caller needs to figure that out and pass
3656  * in the correct intel_watermark_params structure.
3657  *
3658  * As the pixel clock runs, the FIFO will be drained at a rate that depends
3659  * on the pixel size.  When it reaches the watermark level, it'll start
3660  * fetching FIFO line sized based chunks from memory until the FIFO fills
3661  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
3662  * will occur, and a display engine hang could result.
3663  */
3664 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3665                                         const struct intel_watermark_params *wm,
3666                                         int fifo_size,
3667                                         int pixel_size,
3668                                         unsigned long latency_ns)
3669 {
3670         long entries_required, wm_size;
3671
3672         /*
3673          * Note: we need to make sure we don't overflow for various clock &
3674          * latency values.
3675          * clocks go from a few thousand to several hundred thousand.
3676          * latency is usually a few thousand
3677          */
3678         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3679                 1000;
3680         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3681
3682         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3683
3684         wm_size = fifo_size - (entries_required + wm->guard_size);
3685
3686         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3687
3688         /* Don't promote wm_size to unsigned... */
3689         if (wm_size > (long)wm->max_wm)
3690                 wm_size = wm->max_wm;
3691         if (wm_size <= 0)
3692                 wm_size = wm->default_wm;
3693         return wm_size;
3694 }
3695
3696 struct cxsr_latency {
3697         int is_desktop;
3698         int is_ddr3;
3699         unsigned long fsb_freq;
3700         unsigned long mem_freq;
3701         unsigned long display_sr;
3702         unsigned long display_hpll_disable;
3703         unsigned long cursor_sr;
3704         unsigned long cursor_hpll_disable;
3705 };
3706
3707 static const struct cxsr_latency cxsr_latency_table[] = {
3708         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
3709         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
3710         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
3711         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
3712         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
3713
3714         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
3715         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
3716         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
3717         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
3718         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
3719
3720         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
3721         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
3722         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
3723         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
3724         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
3725
3726         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
3727         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
3728         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
3729         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
3730         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
3731
3732         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
3733         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
3734         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
3735         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
3736         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
3737
3738         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
3739         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
3740         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
3741         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
3742         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
3743 };
3744
3745 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3746                                                          int is_ddr3,
3747                                                          int fsb,
3748                                                          int mem)
3749 {
3750         const struct cxsr_latency *latency;
3751         int i;
3752
3753         if (fsb == 0 || mem == 0)
3754                 return NULL;
3755
3756         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3757                 latency = &cxsr_latency_table[i];
3758                 if (is_desktop == latency->is_desktop &&
3759                     is_ddr3 == latency->is_ddr3 &&
3760                     fsb == latency->fsb_freq && mem == latency->mem_freq)
3761                         return latency;
3762         }
3763
3764         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3765
3766         return NULL;
3767 }
3768
3769 static void pineview_disable_cxsr(struct drm_device *dev)
3770 {
3771         struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773         /* deactivate cxsr */
3774         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3775 }
3776
3777 /*
3778  * Latency for FIFO fetches is dependent on several factors:
3779  *   - memory configuration (speed, channels)
3780  *   - chipset
3781  *   - current MCH state
3782  * It can be fairly high in some situations, so here we assume a fairly
3783  * pessimal value.  It's a tradeoff between extra memory fetches (if we
3784  * set this value too high, the FIFO will fetch frequently to stay full)
3785  * and power consumption (set it too low to save power and we might see
3786  * FIFO underruns and display "flicker").
3787  *
3788  * A value of 5us seems to be a good balance; safe for very low end
3789  * platforms but not overly aggressive on lower latency configs.
3790  */
3791 static const int latency_ns = 5000;
3792
3793 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3794 {
3795         struct drm_i915_private *dev_priv = dev->dev_private;
3796         uint32_t dsparb = I915_READ(DSPARB);
3797         int size;
3798
3799         size = dsparb & 0x7f;
3800         if (plane)
3801                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3802
3803         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3804                       plane ? "B" : "A", size);
3805
3806         return size;
3807 }
3808
3809 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3810 {
3811         struct drm_i915_private *dev_priv = dev->dev_private;
3812         uint32_t dsparb = I915_READ(DSPARB);
3813         int size;
3814
3815         size = dsparb & 0x1ff;
3816         if (plane)
3817                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3818         size >>= 1; /* Convert to cachelines */
3819
3820         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3821                       plane ? "B" : "A", size);
3822
3823         return size;
3824 }
3825
3826 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3827 {
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         uint32_t dsparb = I915_READ(DSPARB);
3830         int size;
3831
3832         size = dsparb & 0x7f;
3833         size >>= 2; /* Convert to cachelines */
3834
3835         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3836                       plane ? "B" : "A",
3837                       size);
3838
3839         return size;
3840 }
3841
3842 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3843 {
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         uint32_t dsparb = I915_READ(DSPARB);
3846         int size;
3847
3848         size = dsparb & 0x7f;
3849         size >>= 1; /* Convert to cachelines */
3850
3851         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3852                       plane ? "B" : "A", size);
3853
3854         return size;
3855 }
3856
3857 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3858 {
3859         struct drm_crtc *crtc, *enabled = NULL;
3860
3861         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3862                 if (crtc->enabled && crtc->fb) {
3863                         if (enabled)
3864                                 return NULL;
3865                         enabled = crtc;
3866                 }
3867         }
3868
3869         return enabled;
3870 }
3871
3872 static void pineview_update_wm(struct drm_device *dev)
3873 {
3874         struct drm_i915_private *dev_priv = dev->dev_private;
3875         struct drm_crtc *crtc;
3876         const struct cxsr_latency *latency;
3877         u32 reg;
3878         unsigned long wm;
3879
3880         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3881                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3882         if (!latency) {
3883                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3884                 pineview_disable_cxsr(dev);
3885                 return;
3886         }
3887
3888         crtc = single_enabled_crtc(dev);
3889         if (crtc) {
3890                 int clock = crtc->mode.clock;
3891                 int pixel_size = crtc->fb->bits_per_pixel / 8;
3892
3893                 /* Display SR */
3894                 wm = intel_calculate_wm(clock, &pineview_display_wm,
3895                                         pineview_display_wm.fifo_size,
3896                                         pixel_size, latency->display_sr);
3897                 reg = I915_READ(DSPFW1);
3898                 reg &= ~DSPFW_SR_MASK;
3899                 reg |= wm << DSPFW_SR_SHIFT;
3900                 I915_WRITE(DSPFW1, reg);
3901                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3902
3903                 /* cursor SR */
3904                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3905                                         pineview_display_wm.fifo_size,
3906                                         pixel_size, latency->cursor_sr);
3907                 reg = I915_READ(DSPFW3);
3908                 reg &= ~DSPFW_CURSOR_SR_MASK;
3909                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3910                 I915_WRITE(DSPFW3, reg);
3911
3912                 /* Display HPLL off SR */
3913                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3914                                         pineview_display_hplloff_wm.fifo_size,
3915                                         pixel_size, latency->display_hpll_disable);
3916                 reg = I915_READ(DSPFW3);
3917                 reg &= ~DSPFW_HPLL_SR_MASK;
3918                 reg |= wm & DSPFW_HPLL_SR_MASK;
3919                 I915_WRITE(DSPFW3, reg);
3920
3921                 /* cursor HPLL off SR */
3922                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3923                                         pineview_display_hplloff_wm.fifo_size,
3924                                         pixel_size, latency->cursor_hpll_disable);
3925                 reg = I915_READ(DSPFW3);
3926                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3927                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3928                 I915_WRITE(DSPFW3, reg);
3929                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3930
3931                 /* activate cxsr */
3932                 I915_WRITE(DSPFW3,
3933                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3934                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3935         } else {
3936                 pineview_disable_cxsr(dev);
3937                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3938         }
3939 }
3940
3941 static bool g4x_compute_wm0(struct drm_device *dev,
3942                             int plane,
3943                             const struct intel_watermark_params *display,
3944                             int display_latency_ns,
3945                             const struct intel_watermark_params *cursor,
3946                             int cursor_latency_ns,
3947                             int *plane_wm,
3948                             int *cursor_wm)
3949 {
3950         struct drm_crtc *crtc;
3951         int htotal, hdisplay, clock, pixel_size;
3952         int line_time_us, line_count;
3953         int entries, tlb_miss;
3954
3955         crtc = intel_get_crtc_for_plane(dev, plane);
3956         if (crtc->fb == NULL || !crtc->enabled) {
3957                 *cursor_wm = cursor->guard_size;
3958                 *plane_wm = display->guard_size;
3959                 return false;
3960         }
3961
3962         htotal = crtc->mode.htotal;
3963         hdisplay = crtc->mode.hdisplay;
3964         clock = crtc->mode.clock;
3965         pixel_size = crtc->fb->bits_per_pixel / 8;
3966
3967         /* Use the small buffer method to calculate plane watermark */
3968         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3969         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3970         if (tlb_miss > 0)
3971                 entries += tlb_miss;
3972         entries = DIV_ROUND_UP(entries, display->cacheline_size);
3973         *plane_wm = entries + display->guard_size;
3974         if (*plane_wm > (int)display->max_wm)
3975                 *plane_wm = display->max_wm;
3976
3977         /* Use the large buffer method to calculate cursor watermark */
3978         line_time_us = ((htotal * 1000) / clock);
3979         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3980         entries = line_count * 64 * pixel_size;
3981         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3982         if (tlb_miss > 0)
3983                 entries += tlb_miss;
3984         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3985         *cursor_wm = entries + cursor->guard_size;
3986         if (*cursor_wm > (int)cursor->max_wm)
3987                 *cursor_wm = (int)cursor->max_wm;
3988
3989         return true;
3990 }
3991
3992 /*
3993  * Check the wm result.
3994  *
3995  * If any calculated watermark values is larger than the maximum value that
3996  * can be programmed into the associated watermark register, that watermark
3997  * must be disabled.
3998  */
3999 static bool g4x_check_srwm(struct drm_device *dev,
4000                            int display_wm, int cursor_wm,
4001                            const struct intel_watermark_params *display,
4002                            const struct intel_watermark_params *cursor)
4003 {
4004         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4005                       display_wm, cursor_wm);
4006
4007         if (display_wm > display->max_wm) {
4008                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4009                               display_wm, display->max_wm);
4010                 return false;
4011         }
4012
4013         if (cursor_wm > cursor->max_wm) {
4014                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4015                               cursor_wm, cursor->max_wm);
4016                 return false;
4017         }
4018
4019         if (!(display_wm || cursor_wm)) {
4020                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4021                 return false;
4022         }
4023
4024         return true;
4025 }
4026
4027 static bool g4x_compute_srwm(struct drm_device *dev,
4028                              int plane,
4029                              int latency_ns,
4030                              const struct intel_watermark_params *display,
4031                              const struct intel_watermark_params *cursor,
4032                              int *display_wm, int *cursor_wm)
4033 {
4034         struct drm_crtc *crtc;
4035         int hdisplay, htotal, pixel_size, clock;
4036         unsigned long line_time_us;
4037         int line_count, line_size;
4038         int small, large;
4039         int entries;
4040
4041         if (!latency_ns) {
4042                 *display_wm = *cursor_wm = 0;
4043                 return false;
4044         }
4045
4046         crtc = intel_get_crtc_for_plane(dev, plane);
4047         hdisplay = crtc->mode.hdisplay;
4048         htotal = crtc->mode.htotal;
4049         clock = crtc->mode.clock;
4050         pixel_size = crtc->fb->bits_per_pixel / 8;
4051
4052         line_time_us = (htotal * 1000) / clock;
4053         line_count = (latency_ns / line_time_us + 1000) / 1000;
4054         line_size = hdisplay * pixel_size;
4055
4056         /* Use the minimum of the small and large buffer method for primary */
4057         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4058         large = line_count * line_size;
4059
4060         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4061         *display_wm = entries + display->guard_size;
4062
4063         /* calculate the self-refresh watermark for display cursor */
4064         entries = line_count * pixel_size * 64;
4065         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4066         *cursor_wm = entries + cursor->guard_size;
4067
4068         return g4x_check_srwm(dev,
4069                               *display_wm, *cursor_wm,
4070                               display, cursor);
4071 }
4072
4073 #define single_plane_enabled(mask) is_power_of_2(mask)
4074
4075 static void g4x_update_wm(struct drm_device *dev)
4076 {
4077         static const int sr_latency_ns = 12000;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4080         int plane_sr, cursor_sr;
4081         unsigned int enabled = 0;
4082
4083         if (g4x_compute_wm0(dev, 0,
4084                             &g4x_wm_info, latency_ns,
4085                             &g4x_cursor_wm_info, latency_ns,
4086                             &planea_wm, &cursora_wm))
4087                 enabled |= 1;
4088
4089         if (g4x_compute_wm0(dev, 1,
4090                             &g4x_wm_info, latency_ns,
4091                             &g4x_cursor_wm_info, latency_ns,
4092                             &planeb_wm, &cursorb_wm))
4093                 enabled |= 2;
4094
4095         plane_sr = cursor_sr = 0;
4096         if (single_plane_enabled(enabled) &&
4097             g4x_compute_srwm(dev, ffs(enabled) - 1,
4098                              sr_latency_ns,
4099                              &g4x_wm_info,
4100                              &g4x_cursor_wm_info,
4101                              &plane_sr, &cursor_sr))
4102                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4103         else
4104                 I915_WRITE(FW_BLC_SELF,
4105                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4106
4107         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4108                       planea_wm, cursora_wm,
4109                       planeb_wm, cursorb_wm,
4110                       plane_sr, cursor_sr);
4111
4112         I915_WRITE(DSPFW1,
4113                    (plane_sr << DSPFW_SR_SHIFT) |
4114                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4115                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
4116                    planea_wm);
4117         I915_WRITE(DSPFW2,
4118                    (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4119                    (cursora_wm << DSPFW_CURSORA_SHIFT));
4120         /* HPLL off in SR has some issues on G4x... disable it */
4121         I915_WRITE(DSPFW3,
4122                    (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4123                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4124 }
4125
4126 static void i965_update_wm(struct drm_device *dev)
4127 {
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         struct drm_crtc *crtc;
4130         int srwm = 1;
4131         int cursor_sr = 16;
4132
4133         /* Calc sr entries for one plane configs */
4134         crtc = single_enabled_crtc(dev);
4135         if (crtc) {
4136                 /* self-refresh has much higher latency */
4137                 static const int sr_latency_ns = 12000;
4138                 int clock = crtc->mode.clock;
4139                 int htotal = crtc->mode.htotal;
4140                 int hdisplay = crtc->mode.hdisplay;
4141                 int pixel_size = crtc->fb->bits_per_pixel / 8;
4142                 unsigned long line_time_us;
4143                 int entries;
4144
4145                 line_time_us = ((htotal * 1000) / clock);
4146
4147                 /* Use ns/us then divide to preserve precision */
4148                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4149                         pixel_size * hdisplay;
4150                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4151                 srwm = I965_FIFO_SIZE - entries;
4152                 if (srwm < 0)
4153                         srwm = 1;
4154                 srwm &= 0x1ff;
4155                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4156                               entries, srwm);
4157
4158                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4159                         pixel_size * 64;
4160                 entries = DIV_ROUND_UP(entries,
4161                                           i965_cursor_wm_info.cacheline_size);
4162                 cursor_sr = i965_cursor_wm_info.fifo_size -
4163                         (entries + i965_cursor_wm_info.guard_size);
4164
4165                 if (cursor_sr > i965_cursor_wm_info.max_wm)
4166                         cursor_sr = i965_cursor_wm_info.max_wm;
4167
4168                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4169                               "cursor %d\n", srwm, cursor_sr);
4170
4171                 if (IS_CRESTLINE(dev))
4172                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4173         } else {
4174                 /* Turn off self refresh if both pipes are enabled */
4175                 if (IS_CRESTLINE(dev))
4176                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4177                                    & ~FW_BLC_SELF_EN);
4178         }
4179
4180         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4181                       srwm);
4182
4183         /* 965 has limitations... */
4184         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4185                    (8 << 16) | (8 << 8) | (8 << 0));
4186         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4187         /* update cursor SR watermark */
4188         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4189 }
4190
4191 static void i9xx_update_wm(struct drm_device *dev)
4192 {
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         const struct intel_watermark_params *wm_info;
4195         uint32_t fwater_lo;
4196         uint32_t fwater_hi;
4197         int cwm, srwm = 1;
4198         int fifo_size;
4199         int planea_wm, planeb_wm;
4200         struct drm_crtc *crtc, *enabled = NULL;
4201
4202         if (IS_I945GM(dev))
4203                 wm_info = &i945_wm_info;
4204         else if (!IS_GEN2(dev))
4205                 wm_info = &i915_wm_info;
4206         else
4207                 wm_info = &i855_wm_info;
4208
4209         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4210         crtc = intel_get_crtc_for_plane(dev, 0);
4211         if (crtc->enabled && crtc->fb) {
4212                 planea_wm = intel_calculate_wm(crtc->mode.clock,
4213                                                wm_info, fifo_size,
4214                                                crtc->fb->bits_per_pixel / 8,
4215                                                latency_ns);
4216                 enabled = crtc;
4217         } else
4218                 planea_wm = fifo_size - wm_info->guard_size;
4219
4220         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4221         crtc = intel_get_crtc_for_plane(dev, 1);
4222         if (crtc->enabled && crtc->fb) {
4223                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4224                                                wm_info, fifo_size,
4225                                                crtc->fb->bits_per_pixel / 8,
4226                                                latency_ns);
4227                 if (enabled == NULL)
4228                         enabled = crtc;
4229                 else
4230                         enabled = NULL;
4231         } else
4232                 planeb_wm = fifo_size - wm_info->guard_size;
4233
4234         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4235
4236         /*
4237          * Overlay gets an aggressive default since video jitter is bad.
4238          */
4239         cwm = 2;
4240
4241         /* Play safe and disable self-refresh before adjusting watermarks. */
4242         if (IS_I945G(dev) || IS_I945GM(dev))
4243                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4244         else if (IS_I915GM(dev))
4245                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4246
4247         /* Calc sr entries for one plane configs */
4248         if (HAS_FW_BLC(dev) && enabled) {
4249                 /* self-refresh has much higher latency */
4250                 static const int sr_latency_ns = 6000;
4251                 int clock = enabled->mode.clock;
4252                 int htotal = enabled->mode.htotal;
4253                 int hdisplay = enabled->mode.hdisplay;
4254                 int pixel_size = enabled->fb->bits_per_pixel / 8;
4255                 unsigned long line_time_us;
4256                 int entries;
4257
4258                 line_time_us = (htotal * 1000) / clock;
4259
4260                 /* Use ns/us then divide to preserve precision */
4261                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4262                         pixel_size * hdisplay;
4263                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4264                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4265                 srwm = wm_info->fifo_size - entries;
4266                 if (srwm < 0)
4267                         srwm = 1;
4268
4269                 if (IS_I945G(dev) || IS_I945GM(dev))
4270                         I915_WRITE(FW_BLC_SELF,
4271                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4272                 else if (IS_I915GM(dev))
4273                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4274         }
4275
4276         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4277                       planea_wm, planeb_wm, cwm, srwm);
4278
4279         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4280         fwater_hi = (cwm & 0x1f);
4281
4282         /* Set request length to 8 cachelines per fetch */
4283         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4284         fwater_hi = fwater_hi | (1 << 8);
4285
4286         I915_WRITE(FW_BLC, fwater_lo);
4287         I915_WRITE(FW_BLC2, fwater_hi);
4288
4289         if (HAS_FW_BLC(dev)) {
4290                 if (enabled) {
4291                         if (IS_I945G(dev) || IS_I945GM(dev))
4292                                 I915_WRITE(FW_BLC_SELF,
4293                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4294                         else if (IS_I915GM(dev))
4295                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4296                         DRM_DEBUG_KMS("memory self refresh enabled\n");
4297                 } else
4298                         DRM_DEBUG_KMS("memory self refresh disabled\n");
4299         }
4300 }
4301
4302 static void i830_update_wm(struct drm_device *dev)
4303 {
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         struct drm_crtc *crtc;
4306         uint32_t fwater_lo;
4307         int planea_wm;
4308
4309         crtc = single_enabled_crtc(dev);
4310         if (crtc == NULL)
4311                 return;
4312
4313         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4314                                        dev_priv->display.get_fifo_size(dev, 0),
4315                                        crtc->fb->bits_per_pixel / 8,
4316                                        latency_ns);
4317         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4318         fwater_lo |= (3<<8) | planea_wm;
4319
4320         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4321
4322         I915_WRITE(FW_BLC, fwater_lo);
4323 }
4324
4325 #define ILK_LP0_PLANE_LATENCY           700
4326 #define ILK_LP0_CURSOR_LATENCY          1300
4327
4328 /*
4329  * Check the wm result.
4330  *
4331  * If any calculated watermark values is larger than the maximum value that
4332  * can be programmed into the associated watermark register, that watermark
4333  * must be disabled.
4334  */
4335 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4336                                 int fbc_wm, int display_wm, int cursor_wm,
4337                                 const struct intel_watermark_params *display,
4338                                 const struct intel_watermark_params *cursor)
4339 {
4340         struct drm_i915_private *dev_priv = dev->dev_private;
4341
4342         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4343                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4344
4345         if (fbc_wm > SNB_FBC_MAX_SRWM) {
4346                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4347                               fbc_wm, SNB_FBC_MAX_SRWM, level);
4348
4349                 /* fbc has it's own way to disable FBC WM */
4350                 I915_WRITE(DISP_ARB_CTL,
4351                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4352                 return false;
4353         }
4354
4355         if (display_wm > display->max_wm) {
4356                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4357                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
4358                 return false;
4359         }
4360
4361         if (cursor_wm > cursor->max_wm) {
4362                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4363                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4364                 return false;
4365         }
4366
4367         if (!(fbc_wm || display_wm || cursor_wm)) {
4368                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4369                 return false;
4370         }
4371
4372         return true;
4373 }
4374
4375 /*
4376  * Compute watermark values of WM[1-3],
4377  */
4378 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4379                                   int latency_ns,
4380                                   const struct intel_watermark_params *display,
4381                                   const struct intel_watermark_params *cursor,
4382                                   int *fbc_wm, int *display_wm, int *cursor_wm)
4383 {
4384         struct drm_crtc *crtc;
4385         unsigned long line_time_us;
4386         int hdisplay, htotal, pixel_size, clock;
4387         int line_count, line_size;
4388         int small, large;
4389         int entries;
4390
4391         if (!latency_ns) {
4392                 *fbc_wm = *display_wm = *cursor_wm = 0;
4393                 return false;
4394         }
4395
4396         crtc = intel_get_crtc_for_plane(dev, plane);
4397         hdisplay = crtc->mode.hdisplay;
4398         htotal = crtc->mode.htotal;
4399         clock = crtc->mode.clock;
4400         pixel_size = crtc->fb->bits_per_pixel / 8;
4401
4402         line_time_us = (htotal * 1000) / clock;
4403         line_count = (latency_ns / line_time_us + 1000) / 1000;
4404         line_size = hdisplay * pixel_size;
4405
4406         /* Use the minimum of the small and large buffer method for primary */
4407         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4408         large = line_count * line_size;
4409
4410         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4411         *display_wm = entries + display->guard_size;
4412
4413         /*
4414          * Spec says:
4415          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4416          */
4417         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4418
4419         /* calculate the self-refresh watermark for display cursor */
4420         entries = line_count * pixel_size * 64;
4421         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4422         *cursor_wm = entries + cursor->guard_size;
4423
4424         return ironlake_check_srwm(dev, level,
4425                                    *fbc_wm, *display_wm, *cursor_wm,
4426                                    display, cursor);
4427 }
4428
4429 static void ironlake_update_wm(struct drm_device *dev)
4430 {
4431         struct drm_i915_private *dev_priv = dev->dev_private;
4432         int fbc_wm, plane_wm, cursor_wm;
4433         unsigned int enabled;
4434
4435         enabled = 0;
4436         if (g4x_compute_wm0(dev, 0,
4437                             &ironlake_display_wm_info,
4438                             ILK_LP0_PLANE_LATENCY,
4439                             &ironlake_cursor_wm_info,
4440                             ILK_LP0_CURSOR_LATENCY,
4441                             &plane_wm, &cursor_wm)) {
4442                 I915_WRITE(WM0_PIPEA_ILK,
4443                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4444                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4445                               " plane %d, " "cursor: %d\n",
4446                               plane_wm, cursor_wm);
4447                 enabled |= 1;
4448         }
4449
4450         if (g4x_compute_wm0(dev, 1,
4451                             &ironlake_display_wm_info,
4452                             ILK_LP0_PLANE_LATENCY,
4453                             &ironlake_cursor_wm_info,
4454                             ILK_LP0_CURSOR_LATENCY,
4455                             &plane_wm, &cursor_wm)) {
4456                 I915_WRITE(WM0_PIPEB_ILK,
4457                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4458                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4459                               " plane %d, cursor: %d\n",
4460                               plane_wm, cursor_wm);
4461                 enabled |= 2;
4462         }
4463
4464         /*
4465          * Calculate and update the self-refresh watermark only when one
4466          * display plane is used.
4467          */
4468         I915_WRITE(WM3_LP_ILK, 0);
4469         I915_WRITE(WM2_LP_ILK, 0);
4470         I915_WRITE(WM1_LP_ILK, 0);
4471
4472         if (!single_plane_enabled(enabled))
4473                 return;
4474         enabled = ffs(enabled) - 1;
4475
4476         /* WM1 */
4477         if (!ironlake_compute_srwm(dev, 1, enabled,
4478                                    ILK_READ_WM1_LATENCY() * 500,
4479                                    &ironlake_display_srwm_info,
4480                                    &ironlake_cursor_srwm_info,
4481                                    &fbc_wm, &plane_wm, &cursor_wm))
4482                 return;
4483
4484         I915_WRITE(WM1_LP_ILK,
4485                    WM1_LP_SR_EN |
4486                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4487                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4488                    (plane_wm << WM1_LP_SR_SHIFT) |
4489                    cursor_wm);
4490
4491         /* WM2 */
4492         if (!ironlake_compute_srwm(dev, 2, enabled,
4493                                    ILK_READ_WM2_LATENCY() * 500,
4494                                    &ironlake_display_srwm_info,
4495                                    &ironlake_cursor_srwm_info,
4496                                    &fbc_wm, &plane_wm, &cursor_wm))
4497                 return;
4498
4499         I915_WRITE(WM2_LP_ILK,
4500                    WM2_LP_EN |
4501                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4502                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4503                    (plane_wm << WM1_LP_SR_SHIFT) |
4504                    cursor_wm);
4505
4506         /*
4507          * WM3 is unsupported on ILK, probably because we don't have latency
4508          * data for that power state
4509          */
4510 }
4511
4512 static void sandybridge_update_wm(struct drm_device *dev)
4513 {
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
4516         int fbc_wm, plane_wm, cursor_wm;
4517         unsigned int enabled;
4518
4519         enabled = 0;
4520         if (g4x_compute_wm0(dev, 0,
4521                             &sandybridge_display_wm_info, latency,
4522                             &sandybridge_cursor_wm_info, latency,
4523                             &plane_wm, &cursor_wm)) {
4524                 I915_WRITE(WM0_PIPEA_ILK,
4525                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4526                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4527                               " plane %d, " "cursor: %d\n",
4528                               plane_wm, cursor_wm);
4529                 enabled |= 1;
4530         }
4531
4532         if (g4x_compute_wm0(dev, 1,
4533                             &sandybridge_display_wm_info, latency,
4534                             &sandybridge_cursor_wm_info, latency,
4535                             &plane_wm, &cursor_wm)) {
4536                 I915_WRITE(WM0_PIPEB_ILK,
4537                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4538                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4539                               " plane %d, cursor: %d\n",
4540                               plane_wm, cursor_wm);
4541                 enabled |= 2;
4542         }
4543
4544         /* IVB has 3 pipes */
4545         if (IS_IVYBRIDGE(dev) &&
4546             g4x_compute_wm0(dev, 2,
4547                             &sandybridge_display_wm_info, latency,
4548                             &sandybridge_cursor_wm_info, latency,
4549                             &plane_wm, &cursor_wm)) {
4550                 I915_WRITE(WM0_PIPEC_IVB,
4551                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4552                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4553                               " plane %d, cursor: %d\n",
4554                               plane_wm, cursor_wm);
4555                 enabled |= 3;
4556         }
4557
4558         /*
4559          * Calculate and update the self-refresh watermark only when one
4560          * display plane is used.
4561          *
4562          * SNB support 3 levels of watermark.
4563          *
4564          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4565          * and disabled in the descending order
4566          *
4567          */
4568         I915_WRITE(WM3_LP_ILK, 0);
4569         I915_WRITE(WM2_LP_ILK, 0);
4570         I915_WRITE(WM1_LP_ILK, 0);
4571
4572         if (!single_plane_enabled(enabled))
4573                 return;
4574         enabled = ffs(enabled) - 1;
4575
4576         /* WM1 */
4577         if (!ironlake_compute_srwm(dev, 1, enabled,
4578                                    SNB_READ_WM1_LATENCY() * 500,
4579                                    &sandybridge_display_srwm_info,
4580                                    &sandybridge_cursor_srwm_info,
4581                                    &fbc_wm, &plane_wm, &cursor_wm))
4582                 return;
4583
4584         I915_WRITE(WM1_LP_ILK,
4585                    WM1_LP_SR_EN |
4586                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4587                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4588                    (plane_wm << WM1_LP_SR_SHIFT) |
4589                    cursor_wm);
4590
4591         /* WM2 */
4592         if (!ironlake_compute_srwm(dev, 2, enabled,
4593                                    SNB_READ_WM2_LATENCY() * 500,
4594                                    &sandybridge_display_srwm_info,
4595                                    &sandybridge_cursor_srwm_info,
4596                                    &fbc_wm, &plane_wm, &cursor_wm))
4597                 return;
4598
4599         I915_WRITE(WM2_LP_ILK,
4600                    WM2_LP_EN |
4601                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4602                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4603                    (plane_wm << WM1_LP_SR_SHIFT) |
4604                    cursor_wm);
4605
4606         /* WM3 */
4607         if (!ironlake_compute_srwm(dev, 3, enabled,
4608                                    SNB_READ_WM3_LATENCY() * 500,
4609                                    &sandybridge_display_srwm_info,
4610                                    &sandybridge_cursor_srwm_info,
4611                                    &fbc_wm, &plane_wm, &cursor_wm))
4612                 return;
4613
4614         I915_WRITE(WM3_LP_ILK,
4615                    WM3_LP_EN |
4616                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4617                    (fbc_wm << WM1_LP_FBC_SHIFT) |
4618                    (plane_wm << WM1_LP_SR_SHIFT) |
4619                    cursor_wm);
4620 }
4621
4622 /**
4623  * intel_update_watermarks - update FIFO watermark values based on current modes
4624  *
4625  * Calculate watermark values for the various WM regs based on current mode
4626  * and plane configuration.
4627  *
4628  * There are several cases to deal with here:
4629  *   - normal (i.e. non-self-refresh)
4630  *   - self-refresh (SR) mode
4631  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4632  *   - lines are small relative to FIFO size (buffer can hold more than 2
4633  *     lines), so need to account for TLB latency
4634  *
4635  *   The normal calculation is:
4636  *     watermark = dotclock * bytes per pixel * latency
4637  *   where latency is platform & configuration dependent (we assume pessimal
4638  *   values here).
4639  *
4640  *   The SR calculation is:
4641  *     watermark = (trunc(latency/line time)+1) * surface width *
4642  *       bytes per pixel
4643  *   where
4644  *     line time = htotal / dotclock
4645  *     surface width = hdisplay for normal plane and 64 for cursor
4646  *   and latency is assumed to be high, as above.
4647  *
4648  * The final value programmed to the register should always be rounded up,
4649  * and include an extra 2 entries to account for clock crossings.
4650  *
4651  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4652  * to set the non-SR watermarks to 8.
4653  */
4654 static void intel_update_watermarks(struct drm_device *dev)
4655 {
4656         struct drm_i915_private *dev_priv = dev->dev_private;
4657
4658         if (dev_priv->display.update_wm)
4659                 dev_priv->display.update_wm(dev);
4660 }
4661
4662 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4663 {
4664         if (i915_panel_use_ssc >= 0)
4665                 return i915_panel_use_ssc != 0;
4666         return dev_priv->lvds_use_ssc
4667                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4668 }
4669
4670 /**
4671  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4672  * @crtc: CRTC structure
4673  *
4674  * A pipe may be connected to one or more outputs.  Based on the depth of the
4675  * attached framebuffer, choose a good color depth to use on the pipe.
4676  *
4677  * If possible, match the pipe depth to the fb depth.  In some cases, this
4678  * isn't ideal, because the connected output supports a lesser or restricted
4679  * set of depths.  Resolve that here:
4680  *    LVDS typically supports only 6bpc, so clamp down in that case
4681  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4682  *    Displays may support a restricted set as well, check EDID and clamp as
4683  *      appropriate.
4684  *
4685  * RETURNS:
4686  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4687  * true if they don't match).
4688  */
4689 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4690                                          unsigned int *pipe_bpp)
4691 {
4692         struct drm_device *dev = crtc->dev;
4693         struct drm_i915_private *dev_priv = dev->dev_private;
4694         struct drm_encoder *encoder;
4695         struct drm_connector *connector;
4696         unsigned int display_bpc = UINT_MAX, bpc;
4697
4698         /* Walk the encoders & connectors on this crtc, get min bpc */
4699         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4700                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4701
4702                 if (encoder->crtc != crtc)
4703                         continue;
4704
4705                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4706                         unsigned int lvds_bpc;
4707
4708                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4709                             LVDS_A3_POWER_UP)
4710                                 lvds_bpc = 8;
4711                         else
4712                                 lvds_bpc = 6;
4713
4714                         if (lvds_bpc < display_bpc) {
4715                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4716                                 display_bpc = lvds_bpc;
4717                         }
4718                         continue;
4719                 }
4720
4721                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4722                         /* Use VBT settings if we have an eDP panel */
4723                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4724
4725                         if (edp_bpc < display_bpc) {
4726                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4727                                 display_bpc = edp_bpc;
4728                         }
4729                         continue;
4730                 }
4731
4732                 /* Not one of the known troublemakers, check the EDID */
4733                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4734                                     head) {
4735                         if (connector->encoder != encoder)
4736                                 continue;
4737
4738                         /* Don't use an invalid EDID bpc value */
4739                         if (connector->display_info.bpc &&
4740                             connector->display_info.bpc < display_bpc) {
4741                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4742                                 display_bpc = connector->display_info.bpc;
4743                         }
4744                 }
4745
4746                 /*
4747                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4748                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4749                  */
4750                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4751                         if (display_bpc > 8 && display_bpc < 12) {
4752                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4753                                 display_bpc = 12;
4754                         } else {
4755                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4756                                 display_bpc = 8;
4757                         }
4758                 }
4759         }
4760
4761         /*
4762          * We could just drive the pipe at the highest bpc all the time and
4763          * enable dithering as needed, but that costs bandwidth.  So choose
4764          * the minimum value that expresses the full color range of the fb but
4765          * also stays within the max display bpc discovered above.
4766          */
4767
4768         switch (crtc->fb->depth) {
4769         case 8:
4770                 bpc = 8; /* since we go through a colormap */
4771                 break;
4772         case 15:
4773         case 16:
4774                 bpc = 6; /* min is 18bpp */
4775                 break;
4776         case 24:
4777                 bpc = 8;
4778                 break;
4779         case 30:
4780                 bpc = 10;
4781                 break;
4782         case 48:
4783                 bpc = 12;
4784                 break;
4785         default:
4786                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4787                 bpc = min((unsigned int)8, display_bpc);
4788                 break;
4789         }
4790
4791         display_bpc = min(display_bpc, bpc);
4792
4793         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4794                       bpc, display_bpc);
4795
4796         *pipe_bpp = display_bpc * 3;
4797
4798         return display_bpc != bpc;
4799 }
4800
4801 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4802                               struct drm_display_mode *mode,
4803                               struct drm_display_mode *adjusted_mode,
4804                               int x, int y,
4805                               struct drm_framebuffer *old_fb)
4806 {
4807         struct drm_device *dev = crtc->dev;
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4810         int pipe = intel_crtc->pipe;
4811         int plane = intel_crtc->plane;
4812         int refclk, num_connectors = 0;
4813         intel_clock_t clock, reduced_clock;
4814         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4815         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4816         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4817         struct drm_mode_config *mode_config = &dev->mode_config;
4818         struct intel_encoder *encoder;
4819         const intel_limit_t *limit;
4820         int ret;
4821         u32 temp;
4822         u32 lvds_sync = 0;
4823
4824         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4825                 if (encoder->base.crtc != crtc)
4826                         continue;
4827
4828                 switch (encoder->type) {
4829                 case INTEL_OUTPUT_LVDS:
4830                         is_lvds = true;
4831                         break;
4832                 case INTEL_OUTPUT_SDVO:
4833                 case INTEL_OUTPUT_HDMI:
4834                         is_sdvo = true;
4835                         if (encoder->needs_tv_clock)
4836                                 is_tv = true;
4837                         break;
4838                 case INTEL_OUTPUT_DVO:
4839                         is_dvo = true;
4840                         break;
4841                 case INTEL_OUTPUT_TVOUT:
4842                         is_tv = true;
4843                         break;
4844                 case INTEL_OUTPUT_ANALOG:
4845                         is_crt = true;
4846                         break;
4847                 case INTEL_OUTPUT_DISPLAYPORT:
4848                         is_dp = true;
4849                         break;
4850                 }
4851
4852                 num_connectors++;
4853         }
4854
4855         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4856                 refclk = dev_priv->lvds_ssc_freq * 1000;
4857                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4858                               refclk / 1000);
4859         } else if (!IS_GEN2(dev)) {
4860                 refclk = 96000;
4861         } else {
4862                 refclk = 48000;
4863         }
4864
4865         /*
4866          * Returns a set of divisors for the desired target clock with the given
4867          * refclk, or FALSE.  The returned values represent the clock equation:
4868          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4869          */
4870         limit = intel_limit(crtc, refclk);
4871         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4872         if (!ok) {
4873                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4874                 return -EINVAL;
4875         }
4876
4877         /* Ensure that the cursor is valid for the new mode before changing... */
4878         intel_crtc_update_cursor(crtc, true);
4879
4880         if (is_lvds && dev_priv->lvds_downclock_avail) {
4881                 has_reduced_clock = limit->find_pll(limit, crtc,
4882                                                     dev_priv->lvds_downclock,
4883                                                     refclk,
4884                                                     &reduced_clock);
4885                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4886                         /*
4887                          * If the different P is found, it means that we can't
4888                          * switch the display clock by using the FP0/FP1.
4889                          * In such case we will disable the LVDS downclock
4890                          * feature.
4891                          */
4892                         DRM_DEBUG_KMS("Different P is found for "
4893                                       "LVDS clock/downclock\n");
4894                         has_reduced_clock = 0;
4895                 }
4896         }
4897         /* SDVO TV has fixed PLL values depend on its clock range,
4898            this mirrors vbios setting. */
4899         if (is_sdvo && is_tv) {
4900                 if (adjusted_mode->clock >= 100000
4901                     && adjusted_mode->clock < 140500) {
4902                         clock.p1 = 2;
4903                         clock.p2 = 10;
4904                         clock.n = 3;
4905                         clock.m1 = 16;
4906                         clock.m2 = 8;
4907                 } else if (adjusted_mode->clock >= 140500
4908                            && adjusted_mode->clock <= 200000) {
4909                         clock.p1 = 1;
4910                         clock.p2 = 10;
4911                         clock.n = 6;
4912                         clock.m1 = 12;
4913                         clock.m2 = 8;
4914                 }
4915         }
4916
4917         if (IS_PINEVIEW(dev)) {
4918                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4919                 if (has_reduced_clock)
4920                         fp2 = (1 << reduced_clock.n) << 16 |
4921                                 reduced_clock.m1 << 8 | reduced_clock.m2;
4922         } else {
4923                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4924                 if (has_reduced_clock)
4925                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4926                                 reduced_clock.m2;
4927         }
4928
4929         dpll = DPLL_VGA_MODE_DIS;
4930
4931         if (!IS_GEN2(dev)) {
4932                 if (is_lvds)
4933                         dpll |= DPLLB_MODE_LVDS;
4934                 else
4935                         dpll |= DPLLB_MODE_DAC_SERIAL;
4936                 if (is_sdvo) {
4937                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4938                         if (pixel_multiplier > 1) {
4939                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4940                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4941                         }
4942                         dpll |= DPLL_DVO_HIGH_SPEED;
4943                 }
4944                 if (is_dp)
4945                         dpll |= DPLL_DVO_HIGH_SPEED;
4946
4947                 /* compute bitmask from p1 value */
4948                 if (IS_PINEVIEW(dev))
4949                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4950                 else {
4951                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4952                         if (IS_G4X(dev) && has_reduced_clock)
4953                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4954                 }
4955                 switch (clock.p2) {
4956                 case 5:
4957                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4958                         break;
4959                 case 7:
4960                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4961                         break;
4962                 case 10:
4963                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4964                         break;
4965                 case 14:
4966                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4967                         break;
4968                 }
4969                 if (INTEL_INFO(dev)->gen >= 4)
4970                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4971         } else {
4972                 if (is_lvds) {
4973                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4974                 } else {
4975                         if (clock.p1 == 2)
4976                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
4977                         else
4978                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4979                         if (clock.p2 == 4)
4980                                 dpll |= PLL_P2_DIVIDE_BY_4;
4981                 }
4982         }
4983
4984         if (is_sdvo && is_tv)
4985                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4986         else if (is_tv)
4987                 /* XXX: just matching BIOS for now */
4988                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4989                 dpll |= 3;
4990         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4991                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4992         else
4993                 dpll |= PLL_REF_INPUT_DREFCLK;
4994
4995         /* setup pipeconf */
4996         pipeconf = I915_READ(PIPECONF(pipe));
4997
4998         /* Set up the display plane register */
4999         dspcntr = DISPPLANE_GAMMA_ENABLE;
5000
5001         /* Ironlake's plane is forced to pipe, bit 24 is to
5002            enable color space conversion */
5003         if (pipe == 0)
5004                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5005         else
5006                 dspcntr |= DISPPLANE_SEL_PIPE_B;
5007
5008         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5009                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5010                  * core speed.
5011                  *
5012                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5013                  * pipe == 0 check?
5014                  */
5015                 if (mode->clock >
5016                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5017                         pipeconf |= PIPECONF_DOUBLE_WIDE;
5018                 else
5019                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5020         }
5021
5022         dpll |= DPLL_VCO_ENABLE;
5023
5024         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5025         drm_mode_debug_printmodeline(mode);
5026
5027         I915_WRITE(FP0(pipe), fp);
5028         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5029
5030         POSTING_READ(DPLL(pipe));
5031         udelay(150);
5032
5033         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5034          * This is an exception to the general rule that mode_set doesn't turn
5035          * things on.
5036          */
5037         if (is_lvds) {
5038                 temp = I915_READ(LVDS);
5039                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5040                 if (pipe == 1) {
5041                         temp |= LVDS_PIPEB_SELECT;
5042                 } else {
5043                         temp &= ~LVDS_PIPEB_SELECT;
5044                 }
5045                 /* set the corresponsding LVDS_BORDER bit */
5046                 temp |= dev_priv->lvds_border_bits;
5047                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5048                  * set the DPLLs for dual-channel mode or not.
5049                  */
5050                 if (clock.p2 == 7)
5051                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5052                 else
5053                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5054
5055                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5056                  * appropriately here, but we need to look more thoroughly into how
5057                  * panels behave in the two modes.
5058                  */
5059                 /* set the dithering flag on LVDS as needed */
5060                 if (INTEL_INFO(dev)->gen >= 4) {
5061                         if (dev_priv->lvds_dither)
5062                                 temp |= LVDS_ENABLE_DITHER;
5063                         else
5064                                 temp &= ~LVDS_ENABLE_DITHER;
5065                 }
5066                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5067                         lvds_sync |= LVDS_HSYNC_POLARITY;
5068                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5069                         lvds_sync |= LVDS_VSYNC_POLARITY;
5070                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5071                     != lvds_sync) {
5072                         char flags[2] = "-+";
5073                         DRM_INFO("Changing LVDS panel from "
5074                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5075                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5076                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5077                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5078                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5079                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5080                         temp |= lvds_sync;
5081                 }
5082                 I915_WRITE(LVDS, temp);
5083         }
5084
5085         if (is_dp) {
5086                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5087         }
5088
5089         I915_WRITE(DPLL(pipe), dpll);
5090
5091         /* Wait for the clocks to stabilize. */
5092         POSTING_READ(DPLL(pipe));
5093         udelay(150);
5094
5095         if (INTEL_INFO(dev)->gen >= 4) {
5096                 temp = 0;
5097                 if (is_sdvo) {
5098                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5099                         if (temp > 1)
5100                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5101                         else
5102                                 temp = 0;
5103                 }
5104                 I915_WRITE(DPLL_MD(pipe), temp);
5105         } else {
5106                 /* The pixel multiplier can only be updated once the
5107                  * DPLL is enabled and the clocks are stable.
5108                  *
5109                  * So write it again.
5110                  */
5111                 I915_WRITE(DPLL(pipe), dpll);
5112         }
5113
5114         intel_crtc->lowfreq_avail = false;
5115         if (is_lvds && has_reduced_clock && i915_powersave) {
5116                 I915_WRITE(FP1(pipe), fp2);
5117                 intel_crtc->lowfreq_avail = true;
5118                 if (HAS_PIPE_CXSR(dev)) {
5119                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5120                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5121                 }
5122         } else {
5123                 I915_WRITE(FP1(pipe), fp);
5124                 if (HAS_PIPE_CXSR(dev)) {
5125                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5126                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5127                 }
5128         }
5129
5130         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5131                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5132                 /* the chip adds 2 halflines automatically */
5133                 adjusted_mode->crtc_vdisplay -= 1;
5134                 adjusted_mode->crtc_vtotal -= 1;
5135                 adjusted_mode->crtc_vblank_start -= 1;
5136                 adjusted_mode->crtc_vblank_end -= 1;
5137                 adjusted_mode->crtc_vsync_end -= 1;
5138                 adjusted_mode->crtc_vsync_start -= 1;
5139         } else
5140                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5141
5142         I915_WRITE(HTOTAL(pipe),
5143                    (adjusted_mode->crtc_hdisplay - 1) |
5144                    ((adjusted_mode->crtc_htotal - 1) << 16));
5145         I915_WRITE(HBLANK(pipe),
5146                    (adjusted_mode->crtc_hblank_start - 1) |
5147                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5148         I915_WRITE(HSYNC(pipe),
5149                    (adjusted_mode->crtc_hsync_start - 1) |
5150                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5151
5152         I915_WRITE(VTOTAL(pipe),
5153                    (adjusted_mode->crtc_vdisplay - 1) |
5154                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5155         I915_WRITE(VBLANK(pipe),
5156                    (adjusted_mode->crtc_vblank_start - 1) |
5157                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5158         I915_WRITE(VSYNC(pipe),
5159                    (adjusted_mode->crtc_vsync_start - 1) |
5160                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5161
5162         /* pipesrc and dspsize control the size that is scaled from,
5163          * which should always be the user's requested size.
5164          */
5165         I915_WRITE(DSPSIZE(plane),
5166                    ((mode->vdisplay - 1) << 16) |
5167                    (mode->hdisplay - 1));
5168         I915_WRITE(DSPPOS(plane), 0);
5169         I915_WRITE(PIPESRC(pipe),
5170                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5171
5172         I915_WRITE(PIPECONF(pipe), pipeconf);
5173         POSTING_READ(PIPECONF(pipe));
5174         intel_enable_pipe(dev_priv, pipe, false);
5175
5176         intel_wait_for_vblank(dev, pipe);
5177
5178         I915_WRITE(DSPCNTR(plane), dspcntr);
5179         POSTING_READ(DSPCNTR(plane));
5180         intel_enable_plane(dev_priv, plane, pipe);
5181
5182         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5183
5184         intel_update_watermarks(dev);
5185
5186         return ret;
5187 }
5188
5189 /*
5190  * Initialize reference clocks when the driver loads
5191  */
5192 void ironlake_init_pch_refclk(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195         struct drm_mode_config *mode_config = &dev->mode_config;
5196         struct intel_encoder *encoder;
5197         u32 temp;
5198         bool has_lvds = false;
5199         bool has_cpu_edp = false;
5200         bool has_pch_edp = false;
5201         bool has_panel = false;
5202         bool has_ck505 = false;
5203         bool can_ssc = false;
5204
5205         /* We need to take the global config into account */
5206         list_for_each_entry(encoder, &mode_config->encoder_list,
5207                             base.head) {
5208                 switch (encoder->type) {
5209                 case INTEL_OUTPUT_LVDS:
5210                         has_panel = true;
5211                         has_lvds = true;
5212                         break;
5213                 case INTEL_OUTPUT_EDP:
5214                         has_panel = true;
5215                         if (intel_encoder_is_pch_edp(&encoder->base))
5216                                 has_pch_edp = true;
5217                         else
5218                                 has_cpu_edp = true;
5219                         break;
5220                 }
5221         }
5222
5223         if (HAS_PCH_IBX(dev)) {
5224                 has_ck505 = dev_priv->display_clock_mode;
5225                 can_ssc = has_ck505;
5226         } else {
5227                 has_ck505 = false;
5228                 can_ssc = true;
5229         }
5230
5231         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5232                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5233                       has_ck505);
5234
5235         /* Ironlake: try to setup display ref clock before DPLL
5236          * enabling. This is only under driver's control after
5237          * PCH B stepping, previous chipset stepping should be
5238          * ignoring this setting.
5239          */
5240         temp = I915_READ(PCH_DREF_CONTROL);
5241         /* Always enable nonspread source */
5242         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5243
5244         if (has_ck505)
5245                 temp |= DREF_NONSPREAD_CK505_ENABLE;
5246         else
5247                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5248
5249         if (has_panel) {
5250                 temp &= ~DREF_SSC_SOURCE_MASK;
5251                 temp |= DREF_SSC_SOURCE_ENABLE;
5252
5253                 /* SSC must be turned on before enabling the CPU output  */
5254                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5255                         DRM_DEBUG_KMS("Using SSC on panel\n");
5256                         temp |= DREF_SSC1_ENABLE;
5257                 }
5258
5259                 /* Get SSC going before enabling the outputs */
5260                 I915_WRITE(PCH_DREF_CONTROL, temp);
5261                 POSTING_READ(PCH_DREF_CONTROL);
5262                 udelay(200);
5263
5264                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5265
5266                 /* Enable CPU source on CPU attached eDP */
5267                 if (has_cpu_edp) {
5268                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5269                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5270                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5271                         }
5272                         else
5273                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5274                 } else
5275                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5276
5277                 I915_WRITE(PCH_DREF_CONTROL, temp);
5278                 POSTING_READ(PCH_DREF_CONTROL);
5279                 udelay(200);
5280         } else {
5281                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5282
5283                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5284
5285                 /* Turn off CPU output */
5286                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5287
5288                 I915_WRITE(PCH_DREF_CONTROL, temp);
5289                 POSTING_READ(PCH_DREF_CONTROL);
5290                 udelay(200);
5291
5292                 /* Turn off the SSC source */
5293                 temp &= ~DREF_SSC_SOURCE_MASK;
5294                 temp |= DREF_SSC_SOURCE_DISABLE;
5295
5296                 /* Turn off SSC1 */
5297                 temp &= ~ DREF_SSC1_ENABLE;
5298
5299                 I915_WRITE(PCH_DREF_CONTROL, temp);
5300                 POSTING_READ(PCH_DREF_CONTROL);
5301                 udelay(200);
5302         }
5303 }
5304
5305 static int ironlake_get_refclk(struct drm_crtc *crtc)
5306 {
5307         struct drm_device *dev = crtc->dev;
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         struct intel_encoder *encoder;
5310         struct drm_mode_config *mode_config = &dev->mode_config;
5311         struct intel_encoder *edp_encoder = NULL;
5312         int num_connectors = 0;
5313         bool is_lvds = false;
5314
5315         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5316                 if (encoder->base.crtc != crtc)
5317                         continue;
5318
5319                 switch (encoder->type) {
5320                 case INTEL_OUTPUT_LVDS:
5321                         is_lvds = true;
5322                         break;
5323                 case INTEL_OUTPUT_EDP:
5324                         edp_encoder = encoder;
5325                         break;
5326                 }
5327                 num_connectors++;
5328         }
5329
5330         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5331                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5332                               dev_priv->lvds_ssc_freq);
5333                 return dev_priv->lvds_ssc_freq * 1000;
5334         }
5335
5336         return 120000;
5337 }
5338
5339 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5340                                   struct drm_display_mode *mode,
5341                                   struct drm_display_mode *adjusted_mode,
5342                                   int x, int y,
5343                                   struct drm_framebuffer *old_fb)
5344 {
5345         struct drm_device *dev = crtc->dev;
5346         struct drm_i915_private *dev_priv = dev->dev_private;
5347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348         int pipe = intel_crtc->pipe;
5349         int plane = intel_crtc->plane;
5350         int refclk, num_connectors = 0;
5351         intel_clock_t clock, reduced_clock;
5352         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5353         bool ok, has_reduced_clock = false, is_sdvo = false;
5354         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5355         struct intel_encoder *has_edp_encoder = NULL;
5356         struct drm_mode_config *mode_config = &dev->mode_config;
5357         struct intel_encoder *encoder;
5358         const intel_limit_t *limit;
5359         int ret;
5360         struct fdi_m_n m_n = {0};
5361         u32 temp;
5362         u32 lvds_sync = 0;
5363         int target_clock, pixel_multiplier, lane, link_bw, factor;
5364         unsigned int pipe_bpp;
5365         bool dither;
5366
5367         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5368                 if (encoder->base.crtc != crtc)
5369                         continue;
5370
5371                 switch (encoder->type) {
5372                 case INTEL_OUTPUT_LVDS:
5373                         is_lvds = true;
5374                         break;
5375                 case INTEL_OUTPUT_SDVO:
5376                 case INTEL_OUTPUT_HDMI:
5377                         is_sdvo = true;
5378                         if (encoder->needs_tv_clock)
5379                                 is_tv = true;
5380                         break;
5381                 case INTEL_OUTPUT_TVOUT:
5382                         is_tv = true;
5383                         break;
5384                 case INTEL_OUTPUT_ANALOG:
5385                         is_crt = true;
5386                         break;
5387                 case INTEL_OUTPUT_DISPLAYPORT:
5388                         is_dp = true;
5389                         break;
5390                 case INTEL_OUTPUT_EDP:
5391                         has_edp_encoder = encoder;
5392                         break;
5393                 }
5394
5395                 num_connectors++;
5396         }
5397
5398         refclk = ironlake_get_refclk(crtc);
5399
5400         /*
5401          * Returns a set of divisors for the desired target clock with the given
5402          * refclk, or FALSE.  The returned values represent the clock equation:
5403          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5404          */
5405         limit = intel_limit(crtc, refclk);
5406         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5407         if (!ok) {
5408                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5409                 return -EINVAL;
5410         }
5411
5412         /* Ensure that the cursor is valid for the new mode before changing... */
5413         intel_crtc_update_cursor(crtc, true);
5414
5415         if (is_lvds && dev_priv->lvds_downclock_avail) {
5416                 has_reduced_clock = limit->find_pll(limit, crtc,
5417                                                     dev_priv->lvds_downclock,
5418                                                     refclk,
5419                                                     &reduced_clock);
5420                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5421                         /*
5422                          * If the different P is found, it means that we can't
5423                          * switch the display clock by using the FP0/FP1.
5424                          * In such case we will disable the LVDS downclock
5425                          * feature.
5426                          */
5427                         DRM_DEBUG_KMS("Different P is found for "
5428                                       "LVDS clock/downclock\n");
5429                         has_reduced_clock = 0;
5430                 }
5431         }
5432         /* SDVO TV has fixed PLL values depend on its clock range,
5433            this mirrors vbios setting. */
5434         if (is_sdvo && is_tv) {
5435                 if (adjusted_mode->clock >= 100000
5436                     && adjusted_mode->clock < 140500) {
5437                         clock.p1 = 2;
5438                         clock.p2 = 10;
5439                         clock.n = 3;
5440                         clock.m1 = 16;
5441                         clock.m2 = 8;
5442                 } else if (adjusted_mode->clock >= 140500
5443                            && adjusted_mode->clock <= 200000) {
5444                         clock.p1 = 1;
5445                         clock.p2 = 10;
5446                         clock.n = 6;
5447                         clock.m1 = 12;
5448                         clock.m2 = 8;
5449                 }
5450         }
5451
5452         /* FDI link */
5453         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5454         lane = 0;
5455         /* CPU eDP doesn't require FDI link, so just set DP M/N
5456            according to current link config */
5457         if (has_edp_encoder &&
5458             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5459                 target_clock = mode->clock;
5460                 intel_edp_link_config(has_edp_encoder,
5461                                       &lane, &link_bw);
5462         } else {
5463                 /* [e]DP over FDI requires target mode clock
5464                    instead of link clock */
5465                 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5466                         target_clock = mode->clock;
5467                 else
5468                         target_clock = adjusted_mode->clock;
5469
5470                 /* FDI is a binary signal running at ~2.7GHz, encoding
5471                  * each output octet as 10 bits. The actual frequency
5472                  * is stored as a divider into a 100MHz clock, and the
5473                  * mode pixel clock is stored in units of 1KHz.
5474                  * Hence the bw of each lane in terms of the mode signal
5475                  * is:
5476                  */
5477                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5478         }
5479
5480         /* determine panel color depth */
5481         temp = I915_READ(PIPECONF(pipe));
5482         temp &= ~PIPE_BPC_MASK;
5483         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5484         switch (pipe_bpp) {
5485         case 18:
5486                 temp |= PIPE_6BPC;
5487                 break;
5488         case 24:
5489                 temp |= PIPE_8BPC;
5490                 break;
5491         case 30:
5492                 temp |= PIPE_10BPC;
5493                 break;
5494         case 36:
5495                 temp |= PIPE_12BPC;
5496                 break;
5497         default:
5498                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5499                         pipe_bpp);
5500                 temp |= PIPE_8BPC;
5501                 pipe_bpp = 24;
5502                 break;
5503         }
5504
5505         intel_crtc->bpp = pipe_bpp;
5506         I915_WRITE(PIPECONF(pipe), temp);
5507
5508         if (!lane) {
5509                 /*
5510                  * Account for spread spectrum to avoid
5511                  * oversubscribing the link. Max center spread
5512                  * is 2.5%; use 5% for safety's sake.
5513                  */
5514                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5515                 lane = bps / (link_bw * 8) + 1;
5516         }
5517
5518         intel_crtc->fdi_lanes = lane;
5519
5520         if (pixel_multiplier > 1)
5521                 link_bw *= pixel_multiplier;
5522         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5523                              &m_n);
5524
5525         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5526         if (has_reduced_clock)
5527                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5528                         reduced_clock.m2;
5529
5530         /* Enable autotuning of the PLL clock (if permissible) */
5531         factor = 21;
5532         if (is_lvds) {
5533                 if ((intel_panel_use_ssc(dev_priv) &&
5534                      dev_priv->lvds_ssc_freq == 100) ||
5535                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5536                         factor = 25;
5537         } else if (is_sdvo && is_tv)
5538                 factor = 20;
5539
5540         if (clock.m < factor * clock.n)
5541                 fp |= FP_CB_TUNE;
5542
5543         dpll = 0;
5544
5545         if (is_lvds)
5546                 dpll |= DPLLB_MODE_LVDS;
5547         else
5548                 dpll |= DPLLB_MODE_DAC_SERIAL;
5549         if (is_sdvo) {
5550                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5551                 if (pixel_multiplier > 1) {
5552                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5553                 }
5554                 dpll |= DPLL_DVO_HIGH_SPEED;
5555         }
5556         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5557                 dpll |= DPLL_DVO_HIGH_SPEED;
5558
5559         /* compute bitmask from p1 value */
5560         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5561         /* also FPA1 */
5562         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5563
5564         switch (clock.p2) {
5565         case 5:
5566                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5567                 break;
5568         case 7:
5569                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5570                 break;
5571         case 10:
5572                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5573                 break;
5574         case 14:
5575                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5576                 break;
5577         }
5578
5579         if (is_sdvo && is_tv)
5580                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5581         else if (is_tv)
5582                 /* XXX: just matching BIOS for now */
5583                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5584                 dpll |= 3;
5585         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5586                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5587         else
5588                 dpll |= PLL_REF_INPUT_DREFCLK;
5589
5590         /* setup pipeconf */
5591         pipeconf = I915_READ(PIPECONF(pipe));
5592
5593         /* Set up the display plane register */
5594         dspcntr = DISPPLANE_GAMMA_ENABLE;
5595
5596         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5597         drm_mode_debug_printmodeline(mode);
5598
5599         /* PCH eDP needs FDI, but CPU eDP does not */
5600         if (!intel_crtc->no_pll) {
5601                 if (!has_edp_encoder ||
5602                     intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5603                         I915_WRITE(PCH_FP0(pipe), fp);
5604                         I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5605
5606                         POSTING_READ(PCH_DPLL(pipe));
5607                         udelay(150);
5608                 }
5609         } else {
5610                 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5611                     fp == I915_READ(PCH_FP0(0))) {
5612                         intel_crtc->use_pll_a = true;
5613                         DRM_DEBUG_KMS("using pipe a dpll\n");
5614                 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5615                            fp == I915_READ(PCH_FP0(1))) {
5616                         intel_crtc->use_pll_a = false;
5617                         DRM_DEBUG_KMS("using pipe b dpll\n");
5618                 } else {
5619                         DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5620                         return -EINVAL;
5621                 }
5622         }
5623
5624         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5625          * This is an exception to the general rule that mode_set doesn't turn
5626          * things on.
5627          */
5628         if (is_lvds) {
5629                 temp = I915_READ(PCH_LVDS);
5630                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5631                 if (HAS_PCH_CPT(dev))
5632                         temp |= PORT_TRANS_SEL_CPT(pipe);
5633                 else if (pipe == 1)
5634                         temp |= LVDS_PIPEB_SELECT;
5635                 else
5636                         temp &= ~LVDS_PIPEB_SELECT;
5637
5638                 /* set the corresponsding LVDS_BORDER bit */
5639                 temp |= dev_priv->lvds_border_bits;
5640                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5641                  * set the DPLLs for dual-channel mode or not.
5642                  */
5643                 if (clock.p2 == 7)
5644                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5645                 else
5646                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5647
5648                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5649                  * appropriately here, but we need to look more thoroughly into how
5650                  * panels behave in the two modes.
5651                  */
5652                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5653                         lvds_sync |= LVDS_HSYNC_POLARITY;
5654                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5655                         lvds_sync |= LVDS_VSYNC_POLARITY;
5656                 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5657                     != lvds_sync) {
5658                         char flags[2] = "-+";
5659                         DRM_INFO("Changing LVDS panel from "
5660                                  "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5661                                  flags[!(temp & LVDS_HSYNC_POLARITY)],
5662                                  flags[!(temp & LVDS_VSYNC_POLARITY)],
5663                                  flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5664                                  flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5665                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5666                         temp |= lvds_sync;
5667                 }
5668                 I915_WRITE(PCH_LVDS, temp);
5669         }
5670
5671         pipeconf &= ~PIPECONF_DITHER_EN;
5672         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5673         if ((is_lvds && dev_priv->lvds_dither) || dither) {
5674                 pipeconf |= PIPECONF_DITHER_EN;
5675                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5676         }
5677         if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5678                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5679         } else {
5680                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5681                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5682                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5683                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5684                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5685         }
5686
5687         if (!intel_crtc->no_pll &&
5688             (!has_edp_encoder ||
5689              intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5690                 I915_WRITE(PCH_DPLL(pipe), dpll);
5691
5692                 /* Wait for the clocks to stabilize. */
5693                 POSTING_READ(PCH_DPLL(pipe));
5694                 udelay(150);
5695
5696                 /* The pixel multiplier can only be updated once the
5697                  * DPLL is enabled and the clocks are stable.
5698                  *
5699                  * So write it again.
5700                  */
5701                 I915_WRITE(PCH_DPLL(pipe), dpll);
5702         }
5703
5704         intel_crtc->lowfreq_avail = false;
5705         if (!intel_crtc->no_pll) {
5706                 if (is_lvds && has_reduced_clock && i915_powersave) {
5707                         I915_WRITE(PCH_FP1(pipe), fp2);
5708                         intel_crtc->lowfreq_avail = true;
5709                         if (HAS_PIPE_CXSR(dev)) {
5710                                 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5711                                 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5712                         }
5713                 } else {
5714                         I915_WRITE(PCH_FP1(pipe), fp);
5715                         if (HAS_PIPE_CXSR(dev)) {
5716                                 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5717                                 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5718                         }
5719                 }
5720         }
5721
5722         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5723                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5724                 /* the chip adds 2 halflines automatically */
5725                 adjusted_mode->crtc_vdisplay -= 1;
5726                 adjusted_mode->crtc_vtotal -= 1;
5727                 adjusted_mode->crtc_vblank_start -= 1;
5728                 adjusted_mode->crtc_vblank_end -= 1;
5729                 adjusted_mode->crtc_vsync_end -= 1;
5730                 adjusted_mode->crtc_vsync_start -= 1;
5731         } else
5732                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5733
5734         I915_WRITE(HTOTAL(pipe),
5735                    (adjusted_mode->crtc_hdisplay - 1) |
5736                    ((adjusted_mode->crtc_htotal - 1) << 16));
5737         I915_WRITE(HBLANK(pipe),
5738                    (adjusted_mode->crtc_hblank_start - 1) |
5739                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5740         I915_WRITE(HSYNC(pipe),
5741                    (adjusted_mode->crtc_hsync_start - 1) |
5742                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5743
5744         I915_WRITE(VTOTAL(pipe),
5745                    (adjusted_mode->crtc_vdisplay - 1) |
5746                    ((adjusted_mode->crtc_vtotal - 1) << 16));
5747         I915_WRITE(VBLANK(pipe),
5748                    (adjusted_mode->crtc_vblank_start - 1) |
5749                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
5750         I915_WRITE(VSYNC(pipe),
5751                    (adjusted_mode->crtc_vsync_start - 1) |
5752                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5753
5754         /* pipesrc controls the size that is scaled from, which should
5755          * always be the user's requested size.
5756          */
5757         I915_WRITE(PIPESRC(pipe),
5758                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5759
5760         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5761         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5762         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5763         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5764
5765         if (has_edp_encoder &&
5766             !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5767                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5768         }
5769
5770         I915_WRITE(PIPECONF(pipe), pipeconf);
5771         POSTING_READ(PIPECONF(pipe));
5772
5773         intel_wait_for_vblank(dev, pipe);
5774
5775         if (IS_GEN5(dev)) {
5776                 /* enable address swizzle for tiling buffer */
5777                 temp = I915_READ(DISP_ARB_CTL);
5778                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5779         }
5780
5781         I915_WRITE(DSPCNTR(plane), dspcntr);
5782         POSTING_READ(DSPCNTR(plane));
5783
5784         ret = intel_pipe_set_base(crtc, x, y, old_fb);
5785
5786         intel_update_watermarks(dev);
5787
5788         return ret;
5789 }
5790
5791 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5792                                struct drm_display_mode *mode,
5793                                struct drm_display_mode *adjusted_mode,
5794                                int x, int y,
5795                                struct drm_framebuffer *old_fb)
5796 {
5797         struct drm_device *dev = crtc->dev;
5798         struct drm_i915_private *dev_priv = dev->dev_private;
5799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5800         int pipe = intel_crtc->pipe;
5801         int ret;
5802
5803         drm_vblank_pre_modeset(dev, pipe);
5804
5805         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5806                                               x, y, old_fb);
5807
5808         drm_vblank_post_modeset(dev, pipe);
5809
5810         intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5811
5812         return ret;
5813 }
5814
5815 static void g4x_write_eld(struct drm_connector *connector,
5816                           struct drm_crtc *crtc)
5817 {
5818         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5819         uint8_t *eld = connector->eld;
5820         uint32_t eldv;
5821         uint32_t len;
5822         uint32_t i;
5823
5824         i = I915_READ(G4X_AUD_VID_DID);
5825
5826         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5827                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5828         else
5829                 eldv = G4X_ELDV_DEVCTG;
5830
5831         i = I915_READ(G4X_AUD_CNTL_ST);
5832         i &= ~(eldv | G4X_ELD_ADDR);
5833         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5834         I915_WRITE(G4X_AUD_CNTL_ST, i);
5835
5836         if (!eld[0])
5837                 return;
5838
5839         len = min_t(uint8_t, eld[2], len);
5840         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5841         for (i = 0; i < len; i++)
5842                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5843
5844         i = I915_READ(G4X_AUD_CNTL_ST);
5845         i |= eldv;
5846         I915_WRITE(G4X_AUD_CNTL_ST, i);
5847 }
5848
5849 static void ironlake_write_eld(struct drm_connector *connector,
5850                                      struct drm_crtc *crtc)
5851 {
5852         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5853         uint8_t *eld = connector->eld;
5854         uint32_t eldv;
5855         uint32_t i;
5856         int len;
5857         int hdmiw_hdmiedid;
5858         int aud_cntl_st;
5859         int aud_cntrl_st2;
5860
5861         if (IS_IVYBRIDGE(connector->dev)) {
5862                 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5863                 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5864                 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5865         } else {
5866                 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5867                 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5868                 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5869         }
5870
5871         i = to_intel_crtc(crtc)->pipe;
5872         hdmiw_hdmiedid += i * 0x100;
5873         aud_cntl_st += i * 0x100;
5874
5875         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5876
5877         i = I915_READ(aud_cntl_st);
5878         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5879         if (!i) {
5880                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5881                 /* operate blindly on all ports */
5882                 eldv = GEN5_ELD_VALIDB;
5883                 eldv |= GEN5_ELD_VALIDB << 4;
5884                 eldv |= GEN5_ELD_VALIDB << 8;
5885         } else {
5886                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5887                 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5888         }
5889
5890         i = I915_READ(aud_cntrl_st2);
5891         i &= ~eldv;
5892         I915_WRITE(aud_cntrl_st2, i);
5893
5894         if (!eld[0])
5895                 return;
5896
5897         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5898                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5899                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5900         }
5901
5902         i = I915_READ(aud_cntl_st);
5903         i &= ~GEN5_ELD_ADDRESS;
5904         I915_WRITE(aud_cntl_st, i);
5905
5906         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5907         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5908         for (i = 0; i < len; i++)
5909                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5910
5911         i = I915_READ(aud_cntrl_st2);
5912         i |= eldv;
5913         I915_WRITE(aud_cntrl_st2, i);
5914 }
5915
5916 void intel_write_eld(struct drm_encoder *encoder,
5917                      struct drm_display_mode *mode)
5918 {
5919         struct drm_crtc *crtc = encoder->crtc;
5920         struct drm_connector *connector;
5921         struct drm_device *dev = encoder->dev;
5922         struct drm_i915_private *dev_priv = dev->dev_private;
5923
5924         connector = drm_select_eld(encoder, mode);
5925         if (!connector)
5926                 return;
5927
5928         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5929                          connector->base.id,
5930                          drm_get_connector_name(connector),
5931                          connector->encoder->base.id,
5932                          drm_get_encoder_name(connector->encoder));
5933
5934         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5935
5936         if (dev_priv->display.write_eld)
5937                 dev_priv->display.write_eld(connector, crtc);
5938 }
5939
5940 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5941 void intel_crtc_load_lut(struct drm_crtc *crtc)
5942 {
5943         struct drm_device *dev = crtc->dev;
5944         struct drm_i915_private *dev_priv = dev->dev_private;
5945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5946         int palreg = PALETTE(intel_crtc->pipe);
5947         int i;
5948
5949         /* The clocks have to be on to load the palette. */
5950         if (!crtc->enabled)
5951                 return;
5952
5953         /* use legacy palette for Ironlake */
5954         if (HAS_PCH_SPLIT(dev))
5955                 palreg = LGC_PALETTE(intel_crtc->pipe);
5956
5957         for (i = 0; i < 256; i++) {
5958                 I915_WRITE(palreg + 4 * i,
5959                            (intel_crtc->lut_r[i] << 16) |
5960                            (intel_crtc->lut_g[i] << 8) |
5961                            intel_crtc->lut_b[i]);
5962         }
5963 }
5964
5965 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5966 {
5967         struct drm_device *dev = crtc->dev;
5968         struct drm_i915_private *dev_priv = dev->dev_private;
5969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970         bool visible = base != 0;
5971         u32 cntl;
5972
5973         if (intel_crtc->cursor_visible == visible)
5974                 return;
5975
5976         cntl = I915_READ(_CURACNTR);
5977         if (visible) {
5978                 /* On these chipsets we can only modify the base whilst
5979                  * the cursor is disabled.
5980                  */
5981                 I915_WRITE(_CURABASE, base);
5982
5983                 cntl &= ~(CURSOR_FORMAT_MASK);
5984                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5985                 cntl |= CURSOR_ENABLE |
5986                         CURSOR_GAMMA_ENABLE |
5987                         CURSOR_FORMAT_ARGB;
5988         } else
5989                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5990         I915_WRITE(_CURACNTR, cntl);
5991
5992         intel_crtc->cursor_visible = visible;
5993 }
5994
5995 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5996 {
5997         struct drm_device *dev = crtc->dev;
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000         int pipe = intel_crtc->pipe;
6001         bool visible = base != 0;
6002
6003         if (intel_crtc->cursor_visible != visible) {
6004                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6005                 if (base) {
6006                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6007                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6008                         cntl |= pipe << 28; /* Connect to correct pipe */
6009                 } else {
6010                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6011                         cntl |= CURSOR_MODE_DISABLE;
6012                 }
6013                 I915_WRITE(CURCNTR(pipe), cntl);
6014
6015                 intel_crtc->cursor_visible = visible;
6016         }
6017         /* and commit changes on next vblank */
6018         I915_WRITE(CURBASE(pipe), base);
6019 }
6020
6021 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6022 {
6023         struct drm_device *dev = crtc->dev;
6024         struct drm_i915_private *dev_priv = dev->dev_private;
6025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6026         int pipe = intel_crtc->pipe;
6027         bool visible = base != 0;
6028
6029         if (intel_crtc->cursor_visible != visible) {
6030                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6031                 if (base) {
6032                         cntl &= ~CURSOR_MODE;
6033                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6034                 } else {
6035                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6036                         cntl |= CURSOR_MODE_DISABLE;
6037                 }
6038                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6039
6040                 intel_crtc->cursor_visible = visible;
6041         }
6042         /* and commit changes on next vblank */
6043         I915_WRITE(CURBASE_IVB(pipe), base);
6044 }
6045
6046 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6047 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6048                                      bool on)
6049 {
6050         struct drm_device *dev = crtc->dev;
6051         struct drm_i915_private *dev_priv = dev->dev_private;
6052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6053         int pipe = intel_crtc->pipe;
6054         int x = intel_crtc->cursor_x;
6055         int y = intel_crtc->cursor_y;
6056         u32 base, pos;
6057         bool visible;
6058
6059         pos = 0;
6060
6061         if (on && crtc->enabled && crtc->fb) {
6062                 base = intel_crtc->cursor_addr;
6063                 if (x > (int) crtc->fb->width)
6064                         base = 0;
6065
6066                 if (y > (int) crtc->fb->height)
6067                         base = 0;
6068         } else
6069                 base = 0;
6070
6071         if (x < 0) {
6072                 if (x + intel_crtc->cursor_width < 0)
6073                         base = 0;
6074
6075                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6076                 x = -x;
6077         }
6078         pos |= x << CURSOR_X_SHIFT;
6079
6080         if (y < 0) {
6081                 if (y + intel_crtc->cursor_height < 0)
6082                         base = 0;
6083
6084                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6085                 y = -y;
6086         }
6087         pos |= y << CURSOR_Y_SHIFT;
6088
6089         visible = base != 0;
6090         if (!visible && !intel_crtc->cursor_visible)
6091                 return;
6092
6093         if (IS_IVYBRIDGE(dev)) {
6094                 I915_WRITE(CURPOS_IVB(pipe), pos);
6095                 ivb_update_cursor(crtc, base);
6096         } else {
6097                 I915_WRITE(CURPOS(pipe), pos);
6098                 if (IS_845G(dev) || IS_I865G(dev))
6099                         i845_update_cursor(crtc, base);
6100                 else
6101                         i9xx_update_cursor(crtc, base);
6102         }
6103
6104         if (visible)
6105                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6106 }
6107
6108 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6109                                  struct drm_file *file,
6110                                  uint32_t handle,
6111                                  uint32_t width, uint32_t height)
6112 {
6113         struct drm_device *dev = crtc->dev;
6114         struct drm_i915_private *dev_priv = dev->dev_private;
6115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6116         struct drm_i915_gem_object *obj;
6117         uint32_t addr;
6118         int ret;
6119
6120         DRM_DEBUG_KMS("\n");
6121
6122         /* if we want to turn off the cursor ignore width and height */
6123         if (!handle) {
6124                 DRM_DEBUG_KMS("cursor off\n");
6125                 addr = 0;
6126                 obj = NULL;
6127                 mutex_lock(&dev->struct_mutex);
6128                 goto finish;
6129         }
6130
6131         /* Currently we only support 64x64 cursors */
6132         if (width != 64 || height != 64) {
6133                 DRM_ERROR("we currently only support 64x64 cursors\n");
6134                 return -EINVAL;
6135         }
6136
6137         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6138         if (&obj->base == NULL)
6139                 return -ENOENT;
6140
6141         if (obj->base.size < width * height * 4) {
6142                 DRM_ERROR("buffer is to small\n");
6143                 ret = -ENOMEM;
6144                 goto fail;
6145         }
6146
6147         /* we only need to pin inside GTT if cursor is non-phy */
6148         mutex_lock(&dev->struct_mutex);
6149         if (!dev_priv->info->cursor_needs_physical) {
6150                 if (obj->tiling_mode) {
6151                         DRM_ERROR("cursor cannot be tiled\n");
6152                         ret = -EINVAL;
6153                         goto fail_locked;
6154                 }
6155
6156                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6157                 if (ret) {
6158                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6159                         goto fail_locked;
6160                 }
6161
6162                 ret = i915_gem_object_put_fence(obj);
6163                 if (ret) {
6164                         DRM_ERROR("failed to release fence for cursor");
6165                         goto fail_unpin;
6166                 }
6167
6168                 addr = obj->gtt_offset;
6169         } else {
6170                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6171                 ret = i915_gem_attach_phys_object(dev, obj,
6172                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6173                                                   align);
6174                 if (ret) {
6175                         DRM_ERROR("failed to attach phys object\n");
6176                         goto fail_locked;
6177                 }
6178                 addr = obj->phys_obj->handle->busaddr;
6179         }
6180
6181         if (IS_GEN2(dev))
6182                 I915_WRITE(CURSIZE, (height << 12) | width);
6183
6184  finish:
6185         if (intel_crtc->cursor_bo) {
6186                 if (dev_priv->info->cursor_needs_physical) {
6187                         if (intel_crtc->cursor_bo != obj)
6188                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6189                 } else
6190                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6191                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6192         }
6193
6194         mutex_unlock(&dev->struct_mutex);
6195
6196         intel_crtc->cursor_addr = addr;
6197         intel_crtc->cursor_bo = obj;
6198         intel_crtc->cursor_width = width;
6199         intel_crtc->cursor_height = height;
6200
6201         intel_crtc_update_cursor(crtc, true);
6202
6203         return 0;
6204 fail_unpin:
6205         i915_gem_object_unpin(obj);
6206 fail_locked:
6207         mutex_unlock(&dev->struct_mutex);
6208 fail:
6209         drm_gem_object_unreference_unlocked(&obj->base);
6210         return ret;
6211 }
6212
6213 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6214 {
6215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216
6217         intel_crtc->cursor_x = x;
6218         intel_crtc->cursor_y = y;
6219
6220         intel_crtc_update_cursor(crtc, true);
6221
6222         return 0;
6223 }
6224
6225 /** Sets the color ramps on behalf of RandR */
6226 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6227                                  u16 blue, int regno)
6228 {
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230
6231         intel_crtc->lut_r[regno] = red >> 8;
6232         intel_crtc->lut_g[regno] = green >> 8;
6233         intel_crtc->lut_b[regno] = blue >> 8;
6234 }
6235
6236 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6237                              u16 *blue, int regno)
6238 {
6239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240
6241         *red = intel_crtc->lut_r[regno] << 8;
6242         *green = intel_crtc->lut_g[regno] << 8;
6243         *blue = intel_crtc->lut_b[regno] << 8;
6244 }
6245
6246 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6247                                  u16 *blue, uint32_t start, uint32_t size)
6248 {
6249         int end = (start + size > 256) ? 256 : start + size, i;
6250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251
6252         for (i = start; i < end; i++) {
6253                 intel_crtc->lut_r[i] = red[i] >> 8;
6254                 intel_crtc->lut_g[i] = green[i] >> 8;
6255                 intel_crtc->lut_b[i] = blue[i] >> 8;
6256         }
6257
6258         intel_crtc_load_lut(crtc);
6259 }
6260
6261 /**
6262  * Get a pipe with a simple mode set on it for doing load-based monitor
6263  * detection.
6264  *
6265  * It will be up to the load-detect code to adjust the pipe as appropriate for
6266  * its requirements.  The pipe will be connected to no other encoders.
6267  *
6268  * Currently this code will only succeed if there is a pipe with no encoders
6269  * configured for it.  In the future, it could choose to temporarily disable
6270  * some outputs to free up a pipe for its use.
6271  *
6272  * \return crtc, or NULL if no pipes are available.
6273  */
6274
6275 /* VESA 640x480x72Hz mode to set on the pipe */
6276 static struct drm_display_mode load_detect_mode = {
6277         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6278                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6279 };
6280
6281 static struct drm_framebuffer *
6282 intel_framebuffer_create(struct drm_device *dev,
6283                          struct drm_mode_fb_cmd *mode_cmd,
6284                          struct drm_i915_gem_object *obj)
6285 {
6286         struct intel_framebuffer *intel_fb;
6287         int ret;
6288
6289         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6290         if (!intel_fb) {
6291                 drm_gem_object_unreference_unlocked(&obj->base);
6292                 return ERR_PTR(-ENOMEM);
6293         }
6294
6295         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6296         if (ret) {
6297                 drm_gem_object_unreference_unlocked(&obj->base);
6298                 kfree(intel_fb);
6299                 return ERR_PTR(ret);
6300         }
6301
6302         return &intel_fb->base;
6303 }
6304
6305 static u32
6306 intel_framebuffer_pitch_for_width(int width, int bpp)
6307 {
6308         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6309         return ALIGN(pitch, 64);
6310 }
6311
6312 static u32
6313 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6314 {
6315         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6316         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6317 }
6318
6319 static struct drm_framebuffer *
6320 intel_framebuffer_create_for_mode(struct drm_device *dev,
6321                                   struct drm_display_mode *mode,
6322                                   int depth, int bpp)
6323 {
6324         struct drm_i915_gem_object *obj;
6325         struct drm_mode_fb_cmd mode_cmd;
6326
6327         obj = i915_gem_alloc_object(dev,
6328                                     intel_framebuffer_size_for_mode(mode, bpp));
6329         if (obj == NULL)
6330                 return ERR_PTR(-ENOMEM);
6331
6332         mode_cmd.width = mode->hdisplay;
6333         mode_cmd.height = mode->vdisplay;
6334         mode_cmd.depth = depth;
6335         mode_cmd.bpp = bpp;
6336         mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6337
6338         return intel_framebuffer_create(dev, &mode_cmd, obj);
6339 }
6340
6341 static struct drm_framebuffer *
6342 mode_fits_in_fbdev(struct drm_device *dev,
6343                    struct drm_display_mode *mode)
6344 {
6345         struct drm_i915_private *dev_priv = dev->dev_private;
6346         struct drm_i915_gem_object *obj;
6347         struct drm_framebuffer *fb;
6348
6349         if (dev_priv->fbdev == NULL)
6350                 return NULL;
6351
6352         obj = dev_priv->fbdev->ifb.obj;
6353         if (obj == NULL)
6354                 return NULL;
6355
6356         fb = &dev_priv->fbdev->ifb.base;
6357         if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6358                                                           fb->bits_per_pixel))
6359                 return NULL;
6360
6361         if (obj->base.size < mode->vdisplay * fb->pitch)
6362                 return NULL;
6363
6364         return fb;
6365 }
6366
6367 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6368                                 struct drm_connector *connector,
6369                                 struct drm_display_mode *mode,
6370                                 struct intel_load_detect_pipe *old)
6371 {
6372         struct intel_crtc *intel_crtc;
6373         struct drm_crtc *possible_crtc;
6374         struct drm_encoder *encoder = &intel_encoder->base;
6375         struct drm_crtc *crtc = NULL;
6376         struct drm_device *dev = encoder->dev;
6377         struct drm_framebuffer *old_fb;
6378         int i = -1;
6379
6380         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6381                       connector->base.id, drm_get_connector_name(connector),
6382                       encoder->base.id, drm_get_encoder_name(encoder));
6383
6384         /*
6385          * Algorithm gets a little messy:
6386          *
6387          *   - if the connector already has an assigned crtc, use it (but make
6388          *     sure it's on first)
6389          *
6390          *   - try to find the first unused crtc that can drive this connector,
6391          *     and use that if we find one
6392          */
6393
6394         /* See if we already have a CRTC for this connector */
6395         if (encoder->crtc) {
6396                 crtc = encoder->crtc;
6397
6398                 intel_crtc = to_intel_crtc(crtc);
6399                 old->dpms_mode = intel_crtc->dpms_mode;
6400                 old->load_detect_temp = false;
6401
6402                 /* Make sure the crtc and connector are running */
6403                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6404                         struct drm_encoder_helper_funcs *encoder_funcs;
6405                         struct drm_crtc_helper_funcs *crtc_funcs;
6406
6407                         crtc_funcs = crtc->helper_private;
6408                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6409
6410                         encoder_funcs = encoder->helper_private;
6411                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6412                 }
6413
6414                 return true;
6415         }
6416
6417         /* Find an unused one (if possible) */
6418         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6419                 i++;
6420                 if (!(encoder->possible_crtcs & (1 << i)))
6421                         continue;
6422                 if (!possible_crtc->enabled) {
6423                         crtc = possible_crtc;
6424                         break;
6425                 }
6426         }
6427
6428         /*
6429          * If we didn't find an unused CRTC, don't use any.
6430          */
6431         if (!crtc) {
6432                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6433                 return false;
6434         }
6435
6436         encoder->crtc = crtc;
6437         connector->encoder = encoder;
6438
6439         intel_crtc = to_intel_crtc(crtc);
6440         old->dpms_mode = intel_crtc->dpms_mode;
6441         old->load_detect_temp = true;
6442         old->release_fb = NULL;
6443
6444         if (!mode)
6445                 mode = &load_detect_mode;
6446
6447         old_fb = crtc->fb;
6448
6449         /* We need a framebuffer large enough to accommodate all accesses
6450          * that the plane may generate whilst we perform load detection.
6451          * We can not rely on the fbcon either being present (we get called
6452          * during its initialisation to detect all boot displays, or it may
6453          * not even exist) or that it is large enough to satisfy the
6454          * requested mode.
6455          */
6456         crtc->fb = mode_fits_in_fbdev(dev, mode);
6457         if (crtc->fb == NULL) {
6458                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6459                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6460                 old->release_fb = crtc->fb;
6461         } else
6462                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6463         if (IS_ERR(crtc->fb)) {
6464                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6465                 crtc->fb = old_fb;
6466                 return false;
6467         }
6468
6469         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6470                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6471                 if (old->release_fb)
6472                         old->release_fb->funcs->destroy(old->release_fb);
6473                 crtc->fb = old_fb;
6474                 return false;
6475         }
6476
6477         /* let the connector get through one full cycle before testing */
6478         intel_wait_for_vblank(dev, intel_crtc->pipe);
6479
6480         return true;
6481 }
6482
6483 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6484                                     struct drm_connector *connector,
6485                                     struct intel_load_detect_pipe *old)
6486 {
6487         struct drm_encoder *encoder = &intel_encoder->base;
6488         struct drm_device *dev = encoder->dev;
6489         struct drm_crtc *crtc = encoder->crtc;
6490         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6491         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6492
6493         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6494                       connector->base.id, drm_get_connector_name(connector),
6495                       encoder->base.id, drm_get_encoder_name(encoder));
6496
6497         if (old->load_detect_temp) {
6498                 connector->encoder = NULL;
6499                 drm_helper_disable_unused_functions(dev);
6500
6501                 if (old->release_fb)
6502                         old->release_fb->funcs->destroy(old->release_fb);
6503
6504                 return;
6505         }
6506
6507         /* Switch crtc and encoder back off if necessary */
6508         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6509                 encoder_funcs->dpms(encoder, old->dpms_mode);
6510                 crtc_funcs->dpms(crtc, old->dpms_mode);
6511         }
6512 }
6513
6514 /* Returns the clock of the currently programmed mode of the given pipe. */
6515 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6516 {
6517         struct drm_i915_private *dev_priv = dev->dev_private;
6518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6519         int pipe = intel_crtc->pipe;
6520         u32 dpll = I915_READ(DPLL(pipe));
6521         u32 fp;
6522         intel_clock_t clock;
6523
6524         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6525                 fp = I915_READ(FP0(pipe));
6526         else
6527                 fp = I915_READ(FP1(pipe));
6528
6529         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6530         if (IS_PINEVIEW(dev)) {
6531                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6532                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6533         } else {
6534                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6535                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6536         }
6537
6538         if (!IS_GEN2(dev)) {
6539                 if (IS_PINEVIEW(dev))
6540                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6541                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6542                 else
6543                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6544                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6545
6546                 switch (dpll & DPLL_MODE_MASK) {
6547                 case DPLLB_MODE_DAC_SERIAL:
6548                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6549                                 5 : 10;
6550                         break;
6551                 case DPLLB_MODE_LVDS:
6552                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6553                                 7 : 14;
6554                         break;
6555                 default:
6556                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6557                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6558                         return 0;
6559                 }
6560
6561                 /* XXX: Handle the 100Mhz refclk */
6562                 intel_clock(dev, 96000, &clock);
6563         } else {
6564                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6565
6566                 if (is_lvds) {
6567                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6568                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6569                         clock.p2 = 14;
6570
6571                         if ((dpll & PLL_REF_INPUT_MASK) ==
6572                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6573                                 /* XXX: might not be 66MHz */
6574                                 intel_clock(dev, 66000, &clock);
6575                         } else
6576                                 intel_clock(dev, 48000, &clock);
6577                 } else {
6578                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6579                                 clock.p1 = 2;
6580                         else {
6581                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6582                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6583                         }
6584                         if (dpll & PLL_P2_DIVIDE_BY_4)
6585                                 clock.p2 = 4;
6586                         else
6587                                 clock.p2 = 2;
6588
6589                         intel_clock(dev, 48000, &clock);
6590                 }
6591         }
6592
6593         /* XXX: It would be nice to validate the clocks, but we can't reuse
6594          * i830PllIsValid() because it relies on the xf86_config connector
6595          * configuration being accurate, which it isn't necessarily.
6596          */
6597
6598         return clock.dot;
6599 }
6600
6601 /** Returns the currently programmed mode of the given pipe. */
6602 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6603                                              struct drm_crtc *crtc)
6604 {
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6607         int pipe = intel_crtc->pipe;
6608         struct drm_display_mode *mode;
6609         int htot = I915_READ(HTOTAL(pipe));
6610         int hsync = I915_READ(HSYNC(pipe));
6611         int vtot = I915_READ(VTOTAL(pipe));
6612         int vsync = I915_READ(VSYNC(pipe));
6613
6614         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6615         if (!mode)
6616                 return NULL;
6617
6618         mode->clock = intel_crtc_clock_get(dev, crtc);
6619         mode->hdisplay = (htot & 0xffff) + 1;
6620         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6621         mode->hsync_start = (hsync & 0xffff) + 1;
6622         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6623         mode->vdisplay = (vtot & 0xffff) + 1;
6624         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6625         mode->vsync_start = (vsync & 0xffff) + 1;
6626         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6627
6628         drm_mode_set_name(mode);
6629         drm_mode_set_crtcinfo(mode, 0);
6630
6631         return mode;
6632 }
6633
6634 #define GPU_IDLE_TIMEOUT 500 /* ms */
6635
6636 /* When this timer fires, we've been idle for awhile */
6637 static void intel_gpu_idle_timer(unsigned long arg)
6638 {
6639         struct drm_device *dev = (struct drm_device *)arg;
6640         drm_i915_private_t *dev_priv = dev->dev_private;
6641
6642         if (!list_empty(&dev_priv->mm.active_list)) {
6643                 /* Still processing requests, so just re-arm the timer. */
6644                 mod_timer(&dev_priv->idle_timer, jiffies +
6645                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6646                 return;
6647         }
6648
6649         dev_priv->busy = false;
6650         queue_work(dev_priv->wq, &dev_priv->idle_work);
6651 }
6652
6653 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6654
6655 static void intel_crtc_idle_timer(unsigned long arg)
6656 {
6657         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6658         struct drm_crtc *crtc = &intel_crtc->base;
6659         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6660         struct intel_framebuffer *intel_fb;
6661
6662         intel_fb = to_intel_framebuffer(crtc->fb);
6663         if (intel_fb && intel_fb->obj->active) {
6664                 /* The framebuffer is still being accessed by the GPU. */
6665                 mod_timer(&intel_crtc->idle_timer, jiffies +
6666                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6667                 return;
6668         }
6669
6670         intel_crtc->busy = false;
6671         queue_work(dev_priv->wq, &dev_priv->idle_work);
6672 }
6673
6674 static void intel_increase_pllclock(struct drm_crtc *crtc)
6675 {
6676         struct drm_device *dev = crtc->dev;
6677         drm_i915_private_t *dev_priv = dev->dev_private;
6678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6679         int pipe = intel_crtc->pipe;
6680         int dpll_reg = DPLL(pipe);
6681         int dpll;
6682
6683         if (HAS_PCH_SPLIT(dev))
6684                 return;
6685
6686         if (!dev_priv->lvds_downclock_avail)
6687                 return;
6688
6689         dpll = I915_READ(dpll_reg);
6690         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6691                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6692
6693                 /* Unlock panel regs */
6694                 I915_WRITE(PP_CONTROL,
6695                            I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6696
6697                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6698                 I915_WRITE(dpll_reg, dpll);
6699                 intel_wait_for_vblank(dev, pipe);
6700
6701                 dpll = I915_READ(dpll_reg);
6702                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6703                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6704
6705                 /* ...and lock them again */
6706                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6707         }
6708
6709         /* Schedule downclock */
6710         mod_timer(&intel_crtc->idle_timer, jiffies +
6711                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6712 }
6713
6714 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6715 {
6716         struct drm_device *dev = crtc->dev;
6717         drm_i915_private_t *dev_priv = dev->dev_private;
6718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6719         int pipe = intel_crtc->pipe;
6720         int dpll_reg = DPLL(pipe);
6721         int dpll = I915_READ(dpll_reg);
6722
6723         if (HAS_PCH_SPLIT(dev))
6724                 return;
6725
6726         if (!dev_priv->lvds_downclock_avail)
6727                 return;
6728
6729         /*
6730          * Since this is called by a timer, we should never get here in
6731          * the manual case.
6732          */
6733         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6734                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6735
6736                 /* Unlock panel regs */
6737                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6738                            PANEL_UNLOCK_REGS);
6739
6740                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6741                 I915_WRITE(dpll_reg, dpll);
6742                 intel_wait_for_vblank(dev, pipe);
6743                 dpll = I915_READ(dpll_reg);
6744                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6745                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6746
6747                 /* ...and lock them again */
6748                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6749         }
6750
6751 }
6752
6753 /**
6754  * intel_idle_update - adjust clocks for idleness
6755  * @work: work struct
6756  *
6757  * Either the GPU or display (or both) went idle.  Check the busy status
6758  * here and adjust the CRTC and GPU clocks as necessary.
6759  */
6760 static void intel_idle_update(struct work_struct *work)
6761 {
6762         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6763                                                     idle_work);
6764         struct drm_device *dev = dev_priv->dev;
6765         struct drm_crtc *crtc;
6766         struct intel_crtc *intel_crtc;
6767
6768         if (!i915_powersave)
6769                 return;
6770
6771         mutex_lock(&dev->struct_mutex);
6772
6773         i915_update_gfx_val(dev_priv);
6774
6775         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6776                 /* Skip inactive CRTCs */
6777                 if (!crtc->fb)
6778                         continue;
6779
6780                 intel_crtc = to_intel_crtc(crtc);
6781                 if (!intel_crtc->busy)
6782                         intel_decrease_pllclock(crtc);
6783         }
6784
6785
6786         mutex_unlock(&dev->struct_mutex);
6787 }
6788
6789 /**
6790  * intel_mark_busy - mark the GPU and possibly the display busy
6791  * @dev: drm device
6792  * @obj: object we're operating on
6793  *
6794  * Callers can use this function to indicate that the GPU is busy processing
6795  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6796  * buffer), we'll also mark the display as busy, so we know to increase its
6797  * clock frequency.
6798  */
6799 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6800 {
6801         drm_i915_private_t *dev_priv = dev->dev_private;
6802         struct drm_crtc *crtc = NULL;
6803         struct intel_framebuffer *intel_fb;
6804         struct intel_crtc *intel_crtc;
6805
6806         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6807                 return;
6808
6809         if (!dev_priv->busy)
6810                 dev_priv->busy = true;
6811         else
6812                 mod_timer(&dev_priv->idle_timer, jiffies +
6813                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6814
6815         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6816                 if (!crtc->fb)
6817                         continue;
6818
6819                 intel_crtc = to_intel_crtc(crtc);
6820                 intel_fb = to_intel_framebuffer(crtc->fb);
6821                 if (intel_fb->obj == obj) {
6822                         if (!intel_crtc->busy) {
6823                                 /* Non-busy -> busy, upclock */
6824                                 intel_increase_pllclock(crtc);
6825                                 intel_crtc->busy = true;
6826                         } else {
6827                                 /* Busy -> busy, put off timer */
6828                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6829                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6830                         }
6831                 }
6832         }
6833 }
6834
6835 static void intel_crtc_destroy(struct drm_crtc *crtc)
6836 {
6837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838         struct drm_device *dev = crtc->dev;
6839         struct intel_unpin_work *work;
6840         unsigned long flags;
6841
6842         spin_lock_irqsave(&dev->event_lock, flags);
6843         work = intel_crtc->unpin_work;
6844         intel_crtc->unpin_work = NULL;
6845         spin_unlock_irqrestore(&dev->event_lock, flags);
6846
6847         if (work) {
6848                 cancel_work_sync(&work->work);
6849                 kfree(work);
6850         }
6851
6852         drm_crtc_cleanup(crtc);
6853
6854         kfree(intel_crtc);
6855 }
6856
6857 static void intel_unpin_work_fn(struct work_struct *__work)
6858 {
6859         struct intel_unpin_work *work =
6860                 container_of(__work, struct intel_unpin_work, work);
6861
6862         mutex_lock(&work->dev->struct_mutex);
6863         i915_gem_object_unpin(work->old_fb_obj);
6864         drm_gem_object_unreference(&work->pending_flip_obj->base);
6865         drm_gem_object_unreference(&work->old_fb_obj->base);
6866
6867         intel_update_fbc(work->dev);
6868         mutex_unlock(&work->dev->struct_mutex);
6869         kfree(work);
6870 }
6871
6872 static void do_intel_finish_page_flip(struct drm_device *dev,
6873                                       struct drm_crtc *crtc)
6874 {
6875         drm_i915_private_t *dev_priv = dev->dev_private;
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         struct intel_unpin_work *work;
6878         struct drm_i915_gem_object *obj;
6879         struct drm_pending_vblank_event *e;
6880         struct timeval tnow, tvbl;
6881         unsigned long flags;
6882
6883         /* Ignore early vblank irqs */
6884         if (intel_crtc == NULL)
6885                 return;
6886
6887         do_gettimeofday(&tnow);
6888
6889         spin_lock_irqsave(&dev->event_lock, flags);
6890         work = intel_crtc->unpin_work;
6891         if (work == NULL || !work->pending) {
6892                 spin_unlock_irqrestore(&dev->event_lock, flags);
6893                 return;
6894         }
6895
6896         intel_crtc->unpin_work = NULL;
6897
6898         if (work->event) {
6899                 e = work->event;
6900                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6901
6902                 /* Called before vblank count and timestamps have
6903                  * been updated for the vblank interval of flip
6904                  * completion? Need to increment vblank count and
6905                  * add one videorefresh duration to returned timestamp
6906                  * to account for this. We assume this happened if we
6907                  * get called over 0.9 frame durations after the last
6908                  * timestamped vblank.
6909                  *
6910                  * This calculation can not be used with vrefresh rates
6911                  * below 5Hz (10Hz to be on the safe side) without
6912                  * promoting to 64 integers.
6913                  */
6914                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6915                     9 * crtc->framedur_ns) {
6916                         e->event.sequence++;
6917                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6918                                              crtc->framedur_ns);
6919                 }
6920
6921                 e->event.tv_sec = tvbl.tv_sec;
6922                 e->event.tv_usec = tvbl.tv_usec;
6923
6924                 list_add_tail(&e->base.link,
6925                               &e->base.file_priv->event_list);
6926                 wake_up_interruptible(&e->base.file_priv->event_wait);
6927         }
6928
6929         drm_vblank_put(dev, intel_crtc->pipe);
6930
6931         spin_unlock_irqrestore(&dev->event_lock, flags);
6932
6933         obj = work->old_fb_obj;
6934
6935         atomic_clear_mask(1 << intel_crtc->plane,
6936                           &obj->pending_flip.counter);
6937         if (atomic_read(&obj->pending_flip) == 0)
6938                 wake_up(&dev_priv->pending_flip_queue);
6939
6940         schedule_work(&work->work);
6941
6942         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6943 }
6944
6945 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6946 {
6947         drm_i915_private_t *dev_priv = dev->dev_private;
6948         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6949
6950         do_intel_finish_page_flip(dev, crtc);
6951 }
6952
6953 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6954 {
6955         drm_i915_private_t *dev_priv = dev->dev_private;
6956         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6957
6958         do_intel_finish_page_flip(dev, crtc);
6959 }
6960
6961 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6962 {
6963         drm_i915_private_t *dev_priv = dev->dev_private;
6964         struct intel_crtc *intel_crtc =
6965                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6966         unsigned long flags;
6967
6968         spin_lock_irqsave(&dev->event_lock, flags);
6969         if (intel_crtc->unpin_work) {
6970                 if ((++intel_crtc->unpin_work->pending) > 1)
6971                         DRM_ERROR("Prepared flip multiple times\n");
6972         } else {
6973                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6974         }
6975         spin_unlock_irqrestore(&dev->event_lock, flags);
6976 }
6977
6978 static int intel_gen2_queue_flip(struct drm_device *dev,
6979                                  struct drm_crtc *crtc,
6980                                  struct drm_framebuffer *fb,
6981                                  struct drm_i915_gem_object *obj)
6982 {
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6985         unsigned long offset;
6986         u32 flip_mask;
6987         int ret;
6988
6989         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6990         if (ret)
6991                 goto out;
6992
6993         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6994         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6995
6996         ret = BEGIN_LP_RING(6);
6997         if (ret)
6998                 goto out;
6999
7000         /* Can't queue multiple flips, so wait for the previous
7001          * one to finish before executing the next.
7002          */
7003         if (intel_crtc->plane)
7004                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7005         else
7006                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7007         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7008         OUT_RING(MI_NOOP);
7009         OUT_RING(MI_DISPLAY_FLIP |
7010                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7011         OUT_RING(fb->pitch);
7012         OUT_RING(obj->gtt_offset + offset);
7013         OUT_RING(MI_NOOP);
7014         ADVANCE_LP_RING();
7015 out:
7016         return ret;
7017 }
7018
7019 static int intel_gen3_queue_flip(struct drm_device *dev,
7020                                  struct drm_crtc *crtc,
7021                                  struct drm_framebuffer *fb,
7022                                  struct drm_i915_gem_object *obj)
7023 {
7024         struct drm_i915_private *dev_priv = dev->dev_private;
7025         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7026         unsigned long offset;
7027         u32 flip_mask;
7028         int ret;
7029
7030         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7031         if (ret)
7032                 goto out;
7033
7034         /* Offset into the new buffer for cases of shared fbs between CRTCs */
7035         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7036
7037         ret = BEGIN_LP_RING(6);
7038         if (ret)
7039                 goto out;
7040
7041         if (intel_crtc->plane)
7042                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7043         else
7044                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7045         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7046         OUT_RING(MI_NOOP);
7047         OUT_RING(MI_DISPLAY_FLIP_I915 |
7048                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7049         OUT_RING(fb->pitch);
7050         OUT_RING(obj->gtt_offset + offset);
7051         OUT_RING(MI_NOOP);
7052
7053         ADVANCE_LP_RING();
7054 out:
7055         return ret;
7056 }
7057
7058 static int intel_gen4_queue_flip(struct drm_device *dev,
7059                                  struct drm_crtc *crtc,
7060                                  struct drm_framebuffer *fb,
7061                                  struct drm_i915_gem_object *obj)
7062 {
7063         struct drm_i915_private *dev_priv = dev->dev_private;
7064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065         uint32_t pf, pipesrc;
7066         int ret;
7067
7068         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7069         if (ret)
7070                 goto out;
7071
7072         ret = BEGIN_LP_RING(4);
7073         if (ret)
7074                 goto out;
7075
7076         /* i965+ uses the linear or tiled offsets from the
7077          * Display Registers (which do not change across a page-flip)
7078          * so we need only reprogram the base address.
7079          */
7080         OUT_RING(MI_DISPLAY_FLIP |
7081                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7082         OUT_RING(fb->pitch);
7083         OUT_RING(obj->gtt_offset | obj->tiling_mode);
7084
7085         /* XXX Enabling the panel-fitter across page-flip is so far
7086          * untested on non-native modes, so ignore it for now.
7087          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7088          */
7089         pf = 0;
7090         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7091         OUT_RING(pf | pipesrc);
7092         ADVANCE_LP_RING();
7093 out:
7094         return ret;
7095 }
7096
7097 static int intel_gen6_queue_flip(struct drm_device *dev,
7098                                  struct drm_crtc *crtc,
7099                                  struct drm_framebuffer *fb,
7100                                  struct drm_i915_gem_object *obj)
7101 {
7102         struct drm_i915_private *dev_priv = dev->dev_private;
7103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104         uint32_t pf, pipesrc;
7105         int ret;
7106
7107         ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7108         if (ret)
7109                 goto out;
7110
7111         ret = BEGIN_LP_RING(4);
7112         if (ret)
7113                 goto out;
7114
7115         OUT_RING(MI_DISPLAY_FLIP |
7116                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7117         OUT_RING(fb->pitch | obj->tiling_mode);
7118         OUT_RING(obj->gtt_offset);
7119
7120         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7121         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7122         OUT_RING(pf | pipesrc);
7123         ADVANCE_LP_RING();
7124 out:
7125         return ret;
7126 }
7127
7128 /*
7129  * On gen7 we currently use the blit ring because (in early silicon at least)
7130  * the render ring doesn't give us interrpts for page flip completion, which
7131  * means clients will hang after the first flip is queued.  Fortunately the
7132  * blit ring generates interrupts properly, so use it instead.
7133  */
7134 static int intel_gen7_queue_flip(struct drm_device *dev,
7135                                  struct drm_crtc *crtc,
7136                                  struct drm_framebuffer *fb,
7137                                  struct drm_i915_gem_object *obj)
7138 {
7139         struct drm_i915_private *dev_priv = dev->dev_private;
7140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7141         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7142         int ret;
7143
7144         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7145         if (ret)
7146                 goto out;
7147
7148         ret = intel_ring_begin(ring, 4);
7149         if (ret)
7150                 goto out;
7151
7152         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7153         intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7154         intel_ring_emit(ring, (obj->gtt_offset));
7155         intel_ring_emit(ring, (MI_NOOP));
7156         intel_ring_advance(ring);
7157 out:
7158         return ret;
7159 }
7160
7161 static int intel_default_queue_flip(struct drm_device *dev,
7162                                     struct drm_crtc *crtc,
7163                                     struct drm_framebuffer *fb,
7164                                     struct drm_i915_gem_object *obj)
7165 {
7166         return -ENODEV;
7167 }
7168
7169 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7170                                 struct drm_framebuffer *fb,
7171                                 struct drm_pending_vblank_event *event)
7172 {
7173         struct drm_device *dev = crtc->dev;
7174         struct drm_i915_private *dev_priv = dev->dev_private;
7175         struct intel_framebuffer *intel_fb;
7176         struct drm_i915_gem_object *obj;
7177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178         struct intel_unpin_work *work;
7179         unsigned long flags;
7180         int ret;
7181
7182         work = kzalloc(sizeof *work, GFP_KERNEL);
7183         if (work == NULL)
7184                 return -ENOMEM;
7185
7186         work->event = event;
7187         work->dev = crtc->dev;
7188         intel_fb = to_intel_framebuffer(crtc->fb);
7189         work->old_fb_obj = intel_fb->obj;
7190         INIT_WORK(&work->work, intel_unpin_work_fn);
7191
7192         /* We borrow the event spin lock for protecting unpin_work */
7193         spin_lock_irqsave(&dev->event_lock, flags);
7194         if (intel_crtc->unpin_work) {
7195                 spin_unlock_irqrestore(&dev->event_lock, flags);
7196                 kfree(work);
7197
7198                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7199                 return -EBUSY;
7200         }
7201         intel_crtc->unpin_work = work;
7202         spin_unlock_irqrestore(&dev->event_lock, flags);
7203
7204         intel_fb = to_intel_framebuffer(fb);
7205         obj = intel_fb->obj;
7206
7207         mutex_lock(&dev->struct_mutex);
7208
7209         /* Reference the objects for the scheduled work. */
7210         drm_gem_object_reference(&work->old_fb_obj->base);
7211         drm_gem_object_reference(&obj->base);
7212
7213         crtc->fb = fb;
7214
7215         ret = drm_vblank_get(dev, intel_crtc->pipe);
7216         if (ret)
7217                 goto cleanup_objs;
7218
7219         work->pending_flip_obj = obj;
7220
7221         work->enable_stall_check = true;
7222
7223         /* Block clients from rendering to the new back buffer until
7224          * the flip occurs and the object is no longer visible.
7225          */
7226         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7227
7228         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7229         if (ret)
7230                 goto cleanup_pending;
7231
7232         intel_disable_fbc(dev);
7233         mutex_unlock(&dev->struct_mutex);
7234
7235         trace_i915_flip_request(intel_crtc->plane, obj);
7236
7237         return 0;
7238
7239 cleanup_pending:
7240         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7241 cleanup_objs:
7242         drm_gem_object_unreference(&work->old_fb_obj->base);
7243         drm_gem_object_unreference(&obj->base);
7244         mutex_unlock(&dev->struct_mutex);
7245
7246         spin_lock_irqsave(&dev->event_lock, flags);
7247         intel_crtc->unpin_work = NULL;
7248         spin_unlock_irqrestore(&dev->event_lock, flags);
7249
7250         kfree(work);
7251
7252         return ret;
7253 }
7254
7255 static void intel_sanitize_modesetting(struct drm_device *dev,
7256                                        int pipe, int plane)
7257 {
7258         struct drm_i915_private *dev_priv = dev->dev_private;
7259         u32 reg, val;
7260
7261         if (HAS_PCH_SPLIT(dev))
7262                 return;
7263
7264         /* Who knows what state these registers were left in by the BIOS or
7265          * grub?
7266          *
7267          * If we leave the registers in a conflicting state (e.g. with the
7268          * display plane reading from the other pipe than the one we intend
7269          * to use) then when we attempt to teardown the active mode, we will
7270          * not disable the pipes and planes in the correct order -- leaving
7271          * a plane reading from a disabled pipe and possibly leading to
7272          * undefined behaviour.
7273          */
7274
7275         reg = DSPCNTR(plane);
7276         val = I915_READ(reg);
7277
7278         if ((val & DISPLAY_PLANE_ENABLE) == 0)
7279                 return;
7280         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7281                 return;
7282
7283         /* This display plane is active and attached to the other CPU pipe. */
7284         pipe = !pipe;
7285
7286         /* Disable the plane and wait for it to stop reading from the pipe. */
7287         intel_disable_plane(dev_priv, plane, pipe);
7288         intel_disable_pipe(dev_priv, pipe);
7289 }
7290
7291 static void intel_crtc_reset(struct drm_crtc *crtc)
7292 {
7293         struct drm_device *dev = crtc->dev;
7294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7295
7296         /* Reset flags back to the 'unknown' status so that they
7297          * will be correctly set on the initial modeset.
7298          */
7299         intel_crtc->dpms_mode = -1;
7300
7301         /* We need to fix up any BIOS configuration that conflicts with
7302          * our expectations.
7303          */
7304         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7305 }
7306
7307 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7308         .dpms = intel_crtc_dpms,
7309         .mode_fixup = intel_crtc_mode_fixup,
7310         .mode_set = intel_crtc_mode_set,
7311         .mode_set_base = intel_pipe_set_base,
7312         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7313         .load_lut = intel_crtc_load_lut,
7314         .disable = intel_crtc_disable,
7315 };
7316
7317 static const struct drm_crtc_funcs intel_crtc_funcs = {
7318         .reset = intel_crtc_reset,
7319         .cursor_set = intel_crtc_cursor_set,
7320         .cursor_move = intel_crtc_cursor_move,
7321         .gamma_set = intel_crtc_gamma_set,
7322         .set_config = drm_crtc_helper_set_config,
7323         .destroy = intel_crtc_destroy,
7324         .page_flip = intel_crtc_page_flip,
7325 };
7326
7327 static void intel_crtc_init(struct drm_device *dev, int pipe)
7328 {
7329         drm_i915_private_t *dev_priv = dev->dev_private;
7330         struct intel_crtc *intel_crtc;
7331         int i;
7332
7333         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7334         if (intel_crtc == NULL)
7335                 return;
7336
7337         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7338
7339         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7340         for (i = 0; i < 256; i++) {
7341                 intel_crtc->lut_r[i] = i;
7342                 intel_crtc->lut_g[i] = i;
7343                 intel_crtc->lut_b[i] = i;
7344         }
7345
7346         /* Swap pipes & planes for FBC on pre-965 */
7347         intel_crtc->pipe = pipe;
7348         intel_crtc->plane = pipe;
7349         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7350                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7351                 intel_crtc->plane = !pipe;
7352         }
7353
7354         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7355                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7356         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7357         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7358
7359         intel_crtc_reset(&intel_crtc->base);
7360         intel_crtc->active = true; /* force the pipe off on setup_init_config */
7361         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7362
7363         if (HAS_PCH_SPLIT(dev)) {
7364                 if (pipe == 2 && IS_IVYBRIDGE(dev))
7365                         intel_crtc->no_pll = true;
7366                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7367                 intel_helper_funcs.commit = ironlake_crtc_commit;
7368         } else {
7369                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7370                 intel_helper_funcs.commit = i9xx_crtc_commit;
7371         }
7372
7373         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7374
7375         intel_crtc->busy = false;
7376
7377         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7378                     (unsigned long)intel_crtc);
7379 }
7380
7381 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7382                                 struct drm_file *file)
7383 {
7384         drm_i915_private_t *dev_priv = dev->dev_private;
7385         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7386         struct drm_mode_object *drmmode_obj;
7387         struct intel_crtc *crtc;
7388
7389         if (!dev_priv) {
7390                 DRM_ERROR("called with no initialization\n");
7391                 return -EINVAL;
7392         }
7393
7394         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7395                         DRM_MODE_OBJECT_CRTC);
7396
7397         if (!drmmode_obj) {
7398                 DRM_ERROR("no such CRTC id\n");
7399                 return -EINVAL;
7400         }
7401
7402         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7403         pipe_from_crtc_id->pipe = crtc->pipe;
7404
7405         return 0;
7406 }
7407
7408 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7409 {
7410         struct intel_encoder *encoder;
7411         int index_mask = 0;
7412         int entry = 0;
7413
7414         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7415                 if (type_mask & encoder->clone_mask)
7416                         index_mask |= (1 << entry);
7417                 entry++;
7418         }
7419
7420         return index_mask;
7421 }
7422
7423 static bool has_edp_a(struct drm_device *dev)
7424 {
7425         struct drm_i915_private *dev_priv = dev->dev_private;
7426
7427         if (!IS_MOBILE(dev))
7428                 return false;
7429
7430         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7431                 return false;
7432
7433         if (IS_GEN5(dev) &&
7434             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7435                 return false;
7436
7437         return true;
7438 }
7439
7440 static void intel_setup_outputs(struct drm_device *dev)
7441 {
7442         struct drm_i915_private *dev_priv = dev->dev_private;
7443         struct intel_encoder *encoder;
7444         bool dpd_is_edp = false;
7445         bool has_lvds = false;
7446
7447         if (IS_MOBILE(dev) && !IS_I830(dev))
7448                 has_lvds = intel_lvds_init(dev);
7449         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7450                 /* disable the panel fitter on everything but LVDS */
7451                 I915_WRITE(PFIT_CONTROL, 0);
7452         }
7453
7454         if (HAS_PCH_SPLIT(dev)) {
7455                 dpd_is_edp = intel_dpd_is_edp(dev);
7456
7457                 if (has_edp_a(dev))
7458                         intel_dp_init(dev, DP_A);
7459
7460                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7461                         intel_dp_init(dev, PCH_DP_D);
7462         }
7463
7464         intel_crt_init(dev);
7465
7466         if (HAS_PCH_SPLIT(dev)) {
7467                 int found;
7468
7469                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7470                         /* PCH SDVOB multiplex with HDMIB */
7471                         found = intel_sdvo_init(dev, PCH_SDVOB);
7472                         if (!found)
7473                                 intel_hdmi_init(dev, HDMIB);
7474                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7475                                 intel_dp_init(dev, PCH_DP_B);
7476                 }
7477
7478                 if (I915_READ(HDMIC) & PORT_DETECTED)
7479                         intel_hdmi_init(dev, HDMIC);
7480
7481                 if (I915_READ(HDMID) & PORT_DETECTED)
7482                         intel_hdmi_init(dev, HDMID);
7483
7484                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7485                         intel_dp_init(dev, PCH_DP_C);
7486
7487                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7488                         intel_dp_init(dev, PCH_DP_D);
7489
7490         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7491                 bool found = false;
7492
7493                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7494                         DRM_DEBUG_KMS("probing SDVOB\n");
7495                         found = intel_sdvo_init(dev, SDVOB);
7496                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7497                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7498                                 intel_hdmi_init(dev, SDVOB);
7499                         }
7500
7501                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7502                                 DRM_DEBUG_KMS("probing DP_B\n");
7503                                 intel_dp_init(dev, DP_B);
7504                         }
7505                 }
7506
7507                 /* Before G4X SDVOC doesn't have its own detect register */
7508
7509                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7510                         DRM_DEBUG_KMS("probing SDVOC\n");
7511                         found = intel_sdvo_init(dev, SDVOC);
7512                 }
7513
7514                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7515
7516                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7517                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7518                                 intel_hdmi_init(dev, SDVOC);
7519                         }
7520                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7521                                 DRM_DEBUG_KMS("probing DP_C\n");
7522                                 intel_dp_init(dev, DP_C);
7523                         }
7524                 }
7525
7526                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7527                     (I915_READ(DP_D) & DP_DETECTED)) {
7528                         DRM_DEBUG_KMS("probing DP_D\n");
7529                         intel_dp_init(dev, DP_D);
7530                 }
7531         } else if (IS_GEN2(dev))
7532                 intel_dvo_init(dev);
7533
7534         if (SUPPORTS_TV(dev))
7535                 intel_tv_init(dev);
7536
7537         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7538                 encoder->base.possible_crtcs = encoder->crtc_mask;
7539                 encoder->base.possible_clones =
7540                         intel_encoder_clones(dev, encoder->clone_mask);
7541         }
7542
7543         /* disable all the possible outputs/crtcs before entering KMS mode */
7544         drm_helper_disable_unused_functions(dev);
7545
7546         if (HAS_PCH_SPLIT(dev))
7547                 ironlake_init_pch_refclk(dev);
7548 }
7549
7550 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7551 {
7552         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7553
7554         drm_framebuffer_cleanup(fb);
7555         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7556
7557         kfree(intel_fb);
7558 }
7559
7560 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7561                                                 struct drm_file *file,
7562                                                 unsigned int *handle)
7563 {
7564         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7565         struct drm_i915_gem_object *obj = intel_fb->obj;
7566
7567         return drm_gem_handle_create(file, &obj->base, handle);
7568 }
7569
7570 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7571         .destroy = intel_user_framebuffer_destroy,
7572         .create_handle = intel_user_framebuffer_create_handle,
7573 };
7574
7575 int intel_framebuffer_init(struct drm_device *dev,
7576                            struct intel_framebuffer *intel_fb,
7577                            struct drm_mode_fb_cmd *mode_cmd,
7578                            struct drm_i915_gem_object *obj)
7579 {
7580         int ret;
7581
7582         if (obj->tiling_mode == I915_TILING_Y)
7583                 return -EINVAL;
7584
7585         if (mode_cmd->pitch & 63)
7586                 return -EINVAL;
7587
7588         switch (mode_cmd->bpp) {
7589         case 8:
7590         case 16:
7591                 /* Only pre-ILK can handle 5:5:5 */
7592                 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7593                         return -EINVAL;
7594                 break;
7595
7596         case 24:
7597         case 32:
7598                 break;
7599         default:
7600                 return -EINVAL;
7601         }
7602
7603         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7604         if (ret) {
7605                 DRM_ERROR("framebuffer init failed %d\n", ret);
7606                 return ret;
7607         }
7608
7609         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7610         intel_fb->obj = obj;
7611         return 0;
7612 }
7613
7614 static struct drm_framebuffer *
7615 intel_user_framebuffer_create(struct drm_device *dev,
7616                               struct drm_file *filp,
7617                               struct drm_mode_fb_cmd *mode_cmd)
7618 {
7619         struct drm_i915_gem_object *obj;
7620
7621         obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7622         if (&obj->base == NULL)
7623                 return ERR_PTR(-ENOENT);
7624
7625         return intel_framebuffer_create(dev, mode_cmd, obj);
7626 }
7627
7628 static const struct drm_mode_config_funcs intel_mode_funcs = {
7629         .fb_create = intel_user_framebuffer_create,
7630         .output_poll_changed = intel_fb_output_poll_changed,
7631 };
7632
7633 static struct drm_i915_gem_object *
7634 intel_alloc_context_page(struct drm_device *dev)
7635 {
7636         struct drm_i915_gem_object *ctx;
7637         int ret;
7638
7639         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7640
7641         ctx = i915_gem_alloc_object(dev, 4096);
7642         if (!ctx) {
7643                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7644                 return NULL;
7645         }
7646
7647         ret = i915_gem_object_pin(ctx, 4096, true);
7648         if (ret) {
7649                 DRM_ERROR("failed to pin power context: %d\n", ret);
7650                 goto err_unref;
7651         }
7652
7653         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7654         if (ret) {
7655                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7656                 goto err_unpin;
7657         }
7658
7659         return ctx;
7660
7661 err_unpin:
7662         i915_gem_object_unpin(ctx);
7663 err_unref:
7664         drm_gem_object_unreference(&ctx->base);
7665         mutex_unlock(&dev->struct_mutex);
7666         return NULL;
7667 }
7668
7669 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7670 {
7671         struct drm_i915_private *dev_priv = dev->dev_private;
7672         u16 rgvswctl;
7673
7674         rgvswctl = I915_READ16(MEMSWCTL);
7675         if (rgvswctl & MEMCTL_CMD_STS) {
7676                 DRM_DEBUG("gpu busy, RCS change rejected\n");
7677                 return false; /* still busy with another command */
7678         }
7679
7680         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7681                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7682         I915_WRITE16(MEMSWCTL, rgvswctl);
7683         POSTING_READ16(MEMSWCTL);
7684
7685         rgvswctl |= MEMCTL_CMD_STS;
7686         I915_WRITE16(MEMSWCTL, rgvswctl);
7687
7688         return true;
7689 }
7690
7691 void ironlake_enable_drps(struct drm_device *dev)
7692 {
7693         struct drm_i915_private *dev_priv = dev->dev_private;
7694         u32 rgvmodectl = I915_READ(MEMMODECTL);
7695         u8 fmax, fmin, fstart, vstart;
7696
7697         /* Enable temp reporting */
7698         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7699         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7700
7701         /* 100ms RC evaluation intervals */
7702         I915_WRITE(RCUPEI, 100000);
7703         I915_WRITE(RCDNEI, 100000);
7704
7705         /* Set max/min thresholds to 90ms and 80ms respectively */
7706         I915_WRITE(RCBMAXAVG, 90000);
7707         I915_WRITE(RCBMINAVG, 80000);
7708
7709         I915_WRITE(MEMIHYST, 1);
7710
7711         /* Set up min, max, and cur for interrupt handling */
7712         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7713         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7714         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7715                 MEMMODE_FSTART_SHIFT;
7716
7717         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7718                 PXVFREQ_PX_SHIFT;
7719
7720         dev_priv->fmax = fmax; /* IPS callback will increase this */
7721         dev_priv->fstart = fstart;
7722
7723         dev_priv->max_delay = fstart;
7724         dev_priv->min_delay = fmin;
7725         dev_priv->cur_delay = fstart;
7726
7727         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7728                          fmax, fmin, fstart);
7729
7730         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7731
7732         /*
7733          * Interrupts will be enabled in ironlake_irq_postinstall
7734          */
7735
7736         I915_WRITE(VIDSTART, vstart);
7737         POSTING_READ(VIDSTART);
7738
7739         rgvmodectl |= MEMMODE_SWMODE_EN;
7740         I915_WRITE(MEMMODECTL, rgvmodectl);
7741
7742         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7743                 DRM_ERROR("stuck trying to change perf mode\n");
7744         msleep(1);
7745
7746         ironlake_set_drps(dev, fstart);
7747
7748         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7749                 I915_READ(0x112e0);
7750         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7751         dev_priv->last_count2 = I915_READ(0x112f4);
7752         getrawmonotonic(&dev_priv->last_time2);
7753 }
7754
7755 void ironlake_disable_drps(struct drm_device *dev)
7756 {
7757         struct drm_i915_private *dev_priv = dev->dev_private;
7758         u16 rgvswctl = I915_READ16(MEMSWCTL);
7759
7760         /* Ack interrupts, disable EFC interrupt */
7761         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7762         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7763         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7764         I915_WRITE(DEIIR, DE_PCU_EVENT);
7765         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7766
7767         /* Go back to the starting frequency */
7768         ironlake_set_drps(dev, dev_priv->fstart);
7769         msleep(1);
7770         rgvswctl |= MEMCTL_CMD_STS;
7771         I915_WRITE(MEMSWCTL, rgvswctl);
7772         msleep(1);
7773
7774 }
7775
7776 void gen6_set_rps(struct drm_device *dev, u8 val)
7777 {
7778         struct drm_i915_private *dev_priv = dev->dev_private;
7779         u32 swreq;
7780
7781         swreq = (val & 0x3ff) << 25;
7782         I915_WRITE(GEN6_RPNSWREQ, swreq);
7783 }
7784
7785 void gen6_disable_rps(struct drm_device *dev)
7786 {
7787         struct drm_i915_private *dev_priv = dev->dev_private;
7788
7789         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7790         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7791         I915_WRITE(GEN6_PMIER, 0);
7792         /* Complete PM interrupt masking here doesn't race with the rps work
7793          * item again unmasking PM interrupts because that is using a different
7794          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7795          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7796
7797         spin_lock_irq(&dev_priv->rps_lock);
7798         dev_priv->pm_iir = 0;
7799         spin_unlock_irq(&dev_priv->rps_lock);
7800
7801         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7802 }
7803
7804 static unsigned long intel_pxfreq(u32 vidfreq)
7805 {
7806         unsigned long freq;
7807         int div = (vidfreq & 0x3f0000) >> 16;
7808         int post = (vidfreq & 0x3000) >> 12;
7809         int pre = (vidfreq & 0x7);
7810
7811         if (!pre)
7812                 return 0;
7813
7814         freq = ((div * 133333) / ((1<<post) * pre));
7815
7816         return freq;
7817 }
7818
7819 void intel_init_emon(struct drm_device *dev)
7820 {
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         u32 lcfuse;
7823         u8 pxw[16];
7824         int i;
7825
7826         /* Disable to program */
7827         I915_WRITE(ECR, 0);
7828         POSTING_READ(ECR);
7829
7830         /* Program energy weights for various events */
7831         I915_WRITE(SDEW, 0x15040d00);
7832         I915_WRITE(CSIEW0, 0x007f0000);
7833         I915_WRITE(CSIEW1, 0x1e220004);
7834         I915_WRITE(CSIEW2, 0x04000004);
7835
7836         for (i = 0; i < 5; i++)
7837                 I915_WRITE(PEW + (i * 4), 0);
7838         for (i = 0; i < 3; i++)
7839                 I915_WRITE(DEW + (i * 4), 0);
7840
7841         /* Program P-state weights to account for frequency power adjustment */
7842         for (i = 0; i < 16; i++) {
7843                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7844                 unsigned long freq = intel_pxfreq(pxvidfreq);
7845                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7846                         PXVFREQ_PX_SHIFT;
7847                 unsigned long val;
7848
7849                 val = vid * vid;
7850                 val *= (freq / 1000);
7851                 val *= 255;
7852                 val /= (127*127*900);
7853                 if (val > 0xff)
7854                         DRM_ERROR("bad pxval: %ld\n", val);
7855                 pxw[i] = val;
7856         }
7857         /* Render standby states get 0 weight */
7858         pxw[14] = 0;
7859         pxw[15] = 0;
7860
7861         for (i = 0; i < 4; i++) {
7862                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7863                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7864                 I915_WRITE(PXW + (i * 4), val);
7865         }
7866
7867         /* Adjust magic regs to magic values (more experimental results) */
7868         I915_WRITE(OGW0, 0);
7869         I915_WRITE(OGW1, 0);
7870         I915_WRITE(EG0, 0x00007f00);
7871         I915_WRITE(EG1, 0x0000000e);
7872         I915_WRITE(EG2, 0x000e0000);
7873         I915_WRITE(EG3, 0x68000300);
7874         I915_WRITE(EG4, 0x42000000);
7875         I915_WRITE(EG5, 0x00140031);
7876         I915_WRITE(EG6, 0);
7877         I915_WRITE(EG7, 0);
7878
7879         for (i = 0; i < 8; i++)
7880                 I915_WRITE(PXWL + (i * 4), 0);
7881
7882         /* Enable PMON + select events */
7883         I915_WRITE(ECR, 0x80000019);
7884
7885         lcfuse = I915_READ(LCFUSE02);
7886
7887         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7888 }
7889
7890 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7891 {
7892         u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7893         u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7894         u32 pcu_mbox, rc6_mask = 0;
7895         int cur_freq, min_freq, max_freq;
7896         int i;
7897
7898         /* Here begins a magic sequence of register writes to enable
7899          * auto-downclocking.
7900          *
7901          * Perhaps there might be some value in exposing these to
7902          * userspace...
7903          */
7904         I915_WRITE(GEN6_RC_STATE, 0);
7905         mutex_lock(&dev_priv->dev->struct_mutex);
7906         gen6_gt_force_wake_get(dev_priv);
7907
7908         /* disable the counters and set deterministic thresholds */
7909         I915_WRITE(GEN6_RC_CONTROL, 0);
7910
7911         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7912         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7913         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7914         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7915         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7916
7917         for (i = 0; i < I915_NUM_RINGS; i++)
7918                 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7919
7920         I915_WRITE(GEN6_RC_SLEEP, 0);
7921         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7922         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7923         I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7924         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7925
7926         if (i915_enable_rc6)
7927                 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7928                         GEN6_RC_CTL_RC6_ENABLE;
7929
7930         I915_WRITE(GEN6_RC_CONTROL,
7931                    rc6_mask |
7932                    GEN6_RC_CTL_EI_MODE(1) |
7933                    GEN6_RC_CTL_HW_ENABLE);
7934
7935         I915_WRITE(GEN6_RPNSWREQ,
7936                    GEN6_FREQUENCY(10) |
7937                    GEN6_OFFSET(0) |
7938                    GEN6_AGGRESSIVE_TURBO);
7939         I915_WRITE(GEN6_RC_VIDEO_FREQ,
7940                    GEN6_FREQUENCY(12));
7941
7942         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7943         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7944                    18 << 24 |
7945                    6 << 16);
7946         I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7947         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7948         I915_WRITE(GEN6_RP_UP_EI, 100000);
7949         I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7950         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7951         I915_WRITE(GEN6_RP_CONTROL,
7952                    GEN6_RP_MEDIA_TURBO |
7953                    GEN6_RP_USE_NORMAL_FREQ |
7954                    GEN6_RP_MEDIA_IS_GFX |
7955                    GEN6_RP_ENABLE |
7956                    GEN6_RP_UP_BUSY_AVG |
7957                    GEN6_RP_DOWN_IDLE_CONT);
7958
7959         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7960                      500))
7961                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7962
7963         I915_WRITE(GEN6_PCODE_DATA, 0);
7964         I915_WRITE(GEN6_PCODE_MAILBOX,
7965                    GEN6_PCODE_READY |
7966                    GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7967         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7968                      500))
7969                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7970
7971         min_freq = (rp_state_cap & 0xff0000) >> 16;
7972         max_freq = rp_state_cap & 0xff;
7973         cur_freq = (gt_perf_status & 0xff00) >> 8;
7974
7975         /* Check for overclock support */
7976         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7977                      500))
7978                 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7979         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7980         pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7981         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7982                      500))
7983                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7984         if (pcu_mbox & (1<<31)) { /* OC supported */
7985                 max_freq = pcu_mbox & 0xff;
7986                 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7987         }
7988
7989         /* In units of 100MHz */
7990         dev_priv->max_delay = max_freq;
7991         dev_priv->min_delay = min_freq;
7992         dev_priv->cur_delay = cur_freq;
7993
7994         /* requires MSI enabled */
7995         I915_WRITE(GEN6_PMIER,
7996                    GEN6_PM_MBOX_EVENT |
7997                    GEN6_PM_THERMAL_EVENT |
7998                    GEN6_PM_RP_DOWN_TIMEOUT |
7999                    GEN6_PM_RP_UP_THRESHOLD |
8000                    GEN6_PM_RP_DOWN_THRESHOLD |
8001                    GEN6_PM_RP_UP_EI_EXPIRED |
8002                    GEN6_PM_RP_DOWN_EI_EXPIRED);
8003         spin_lock_irq(&dev_priv->rps_lock);
8004         WARN_ON(dev_priv->pm_iir != 0);
8005         I915_WRITE(GEN6_PMIMR, 0);
8006         spin_unlock_irq(&dev_priv->rps_lock);
8007         /* enable all PM interrupts */
8008         I915_WRITE(GEN6_PMINTRMSK, 0);
8009
8010         gen6_gt_force_wake_put(dev_priv);
8011         mutex_unlock(&dev_priv->dev->struct_mutex);
8012 }
8013
8014 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8015 {
8016         int min_freq = 15;
8017         int gpu_freq, ia_freq, max_ia_freq;
8018         int scaling_factor = 180;
8019
8020         max_ia_freq = cpufreq_quick_get_max(0);
8021         /*
8022          * Default to measured freq if none found, PCU will ensure we don't go
8023          * over
8024          */
8025         if (!max_ia_freq)
8026                 max_ia_freq = tsc_khz;
8027
8028         /* Convert from kHz to MHz */
8029         max_ia_freq /= 1000;
8030
8031         mutex_lock(&dev_priv->dev->struct_mutex);
8032
8033         /*
8034          * For each potential GPU frequency, load a ring frequency we'd like
8035          * to use for memory access.  We do this by specifying the IA frequency
8036          * the PCU should use as a reference to determine the ring frequency.
8037          */
8038         for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8039              gpu_freq--) {
8040                 int diff = dev_priv->max_delay - gpu_freq;
8041
8042                 /*
8043                  * For GPU frequencies less than 750MHz, just use the lowest
8044                  * ring freq.
8045                  */
8046                 if (gpu_freq < min_freq)
8047                         ia_freq = 800;
8048                 else
8049                         ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8050                 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8051
8052                 I915_WRITE(GEN6_PCODE_DATA,
8053                            (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8054                            gpu_freq);
8055                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8056                            GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8057                 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8058                               GEN6_PCODE_READY) == 0, 10)) {
8059                         DRM_ERROR("pcode write of freq table timed out\n");
8060                         continue;
8061                 }
8062         }
8063
8064         mutex_unlock(&dev_priv->dev->struct_mutex);
8065 }
8066
8067 static void ironlake_init_clock_gating(struct drm_device *dev)
8068 {
8069         struct drm_i915_private *dev_priv = dev->dev_private;
8070         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8071
8072         /* Required for FBC */
8073         dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8074                 DPFCRUNIT_CLOCK_GATE_DISABLE |
8075                 DPFDUNIT_CLOCK_GATE_DISABLE;
8076         /* Required for CxSR */
8077         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8078
8079         I915_WRITE(PCH_3DCGDIS0,
8080                    MARIUNIT_CLOCK_GATE_DISABLE |
8081                    SVSMUNIT_CLOCK_GATE_DISABLE);
8082         I915_WRITE(PCH_3DCGDIS1,
8083                    VFMUNIT_CLOCK_GATE_DISABLE);
8084
8085         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8086
8087         /*
8088          * According to the spec the following bits should be set in
8089          * order to enable memory self-refresh
8090          * The bit 22/21 of 0x42004
8091          * The bit 5 of 0x42020
8092          * The bit 15 of 0x45000
8093          */
8094         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8095                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8096                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8097         I915_WRITE(ILK_DSPCLK_GATE,
8098                    (I915_READ(ILK_DSPCLK_GATE) |
8099                     ILK_DPARB_CLK_GATE));
8100         I915_WRITE(DISP_ARB_CTL,
8101                    (I915_READ(DISP_ARB_CTL) |
8102                     DISP_FBC_WM_DIS));
8103         I915_WRITE(WM3_LP_ILK, 0);
8104         I915_WRITE(WM2_LP_ILK, 0);
8105         I915_WRITE(WM1_LP_ILK, 0);
8106
8107         /*
8108          * Based on the document from hardware guys the following bits
8109          * should be set unconditionally in order to enable FBC.
8110          * The bit 22 of 0x42000
8111          * The bit 22 of 0x42004
8112          * The bit 7,8,9 of 0x42020.
8113          */
8114         if (IS_IRONLAKE_M(dev)) {
8115                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8116                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8117                            ILK_FBCQ_DIS);
8118                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8119                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8120                            ILK_DPARB_GATE);
8121                 I915_WRITE(ILK_DSPCLK_GATE,
8122                            I915_READ(ILK_DSPCLK_GATE) |
8123                            ILK_DPFC_DIS1 |
8124                            ILK_DPFC_DIS2 |
8125                            ILK_CLK_FBC);
8126         }
8127
8128         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8129                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8130                    ILK_ELPIN_409_SELECT);
8131         I915_WRITE(_3D_CHICKEN2,
8132                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8133                    _3D_CHICKEN2_WM_READ_PIPELINED);
8134 }
8135
8136 static void gen6_init_clock_gating(struct drm_device *dev)
8137 {
8138         struct drm_i915_private *dev_priv = dev->dev_private;
8139         int pipe;
8140         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8141
8142         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8143
8144         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8145                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8146                    ILK_ELPIN_409_SELECT);
8147
8148         I915_WRITE(WM3_LP_ILK, 0);
8149         I915_WRITE(WM2_LP_ILK, 0);
8150         I915_WRITE(WM1_LP_ILK, 0);
8151
8152         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8153          * gating disable must be set.  Failure to set it results in
8154          * flickering pixels due to Z write ordering failures after
8155          * some amount of runtime in the Mesa "fire" demo, and Unigine
8156          * Sanctuary and Tropics, and apparently anything else with
8157          * alpha test or pixel discard.
8158          *
8159          * According to the spec, bit 11 (RCCUNIT) must also be set,
8160          * but we didn't debug actual testcases to find it out.
8161          */
8162         I915_WRITE(GEN6_UCGCTL2,
8163                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8164                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8165
8166         /*
8167          * According to the spec the following bits should be
8168          * set in order to enable memory self-refresh and fbc:
8169          * The bit21 and bit22 of 0x42000
8170          * The bit21 and bit22 of 0x42004
8171          * The bit5 and bit7 of 0x42020
8172          * The bit14 of 0x70180
8173          * The bit14 of 0x71180
8174          */
8175         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8176                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8177                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8178         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8179                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8180                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8181         I915_WRITE(ILK_DSPCLK_GATE,
8182                    I915_READ(ILK_DSPCLK_GATE) |
8183                    ILK_DPARB_CLK_GATE  |
8184                    ILK_DPFD_CLK_GATE);
8185
8186         for_each_pipe(pipe) {
8187                 I915_WRITE(DSPCNTR(pipe),
8188                            I915_READ(DSPCNTR(pipe)) |
8189                            DISPPLANE_TRICKLE_FEED_DISABLE);
8190                 intel_flush_display_plane(dev_priv, pipe);
8191         }
8192 }
8193
8194 static void ivybridge_init_clock_gating(struct drm_device *dev)
8195 {
8196         struct drm_i915_private *dev_priv = dev->dev_private;
8197         int pipe;
8198         uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8199
8200         I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8201
8202         I915_WRITE(WM3_LP_ILK, 0);
8203         I915_WRITE(WM2_LP_ILK, 0);
8204         I915_WRITE(WM1_LP_ILK, 0);
8205
8206         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8207
8208         for_each_pipe(pipe) {
8209                 I915_WRITE(DSPCNTR(pipe),
8210                            I915_READ(DSPCNTR(pipe)) |
8211                            DISPPLANE_TRICKLE_FEED_DISABLE);
8212                 intel_flush_display_plane(dev_priv, pipe);
8213         }
8214 }
8215
8216 static void g4x_init_clock_gating(struct drm_device *dev)
8217 {
8218         struct drm_i915_private *dev_priv = dev->dev_private;
8219         uint32_t dspclk_gate;
8220
8221         I915_WRITE(RENCLK_GATE_D1, 0);
8222         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8223                    GS_UNIT_CLOCK_GATE_DISABLE |
8224                    CL_UNIT_CLOCK_GATE_DISABLE);
8225         I915_WRITE(RAMCLK_GATE_D, 0);
8226         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8227                 OVRUNIT_CLOCK_GATE_DISABLE |
8228                 OVCUNIT_CLOCK_GATE_DISABLE;
8229         if (IS_GM45(dev))
8230                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8231         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8232 }
8233
8234 static void crestline_init_clock_gating(struct drm_device *dev)
8235 {
8236         struct drm_i915_private *dev_priv = dev->dev_private;
8237
8238         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8239         I915_WRITE(RENCLK_GATE_D2, 0);
8240         I915_WRITE(DSPCLK_GATE_D, 0);
8241         I915_WRITE(RAMCLK_GATE_D, 0);
8242         I915_WRITE16(DEUC, 0);
8243 }
8244
8245 static void broadwater_init_clock_gating(struct drm_device *dev)
8246 {
8247         struct drm_i915_private *dev_priv = dev->dev_private;
8248
8249         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8250                    I965_RCC_CLOCK_GATE_DISABLE |
8251                    I965_RCPB_CLOCK_GATE_DISABLE |
8252                    I965_ISC_CLOCK_GATE_DISABLE |
8253                    I965_FBC_CLOCK_GATE_DISABLE);
8254         I915_WRITE(RENCLK_GATE_D2, 0);
8255 }
8256
8257 static void gen3_init_clock_gating(struct drm_device *dev)
8258 {
8259         struct drm_i915_private *dev_priv = dev->dev_private;
8260         u32 dstate = I915_READ(D_STATE);
8261
8262         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8263                 DSTATE_DOT_CLOCK_GATING;
8264         I915_WRITE(D_STATE, dstate);
8265 }
8266
8267 static void i85x_init_clock_gating(struct drm_device *dev)
8268 {
8269         struct drm_i915_private *dev_priv = dev->dev_private;
8270
8271         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8272 }
8273
8274 static void i830_init_clock_gating(struct drm_device *dev)
8275 {
8276         struct drm_i915_private *dev_priv = dev->dev_private;
8277
8278         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8279 }
8280
8281 static void ibx_init_clock_gating(struct drm_device *dev)
8282 {
8283         struct drm_i915_private *dev_priv = dev->dev_private;
8284
8285         /*
8286          * On Ibex Peak and Cougar Point, we need to disable clock
8287          * gating for the panel power sequencer or it will fail to
8288          * start up when no ports are active.
8289          */
8290         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8291 }
8292
8293 static void cpt_init_clock_gating(struct drm_device *dev)
8294 {
8295         struct drm_i915_private *dev_priv = dev->dev_private;
8296         int pipe;
8297
8298         /*
8299          * On Ibex Peak and Cougar Point, we need to disable clock
8300          * gating for the panel power sequencer or it will fail to
8301          * start up when no ports are active.
8302          */
8303         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8304         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8305                    DPLS_EDP_PPS_FIX_DIS);
8306         /* Without this, mode sets may fail silently on FDI */
8307         for_each_pipe(pipe)
8308                 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8309 }
8310
8311 static void ironlake_teardown_rc6(struct drm_device *dev)
8312 {
8313         struct drm_i915_private *dev_priv = dev->dev_private;
8314
8315         if (dev_priv->renderctx) {
8316                 i915_gem_object_unpin(dev_priv->renderctx);
8317                 drm_gem_object_unreference(&dev_priv->renderctx->base);
8318                 dev_priv->renderctx = NULL;
8319         }
8320
8321         if (dev_priv->pwrctx) {
8322                 i915_gem_object_unpin(dev_priv->pwrctx);
8323                 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8324                 dev_priv->pwrctx = NULL;
8325         }
8326 }
8327
8328 static void ironlake_disable_rc6(struct drm_device *dev)
8329 {
8330         struct drm_i915_private *dev_priv = dev->dev_private;
8331
8332         if (I915_READ(PWRCTXA)) {
8333                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8334                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8335                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8336                          50);
8337
8338                 I915_WRITE(PWRCTXA, 0);
8339                 POSTING_READ(PWRCTXA);
8340
8341                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8342                 POSTING_READ(RSTDBYCTL);
8343         }
8344
8345         ironlake_teardown_rc6(dev);
8346 }
8347
8348 static int ironlake_setup_rc6(struct drm_device *dev)
8349 {
8350         struct drm_i915_private *dev_priv = dev->dev_private;
8351
8352         if (dev_priv->renderctx == NULL)
8353                 dev_priv->renderctx = intel_alloc_context_page(dev);
8354         if (!dev_priv->renderctx)
8355                 return -ENOMEM;
8356
8357         if (dev_priv->pwrctx == NULL)
8358                 dev_priv->pwrctx = intel_alloc_context_page(dev);
8359         if (!dev_priv->pwrctx) {
8360                 ironlake_teardown_rc6(dev);
8361                 return -ENOMEM;
8362         }
8363
8364         return 0;
8365 }
8366
8367 void ironlake_enable_rc6(struct drm_device *dev)
8368 {
8369         struct drm_i915_private *dev_priv = dev->dev_private;
8370         int ret;
8371
8372         /* rc6 disabled by default due to repeated reports of hanging during
8373          * boot and resume.
8374          */
8375         if (!i915_enable_rc6)
8376                 return;
8377
8378         mutex_lock(&dev->struct_mutex);
8379         ret = ironlake_setup_rc6(dev);
8380         if (ret) {
8381                 mutex_unlock(&dev->struct_mutex);
8382                 return;
8383         }
8384
8385         /*
8386          * GPU can automatically power down the render unit if given a page
8387          * to save state.
8388          */
8389         ret = BEGIN_LP_RING(6);
8390         if (ret) {
8391                 ironlake_teardown_rc6(dev);
8392                 mutex_unlock(&dev->struct_mutex);
8393                 return;
8394         }
8395
8396         OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8397         OUT_RING(MI_SET_CONTEXT);
8398         OUT_RING(dev_priv->renderctx->gtt_offset |
8399                  MI_MM_SPACE_GTT |
8400                  MI_SAVE_EXT_STATE_EN |
8401                  MI_RESTORE_EXT_STATE_EN |
8402                  MI_RESTORE_INHIBIT);
8403         OUT_RING(MI_SUSPEND_FLUSH);
8404         OUT_RING(MI_NOOP);
8405         OUT_RING(MI_FLUSH);
8406         ADVANCE_LP_RING();
8407
8408         /*
8409          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8410          * does an implicit flush, combined with MI_FLUSH above, it should be
8411          * safe to assume that renderctx is valid
8412          */
8413         ret = intel_wait_ring_idle(LP_RING(dev_priv));
8414         if (ret) {
8415                 DRM_ERROR("failed to enable ironlake power power savings\n");
8416                 ironlake_teardown_rc6(dev);
8417                 mutex_unlock(&dev->struct_mutex);
8418                 return;
8419         }
8420
8421         I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8422         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8423         mutex_unlock(&dev->struct_mutex);
8424 }
8425
8426 void intel_init_clock_gating(struct drm_device *dev)
8427 {
8428         struct drm_i915_private *dev_priv = dev->dev_private;
8429
8430         dev_priv->display.init_clock_gating(dev);
8431
8432         if (dev_priv->display.init_pch_clock_gating)
8433                 dev_priv->display.init_pch_clock_gating(dev);
8434 }
8435
8436 /* Set up chip specific display functions */
8437 static void intel_init_display(struct drm_device *dev)
8438 {
8439         struct drm_i915_private *dev_priv = dev->dev_private;
8440
8441         /* We always want a DPMS function */
8442         if (HAS_PCH_SPLIT(dev)) {
8443                 dev_priv->display.dpms = ironlake_crtc_dpms;
8444                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8445                 dev_priv->display.update_plane = ironlake_update_plane;
8446         } else {
8447                 dev_priv->display.dpms = i9xx_crtc_dpms;
8448                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8449                 dev_priv->display.update_plane = i9xx_update_plane;
8450         }
8451
8452         if (I915_HAS_FBC(dev)) {
8453                 if (HAS_PCH_SPLIT(dev)) {
8454                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8455                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
8456                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
8457                 } else if (IS_GM45(dev)) {
8458                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8459                         dev_priv->display.enable_fbc = g4x_enable_fbc;
8460                         dev_priv->display.disable_fbc = g4x_disable_fbc;
8461                 } else if (IS_CRESTLINE(dev)) {
8462                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8463                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
8464                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
8465                 }
8466                 /* 855GM needs testing */
8467         }
8468
8469         /* Returns the core display clock speed */
8470         if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8471                 dev_priv->display.get_display_clock_speed =
8472                         i945_get_display_clock_speed;
8473         else if (IS_I915G(dev))
8474                 dev_priv->display.get_display_clock_speed =
8475                         i915_get_display_clock_speed;
8476         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8477                 dev_priv->display.get_display_clock_speed =
8478                         i9xx_misc_get_display_clock_speed;
8479         else if (IS_I915GM(dev))
8480                 dev_priv->display.get_display_clock_speed =
8481                         i915gm_get_display_clock_speed;
8482         else if (IS_I865G(dev))
8483                 dev_priv->display.get_display_clock_speed =
8484                         i865_get_display_clock_speed;
8485         else if (IS_I85X(dev))
8486                 dev_priv->display.get_display_clock_speed =
8487                         i855_get_display_clock_speed;
8488         else /* 852, 830 */
8489                 dev_priv->display.get_display_clock_speed =
8490                         i830_get_display_clock_speed;
8491
8492         /* For FIFO watermark updates */
8493         if (HAS_PCH_SPLIT(dev)) {
8494                 if (HAS_PCH_IBX(dev))
8495                         dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8496                 else if (HAS_PCH_CPT(dev))
8497                         dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8498
8499                 if (IS_GEN5(dev)) {
8500                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8501                                 dev_priv->display.update_wm = ironlake_update_wm;
8502                         else {
8503                                 DRM_DEBUG_KMS("Failed to get proper latency. "
8504                                               "Disable CxSR\n");
8505                                 dev_priv->display.update_wm = NULL;
8506                         }
8507                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8508                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8509                         dev_priv->display.write_eld = ironlake_write_eld;
8510                 } else if (IS_GEN6(dev)) {
8511                         if (SNB_READ_WM0_LATENCY()) {
8512                                 dev_priv->display.update_wm = sandybridge_update_wm;
8513                         } else {
8514                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8515                                               "Disable CxSR\n");
8516                                 dev_priv->display.update_wm = NULL;
8517                         }
8518                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8519                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8520                         dev_priv->display.write_eld = ironlake_write_eld;
8521                 } else if (IS_IVYBRIDGE(dev)) {
8522                         /* FIXME: detect B0+ stepping and use auto training */
8523                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8524                         if (SNB_READ_WM0_LATENCY()) {
8525                                 dev_priv->display.update_wm = sandybridge_update_wm;
8526                         } else {
8527                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
8528                                               "Disable CxSR\n");
8529                                 dev_priv->display.update_wm = NULL;
8530                         }
8531                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8532                         dev_priv->display.write_eld = ironlake_write_eld;
8533                 } else
8534                         dev_priv->display.update_wm = NULL;
8535         } else if (IS_PINEVIEW(dev)) {
8536                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8537                                             dev_priv->is_ddr3,
8538                                             dev_priv->fsb_freq,
8539                                             dev_priv->mem_freq)) {
8540                         DRM_INFO("failed to find known CxSR latency "
8541                                  "(found ddr%s fsb freq %d, mem freq %d), "
8542                                  "disabling CxSR\n",
8543                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8544                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8545                         /* Disable CxSR and never update its watermark again */
8546                         pineview_disable_cxsr(dev);
8547                         dev_priv->display.update_wm = NULL;
8548                 } else
8549                         dev_priv->display.update_wm = pineview_update_wm;
8550                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8551         } else if (IS_G4X(dev)) {
8552                 dev_priv->display.write_eld = g4x_write_eld;
8553                 dev_priv->display.update_wm = g4x_update_wm;
8554                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8555         } else if (IS_GEN4(dev)) {
8556                 dev_priv->display.update_wm = i965_update_wm;
8557                 if (IS_CRESTLINE(dev))
8558                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8559                 else if (IS_BROADWATER(dev))
8560                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8561         } else if (IS_GEN3(dev)) {
8562                 dev_priv->display.update_wm = i9xx_update_wm;
8563                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8564                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8565         } else if (IS_I865G(dev)) {
8566                 dev_priv->display.update_wm = i830_update_wm;
8567                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8568                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8569         } else if (IS_I85X(dev)) {
8570                 dev_priv->display.update_wm = i9xx_update_wm;
8571                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8572                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8573         } else {
8574                 dev_priv->display.update_wm = i830_update_wm;
8575                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8576                 if (IS_845G(dev))
8577                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8578                 else
8579                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8580         }
8581
8582         /* Default just returns -ENODEV to indicate unsupported */
8583         dev_priv->display.queue_flip = intel_default_queue_flip;
8584
8585         switch (INTEL_INFO(dev)->gen) {
8586         case 2:
8587                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8588                 break;
8589
8590         case 3:
8591                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8592                 break;
8593
8594         case 4:
8595         case 5:
8596                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8597                 break;
8598
8599         case 6:
8600                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8601                 break;
8602         case 7:
8603                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8604                 break;
8605         }
8606 }
8607
8608 /*
8609  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8610  * resume, or other times.  This quirk makes sure that's the case for
8611  * affected systems.
8612  */
8613 static void quirk_pipea_force(struct drm_device *dev)
8614 {
8615         struct drm_i915_private *dev_priv = dev->dev_private;
8616
8617         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8618         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8619 }
8620
8621 /*
8622  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8623  */
8624 static void quirk_ssc_force_disable(struct drm_device *dev)
8625 {
8626         struct drm_i915_private *dev_priv = dev->dev_private;
8627         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8628 }
8629
8630 struct intel_quirk {
8631         int device;
8632         int subsystem_vendor;
8633         int subsystem_device;
8634         void (*hook)(struct drm_device *dev);
8635 };
8636
8637 struct intel_quirk intel_quirks[] = {
8638         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8639         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8640         /* HP Mini needs pipe A force quirk (LP: #322104) */
8641         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8642
8643         /* Thinkpad R31 needs pipe A force quirk */
8644         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8645         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8646         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8647
8648         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8649         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
8650         /* ThinkPad X40 needs pipe A force quirk */
8651
8652         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8653         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8654
8655         /* 855 & before need to leave pipe A & dpll A up */
8656         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8657         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8658
8659         /* Lenovo U160 cannot use SSC on LVDS */
8660         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8661
8662         /* Sony Vaio Y cannot use SSC on LVDS */
8663         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8664 };
8665
8666 static void intel_init_quirks(struct drm_device *dev)
8667 {
8668         struct pci_dev *d = dev->pdev;
8669         int i;
8670
8671         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8672                 struct intel_quirk *q = &intel_quirks[i];
8673
8674                 if (d->device == q->device &&
8675                     (d->subsystem_vendor == q->subsystem_vendor ||
8676                      q->subsystem_vendor == PCI_ANY_ID) &&
8677                     (d->subsystem_device == q->subsystem_device ||
8678                      q->subsystem_device == PCI_ANY_ID))
8679                         q->hook(dev);
8680         }
8681 }
8682
8683 /* Disable the VGA plane that we never use */
8684 static void i915_disable_vga(struct drm_device *dev)
8685 {
8686         struct drm_i915_private *dev_priv = dev->dev_private;
8687         u8 sr1;
8688         u32 vga_reg;
8689
8690         if (HAS_PCH_SPLIT(dev))
8691                 vga_reg = CPU_VGACNTRL;
8692         else
8693                 vga_reg = VGACNTRL;
8694
8695         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8696         outb(1, VGA_SR_INDEX);
8697         sr1 = inb(VGA_SR_DATA);
8698         outb(sr1 | 1<<5, VGA_SR_DATA);
8699         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8700         udelay(300);
8701
8702         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8703         POSTING_READ(vga_reg);
8704 }
8705
8706 void intel_modeset_init(struct drm_device *dev)
8707 {
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709         int i;
8710
8711         drm_mode_config_init(dev);
8712
8713         dev->mode_config.min_width = 0;
8714         dev->mode_config.min_height = 0;
8715
8716         dev->mode_config.funcs = (void *)&intel_mode_funcs;
8717
8718         intel_init_quirks(dev);
8719
8720         intel_init_display(dev);
8721
8722         if (IS_GEN2(dev)) {
8723                 dev->mode_config.max_width = 2048;
8724                 dev->mode_config.max_height = 2048;
8725         } else if (IS_GEN3(dev)) {
8726                 dev->mode_config.max_width = 4096;
8727                 dev->mode_config.max_height = 4096;
8728         } else {
8729                 dev->mode_config.max_width = 8192;
8730                 dev->mode_config.max_height = 8192;
8731         }
8732         dev->mode_config.fb_base = dev->agp->base;
8733
8734         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8735                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8736
8737         for (i = 0; i < dev_priv->num_pipe; i++) {
8738                 intel_crtc_init(dev, i);
8739         }
8740
8741         /* Just disable it once at startup */
8742         i915_disable_vga(dev);
8743         intel_setup_outputs(dev);
8744
8745         intel_init_clock_gating(dev);
8746
8747         if (IS_IRONLAKE_M(dev)) {
8748                 ironlake_enable_drps(dev);
8749                 intel_init_emon(dev);
8750         }
8751
8752         if (IS_GEN6(dev) || IS_GEN7(dev)) {
8753                 gen6_enable_rps(dev_priv);
8754                 gen6_update_ring_freq(dev_priv);
8755         }
8756
8757         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8758         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8759                     (unsigned long)dev);
8760 }
8761
8762 void intel_modeset_gem_init(struct drm_device *dev)
8763 {
8764         if (IS_IRONLAKE_M(dev))
8765                 ironlake_enable_rc6(dev);
8766
8767         intel_setup_overlay(dev);
8768 }
8769
8770 void intel_modeset_cleanup(struct drm_device *dev)
8771 {
8772         struct drm_i915_private *dev_priv = dev->dev_private;
8773         struct drm_crtc *crtc;
8774         struct intel_crtc *intel_crtc;
8775
8776         drm_kms_helper_poll_fini(dev);
8777         mutex_lock(&dev->struct_mutex);
8778
8779         intel_unregister_dsm_handler();
8780
8781
8782         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8783                 /* Skip inactive CRTCs */
8784                 if (!crtc->fb)
8785                         continue;
8786
8787                 intel_crtc = to_intel_crtc(crtc);
8788                 intel_increase_pllclock(crtc);
8789         }
8790
8791         intel_disable_fbc(dev);
8792
8793         if (IS_IRONLAKE_M(dev))
8794                 ironlake_disable_drps(dev);
8795         if (IS_GEN6(dev) || IS_GEN7(dev))
8796                 gen6_disable_rps(dev);
8797
8798         if (IS_IRONLAKE_M(dev))
8799                 ironlake_disable_rc6(dev);
8800
8801         mutex_unlock(&dev->struct_mutex);
8802
8803         /* Disable the irq before mode object teardown, for the irq might
8804          * enqueue unpin/hotplug work. */
8805         drm_irq_uninstall(dev);
8806         cancel_work_sync(&dev_priv->hotplug_work);
8807         cancel_work_sync(&dev_priv->rps_work);
8808
8809         /* flush any delayed tasks or pending work */
8810         flush_scheduled_work();
8811
8812         /* Shut off idle work before the crtcs get freed. */
8813         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8814                 intel_crtc = to_intel_crtc(crtc);
8815                 del_timer_sync(&intel_crtc->idle_timer);
8816         }
8817         del_timer_sync(&dev_priv->idle_timer);
8818         cancel_work_sync(&dev_priv->idle_work);
8819
8820         drm_mode_config_cleanup(dev);
8821 }
8822
8823 /*
8824  * Return which encoder is currently attached for connector.
8825  */
8826 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8827 {
8828         return &intel_attached_encoder(connector)->base;
8829 }
8830
8831 void intel_connector_attach_encoder(struct intel_connector *connector,
8832                                     struct intel_encoder *encoder)
8833 {
8834         connector->encoder = encoder;
8835         drm_mode_connector_attach_encoder(&connector->base,
8836                                           &encoder->base);
8837 }
8838
8839 /*
8840  * set vga decode state - true == enable VGA decode
8841  */
8842 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8843 {
8844         struct drm_i915_private *dev_priv = dev->dev_private;
8845         u16 gmch_ctrl;
8846
8847         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8848         if (state)
8849                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8850         else
8851                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8852         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8853         return 0;
8854 }
8855
8856 #ifdef CONFIG_DEBUG_FS
8857 #include <linux/seq_file.h>
8858
8859 struct intel_display_error_state {
8860         struct intel_cursor_error_state {
8861                 u32 control;
8862                 u32 position;
8863                 u32 base;
8864                 u32 size;
8865         } cursor[2];
8866
8867         struct intel_pipe_error_state {
8868                 u32 conf;
8869                 u32 source;
8870
8871                 u32 htotal;
8872                 u32 hblank;
8873                 u32 hsync;
8874                 u32 vtotal;
8875                 u32 vblank;
8876                 u32 vsync;
8877         } pipe[2];
8878
8879         struct intel_plane_error_state {
8880                 u32 control;
8881                 u32 stride;
8882                 u32 size;
8883                 u32 pos;
8884                 u32 addr;
8885                 u32 surface;
8886                 u32 tile_offset;
8887         } plane[2];
8888 };
8889
8890 struct intel_display_error_state *
8891 intel_display_capture_error_state(struct drm_device *dev)
8892 {
8893         drm_i915_private_t *dev_priv = dev->dev_private;
8894         struct intel_display_error_state *error;
8895         int i;
8896
8897         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8898         if (error == NULL)
8899                 return NULL;
8900
8901         for (i = 0; i < 2; i++) {
8902                 error->cursor[i].control = I915_READ(CURCNTR(i));
8903                 error->cursor[i].position = I915_READ(CURPOS(i));
8904                 error->cursor[i].base = I915_READ(CURBASE(i));
8905
8906                 error->plane[i].control = I915_READ(DSPCNTR(i));
8907                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8908                 error->plane[i].size = I915_READ(DSPSIZE(i));
8909                 error->plane[i].pos = I915_READ(DSPPOS(i));
8910                 error->plane[i].addr = I915_READ(DSPADDR(i));
8911                 if (INTEL_INFO(dev)->gen >= 4) {
8912                         error->plane[i].surface = I915_READ(DSPSURF(i));
8913                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8914                 }
8915
8916                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8917                 error->pipe[i].source = I915_READ(PIPESRC(i));
8918                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8919                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8920                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8921                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8922                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8923                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8924         }
8925
8926         return error;
8927 }
8928
8929 void
8930 intel_display_print_error_state(struct seq_file *m,
8931                                 struct drm_device *dev,
8932                                 struct intel_display_error_state *error)
8933 {
8934         int i;
8935
8936         for (i = 0; i < 2; i++) {
8937                 seq_printf(m, "Pipe [%d]:\n", i);
8938                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8939                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8940                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8941                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8942                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8943                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8944                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8945                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8946
8947                 seq_printf(m, "Plane [%d]:\n", i);
8948                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8949                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8950                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8951                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8952                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8953                 if (INTEL_INFO(dev)->gen >= 4) {
8954                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8955                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8956                 }
8957
8958                 seq_printf(m, "Cursor [%d]:\n", i);
8959                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8960                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8961                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8962         }
8963 }
8964 #endif