drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "intel_drv.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_dp.h"
  34
  35 #include "drm_crtc_helper.h"
  36
  37 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  38
  39 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  40 static void intel_update_watermarks(struct drm_device *dev);
  41
  42 typedef struct {
  43     /* given values */
  44     int n;
  45     int m1, m2;
  46     int p1, p2;
  47     /* derived values */
  48     int dot;
  49     int vco;
  50     int m;
  51     int p;
  52 } intel_clock_t;
  53
  54 typedef struct {
  55     int min, max;
  56 } intel_range_t;
  57
  58 typedef struct {
  59     int dot_limit;
  60     int p2_slow, p2_fast;
  61 } intel_p2_t;
  62
  63 #define INTEL_P2_NUM                  2
  64 typedef struct intel_limit intel_limit_t;
  65 struct intel_limit {
  66     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  67     intel_p2_t      p2;
  68     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  69                       int, int, intel_clock_t *);
  70 };
  71
  72 #define I8XX_DOT_MIN              25000
  73 #define I8XX_DOT_MAX             350000
  74 #define I8XX_VCO_MIN             930000
  75 #define I8XX_VCO_MAX            1400000
  76 #define I8XX_N_MIN                    3
  77 #define I8XX_N_MAX                   16
  78 #define I8XX_M_MIN                   96
  79 #define I8XX_M_MAX                  140
  80 #define I8XX_M1_MIN                  18
  81 #define I8XX_M1_MAX                  26
  82 #define I8XX_M2_MIN                   6
  83 #define I8XX_M2_MAX                  16
  84 #define I8XX_P_MIN                    4
  85 #define I8XX_P_MAX                  128
  86 #define I8XX_P1_MIN                   2
  87 #define I8XX_P1_MAX                  33
  88 #define I8XX_P1_LVDS_MIN              1
  89 #define I8XX_P1_LVDS_MAX              6
  90 #define I8XX_P2_SLOW                  4
  91 #define I8XX_P2_FAST                  2
  92 #define I8XX_P2_LVDS_SLOW             14
  93 #define I8XX_P2_LVDS_FAST             7
  94 #define I8XX_P2_SLOW_LIMIT       165000
  95
  96 #define I9XX_DOT_MIN              20000
  97 #define I9XX_DOT_MAX             400000
  98 #define I9XX_VCO_MIN            1400000
  99 #define I9XX_VCO_MAX            2800000
 100 #define IGD_VCO_MIN             1700000
 101 #define IGD_VCO_MAX             3500000
 102 #define I9XX_N_MIN                    1
 103 #define I9XX_N_MAX                    6
 104 /* IGD's Ncounter is a ring counter */
 105 #define IGD_N_MIN                     3
 106 #define IGD_N_MAX                     6
 107 #define I9XX_M_MIN                   70
 108 #define I9XX_M_MAX                  120
 109 #define IGD_M_MIN                     2
 110 #define IGD_M_MAX                   256
 111 #define I9XX_M1_MIN                  10
 112 #define I9XX_M1_MAX                  22
 113 #define I9XX_M2_MIN                   5
 114 #define I9XX_M2_MAX                   9
 115 /* IGD M1 is reserved, and must be 0 */
 116 #define IGD_M1_MIN                    0
 117 #define IGD_M1_MAX                    0
 118 #define IGD_M2_MIN                    0
 119 #define IGD_M2_MAX                    254
 120 #define I9XX_P_SDVO_DAC_MIN           5
 121 #define I9XX_P_SDVO_DAC_MAX          80
 122 #define I9XX_P_LVDS_MIN               7
 123 #define I9XX_P_LVDS_MAX              98
 124 #define IGD_P_LVDS_MIN                7
 125 #define IGD_P_LVDS_MAX               112
 126 #define I9XX_P1_MIN                   1
 127 #define I9XX_P1_MAX                   8
 128 #define I9XX_P2_SDVO_DAC_SLOW                10
 129 #define I9XX_P2_SDVO_DAC_FAST                 5
 130 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 131 #define I9XX_P2_LVDS_SLOW                    14
 132 #define I9XX_P2_LVDS_FAST                     7
 133 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 134
 135 /*The parameter is for SDVO on G4x platform*/
 136 #define G4X_DOT_SDVO_MIN           25000
 137 #define G4X_DOT_SDVO_MAX           270000
 138 #define G4X_VCO_MIN                1750000
 139 #define G4X_VCO_MAX                3500000
 140 #define G4X_N_SDVO_MIN             1
 141 #define G4X_N_SDVO_MAX             4
 142 #define G4X_M_SDVO_MIN             104
 143 #define G4X_M_SDVO_MAX             138
 144 #define G4X_M1_SDVO_MIN            17
 145 #define G4X_M1_SDVO_MAX            23
 146 #define G4X_M2_SDVO_MIN            5
 147 #define G4X_M2_SDVO_MAX            11
 148 #define G4X_P_SDVO_MIN             10
 149 #define G4X_P_SDVO_MAX             30
 150 #define G4X_P1_SDVO_MIN            1
 151 #define G4X_P1_SDVO_MAX            3
 152 #define G4X_P2_SDVO_SLOW           10
 153 #define G4X_P2_SDVO_FAST           10
 154 #define G4X_P2_SDVO_LIMIT          270000
 155
 156 /*The parameter is for HDMI_DAC on G4x platform*/
 157 #define G4X_DOT_HDMI_DAC_MIN           22000
 158 #define G4X_DOT_HDMI_DAC_MAX           400000
 159 #define G4X_N_HDMI_DAC_MIN             1
 160 #define G4X_N_HDMI_DAC_MAX             4
 161 #define G4X_M_HDMI_DAC_MIN             104
 162 #define G4X_M_HDMI_DAC_MAX             138
 163 #define G4X_M1_HDMI_DAC_MIN            16
 164 #define G4X_M1_HDMI_DAC_MAX            23
 165 #define G4X_M2_HDMI_DAC_MIN            5
 166 #define G4X_M2_HDMI_DAC_MAX            11
 167 #define G4X_P_HDMI_DAC_MIN             5
 168 #define G4X_P_HDMI_DAC_MAX             80
 169 #define G4X_P1_HDMI_DAC_MIN            1
 170 #define G4X_P1_HDMI_DAC_MAX            8
 171 #define G4X_P2_HDMI_DAC_SLOW           10
 172 #define G4X_P2_HDMI_DAC_FAST           5
 173 #define G4X_P2_HDMI_DAC_LIMIT          165000
 174
 175 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 176 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 177 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 178 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 179 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 180 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 181 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 182 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 183 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 184 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 185 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 186 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 187 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 188 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 189 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 190 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 191 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 192 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 193
 194 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 195 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 196 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 197 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 198 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 199 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 200 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 201 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 202 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 203 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 204 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 205 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 206 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 207 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 208 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 209 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 210 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 211 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 212
 213 /*The parameter is for DISPLAY PORT on G4x platform*/
 214 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 215 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 216 #define G4X_N_DISPLAY_PORT_MIN             1
 217 #define G4X_N_DISPLAY_PORT_MAX             2
 218 #define G4X_M_DISPLAY_PORT_MIN             97
 219 #define G4X_M_DISPLAY_PORT_MAX             108
 220 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 221 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 222 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 223 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 224 #define G4X_P_DISPLAY_PORT_MIN             10
 225 #define G4X_P_DISPLAY_PORT_MAX             20
 226 #define G4X_P1_DISPLAY_PORT_MIN            1
 227 #define G4X_P1_DISPLAY_PORT_MAX            2
 228 #define G4X_P2_DISPLAY_PORT_SLOW           10
 229 #define G4X_P2_DISPLAY_PORT_FAST           10
 230 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 231
 232 /* IGDNG */
 233 /* as we calculate clock using (register_value + 2) for
 234    N/M1/M2, so here the range value for them is (actual_value-2).
 235  */
 236 #define IGDNG_DOT_MIN         25000
 237 #define IGDNG_DOT_MAX         350000
 238 #define IGDNG_VCO_MIN         1760000
 239 #define IGDNG_VCO_MAX         3510000
 240 #define IGDNG_N_MIN           1
 241 #define IGDNG_N_MAX           5
 242 #define IGDNG_M_MIN           79
 243 #define IGDNG_M_MAX           118
 244 #define IGDNG_M1_MIN          12
 245 #define IGDNG_M1_MAX          23
 246 #define IGDNG_M2_MIN          5
 247 #define IGDNG_M2_MAX          9
 248 #define IGDNG_P_SDVO_DAC_MIN  5
 249 #define IGDNG_P_SDVO_DAC_MAX  80
 250 #define IGDNG_P_LVDS_MIN      28
 251 #define IGDNG_P_LVDS_MAX      112
 252 #define IGDNG_P1_MIN          1
 253 #define IGDNG_P1_MAX          8
 254 #define IGDNG_P2_SDVO_DAC_SLOW 10
 255 #define IGDNG_P2_SDVO_DAC_FAST 5
 256 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 257 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 258 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 259
 260 static bool
 261 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 262                     int target, int refclk, intel_clock_t *best_clock);
 263 static bool
 264 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 265                         int target, int refclk, intel_clock_t *best_clock);
 266 static bool
 267 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 268                         int target, int refclk, intel_clock_t *best_clock);
 269
 270 static bool
 271 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 272                       int target, int refclk, intel_clock_t *best_clock);
 273 static bool
 274 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 275                       int target, int refclk, intel_clock_t *best_clock);
 276
 277 static const intel_limit_t intel_limits_i8xx_dvo = {
 278         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 279         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 280         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 281         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 282         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 283         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 284         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 285         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 286         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 287                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 288         .find_pll = intel_find_best_PLL,
 289 };
 290
 291 static const intel_limit_t intel_limits_i8xx_lvds = {
 292         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 293         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 294         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 295         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 296         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 297         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 298         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 299         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 300         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 301                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 302         .find_pll = intel_find_best_PLL,
 303 };
 304
 305 static const intel_limit_t intel_limits_i9xx_sdvo = {
 306         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 307         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 308         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 309         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 310         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 311         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 312         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 313         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 314         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 315                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 316         .find_pll = intel_find_best_PLL,
 317 };
 318
 319 static const intel_limit_t intel_limits_i9xx_lvds = {
 320         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 321         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 322         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 323         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 324         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 325         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 326         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 327         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 328         /* The single-channel range is 25-112Mhz, and dual-channel
 329          * is 80-224Mhz.  Prefer single channel as much as possible.
 330          */
 331         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 332                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 333         .find_pll = intel_find_best_PLL,
 334 };
 335
 336     /* below parameter and function is for G4X Chipset Family*/
 337 static const intel_limit_t intel_limits_g4x_sdvo = {
 338         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 339         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 340         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 341         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 342         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 343         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 344         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 345         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 346         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 347                  .p2_slow = G4X_P2_SDVO_SLOW,
 348                  .p2_fast = G4X_P2_SDVO_FAST
 349         },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_g4x_hdmi = {
 354         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 355         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 356         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 357         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 358         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 359         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 360         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 361         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 362         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 363                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 364                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 365         },
 366         .find_pll = intel_g4x_find_best_PLL,
 367 };
 368
 369 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 370         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 371                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 372         .vco = { .min = G4X_VCO_MIN,
 373                  .max = G4X_VCO_MAX },
 374         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 375                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 376         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 377                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 378         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 379                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 380         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 381                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 382         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 383                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 384         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 386         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 387                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 388                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 389         },
 390         .find_pll = intel_g4x_find_best_PLL,
 391 };
 392
 393 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 394         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 395                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 396         .vco = { .min = G4X_VCO_MIN,
 397                  .max = G4X_VCO_MAX },
 398         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 399                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 400         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 401                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 402         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 403                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 404         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 405                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 406         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 407                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 408         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 409                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 410         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 411                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 412                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 413         },
 414         .find_pll = intel_g4x_find_best_PLL,
 415 };
 416
 417 static const intel_limit_t intel_limits_g4x_display_port = {
 418         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 419                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 420         .vco = { .min = G4X_VCO_MIN,
 421                  .max = G4X_VCO_MAX},
 422         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 423                  .max = G4X_N_DISPLAY_PORT_MAX },
 424         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 425                  .max = G4X_M_DISPLAY_PORT_MAX },
 426         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 427                  .max = G4X_M1_DISPLAY_PORT_MAX },
 428         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 429                  .max = G4X_M2_DISPLAY_PORT_MAX },
 430         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 431                  .max = G4X_P_DISPLAY_PORT_MAX },
 432         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 433                  .max = G4X_P1_DISPLAY_PORT_MAX},
 434         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 435                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 436                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 437         .find_pll = intel_find_pll_g4x_dp,
 438 };
 439
 440 static const intel_limit_t intel_limits_igd_sdvo = {
 441         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 442         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 443         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 444         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 445         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 446         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 447         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 448         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 449         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 450                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 451         .find_pll = intel_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_igd_lvds = {
 455         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 456         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 457         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 458         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 459         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 460         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 461         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 462         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 463         /* IGD only supports single-channel mode. */
 464         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 465                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 466         .find_pll = intel_find_best_PLL,
 467 };
 468
 469 static const intel_limit_t intel_limits_igdng_sdvo = {
 470         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 471         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 472         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 473         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 474         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 475         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 476         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 477         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 478         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 479                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 480                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 481         .find_pll = intel_igdng_find_best_PLL,
 482 };
 483
 484 static const intel_limit_t intel_limits_igdng_lvds = {
 485         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 486         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 487         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 488         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 489         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 490         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 491         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 492         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 493         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 494                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 495                  .p2_fast = IGDNG_P2_LVDS_FAST },
 496         .find_pll = intel_igdng_find_best_PLL,
 497 };
 498
 499 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 500 {
 501         const intel_limit_t *limit;
 502         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 503                 limit = &intel_limits_igdng_lvds;
 504         else
 505                 limit = &intel_limits_igdng_sdvo;
 506
 507         return limit;
 508 }
 509
 510 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 511 {
 512         struct drm_device *dev = crtc->dev;
 513         struct drm_i915_private *dev_priv = dev->dev_private;
 514         const intel_limit_t *limit;
 515
 516         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 517                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 518                     LVDS_CLKB_POWER_UP)
 519                         /* LVDS with dual channel */
 520                         limit = &intel_limits_g4x_dual_channel_lvds;
 521                 else
 522                         /* LVDS with dual channel */
 523                         limit = &intel_limits_g4x_single_channel_lvds;
 524         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 525                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 526                 limit = &intel_limits_g4x_hdmi;
 527         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 528                 limit = &intel_limits_g4x_sdvo;
 529         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 530                 limit = &intel_limits_g4x_display_port;
 531         } else /* The option is for other outputs */
 532                 limit = &intel_limits_i9xx_sdvo;
 533
 534         return limit;
 535 }
 536
 537 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 538 {
 539         struct drm_device *dev = crtc->dev;
 540         const intel_limit_t *limit;
 541
 542         if (IS_IGDNG(dev))
 543                 limit = intel_igdng_limit(crtc);
 544         else if (IS_G4X(dev)) {
 545                 limit = intel_g4x_limit(crtc);
 546         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 548                         limit = &intel_limits_i9xx_lvds;
 549                 else
 550                         limit = &intel_limits_i9xx_sdvo;
 551         } else if (IS_IGD(dev)) {
 552                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 553                         limit = &intel_limits_igd_lvds;
 554                 else
 555                         limit = &intel_limits_igd_sdvo;
 556         } else {
 557                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 558                         limit = &intel_limits_i8xx_lvds;
 559                 else
 560                         limit = &intel_limits_i8xx_dvo;
 561         }
 562         return limit;
 563 }
 564
 565 /* m1 is reserved as 0 in IGD, n is a ring counter */
 566 static void igd_clock(int refclk, intel_clock_t *clock)
 567 {
 568         clock->m = clock->m2 + 2;
 569         clock->p = clock->p1 * clock->p2;
 570         clock->vco = refclk * clock->m / clock->n;
 571         clock->dot = clock->vco / clock->p;
 572 }
 573
 574 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 575 {
 576         if (IS_IGD(dev)) {
 577                 igd_clock(refclk, clock);
 578                 return;
 579         }
 580         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 581         clock->p = clock->p1 * clock->p2;
 582         clock->vco = refclk * clock->m / (clock->n + 2);
 583         clock->dot = clock->vco / clock->p;
 584 }
 585
 586 /**
 587  * Returns whether any output on the specified pipe is of the specified type
 588  */
 589 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 590 {
 591     struct drm_device *dev = crtc->dev;
 592     struct drm_mode_config *mode_config = &dev->mode_config;
 593     struct drm_connector *l_entry;
 594
 595     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 596             if (l_entry->encoder &&
 597                 l_entry->encoder->crtc == crtc) {
 598                     struct intel_output *intel_output = to_intel_output(l_entry);
 599                     if (intel_output->type == type)
 600                             return true;
 601             }
 602     }
 603     return false;
 604 }
 605
 606 struct drm_connector *
 607 intel_pipe_get_output (struct drm_crtc *crtc)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry, *ret = NULL;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     ret = l_entry;
 617                     break;
 618             }
 619     }
 620     return ret;
 621 }
 622
 623 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 624 /**
 625  * Returns whether the given set of divisors are valid for a given refclk with
 626  * the given connectors.
 627  */
 628
 629 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 630 {
 631         const intel_limit_t *limit = intel_limit (crtc);
 632         struct drm_device *dev = crtc->dev;
 633
 634         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 635                 INTELPllInvalid ("p1 out of range\n");
 636         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 637                 INTELPllInvalid ("p out of range\n");
 638         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 639                 INTELPllInvalid ("m2 out of range\n");
 640         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 641                 INTELPllInvalid ("m1 out of range\n");
 642         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 643                 INTELPllInvalid ("m1 <= m2\n");
 644         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 645                 INTELPllInvalid ("m out of range\n");
 646         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 647                 INTELPllInvalid ("n out of range\n");
 648         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 649                 INTELPllInvalid ("vco out of range\n");
 650         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 651          * connector, etc., rather than just a single range.
 652          */
 653         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 654                 INTELPllInvalid ("dot out of range\n");
 655
 656         return true;
 657 }
 658
 659 static bool
 660 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 661                     int target, int refclk, intel_clock_t *best_clock)
 662
 663 {
 664         struct drm_device *dev = crtc->dev;
 665         struct drm_i915_private *dev_priv = dev->dev_private;
 666         intel_clock_t clock;
 667         int err = target;
 668
 669         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 670             (I915_READ(LVDS)) != 0) {
 671                 /*
 672                  * For LVDS, if the panel is on, just rely on its current
 673                  * settings for dual-channel.  We haven't figured out how to
 674                  * reliably set up different single/dual channel state, if we
 675                  * even can.
 676                  */
 677                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 678                     LVDS_CLKB_POWER_UP)
 679                         clock.p2 = limit->p2.p2_fast;
 680                 else
 681                         clock.p2 = limit->p2.p2_slow;
 682         } else {
 683                 if (target < limit->p2.dot_limit)
 684                         clock.p2 = limit->p2.p2_slow;
 685                 else
 686                         clock.p2 = limit->p2.p2_fast;
 687         }
 688
 689         memset (best_clock, 0, sizeof (*best_clock));
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 693                         /* m1 is always 0 in IGD */
 694                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 695                                 break;
 696                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 697                              clock.n++) {
 698                                 for (clock.p1 = limit->p1.min;
 699                                      clock.p1 <= limit->p1.max; clock.p1++) {
 700                                         int this_err;
 701
 702                                         intel_clock(dev, refclk, &clock);
 703
 704                                         if (!intel_PLL_is_valid(crtc, &clock))
 705                                                 continue;
 706
 707                                         this_err = abs(clock.dot - target);
 708                                         if (this_err < err) {
 709                                                 *best_clock = clock;
 710                                                 err = this_err;
 711                                         }
 712                                 }
 713                         }
 714                 }
 715         }
 716
 717         return (err != target);
 718 }
 719
 720 static bool
 721 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 722                         int target, int refclk, intel_clock_t *best_clock)
 723 {
 724         struct drm_device *dev = crtc->dev;
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         intel_clock_t clock;
 727         int max_n;
 728         bool found;
 729         /* approximately equals target * 0.00488 */
 730         int err_most = (target >> 8) + (target >> 10);
 731         found = false;
 732
 733         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 734                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 735                     LVDS_CLKB_POWER_UP)
 736                         clock.p2 = limit->p2.p2_fast;
 737                 else
 738                         clock.p2 = limit->p2.p2_slow;
 739         } else {
 740                 if (target < limit->p2.dot_limit)
 741                         clock.p2 = limit->p2.p2_slow;
 742                 else
 743                         clock.p2 = limit->p2.p2_fast;
 744         }
 745
 746         memset(best_clock, 0, sizeof(*best_clock));
 747         max_n = limit->n.max;
 748         /* based on hardware requriment prefer smaller n to precision */
 749         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 750                 /* based on hardware requirment prefere larger m1,m2, p1 */
 751                 for (clock.m1 = limit->m1.max;
 752                      clock.m1 >= limit->m1.min; clock.m1--) {
 753                         for (clock.m2 = limit->m2.max;
 754                              clock.m2 >= limit->m2.min; clock.m2--) {
 755                                 for (clock.p1 = limit->p1.max;
 756                                      clock.p1 >= limit->p1.min; clock.p1--) {
 757                                         int this_err;
 758
 759                                         intel_clock(dev, refclk, &clock);
 760                                         if (!intel_PLL_is_valid(crtc, &clock))
 761                                                 continue;
 762                                         this_err = abs(clock.dot - target) ;
 763                                         if (this_err < err_most) {
 764                                                 *best_clock = clock;
 765                                                 err_most = this_err;
 766                                                 max_n = clock.n;
 767                                                 found = true;
 768                                         }
 769                                 }
 770                         }
 771                 }
 772         }
 773         return found;
 774 }
 775
 776 static bool
 777 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 778                       int target, int refclk, intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         intel_clock_t clock;
 782         if (target < 200000) {
 783                 clock.n = 1;
 784                 clock.p1 = 2;
 785                 clock.p2 = 10;
 786                 clock.m1 = 12;
 787                 clock.m2 = 9;
 788         } else {
 789                 clock.n = 2;
 790                 clock.p1 = 1;
 791                 clock.p2 = 10;
 792                 clock.m1 = 14;
 793                 clock.m2 = 8;
 794         }
 795         intel_clock(dev, refclk, &clock);
 796         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 797         return true;
 798 }
 799
 800 static bool
 801 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 802                         int target, int refclk, intel_clock_t *best_clock)
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         intel_clock_t clock;
 807         int max_n;
 808         bool found;
 809         int err_most = 47;
 810         found = false;
 811
 812         /* eDP has only 2 clock choice, no n/m/p setting */
 813         if (HAS_eDP)
 814                 return true;
 815
 816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 817                 return intel_find_pll_igdng_dp(limit, crtc, target,
 818                                                refclk, best_clock);
 819
 820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset(best_clock, 0, sizeof(*best_clock));
 834         max_n = limit->n.max;
 835         /* based on hardware requriment prefer smaller n to precision */
 836         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 837                 /* based on hardware requirment prefere larger m1,m2, p1 */
 838                 for (clock.m1 = limit->m1.max;
 839                      clock.m1 >= limit->m1.min; clock.m1--) {
 840                         for (clock.m2 = limit->m2.max;
 841                              clock.m2 >= limit->m2.min; clock.m2--) {
 842                                 for (clock.p1 = limit->p1.max;
 843                                      clock.p1 >= limit->p1.min; clock.p1--) {
 844                                         int this_err;
 845
 846                                         intel_clock(dev, refclk, &clock);
 847                                         if (!intel_PLL_is_valid(crtc, &clock))
 848                                                 continue;
 849                                         this_err = abs((10000 - (target*10000/clock.dot)));
 850                                         if (this_err < err_most) {
 851                                                 *best_clock = clock;
 852                                                 err_most = this_err;
 853                                                 max_n = clock.n;
 854                                                 found = true;
 855                                                 /* found on first matching */
 856                                                 goto out;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862 out:
 863         return found;
 864 }
 865
 866 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 867 static bool
 868 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 869                       int target, int refclk, intel_clock_t *best_clock)
 870 {
 871     intel_clock_t clock;
 872     if (target < 200000) {
 873         clock.p1 = 2;
 874         clock.p2 = 10;
 875         clock.n = 2;
 876         clock.m1 = 23;
 877         clock.m2 = 8;
 878     } else {
 879         clock.p1 = 1;
 880         clock.p2 = 10;
 881         clock.n = 1;
 882         clock.m1 = 14;
 883         clock.m2 = 2;
 884     }
 885     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 886     clock.p = (clock.p1 * clock.p2);
 887     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 888     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 889     return true;
 890 }
 891
 892 void
 893 intel_wait_for_vblank(struct drm_device *dev)
 894 {
 895         /* Wait for 20ms, i.e. one cycle at 50hz. */
 896         mdelay(20);
 897 }
 898
 899 static int
 900 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 901                     struct drm_framebuffer *old_fb)
 902 {
 903         struct drm_device *dev = crtc->dev;
 904         struct drm_i915_private *dev_priv = dev->dev_private;
 905         struct drm_i915_master_private *master_priv;
 906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 907         struct intel_framebuffer *intel_fb;
 908         struct drm_i915_gem_object *obj_priv;
 909         struct drm_gem_object *obj;
 910         int pipe = intel_crtc->pipe;
 911         unsigned long Start, Offset;
 912         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 913         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 914         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 915         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 916         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 917         u32 dspcntr, alignment;
 918         int ret;
 919
 920         /* no fb bound */
 921         if (!crtc->fb) {
 922                 DRM_DEBUG("No FB bound\n");
 923                 return 0;
 924         }
 925
 926         switch (pipe) {
 927         case 0:
 928         case 1:
 929                 break;
 930         default:
 931                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 932                 return -EINVAL;
 933         }
 934
 935         intel_fb = to_intel_framebuffer(crtc->fb);
 936         obj = intel_fb->obj;
 937         obj_priv = obj->driver_private;
 938
 939         switch (obj_priv->tiling_mode) {
 940         case I915_TILING_NONE:
 941                 alignment = 64 * 1024;
 942                 break;
 943         case I915_TILING_X:
 944                 /* pin() will align the object as required by fence */
 945                 alignment = 0;
 946                 break;
 947         case I915_TILING_Y:
 948                 /* FIXME: Is this true? */
 949                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 950                 return -EINVAL;
 951         default:
 952                 BUG();
 953         }
 954
 955         mutex_lock(&dev->struct_mutex);
 956         ret = i915_gem_object_pin(obj, alignment);
 957         if (ret != 0) {
 958                 mutex_unlock(&dev->struct_mutex);
 959                 return ret;
 960         }
 961
 962         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 963         if (ret != 0) {
 964                 i915_gem_object_unpin(obj);
 965                 mutex_unlock(&dev->struct_mutex);
 966                 return ret;
 967         }
 968
 969         /* Pre-i965 needs to install a fence for tiled scan-out */
 970         if (!IS_I965G(dev) &&
 971             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 972             obj_priv->tiling_mode != I915_TILING_NONE) {
 973                 ret = i915_gem_object_get_fence_reg(obj);
 974                 if (ret != 0) {
 975                         i915_gem_object_unpin(obj);
 976                         mutex_unlock(&dev->struct_mutex);
 977                         return ret;
 978                 }
 979         }
 980
 981         dspcntr = I915_READ(dspcntr_reg);
 982         /* Mask out pixel format bits in case we change it */
 983         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 984         switch (crtc->fb->bits_per_pixel) {
 985         case 8:
 986                 dspcntr |= DISPPLANE_8BPP;
 987                 break;
 988         case 16:
 989                 if (crtc->fb->depth == 15)
 990                         dspcntr |= DISPPLANE_15_16BPP;
 991                 else
 992                         dspcntr |= DISPPLANE_16BPP;
 993                 break;
 994         case 24:
 995         case 32:
 996                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 997                 break;
 998         default:
 999                 DRM_ERROR("Unknown color depth\n");
1000                 i915_gem_object_unpin(obj);
1001                 mutex_unlock(&dev->struct_mutex);
1002                 return -EINVAL;
1003         }
1004         if (IS_I965G(dev)) {
1005                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1006                         dspcntr |= DISPPLANE_TILED;
1007                 else
1008                         dspcntr &= ~DISPPLANE_TILED;
1009         }
1010
1011         I915_WRITE(dspcntr_reg, dspcntr);
1012
1013         Start = obj_priv->gtt_offset;
1014         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1015
1016         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1017         I915_WRITE(dspstride, crtc->fb->pitch);
1018         if (IS_I965G(dev)) {
1019                 I915_WRITE(dspbase, Offset);
1020                 I915_READ(dspbase);
1021                 I915_WRITE(dspsurf, Start);
1022                 I915_READ(dspsurf);
1023                 I915_WRITE(dsptileoff, (y << 16) | x);
1024         } else {
1025                 I915_WRITE(dspbase, Start + Offset);
1026                 I915_READ(dspbase);
1027         }
1028
1029         intel_wait_for_vblank(dev);
1030
1031         if (old_fb) {
1032                 intel_fb = to_intel_framebuffer(old_fb);
1033                 i915_gem_object_unpin(intel_fb->obj);
1034         }
1035         mutex_unlock(&dev->struct_mutex);
1036
1037         if (!dev->primary->master)
1038                 return 0;
1039
1040         master_priv = dev->primary->master->driver_priv;
1041         if (!master_priv->sarea_priv)
1042                 return 0;
1043
1044         if (pipe) {
1045                 master_priv->sarea_priv->pipeB_x = x;
1046                 master_priv->sarea_priv->pipeB_y = y;
1047         } else {
1048                 master_priv->sarea_priv->pipeA_x = x;
1049                 master_priv->sarea_priv->pipeA_y = y;
1050         }
1051
1052         return 0;
1053 }
1054
1055 /* Disable the VGA plane that we never use */
1056 static void i915_disable_vga (struct drm_device *dev)
1057 {
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         u8 sr1;
1060         u32 vga_reg;
1061
1062         if (IS_IGDNG(dev))
1063                 vga_reg = CPU_VGACNTRL;
1064         else
1065                 vga_reg = VGACNTRL;
1066
1067         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1068                 return;
1069
1070         I915_WRITE8(VGA_SR_INDEX, 1);
1071         sr1 = I915_READ8(VGA_SR_DATA);
1072         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1073         udelay(100);
1074
1075         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1076 }
1077
1078 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1079 {
1080         struct drm_device *dev = crtc->dev;
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082         u32 dpa_ctl;
1083
1084         DRM_DEBUG("\n");
1085         dpa_ctl = I915_READ(DP_A);
1086         dpa_ctl &= ~DP_PLL_ENABLE;
1087         I915_WRITE(DP_A, dpa_ctl);
1088 }
1089
1090 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1091 {
1092         struct drm_device *dev = crtc->dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         u32 dpa_ctl;
1095
1096         dpa_ctl = I915_READ(DP_A);
1097         dpa_ctl |= DP_PLL_ENABLE;
1098         I915_WRITE(DP_A, dpa_ctl);
1099         udelay(200);
1100 }
1101
1102
1103 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1104 {
1105         struct drm_device *dev = crtc->dev;
1106         struct drm_i915_private *dev_priv = dev->dev_private;
1107         u32 dpa_ctl;
1108
1109         DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1110         dpa_ctl = I915_READ(DP_A);
1111         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1112
1113         if (clock < 200000) {
1114                 u32 temp;
1115                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1116                 /* workaround for 160Mhz:
1117                    1) program 0x4600c bits 15:0 = 0x8124
1118                    2) program 0x46010 bit 0 = 1
1119                    3) program 0x46034 bit 24 = 1
1120                    4) program 0x64000 bit 14 = 1
1121                    */
1122                 temp = I915_READ(0x4600c);
1123                 temp &= 0xffff0000;
1124                 I915_WRITE(0x4600c, temp | 0x8124);
1125
1126                 temp = I915_READ(0x46010);
1127                 I915_WRITE(0x46010, temp | 1);
1128
1129                 temp = I915_READ(0x46034);
1130                 I915_WRITE(0x46034, temp | (1 << 24));
1131         } else {
1132                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1133         }
1134         I915_WRITE(DP_A, dpa_ctl);
1135
1136         udelay(500);
1137 }
1138
1139 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1140 {
1141         struct drm_device *dev = crtc->dev;
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1144         int pipe = intel_crtc->pipe;
1145         int plane = intel_crtc->plane;
1146         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1147         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1148         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1149         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1150         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1151         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1152         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1153         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1154         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1155         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1156         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1157         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1158         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1159         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1160         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1161         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1162         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1163         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1164         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1165         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1166         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1167         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1168         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1169         u32 temp;
1170         int tries = 5, j, n;
1171
1172         /* XXX: When our outputs are all unaware of DPMS modes other than off
1173          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1174          */
1175         switch (mode) {
1176         case DRM_MODE_DPMS_ON:
1177         case DRM_MODE_DPMS_STANDBY:
1178         case DRM_MODE_DPMS_SUSPEND:
1179                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1180                 if (HAS_eDP) {
1181                         /* enable eDP PLL */
1182                         igdng_enable_pll_edp(crtc);
1183                 } else {
1184                         /* enable PCH DPLL */
1185                         temp = I915_READ(pch_dpll_reg);
1186                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1187                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1188                                 I915_READ(pch_dpll_reg);
1189                         }
1190
1191                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1192                         temp = I915_READ(fdi_rx_reg);
1193                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1194                                         FDI_SEL_PCDCLK |
1195                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1196                         I915_READ(fdi_rx_reg);
1197                         udelay(200);
1198
1199                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1200                         temp = I915_READ(fdi_tx_reg);
1201                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1202                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1203                                 I915_READ(fdi_tx_reg);
1204                                 udelay(100);
1205                         }
1206                 }
1207
1208                 /* Enable CPU pipe */
1209                 temp = I915_READ(pipeconf_reg);
1210                 if ((temp & PIPEACONF_ENABLE) == 0) {
1211                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1212                         I915_READ(pipeconf_reg);
1213                         udelay(100);
1214                 }
1215
1216                 /* configure and enable CPU plane */
1217                 temp = I915_READ(dspcntr_reg);
1218                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1219                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1220                         /* Flush the plane changes */
1221                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1222                 }
1223
1224                 if (!HAS_eDP) {
1225                         /* enable CPU FDI TX and PCH FDI RX */
1226                         temp = I915_READ(fdi_tx_reg);
1227                         temp |= FDI_TX_ENABLE;
1228                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1229                         temp &= ~FDI_LINK_TRAIN_NONE;
1230                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1231                         I915_WRITE(fdi_tx_reg, temp);
1232                         I915_READ(fdi_tx_reg);
1233
1234                         temp = I915_READ(fdi_rx_reg);
1235                         temp &= ~FDI_LINK_TRAIN_NONE;
1236                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1237                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1238                         I915_READ(fdi_rx_reg);
1239
1240                         udelay(150);
1241
1242                         /* Train FDI. */
1243                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1244                            for train result */
1245                         temp = I915_READ(fdi_rx_imr_reg);
1246                         temp &= ~FDI_RX_SYMBOL_LOCK;
1247                         temp &= ~FDI_RX_BIT_LOCK;
1248                         I915_WRITE(fdi_rx_imr_reg, temp);
1249                         I915_READ(fdi_rx_imr_reg);
1250                         udelay(150);
1251
1252                         temp = I915_READ(fdi_rx_iir_reg);
1253                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1254
1255                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1256                                 for (j = 0; j < tries; j++) {
1257                                         temp = I915_READ(fdi_rx_iir_reg);
1258                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1259                                         if (temp & FDI_RX_BIT_LOCK)
1260                                                 break;
1261                                         udelay(200);
1262                                 }
1263                                 if (j != tries)
1264                                         I915_WRITE(fdi_rx_iir_reg,
1265                                                         temp | FDI_RX_BIT_LOCK);
1266                                 else
1267                                         DRM_DEBUG("train 1 fail\n");
1268                         } else {
1269                                 I915_WRITE(fdi_rx_iir_reg,
1270                                                 temp | FDI_RX_BIT_LOCK);
1271                                 DRM_DEBUG("train 1 ok 2!\n");
1272                         }
1273                         temp = I915_READ(fdi_tx_reg);
1274                         temp &= ~FDI_LINK_TRAIN_NONE;
1275                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1276                         I915_WRITE(fdi_tx_reg, temp);
1277
1278                         temp = I915_READ(fdi_rx_reg);
1279                         temp &= ~FDI_LINK_TRAIN_NONE;
1280                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1281                         I915_WRITE(fdi_rx_reg, temp);
1282
1283                         udelay(150);
1284
1285                         temp = I915_READ(fdi_rx_iir_reg);
1286                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1287
1288                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1289                                 for (j = 0; j < tries; j++) {
1290                                         temp = I915_READ(fdi_rx_iir_reg);
1291                                         DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1292                                         if (temp & FDI_RX_SYMBOL_LOCK)
1293                                                 break;
1294                                         udelay(200);
1295                                 }
1296                                 if (j != tries) {
1297                                         I915_WRITE(fdi_rx_iir_reg,
1298                                                         temp | FDI_RX_SYMBOL_LOCK);
1299                                         DRM_DEBUG("train 2 ok 1!\n");
1300                                 } else
1301                                         DRM_DEBUG("train 2 fail\n");
1302                         } else {
1303                                 I915_WRITE(fdi_rx_iir_reg,
1304                                                 temp | FDI_RX_SYMBOL_LOCK);
1305                                 DRM_DEBUG("train 2 ok 2!\n");
1306                         }
1307                         DRM_DEBUG("train done\n");
1308
1309                         /* set transcoder timing */
1310                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1311                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1312                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1313
1314                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1315                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1316                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1317
1318                         /* enable PCH transcoder */
1319                         temp = I915_READ(transconf_reg);
1320                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1321                         I915_READ(transconf_reg);
1322
1323                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1324                                 ;
1325
1326                         /* enable normal */
1327
1328                         temp = I915_READ(fdi_tx_reg);
1329                         temp &= ~FDI_LINK_TRAIN_NONE;
1330                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1331                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1332                         I915_READ(fdi_tx_reg);
1333
1334                         temp = I915_READ(fdi_rx_reg);
1335                         temp &= ~FDI_LINK_TRAIN_NONE;
1336                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1337                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1338                         I915_READ(fdi_rx_reg);
1339
1340                         /* wait one idle pattern time */
1341                         udelay(100);
1342
1343                 }
1344
1345                 intel_crtc_load_lut(crtc);
1346
1347         break;
1348         case DRM_MODE_DPMS_OFF:
1349                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1350
1351                 i915_disable_vga(dev);
1352
1353                 /* Disable display plane */
1354                 temp = I915_READ(dspcntr_reg);
1355                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1356                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1357                         /* Flush the plane changes */
1358                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1359                         I915_READ(dspbase_reg);
1360                 }
1361
1362                 /* disable cpu pipe, disable after all planes disabled */
1363                 temp = I915_READ(pipeconf_reg);
1364                 if ((temp & PIPEACONF_ENABLE) != 0) {
1365                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1366                         I915_READ(pipeconf_reg);
1367                         n = 0;
1368                         /* wait for cpu pipe off, pipe state */
1369                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1370                                 n++;
1371                                 if (n < 60) {
1372                                         udelay(500);
1373                                         continue;
1374                                 } else {
1375                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1376                                         break;
1377                                 }
1378                         }
1379                 } else
1380                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1381
1382                 if (HAS_eDP) {
1383                         igdng_disable_pll_edp(crtc);
1384                 }
1385
1386                 /* disable CPU FDI tx and PCH FDI rx */
1387                 temp = I915_READ(fdi_tx_reg);
1388                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1389                 I915_READ(fdi_tx_reg);
1390
1391                 temp = I915_READ(fdi_rx_reg);
1392                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1393                 I915_READ(fdi_rx_reg);
1394
1395                 udelay(100);
1396
1397                 /* still set train pattern 1 */
1398                 temp = I915_READ(fdi_tx_reg);
1399                 temp &= ~FDI_LINK_TRAIN_NONE;
1400                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1401                 I915_WRITE(fdi_tx_reg, temp);
1402
1403                 temp = I915_READ(fdi_rx_reg);
1404                 temp &= ~FDI_LINK_TRAIN_NONE;
1405                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1406                 I915_WRITE(fdi_rx_reg, temp);
1407
1408                 udelay(100);
1409
1410                 /* disable PCH transcoder */
1411                 temp = I915_READ(transconf_reg);
1412                 if ((temp & TRANS_ENABLE) != 0) {
1413                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1414                         I915_READ(transconf_reg);
1415                         n = 0;
1416                         /* wait for PCH transcoder off, transcoder state */
1417                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1418                                 n++;
1419                                 if (n < 60) {
1420                                         udelay(500);
1421                                         continue;
1422                                 } else {
1423                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1424                                         break;
1425                                 }
1426                         }
1427                 }
1428
1429                 /* disable PCH DPLL */
1430                 temp = I915_READ(pch_dpll_reg);
1431                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1432                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1433                         I915_READ(pch_dpll_reg);
1434                 }
1435
1436                 temp = I915_READ(fdi_rx_reg);
1437                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1438                         temp &= ~FDI_SEL_PCDCLK;
1439                         temp &= ~FDI_RX_PLL_ENABLE;
1440                         I915_WRITE(fdi_rx_reg, temp);
1441                         I915_READ(fdi_rx_reg);
1442                 }
1443
1444                 /* Disable CPU FDI TX PLL */
1445                 temp = I915_READ(fdi_tx_reg);
1446                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1447                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1448                         I915_READ(fdi_tx_reg);
1449                         udelay(100);
1450                 }
1451
1452                 /* Disable PF */
1453                 temp = I915_READ(pf_ctl_reg);
1454                 if ((temp & PF_ENABLE) != 0) {
1455                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1456                         I915_READ(pf_ctl_reg);
1457                 }
1458                 I915_WRITE(pf_win_size, 0);
1459
1460                 /* Wait for the clocks to turn off. */
1461                 udelay(150);
1462                 break;
1463         }
1464 }
1465
1466 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1467 {
1468         struct drm_device *dev = crtc->dev;
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1471         int pipe = intel_crtc->pipe;
1472         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1473         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1474         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1475         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1476         u32 temp;
1477
1478         /* XXX: When our outputs are all unaware of DPMS modes other than off
1479          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1480          */
1481         switch (mode) {
1482         case DRM_MODE_DPMS_ON:
1483         case DRM_MODE_DPMS_STANDBY:
1484         case DRM_MODE_DPMS_SUSPEND:
1485                 /* Enable the DPLL */
1486                 temp = I915_READ(dpll_reg);
1487                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1488                         I915_WRITE(dpll_reg, temp);
1489                         I915_READ(dpll_reg);
1490                         /* Wait for the clocks to stabilize. */
1491                         udelay(150);
1492                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1493                         I915_READ(dpll_reg);
1494                         /* Wait for the clocks to stabilize. */
1495                         udelay(150);
1496                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1497                         I915_READ(dpll_reg);
1498                         /* Wait for the clocks to stabilize. */
1499                         udelay(150);
1500                 }
1501
1502                 /* Enable the pipe */
1503                 temp = I915_READ(pipeconf_reg);
1504                 if ((temp & PIPEACONF_ENABLE) == 0)
1505                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1506
1507                 /* Enable the plane */
1508                 temp = I915_READ(dspcntr_reg);
1509                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1510                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1511                         /* Flush the plane changes */
1512                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1513                 }
1514
1515                 intel_crtc_load_lut(crtc);
1516
1517                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1518                 //intel_crtc_dpms_video(crtc, true); TODO
1519                 intel_update_watermarks(dev);
1520         break;
1521         case DRM_MODE_DPMS_OFF:
1522                 intel_update_watermarks(dev);
1523                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1524                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1525
1526                 /* Disable the VGA plane that we never use */
1527                 i915_disable_vga(dev);
1528
1529                 /* Disable display plane */
1530                 temp = I915_READ(dspcntr_reg);
1531                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1532                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1533                         /* Flush the plane changes */
1534                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1535                         I915_READ(dspbase_reg);
1536                 }
1537
1538                 if (!IS_I9XX(dev)) {
1539                         /* Wait for vblank for the disable to take effect */
1540                         intel_wait_for_vblank(dev);
1541                 }
1542
1543                 /* Next, disable display pipes */
1544                 temp = I915_READ(pipeconf_reg);
1545                 if ((temp & PIPEACONF_ENABLE) != 0) {
1546                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1547                         I915_READ(pipeconf_reg);
1548                 }
1549
1550                 /* Wait for vblank for the disable to take effect. */
1551                 intel_wait_for_vblank(dev);
1552
1553                 temp = I915_READ(dpll_reg);
1554                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1555                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1556                         I915_READ(dpll_reg);
1557                 }
1558
1559                 /* Wait for the clocks to turn off. */
1560                 udelay(150);
1561                 break;
1562         }
1563 }
1564
1565 /**
1566  * Sets the power management mode of the pipe and plane.
1567  *
1568  * This code should probably grow support for turning the cursor off and back
1569  * on appropriately at the same time as we're turning the pipe off/on.
1570  */
1571 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1572 {
1573         struct drm_device *dev = crtc->dev;
1574         struct drm_i915_master_private *master_priv;
1575         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1576         int pipe = intel_crtc->pipe;
1577         bool enabled;
1578
1579         if (IS_IGDNG(dev))
1580                 igdng_crtc_dpms(crtc, mode);
1581         else
1582                 i9xx_crtc_dpms(crtc, mode);
1583
1584         if (!dev->primary->master)
1585                 return;
1586
1587         master_priv = dev->primary->master->driver_priv;
1588         if (!master_priv->sarea_priv)
1589                 return;
1590
1591         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1592
1593         switch (pipe) {
1594         case 0:
1595                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1596                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1597                 break;
1598         case 1:
1599                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1600                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1601                 break;
1602         default:
1603                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1604                 break;
1605         }
1606
1607         intel_crtc->dpms_mode = mode;
1608 }
1609
1610 static void intel_crtc_prepare (struct drm_crtc *crtc)
1611 {
1612         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1613         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1614 }
1615
1616 static void intel_crtc_commit (struct drm_crtc *crtc)
1617 {
1618         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1619         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1620 }
1621
1622 void intel_encoder_prepare (struct drm_encoder *encoder)
1623 {
1624         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1625         /* lvds has its own version of prepare see intel_lvds_prepare */
1626         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1627 }
1628
1629 void intel_encoder_commit (struct drm_encoder *encoder)
1630 {
1631         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1632         /* lvds has its own version of commit see intel_lvds_commit */
1633         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1634 }
1635
1636 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1637                                   struct drm_display_mode *mode,
1638                                   struct drm_display_mode *adjusted_mode)
1639 {
1640         struct drm_device *dev = crtc->dev;
1641         if (IS_IGDNG(dev)) {
1642                 /* FDI link clock is fixed at 2.7G */
1643                 if (mode->clock * 3 > 27000 * 4)
1644                         return MODE_CLOCK_HIGH;
1645         }
1646         return true;
1647 }
1648
1649
1650 /** Returns the core display clock speed for i830 - i945 */
1651 static int intel_get_core_clock_speed(struct drm_device *dev)
1652 {
1653
1654         /* Core clock values taken from the published datasheets.
1655          * The 830 may go up to 166 Mhz, which we should check.
1656          */
1657         if (IS_I945G(dev))
1658                 return 400000;
1659         else if (IS_I915G(dev))
1660                 return 333000;
1661         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1662                 return 200000;
1663         else if (IS_I915GM(dev)) {
1664                 u16 gcfgc = 0;
1665
1666                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1667
1668                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1669                         return 133000;
1670                 else {
1671                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1672                         case GC_DISPLAY_CLOCK_333_MHZ:
1673                                 return 333000;
1674                         default:
1675                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1676                                 return 190000;
1677                         }
1678                 }
1679         } else if (IS_I865G(dev))
1680                 return 266000;
1681         else if (IS_I855(dev)) {
1682                 u16 hpllcc = 0;
1683                 /* Assume that the hardware is in the high speed state.  This
1684                  * should be the default.
1685                  */
1686                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1687                 case GC_CLOCK_133_200:
1688                 case GC_CLOCK_100_200:
1689                         return 200000;
1690                 case GC_CLOCK_166_250:
1691                         return 250000;
1692                 case GC_CLOCK_100_133:
1693                         return 133000;
1694                 }
1695         } else /* 852, 830 */
1696                 return 133000;
1697
1698         return 0; /* Silence gcc warning */
1699 }
1700
1701 /**
1702  * Return the pipe currently connected to the panel fitter,
1703  * or -1 if the panel fitter is not present or not in use
1704  */
1705 static int intel_panel_fitter_pipe (struct drm_device *dev)
1706 {
1707         struct drm_i915_private *dev_priv = dev->dev_private;
1708         u32  pfit_control;
1709
1710         /* i830 doesn't have a panel fitter */
1711         if (IS_I830(dev))
1712                 return -1;
1713
1714         pfit_control = I915_READ(PFIT_CONTROL);
1715
1716         /* See if the panel fitter is in use */
1717         if ((pfit_control & PFIT_ENABLE) == 0)
1718                 return -1;
1719
1720         /* 965 can place panel fitter on either pipe */
1721         if (IS_I965G(dev))
1722                 return (pfit_control >> 29) & 0x3;
1723
1724         /* older chips can only use pipe 1 */
1725         return 1;
1726 }
1727
1728 struct fdi_m_n {
1729         u32        tu;
1730         u32        gmch_m;
1731         u32        gmch_n;
1732         u32        link_m;
1733         u32        link_n;
1734 };
1735
1736 static void
1737 fdi_reduce_ratio(u32 *num, u32 *den)
1738 {
1739         while (*num > 0xffffff || *den > 0xffffff) {
1740                 *num >>= 1;
1741                 *den >>= 1;
1742         }
1743 }
1744
1745 #define DATA_N 0x800000
1746 #define LINK_N 0x80000
1747
1748 static void
1749 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1750                 int pixel_clock, int link_clock,
1751                 struct fdi_m_n *m_n)
1752 {
1753         u64 temp;
1754
1755         m_n->tu = 64; /* default size */
1756
1757         temp = (u64) DATA_N * pixel_clock;
1758         temp = div_u64(temp, link_clock);
1759         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
1760         m_n->gmch_n = DATA_N;
1761         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1762
1763         temp = (u64) LINK_N * pixel_clock;
1764         m_n->link_m = div_u64(temp, link_clock);
1765         m_n->link_n = LINK_N;
1766         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1767 }
1768
1769
1770 struct intel_watermark_params {
1771         unsigned long fifo_size;
1772         unsigned long max_wm;
1773         unsigned long default_wm;
1774         unsigned long guard_size;
1775         unsigned long cacheline_size;
1776 };
1777
1778 /* IGD has different values for various configs */
1779 static struct intel_watermark_params igd_display_wm = {
1780         IGD_DISPLAY_FIFO,
1781         IGD_MAX_WM,
1782         IGD_DFT_WM,
1783         IGD_GUARD_WM,
1784         IGD_FIFO_LINE_SIZE
1785 };
1786 static struct intel_watermark_params igd_display_hplloff_wm = {
1787         IGD_DISPLAY_FIFO,
1788         IGD_MAX_WM,
1789         IGD_DFT_HPLLOFF_WM,
1790         IGD_GUARD_WM,
1791         IGD_FIFO_LINE_SIZE
1792 };
1793 static struct intel_watermark_params igd_cursor_wm = {
1794         IGD_CURSOR_FIFO,
1795         IGD_CURSOR_MAX_WM,
1796         IGD_CURSOR_DFT_WM,
1797         IGD_CURSOR_GUARD_WM,
1798         IGD_FIFO_LINE_SIZE,
1799 };
1800 static struct intel_watermark_params igd_cursor_hplloff_wm = {
1801         IGD_CURSOR_FIFO,
1802         IGD_CURSOR_MAX_WM,
1803         IGD_CURSOR_DFT_WM,
1804         IGD_CURSOR_GUARD_WM,
1805         IGD_FIFO_LINE_SIZE
1806 };
1807 static struct intel_watermark_params i945_wm_info = {
1808         I945_FIFO_SIZE,
1809         I915_MAX_WM,
1810         1,
1811         2,
1812         I915_FIFO_LINE_SIZE
1813 };
1814 static struct intel_watermark_params i915_wm_info = {
1815         I915_FIFO_SIZE,
1816         I915_MAX_WM,
1817         1,
1818         2,
1819         I915_FIFO_LINE_SIZE
1820 };
1821 static struct intel_watermark_params i855_wm_info = {
1822         I855GM_FIFO_SIZE,
1823         I915_MAX_WM,
1824         1,
1825         2,
1826         I830_FIFO_LINE_SIZE
1827 };
1828 static struct intel_watermark_params i830_wm_info = {
1829         I830_FIFO_SIZE,
1830         I915_MAX_WM,
1831         1,
1832         2,
1833         I830_FIFO_LINE_SIZE
1834 };
1835
1836 /**
1837  * intel_calculate_wm - calculate watermark level
1838  * @clock_in_khz: pixel clock
1839  * @wm: chip FIFO params
1840  * @pixel_size: display pixel size
1841  * @latency_ns: memory latency for the platform
1842  *
1843  * Calculate the watermark level (the level at which the display plane will
1844  * start fetching from memory again).  Each chip has a different display
1845  * FIFO size and allocation, so the caller needs to figure that out and pass
1846  * in the correct intel_watermark_params structure.
1847  *
1848  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1849  * on the pixel size.  When it reaches the watermark level, it'll start
1850  * fetching FIFO line sized based chunks from memory until the FIFO fills
1851  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1852  * will occur, and a display engine hang could result.
1853  */
1854 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1855                                         struct intel_watermark_params *wm,
1856                                         int pixel_size,
1857                                         unsigned long latency_ns)
1858 {
1859         long entries_required, wm_size;
1860
1861         entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1862         entries_required /= wm->cacheline_size;
1863
1864         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1865
1866         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1867
1868         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
1869
1870         /* Don't promote wm_size to unsigned... */
1871         if (wm_size > (long)wm->max_wm)
1872                 wm_size = wm->max_wm;
1873         if (wm_size <= 0)
1874                 wm_size = wm->default_wm;
1875         return wm_size;
1876 }
1877
1878 struct cxsr_latency {
1879         int is_desktop;
1880         unsigned long fsb_freq;
1881         unsigned long mem_freq;
1882         unsigned long display_sr;
1883         unsigned long display_hpll_disable;
1884         unsigned long cursor_sr;
1885         unsigned long cursor_hpll_disable;
1886 };
1887
1888 static struct cxsr_latency cxsr_latency_table[] = {
1889         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
1890         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
1891         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
1892
1893         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
1894         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
1895         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
1896
1897         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
1898         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
1899         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
1900
1901         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
1902         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
1903         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
1904
1905         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
1906         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
1907         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
1908
1909         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
1910         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
1911         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
1912 };
1913
1914 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1915                                                    int mem)
1916 {
1917         int i;
1918         struct cxsr_latency *latency;
1919
1920         if (fsb == 0 || mem == 0)
1921                 return NULL;
1922
1923         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1924                 latency = &cxsr_latency_table[i];
1925                 if (is_desktop == latency->is_desktop &&
1926                         fsb == latency->fsb_freq && mem == latency->mem_freq)
1927                         break;
1928         }
1929         if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1930                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1931                 return NULL;
1932         }
1933         return latency;
1934 }
1935
1936 static void igd_disable_cxsr(struct drm_device *dev)
1937 {
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         u32 reg;
1940
1941         /* deactivate cxsr */
1942         reg = I915_READ(DSPFW3);
1943         reg &= ~(IGD_SELF_REFRESH_EN);
1944         I915_WRITE(DSPFW3, reg);
1945         DRM_INFO("Big FIFO is disabled\n");
1946 }
1947
1948 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1949                             int pixel_size)
1950 {
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952         u32 reg;
1953         unsigned long wm;
1954         struct cxsr_latency *latency;
1955
1956         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1957                 dev_priv->mem_freq);
1958         if (!latency) {
1959                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1960                 igd_disable_cxsr(dev);
1961                 return;
1962         }
1963
1964         /* Display SR */
1965         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1966                                 latency->display_sr);
1967         reg = I915_READ(DSPFW1);
1968         reg &= 0x7fffff;
1969         reg |= wm << 23;
1970         I915_WRITE(DSPFW1, reg);
1971         DRM_DEBUG("DSPFW1 register is %x\n", reg);
1972
1973         /* cursor SR */
1974         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1975                                 latency->cursor_sr);
1976         reg = I915_READ(DSPFW3);
1977         reg &= ~(0x3f << 24);
1978         reg |= (wm & 0x3f) << 24;
1979         I915_WRITE(DSPFW3, reg);
1980
1981         /* Display HPLL off SR */
1982         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1983                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1984         reg = I915_READ(DSPFW3);
1985         reg &= 0xfffffe00;
1986         reg |= wm & 0x1ff;
1987         I915_WRITE(DSPFW3, reg);
1988
1989         /* cursor HPLL off SR */
1990         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1991                                 latency->cursor_hpll_disable);
1992         reg = I915_READ(DSPFW3);
1993         reg &= ~(0x3f << 16);
1994         reg |= (wm & 0x3f) << 16;
1995         I915_WRITE(DSPFW3, reg);
1996         DRM_DEBUG("DSPFW3 register is %x\n", reg);
1997
1998         /* activate cxsr */
1999         reg = I915_READ(DSPFW3);
2000         reg |= IGD_SELF_REFRESH_EN;
2001         I915_WRITE(DSPFW3, reg);
2002
2003         DRM_INFO("Big FIFO is enabled\n");
2004
2005         return;
2006 }
2007
2008 /*
2009  * Latency for FIFO fetches is dependent on several factors:
2010  *   - memory configuration (speed, channels)
2011  *   - chipset
2012  *   - current MCH state
2013  * It can be fairly high in some situations, so here we assume a fairly
2014  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2015  * set this value too high, the FIFO will fetch frequently to stay full)
2016  * and power consumption (set it too low to save power and we might see
2017  * FIFO underruns and display "flicker").
2018  *
2019  * A value of 5us seems to be a good balance; safe for very low end
2020  * platforms but not overly aggressive on lower latency configs.
2021  */
2022 const static int latency_ns = 5000;
2023
2024 static int intel_get_fifo_size(struct drm_device *dev, int plane)
2025 {
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027         uint32_t dsparb = I915_READ(DSPARB);
2028         int size;
2029
2030         if (IS_I9XX(dev)) {
2031                 if (plane == 0)
2032                         size = dsparb & 0x7f;
2033                 else
2034                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2035                                 (dsparb & 0x7f);
2036         } else if (IS_I85X(dev)) {
2037                 if (plane == 0)
2038                         size = dsparb & 0x1ff;
2039                 else
2040                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2041                                 (dsparb & 0x1ff);
2042                 size >>= 1; /* Convert to cachelines */
2043         } else if (IS_845G(dev)) {
2044                 size = dsparb & 0x7f;
2045                 size >>= 2; /* Convert to cachelines */
2046         } else {
2047                 size = dsparb & 0x7f;
2048                 size >>= 1; /* Convert to cachelines */
2049         }
2050
2051         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2052                   size);
2053
2054         return size;
2055 }
2056
2057 static void i965_update_wm(struct drm_device *dev)
2058 {
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060
2061         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2062
2063         /* 965 has limitations... */
2064         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2065         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2066 }
2067
2068 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2069                            int planeb_clock, int sr_hdisplay, int pixel_size)
2070 {
2071         struct drm_i915_private *dev_priv = dev->dev_private;
2072         uint32_t fwater_lo;
2073         uint32_t fwater_hi;
2074         int total_size, cacheline_size, cwm, srwm = 1;
2075         int planea_wm, planeb_wm;
2076         struct intel_watermark_params planea_params, planeb_params;
2077         unsigned long line_time_us;
2078         int sr_clock, sr_entries = 0;
2079
2080         /* Create copies of the base settings for each pipe */
2081         if (IS_I965GM(dev) || IS_I945GM(dev))
2082                 planea_params = planeb_params = i945_wm_info;
2083         else if (IS_I9XX(dev))
2084                 planea_params = planeb_params = i915_wm_info;
2085         else
2086                 planea_params = planeb_params = i855_wm_info;
2087
2088         /* Grab a couple of global values before we overwrite them */
2089         total_size = planea_params.fifo_size;
2090         cacheline_size = planea_params.cacheline_size;
2091
2092         /* Update per-plane FIFO sizes */
2093         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
2094         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
2095
2096         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2097                                        pixel_size, latency_ns);
2098         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2099                                        pixel_size, latency_ns);
2100         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2101
2102         /*
2103          * Overlay gets an aggressive default since video jitter is bad.
2104          */
2105         cwm = 2;
2106
2107         /* Calc sr entries for one plane configs */
2108         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2109                 /* self-refresh has much higher latency */
2110                 const static int sr_latency_ns = 6000;
2111
2112                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2113                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2114
2115                 /* Use ns/us then divide to preserve precision */
2116                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2117                               pixel_size * sr_hdisplay) / 1000;
2118                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2119                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2120                 srwm = total_size - sr_entries;
2121                 if (srwm < 0)
2122                         srwm = 1;
2123                 if (IS_I9XX(dev))
2124                         I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
2125         }
2126
2127         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2128                   planea_wm, planeb_wm, cwm, srwm);
2129
2130         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2131         fwater_hi = (cwm & 0x1f);
2132
2133         /* Set request length to 8 cachelines per fetch */
2134         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2135         fwater_hi = fwater_hi | (1 << 8);
2136
2137         I915_WRITE(FW_BLC, fwater_lo);
2138         I915_WRITE(FW_BLC2, fwater_hi);
2139 }
2140
2141 static void i830_update_wm(struct drm_device *dev, int planea_clock,
2142                            int pixel_size)
2143 {
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2146         int planea_wm;
2147
2148         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2149
2150         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2151                                        pixel_size, latency_ns);
2152         fwater_lo |= (3<<8) | planea_wm;
2153
2154         DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
2155
2156         I915_WRITE(FW_BLC, fwater_lo);
2157 }
2158
2159 /**
2160  * intel_update_watermarks - update FIFO watermark values based on current modes
2161  *
2162  * Calculate watermark values for the various WM regs based on current mode
2163  * and plane configuration.
2164  *
2165  * There are several cases to deal with here:
2166  *   - normal (i.e. non-self-refresh)
2167  *   - self-refresh (SR) mode
2168  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2169  *   - lines are small relative to FIFO size (buffer can hold more than 2
2170  *     lines), so need to account for TLB latency
2171  *
2172  *   The normal calculation is:
2173  *     watermark = dotclock * bytes per pixel * latency
2174  *   where latency is platform & configuration dependent (we assume pessimal
2175  *   values here).
2176  *
2177  *   The SR calculation is:
2178  *     watermark = (trunc(latency/line time)+1) * surface width *
2179  *       bytes per pixel
2180  *   where
2181  *     line time = htotal / dotclock
2182  *   and latency is assumed to be high, as above.
2183  *
2184  * The final value programmed to the register should always be rounded up,
2185  * and include an extra 2 entries to account for clock crossings.
2186  *
2187  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2188  * to set the non-SR watermarks to 8.
2189   */
2190 static void intel_update_watermarks(struct drm_device *dev)
2191 {
2192         struct drm_crtc *crtc;
2193         struct intel_crtc *intel_crtc;
2194         int sr_hdisplay = 0;
2195         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2196         int enabled = 0, pixel_size = 0;
2197
2198         if (DSPARB_HWCONTROL(dev))
2199                 return;
2200
2201         /* Get the clock config from both planes */
2202         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2203                 intel_crtc = to_intel_crtc(crtc);
2204                 if (crtc->enabled) {
2205                         enabled++;
2206                         if (intel_crtc->plane == 0) {
2207                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2208                                           intel_crtc->pipe, crtc->mode.clock);
2209                                 planea_clock = crtc->mode.clock;
2210                         } else {
2211                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2212                                           intel_crtc->pipe, crtc->mode.clock);
2213                                 planeb_clock = crtc->mode.clock;
2214                         }
2215                         sr_hdisplay = crtc->mode.hdisplay;
2216                         sr_clock = crtc->mode.clock;
2217                         if (crtc->fb)
2218                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2219                         else
2220                                 pixel_size = 4; /* by default */
2221                 }
2222         }
2223
2224         if (enabled <= 0)
2225                 return;
2226
2227         /* Single plane configs can enable self refresh */
2228         if (enabled == 1 && IS_IGD(dev))
2229                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2230         else if (IS_IGD(dev))
2231                 igd_disable_cxsr(dev);
2232
2233         if (IS_I965G(dev))
2234                 i965_update_wm(dev);
2235         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2236                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2237                                pixel_size);
2238         else
2239                 i830_update_wm(dev, planea_clock, pixel_size);
2240 }
2241
2242 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2243                                struct drm_display_mode *mode,
2244                                struct drm_display_mode *adjusted_mode,
2245                                int x, int y,
2246                                struct drm_framebuffer *old_fb)
2247 {
2248         struct drm_device *dev = crtc->dev;
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251         int pipe = intel_crtc->pipe;
2252         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2253         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2254         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2255         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2256         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2257         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2258         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2259         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2260         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2261         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2262         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2263         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2264         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2265         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2266         int refclk, num_outputs = 0;
2267         intel_clock_t clock;
2268         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2269         bool ok, is_sdvo = false, is_dvo = false;
2270         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2271         bool is_edp = false;
2272         struct drm_mode_config *mode_config = &dev->mode_config;
2273         struct drm_connector *connector;
2274         const intel_limit_t *limit;
2275         int ret;
2276         struct fdi_m_n m_n = {0};
2277         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2278         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2279         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2280         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2281         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2282         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2283         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2284         int lvds_reg = LVDS;
2285         u32 temp;
2286         int sdvo_pixel_multiply;
2287         int target_clock;
2288
2289         drm_vblank_pre_modeset(dev, pipe);
2290
2291         list_for_each_entry(connector, &mode_config->connector_list, head) {
2292                 struct intel_output *intel_output = to_intel_output(connector);
2293
2294                 if (!connector->encoder || connector->encoder->crtc != crtc)
2295                         continue;
2296
2297                 switch (intel_output->type) {
2298                 case INTEL_OUTPUT_LVDS:
2299                         is_lvds = true;
2300                         break;
2301                 case INTEL_OUTPUT_SDVO:
2302                 case INTEL_OUTPUT_HDMI:
2303                         is_sdvo = true;
2304                         if (intel_output->needs_tv_clock)
2305                                 is_tv = true;
2306                         break;
2307                 case INTEL_OUTPUT_DVO:
2308                         is_dvo = true;
2309                         break;
2310                 case INTEL_OUTPUT_TVOUT:
2311                         is_tv = true;
2312                         break;
2313                 case INTEL_OUTPUT_ANALOG:
2314                         is_crt = true;
2315                         break;
2316                 case INTEL_OUTPUT_DISPLAYPORT:
2317                         is_dp = true;
2318                         break;
2319                 case INTEL_OUTPUT_EDP:
2320                         is_edp = true;
2321                         break;
2322                 }
2323
2324                 num_outputs++;
2325         }
2326
2327         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2328                 refclk = dev_priv->lvds_ssc_freq * 1000;
2329                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2330         } else if (IS_I9XX(dev)) {
2331                 refclk = 96000;
2332                 if (IS_IGDNG(dev))
2333                         refclk = 120000; /* 120Mhz refclk */
2334         } else {
2335                 refclk = 48000;
2336         }
2337
2338
2339         /*
2340          * Returns a set of divisors for the desired target clock with the given
2341          * refclk, or FALSE.  The returned values represent the clock equation:
2342          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2343          */
2344         limit = intel_limit(crtc);
2345         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2346         if (!ok) {
2347                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2348                 drm_vblank_post_modeset(dev, pipe);
2349                 return -EINVAL;
2350         }
2351
2352         /* SDVO TV has fixed PLL values depend on its clock range,
2353            this mirrors vbios setting. */
2354         if (is_sdvo && is_tv) {
2355                 if (adjusted_mode->clock >= 100000
2356                                 && adjusted_mode->clock < 140500) {
2357                         clock.p1 = 2;
2358                         clock.p2 = 10;
2359                         clock.n = 3;
2360                         clock.m1 = 16;
2361                         clock.m2 = 8;
2362                 } else if (adjusted_mode->clock >= 140500
2363                                 && adjusted_mode->clock <= 200000) {
2364                         clock.p1 = 1;
2365                         clock.p2 = 10;
2366                         clock.n = 6;
2367                         clock.m1 = 12;
2368                         clock.m2 = 8;
2369                 }
2370         }
2371
2372         /* FDI link */
2373         if (IS_IGDNG(dev)) {
2374                 int lane, link_bw;
2375                 /* eDP doesn't require FDI link, so just set DP M/N
2376                    according to current link config */
2377                 if (is_edp) {
2378                         struct drm_connector *edp;
2379                         target_clock = mode->clock;
2380                         edp = intel_pipe_get_output(crtc);
2381                         intel_edp_link_config(to_intel_output(edp),
2382                                         &lane, &link_bw);
2383                 } else {
2384                         /* DP over FDI requires target mode clock
2385                            instead of link clock */
2386                         if (is_dp)
2387                                 target_clock = mode->clock;
2388                         else
2389                                 target_clock = adjusted_mode->clock;
2390                         lane = 4;
2391                         link_bw = 270000;
2392                 }
2393                 igdng_compute_m_n(3, lane, target_clock,
2394                                   link_bw, &m_n);
2395         }
2396
2397         if (IS_IGD(dev))
2398                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2399         else
2400                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2401
2402         if (!IS_IGDNG(dev))
2403                 dpll = DPLL_VGA_MODE_DIS;
2404
2405         if (IS_I9XX(dev)) {
2406                 if (is_lvds)
2407                         dpll |= DPLLB_MODE_LVDS;
2408                 else
2409                         dpll |= DPLLB_MODE_DAC_SERIAL;
2410                 if (is_sdvo) {
2411                         dpll |= DPLL_DVO_HIGH_SPEED;
2412                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2413                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2414                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2415                         else if (IS_IGDNG(dev))
2416                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2417                 }
2418                 if (is_dp)
2419                         dpll |= DPLL_DVO_HIGH_SPEED;
2420
2421                 /* compute bitmask from p1 value */
2422                 if (IS_IGD(dev))
2423                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2424                 else {
2425                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2426                         /* also FPA1 */
2427                         if (IS_IGDNG(dev))
2428                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2429                 }
2430                 switch (clock.p2) {
2431                 case 5:
2432                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2433                         break;
2434                 case 7:
2435                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2436                         break;
2437                 case 10:
2438                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2439                         break;
2440                 case 14:
2441                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2442                         break;
2443                 }
2444                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2445                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2446         } else {
2447                 if (is_lvds) {
2448                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2449                 } else {
2450                         if (clock.p1 == 2)
2451                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2452                         else
2453                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2454                         if (clock.p2 == 4)
2455                                 dpll |= PLL_P2_DIVIDE_BY_4;
2456                 }
2457         }
2458
2459         if (is_sdvo && is_tv)
2460                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2461         else if (is_tv)
2462                 /* XXX: just matching BIOS for now */
2463                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2464                 dpll |= 3;
2465         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2466                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2467         else
2468                 dpll |= PLL_REF_INPUT_DREFCLK;
2469
2470         /* setup pipeconf */
2471         pipeconf = I915_READ(pipeconf_reg);
2472
2473         /* Set up the display plane register */
2474         dspcntr = DISPPLANE_GAMMA_ENABLE;
2475
2476         /* IGDNG's plane is forced to pipe, bit 24 is to
2477            enable color space conversion */
2478         if (!IS_IGDNG(dev)) {
2479                 if (pipe == 0)
2480                         dspcntr |= DISPPLANE_SEL_PIPE_A;
2481                 else
2482                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2483         }
2484
2485         if (pipe == 0 && !IS_I965G(dev)) {
2486                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2487                  * core speed.
2488                  *
2489                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2490                  * pipe == 0 check?
2491                  */
2492                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2493                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2494                 else
2495                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2496         }
2497
2498         dspcntr |= DISPLAY_PLANE_ENABLE;
2499         pipeconf |= PIPEACONF_ENABLE;
2500         dpll |= DPLL_VCO_ENABLE;
2501
2502
2503         /* Disable the panel fitter if it was on our pipe */
2504         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2505                 I915_WRITE(PFIT_CONTROL, 0);
2506
2507         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2508         drm_mode_debug_printmodeline(mode);
2509
2510         /* assign to IGDNG registers */
2511         if (IS_IGDNG(dev)) {
2512                 fp_reg = pch_fp_reg;
2513                 dpll_reg = pch_dpll_reg;
2514         }
2515
2516         if (is_edp) {
2517                 igdng_disable_pll_edp(crtc);
2518         } else if ((dpll & DPLL_VCO_ENABLE)) {
2519                 I915_WRITE(fp_reg, fp);
2520                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2521                 I915_READ(dpll_reg);
2522                 udelay(150);
2523         }
2524
2525         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2526          * This is an exception to the general rule that mode_set doesn't turn
2527          * things on.
2528          */
2529         if (is_lvds) {
2530                 u32 lvds;
2531
2532                 if (IS_IGDNG(dev))
2533                         lvds_reg = PCH_LVDS;
2534
2535                 lvds = I915_READ(lvds_reg);
2536                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2537                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2538                  * set the DPLLs for dual-channel mode or not.
2539                  */
2540                 if (clock.p2 == 7)
2541                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2542                 else
2543                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2544
2545                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2546                  * appropriately here, but we need to look more thoroughly into how
2547                  * panels behave in the two modes.
2548                  */
2549
2550                 I915_WRITE(lvds_reg, lvds);
2551                 I915_READ(lvds_reg);
2552         }
2553         if (is_dp)
2554                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2555
2556         if (!is_edp) {
2557                 I915_WRITE(fp_reg, fp);
2558                 I915_WRITE(dpll_reg, dpll);
2559                 I915_READ(dpll_reg);
2560                 /* Wait for the clocks to stabilize. */
2561                 udelay(150);
2562
2563                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2564                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2565                         I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2566                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2567                 } else {
2568                         /* write it again -- the BIOS does, after all */
2569                         I915_WRITE(dpll_reg, dpll);
2570                 }
2571                 I915_READ(dpll_reg);
2572                 /* Wait for the clocks to stabilize. */
2573                 udelay(150);
2574         }
2575
2576         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2577                    ((adjusted_mode->crtc_htotal - 1) << 16));
2578         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2579                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2580         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2581                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2582         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2583                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2584         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2585                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2586         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2587                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2588         /* pipesrc and dspsize control the size that is scaled from, which should
2589          * always be the user's requested size.
2590          */
2591         if (!IS_IGDNG(dev)) {
2592                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2593                                 (mode->hdisplay - 1));
2594                 I915_WRITE(dsppos_reg, 0);
2595         }
2596         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2597
2598         if (IS_IGDNG(dev)) {
2599                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2600                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2601                 I915_WRITE(link_m1_reg, m_n.link_m);
2602                 I915_WRITE(link_n1_reg, m_n.link_n);
2603
2604                 if (is_edp) {
2605                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
2606                 } else {
2607                         /* enable FDI RX PLL too */
2608                         temp = I915_READ(fdi_rx_reg);
2609                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2610                         udelay(200);
2611                 }
2612         }
2613
2614         I915_WRITE(pipeconf_reg, pipeconf);
2615         I915_READ(pipeconf_reg);
2616
2617         intel_wait_for_vblank(dev);
2618
2619         I915_WRITE(dspcntr_reg, dspcntr);
2620
2621         /* Flush the plane changes */
2622         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2623
2624         intel_update_watermarks(dev);
2625
2626         drm_vblank_post_modeset(dev, pipe);
2627
2628         return ret;
2629 }
2630
2631 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2632 void intel_crtc_load_lut(struct drm_crtc *crtc)
2633 {
2634         struct drm_device *dev = crtc->dev;
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2638         int i;
2639
2640         /* The clocks have to be on to load the palette. */
2641         if (!crtc->enabled)
2642                 return;
2643
2644         /* use legacy palette for IGDNG */
2645         if (IS_IGDNG(dev))
2646                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2647                                                    LGC_PALETTE_B;
2648
2649         for (i = 0; i < 256; i++) {
2650                 I915_WRITE(palreg + 4 * i,
2651                            (intel_crtc->lut_r[i] << 16) |
2652                            (intel_crtc->lut_g[i] << 8) |
2653                            intel_crtc->lut_b[i]);
2654         }
2655 }
2656
2657 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2658                                  struct drm_file *file_priv,
2659                                  uint32_t handle,
2660                                  uint32_t width, uint32_t height)
2661 {
2662         struct drm_device *dev = crtc->dev;
2663         struct drm_i915_private *dev_priv = dev->dev_private;
2664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2665         struct drm_gem_object *bo;
2666         struct drm_i915_gem_object *obj_priv;
2667         int pipe = intel_crtc->pipe;
2668         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2669         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2670         uint32_t temp = I915_READ(control);
2671         size_t addr;
2672         int ret;
2673
2674         DRM_DEBUG("\n");
2675
2676         /* if we want to turn off the cursor ignore width and height */
2677         if (!handle) {
2678                 DRM_DEBUG("cursor off\n");
2679                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2680                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2681                         temp |= CURSOR_MODE_DISABLE;
2682                 } else {
2683                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2684                 }
2685                 addr = 0;
2686                 bo = NULL;
2687                 mutex_lock(&dev->struct_mutex);
2688                 goto finish;
2689         }
2690
2691         /* Currently we only support 64x64 cursors */
2692         if (width != 64 || height != 64) {
2693                 DRM_ERROR("we currently only support 64x64 cursors\n");
2694                 return -EINVAL;
2695         }
2696
2697         bo = drm_gem_object_lookup(dev, file_priv, handle);
2698         if (!bo)
2699                 return -ENOENT;
2700
2701         obj_priv = bo->driver_private;
2702
2703         if (bo->size < width * height * 4) {
2704                 DRM_ERROR("buffer is to small\n");
2705                 ret = -ENOMEM;
2706                 goto fail;
2707         }
2708
2709         /* we only need to pin inside GTT if cursor is non-phy */
2710         mutex_lock(&dev->struct_mutex);
2711         if (!dev_priv->cursor_needs_physical) {
2712                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2713                 if (ret) {
2714                         DRM_ERROR("failed to pin cursor bo\n");
2715                         goto fail_locked;
2716                 }
2717                 addr = obj_priv->gtt_offset;
2718         } else {
2719                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2720                 if (ret) {
2721                         DRM_ERROR("failed to attach phys object\n");
2722                         goto fail_locked;
2723                 }
2724                 addr = obj_priv->phys_obj->handle->busaddr;
2725         }
2726
2727         if (!IS_I9XX(dev))
2728                 I915_WRITE(CURSIZE, (height << 12) | width);
2729
2730         /* Hooray for CUR*CNTR differences */
2731         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2732                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2733                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2734                 temp |= (pipe << 28); /* Connect to correct pipe */
2735         } else {
2736                 temp &= ~(CURSOR_FORMAT_MASK);
2737                 temp |= CURSOR_ENABLE;
2738                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2739         }
2740
2741  finish:
2742         I915_WRITE(control, temp);
2743         I915_WRITE(base, addr);
2744
2745         if (intel_crtc->cursor_bo) {
2746                 if (dev_priv->cursor_needs_physical) {
2747                         if (intel_crtc->cursor_bo != bo)
2748                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2749                 } else
2750                         i915_gem_object_unpin(intel_crtc->cursor_bo);
2751                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2752         }
2753         mutex_unlock(&dev->struct_mutex);
2754
2755         intel_crtc->cursor_addr = addr;
2756         intel_crtc->cursor_bo = bo;
2757
2758         return 0;
2759 fail:
2760         mutex_lock(&dev->struct_mutex);
2761 fail_locked:
2762         drm_gem_object_unreference(bo);
2763         mutex_unlock(&dev->struct_mutex);
2764         return ret;
2765 }
2766
2767 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2768 {
2769         struct drm_device *dev = crtc->dev;
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772         int pipe = intel_crtc->pipe;
2773         uint32_t temp = 0;
2774         uint32_t adder;
2775
2776         if (x < 0) {
2777                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2778                 x = -x;
2779         }
2780         if (y < 0) {
2781                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2782                 y = -y;
2783         }
2784
2785         temp |= x << CURSOR_X_SHIFT;
2786         temp |= y << CURSOR_Y_SHIFT;
2787
2788         adder = intel_crtc->cursor_addr;
2789         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2790         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2791
2792         return 0;
2793 }
2794
2795 /** Sets the color ramps on behalf of RandR */
2796 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2797                                  u16 blue, int regno)
2798 {
2799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2800
2801         intel_crtc->lut_r[regno] = red >> 8;
2802         intel_crtc->lut_g[regno] = green >> 8;
2803         intel_crtc->lut_b[regno] = blue >> 8;
2804 }
2805
2806 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2807                                  u16 *blue, uint32_t size)
2808 {
2809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810         int i;
2811
2812         if (size != 256)
2813                 return;
2814
2815         for (i = 0; i < 256; i++) {
2816                 intel_crtc->lut_r[i] = red[i] >> 8;
2817                 intel_crtc->lut_g[i] = green[i] >> 8;
2818                 intel_crtc->lut_b[i] = blue[i] >> 8;
2819         }
2820
2821         intel_crtc_load_lut(crtc);
2822 }
2823
2824 /**
2825  * Get a pipe with a simple mode set on it for doing load-based monitor
2826  * detection.
2827  *
2828  * It will be up to the load-detect code to adjust the pipe as appropriate for
2829  * its requirements.  The pipe will be connected to no other outputs.
2830  *
2831  * Currently this code will only succeed if there is a pipe with no outputs
2832  * configured for it.  In the future, it could choose to temporarily disable
2833  * some outputs to free up a pipe for its use.
2834  *
2835  * \return crtc, or NULL if no pipes are available.
2836  */
2837
2838 /* VESA 640x480x72Hz mode to set on the pipe */
2839 static struct drm_display_mode load_detect_mode = {
2840         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2841                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2842 };
2843
2844 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2845                                             struct drm_display_mode *mode,
2846                                             int *dpms_mode)
2847 {
2848         struct intel_crtc *intel_crtc;
2849         struct drm_crtc *possible_crtc;
2850         struct drm_crtc *supported_crtc =NULL;
2851         struct drm_encoder *encoder = &intel_output->enc;
2852         struct drm_crtc *crtc = NULL;
2853         struct drm_device *dev = encoder->dev;
2854         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2855         struct drm_crtc_helper_funcs *crtc_funcs;
2856         int i = -1;
2857
2858         /*
2859          * Algorithm gets a little messy:
2860          *   - if the connector already has an assigned crtc, use it (but make
2861          *     sure it's on first)
2862          *   - try to find the first unused crtc that can drive this connector,
2863          *     and use that if we find one
2864          *   - if there are no unused crtcs available, try to use the first
2865          *     one we found that supports the connector
2866          */
2867
2868         /* See if we already have a CRTC for this connector */
2869         if (encoder->crtc) {
2870                 crtc = encoder->crtc;
2871                 /* Make sure the crtc and connector are running */
2872                 intel_crtc = to_intel_crtc(crtc);
2873                 *dpms_mode = intel_crtc->dpms_mode;
2874                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2875                         crtc_funcs = crtc->helper_private;
2876                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2877                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2878                 }
2879                 return crtc;
2880         }
2881
2882         /* Find an unused one (if possible) */
2883         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2884                 i++;
2885                 if (!(encoder->possible_crtcs & (1 << i)))
2886                         continue;
2887                 if (!possible_crtc->enabled) {
2888                         crtc = possible_crtc;
2889                         break;
2890                 }
2891                 if (!supported_crtc)
2892                         supported_crtc = possible_crtc;
2893         }
2894
2895         /*
2896          * If we didn't find an unused CRTC, don't use any.
2897          */
2898         if (!crtc) {
2899                 return NULL;
2900         }
2901
2902         encoder->crtc = crtc;
2903         intel_output->base.encoder = encoder;
2904         intel_output->load_detect_temp = true;
2905
2906         intel_crtc = to_intel_crtc(crtc);
2907         *dpms_mode = intel_crtc->dpms_mode;
2908
2909         if (!crtc->enabled) {
2910                 if (!mode)
2911                         mode = &load_detect_mode;
2912                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2913         } else {
2914                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2915                         crtc_funcs = crtc->helper_private;
2916                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2917                 }
2918
2919                 /* Add this connector to the crtc */
2920                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2921                 encoder_funcs->commit(encoder);
2922         }
2923         /* let the connector get through one full cycle before testing */
2924         intel_wait_for_vblank(dev);
2925
2926         return crtc;
2927 }
2928
2929 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2930 {
2931         struct drm_encoder *encoder = &intel_output->enc;
2932         struct drm_device *dev = encoder->dev;
2933         struct drm_crtc *crtc = encoder->crtc;
2934         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2935         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2936
2937         if (intel_output->load_detect_temp) {
2938                 encoder->crtc = NULL;
2939                 intel_output->base.encoder = NULL;
2940                 intel_output->load_detect_temp = false;
2941                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2942                 drm_helper_disable_unused_functions(dev);
2943         }
2944
2945         /* Switch crtc and output back off if necessary */
2946         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2947                 if (encoder->crtc == crtc)
2948                         encoder_funcs->dpms(encoder, dpms_mode);
2949                 crtc_funcs->dpms(crtc, dpms_mode);
2950         }
2951 }
2952
2953 /* Returns the clock of the currently programmed mode of the given pipe. */
2954 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2955 {
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2958         int pipe = intel_crtc->pipe;
2959         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2960         u32 fp;
2961         intel_clock_t clock;
2962
2963         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2964                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2965         else
2966                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2967
2968         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2969         if (IS_IGD(dev)) {
2970                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2971                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2972         } else {
2973                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2974                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2975         }
2976
2977         if (IS_I9XX(dev)) {
2978                 if (IS_IGD(dev))
2979                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2980                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2981                 else
2982                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2983                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2984
2985                 switch (dpll & DPLL_MODE_MASK) {
2986                 case DPLLB_MODE_DAC_SERIAL:
2987                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2988                                 5 : 10;
2989                         break;
2990                 case DPLLB_MODE_LVDS:
2991                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2992                                 7 : 14;
2993                         break;
2994                 default:
2995                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2996                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2997                         return 0;
2998                 }
2999
3000                 /* XXX: Handle the 100Mhz refclk */
3001                 intel_clock(dev, 96000, &clock);
3002         } else {
3003                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3004
3005                 if (is_lvds) {
3006                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3007                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3008                         clock.p2 = 14;
3009
3010                         if ((dpll & PLL_REF_INPUT_MASK) ==
3011                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3012                                 /* XXX: might not be 66MHz */
3013                                 intel_clock(dev, 66000, &clock);
3014                         } else
3015                                 intel_clock(dev, 48000, &clock);
3016                 } else {
3017                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3018                                 clock.p1 = 2;
3019                         else {
3020                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3021                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3022                         }
3023                         if (dpll & PLL_P2_DIVIDE_BY_4)
3024                                 clock.p2 = 4;
3025                         else
3026                                 clock.p2 = 2;
3027
3028                         intel_clock(dev, 48000, &clock);
3029                 }
3030         }
3031
3032         /* XXX: It would be nice to validate the clocks, but we can't reuse
3033          * i830PllIsValid() because it relies on the xf86_config connector
3034          * configuration being accurate, which it isn't necessarily.
3035          */
3036
3037         return clock.dot;
3038 }
3039
3040 /** Returns the currently programmed mode of the given pipe. */
3041 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3042                                              struct drm_crtc *crtc)
3043 {
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3046         int pipe = intel_crtc->pipe;
3047         struct drm_display_mode *mode;
3048         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3049         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3050         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3051         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3052
3053         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3054         if (!mode)
3055                 return NULL;
3056
3057         mode->clock = intel_crtc_clock_get(dev, crtc);
3058         mode->hdisplay = (htot & 0xffff) + 1;
3059         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3060         mode->hsync_start = (hsync & 0xffff) + 1;
3061         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3062         mode->vdisplay = (vtot & 0xffff) + 1;
3063         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3064         mode->vsync_start = (vsync & 0xffff) + 1;
3065         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3066
3067         drm_mode_set_name(mode);
3068         drm_mode_set_crtcinfo(mode, 0);
3069
3070         return mode;
3071 }
3072
3073 static void intel_crtc_destroy(struct drm_crtc *crtc)
3074 {
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076
3077         if (intel_crtc->mode_set.mode)
3078                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
3079         drm_crtc_cleanup(crtc);
3080         kfree(intel_crtc);
3081 }
3082
3083 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
3084         .dpms = intel_crtc_dpms,
3085         .mode_fixup = intel_crtc_mode_fixup,
3086         .mode_set = intel_crtc_mode_set,
3087         .mode_set_base = intel_pipe_set_base,
3088         .prepare = intel_crtc_prepare,
3089         .commit = intel_crtc_commit,
3090 };
3091
3092 static const struct drm_crtc_funcs intel_crtc_funcs = {
3093         .cursor_set = intel_crtc_cursor_set,
3094         .cursor_move = intel_crtc_cursor_move,
3095         .gamma_set = intel_crtc_gamma_set,
3096         .set_config = drm_crtc_helper_set_config,
3097         .destroy = intel_crtc_destroy,
3098 };
3099
3100
3101 static void intel_crtc_init(struct drm_device *dev, int pipe)
3102 {
3103         struct intel_crtc *intel_crtc;
3104         int i;
3105
3106         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
3107         if (intel_crtc == NULL)
3108                 return;
3109
3110         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
3111
3112         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
3113         intel_crtc->pipe = pipe;
3114         intel_crtc->plane = pipe;
3115         for (i = 0; i < 256; i++) {
3116                 intel_crtc->lut_r[i] = i;
3117                 intel_crtc->lut_g[i] = i;
3118                 intel_crtc->lut_b[i] = i;
3119         }
3120
3121         intel_crtc->cursor_addr = 0;
3122         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
3123         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
3124
3125         intel_crtc->mode_set.crtc = &intel_crtc->base;
3126         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
3127         intel_crtc->mode_set.num_connectors = 0;
3128
3129         if (i915_fbpercrtc) {
3130
3131
3132
3133         }
3134 }
3135
3136 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
3137                                 struct drm_file *file_priv)
3138 {
3139         drm_i915_private_t *dev_priv = dev->dev_private;
3140         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
3141         struct drm_crtc *crtc = NULL;
3142         int pipe = -1;
3143
3144         if (!dev_priv) {
3145                 DRM_ERROR("called with no initialization\n");
3146                 return -EINVAL;
3147         }
3148
3149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
3152                         pipe = intel_crtc->pipe;
3153                         break;
3154                 }
3155         }
3156
3157         if (pipe == -1) {
3158                 DRM_ERROR("no such CRTC id\n");
3159                 return -EINVAL;
3160         }
3161
3162         pipe_from_crtc_id->pipe = pipe;
3163
3164        return 0;
3165 }
3166
3167 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3168 {
3169         struct drm_crtc *crtc = NULL;
3170
3171         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3172                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173                 if (intel_crtc->pipe == pipe)
3174                         break;
3175         }
3176         return crtc;
3177 }
3178
3179 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3180 {
3181         int index_mask = 0;
3182         struct drm_connector *connector;
3183         int entry = 0;
3184
3185         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3186                 struct intel_output *intel_output = to_intel_output(connector);
3187                 if (type_mask & intel_output->clone_mask)
3188                         index_mask |= (1 << entry);
3189                 entry++;
3190         }
3191         return index_mask;
3192 }
3193
3194
3195 static void intel_setup_outputs(struct drm_device *dev)
3196 {
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         struct drm_connector *connector;
3199
3200         intel_crt_init(dev);
3201
3202         /* Set up integrated LVDS */
3203         if (IS_MOBILE(dev) && !IS_I830(dev))
3204                 intel_lvds_init(dev);
3205
3206         if (IS_IGDNG(dev)) {
3207                 int found;
3208
3209                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3210                         intel_dp_init(dev, DP_A);
3211
3212                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3213                         /* check SDVOB */
3214                         /* found = intel_sdvo_init(dev, HDMIB); */
3215                         found = 0;
3216                         if (!found)
3217                                 intel_hdmi_init(dev, HDMIB);
3218                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3219                                 intel_dp_init(dev, PCH_DP_B);
3220                 }
3221
3222                 if (I915_READ(HDMIC) & PORT_DETECTED)
3223                         intel_hdmi_init(dev, HDMIC);
3224
3225                 if (I915_READ(HDMID) & PORT_DETECTED)
3226                         intel_hdmi_init(dev, HDMID);
3227
3228                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3229                         intel_dp_init(dev, PCH_DP_C);
3230
3231                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3232                         intel_dp_init(dev, PCH_DP_D);
3233
3234         } else if (IS_I9XX(dev)) {
3235                 bool found = false;
3236
3237                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3238                         found = intel_sdvo_init(dev, SDVOB);
3239                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3240                                 intel_hdmi_init(dev, SDVOB);
3241
3242                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3243                                 intel_dp_init(dev, DP_B);
3244                 }
3245
3246                 /* Before G4X SDVOC doesn't have its own detect register */
3247
3248                 if (I915_READ(SDVOB) & SDVO_DETECTED)
3249                         found = intel_sdvo_init(dev, SDVOC);
3250
3251                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
3252
3253                         if (SUPPORTS_INTEGRATED_HDMI(dev))
3254                                 intel_hdmi_init(dev, SDVOC);
3255                         if (SUPPORTS_INTEGRATED_DP(dev))
3256                                 intel_dp_init(dev, DP_C);
3257                 }
3258
3259                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3260                         intel_dp_init(dev, DP_D);
3261         } else
3262                 intel_dvo_init(dev);
3263
3264         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3265                 intel_tv_init(dev);
3266
3267         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3268                 struct intel_output *intel_output = to_intel_output(connector);
3269                 struct drm_encoder *encoder = &intel_output->enc;
3270
3271                 encoder->possible_crtcs = intel_output->crtc_mask;
3272                 encoder->possible_clones = intel_connector_clones(dev,
3273                                                 intel_output->clone_mask);
3274         }
3275 }
3276
3277 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3278 {
3279         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3280         struct drm_device *dev = fb->dev;
3281
3282         if (fb->fbdev)
3283                 intelfb_remove(dev, fb);
3284
3285         drm_framebuffer_cleanup(fb);
3286         mutex_lock(&dev->struct_mutex);
3287         drm_gem_object_unreference(intel_fb->obj);
3288         mutex_unlock(&dev->struct_mutex);
3289
3290         kfree(intel_fb);
3291 }
3292
3293 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3294                                                 struct drm_file *file_priv,
3295                                                 unsigned int *handle)
3296 {
3297         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3298         struct drm_gem_object *object = intel_fb->obj;
3299
3300         return drm_gem_handle_create(file_priv, object, handle);
3301 }
3302
3303 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3304         .destroy = intel_user_framebuffer_destroy,
3305         .create_handle = intel_user_framebuffer_create_handle,
3306 };
3307
3308 int intel_framebuffer_create(struct drm_device *dev,
3309                              struct drm_mode_fb_cmd *mode_cmd,
3310                              struct drm_framebuffer **fb,
3311                              struct drm_gem_object *obj)
3312 {
3313         struct intel_framebuffer *intel_fb;
3314         int ret;
3315
3316         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3317         if (!intel_fb)
3318                 return -ENOMEM;
3319
3320         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3321         if (ret) {
3322                 DRM_ERROR("framebuffer init failed %d\n", ret);
3323                 return ret;
3324         }
3325
3326         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3327
3328         intel_fb->obj = obj;
3329
3330         *fb = &intel_fb->base;
3331
3332         return 0;
3333 }
3334
3335
3336 static struct drm_framebuffer *
3337 intel_user_framebuffer_create(struct drm_device *dev,
3338                               struct drm_file *filp,
3339                               struct drm_mode_fb_cmd *mode_cmd)
3340 {
3341         struct drm_gem_object *obj;
3342         struct drm_framebuffer *fb;
3343         int ret;
3344
3345         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3346         if (!obj)
3347                 return NULL;
3348
3349         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3350         if (ret) {
3351                 mutex_lock(&dev->struct_mutex);
3352                 drm_gem_object_unreference(obj);
3353                 mutex_unlock(&dev->struct_mutex);
3354                 return NULL;
3355         }
3356
3357         return fb;
3358 }
3359
3360 static const struct drm_mode_config_funcs intel_mode_funcs = {
3361         .fb_create = intel_user_framebuffer_create,
3362         .fb_changed = intelfb_probe,
3363 };
3364
3365 void intel_modeset_init(struct drm_device *dev)
3366 {
3367         int num_pipe;
3368         int i;
3369
3370         drm_mode_config_init(dev);
3371
3372         dev->mode_config.min_width = 0;
3373         dev->mode_config.min_height = 0;
3374
3375         dev->mode_config.funcs = (void *)&intel_mode_funcs;
3376
3377         if (IS_I965G(dev)) {
3378                 dev->mode_config.max_width = 8192;
3379                 dev->mode_config.max_height = 8192;
3380         } else if (IS_I9XX(dev)) {
3381                 dev->mode_config.max_width = 4096;
3382                 dev->mode_config.max_height = 4096;
3383         } else {
3384                 dev->mode_config.max_width = 2048;
3385                 dev->mode_config.max_height = 2048;
3386         }
3387
3388         /* set memory base */
3389         if (IS_I9XX(dev))
3390                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3391         else
3392                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3393
3394         if (IS_MOBILE(dev) || IS_I9XX(dev))
3395                 num_pipe = 2;
3396         else
3397                 num_pipe = 1;
3398         DRM_DEBUG("%d display pipe%s available.\n",
3399                   num_pipe, num_pipe > 1 ? "s" : "");
3400
3401         for (i = 0; i < num_pipe; i++) {
3402                 intel_crtc_init(dev, i);
3403         }
3404
3405         intel_setup_outputs(dev);
3406 }
3407
3408 void intel_modeset_cleanup(struct drm_device *dev)
3409 {
3410         drm_mode_config_cleanup(dev);
3411 }
3412
3413
3414 /* current intel driver doesn't take advantage of encoders
3415    always give back the encoder for the connector
3416 */
3417 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3418 {
3419         struct intel_output *intel_output = to_intel_output(connector);
3420
3421         return &intel_output->enc;
3422 }