drm: radeon: fix error value sign
[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50     /* given values */
51     int n;
52     int m1, m2;
53     int p1, p2;
54     /* derived values */
55     int dot;
56     int vco;
57     int m;
58     int p;
59 } intel_clock_t;
60
61 typedef struct {
62     int min, max;
63 } intel_range_t;
64
65 typedef struct {
66     int dot_limit;
67     int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM                  2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
74     intel_p2_t      p2;
75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76                       int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN              25000
80 #define I8XX_DOT_MAX             350000
81 #define I8XX_VCO_MIN             930000
82 #define I8XX_VCO_MAX            1400000
83 #define I8XX_N_MIN                    3
84 #define I8XX_N_MAX                   16
85 #define I8XX_M_MIN                   96
86 #define I8XX_M_MAX                  140
87 #define I8XX_M1_MIN                  18
88 #define I8XX_M1_MAX                  26
89 #define I8XX_M2_MIN                   6
90 #define I8XX_M2_MAX                  16
91 #define I8XX_P_MIN                    4
92 #define I8XX_P_MAX                  128
93 #define I8XX_P1_MIN                   2
94 #define I8XX_P1_MAX                  33
95 #define I8XX_P1_LVDS_MIN              1
96 #define I8XX_P1_LVDS_MAX              6
97 #define I8XX_P2_SLOW                  4
98 #define I8XX_P2_FAST                  2
99 #define I8XX_P2_LVDS_SLOW             14
100 #define I8XX_P2_LVDS_FAST             7
101 #define I8XX_P2_SLOW_LIMIT       165000
102
103 #define I9XX_DOT_MIN              20000
104 #define I9XX_DOT_MAX             400000
105 #define I9XX_VCO_MIN            1400000
106 #define I9XX_VCO_MAX            2800000
107 #define PINEVIEW_VCO_MIN                1700000
108 #define PINEVIEW_VCO_MAX                3500000
109 #define I9XX_N_MIN                    1
110 #define I9XX_N_MAX                    6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN                3
113 #define PINEVIEW_N_MAX                6
114 #define I9XX_M_MIN                   70
115 #define I9XX_M_MAX                  120
116 #define PINEVIEW_M_MIN                2
117 #define PINEVIEW_M_MAX              256
118 #define I9XX_M1_MIN                  10
119 #define I9XX_M1_MAX                  22
120 #define I9XX_M2_MIN                   5
121 #define I9XX_M2_MAX                   9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN               0
124 #define PINEVIEW_M1_MAX               0
125 #define PINEVIEW_M2_MIN               0
126 #define PINEVIEW_M2_MAX               254
127 #define I9XX_P_SDVO_DAC_MIN           5
128 #define I9XX_P_SDVO_DAC_MAX          80
129 #define I9XX_P_LVDS_MIN               7
130 #define I9XX_P_LVDS_MAX              98
131 #define PINEVIEW_P_LVDS_MIN                   7
132 #define PINEVIEW_P_LVDS_MAX                  112
133 #define I9XX_P1_MIN                   1
134 #define I9XX_P1_MAX                   8
135 #define I9XX_P2_SDVO_DAC_SLOW                10
136 #define I9XX_P2_SDVO_DAC_FAST                 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
138 #define I9XX_P2_LVDS_SLOW                    14
139 #define I9XX_P2_LVDS_FAST                     7
140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN           25000
144 #define G4X_DOT_SDVO_MAX           270000
145 #define G4X_VCO_MIN                1750000
146 #define G4X_VCO_MAX                3500000
147 #define G4X_N_SDVO_MIN             1
148 #define G4X_N_SDVO_MAX             4
149 #define G4X_M_SDVO_MIN             104
150 #define G4X_M_SDVO_MAX             138
151 #define G4X_M1_SDVO_MIN            17
152 #define G4X_M1_SDVO_MAX            23
153 #define G4X_M2_SDVO_MIN            5
154 #define G4X_M2_SDVO_MAX            11
155 #define G4X_P_SDVO_MIN             10
156 #define G4X_P_SDVO_MAX             30
157 #define G4X_P1_SDVO_MIN            1
158 #define G4X_P1_SDVO_MAX            3
159 #define G4X_P2_SDVO_SLOW           10
160 #define G4X_P2_SDVO_FAST           10
161 #define G4X_P2_SDVO_LIMIT          270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN           22000
165 #define G4X_DOT_HDMI_DAC_MAX           400000
166 #define G4X_N_HDMI_DAC_MIN             1
167 #define G4X_N_HDMI_DAC_MAX             4
168 #define G4X_M_HDMI_DAC_MIN             104
169 #define G4X_M_HDMI_DAC_MAX             138
170 #define G4X_M1_HDMI_DAC_MIN            16
171 #define G4X_M1_HDMI_DAC_MAX            23
172 #define G4X_M2_HDMI_DAC_MIN            5
173 #define G4X_M2_HDMI_DAC_MAX            11
174 #define G4X_P_HDMI_DAC_MIN             5
175 #define G4X_P_HDMI_DAC_MAX             80
176 #define G4X_P1_HDMI_DAC_MIN            1
177 #define G4X_P1_HDMI_DAC_MAX            8
178 #define G4X_P2_HDMI_DAC_SLOW           10
179 #define G4X_P2_HDMI_DAC_FAST           5
180 #define G4X_P2_HDMI_DAC_LIMIT          165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
223 #define G4X_N_DISPLAY_PORT_MIN             1
224 #define G4X_N_DISPLAY_PORT_MAX             2
225 #define G4X_M_DISPLAY_PORT_MIN             97
226 #define G4X_M_DISPLAY_PORT_MAX             108
227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
231 #define G4X_P_DISPLAY_PORT_MIN             10
232 #define G4X_P_DISPLAY_PORT_MAX             20
233 #define G4X_P1_DISPLAY_PORT_MIN            1
234 #define G4X_P1_DISPLAY_PORT_MAX            2
235 #define G4X_P2_DISPLAY_PORT_SLOW           10
236 #define G4X_P2_DISPLAY_PORT_FAST           10
237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241    N/M1/M2, so here the range value for them is (actual_value-2).
242  */
243 #define IRONLAKE_DOT_MIN         25000
244 #define IRONLAKE_DOT_MAX         350000
245 #define IRONLAKE_VCO_MIN         1760000
246 #define IRONLAKE_VCO_MAX         3510000
247 #define IRONLAKE_M1_MIN          12
248 #define IRONLAKE_M1_MAX          22
249 #define IRONLAKE_M2_MIN          5
250 #define IRONLAKE_M2_MAX          9
251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN      1
257 #define IRONLAKE_DAC_N_MAX      5
258 #define IRONLAKE_DAC_M_MIN      79
259 #define IRONLAKE_DAC_M_MAX      127
260 #define IRONLAKE_DAC_P_MIN      5
261 #define IRONLAKE_DAC_P_MAX      80
262 #define IRONLAKE_DAC_P1_MIN     1
263 #define IRONLAKE_DAC_P1_MAX     8
264 #define IRONLAKE_DAC_P2_SLOW    10
265 #define IRONLAKE_DAC_P2_FAST    5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN   1
269 #define IRONLAKE_LVDS_S_N_MAX   3
270 #define IRONLAKE_LVDS_S_M_MIN   79
271 #define IRONLAKE_LVDS_S_M_MAX   118
272 #define IRONLAKE_LVDS_S_P_MIN   28
273 #define IRONLAKE_LVDS_S_P_MAX   112
274 #define IRONLAKE_LVDS_S_P1_MIN  2
275 #define IRONLAKE_LVDS_S_P1_MAX  8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN   1
281 #define IRONLAKE_LVDS_D_N_MAX   3
282 #define IRONLAKE_LVDS_D_M_MIN   79
283 #define IRONLAKE_LVDS_D_M_MAX   127
284 #define IRONLAKE_LVDS_D_P_MIN   14
285 #define IRONLAKE_LVDS_D_P_MAX   56
286 #define IRONLAKE_LVDS_D_P1_MIN  2
287 #define IRONLAKE_LVDS_D_P1_MAX  8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN               1
317 #define IRONLAKE_DP_N_MAX               2
318 #define IRONLAKE_DP_M_MIN               81
319 #define IRONLAKE_DP_M_MAX               90
320 #define IRONLAKE_DP_P_MIN               10
321 #define IRONLAKE_DP_P_MAX               20
322 #define IRONLAKE_DP_P2_FAST             10
323 #define IRONLAKE_DP_P2_SLOW             10
324 #define IRONLAKE_DP_P2_LIMIT            0
325 #define IRONLAKE_DP_P1_MIN              1
326 #define IRONLAKE_DP_P1_MAX              2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333                     int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336                         int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340                       int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343                            int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348         if (IS_GEN5(dev)) {
349                 struct drm_i915_private *dev_priv = dev->dev_private;
350                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351         } else
352                 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
357         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
358         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
359         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
360         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
361         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
362         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
363         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
364         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
366         .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
371         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
372         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
373         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
374         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
375         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
376         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
377         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
378         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
380         .find_pll = intel_find_best_PLL,
381 };
382         
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
385         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
386         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
387         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
388         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
389         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
390         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
391         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
392         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394         .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
399         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
400         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
401         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
402         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
403         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
404         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
405         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
406         /* The single-channel range is 25-112Mhz, and dual-channel
407          * is 80-224Mhz.  Prefer single channel as much as possible.
408          */
409         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
411         .find_pll = intel_find_best_PLL,
412 };
413
414     /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
417         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
418         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
419         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
420         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
421         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
422         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
423         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
424         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
425                  .p2_slow = G4X_P2_SDVO_SLOW,
426                  .p2_fast = G4X_P2_SDVO_FAST
427         },
428         .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
433         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
434         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
435         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
436         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
437         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
438         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
439         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
440         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442                  .p2_fast = G4X_P2_HDMI_DAC_FAST
443         },
444         .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450         .vco = { .min = G4X_VCO_MIN,
451                  .max = G4X_VCO_MAX },
452         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467         },
468         .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474         .vco = { .min = G4X_VCO_MIN,
475                  .max = G4X_VCO_MAX },
476         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491         },
492         .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497                  .max = G4X_DOT_DISPLAY_PORT_MAX },
498         .vco = { .min = G4X_VCO_MIN,
499                  .max = G4X_VCO_MAX},
500         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
501                  .max = G4X_N_DISPLAY_PORT_MAX },
502         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
503                  .max = G4X_M_DISPLAY_PORT_MAX },
504         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
505                  .max = G4X_M1_DISPLAY_PORT_MAX },
506         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
507                  .max = G4X_M2_DISPLAY_PORT_MAX },
508         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
509                  .max = G4X_P_DISPLAY_PORT_MAX },
510         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
511                  .max = G4X_P1_DISPLAY_PORT_MAX},
512         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515         .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
520         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
521         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
522         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
523         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
524         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
525         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
526         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
527         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529         .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
534         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
535         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
536         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
537         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
538         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
539         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
540         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
541         /* Pineview only supports single-channel mode. */
542         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
544         .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
549         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
550         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
551         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
552         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
553         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
554         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
555         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
556         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
558                  .p2_fast = IRONLAKE_DAC_P2_FAST },
559         .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
564         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
565         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
566         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
567         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
568         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
569         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
570         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
571         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574         .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
579         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
580         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
581         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
582         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
583         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
584         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
585         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
586         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589         .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
594         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
595         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
598         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
599         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604         .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
609         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
610         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
613         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
614         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619         .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623         .dot = { .min = IRONLAKE_DOT_MIN,
624                  .max = IRONLAKE_DOT_MAX },
625         .vco = { .min = IRONLAKE_VCO_MIN,
626                  .max = IRONLAKE_VCO_MAX},
627         .n   = { .min = IRONLAKE_DP_N_MIN,
628                  .max = IRONLAKE_DP_N_MAX },
629         .m   = { .min = IRONLAKE_DP_M_MIN,
630                  .max = IRONLAKE_DP_M_MAX },
631         .m1  = { .min = IRONLAKE_M1_MIN,
632                  .max = IRONLAKE_M1_MAX },
633         .m2  = { .min = IRONLAKE_M2_MIN,
634                  .max = IRONLAKE_M2_MAX },
635         .p   = { .min = IRONLAKE_DP_P_MIN,
636                  .max = IRONLAKE_DP_P_MAX },
637         .p1  = { .min = IRONLAKE_DP_P1_MIN,
638                  .max = IRONLAKE_DP_P1_MAX},
639         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640                  .p2_slow = IRONLAKE_DP_P2_SLOW,
641                  .p2_fast = IRONLAKE_DP_P2_FAST },
642         .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
646 {
647         struct drm_device *dev = crtc->dev;
648         struct drm_i915_private *dev_priv = dev->dev_private;
649         const intel_limit_t *limit;
650         int refclk = 120;
651
652         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
654                         refclk = 100;
655
656                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
657                     LVDS_CLKB_POWER_UP) {
658                         /* LVDS dual channel */
659                         if (refclk == 100)
660                                 limit = &intel_limits_ironlake_dual_lvds_100m;
661                         else
662                                 limit = &intel_limits_ironlake_dual_lvds;
663                 } else {
664                         if (refclk == 100)
665                                 limit = &intel_limits_ironlake_single_lvds_100m;
666                         else
667                                 limit = &intel_limits_ironlake_single_lvds;
668                 }
669         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
670                         HAS_eDP)
671                 limit = &intel_limits_ironlake_display_port;
672         else
673                 limit = &intel_limits_ironlake_dac;
674
675         return limit;
676 }
677
678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
679 {
680         struct drm_device *dev = crtc->dev;
681         struct drm_i915_private *dev_priv = dev->dev_private;
682         const intel_limit_t *limit;
683
684         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
685                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
686                     LVDS_CLKB_POWER_UP)
687                         /* LVDS with dual channel */
688                         limit = &intel_limits_g4x_dual_channel_lvds;
689                 else
690                         /* LVDS with dual channel */
691                         limit = &intel_limits_g4x_single_channel_lvds;
692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
694                 limit = &intel_limits_g4x_hdmi;
695         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
696                 limit = &intel_limits_g4x_sdvo;
697         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
698                 limit = &intel_limits_g4x_display_port;
699         } else /* The option is for other outputs */
700                 limit = &intel_limits_i9xx_sdvo;
701
702         return limit;
703 }
704
705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
706 {
707         struct drm_device *dev = crtc->dev;
708         const intel_limit_t *limit;
709
710         if (HAS_PCH_SPLIT(dev))
711                 limit = intel_ironlake_limit(crtc);
712         else if (IS_G4X(dev)) {
713                 limit = intel_g4x_limit(crtc);
714         } else if (IS_PINEVIEW(dev)) {
715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716                         limit = &intel_limits_pineview_lvds;
717                 else
718                         limit = &intel_limits_pineview_sdvo;
719         } else if (!IS_GEN2(dev)) {
720                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
721                         limit = &intel_limits_i9xx_lvds;
722                 else
723                         limit = &intel_limits_i9xx_sdvo;
724         } else {
725                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
726                         limit = &intel_limits_i8xx_lvds;
727                 else
728                         limit = &intel_limits_i8xx_dvo;
729         }
730         return limit;
731 }
732
733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
734 static void pineview_clock(int refclk, intel_clock_t *clock)
735 {
736         clock->m = clock->m2 + 2;
737         clock->p = clock->p1 * clock->p2;
738         clock->vco = refclk * clock->m / clock->n;
739         clock->dot = clock->vco / clock->p;
740 }
741
742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
743 {
744         if (IS_PINEVIEW(dev)) {
745                 pineview_clock(refclk, clock);
746                 return;
747         }
748         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
749         clock->p = clock->p1 * clock->p2;
750         clock->vco = refclk * clock->m / (clock->n + 2);
751         clock->dot = clock->vco / clock->p;
752 }
753
754 /**
755  * Returns whether any output on the specified pipe is of the specified type
756  */
757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
758 {
759         struct drm_device *dev = crtc->dev;
760         struct drm_mode_config *mode_config = &dev->mode_config;
761         struct intel_encoder *encoder;
762
763         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
764                 if (encoder->base.crtc == crtc && encoder->type == type)
765                         return true;
766
767         return false;
768 }
769
770 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
771 /**
772  * Returns whether the given set of divisors are valid for a given refclk with
773  * the given connectors.
774  */
775
776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
777 {
778         const intel_limit_t *limit = intel_limit (crtc);
779         struct drm_device *dev = crtc->dev;
780
781         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
782                 INTELPllInvalid ("p1 out of range\n");
783         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
784                 INTELPllInvalid ("p out of range\n");
785         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
786                 INTELPllInvalid ("m2 out of range\n");
787         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
788                 INTELPllInvalid ("m1 out of range\n");
789         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
790                 INTELPllInvalid ("m1 <= m2\n");
791         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
792                 INTELPllInvalid ("m out of range\n");
793         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
794                 INTELPllInvalid ("n out of range\n");
795         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
796                 INTELPllInvalid ("vco out of range\n");
797         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
798          * connector, etc., rather than just a single range.
799          */
800         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
801                 INTELPllInvalid ("dot out of range\n");
802
803         return true;
804 }
805
806 static bool
807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
808                     int target, int refclk, intel_clock_t *best_clock)
809
810 {
811         struct drm_device *dev = crtc->dev;
812         struct drm_i915_private *dev_priv = dev->dev_private;
813         intel_clock_t clock;
814         int err = target;
815
816         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
817             (I915_READ(LVDS)) != 0) {
818                 /*
819                  * For LVDS, if the panel is on, just rely on its current
820                  * settings for dual-channel.  We haven't figured out how to
821                  * reliably set up different single/dual channel state, if we
822                  * even can.
823                  */
824                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
825                     LVDS_CLKB_POWER_UP)
826                         clock.p2 = limit->p2.p2_fast;
827                 else
828                         clock.p2 = limit->p2.p2_slow;
829         } else {
830                 if (target < limit->p2.dot_limit)
831                         clock.p2 = limit->p2.p2_slow;
832                 else
833                         clock.p2 = limit->p2.p2_fast;
834         }
835
836         memset (best_clock, 0, sizeof (*best_clock));
837
838         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
839              clock.m1++) {
840                 for (clock.m2 = limit->m2.min;
841                      clock.m2 <= limit->m2.max; clock.m2++) {
842                         /* m1 is always 0 in Pineview */
843                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
844                                 break;
845                         for (clock.n = limit->n.min;
846                              clock.n <= limit->n.max; clock.n++) {
847                                 for (clock.p1 = limit->p1.min;
848                                         clock.p1 <= limit->p1.max; clock.p1++) {
849                                         int this_err;
850
851                                         intel_clock(dev, refclk, &clock);
852
853                                         if (!intel_PLL_is_valid(crtc, &clock))
854                                                 continue;
855
856                                         this_err = abs(clock.dot - target);
857                                         if (this_err < err) {
858                                                 *best_clock = clock;
859                                                 err = this_err;
860                                         }
861                                 }
862                         }
863                 }
864         }
865
866         return (err != target);
867 }
868
869 static bool
870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
871                         int target, int refclk, intel_clock_t *best_clock)
872 {
873         struct drm_device *dev = crtc->dev;
874         struct drm_i915_private *dev_priv = dev->dev_private;
875         intel_clock_t clock;
876         int max_n;
877         bool found;
878         /* approximately equals target * 0.00585 */
879         int err_most = (target >> 8) + (target >> 9);
880         found = false;
881
882         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
883                 int lvds_reg;
884
885                 if (HAS_PCH_SPLIT(dev))
886                         lvds_reg = PCH_LVDS;
887                 else
888                         lvds_reg = LVDS;
889                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
890                     LVDS_CLKB_POWER_UP)
891                         clock.p2 = limit->p2.p2_fast;
892                 else
893                         clock.p2 = limit->p2.p2_slow;
894         } else {
895                 if (target < limit->p2.dot_limit)
896                         clock.p2 = limit->p2.p2_slow;
897                 else
898                         clock.p2 = limit->p2.p2_fast;
899         }
900
901         memset(best_clock, 0, sizeof(*best_clock));
902         max_n = limit->n.max;
903         /* based on hardware requirement, prefer smaller n to precision */
904         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
905                 /* based on hardware requirement, prefere larger m1,m2 */
906                 for (clock.m1 = limit->m1.max;
907                      clock.m1 >= limit->m1.min; clock.m1--) {
908                         for (clock.m2 = limit->m2.max;
909                              clock.m2 >= limit->m2.min; clock.m2--) {
910                                 for (clock.p1 = limit->p1.max;
911                                      clock.p1 >= limit->p1.min; clock.p1--) {
912                                         int this_err;
913
914                                         intel_clock(dev, refclk, &clock);
915                                         if (!intel_PLL_is_valid(crtc, &clock))
916                                                 continue;
917                                         this_err = abs(clock.dot - target) ;
918                                         if (this_err < err_most) {
919                                                 *best_clock = clock;
920                                                 err_most = this_err;
921                                                 max_n = clock.n;
922                                                 found = true;
923                                         }
924                                 }
925                         }
926                 }
927         }
928         return found;
929 }
930
931 static bool
932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
933                            int target, int refclk, intel_clock_t *best_clock)
934 {
935         struct drm_device *dev = crtc->dev;
936         intel_clock_t clock;
937
938         if (target < 200000) {
939                 clock.n = 1;
940                 clock.p1 = 2;
941                 clock.p2 = 10;
942                 clock.m1 = 12;
943                 clock.m2 = 9;
944         } else {
945                 clock.n = 2;
946                 clock.p1 = 1;
947                 clock.p2 = 10;
948                 clock.m1 = 14;
949                 clock.m2 = 8;
950         }
951         intel_clock(dev, refclk, &clock);
952         memcpy(best_clock, &clock, sizeof(intel_clock_t));
953         return true;
954 }
955
956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
957 static bool
958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
959                       int target, int refclk, intel_clock_t *best_clock)
960 {
961         intel_clock_t clock;
962         if (target < 200000) {
963                 clock.p1 = 2;
964                 clock.p2 = 10;
965                 clock.n = 2;
966                 clock.m1 = 23;
967                 clock.m2 = 8;
968         } else {
969                 clock.p1 = 1;
970                 clock.p2 = 10;
971                 clock.n = 1;
972                 clock.m1 = 14;
973                 clock.m2 = 2;
974         }
975         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
976         clock.p = (clock.p1 * clock.p2);
977         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
978         clock.vco = 0;
979         memcpy(best_clock, &clock, sizeof(intel_clock_t));
980         return true;
981 }
982
983 /**
984  * intel_wait_for_vblank - wait for vblank on a given pipe
985  * @dev: drm device
986  * @pipe: pipe to wait for
987  *
988  * Wait for vblank to occur on a given pipe.  Needed for various bits of
989  * mode setting code.
990  */
991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
992 {
993         struct drm_i915_private *dev_priv = dev->dev_private;
994         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
995
996         /* Clear existing vblank status. Note this will clear any other
997          * sticky status fields as well.
998          *
999          * This races with i915_driver_irq_handler() with the result
1000          * that either function could miss a vblank event.  Here it is not
1001          * fatal, as we will either wait upon the next vblank interrupt or
1002          * timeout.  Generally speaking intel_wait_for_vblank() is only
1003          * called during modeset at which time the GPU should be idle and
1004          * should *not* be performing page flips and thus not waiting on
1005          * vblanks...
1006          * Currently, the result of us stealing a vblank from the irq
1007          * handler is that a single frame will be skipped during swapbuffers.
1008          */
1009         I915_WRITE(pipestat_reg,
1010                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012         /* Wait for vblank interrupt bit to set */
1013         if (wait_for(I915_READ(pipestat_reg) &
1014                      PIPE_VBLANK_INTERRUPT_STATUS,
1015                      50))
1016                 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @dev: drm device
1022  * @pipe: pipe to wait for
1023  *
1024  * After disabling a pipe, we can't wait for vblank in the usual way,
1025  * spinning on the vblank interrupt status bit, since we won't actually
1026  * see an interrupt when the pipe is disabled.
1027  *
1028  * On Gen4 and above:
1029  *   wait for the pipe register state bit to turn off
1030  *
1031  * Otherwise:
1032  *   wait for the display line value to settle (it usually
1033  *   ends up stopping at the start of the next frame).
1034  *
1035  */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040         if (INTEL_INFO(dev)->gen >= 4) {
1041                 int reg = PIPECONF(pipe);
1042
1043                 /* Wait for the Pipe State to go off */
1044                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045                              100))
1046                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047         } else {
1048                 u32 last_line;
1049                 int reg = PIPEDSL(pipe);
1050                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052                 /* Wait for the display line to settle */
1053                 do {
1054                         last_line = I915_READ(reg) & DSL_LINEMASK;
1055                         mdelay(5);
1056                 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057                          time_after(timeout, jiffies));
1058                 if (time_after(jiffies, timeout))
1059                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060         }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067         struct drm_framebuffer *fb = crtc->fb;
1068         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071         int plane, i;
1072         u32 fbc_ctl, fbc_ctl2;
1073
1074         if (fb->pitch == dev_priv->cfb_pitch &&
1075             obj_priv->fence_reg == dev_priv->cfb_fence &&
1076             intel_crtc->plane == dev_priv->cfb_plane &&
1077             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078                 return;
1079
1080         i8xx_disable_fbc(dev);
1081
1082         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084         if (fb->pitch < dev_priv->cfb_pitch)
1085                 dev_priv->cfb_pitch = fb->pitch;
1086
1087         /* FBC_CTL wants 64B units */
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093         /* Clear old tags */
1094         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095                 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097         /* Set it up... */
1098         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099         if (obj_priv->tiling_mode != I915_TILING_NONE)
1100                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104         /* enable it... */
1105         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106         if (IS_I945GM(dev))
1107                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110         if (obj_priv->tiling_mode != I915_TILING_NONE)
1111                 fbc_ctl |= dev_priv->cfb_fence;
1112         I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120         struct drm_i915_private *dev_priv = dev->dev_private;
1121         u32 fbc_ctl;
1122
1123         /* Disable compression */
1124         fbc_ctl = I915_READ(FBC_CONTROL);
1125         if ((fbc_ctl & FBC_CTL_EN) == 0)
1126                 return;
1127
1128         fbc_ctl &= ~FBC_CTL_EN;
1129         I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131         /* Wait for compressing bit to clear */
1132         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133                 DRM_DEBUG_KMS("FBC idle timed out\n");
1134                 return;
1135         }
1136
1137         DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149         struct drm_device *dev = crtc->dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct drm_framebuffer *fb = crtc->fb;
1152         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156         unsigned long stall_watermark = 200;
1157         u32 dpfc_ctl;
1158
1159         dpfc_ctl = I915_READ(DPFC_CONTROL);
1160         if (dpfc_ctl & DPFC_CTL_EN) {
1161                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1163                     dev_priv->cfb_plane == intel_crtc->plane &&
1164                     dev_priv->cfb_y == crtc->y)
1165                         return;
1166
1167                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168                 POSTING_READ(DPFC_CONTROL);
1169                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170         }
1171
1172         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173         dev_priv->cfb_fence = obj_priv->fence_reg;
1174         dev_priv->cfb_plane = intel_crtc->plane;
1175         dev_priv->cfb_y = crtc->y;
1176
1177         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181         } else {
1182                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183         }
1184
1185         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190         /* enable it... */
1191         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199         u32 dpfc_ctl;
1200
1201         /* Disable compression */
1202         dpfc_ctl = I915_READ(DPFC_CONTROL);
1203         if (dpfc_ctl & DPFC_CTL_EN) {
1204                 dpfc_ctl &= ~DPFC_CTL_EN;
1205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207                 DRM_DEBUG_KMS("disabled FBC\n");
1208         }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220         struct drm_device *dev = crtc->dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         struct drm_framebuffer *fb = crtc->fb;
1223         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227         unsigned long stall_watermark = 200;
1228         u32 dpfc_ctl;
1229
1230         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231         if (dpfc_ctl & DPFC_CTL_EN) {
1232                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1234                     dev_priv->cfb_plane == intel_crtc->plane &&
1235                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236                     dev_priv->cfb_y == crtc->y)
1237                         return;
1238
1239                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240                 POSTING_READ(ILK_DPFC_CONTROL);
1241                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242         }
1243
1244         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245         dev_priv->cfb_fence = obj_priv->fence_reg;
1246         dev_priv->cfb_plane = intel_crtc->plane;
1247         dev_priv->cfb_offset = obj_priv->gtt_offset;
1248         dev_priv->cfb_y = crtc->y;
1249
1250         dpfc_ctl &= DPFC_RESERVED;
1251         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255         } else {
1256                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257         }
1258
1259         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264         /* enable it... */
1265         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         u32 dpfc_ctl;
1274
1275         /* Disable compression */
1276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277         if (dpfc_ctl & DPFC_CTL_EN) {
1278                 dpfc_ctl &= ~DPFC_CTL_EN;
1279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281                 DRM_DEBUG_KMS("disabled FBC\n");
1282         }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294         struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296         if (!dev_priv->display.fbc_enabled)
1297                 return false;
1298
1299         return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306         if (!dev_priv->display.enable_fbc)
1307                 return;
1308
1309         dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316         if (!dev_priv->display.disable_fbc)
1317                 return;
1318
1319         dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323  * intel_update_fbc - enable/disable FBC as needed
1324  * @dev: the drm_device
1325  *
1326  * Set up the framebuffer compression hardware at mode set time.  We
1327  * enable it if possible:
1328  *   - plane A only (on pre-965)
1329  *   - no pixel mulitply/line duplication
1330  *   - no alpha buffer discard
1331  *   - no dual wide
1332  *   - framebuffer <= 2048 in width, 1536 in height
1333  *
1334  * We can't assume that any compression will take place (worst case),
1335  * so the compressed buffer has to be the same size as the uncompressed
1336  * one.  It also must reside (along with the line length buffer) in
1337  * stolen memory.
1338  *
1339  * We need to enable/disable FBC on a global basis.
1340  */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct drm_crtc *crtc = NULL, *tmp_crtc;
1345         struct intel_crtc *intel_crtc;
1346         struct drm_framebuffer *fb;
1347         struct intel_framebuffer *intel_fb;
1348         struct drm_i915_gem_object *obj_priv;
1349
1350         DRM_DEBUG_KMS("\n");
1351
1352         if (!i915_powersave)
1353                 return;
1354
1355         if (!I915_HAS_FBC(dev))
1356                 return;
1357
1358         /*
1359          * If FBC is already on, we just have to verify that we can
1360          * keep it that way...
1361          * Need to disable if:
1362          *   - more than one pipe is active
1363          *   - changing FBC params (stride, fence, mode)
1364          *   - new fb is too large to fit in compressed buffer
1365          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1366          */
1367         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368                 if (tmp_crtc->enabled) {
1369                         if (crtc) {
1370                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372                                 goto out_disable;
1373                         }
1374                         crtc = tmp_crtc;
1375                 }
1376         }
1377
1378         if (!crtc || crtc->fb == NULL) {
1379                 DRM_DEBUG_KMS("no output, disabling\n");
1380                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381                 goto out_disable;
1382         }
1383
1384         intel_crtc = to_intel_crtc(crtc);
1385         fb = crtc->fb;
1386         intel_fb = to_intel_framebuffer(fb);
1387         obj_priv = to_intel_bo(intel_fb->obj);
1388
1389         if (intel_fb->obj->size > dev_priv->cfb_size) {
1390                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391                               "compression\n");
1392                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393                 goto out_disable;
1394         }
1395         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397                 DRM_DEBUG_KMS("mode incompatible with compression, "
1398                               "disabling\n");
1399                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400                 goto out_disable;
1401         }
1402         if ((crtc->mode.hdisplay > 2048) ||
1403             (crtc->mode.vdisplay > 1536)) {
1404                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406                 goto out_disable;
1407         }
1408         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411                 goto out_disable;
1412         }
1413         if (obj_priv->tiling_mode != I915_TILING_X) {
1414                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416                 goto out_disable;
1417         }
1418
1419         /* If the kernel debugger is active, always disable compression */
1420         if (in_dbg_master())
1421                 goto out_disable;
1422
1423         intel_enable_fbc(crtc, 500);
1424         return;
1425
1426 out_disable:
1427         /* Multiple disables should be harmless */
1428         if (intel_fbc_enabled(dev)) {
1429                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430                 intel_disable_fbc(dev);
1431         }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436                            struct drm_gem_object *obj,
1437                            bool pipelined)
1438 {
1439         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440         u32 alignment;
1441         int ret;
1442
1443         switch (obj_priv->tiling_mode) {
1444         case I915_TILING_NONE:
1445                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446                         alignment = 128 * 1024;
1447                 else if (INTEL_INFO(dev)->gen >= 4)
1448                         alignment = 4 * 1024;
1449                 else
1450                         alignment = 64 * 1024;
1451                 break;
1452         case I915_TILING_X:
1453                 /* pin() will align the object as required by fence */
1454                 alignment = 0;
1455                 break;
1456         case I915_TILING_Y:
1457                 /* FIXME: Is this true? */
1458                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459                 return -EINVAL;
1460         default:
1461                 BUG();
1462         }
1463
1464         ret = i915_gem_object_pin(obj, alignment);
1465         if (ret)
1466                 return ret;
1467
1468         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469         if (ret)
1470                 goto err_unpin;
1471
1472         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473          * fence, whereas 965+ only requires a fence if using
1474          * framebuffer compression.  For simplicity, we always install
1475          * a fence as the cost is not that onerous.
1476          */
1477         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478             obj_priv->tiling_mode != I915_TILING_NONE) {
1479                 ret = i915_gem_object_get_fence_reg(obj, false);
1480                 if (ret)
1481                         goto err_unpin;
1482         }
1483
1484         return 0;
1485
1486 err_unpin:
1487         i915_gem_object_unpin(obj);
1488         return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494                            int x, int y, enum mode_set_atomic state)
1495 {
1496         struct drm_device *dev = crtc->dev;
1497         struct drm_i915_private *dev_priv = dev->dev_private;
1498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499         struct intel_framebuffer *intel_fb;
1500         struct drm_i915_gem_object *obj_priv;
1501         struct drm_gem_object *obj;
1502         int plane = intel_crtc->plane;
1503         unsigned long Start, Offset;
1504         u32 dspcntr;
1505         u32 reg;
1506
1507         switch (plane) {
1508         case 0:
1509         case 1:
1510                 break;
1511         default:
1512                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513                 return -EINVAL;
1514         }
1515
1516         intel_fb = to_intel_framebuffer(fb);
1517         obj = intel_fb->obj;
1518         obj_priv = to_intel_bo(obj);
1519
1520         reg = DSPCNTR(plane);
1521         dspcntr = I915_READ(reg);
1522         /* Mask out pixel format bits in case we change it */
1523         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524         switch (fb->bits_per_pixel) {
1525         case 8:
1526                 dspcntr |= DISPPLANE_8BPP;
1527                 break;
1528         case 16:
1529                 if (fb->depth == 15)
1530                         dspcntr |= DISPPLANE_15_16BPP;
1531                 else
1532                         dspcntr |= DISPPLANE_16BPP;
1533                 break;
1534         case 24:
1535         case 32:
1536                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537                 break;
1538         default:
1539                 DRM_ERROR("Unknown color depth\n");
1540                 return -EINVAL;
1541         }
1542         if (INTEL_INFO(dev)->gen >= 4) {
1543                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544                         dspcntr |= DISPPLANE_TILED;
1545                 else
1546                         dspcntr &= ~DISPPLANE_TILED;
1547         }
1548
1549         if (HAS_PCH_SPLIT(dev))
1550                 /* must disable */
1551                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553         I915_WRITE(reg, dspcntr);
1554
1555         Start = obj_priv->gtt_offset;
1556         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559                       Start, Offset, x, y, fb->pitch);
1560         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561         if (INTEL_INFO(dev)->gen >= 4) {
1562                 I915_WRITE(DSPSURF(plane), Start);
1563                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564                 I915_WRITE(DSPADDR(plane), Offset);
1565         } else
1566                 I915_WRITE(DSPADDR(plane), Start + Offset);
1567         POSTING_READ(reg);
1568
1569         intel_update_fbc(dev);
1570         intel_increase_pllclock(crtc);
1571
1572         return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577                     struct drm_framebuffer *old_fb)
1578 {
1579         struct drm_device *dev = crtc->dev;
1580         struct drm_i915_master_private *master_priv;
1581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582         int ret;
1583
1584         /* no fb bound */
1585         if (!crtc->fb) {
1586                 DRM_DEBUG_KMS("No FB bound\n");
1587                 return 0;
1588         }
1589
1590         switch (intel_crtc->plane) {
1591         case 0:
1592         case 1:
1593                 break;
1594         default:
1595                 return -EINVAL;
1596         }
1597
1598         mutex_lock(&dev->struct_mutex);
1599         ret = intel_pin_and_fence_fb_obj(dev,
1600                                          to_intel_framebuffer(crtc->fb)->obj,
1601                                          false);
1602         if (ret != 0) {
1603                 mutex_unlock(&dev->struct_mutex);
1604                 return ret;
1605         }
1606
1607         if (old_fb) {
1608                 struct drm_i915_private *dev_priv = dev->dev_private;
1609                 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612                 wait_event(dev_priv->pending_flip_queue,
1613                            atomic_read(&obj_priv->pending_flip) == 0);
1614         }
1615
1616         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1617                                          LEAVE_ATOMIC_MODE_SET);
1618         if (ret) {
1619                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1620                 mutex_unlock(&dev->struct_mutex);
1621                 return ret;
1622         }
1623
1624         if (old_fb)
1625                 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1626
1627         mutex_unlock(&dev->struct_mutex);
1628
1629         if (!dev->primary->master)
1630                 return 0;
1631
1632         master_priv = dev->primary->master->driver_priv;
1633         if (!master_priv->sarea_priv)
1634                 return 0;
1635
1636         if (intel_crtc->pipe) {
1637                 master_priv->sarea_priv->pipeB_x = x;
1638                 master_priv->sarea_priv->pipeB_y = y;
1639         } else {
1640                 master_priv->sarea_priv->pipeA_x = x;
1641                 master_priv->sarea_priv->pipeA_y = y;
1642         }
1643
1644         return 0;
1645 }
1646
1647 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1648 {
1649         struct drm_device *dev = crtc->dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         u32 dpa_ctl;
1652
1653         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1654         dpa_ctl = I915_READ(DP_A);
1655         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1656
1657         if (clock < 200000) {
1658                 u32 temp;
1659                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1660                 /* workaround for 160Mhz:
1661                    1) program 0x4600c bits 15:0 = 0x8124
1662                    2) program 0x46010 bit 0 = 1
1663                    3) program 0x46034 bit 24 = 1
1664                    4) program 0x64000 bit 14 = 1
1665                    */
1666                 temp = I915_READ(0x4600c);
1667                 temp &= 0xffff0000;
1668                 I915_WRITE(0x4600c, temp | 0x8124);
1669
1670                 temp = I915_READ(0x46010);
1671                 I915_WRITE(0x46010, temp | 1);
1672
1673                 temp = I915_READ(0x46034);
1674                 I915_WRITE(0x46034, temp | (1 << 24));
1675         } else {
1676                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1677         }
1678         I915_WRITE(DP_A, dpa_ctl);
1679
1680         POSTING_READ(DP_A);
1681         udelay(500);
1682 }
1683
1684 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1685 {
1686         struct drm_device *dev = crtc->dev;
1687         struct drm_i915_private *dev_priv = dev->dev_private;
1688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1689         int pipe = intel_crtc->pipe;
1690         u32 reg, temp;
1691
1692         /* enable normal train */
1693         reg = FDI_TX_CTL(pipe);
1694         temp = I915_READ(reg);
1695         temp &= ~FDI_LINK_TRAIN_NONE;
1696         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1697         I915_WRITE(reg, temp);
1698
1699         reg = FDI_RX_CTL(pipe);
1700         temp = I915_READ(reg);
1701         if (HAS_PCH_CPT(dev)) {
1702                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1703                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1704         } else {
1705                 temp &= ~FDI_LINK_TRAIN_NONE;
1706                 temp |= FDI_LINK_TRAIN_NONE;
1707         }
1708         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1709
1710         /* wait one idle pattern time */
1711         POSTING_READ(reg);
1712         udelay(1000);
1713 }
1714
1715 /* The FDI link training functions for ILK/Ibexpeak. */
1716 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1717 {
1718         struct drm_device *dev = crtc->dev;
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1721         int pipe = intel_crtc->pipe;
1722         u32 reg, temp, tries;
1723
1724         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1725            for train result */
1726         reg = FDI_RX_IMR(pipe);
1727         temp = I915_READ(reg);
1728         temp &= ~FDI_RX_SYMBOL_LOCK;
1729         temp &= ~FDI_RX_BIT_LOCK;
1730         I915_WRITE(reg, temp);
1731         I915_READ(reg);
1732         udelay(150);
1733
1734         /* enable CPU FDI TX and PCH FDI RX */
1735         reg = FDI_TX_CTL(pipe);
1736         temp = I915_READ(reg);
1737         temp &= ~(7 << 19);
1738         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1739         temp &= ~FDI_LINK_TRAIN_NONE;
1740         temp |= FDI_LINK_TRAIN_PATTERN_1;
1741         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1742
1743         reg = FDI_RX_CTL(pipe);
1744         temp = I915_READ(reg);
1745         temp &= ~FDI_LINK_TRAIN_NONE;
1746         temp |= FDI_LINK_TRAIN_PATTERN_1;
1747         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1748
1749         POSTING_READ(reg);
1750         udelay(150);
1751
1752         /* Ironlake workaround, enable clock pointer after FDI enable*/
1753         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1754
1755         reg = FDI_RX_IIR(pipe);
1756         for (tries = 0; tries < 5; tries++) {
1757                 temp = I915_READ(reg);
1758                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1759
1760                 if ((temp & FDI_RX_BIT_LOCK)) {
1761                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1762                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1763                         break;
1764                 }
1765         }
1766         if (tries == 5)
1767                 DRM_ERROR("FDI train 1 fail!\n");
1768
1769         /* Train 2 */
1770         reg = FDI_TX_CTL(pipe);
1771         temp = I915_READ(reg);
1772         temp &= ~FDI_LINK_TRAIN_NONE;
1773         temp |= FDI_LINK_TRAIN_PATTERN_2;
1774         I915_WRITE(reg, temp);
1775
1776         reg = FDI_RX_CTL(pipe);
1777         temp = I915_READ(reg);
1778         temp &= ~FDI_LINK_TRAIN_NONE;
1779         temp |= FDI_LINK_TRAIN_PATTERN_2;
1780         I915_WRITE(reg, temp);
1781
1782         POSTING_READ(reg);
1783         udelay(150);
1784
1785         reg = FDI_RX_IIR(pipe);
1786         for (tries = 0; tries < 5; tries++) {
1787                 temp = I915_READ(reg);
1788                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1789
1790                 if (temp & FDI_RX_SYMBOL_LOCK) {
1791                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1792                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1793                         break;
1794                 }
1795         }
1796         if (tries == 5)
1797                 DRM_ERROR("FDI train 2 fail!\n");
1798
1799         DRM_DEBUG_KMS("FDI train done\n");
1800
1801 }
1802
1803 static const int const snb_b_fdi_train_param [] = {
1804         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1805         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1806         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1807         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1808 };
1809
1810 /* The FDI link training functions for SNB/Cougarpoint. */
1811 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1812 {
1813         struct drm_device *dev = crtc->dev;
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1816         int pipe = intel_crtc->pipe;
1817         u32 reg, temp, i;
1818
1819         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1820            for train result */
1821         reg = FDI_RX_IMR(pipe);
1822         temp = I915_READ(reg);
1823         temp &= ~FDI_RX_SYMBOL_LOCK;
1824         temp &= ~FDI_RX_BIT_LOCK;
1825         I915_WRITE(reg, temp);
1826
1827         POSTING_READ(reg);
1828         udelay(150);
1829
1830         /* enable CPU FDI TX and PCH FDI RX */
1831         reg = FDI_TX_CTL(pipe);
1832         temp = I915_READ(reg);
1833         temp &= ~(7 << 19);
1834         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1835         temp &= ~FDI_LINK_TRAIN_NONE;
1836         temp |= FDI_LINK_TRAIN_PATTERN_1;
1837         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838         /* SNB-B */
1839         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1840         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1841
1842         reg = FDI_RX_CTL(pipe);
1843         temp = I915_READ(reg);
1844         if (HAS_PCH_CPT(dev)) {
1845                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1846                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1847         } else {
1848                 temp &= ~FDI_LINK_TRAIN_NONE;
1849                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1850         }
1851         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1852
1853         POSTING_READ(reg);
1854         udelay(150);
1855
1856         for (i = 0; i < 4; i++ ) {
1857                 reg = FDI_TX_CTL(pipe);
1858                 temp = I915_READ(reg);
1859                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1860                 temp |= snb_b_fdi_train_param[i];
1861                 I915_WRITE(reg, temp);
1862
1863                 POSTING_READ(reg);
1864                 udelay(500);
1865
1866                 reg = FDI_RX_IIR(pipe);
1867                 temp = I915_READ(reg);
1868                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1869
1870                 if (temp & FDI_RX_BIT_LOCK) {
1871                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1872                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1873                         break;
1874                 }
1875         }
1876         if (i == 4)
1877                 DRM_ERROR("FDI train 1 fail!\n");
1878
1879         /* Train 2 */
1880         reg = FDI_TX_CTL(pipe);
1881         temp = I915_READ(reg);
1882         temp &= ~FDI_LINK_TRAIN_NONE;
1883         temp |= FDI_LINK_TRAIN_PATTERN_2;
1884         if (IS_GEN6(dev)) {
1885                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1886                 /* SNB-B */
1887                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1888         }
1889         I915_WRITE(reg, temp);
1890
1891         reg = FDI_RX_CTL(pipe);
1892         temp = I915_READ(reg);
1893         if (HAS_PCH_CPT(dev)) {
1894                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1895                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1896         } else {
1897                 temp &= ~FDI_LINK_TRAIN_NONE;
1898                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1899         }
1900         I915_WRITE(reg, temp);
1901
1902         POSTING_READ(reg);
1903         udelay(150);
1904
1905         for (i = 0; i < 4; i++ ) {
1906                 reg = FDI_TX_CTL(pipe);
1907                 temp = I915_READ(reg);
1908                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1909                 temp |= snb_b_fdi_train_param[i];
1910                 I915_WRITE(reg, temp);
1911
1912                 POSTING_READ(reg);
1913                 udelay(500);
1914
1915                 reg = FDI_RX_IIR(pipe);
1916                 temp = I915_READ(reg);
1917                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1918
1919                 if (temp & FDI_RX_SYMBOL_LOCK) {
1920                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1921                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1922                         break;
1923                 }
1924         }
1925         if (i == 4)
1926                 DRM_ERROR("FDI train 2 fail!\n");
1927
1928         DRM_DEBUG_KMS("FDI train done.\n");
1929 }
1930
1931 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1932 {
1933         struct drm_device *dev = crtc->dev;
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1936         int pipe = intel_crtc->pipe;
1937         u32 reg, temp;
1938
1939         /* Write the TU size bits so error detection works */
1940         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1941                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1942
1943         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1944         reg = FDI_RX_CTL(pipe);
1945         temp = I915_READ(reg);
1946         temp &= ~((0x7 << 19) | (0x7 << 16));
1947         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1948         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1949         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1950
1951         POSTING_READ(reg);
1952         udelay(200);
1953
1954         /* Switch from Rawclk to PCDclk */
1955         temp = I915_READ(reg);
1956         I915_WRITE(reg, temp | FDI_PCDCLK);
1957
1958         POSTING_READ(reg);
1959         udelay(200);
1960
1961         /* Enable CPU FDI TX PLL, always on for Ironlake */
1962         reg = FDI_TX_CTL(pipe);
1963         temp = I915_READ(reg);
1964         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1965                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1966
1967                 POSTING_READ(reg);
1968                 udelay(100);
1969         }
1970 }
1971
1972 static void intel_flush_display_plane(struct drm_device *dev,
1973                                       int plane)
1974 {
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         u32 reg = DSPADDR(plane);
1977         I915_WRITE(reg, I915_READ(reg));
1978 }
1979
1980 /*
1981  * When we disable a pipe, we need to clear any pending scanline wait events
1982  * to avoid hanging the ring, which we assume we are waiting on.
1983  */
1984 static void intel_clear_scanline_wait(struct drm_device *dev)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 tmp;
1988
1989         if (IS_GEN2(dev))
1990                 /* Can't break the hang on i8xx */
1991                 return;
1992
1993         tmp = I915_READ(PRB0_CTL);
1994         if (tmp & RING_WAIT) {
1995                 I915_WRITE(PRB0_CTL, tmp);
1996                 POSTING_READ(PRB0_CTL);
1997         }
1998 }
1999
2000 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2001 {
2002         struct drm_i915_gem_object *obj_priv;
2003         struct drm_i915_private *dev_priv;
2004
2005         if (crtc->fb == NULL)
2006                 return;
2007
2008         obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2009         dev_priv = crtc->dev->dev_private;
2010         wait_event(dev_priv->pending_flip_queue,
2011                    atomic_read(&obj_priv->pending_flip) == 0);
2012 }
2013
2014 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2015 {
2016         struct drm_device *dev = crtc->dev;
2017         struct drm_i915_private *dev_priv = dev->dev_private;
2018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2019         int pipe = intel_crtc->pipe;
2020         int plane = intel_crtc->plane;
2021         u32 reg, temp;
2022
2023         if (intel_crtc->active)
2024                 return;
2025
2026         intel_crtc->active = true;
2027         intel_update_watermarks(dev);
2028
2029         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2030                 temp = I915_READ(PCH_LVDS);
2031                 if ((temp & LVDS_PORT_EN) == 0)
2032                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2033         }
2034
2035         ironlake_fdi_enable(crtc);
2036
2037         /* Enable panel fitting for LVDS */
2038         if (dev_priv->pch_pf_size &&
2039             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2040                 /* Force use of hard-coded filter coefficients
2041                  * as some pre-programmed values are broken,
2042                  * e.g. x201.
2043                  */
2044                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2045                            PF_ENABLE | PF_FILTER_MED_3x3);
2046                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2047                            dev_priv->pch_pf_pos);
2048                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2049                            dev_priv->pch_pf_size);
2050         }
2051
2052         /* Enable CPU pipe */
2053         reg = PIPECONF(pipe);
2054         temp = I915_READ(reg);
2055         if ((temp & PIPECONF_ENABLE) == 0) {
2056                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2057                 POSTING_READ(reg);
2058                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2059         }
2060
2061         /* configure and enable CPU plane */
2062         reg = DSPCNTR(plane);
2063         temp = I915_READ(reg);
2064         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2065                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2066                 intel_flush_display_plane(dev, plane);
2067         }
2068
2069         /* For PCH output, training FDI link */
2070         if (IS_GEN6(dev))
2071                 gen6_fdi_link_train(crtc);
2072         else
2073                 ironlake_fdi_link_train(crtc);
2074
2075         /* enable PCH DPLL */
2076         reg = PCH_DPLL(pipe);
2077         temp = I915_READ(reg);
2078         if ((temp & DPLL_VCO_ENABLE) == 0) {
2079                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2080                 POSTING_READ(reg);
2081                 udelay(200);
2082         }
2083
2084         if (HAS_PCH_CPT(dev)) {
2085                 /* Be sure PCH DPLL SEL is set */
2086                 temp = I915_READ(PCH_DPLL_SEL);
2087                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2088                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2089                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2090                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2091                 I915_WRITE(PCH_DPLL_SEL, temp);
2092         }
2093
2094         /* set transcoder timing */
2095         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2096         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2097         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2098
2099         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2100         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2101         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2102
2103         intel_fdi_normal_train(crtc);
2104
2105         /* For PCH DP, enable TRANS_DP_CTL */
2106         if (HAS_PCH_CPT(dev) &&
2107             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2108                 reg = TRANS_DP_CTL(pipe);
2109                 temp = I915_READ(reg);
2110                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2111                           TRANS_DP_SYNC_MASK);
2112                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2113                          TRANS_DP_ENH_FRAMING);
2114
2115                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2116                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2117                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2118                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2119
2120                 switch (intel_trans_dp_port_sel(crtc)) {
2121                 case PCH_DP_B:
2122                         temp |= TRANS_DP_PORT_SEL_B;
2123                         break;
2124                 case PCH_DP_C:
2125                         temp |= TRANS_DP_PORT_SEL_C;
2126                         break;
2127                 case PCH_DP_D:
2128                         temp |= TRANS_DP_PORT_SEL_D;
2129                         break;
2130                 default:
2131                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2132                         temp |= TRANS_DP_PORT_SEL_B;
2133                         break;
2134                 }
2135
2136                 I915_WRITE(reg, temp);
2137         }
2138
2139         /* enable PCH transcoder */
2140         reg = TRANSCONF(pipe);
2141         temp = I915_READ(reg);
2142         /*
2143          * make the BPC in transcoder be consistent with
2144          * that in pipeconf reg.
2145          */
2146         temp &= ~PIPE_BPC_MASK;
2147         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2148         I915_WRITE(reg, temp | TRANS_ENABLE);
2149         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2150                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2151
2152         intel_crtc_load_lut(crtc);
2153         intel_update_fbc(dev);
2154         intel_crtc_update_cursor(crtc, true);
2155 }
2156
2157 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2158 {
2159         struct drm_device *dev = crtc->dev;
2160         struct drm_i915_private *dev_priv = dev->dev_private;
2161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2162         int pipe = intel_crtc->pipe;
2163         int plane = intel_crtc->plane;
2164         u32 reg, temp;
2165
2166         if (!intel_crtc->active)
2167                 return;
2168
2169         intel_crtc_wait_for_pending_flips(crtc);
2170         drm_vblank_off(dev, pipe);
2171         intel_crtc_update_cursor(crtc, false);
2172
2173         /* Disable display plane */
2174         reg = DSPCNTR(plane);
2175         temp = I915_READ(reg);
2176         if (temp & DISPLAY_PLANE_ENABLE) {
2177                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2178                 intel_flush_display_plane(dev, plane);
2179         }
2180
2181         if (dev_priv->cfb_plane == plane &&
2182             dev_priv->display.disable_fbc)
2183                 dev_priv->display.disable_fbc(dev);
2184
2185         /* disable cpu pipe, disable after all planes disabled */
2186         reg = PIPECONF(pipe);
2187         temp = I915_READ(reg);
2188         if (temp & PIPECONF_ENABLE) {
2189                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2190                 POSTING_READ(reg);
2191                 /* wait for cpu pipe off, pipe state */
2192                 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2193         }
2194
2195         /* Disable PF */
2196         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2197         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2198
2199         /* disable CPU FDI tx and PCH FDI rx */
2200         reg = FDI_TX_CTL(pipe);
2201         temp = I915_READ(reg);
2202         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2203         POSTING_READ(reg);
2204
2205         reg = FDI_RX_CTL(pipe);
2206         temp = I915_READ(reg);
2207         temp &= ~(0x7 << 16);
2208         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2209         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2210
2211         POSTING_READ(reg);
2212         udelay(100);
2213
2214         /* Ironlake workaround, disable clock pointer after downing FDI */
2215         if (HAS_PCH_IBX(dev))
2216                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2217                            I915_READ(FDI_RX_CHICKEN(pipe) &
2218                                      ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2219
2220         /* still set train pattern 1 */
2221         reg = FDI_TX_CTL(pipe);
2222         temp = I915_READ(reg);
2223         temp &= ~FDI_LINK_TRAIN_NONE;
2224         temp |= FDI_LINK_TRAIN_PATTERN_1;
2225         I915_WRITE(reg, temp);
2226
2227         reg = FDI_RX_CTL(pipe);
2228         temp = I915_READ(reg);
2229         if (HAS_PCH_CPT(dev)) {
2230                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2231                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2232         } else {
2233                 temp &= ~FDI_LINK_TRAIN_NONE;
2234                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2235         }
2236         /* BPC in FDI rx is consistent with that in PIPECONF */
2237         temp &= ~(0x07 << 16);
2238         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2239         I915_WRITE(reg, temp);
2240
2241         POSTING_READ(reg);
2242         udelay(100);
2243
2244         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2245                 temp = I915_READ(PCH_LVDS);
2246                 if (temp & LVDS_PORT_EN) {
2247                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2248                         POSTING_READ(PCH_LVDS);
2249                         udelay(100);
2250                 }
2251         }
2252
2253         /* disable PCH transcoder */
2254         reg = TRANSCONF(plane);
2255         temp = I915_READ(reg);
2256         if (temp & TRANS_ENABLE) {
2257                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2258                 /* wait for PCH transcoder off, transcoder state */
2259                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2260                         DRM_ERROR("failed to disable transcoder\n");
2261         }
2262
2263         if (HAS_PCH_CPT(dev)) {
2264                 /* disable TRANS_DP_CTL */
2265                 reg = TRANS_DP_CTL(pipe);
2266                 temp = I915_READ(reg);
2267                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2268                 I915_WRITE(reg, temp);
2269
2270                 /* disable DPLL_SEL */
2271                 temp = I915_READ(PCH_DPLL_SEL);
2272                 if (pipe == 0)
2273                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2274                 else
2275                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2276                 I915_WRITE(PCH_DPLL_SEL, temp);
2277         }
2278
2279         /* disable PCH DPLL */
2280         reg = PCH_DPLL(pipe);
2281         temp = I915_READ(reg);
2282         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2283
2284         /* Switch from PCDclk to Rawclk */
2285         reg = FDI_RX_CTL(pipe);
2286         temp = I915_READ(reg);
2287         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2288
2289         /* Disable CPU FDI TX PLL */
2290         reg = FDI_TX_CTL(pipe);
2291         temp = I915_READ(reg);
2292         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2293
2294         POSTING_READ(reg);
2295         udelay(100);
2296
2297         reg = FDI_RX_CTL(pipe);
2298         temp = I915_READ(reg);
2299         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2300
2301         /* Wait for the clocks to turn off. */
2302         POSTING_READ(reg);
2303         udelay(100);
2304
2305         intel_crtc->active = false;
2306         intel_update_watermarks(dev);
2307         intel_update_fbc(dev);
2308         intel_clear_scanline_wait(dev);
2309 }
2310
2311 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2312 {
2313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314         int pipe = intel_crtc->pipe;
2315         int plane = intel_crtc->plane;
2316
2317         /* XXX: When our outputs are all unaware of DPMS modes other than off
2318          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2319          */
2320         switch (mode) {
2321         case DRM_MODE_DPMS_ON:
2322         case DRM_MODE_DPMS_STANDBY:
2323         case DRM_MODE_DPMS_SUSPEND:
2324                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2325                 ironlake_crtc_enable(crtc);
2326                 break;
2327
2328         case DRM_MODE_DPMS_OFF:
2329                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2330                 ironlake_crtc_disable(crtc);
2331                 break;
2332         }
2333 }
2334
2335 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2336 {
2337         if (!enable && intel_crtc->overlay) {
2338                 struct drm_device *dev = intel_crtc->base.dev;
2339
2340                 mutex_lock(&dev->struct_mutex);
2341                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2342                 mutex_unlock(&dev->struct_mutex);
2343         }
2344
2345         /* Let userspace switch the overlay on again. In most cases userspace
2346          * has to recompute where to put it anyway.
2347          */
2348 }
2349
2350 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2351 {
2352         struct drm_device *dev = crtc->dev;
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355         int pipe = intel_crtc->pipe;
2356         int plane = intel_crtc->plane;
2357         u32 reg, temp;
2358
2359         if (intel_crtc->active)
2360                 return;
2361
2362         intel_crtc->active = true;
2363         intel_update_watermarks(dev);
2364
2365         /* Enable the DPLL */
2366         reg = DPLL(pipe);
2367         temp = I915_READ(reg);
2368         if ((temp & DPLL_VCO_ENABLE) == 0) {
2369                 I915_WRITE(reg, temp);
2370
2371                 /* Wait for the clocks to stabilize. */
2372                 POSTING_READ(reg);
2373                 udelay(150);
2374
2375                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2376
2377                 /* Wait for the clocks to stabilize. */
2378                 POSTING_READ(reg);
2379                 udelay(150);
2380
2381                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2382
2383                 /* Wait for the clocks to stabilize. */
2384                 POSTING_READ(reg);
2385                 udelay(150);
2386         }
2387
2388         /* Enable the pipe */
2389         reg = PIPECONF(pipe);
2390         temp = I915_READ(reg);
2391         if ((temp & PIPECONF_ENABLE) == 0)
2392                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2393
2394         /* Enable the plane */
2395         reg = DSPCNTR(plane);
2396         temp = I915_READ(reg);
2397         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2398                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2399                 intel_flush_display_plane(dev, plane);
2400         }
2401
2402         intel_crtc_load_lut(crtc);
2403         intel_update_fbc(dev);
2404
2405         /* Give the overlay scaler a chance to enable if it's on this pipe */
2406         intel_crtc_dpms_overlay(intel_crtc, true);
2407         intel_crtc_update_cursor(crtc, true);
2408 }
2409
2410 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2411 {
2412         struct drm_device *dev = crtc->dev;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415         int pipe = intel_crtc->pipe;
2416         int plane = intel_crtc->plane;
2417         u32 reg, temp;
2418
2419         if (!intel_crtc->active)
2420                 return;
2421
2422         /* Give the overlay scaler a chance to disable if it's on this pipe */
2423         intel_crtc_wait_for_pending_flips(crtc);
2424         drm_vblank_off(dev, pipe);
2425         intel_crtc_dpms_overlay(intel_crtc, false);
2426         intel_crtc_update_cursor(crtc, false);
2427
2428         if (dev_priv->cfb_plane == plane &&
2429             dev_priv->display.disable_fbc)
2430                 dev_priv->display.disable_fbc(dev);
2431
2432         /* Disable display plane */
2433         reg = DSPCNTR(plane);
2434         temp = I915_READ(reg);
2435         if (temp & DISPLAY_PLANE_ENABLE) {
2436                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2437                 /* Flush the plane changes */
2438                 intel_flush_display_plane(dev, plane);
2439
2440                 /* Wait for vblank for the disable to take effect */
2441                 if (IS_GEN2(dev))
2442                         intel_wait_for_vblank(dev, pipe);
2443         }
2444
2445         /* Don't disable pipe A or pipe A PLLs if needed */
2446         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2447                 goto done;
2448
2449         /* Next, disable display pipes */
2450         reg = PIPECONF(pipe);
2451         temp = I915_READ(reg);
2452         if (temp & PIPECONF_ENABLE) {
2453                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2454
2455                 /* Wait for the pipe to turn off */
2456                 POSTING_READ(reg);
2457                 intel_wait_for_pipe_off(dev, pipe);
2458         }
2459
2460         reg = DPLL(pipe);
2461         temp = I915_READ(reg);
2462         if (temp & DPLL_VCO_ENABLE) {
2463                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2464
2465                 /* Wait for the clocks to turn off. */
2466                 POSTING_READ(reg);
2467                 udelay(150);
2468         }
2469
2470 done:
2471         intel_crtc->active = false;
2472         intel_update_fbc(dev);
2473         intel_update_watermarks(dev);
2474         intel_clear_scanline_wait(dev);
2475 }
2476
2477 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2478 {
2479         /* XXX: When our outputs are all unaware of DPMS modes other than off
2480          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2481          */
2482         switch (mode) {
2483         case DRM_MODE_DPMS_ON:
2484         case DRM_MODE_DPMS_STANDBY:
2485         case DRM_MODE_DPMS_SUSPEND:
2486                 i9xx_crtc_enable(crtc);
2487                 break;
2488         case DRM_MODE_DPMS_OFF:
2489                 i9xx_crtc_disable(crtc);
2490                 break;
2491         }
2492 }
2493
2494 /**
2495  * Sets the power management mode of the pipe and plane.
2496  */
2497 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2498 {
2499         struct drm_device *dev = crtc->dev;
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501         struct drm_i915_master_private *master_priv;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         int pipe = intel_crtc->pipe;
2504         bool enabled;
2505
2506         if (intel_crtc->dpms_mode == mode)
2507                 return;
2508
2509         intel_crtc->dpms_mode = mode;
2510
2511         dev_priv->display.dpms(crtc, mode);
2512
2513         if (!dev->primary->master)
2514                 return;
2515
2516         master_priv = dev->primary->master->driver_priv;
2517         if (!master_priv->sarea_priv)
2518                 return;
2519
2520         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2521
2522         switch (pipe) {
2523         case 0:
2524                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2525                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2526                 break;
2527         case 1:
2528                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2529                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2530                 break;
2531         default:
2532                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2533                 break;
2534         }
2535 }
2536
2537 static void intel_crtc_disable(struct drm_crtc *crtc)
2538 {
2539         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2540         struct drm_device *dev = crtc->dev;
2541
2542         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2543
2544         if (crtc->fb) {
2545                 mutex_lock(&dev->struct_mutex);
2546                 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2547                 mutex_unlock(&dev->struct_mutex);
2548         }
2549 }
2550
2551 /* Prepare for a mode set.
2552  *
2553  * Note we could be a lot smarter here.  We need to figure out which outputs
2554  * will be enabled, which disabled (in short, how the config will changes)
2555  * and perform the minimum necessary steps to accomplish that, e.g. updating
2556  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2557  * panel fitting is in the proper state, etc.
2558  */
2559 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2560 {
2561         i9xx_crtc_disable(crtc);
2562 }
2563
2564 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2565 {
2566         i9xx_crtc_enable(crtc);
2567 }
2568
2569 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2570 {
2571         ironlake_crtc_disable(crtc);
2572 }
2573
2574 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2575 {
2576         ironlake_crtc_enable(crtc);
2577 }
2578
2579 void intel_encoder_prepare (struct drm_encoder *encoder)
2580 {
2581         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2582         /* lvds has its own version of prepare see intel_lvds_prepare */
2583         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2584 }
2585
2586 void intel_encoder_commit (struct drm_encoder *encoder)
2587 {
2588         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2589         /* lvds has its own version of commit see intel_lvds_commit */
2590         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2591 }
2592
2593 void intel_encoder_destroy(struct drm_encoder *encoder)
2594 {
2595         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2596
2597         drm_encoder_cleanup(encoder);
2598         kfree(intel_encoder);
2599 }
2600
2601 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2602                                   struct drm_display_mode *mode,
2603                                   struct drm_display_mode *adjusted_mode)
2604 {
2605         struct drm_device *dev = crtc->dev;
2606
2607         if (HAS_PCH_SPLIT(dev)) {
2608                 /* FDI link clock is fixed at 2.7G */
2609                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2610                         return false;
2611         }
2612
2613         /* XXX some encoders set the crtcinfo, others don't.
2614          * Obviously we need some form of conflict resolution here...
2615          */
2616         if (adjusted_mode->crtc_htotal == 0)
2617                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2618
2619         return true;
2620 }
2621
2622 static int i945_get_display_clock_speed(struct drm_device *dev)
2623 {
2624         return 400000;
2625 }
2626
2627 static int i915_get_display_clock_speed(struct drm_device *dev)
2628 {
2629         return 333000;
2630 }
2631
2632 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2633 {
2634         return 200000;
2635 }
2636
2637 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2638 {
2639         u16 gcfgc = 0;
2640
2641         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2642
2643         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2644                 return 133000;
2645         else {
2646                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2647                 case GC_DISPLAY_CLOCK_333_MHZ:
2648                         return 333000;
2649                 default:
2650                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2651                         return 190000;
2652                 }
2653         }
2654 }
2655
2656 static int i865_get_display_clock_speed(struct drm_device *dev)
2657 {
2658         return 266000;
2659 }
2660
2661 static int i855_get_display_clock_speed(struct drm_device *dev)
2662 {
2663         u16 hpllcc = 0;
2664         /* Assume that the hardware is in the high speed state.  This
2665          * should be the default.
2666          */
2667         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2668         case GC_CLOCK_133_200:
2669         case GC_CLOCK_100_200:
2670                 return 200000;
2671         case GC_CLOCK_166_250:
2672                 return 250000;
2673         case GC_CLOCK_100_133:
2674                 return 133000;
2675         }
2676
2677         /* Shouldn't happen */
2678         return 0;
2679 }
2680
2681 static int i830_get_display_clock_speed(struct drm_device *dev)
2682 {
2683         return 133000;
2684 }
2685
2686 struct fdi_m_n {
2687         u32        tu;
2688         u32        gmch_m;
2689         u32        gmch_n;
2690         u32        link_m;
2691         u32        link_n;
2692 };
2693
2694 static void
2695 fdi_reduce_ratio(u32 *num, u32 *den)
2696 {
2697         while (*num > 0xffffff || *den > 0xffffff) {
2698                 *num >>= 1;
2699                 *den >>= 1;
2700         }
2701 }
2702
2703 #define DATA_N 0x800000
2704 #define LINK_N 0x80000
2705
2706 static void
2707 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2708                      int link_clock, struct fdi_m_n *m_n)
2709 {
2710         u64 temp;
2711
2712         m_n->tu = 64; /* default size */
2713
2714         temp = (u64) DATA_N * pixel_clock;
2715         temp = div_u64(temp, link_clock);
2716         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2717         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2718         m_n->gmch_n = DATA_N;
2719         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2720
2721         temp = (u64) LINK_N * pixel_clock;
2722         m_n->link_m = div_u64(temp, link_clock);
2723         m_n->link_n = LINK_N;
2724         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2725 }
2726
2727
2728 struct intel_watermark_params {
2729         unsigned long fifo_size;
2730         unsigned long max_wm;
2731         unsigned long default_wm;
2732         unsigned long guard_size;
2733         unsigned long cacheline_size;
2734 };
2735
2736 /* Pineview has different values for various configs */
2737 static struct intel_watermark_params pineview_display_wm = {
2738         PINEVIEW_DISPLAY_FIFO,
2739         PINEVIEW_MAX_WM,
2740         PINEVIEW_DFT_WM,
2741         PINEVIEW_GUARD_WM,
2742         PINEVIEW_FIFO_LINE_SIZE
2743 };
2744 static struct intel_watermark_params pineview_display_hplloff_wm = {
2745         PINEVIEW_DISPLAY_FIFO,
2746         PINEVIEW_MAX_WM,
2747         PINEVIEW_DFT_HPLLOFF_WM,
2748         PINEVIEW_GUARD_WM,
2749         PINEVIEW_FIFO_LINE_SIZE
2750 };
2751 static struct intel_watermark_params pineview_cursor_wm = {
2752         PINEVIEW_CURSOR_FIFO,
2753         PINEVIEW_CURSOR_MAX_WM,
2754         PINEVIEW_CURSOR_DFT_WM,
2755         PINEVIEW_CURSOR_GUARD_WM,
2756         PINEVIEW_FIFO_LINE_SIZE,
2757 };
2758 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2759         PINEVIEW_CURSOR_FIFO,
2760         PINEVIEW_CURSOR_MAX_WM,
2761         PINEVIEW_CURSOR_DFT_WM,
2762         PINEVIEW_CURSOR_GUARD_WM,
2763         PINEVIEW_FIFO_LINE_SIZE
2764 };
2765 static struct intel_watermark_params g4x_wm_info = {
2766         G4X_FIFO_SIZE,
2767         G4X_MAX_WM,
2768         G4X_MAX_WM,
2769         2,
2770         G4X_FIFO_LINE_SIZE,
2771 };
2772 static struct intel_watermark_params g4x_cursor_wm_info = {
2773         I965_CURSOR_FIFO,
2774         I965_CURSOR_MAX_WM,
2775         I965_CURSOR_DFT_WM,
2776         2,
2777         G4X_FIFO_LINE_SIZE,
2778 };
2779 static struct intel_watermark_params i965_cursor_wm_info = {
2780         I965_CURSOR_FIFO,
2781         I965_CURSOR_MAX_WM,
2782         I965_CURSOR_DFT_WM,
2783         2,
2784         I915_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params i945_wm_info = {
2787         I945_FIFO_SIZE,
2788         I915_MAX_WM,
2789         1,
2790         2,
2791         I915_FIFO_LINE_SIZE
2792 };
2793 static struct intel_watermark_params i915_wm_info = {
2794         I915_FIFO_SIZE,
2795         I915_MAX_WM,
2796         1,
2797         2,
2798         I915_FIFO_LINE_SIZE
2799 };
2800 static struct intel_watermark_params i855_wm_info = {
2801         I855GM_FIFO_SIZE,
2802         I915_MAX_WM,
2803         1,
2804         2,
2805         I830_FIFO_LINE_SIZE
2806 };
2807 static struct intel_watermark_params i830_wm_info = {
2808         I830_FIFO_SIZE,
2809         I915_MAX_WM,
2810         1,
2811         2,
2812         I830_FIFO_LINE_SIZE
2813 };
2814
2815 static struct intel_watermark_params ironlake_display_wm_info = {
2816         ILK_DISPLAY_FIFO,
2817         ILK_DISPLAY_MAXWM,
2818         ILK_DISPLAY_DFTWM,
2819         2,
2820         ILK_FIFO_LINE_SIZE
2821 };
2822
2823 static struct intel_watermark_params ironlake_cursor_wm_info = {
2824         ILK_CURSOR_FIFO,
2825         ILK_CURSOR_MAXWM,
2826         ILK_CURSOR_DFTWM,
2827         2,
2828         ILK_FIFO_LINE_SIZE
2829 };
2830
2831 static struct intel_watermark_params ironlake_display_srwm_info = {
2832         ILK_DISPLAY_SR_FIFO,
2833         ILK_DISPLAY_MAX_SRWM,
2834         ILK_DISPLAY_DFT_SRWM,
2835         2,
2836         ILK_FIFO_LINE_SIZE
2837 };
2838
2839 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2840         ILK_CURSOR_SR_FIFO,
2841         ILK_CURSOR_MAX_SRWM,
2842         ILK_CURSOR_DFT_SRWM,
2843         2,
2844         ILK_FIFO_LINE_SIZE
2845 };
2846
2847 /**
2848  * intel_calculate_wm - calculate watermark level
2849  * @clock_in_khz: pixel clock
2850  * @wm: chip FIFO params
2851  * @pixel_size: display pixel size
2852  * @latency_ns: memory latency for the platform
2853  *
2854  * Calculate the watermark level (the level at which the display plane will
2855  * start fetching from memory again).  Each chip has a different display
2856  * FIFO size and allocation, so the caller needs to figure that out and pass
2857  * in the correct intel_watermark_params structure.
2858  *
2859  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2860  * on the pixel size.  When it reaches the watermark level, it'll start
2861  * fetching FIFO line sized based chunks from memory until the FIFO fills
2862  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2863  * will occur, and a display engine hang could result.
2864  */
2865 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2866                                         struct intel_watermark_params *wm,
2867                                         int pixel_size,
2868                                         unsigned long latency_ns)
2869 {
2870         long entries_required, wm_size;
2871
2872         /*
2873          * Note: we need to make sure we don't overflow for various clock &
2874          * latency values.
2875          * clocks go from a few thousand to several hundred thousand.
2876          * latency is usually a few thousand
2877          */
2878         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2879                 1000;
2880         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2881
2882         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2883
2884         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2885
2886         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2887
2888         /* Don't promote wm_size to unsigned... */
2889         if (wm_size > (long)wm->max_wm)
2890                 wm_size = wm->max_wm;
2891         if (wm_size <= 0)
2892                 wm_size = wm->default_wm;
2893         return wm_size;
2894 }
2895
2896 struct cxsr_latency {
2897         int is_desktop;
2898         int is_ddr3;
2899         unsigned long fsb_freq;
2900         unsigned long mem_freq;
2901         unsigned long display_sr;
2902         unsigned long display_hpll_disable;
2903         unsigned long cursor_sr;
2904         unsigned long cursor_hpll_disable;
2905 };
2906
2907 static const struct cxsr_latency cxsr_latency_table[] = {
2908         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2909         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2910         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2911         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2912         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2913
2914         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2915         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2916         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2917         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2918         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2919
2920         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2921         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2922         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2923         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2924         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2925
2926         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2927         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2928         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2929         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2930         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2931
2932         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2933         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2934         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2935         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2936         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2937
2938         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2939         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2940         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2941         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2942         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2943 };
2944
2945 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2946                                                          int is_ddr3,
2947                                                          int fsb,
2948                                                          int mem)
2949 {
2950         const struct cxsr_latency *latency;
2951         int i;
2952
2953         if (fsb == 0 || mem == 0)
2954                 return NULL;
2955
2956         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2957                 latency = &cxsr_latency_table[i];
2958                 if (is_desktop == latency->is_desktop &&
2959                     is_ddr3 == latency->is_ddr3 &&
2960                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2961                         return latency;
2962         }
2963
2964         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2965
2966         return NULL;
2967 }
2968
2969 static void pineview_disable_cxsr(struct drm_device *dev)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972
2973         /* deactivate cxsr */
2974         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2975 }
2976
2977 /*
2978  * Latency for FIFO fetches is dependent on several factors:
2979  *   - memory configuration (speed, channels)
2980  *   - chipset
2981  *   - current MCH state
2982  * It can be fairly high in some situations, so here we assume a fairly
2983  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2984  * set this value too high, the FIFO will fetch frequently to stay full)
2985  * and power consumption (set it too low to save power and we might see
2986  * FIFO underruns and display "flicker").
2987  *
2988  * A value of 5us seems to be a good balance; safe for very low end
2989  * platforms but not overly aggressive on lower latency configs.
2990  */
2991 static const int latency_ns = 5000;
2992
2993 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         uint32_t dsparb = I915_READ(DSPARB);
2997         int size;
2998
2999         size = dsparb & 0x7f;
3000         if (plane)
3001                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3002
3003         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3004                       plane ? "B" : "A", size);
3005
3006         return size;
3007 }
3008
3009 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3010 {
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         uint32_t dsparb = I915_READ(DSPARB);
3013         int size;
3014
3015         size = dsparb & 0x1ff;
3016         if (plane)
3017                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3018         size >>= 1; /* Convert to cachelines */
3019
3020         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3021                       plane ? "B" : "A", size);
3022
3023         return size;
3024 }
3025
3026 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3027 {
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         uint32_t dsparb = I915_READ(DSPARB);
3030         int size;
3031
3032         size = dsparb & 0x7f;
3033         size >>= 2; /* Convert to cachelines */
3034
3035         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3036                       plane ? "B" : "A",
3037                       size);
3038
3039         return size;
3040 }
3041
3042 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3043 {
3044         struct drm_i915_private *dev_priv = dev->dev_private;
3045         uint32_t dsparb = I915_READ(DSPARB);
3046         int size;
3047
3048         size = dspa