drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "i915_drm.h"
  30 #include "intel_drv.h"
  31
  32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  33 {
  34         struct drm_i915_private *dev_priv = dev->dev_private;
  35         u32     dpll_reg;
  36
  37         if (HAS_PCH_SPLIT(dev))
  38                 dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
  39         else
  40                 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
  41
  42         return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
  43 }
  44
  45 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  46 {
  47         struct drm_i915_private *dev_priv = dev->dev_private;
  48         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  49         u32 *array;
  50         int i;
  51
  52         if (!i915_pipe_enabled(dev, pipe))
  53                 return;
  54
  55         if (HAS_PCH_SPLIT(dev))
  56                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  57
  58         if (pipe == PIPE_A)
  59                 array = dev_priv->save_palette_a;
  60         else
  61                 array = dev_priv->save_palette_b;
  62
  63         for(i = 0; i < 256; i++)
  64                 array[i] = I915_READ(reg + (i << 2));
  65 }
  66
  67 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  68 {
  69         struct drm_i915_private *dev_priv = dev->dev_private;
  70         unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
  71         u32 *array;
  72         int i;
  73
  74         if (!i915_pipe_enabled(dev, pipe))
  75                 return;
  76
  77         if (HAS_PCH_SPLIT(dev))
  78                 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
  79
  80         if (pipe == PIPE_A)
  81                 array = dev_priv->save_palette_a;
  82         else
  83                 array = dev_priv->save_palette_b;
  84
  85         for(i = 0; i < 256; i++)
  86                 I915_WRITE(reg + (i << 2), array[i]);
  87 }
  88
  89 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  90 {
  91         struct drm_i915_private *dev_priv = dev->dev_private;
  92
  93         I915_WRITE8(index_port, reg);
  94         return I915_READ8(data_port);
  95 }
  96
  97 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
  98 {
  99         struct drm_i915_private *dev_priv = dev->dev_private;
 100
 101         I915_READ8(st01);
 102         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 103         return I915_READ8(VGA_AR_DATA_READ);
 104 }
 105
 106 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
 107 {
 108         struct drm_i915_private *dev_priv = dev->dev_private;
 109
 110         I915_READ8(st01);
 111         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 112         I915_WRITE8(VGA_AR_DATA_WRITE, val);
 113 }
 114
 115 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118
 119         I915_WRITE8(index_port, reg);
 120         I915_WRITE8(data_port, val);
 121 }
 122
 123 static void i915_save_vga(struct drm_device *dev)
 124 {
 125         struct drm_i915_private *dev_priv = dev->dev_private;
 126         int i;
 127         u16 cr_index, cr_data, st01;
 128
 129         /* VGA color palette registers */
 130         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
 131
 132         /* MSR bits */
 133         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
 134         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 135                 cr_index = VGA_CR_INDEX_CGA;
 136                 cr_data = VGA_CR_DATA_CGA;
 137                 st01 = VGA_ST01_CGA;
 138         } else {
 139                 cr_index = VGA_CR_INDEX_MDA;
 140                 cr_data = VGA_CR_DATA_MDA;
 141                 st01 = VGA_ST01_MDA;
 142         }
 143
 144         /* CRT controller regs */
 145         i915_write_indexed(dev, cr_index, cr_data, 0x11,
 146                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
 147                            (~0x80));
 148         for (i = 0; i <= 0x24; i++)
 149                 dev_priv->saveCR[i] =
 150                         i915_read_indexed(dev, cr_index, cr_data, i);
 151         /* Make sure we don't turn off CR group 0 writes */
 152         dev_priv->saveCR[0x11] &= ~0x80;
 153
 154         /* Attribute controller registers */
 155         I915_READ8(st01);
 156         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
 157         for (i = 0; i <= 0x14; i++)
 158                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
 159         I915_READ8(st01);
 160         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
 161         I915_READ8(st01);
 162
 163         /* Graphics controller registers */
 164         for (i = 0; i < 9; i++)
 165                 dev_priv->saveGR[i] =
 166                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
 167
 168         dev_priv->saveGR[0x10] =
 169                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 170         dev_priv->saveGR[0x11] =
 171                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 172         dev_priv->saveGR[0x18] =
 173                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 174
 175         /* Sequencer registers */
 176         for (i = 0; i < 8; i++)
 177                 dev_priv->saveSR[i] =
 178                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
 179 }
 180
 181 static void i915_restore_vga(struct drm_device *dev)
 182 {
 183         struct drm_i915_private *dev_priv = dev->dev_private;
 184         int i;
 185         u16 cr_index, cr_data, st01;
 186
 187         /* MSR bits */
 188         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
 189         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 190                 cr_index = VGA_CR_INDEX_CGA;
 191                 cr_data = VGA_CR_DATA_CGA;
 192                 st01 = VGA_ST01_CGA;
 193         } else {
 194                 cr_index = VGA_CR_INDEX_MDA;
 195                 cr_data = VGA_CR_DATA_MDA;
 196                 st01 = VGA_ST01_MDA;
 197         }
 198
 199         /* Sequencer registers, don't write SR07 */
 200         for (i = 0; i < 7; i++)
 201                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
 202                                    dev_priv->saveSR[i]);
 203
 204         /* CRT controller regs */
 205         /* Enable CR group 0 writes */
 206         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 207         for (i = 0; i <= 0x24; i++)
 208                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
 209
 210         /* Graphics controller regs */
 211         for (i = 0; i < 9; i++)
 212                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
 213                                    dev_priv->saveGR[i]);
 214
 215         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 216                            dev_priv->saveGR[0x10]);
 217         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 218                            dev_priv->saveGR[0x11]);
 219         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 220                            dev_priv->saveGR[0x18]);
 221
 222         /* Attribute controller registers */
 223         I915_READ8(st01); /* switch back to index mode */
 224         for (i = 0; i <= 0x14; i++)
 225                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
 226         I915_READ8(st01); /* switch back to index mode */
 227         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
 228         I915_READ8(st01);
 229
 230         /* VGA color palette registers */
 231         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 232 }
 233
 234 static void i915_save_modeset_reg(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         int i;
 238
 239         if (drm_core_check_feature(dev, DRIVER_MODESET))
 240                 return;
 241
 242         /* Cursor state */
 243         dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
 244         dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
 245         dev_priv->saveCURABASE = I915_READ(_CURABASE);
 246         dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
 247         dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
 248         dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
 249         if (IS_GEN2(dev))
 250                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 251
 252         if (HAS_PCH_SPLIT(dev)) {
 253                 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 254                 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 255         }
 256
 257         /* Pipe & plane A info */
 258         dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
 259         dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
 260         if (HAS_PCH_SPLIT(dev)) {
 261                 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
 262                 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
 263                 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
 264         } else {
 265                 dev_priv->saveFPA0 = I915_READ(_FPA0);
 266                 dev_priv->saveFPA1 = I915_READ(_FPA1);
 267                 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
 268         }
 269         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 270                 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
 271         dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
 272         dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
 273         dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
 274         dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
 275         dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
 276         dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
 277         if (!HAS_PCH_SPLIT(dev))
 278                 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
 279
 280         if (HAS_PCH_SPLIT(dev)) {
 281                 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
 282                 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
 283                 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
 284                 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
 285
 286                 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
 287                 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
 288
 289                 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
 290                 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
 291                 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
 292
 293                 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
 294                 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
 295                 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
 296                 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
 297                 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
 298                 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
 299                 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
 300         }
 301
 302         dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
 303         dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
 304         dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
 305         dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
 306         dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
 307         if (INTEL_INFO(dev)->gen >= 4) {
 308                 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
 309                 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
 310         }
 311         i915_save_palette(dev, PIPE_A);
 312         dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
 313
 314         /* Pipe & plane B info */
 315         dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
 316         dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
 317         if (HAS_PCH_SPLIT(dev)) {
 318                 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
 319                 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
 320                 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
 321         } else {
 322                 dev_priv->saveFPB0 = I915_READ(_FPB0);
 323                 dev_priv->saveFPB1 = I915_READ(_FPB1);
 324                 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
 325         }
 326         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 327                 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
 328         dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
 329         dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
 330         dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
 331         dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
 332         dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
 333         dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
 334         if (!HAS_PCH_SPLIT(dev))
 335                 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
 336
 337         if (HAS_PCH_SPLIT(dev)) {
 338                 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
 339                 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
 340                 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
 341                 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
 342
 343                 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
 344                 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
 345
 346                 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
 347                 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
 348                 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
 349
 350                 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
 351                 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
 352                 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
 353                 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
 354                 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
 355                 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
 356                 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
 357         }
 358
 359         dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
 360         dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
 361         dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
 362         dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
 363         dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
 364         if (INTEL_INFO(dev)->gen >= 4) {
 365                 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
 366                 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
 367         }
 368         i915_save_palette(dev, PIPE_B);
 369         dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
 370
 371         /* Fences */
 372         switch (INTEL_INFO(dev)->gen) {
 373         case 6:
 374                 for (i = 0; i < 16; i++)
 375                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 376                 break;
 377         case 5:
 378         case 4:
 379                 for (i = 0; i < 16; i++)
 380                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 381                 break;
 382         case 3:
 383                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 384                         for (i = 0; i < 8; i++)
 385                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 386         case 2:
 387                 for (i = 0; i < 8; i++)
 388                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 389                 break;
 390         }
 391
 392         return;
 393 }
 394
 395 static void i915_restore_modeset_reg(struct drm_device *dev)
 396 {
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         int dpll_a_reg, fpa0_reg, fpa1_reg;
 399         int dpll_b_reg, fpb0_reg, fpb1_reg;
 400         int i;
 401
 402         if (drm_core_check_feature(dev, DRIVER_MODESET))
 403                 return;
 404
 405         /* Fences */
 406         switch (INTEL_INFO(dev)->gen) {
 407         case 6:
 408                 for (i = 0; i < 16; i++)
 409                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
 410                 break;
 411         case 5:
 412         case 4:
 413                 for (i = 0; i < 16; i++)
 414                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
 415                 break;
 416         case 3:
 417         case 2:
 418                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 419                         for (i = 0; i < 8; i++)
 420                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
 421                 for (i = 0; i < 8; i++)
 422                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
 423                 break;
 424         }
 425
 426
 427         if (HAS_PCH_SPLIT(dev)) {
 428                 dpll_a_reg = _PCH_DPLL_A;
 429                 dpll_b_reg = _PCH_DPLL_B;
 430                 fpa0_reg = _PCH_FPA0;
 431                 fpb0_reg = _PCH_FPB0;
 432                 fpa1_reg = _PCH_FPA1;
 433                 fpb1_reg = _PCH_FPB1;
 434         } else {
 435                 dpll_a_reg = _DPLL_A;
 436                 dpll_b_reg = _DPLL_B;
 437                 fpa0_reg = _FPA0;
 438                 fpb0_reg = _FPB0;
 439                 fpa1_reg = _FPA1;
 440                 fpb1_reg = _FPB1;
 441         }
 442
 443         if (HAS_PCH_SPLIT(dev)) {
 444                 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 445                 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 446         }
 447
 448         /* Pipe & plane A info */
 449         /* Prime the clock */
 450         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 451                 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
 452                            ~DPLL_VCO_ENABLE);
 453                 POSTING_READ(dpll_a_reg);
 454                 udelay(150);
 455         }
 456         I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
 457         I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
 458         /* Actually enable it */
 459         I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
 460         POSTING_READ(dpll_a_reg);
 461         udelay(150);
 462         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 463                 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 464                 POSTING_READ(_DPLL_A_MD);
 465         }
 466         udelay(150);
 467
 468         /* Restore mode */
 469         I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
 470         I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
 471         I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
 472         I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
 473         I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
 474         I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
 475         if (!HAS_PCH_SPLIT(dev))
 476                 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 477
 478         if (HAS_PCH_SPLIT(dev)) {
 479                 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 480                 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 481                 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 482                 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 483
 484                 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
 485                 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 486
 487                 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
 488                 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
 489                 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 490
 491                 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
 492                 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
 493                 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
 494                 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
 495                 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
 496                 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
 497                 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
 498         }
 499
 500         /* Restore plane info */
 501         I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
 502         I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
 503         I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
 504         I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
 505         I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 506         if (INTEL_INFO(dev)->gen >= 4) {
 507                 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
 508                 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 509         }
 510
 511         I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
 512
 513         i915_restore_palette(dev, PIPE_A);
 514         /* Enable the plane */
 515         I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
 516         I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
 517
 518         /* Pipe & plane B info */
 519         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 520                 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
 521                            ~DPLL_VCO_ENABLE);
 522                 POSTING_READ(dpll_b_reg);
 523                 udelay(150);
 524         }
 525         I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
 526         I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
 527         /* Actually enable it */
 528         I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
 529         POSTING_READ(dpll_b_reg);
 530         udelay(150);
 531         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 532                 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 533                 POSTING_READ(_DPLL_B_MD);
 534         }
 535         udelay(150);
 536
 537         /* Restore mode */
 538         I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
 539         I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
 540         I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
 541         I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
 542         I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
 543         I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
 544         if (!HAS_PCH_SPLIT(dev))
 545                 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 546
 547         if (HAS_PCH_SPLIT(dev)) {
 548                 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 549                 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 550                 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 551                 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 552
 553                 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
 554                 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 555
 556                 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
 557                 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
 558                 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 559
 560                 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
 561                 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
 562                 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
 563                 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
 564                 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
 565                 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
 566                 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
 567         }
 568
 569         /* Restore plane info */
 570         I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
 571         I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
 572         I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
 573         I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
 574         I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 575         if (INTEL_INFO(dev)->gen >= 4) {
 576                 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
 577                 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 578         }
 579
 580         I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
 581
 582         i915_restore_palette(dev, PIPE_B);
 583         /* Enable the plane */
 584         I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
 585         I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
 586
 587         /* Cursor state */
 588         I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
 589         I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
 590         I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
 591         I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
 592         I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
 593         I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
 594         if (IS_GEN2(dev))
 595                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 596
 597         return;
 598 }
 599
 600 static void i915_save_display(struct drm_device *dev)
 601 {
 602         struct drm_i915_private *dev_priv = dev->dev_private;
 603
 604         /* Display arbitration control */
 605         dev_priv->saveDSPARB = I915_READ(DSPARB);
 606
 607         /* This is only meaningful in non-KMS mode */
 608         /* Don't save them in KMS mode */
 609         i915_save_modeset_reg(dev);
 610
 611         /* CRT state */
 612         if (HAS_PCH_SPLIT(dev)) {
 613                 dev_priv->saveADPA = I915_READ(PCH_ADPA);
 614         } else {
 615                 dev_priv->saveADPA = I915_READ(ADPA);
 616         }
 617
 618         /* LVDS state */
 619         if (HAS_PCH_SPLIT(dev)) {
 620                 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
 621                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
 622                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
 623                 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
 624                 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
 625                 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
 626         } else {
 627                 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 628                 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 629                 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 630                 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
 631                 if (INTEL_INFO(dev)->gen >= 4)
 632                         dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 633                 if (IS_MOBILE(dev) && !IS_I830(dev))
 634                         dev_priv->saveLVDS = I915_READ(LVDS);
 635         }
 636
 637         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 638                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 639
 640         if (HAS_PCH_SPLIT(dev)) {
 641                 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
 642                 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
 643                 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
 644         } else {
 645                 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 646                 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 647                 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 648         }
 649
 650         /* Display Port state */
 651         if (SUPPORTS_INTEGRATED_DP(dev)) {
 652                 dev_priv->saveDP_B = I915_READ(DP_B);
 653                 dev_priv->saveDP_C = I915_READ(DP_C);
 654                 dev_priv->saveDP_D = I915_READ(DP_D);
 655                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
 656                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
 657                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
 658                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
 659                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
 660                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
 661                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
 662                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
 663         }
 664         /* FIXME: save TV & SDVO state */
 665
 666         /* Only save FBC state on the platform that supports FBC */
 667         if (I915_HAS_FBC(dev)) {
 668                 if (HAS_PCH_SPLIT(dev)) {
 669                         dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
 670                 } else if (IS_GM45(dev)) {
 671                         dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
 672                 } else {
 673                         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 674                         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 675                         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 676                         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 677                 }
 678         }
 679
 680         /* VGA state */
 681         dev_priv->saveVGA0 = I915_READ(VGA0);
 682         dev_priv->saveVGA1 = I915_READ(VGA1);
 683         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 684         if (HAS_PCH_SPLIT(dev))
 685                 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
 686         else
 687                 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 688
 689         i915_save_vga(dev);
 690 }
 691
 692 static void i915_restore_display(struct drm_device *dev)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695
 696         /* Display arbitration */
 697         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 698
 699         /* Display port ratios (must be done before clock is set) */
 700         if (SUPPORTS_INTEGRATED_DP(dev)) {
 701                 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
 702                 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
 703                 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
 704                 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
 705                 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
 706                 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
 707                 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
 708                 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
 709         }
 710
 711         /* This is only meaningful in non-KMS mode */
 712         /* Don't restore them in KMS mode */
 713         i915_restore_modeset_reg(dev);
 714
 715         /* CRT state */
 716         if (HAS_PCH_SPLIT(dev))
 717                 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
 718         else
 719                 I915_WRITE(ADPA, dev_priv->saveADPA);
 720
 721         /* LVDS state */
 722         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
 723                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 724
 725         if (HAS_PCH_SPLIT(dev)) {
 726                 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
 727         } else if (IS_MOBILE(dev) && !IS_I830(dev))
 728                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 729
 730         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
 731                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 732
 733         if (HAS_PCH_SPLIT(dev)) {
 734                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
 735                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
 736                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
 737                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
 738                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 739                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 740                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
 741                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
 742                 I915_WRITE(RSTDBYCTL,
 743                            dev_priv->saveMCHBAR_RENDER_STANDBY);
 744         } else {
 745                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 746                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 747                 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
 748                 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 749                 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 750                 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 751                 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 752         }
 753
 754         /* Display Port state */
 755         if (SUPPORTS_INTEGRATED_DP(dev)) {
 756                 I915_WRITE(DP_B, dev_priv->saveDP_B);
 757                 I915_WRITE(DP_C, dev_priv->saveDP_C);
 758                 I915_WRITE(DP_D, dev_priv->saveDP_D);
 759         }
 760         /* FIXME: restore TV & SDVO state */
 761
 762         /* only restore FBC info on the platform that supports FBC*/
 763         if (I915_HAS_FBC(dev)) {
 764                 if (HAS_PCH_SPLIT(dev)) {
 765                         ironlake_disable_fbc(dev);
 766                         I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 767                 } else if (IS_GM45(dev)) {
 768                         g4x_disable_fbc(dev);
 769                         I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
 770                 } else {
 771                         i8xx_disable_fbc(dev);
 772                         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 773                         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 774                         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 775                         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 776                 }
 777         }
 778         /* VGA state */
 779         if (HAS_PCH_SPLIT(dev))
 780                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
 781         else
 782                 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 783
 784         I915_WRITE(VGA0, dev_priv->saveVGA0);
 785         I915_WRITE(VGA1, dev_priv->saveVGA1);
 786         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 787         POSTING_READ(VGA_PD);
 788         udelay(150);
 789
 790         i915_restore_vga(dev);
 791 }
 792
 793 int i915_save_state(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         int i;
 797
 798         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 799
 800         mutex_lock(&dev->struct_mutex);
 801
 802         /* Hardware status page */
 803         dev_priv->saveHWS = I915_READ(HWS_PGA);
 804
 805         i915_save_display(dev);
 806
 807         /* Interrupt state */
 808         if (HAS_PCH_SPLIT(dev)) {
 809                 dev_priv->saveDEIER = I915_READ(DEIER);
 810                 dev_priv->saveDEIMR = I915_READ(DEIMR);
 811                 dev_priv->saveGTIER = I915_READ(GTIER);
 812                 dev_priv->saveGTIMR = I915_READ(GTIMR);
 813                 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
 814                 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
 815                 dev_priv->saveMCHBAR_RENDER_STANDBY =
 816                         I915_READ(RSTDBYCTL);
 817         } else {
 818                 dev_priv->saveIER = I915_READ(IER);
 819                 dev_priv->saveIMR = I915_READ(IMR);
 820         }
 821
 822         if (IS_IRONLAKE_M(dev))
 823                 ironlake_disable_drps(dev);
 824         if (IS_GEN6(dev))
 825                 gen6_disable_rps(dev);
 826
 827         /* Cache mode state */
 828         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 829
 830         /* Memory Arbitration state */
 831         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 832
 833         /* Scratch space */
 834         for (i = 0; i < 16; i++) {
 835                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 836                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 837         }
 838         for (i = 0; i < 3; i++)
 839                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 840
 841         mutex_unlock(&dev->struct_mutex);
 842
 843         return 0;
 844 }
 845
 846 int i915_restore_state(struct drm_device *dev)
 847 {
 848         struct drm_i915_private *dev_priv = dev->dev_private;
 849         int i;
 850
 851         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 852
 853         mutex_lock(&dev->struct_mutex);
 854
 855         /* Hardware status page */
 856         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 857
 858         i915_restore_display(dev);
 859
 860         /* Interrupt state */
 861         if (HAS_PCH_SPLIT(dev)) {
 862                 I915_WRITE(DEIER, dev_priv->saveDEIER);
 863                 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
 864                 I915_WRITE(GTIER, dev_priv->saveGTIER);
 865                 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
 866                 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
 867                 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
 868         } else {
 869                 I915_WRITE(IER, dev_priv->saveIER);
 870                 I915_WRITE(IMR, dev_priv->saveIMR);
 871         }
 872         mutex_unlock(&dev->struct_mutex);
 873
 874         intel_init_clock_gating(dev);
 875
 876         if (IS_IRONLAKE_M(dev)) {
 877                 ironlake_enable_drps(dev);
 878                 intel_init_emon(dev);
 879         }
 880
 881         if (IS_GEN6(dev))
 882                 gen6_enable_rps(dev_priv);
 883
 884         mutex_lock(&dev->struct_mutex);
 885
 886         /* Cache mode state */
 887         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 888
 889         /* Memory arbitration state */
 890         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 891
 892         for (i = 0; i < 16; i++) {
 893                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 894                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
 895         }
 896         for (i = 0; i < 3; i++)
 897                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 898
 899         mutex_unlock(&dev->struct_mutex);
 900
 901         intel_i2c_reset(dev);
 902
 903         return 0;
 904 }