drivers/gpu/drm/i915/i915_suspend.c

   1 /*
   2  *
   3  * Copyright 2008 (c) Intel Corporation
   4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "i915_drm.h"
  30 #include "i915_drv.h"
  31
  32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  33 {
  34         struct drm_i915_private *dev_priv = dev->dev_private;
  35
  36         if (pipe == PIPE_A)
  37                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  38         else
  39                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  40 }
  41
  42 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  43 {
  44         struct drm_i915_private *dev_priv = dev->dev_private;
  45         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  46         u32 *array;
  47         int i;
  48
  49         if (!i915_pipe_enabled(dev, pipe))
  50                 return;
  51
  52         if (pipe == PIPE_A)
  53                 array = dev_priv->save_palette_a;
  54         else
  55                 array = dev_priv->save_palette_b;
  56
  57         for(i = 0; i < 256; i++)
  58                 array[i] = I915_READ(reg + (i << 2));
  59 }
  60
  61 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  62 {
  63         struct drm_i915_private *dev_priv = dev->dev_private;
  64         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  65         u32 *array;
  66         int i;
  67
  68         if (!i915_pipe_enabled(dev, pipe))
  69                 return;
  70
  71         if (pipe == PIPE_A)
  72                 array = dev_priv->save_palette_a;
  73         else
  74                 array = dev_priv->save_palette_b;
  75
  76         for(i = 0; i < 256; i++)
  77                 I915_WRITE(reg + (i << 2), array[i]);
  78 }
  79
  80 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
  81 {
  82         struct drm_i915_private *dev_priv = dev->dev_private;
  83
  84         I915_WRITE8(index_port, reg);
  85         return I915_READ8(data_port);
  86 }
  87
  88 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
  89 {
  90         struct drm_i915_private *dev_priv = dev->dev_private;
  91
  92         I915_READ8(st01);
  93         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
  94         return I915_READ8(VGA_AR_DATA_READ);
  95 }
  96
  97 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
  98 {
  99         struct drm_i915_private *dev_priv = dev->dev_private;
 100
 101         I915_READ8(st01);
 102         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
 103         I915_WRITE8(VGA_AR_DATA_WRITE, val);
 104 }
 105
 106 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
 107 {
 108         struct drm_i915_private *dev_priv = dev->dev_private;
 109
 110         I915_WRITE8(index_port, reg);
 111         I915_WRITE8(data_port, val);
 112 }
 113
 114 static void i915_save_vga(struct drm_device *dev)
 115 {
 116         struct drm_i915_private *dev_priv = dev->dev_private;
 117         int i;
 118         u16 cr_index, cr_data, st01;
 119
 120         /* VGA color palette registers */
 121         dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
 122
 123         /* MSR bits */
 124         dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
 125         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 126                 cr_index = VGA_CR_INDEX_CGA;
 127                 cr_data = VGA_CR_DATA_CGA;
 128                 st01 = VGA_ST01_CGA;
 129         } else {
 130                 cr_index = VGA_CR_INDEX_MDA;
 131                 cr_data = VGA_CR_DATA_MDA;
 132                 st01 = VGA_ST01_MDA;
 133         }
 134
 135         /* CRT controller regs */
 136         i915_write_indexed(dev, cr_index, cr_data, 0x11,
 137                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
 138                            (~0x80));
 139         for (i = 0; i <= 0x24; i++)
 140                 dev_priv->saveCR[i] =
 141                         i915_read_indexed(dev, cr_index, cr_data, i);
 142         /* Make sure we don't turn off CR group 0 writes */
 143         dev_priv->saveCR[0x11] &= ~0x80;
 144
 145         /* Attribute controller registers */
 146         I915_READ8(st01);
 147         dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
 148         for (i = 0; i <= 0x14; i++)
 149                 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
 150         I915_READ8(st01);
 151         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
 152         I915_READ8(st01);
 153
 154         /* Graphics controller registers */
 155         for (i = 0; i < 9; i++)
 156                 dev_priv->saveGR[i] =
 157                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
 158
 159         dev_priv->saveGR[0x10] =
 160                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 161         dev_priv->saveGR[0x11] =
 162                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 163         dev_priv->saveGR[0x18] =
 164                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 165
 166         /* Sequencer registers */
 167         for (i = 0; i < 8; i++)
 168                 dev_priv->saveSR[i] =
 169                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
 170 }
 171
 172 static void i915_restore_vga(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         int i;
 176         u16 cr_index, cr_data, st01;
 177
 178         /* MSR bits */
 179         I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
 180         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 181                 cr_index = VGA_CR_INDEX_CGA;
 182                 cr_data = VGA_CR_DATA_CGA;
 183                 st01 = VGA_ST01_CGA;
 184         } else {
 185                 cr_index = VGA_CR_INDEX_MDA;
 186                 cr_data = VGA_CR_DATA_MDA;
 187                 st01 = VGA_ST01_MDA;
 188         }
 189
 190         /* Sequencer registers, don't write SR07 */
 191         for (i = 0; i < 7; i++)
 192                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
 193                                    dev_priv->saveSR[i]);
 194
 195         /* CRT controller regs */
 196         /* Enable CR group 0 writes */
 197         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 198         for (i = 0; i <= 0x24; i++)
 199                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
 200
 201         /* Graphics controller regs */
 202         for (i = 0; i < 9; i++)
 203                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
 204                                    dev_priv->saveGR[i]);
 205
 206         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 207                            dev_priv->saveGR[0x10]);
 208         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 209                            dev_priv->saveGR[0x11]);
 210         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 211                            dev_priv->saveGR[0x18]);
 212
 213         /* Attribute controller registers */
 214         I915_READ8(st01); /* switch back to index mode */
 215         for (i = 0; i <= 0x14; i++)
 216                 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
 217         I915_READ8(st01); /* switch back to index mode */
 218         I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
 219         I915_READ8(st01);
 220
 221         /* VGA color palette registers */
 222         I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
 223 }
 224
 225 static void i915_save_modeset_reg(struct drm_device *dev)
 226 {
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228
 229         if (drm_core_check_feature(dev, DRIVER_MODESET))
 230                 return;
 231         /* Pipe & plane A info */
 232         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 233         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 234         dev_priv->saveFPA0 = I915_READ(FPA0);
 235         dev_priv->saveFPA1 = I915_READ(FPA1);
 236         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 237         if (IS_I965G(dev))
 238                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 239         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 240         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 241         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 242         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 243         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 244         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 245         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 246
 247         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 248         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 249         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 250         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 251         dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
 252         if (IS_I965G(dev)) {
 253                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 254                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 255         }
 256         i915_save_palette(dev, PIPE_A);
 257         dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
 258
 259         /* Pipe & plane B info */
 260         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 261         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 262         dev_priv->saveFPB0 = I915_READ(FPB0);
 263         dev_priv->saveFPB1 = I915_READ(FPB1);
 264         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 265         if (IS_I965G(dev))
 266                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 267         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 268         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 269         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 270         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 271         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 272         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 273         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 274
 275         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 276         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 277         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 278         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 279         dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
 280         if (IS_I965GM(dev) || IS_GM45(dev)) {
 281                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 282                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 283         }
 284         i915_save_palette(dev, PIPE_B);
 285         dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
 286         return;
 287 }
 288 static void i915_restore_modeset_reg(struct drm_device *dev)
 289 {
 290         struct drm_i915_private *dev_priv = dev->dev_private;
 291
 292         if (drm_core_check_feature(dev, DRIVER_MODESET))
 293                 return;
 294
 295         /* Pipe & plane A info */
 296         /* Prime the clock */
 297         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 298                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 299                            ~DPLL_VCO_ENABLE);
 300                 DRM_UDELAY(150);
 301         }
 302         I915_WRITE(FPA0, dev_priv->saveFPA0);
 303         I915_WRITE(FPA1, dev_priv->saveFPA1);
 304         /* Actually enable it */
 305         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 306         DRM_UDELAY(150);
 307         if (IS_I965G(dev))
 308                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 309         DRM_UDELAY(150);
 310
 311         /* Restore mode */
 312         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 313         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 314         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 315         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 316         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 317         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 318         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 319
 320         /* Restore plane info */
 321         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 322         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 323         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 324         I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
 325         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 326         if (IS_I965G(dev)) {
 327                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 328                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 329         }
 330
 331         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 332
 333         i915_restore_palette(dev, PIPE_A);
 334         /* Enable the plane */
 335         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 336         I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
 337
 338         /* Pipe & plane B info */
 339         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 340                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 341                            ~DPLL_VCO_ENABLE);
 342                 DRM_UDELAY(150);
 343         }
 344         I915_WRITE(FPB0, dev_priv->saveFPB0);
 345         I915_WRITE(FPB1, dev_priv->saveFPB1);
 346         /* Actually enable it */
 347         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 348         DRM_UDELAY(150);
 349         if (IS_I965G(dev))
 350                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 351         DRM_UDELAY(150);
 352
 353         /* Restore mode */
 354         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 355         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 356         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 357         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 358         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 359         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 360         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 361
 362         /* Restore plane info */
 363         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 364         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 365         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 366         I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
 367         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 368         if (IS_I965G(dev)) {
 369                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 370                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 371         }
 372
 373         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 374
 375         i915_restore_palette(dev, PIPE_B);
 376         /* Enable the plane */
 377         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 378         I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
 379
 380         return;
 381 }
 382 int i915_save_state(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         int i;
 386
 387         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 388
 389         /* Render Standby */
 390         if (IS_I965G(dev) && IS_MOBILE(dev))
 391                 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
 392
 393         /* Hardware status page */
 394         dev_priv->saveHWS = I915_READ(HWS_PGA);
 395
 396         /* Display arbitration control */
 397         dev_priv->saveDSPARB = I915_READ(DSPARB);
 398
 399         /* This is only meaningful in non-KMS mode */
 400         /* Don't save them in KMS mode */
 401         i915_save_modeset_reg(dev);
 402         /* Cursor state */
 403         dev_priv->saveCURACNTR = I915_READ(CURACNTR);
 404         dev_priv->saveCURAPOS = I915_READ(CURAPOS);
 405         dev_priv->saveCURABASE = I915_READ(CURABASE);
 406         dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
 407         dev_priv->saveCURBPOS = I915_READ(CURBPOS);
 408         dev_priv->saveCURBBASE = I915_READ(CURBBASE);
 409         if (!IS_I9XX(dev))
 410                 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 411
 412         /* CRT state */
 413         dev_priv->saveADPA = I915_READ(ADPA);
 414
 415         /* LVDS state */
 416         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 417         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 418         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 419         if (IS_I965G(dev))
 420                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 421         if (IS_MOBILE(dev) && !IS_I830(dev))
 422                 dev_priv->saveLVDS = I915_READ(LVDS);
 423         if (!IS_I830(dev) && !IS_845G(dev))
 424                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 425         dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
 426         dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
 427         dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
 428
 429         /* Display Port state */
 430         if (SUPPORTS_INTEGRATED_DP(dev)) {
 431                 dev_priv->saveDP_B = I915_READ(DP_B);
 432                 dev_priv->saveDP_C = I915_READ(DP_C);
 433                 dev_priv->saveDP_D = I915_READ(DP_D);
 434                 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
 435                 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
 436                 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
 437                 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
 438                 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
 439                 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
 440                 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
 441                 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
 442         }
 443         /* FIXME: save TV & SDVO state */
 444
 445         /* FBC state */
 446         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 447         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 448         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 449         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 450
 451         /* Interrupt state */
 452         dev_priv->saveIIR = I915_READ(IIR);
 453         dev_priv->saveIER = I915_READ(IER);
 454         dev_priv->saveIMR = I915_READ(IMR);
 455
 456         /* VGA state */
 457         dev_priv->saveVGA0 = I915_READ(VGA0);
 458         dev_priv->saveVGA1 = I915_READ(VGA1);
 459         dev_priv->saveVGA_PD = I915_READ(VGA_PD);
 460         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 461
 462         /* Clock gating state */
 463         dev_priv->saveD_STATE = I915_READ(D_STATE);
 464         dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
 465
 466         /* Cache mode state */
 467         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 468
 469         /* Memory Arbitration state */
 470         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 471
 472         /* Scratch space */
 473         for (i = 0; i < 16; i++) {
 474                 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
 475                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 476         }
 477         for (i = 0; i < 3; i++)
 478                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 479
 480         /* Fences */
 481         if (IS_I965G(dev)) {
 482                 for (i = 0; i < 16; i++)
 483                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 484         } else {
 485                 for (i = 0; i < 8; i++)
 486                         dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 487
 488                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 489                         for (i = 0; i < 8; i++)
 490                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 491         }
 492         i915_save_vga(dev);
 493
 494         return 0;
 495 }
 496
 497 int i915_restore_state(struct drm_device *dev)
 498 {
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500         int i;
 501
 502         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 503
 504         /* Render Standby */
 505         if (IS_I965G(dev) && IS_MOBILE(dev))
 506                 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
 507
 508         /* Hardware status page */
 509         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 510
 511         /* Display arbitration */
 512         I915_WRITE(DSPARB, dev_priv->saveDSPARB);
 513
 514         /* Fences */
 515         if (IS_I965G(dev)) {
 516                 for (i = 0; i < 16; i++)
 517                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
 518         } else {
 519                 for (i = 0; i < 8; i++)
 520                         I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
 521                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 522                         for (i = 0; i < 8; i++)
 523                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
 524         }
 525
 526         /* Display port ratios (must be done before clock is set) */
 527         if (SUPPORTS_INTEGRATED_DP(dev)) {
 528                 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
 529                 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
 530                 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
 531                 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
 532                 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
 533                 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
 534                 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
 535                 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
 536         }
 537         /* This is only meaningful in non-KMS mode */
 538         /* Don't restore them in KMS mode */
 539         i915_restore_modeset_reg(dev);
 540         /* Cursor state */
 541         I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
 542         I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
 543         I915_WRITE(CURABASE, dev_priv->saveCURABASE);
 544         I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
 545         I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
 546         I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
 547         if (!IS_I9XX(dev))
 548                 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 549
 550         /* CRT state */
 551         I915_WRITE(ADPA, dev_priv->saveADPA);
 552
 553         /* LVDS state */
 554         if (IS_I965G(dev))
 555                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 556         if (IS_MOBILE(dev) && !IS_I830(dev))
 557                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 558         if (!IS_I830(dev) && !IS_845G(dev))
 559                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 560
 561         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 562         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 563         I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
 564         I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 565         I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
 566         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 567
 568         /* Display Port state */
 569         if (SUPPORTS_INTEGRATED_DP(dev)) {
 570                 I915_WRITE(DP_B, dev_priv->saveDP_B);
 571                 I915_WRITE(DP_C, dev_priv->saveDP_C);
 572                 I915_WRITE(DP_D, dev_priv->saveDP_D);
 573         }
 574         /* FIXME: restore TV & SDVO state */
 575
 576         /* FBC info */
 577         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 578         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 579         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 580         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 581
 582         /* VGA state */
 583         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 584         I915_WRITE(VGA0, dev_priv->saveVGA0);
 585         I915_WRITE(VGA1, dev_priv->saveVGA1);
 586         I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
 587         DRM_UDELAY(150);
 588
 589         /* Clock gating state */
 590         I915_WRITE (D_STATE, dev_priv->saveD_STATE);
 591         I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
 592
 593         /* Cache mode state */
 594         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 595
 596         /* Memory arbitration state */
 597         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 598
 599         for (i = 0; i < 16; i++) {
 600                 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
 601                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
 602         }
 603         for (i = 0; i < 3; i++)
 604                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 605
 606         i915_restore_vga(dev);
 607
 608         return 0;
 609 }
 610