1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
32 #define INTEL_GMCH_CTRL 0x52
33 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
34 #define INTEL_GMCH_ENABLED 0x4
35 #define INTEL_GMCH_MEM_MASK 0x1
36 #define INTEL_GMCH_MEM_64M 0x1
37 #define INTEL_GMCH_MEM_128M 0
39 #define INTEL_GMCH_GMS_MASK (0xf << 4)
40 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
41 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
42 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
47 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
48 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
49 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
50 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
51 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
52 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
53 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
54 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
56 #define SNB_GMCH_CTRL 0x50
57 #define SNB_GMCH_GMS_STOLEN_MASK 0xF8
58 #define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
59 #define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
60 #define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
61 #define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
62 #define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
63 #define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
64 #define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
65 #define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
66 #define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
67 #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
68 #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
69 #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
70 #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
71 #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
72 #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
73 #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
75 /* PCI config space */
77 #define HPLLCC 0xc0 /* 855 only */
78 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
79 #define GC_CLOCK_133_200 (0 << 0)
80 #define GC_CLOCK_100_200 (1 << 0)
81 #define GC_CLOCK_100_133 (2 << 0)
82 #define GC_CLOCK_166_250 (3 << 0)
84 #define GCFGC 0xf0 /* 915+ only */
85 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
86 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
87 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
88 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
89 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
90 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
91 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
92 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
93 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
94 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
95 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
96 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
97 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
98 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
99 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
100 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
101 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
102 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
103 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
104 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
105 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
106 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
107 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
110 #define GDRST_FULL (0<<2)
111 #define GDRST_RENDER (1<<2)
112 #define GDRST_MEDIA (3<<2)
116 #define VGA_ST01_MDA 0x3ba
117 #define VGA_ST01_CGA 0x3da
119 #define VGA_MSR_WRITE 0x3c2
120 #define VGA_MSR_READ 0x3cc
121 #define VGA_MSR_MEM_EN (1<<1)
122 #define VGA_MSR_CGA_MODE (1<<0)
124 #define VGA_SR_INDEX 0x3c4
125 #define VGA_SR_DATA 0x3c5
127 #define VGA_AR_INDEX 0x3c0
128 #define VGA_AR_VID_EN (1<<5)
129 #define VGA_AR_DATA_WRITE 0x3c0
130 #define VGA_AR_DATA_READ 0x3c1
132 #define VGA_GR_INDEX 0x3ce
133 #define VGA_GR_DATA 0x3cf
135 #define VGA_GR_MEM_READ_MODE_SHIFT 3
136 #define VGA_GR_MEM_READ_MODE_PLANE 1
138 #define VGA_GR_MEM_MODE_MASK 0xc
139 #define VGA_GR_MEM_MODE_SHIFT 2
140 #define VGA_GR_MEM_A0000_AFFFF 0
141 #define VGA_GR_MEM_A0000_BFFFF 1
142 #define VGA_GR_MEM_B0000_B7FFF 2
143 #define VGA_GR_MEM_B0000_BFFFF 3
145 #define VGA_DACMASK 0x3c6
146 #define VGA_DACRX 0x3c7
147 #define VGA_DACWX 0x3c8
148 #define VGA_DACDATA 0x3c9
150 #define VGA_CR_INDEX_MDA 0x3b4
151 #define VGA_CR_DATA_MDA 0x3b5
152 #define VGA_CR_INDEX_CGA 0x3d4
153 #define VGA_CR_DATA_CGA 0x3d5
156 * Memory interface instructions used by the kernel
158 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
160 #define MI_NOOP MI_INSTR(0, 0)
161 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
162 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
163 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
164 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
165 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
166 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
167 #define MI_FLUSH MI_INSTR(0x04, 0)
168 #define MI_READ_FLUSH (1 << 0)
169 #define MI_EXE_FLUSH (1 << 1)
170 #define MI_NO_WRITE_FLUSH (1 << 2)
171 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
172 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
173 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
174 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
175 #define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
176 #define MI_OVERLAY_CONTINUE (0x0<<21)
177 #define MI_OVERLAY_ON (0x1<<21)
178 #define MI_OVERLAY_OFF (0x2<<21)
179 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
180 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
181 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
182 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
183 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
184 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
185 #define MI_STORE_DWORD_INDEX_SHIFT 2
186 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
187 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
188 #define MI_BATCH_NON_SECURE (1)
189 #define MI_BATCH_NON_SECURE_I965 (1<<8)
190 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
193 * 3D instructions used by the kernel
195 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
197 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
198 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
199 #define SC_UPDATE_SCISSOR (0x1<<1)
200 #define SC_ENABLE_MASK (0x1<<0)
201 #define SC_ENABLE (0x1<<0)
202 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
203 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
204 #define SCI_YMIN_MASK (0xffff<<16)
205 #define SCI_XMIN_MASK (0xffff<<0)
206 #define SCI_YMAX_MASK (0xffff<<16)
207 #define SCI_XMAX_MASK (0xffff<<0)
208 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
209 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
210 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
211 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
212 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
213 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
214 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
215 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
216 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
217 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
218 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
219 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
220 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
221 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
222 #define BLT_DEPTH_8 (0<<24)
223 #define BLT_DEPTH_16_565 (1<<24)
224 #define BLT_DEPTH_16_1555 (2<<24)
225 #define BLT_DEPTH_32 (3<<24)
226 #define BLT_ROP_GXCOPY (0xcc<<16)
227 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
228 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
229 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
230 #define ASYNC_FLIP (1<<22)
231 #define DISPLAY_PLANE_A (0<<20)
232 #define DISPLAY_PLANE_B (1<<20)
237 #define FENCE_REG_830_0 0x2000
238 #define FENCE_REG_945_8 0x3000
239 #define I830_FENCE_START_MASK 0x07f80000
240 #define I830_FENCE_TILING_Y_SHIFT 12
241 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
242 #define I830_FENCE_PITCH_SHIFT 4
243 #define I830_FENCE_REG_VALID (1<<0)
244 #define I915_FENCE_MAX_PITCH_VAL 0x10
245 #define I830_FENCE_MAX_PITCH_VAL 6
246 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
248 #define I915_FENCE_START_MASK 0x0ff00000
249 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
251 #define FENCE_REG_965_0 0x03000
252 #define I965_FENCE_PITCH_SHIFT 2
253 #define I965_FENCE_TILING_Y_SHIFT 1
254 #define I965_FENCE_REG_VALID (1<<0)
255 #define I965_FENCE_MAX_PITCH_VAL 0x0400
257 #define FENCE_REG_SANDYBRIDGE_0 0x100000
258 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
261 * Instruction and interrupt control regs
263 #define PGTBL_ER 0x02024
264 #define PRB0_TAIL 0x02030
265 #define PRB0_HEAD 0x02034
266 #define PRB0_START 0x02038
267 #define PRB0_CTL 0x0203c
268 #define TAIL_ADDR 0x001FFFF8
269 #define HEAD_WRAP_COUNT 0xFFE00000
270 #define HEAD_WRAP_ONE 0x00200000
271 #define HEAD_ADDR 0x001FFFFC
272 #define RING_NR_PAGES 0x001FF000
273 #define RING_REPORT_MASK 0x00000006
274 #define RING_REPORT_64K 0x00000002
275 #define RING_REPORT_128K 0x00000004
276 #define RING_NO_REPORT 0x00000000
277 #define RING_VALID_MASK 0x00000001
278 #define RING_VALID 0x00000001
279 #define RING_INVALID 0x00000000
280 #define PRB1_TAIL 0x02040 /* 915+ only */
281 #define PRB1_HEAD 0x02044 /* 915+ only */
282 #define PRB1_START 0x02048 /* 915+ only */
283 #define PRB1_CTL 0x0204c /* 915+ only */
284 #define IPEIR_I965 0x02064
285 #define IPEHR_I965 0x02068
286 #define INSTDONE_I965 0x0206c
287 #define INSTPS 0x02070 /* 965+ only */
288 #define INSTDONE1 0x0207c /* 965+ only */
289 #define ACTHD_I965 0x02074
290 #define HWS_PGA 0x02080
291 #define HWS_PGA_GEN6 0x04080
292 #define HWS_ADDRESS_MASK 0xfffff000
293 #define HWS_START_ADDRESS_SHIFT 4
294 #define PWRCTXA 0x2088 /* 965GM+ only */
295 #define PWRCTX_EN (1<<0)
296 #define IPEIR 0x02088
297 #define IPEHR 0x0208c
298 #define INSTDONE 0x02090
299 #define NOPID 0x02094
300 #define HWSTAM 0x02098
302 #define MI_MODE 0x0209c
303 # define VS_TIMER_DISPATCH (1 << 6)
305 #define SCPD0 0x0209c /* 915+ only */
310 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
311 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
312 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
313 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
314 #define I915_HWB_OOM_INTERRUPT (1<<13)
315 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
316 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
317 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
318 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
319 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
320 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
321 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
322 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
323 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
324 #define I915_DEBUG_INTERRUPT (1<<2)
325 #define I915_USER_INTERRUPT (1<<1)
326 #define I915_ASLE_INTERRUPT (1<<0)
330 #define GM45_ERROR_PAGE_TABLE (1<<5)
331 #define GM45_ERROR_MEM_PRIV (1<<4)
332 #define I915_ERROR_PAGE_TABLE (1<<4)
333 #define GM45_ERROR_CP_PRIV (1<<3)
334 #define I915_ERROR_MEMORY_REFRESH (1<<1)
335 #define I915_ERROR_INSTRUCTION (1<<0)
336 #define INSTPM 0x020c0
337 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
338 #define ACTHD 0x020c8
339 #define FW_BLC 0x020d8
340 #define FW_BLC2 0x020dc
341 #define FW_BLC_SELF 0x020e0 /* 915+ only */
342 #define FW_BLC_SELF_EN_MASK (1<<31)
343 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
344 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
345 #define MM_BURST_LENGTH 0x00700000
346 #define MM_FIFO_WATERMARK 0x0001F000
347 #define LM_BURST_LENGTH 0x00000700
348 #define LM_FIFO_WATERMARK 0x0000001F
349 #define MI_ARB_STATE 0x020e4 /* 915+ only */
350 #define CACHE_MODE_0 0x02120 /* 915+ only */
351 #define CM0_MASK_SHIFT 16
352 #define CM0_IZ_OPT_DISABLE (1<<6)
353 #define CM0_ZR_OPT_DISABLE (1<<5)
354 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
355 #define CM0_COLOR_EVICT_DISABLE (1<<3)
356 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
357 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
358 #define BB_ADDR 0x02140 /* 8 bytes */
359 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
363 * Framebuffer compression (915+ only)
366 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
367 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
368 #define FBC_CONTROL 0x03208
369 #define FBC_CTL_EN (1<<31)
370 #define FBC_CTL_PERIODIC (1<<30)
371 #define FBC_CTL_INTERVAL_SHIFT (16)
372 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
373 #define FBC_CTL_C3_IDLE (1<<13)
374 #define FBC_CTL_STRIDE_SHIFT (5)
375 #define FBC_CTL_FENCENO (1<<0)
376 #define FBC_COMMAND 0x0320c
377 #define FBC_CMD_COMPRESS (1<<0)
378 #define FBC_STATUS 0x03210
379 #define FBC_STAT_COMPRESSING (1<<31)
380 #define FBC_STAT_COMPRESSED (1<<30)
381 #define FBC_STAT_MODIFIED (1<<29)
382 #define FBC_STAT_CURRENT_LINE (1<<0)
383 #define FBC_CONTROL2 0x03214
384 #define FBC_CTL_FENCE_DBL (0<<4)
385 #define FBC_CTL_IDLE_IMM (0<<2)
386 #define FBC_CTL_IDLE_FULL (1<<2)
387 #define FBC_CTL_IDLE_LINE (2<<2)
388 #define FBC_CTL_IDLE_DEBUG (3<<2)
389 #define FBC_CTL_CPU_FENCE (1<<1)
390 #define FBC_CTL_PLANEA (0<<0)
391 #define FBC_CTL_PLANEB (1<<0)
392 #define FBC_FENCE_OFF 0x0321b
393 #define FBC_TAG 0x03300
395 #define FBC_LL_SIZE (1536)
397 /* Framebuffer compression for GM45+ */
398 #define DPFC_CB_BASE 0x3200
399 #define DPFC_CONTROL 0x3208
400 #define DPFC_CTL_EN (1<<31)
401 #define DPFC_CTL_PLANEA (0<<30)
402 #define DPFC_CTL_PLANEB (1<<30)
403 #define DPFC_CTL_FENCE_EN (1<<29)
404 #define DPFC_SR_EN (1<<10)
405 #define DPFC_CTL_LIMIT_1X (0<<6)
406 #define DPFC_CTL_LIMIT_2X (1<<6)
407 #define DPFC_CTL_LIMIT_4X (2<<6)
408 #define DPFC_RECOMP_CTL 0x320c
409 #define DPFC_RECOMP_STALL_EN (1<<27)
410 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
411 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
412 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
413 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
414 #define DPFC_STATUS 0x3210
415 #define DPFC_INVAL_SEG_SHIFT (16)
416 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
417 #define DPFC_COMP_SEG_SHIFT (0)
418 #define DPFC_COMP_SEG_MASK (0x000003ff)
419 #define DPFC_STATUS2 0x3214
420 #define DPFC_FENCE_YOFF 0x3218
421 #define DPFC_CHICKEN 0x3224
422 #define DPFC_HT_MODIFY (1<<31)
435 # define GPIO_CLOCK_DIR_MASK (1 << 0)
436 # define GPIO_CLOCK_DIR_IN (0 << 1)
437 # define GPIO_CLOCK_DIR_OUT (1 << 1)
438 # define GPIO_CLOCK_VAL_MASK (1 << 2)
439 # define GPIO_CLOCK_VAL_OUT (1 << 3)
440 # define GPIO_CLOCK_VAL_IN (1 << 4)
441 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
442 # define GPIO_DATA_DIR_MASK (1 << 8)
443 # define GPIO_DATA_DIR_IN (0 << 9)
444 # define GPIO_DATA_DIR_OUT (1 << 9)
445 # define GPIO_DATA_VAL_MASK (1 << 10)
446 # define GPIO_DATA_VAL_OUT (1 << 11)
447 # define GPIO_DATA_VAL_IN (1 << 12)
448 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
450 #define GMBUS0 0x5100
451 #define GMBUS1 0x5104
452 #define GMBUS2 0x5108
453 #define GMBUS3 0x510c
454 #define GMBUS4 0x5110
455 #define GMBUS5 0x5120
458 * Clock control & power management
463 #define VGA_PD 0x6010
464 #define VGA0_PD_P2_DIV_4 (1 << 7)
465 #define VGA0_PD_P1_DIV_2 (1 << 5)
466 #define VGA0_PD_P1_SHIFT 0
467 #define VGA0_PD_P1_MASK (0x1f << 0)
468 #define VGA1_PD_P2_DIV_4 (1 << 15)
469 #define VGA1_PD_P1_DIV_2 (1 << 13)
470 #define VGA1_PD_P1_SHIFT 8
471 #define VGA1_PD_P1_MASK (0x1f << 8)
472 #define DPLL_A 0x06014
473 #define DPLL_B 0x06018
474 #define DPLL_VCO_ENABLE (1 << 31)
475 #define DPLL_DVO_HIGH_SPEED (1 << 30)
476 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
477 #define DPLL_VGA_MODE_DIS (1 << 28)
478 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
479 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
480 #define DPLL_MODE_MASK (3 << 26)
481 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
482 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
483 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
484 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
485 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
486 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
487 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
489 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
490 #define I915_CRC_ERROR_ENABLE (1UL<<29)
491 #define I915_CRC_DONE_ENABLE (1UL<<28)
492 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
493 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
494 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
495 #define I915_DPST_EVENT_ENABLE (1UL<<23)
496 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
497 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
498 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
499 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
500 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
501 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
502 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
503 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
504 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
505 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
506 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
507 #define I915_DPST_EVENT_STATUS (1UL<<7)
508 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
509 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
510 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
511 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
512 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
513 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
515 #define SRX_INDEX 0x3c4
516 #define SRX_DATA 0x3c5
518 #define SR01_SCREEN_OFF (1<<5)
521 #define PPCR_ON (1<<0)
524 #define DVOB_ON (1<<31)
526 #define DVOC_ON (1<<31)
528 #define LVDS_ON (1<<31)
531 #define ADPA_DPMS_MASK (~(3<<10))
532 #define ADPA_DPMS_ON (0<<10)
533 #define ADPA_DPMS_SUSPEND (1<<10)
534 #define ADPA_DPMS_STANDBY (2<<10)
535 #define ADPA_DPMS_OFF (3<<10)
537 #define RING_TAIL 0x00
538 #define TAIL_ADDR 0x001FFFF8
539 #define RING_HEAD 0x04
540 #define HEAD_WRAP_COUNT 0xFFE00000
541 #define HEAD_WRAP_ONE 0x00200000
542 #define HEAD_ADDR 0x001FFFFC
543 #define RING_START 0x08
544 #define START_ADDR 0xFFFFF000
545 #define RING_LEN 0x0C
546 #define RING_NR_PAGES 0x001FF000
547 #define RING_REPORT_MASK 0x00000006
548 #define RING_REPORT_64K 0x00000002
549 #define RING_REPORT_128K 0x00000004
550 #define RING_NO_REPORT 0x00000000
551 #define RING_VALID_MASK 0x00000001
552 #define RING_VALID 0x00000001
553 #define RING_INVALID 0x00000000
555 /* Scratch pad debug 0 reg:
557 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
559 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
560 * this field (only one bit may be set).
562 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
563 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
564 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
565 /* i830, required in DVO non-gang */
566 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
567 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
568 #define PLL_REF_INPUT_DREFCLK (0 << 13)
569 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
570 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
571 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
572 #define PLL_REF_INPUT_MASK (3 << 13)
573 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
575 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
576 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
577 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
578 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
579 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
582 * Parallel to Serial Load Pulse phase selection.
583 * Selects the phase for the 10X DPLL clock for the PCIe
584 * digital display port. The range is 4 to 13; 10 or more
585 * is just a flip delay. The default is 6
587 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
588 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
590 * SDVO multiplier for 945G/GM. Not used on 965.
592 #define SDVO_MULTIPLIER_MASK 0x000000ff
593 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
594 #define SDVO_MULTIPLIER_SHIFT_VGA 0
595 #define DPLL_A_MD 0x0601c /* 965+ only */
597 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
599 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
601 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
602 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
603 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
604 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
605 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
607 * SDVO/UDI pixel multiplier.
609 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
610 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
611 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
612 * dummy bytes in the datastream at an increased clock rate, with both sides of
613 * the link knowing how many bytes are fill.
615 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
616 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
617 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
618 * through an SDVO command.
620 * This register field has values of multiplication factor minus 1, with
621 * a maximum multiplier of 5 for SDVO.
623 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
624 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
626 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
627 * This best be set to the default value (3) or the CRT won't work. No,
628 * I don't entirely understand what this does...
630 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
631 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
632 #define DPLL_B_MD 0x06020 /* 965+ only */
637 #define FP_N_DIV_MASK 0x003f0000
638 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
639 #define FP_N_DIV_SHIFT 16
640 #define FP_M1_DIV_MASK 0x00003f00
641 #define FP_M1_DIV_SHIFT 8
642 #define FP_M2_DIV_MASK 0x0000003f
643 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
644 #define FP_M2_DIV_SHIFT 0
645 #define DPLL_TEST 0x606c
646 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
647 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
648 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
649 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
650 #define DPLLB_TEST_N_BYPASS (1 << 19)
651 #define DPLLB_TEST_M_BYPASS (1 << 18)
652 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
653 #define DPLLA_TEST_N_BYPASS (1 << 3)
654 #define DPLLA_TEST_M_BYPASS (1 << 2)
655 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
656 #define D_STATE 0x6104
657 #define DSTATE_PLL_D3_OFF (1<<3)
658 #define DSTATE_GFX_CLOCK_GATING (1<<1)
659 #define DSTATE_DOT_CLOCK_GATING (1<<0)
660 #define DSPCLK_GATE_D 0x6200
661 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
662 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
663 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
664 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
665 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
666 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
667 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
668 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
669 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
670 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
671 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
672 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
673 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
674 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
675 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
676 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
677 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
678 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
679 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
680 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
681 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
682 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
683 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
684 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
685 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
686 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
687 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
688 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
690 * This bit must be set on the 830 to prevent hangs when turning off the
693 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
694 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
695 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
696 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
697 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
699 #define RENCLK_GATE_D1 0x6204
700 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
701 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
702 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
703 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
704 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
705 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
706 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
707 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
708 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
709 /** This bit must be unset on 855,865 */
710 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
711 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
712 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
713 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
714 /** This bit must be set on 855,865. */
715 # define SV_CLOCK_GATE_DISABLE (1 << 0)
716 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
717 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
718 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
719 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
720 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
721 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
722 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
723 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
724 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
725 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
726 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
727 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
728 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
729 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
730 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
731 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
732 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
734 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
735 /** This bit must always be set on 965G/965GM */
736 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
737 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
738 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
739 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
740 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
741 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
742 /** This bit must always be set on 965G */
743 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
744 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
745 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
746 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
747 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
748 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
749 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
750 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
751 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
752 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
753 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
754 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
755 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
756 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
757 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
758 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
759 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
760 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
761 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
763 #define RENCLK_GATE_D2 0x6208
764 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
765 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
766 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
767 #define RAMCLK_GATE_D 0x6210 /* CRL only */
768 #define DEUC 0x6214 /* CRL only */
774 #define PALETTE_A 0x0a000
775 #define PALETTE_B 0x0a800
782 * This mirrors the MCHBAR MMIO space whose location is determined by
783 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
784 * every way. It is not accessible from the CP register read instructions.
787 #define MCHBAR_MIRROR_BASE 0x10000
789 /** 915-945 and GM965 MCH register controlling DRAM channel access */
791 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
792 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
793 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
794 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
795 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
796 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
798 /** 965 MCH register controlling DRAM channel configuration */
799 #define C0DRB3 0x10206
800 #define C1DRB3 0x10606
802 /* Clocking configuration register */
803 #define CLKCFG 0x10c00
804 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
805 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
806 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
807 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
808 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
809 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
810 /* Note, below two are guess */
811 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
812 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
813 #define CLKCFG_FSB_MASK (7 << 0)
814 #define CLKCFG_MEM_533 (1 << 4)
815 #define CLKCFG_MEM_667 (2 << 4)
816 #define CLKCFG_MEM_800 (3 << 4)
817 #define CLKCFG_MEM_MASK (7 << 4)
819 #define CRSTANDVID 0x11100
820 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
821 #define PXVFREQ_PX_MASK 0x7f000000
822 #define PXVFREQ_PX_SHIFT 24
823 #define VIDFREQ_BASE 0x11110
824 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
825 #define VIDFREQ2 0x11114
826 #define VIDFREQ3 0x11118
827 #define VIDFREQ4 0x1111c
828 #define VIDFREQ_P0_MASK 0x1f000000
829 #define VIDFREQ_P0_SHIFT 24
830 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
831 #define VIDFREQ_P0_CSCLK_SHIFT 20
832 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
833 #define VIDFREQ_P0_CRCLK_SHIFT 16
834 #define VIDFREQ_P1_MASK 0x00001f00
835 #define VIDFREQ_P1_SHIFT 8
836 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
837 #define VIDFREQ_P1_CSCLK_SHIFT 4
838 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
839 #define INTTOEXT_BASE_ILK 0x11300
840 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
841 #define INTTOEXT_MAP3_SHIFT 24
842 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
843 #define INTTOEXT_MAP2_SHIFT 16
844 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
845 #define INTTOEXT_MAP1_SHIFT 8
846 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
847 #define INTTOEXT_MAP0_SHIFT 0
848 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
849 #define MEMSWCTL 0x11170 /* Ironlake only */
850 #define MEMCTL_CMD_MASK 0xe000
851 #define MEMCTL_CMD_SHIFT 13
852 #define MEMCTL_CMD_RCLK_OFF 0
853 #define MEMCTL_CMD_RCLK_ON 1
854 #define MEMCTL_CMD_CHFREQ 2
855 #define MEMCTL_CMD_CHVID 3
856 #define MEMCTL_CMD_VMMOFF 4
857 #define MEMCTL_CMD_VMMON 5
858 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
859 when command complete */
860 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
861 #define MEMCTL_FREQ_SHIFT 8
862 #define MEMCTL_SFCAVM (1<<7)
863 #define MEMCTL_TGT_VID_MASK 0x007f
864 #define MEMIHYST 0x1117c
865 #define MEMINTREN 0x11180 /* 16 bits */
866 #define MEMINT_RSEXIT_EN (1<<8)
867 #define MEMINT_CX_SUPR_EN (1<<7)
868 #define MEMINT_CONT_BUSY_EN (1<<6)
869 #define MEMINT_AVG_BUSY_EN (1<<5)
870 #define MEMINT_EVAL_CHG_EN (1<<4)
871 #define MEMINT_MON_IDLE_EN (1<<3)
872 #define MEMINT_UP_EVAL_EN (1<<2)
873 #define MEMINT_DOWN_EVAL_EN (1<<1)
874 #define MEMINT_SW_CMD_EN (1<<0)
875 #define MEMINTRSTR 0x11182 /* 16 bits */
876 #define MEM_RSEXIT_MASK 0xc000
877 #define MEM_RSEXIT_SHIFT 14
878 #define MEM_CONT_BUSY_MASK 0x3000
879 #define MEM_CONT_BUSY_SHIFT 12
880 #define MEM_AVG_BUSY_MASK 0x0c00
881 #define MEM_AVG_BUSY_SHIFT 10
882 #define MEM_EVAL_CHG_MASK 0x0300
883 #define MEM_EVAL_BUSY_SHIFT 8
884 #define MEM_MON_IDLE_MASK 0x00c0
885 #define MEM_MON_IDLE_SHIFT 6
886 #define MEM_UP_EVAL_MASK 0x0030
887 #define MEM_UP_EVAL_SHIFT 4
888 #define MEM_DOWN_EVAL_MASK 0x000c
889 #define MEM_DOWN_EVAL_SHIFT 2
890 #define MEM_SW_CMD_MASK 0x0003
891 #define MEM_INT_STEER_GFX 0
892 #define MEM_INT_STEER_CMR 1
893 #define MEM_INT_STEER_SMI 2
894 #define MEM_INT_STEER_SCI 3
895 #define MEMINTRSTS 0x11184
896 #define MEMINT_RSEXIT (1<<7)
897 #define MEMINT_CONT_BUSY (1<<6)
898 #define MEMINT_AVG_BUSY (1<<5)
899 #define MEMINT_EVAL_CHG (1<<4)
900 #define MEMINT_MON_IDLE (1<<3)
901 #define MEMINT_UP_EVAL (1<<2)
902 #define MEMINT_DOWN_EVAL (1<<1)
903 #define MEMINT_SW_CMD (1<<0)
904 #define MEMMODECTL 0x11190
905 #define MEMMODE_BOOST_EN (1<<31)
906 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
907 #define MEMMODE_BOOST_FREQ_SHIFT 24
908 #define MEMMODE_IDLE_MODE_MASK 0x00030000
909 #define MEMMODE_IDLE_MODE_SHIFT 16
910 #define MEMMODE_IDLE_MODE_EVAL 0
911 #define MEMMODE_IDLE_MODE_CONT 1
912 #define MEMMODE_HWIDLE_EN (1<<15)
913 #define MEMMODE_SWMODE_EN (1<<14)
914 #define MEMMODE_RCLK_GATE (1<<13)
915 #define MEMMODE_HW_UPDATE (1<<12)
916 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
917 #define MEMMODE_FSTART_SHIFT 8
918 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
919 #define MEMMODE_FMAX_SHIFT 4
920 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
921 #define RCBMAXAVG 0x1119c
922 #define MEMSWCTL2 0x1119e /* Cantiga only */
923 #define SWMEMCMD_RENDER_OFF (0 << 13)
924 #define SWMEMCMD_RENDER_ON (1 << 13)
925 #define SWMEMCMD_SWFREQ (2 << 13)
926 #define SWMEMCMD_TARVID (3 << 13)
927 #define SWMEMCMD_VRM_OFF (4 << 13)
928 #define SWMEMCMD_VRM_ON (5 << 13)
929 #define CMDSTS (1<<12)
930 #define SFCAVM (1<<11)
931 #define SWFREQ_MASK 0x0380 /* P0-7 */
932 #define SWFREQ_SHIFT 7
933 #define TARVID_MASK 0x001f
934 #define MEMSTAT_CTG 0x111a0
935 #define RCBMINAVG 0x111a0
936 #define RCUPEI 0x111b0
937 #define RCDNEI 0x111b4
938 #define MCHBAR_RENDER_STANDBY 0x111b8
939 #define RCX_SW_EXIT (1<<23)
940 #define RSX_STATUS_MASK 0x00700000
941 #define VIDCTL 0x111c0
942 #define VIDSTS 0x111c8
943 #define VIDSTART 0x111cc /* 8 bits */
944 #define MEMSTAT_ILK 0x111f8
945 #define MEMSTAT_VID_MASK 0x7f00
946 #define MEMSTAT_VID_SHIFT 8
947 #define MEMSTAT_PSTATE_MASK 0x00f8
948 #define MEMSTAT_PSTATE_SHIFT 3
949 #define MEMSTAT_MON_ACTV (1<<2)
950 #define MEMSTAT_SRC_CTL_MASK 0x0003
951 #define MEMSTAT_SRC_CTL_CORE 0
952 #define MEMSTAT_SRC_CTL_TRB 1
953 #define MEMSTAT_SRC_CTL_THM 2
954 #define MEMSTAT_SRC_CTL_STDBY 3
955 #define RCPREVBSYTUPAVG 0x113b8
956 #define RCPREVBSYTDNAVG 0x113bc
957 #define PEG_BAND_GAP_DATA 0x14d68
963 #define OVADD 0x30000
964 #define DOVSTA 0x30008
965 #define OC_BUF (0x3<<20)
966 #define OGAMC5 0x30010
967 #define OGAMC4 0x30014
968 #define OGAMC3 0x30018
969 #define OGAMC2 0x3001c
970 #define OGAMC1 0x30020
971 #define OGAMC0 0x30024
974 * Display engine regs
977 /* Pipe A timing regs */
978 #define HTOTAL_A 0x60000
979 #define HBLANK_A 0x60004
980 #define HSYNC_A 0x60008
981 #define VTOTAL_A 0x6000c
982 #define VBLANK_A 0x60010
983 #define VSYNC_A 0x60014
984 #define PIPEASRC 0x6001c
985 #define BCLRPAT_A 0x60020
987 /* Pipe B timing regs */
988 #define HTOTAL_B 0x61000
989 #define HBLANK_B 0x61004
990 #define HSYNC_B 0x61008
991 #define VTOTAL_B 0x6100c
992 #define VBLANK_B 0x61010
993 #define VSYNC_B 0x61014
994 #define PIPEBSRC 0x6101c
995 #define BCLRPAT_B 0x61020
997 /* VGA port control */
999 #define ADPA_DAC_ENABLE (1<<31)
1000 #define ADPA_DAC_DISABLE 0
1001 #define ADPA_PIPE_SELECT_MASK (1<<30)
1002 #define ADPA_PIPE_A_SELECT 0
1003 #define ADPA_PIPE_B_SELECT (1<<30)
1004 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1005 #define ADPA_SETS_HVPOLARITY 0
1006 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1007 #define ADPA_VSYNC_CNTL_ENABLE 0
1008 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1009 #define ADPA_HSYNC_CNTL_ENABLE 0
1010 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1011 #define ADPA_VSYNC_ACTIVE_LOW 0
1012 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1013 #define ADPA_HSYNC_ACTIVE_LOW 0
1014 #define ADPA_DPMS_MASK (~(3<<10))
1015 #define ADPA_DPMS_ON (0<<10)
1016 #define ADPA_DPMS_SUSPEND (1<<10)
1017 #define ADPA_DPMS_STANDBY (2<<10)
1018 #define ADPA_DPMS_OFF (3<<10)
1020 /* Hotplug control (945+ only) */
1021 #define PORT_HOTPLUG_EN 0x61110
1022 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1023 #define DPB_HOTPLUG_INT_EN (1 << 29)
1024 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1025 #define DPC_HOTPLUG_INT_EN (1 << 28)
1026 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1027 #define DPD_HOTPLUG_INT_EN (1 << 27)
1028 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1029 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1030 #define TV_HOTPLUG_INT_EN (1 << 18)
1031 #define CRT_HOTPLUG_INT_EN (1 << 9)
1032 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1033 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1034 /* must use period 64 on GM45 according to docs */
1035 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1036 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1037 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1038 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1039 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1040 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1041 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1042 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1043 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1044 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1045 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1046 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1047 #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
1048 #define CRT_FORCE_HOTPLUG_MASK 0xfffffe1f
1050 #define PORT_HOTPLUG_STAT 0x61114
1051 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1052 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1053 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1054 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1055 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1056 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1057 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1058 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1059 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1060 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1061 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1062 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1063 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1064 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1066 /* SDVO port control */
1067 #define SDVOB 0x61140
1068 #define SDVOC 0x61160
1069 #define SDVO_ENABLE (1 << 31)
1070 #define SDVO_PIPE_B_SELECT (1 << 30)
1071 #define SDVO_STALL_SELECT (1 << 29)
1072 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1074 * 915G/GM SDVO pixel multiplier.
1076 * Programmed value is multiplier - 1, up to 5x.
1078 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1080 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1081 #define SDVO_PORT_MULTIPLY_SHIFT 23
1082 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1083 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1084 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1085 #define SDVOC_GANG_MODE (1 << 16)
1086 #define SDVO_ENCODING_SDVO (0x0 << 10)
1087 #define SDVO_ENCODING_HDMI (0x2 << 10)
1088 /** Requird for HDMI operation */
1089 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1090 #define SDVO_BORDER_ENABLE (1 << 7)
1091 #define SDVO_AUDIO_ENABLE (1 << 6)
1092 /** New with 965, default is to be set */
1093 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1094 /** New with 965, default is to be set */
1095 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1096 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1097 #define SDVO_DETECTED (1 << 2)
1098 /* Bits to be preserved when writing */
1099 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1100 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1102 /* DVO port control */
1103 #define DVOA 0x61120
1104 #define DVOB 0x61140
1105 #define DVOC 0x61160
1106 #define DVO_ENABLE (1 << 31)
1107 #define DVO_PIPE_B_SELECT (1 << 30)
1108 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1109 #define DVO_PIPE_STALL (1 << 28)
1110 #define DVO_PIPE_STALL_TV (2 << 28)
1111 #define DVO_PIPE_STALL_MASK (3 << 28)
1112 #define DVO_USE_VGA_SYNC (1 << 15)
1113 #define DVO_DATA_ORDER_I740 (0 << 14)
1114 #define DVO_DATA_ORDER_FP (1 << 14)
1115 #define DVO_VSYNC_DISABLE (1 << 11)
1116 #define DVO_HSYNC_DISABLE (1 << 10)
1117 #define DVO_VSYNC_TRISTATE (1 << 9)
1118 #define DVO_HSYNC_TRISTATE (1 << 8)
1119 #define DVO_BORDER_ENABLE (1 << 7)
1120 #define DVO_DATA_ORDER_GBRG (1 << 6)
1121 #define DVO_DATA_ORDER_RGGB (0 << 6)
1122 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1123 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1124 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1125 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1126 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1127 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1128 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1129 #define DVO_PRESERVE_MASK (0x7<<24)
1130 #define DVOA_SRCDIM 0x61124
1131 #define DVOB_SRCDIM 0x61144
1132 #define DVOC_SRCDIM 0x61164
1133 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1134 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1136 /* LVDS port control */
1137 #define LVDS 0x61180
1139 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1140 * the DPLL semantics change when the LVDS is assigned to that pipe.
1142 #define LVDS_PORT_EN (1 << 31)
1143 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1144 #define LVDS_PIPEB_SELECT (1 << 30)
1145 /* LVDS dithering flag on 965/g4x platform */
1146 #define LVDS_ENABLE_DITHER (1 << 25)
1147 /* Enable border for unscaled (or aspect-scaled) display */
1148 #define LVDS_BORDER_ENABLE (1 << 15)
1150 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1153 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1154 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1155 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1157 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1158 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1161 #define LVDS_A3_POWER_MASK (3 << 6)
1162 #define LVDS_A3_POWER_DOWN (0 << 6)
1163 #define LVDS_A3_POWER_UP (3 << 6)
1165 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1168 #define LVDS_CLKB_POWER_MASK (3 << 4)
1169 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1170 #define LVDS_CLKB_POWER_UP (3 << 4)
1172 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1173 * setting for whether we are in dual-channel mode. The B3 pair will
1174 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1176 #define LVDS_B0B3_POWER_MASK (3 << 2)
1177 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1178 #define LVDS_B0B3_POWER_UP (3 << 2)
1180 /* Panel power sequencing */
1181 #define PP_STATUS 0x61200
1182 #define PP_ON (1 << 31)
1184 * Indicates that all dependencies of the panel are on:
1188 * - LVDS/DVOB/DVOC on
1190 #define PP_READY (1 << 30)
1191 #define PP_SEQUENCE_NONE (0 << 28)
1192 #define PP_SEQUENCE_ON (1 << 28)
1193 #define PP_SEQUENCE_OFF (2 << 28)
1194 #define PP_SEQUENCE_MASK 0x30000000
1195 #define PP_CONTROL 0x61204
1196 #define POWER_TARGET_ON (1 << 0)
1197 #define PP_ON_DELAYS 0x61208
1198 #define PP_OFF_DELAYS 0x6120c
1199 #define PP_DIVISOR 0x61210
1202 #define PFIT_CONTROL 0x61230
1203 #define PFIT_ENABLE (1 << 31)
1204 #define PFIT_PIPE_MASK (3 << 29)
1205 #define PFIT_PIPE_SHIFT 29
1206 #define VERT_INTERP_DISABLE (0 << 10)
1207 #define VERT_INTERP_BILINEAR (1 << 10)
1208 #define VERT_INTERP_MASK (3 << 10)
1209 #define VERT_AUTO_SCALE (1 << 9)
1210 #define HORIZ_INTERP_DISABLE (0 << 6)
1211 #define HORIZ_INTERP_BILINEAR (1 << 6)
1212 #define HORIZ_INTERP_MASK (3 << 6)
1213 #define HORIZ_AUTO_SCALE (1 << 5)
1214 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1215 #define PFIT_FILTER_FUZZY (0 << 24)
1216 #define PFIT_SCALING_AUTO (0 << 26)
1217 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1218 #define PFIT_SCALING_PILLAR (2 << 26)
1219 #define PFIT_SCALING_LETTER (3 << 26)
1220 #define PFIT_PGM_RATIOS 0x61234
1221 #define PFIT_VERT_SCALE_MASK 0xfff00000
1222 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1224 #define PFIT_VERT_SCALE_SHIFT 20
1225 #define PFIT_VERT_SCALE_MASK 0xfff00000
1226 #define PFIT_HORIZ_SCALE_SHIFT 4
1227 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1229 #define PFIT_VERT_SCALE_SHIFT_965 16
1230 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1231 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1232 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1234 #define PFIT_AUTO_RATIOS 0x61238
1236 /* Backlight control */
1237 #define BLC_PWM_CTL 0x61254
1238 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1239 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1240 #define BLM_COMBINATION_MODE (1 << 30)
1242 * This is the most significant 15 bits of the number of backlight cycles in a
1243 * complete cycle of the modulated backlight control.
1245 * The actual value is this field multiplied by two.
1247 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1248 #define BLM_LEGACY_MODE (1 << 16)
1250 * This is the number of cycles out of the backlight modulation cycle for which
1251 * the backlight is on.
1253 * This field must be no greater than the number of cycles in the complete
1254 * backlight modulation cycle.
1256 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1257 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1259 #define BLC_HIST_CTL 0x61260
1261 /* TV port control */
1262 #define TV_CTL 0x68000
1263 /** Enables the TV encoder */
1264 # define TV_ENC_ENABLE (1 << 31)
1265 /** Sources the TV encoder input from pipe B instead of A. */
1266 # define TV_ENC_PIPEB_SELECT (1 << 30)
1267 /** Outputs composite video (DAC A only) */
1268 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1269 /** Outputs SVideo video (DAC B/C) */
1270 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1271 /** Outputs Component video (DAC A/B/C) */
1272 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1273 /** Outputs Composite and SVideo (DAC A/B/C) */
1274 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1275 # define TV_TRILEVEL_SYNC (1 << 21)
1276 /** Enables slow sync generation (945GM only) */
1277 # define TV_SLOW_SYNC (1 << 20)
1278 /** Selects 4x oversampling for 480i and 576p */
1279 # define TV_OVERSAMPLE_4X (0 << 18)
1280 /** Selects 2x oversampling for 720p and 1080i */
1281 # define TV_OVERSAMPLE_2X (1 << 18)
1282 /** Selects no oversampling for 1080p */
1283 # define TV_OVERSAMPLE_NONE (2 << 18)
1284 /** Selects 8x oversampling */
1285 # define TV_OVERSAMPLE_8X (3 << 18)
1286 /** Selects progressive mode rather than interlaced */
1287 # define TV_PROGRESSIVE (1 << 17)
1288 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1289 # define TV_PAL_BURST (1 << 16)
1290 /** Field for setting delay of Y compared to C */
1291 # define TV_YC_SKEW_MASK (7 << 12)
1292 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1293 # define TV_ENC_SDP_FIX (1 << 11)
1295 * Enables a fix for the 915GM only.
1297 * Not sure what it does.
1299 # define TV_ENC_C0_FIX (1 << 10)
1300 /** Bits that must be preserved by software */
1301 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1302 # define TV_FUSE_STATE_MASK (3 << 4)
1303 /** Read-only state that reports all features enabled */
1304 # define TV_FUSE_STATE_ENABLED (0 << 4)
1305 /** Read-only state that reports that Macrovision is disabled in hardware*/
1306 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1307 /** Read-only state that reports that TV-out is disabled in hardware. */
1308 # define TV_FUSE_STATE_DISABLED (2 << 4)
1309 /** Normal operation */
1310 # define TV_TEST_MODE_NORMAL (0 << 0)
1311 /** Encoder test pattern 1 - combo pattern */
1312 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1313 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1314 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1315 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1316 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1317 /** Encoder test pattern 4 - random noise */
1318 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1319 /** Encoder test pattern 5 - linear color ramps */
1320 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1322 * This test mode forces the DACs to 50% of full output.
1324 * This is used for load detection in combination with TVDAC_SENSE_MASK
1326 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1327 # define TV_TEST_MODE_MASK (7 << 0)
1329 #define TV_DAC 0x68004
1331 * Reports that DAC state change logic has reported change (RO).
1333 * This gets cleared when TV_DAC_STATE_EN is cleared
1335 # define TVDAC_STATE_CHG (1 << 31)
1336 # define TVDAC_SENSE_MASK (7 << 28)
1337 /** Reports that DAC A voltage is above the detect threshold */
1338 # define TVDAC_A_SENSE (1 << 30)
1339 /** Reports that DAC B voltage is above the detect threshold */
1340 # define TVDAC_B_SENSE (1 << 29)
1341 /** Reports that DAC C voltage is above the detect threshold */
1342 # define TVDAC_C_SENSE (1 << 28)
1344 * Enables DAC state detection logic, for load-based TV detection.
1346 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1347 * to off, for load detection to work.
1349 # define TVDAC_STATE_CHG_EN (1 << 27)
1350 /** Sets the DAC A sense value to high */
1351 # define TVDAC_A_SENSE_CTL (1 << 26)
1352 /** Sets the DAC B sense value to high */
1353 # define TVDAC_B_SENSE_CTL (1 << 25)
1354 /** Sets the DAC C sense value to high */
1355 # define TVDAC_C_SENSE_CTL (1 << 24)
1356 /** Overrides the ENC_ENABLE and DAC voltage levels */
1357 # define DAC_CTL_OVERRIDE (1 << 7)
1358 /** Sets the slew rate. Must be preserved in software */
1359 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1360 # define DAC_A_1_3_V (0 << 4)
1361 # define DAC_A_1_1_V (1 << 4)
1362 # define DAC_A_0_7_V (2 << 4)
1363 # define DAC_A_MASK (3 << 4)
1364 # define DAC_B_1_3_V (0 << 2)
1365 # define DAC_B_1_1_V (1 << 2)
1366 # define DAC_B_0_7_V (2 << 2)
1367 # define DAC_B_MASK (3 << 2)
1368 # define DAC_C_1_3_V (0 << 0)
1369 # define DAC_C_1_1_V (1 << 0)
1370 # define DAC_C_0_7_V (2 << 0)
1371 # define DAC_C_MASK (3 << 0)
1374 * CSC coefficients are stored in a floating point format with 9 bits of
1375 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1376 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1377 * -1 (0x3) being the only legal negative value.
1379 #define TV_CSC_Y 0x68010
1380 # define TV_RY_MASK 0x07ff0000
1381 # define TV_RY_SHIFT 16
1382 # define TV_GY_MASK 0x00000fff
1383 # define TV_GY_SHIFT 0
1385 #define TV_CSC_Y2 0x68014
1386 # define TV_BY_MASK 0x07ff0000
1387 # define TV_BY_SHIFT 16
1389 * Y attenuation for component video.
1391 * Stored in 1.9 fixed point.
1393 # define TV_AY_MASK 0x000003ff
1394 # define TV_AY_SHIFT 0
1396 #define TV_CSC_U 0x68018
1397 # define TV_RU_MASK 0x07ff0000
1398 # define TV_RU_SHIFT 16
1399 # define TV_GU_MASK 0x000007ff
1400 # define TV_GU_SHIFT 0
1402 #define TV_CSC_U2 0x6801c
1403 # define TV_BU_MASK 0x07ff0000
1404 # define TV_BU_SHIFT 16
1406 * U attenuation for component video.
1408 * Stored in 1.9 fixed point.
1410 # define TV_AU_MASK 0x000003ff
1411 # define TV_AU_SHIFT 0
1413 #define TV_CSC_V 0x68020
1414 # define TV_RV_MASK 0x0fff0000
1415 # define TV_RV_SHIFT 16
1416 # define TV_GV_MASK 0x000007ff
1417 # define TV_GV_SHIFT 0
1419 #define TV_CSC_V2 0x68024
1420 # define TV_BV_MASK 0x07ff0000
1421 # define TV_BV_SHIFT 16
1423 * V attenuation for component video.
1425 * Stored in 1.9 fixed point.
1427 # define TV_AV_MASK 0x000007ff
1428 # define TV_AV_SHIFT 0
1430 #define TV_CLR_KNOBS 0x68028
1431 /** 2s-complement brightness adjustment */
1432 # define TV_BRIGHTNESS_MASK 0xff000000
1433 # define TV_BRIGHTNESS_SHIFT 24
1434 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1435 # define TV_CONTRAST_MASK 0x00ff0000
1436 # define TV_CONTRAST_SHIFT 16
1437 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1438 # define TV_SATURATION_MASK 0x0000ff00
1439 # define TV_SATURATION_SHIFT 8
1440 /** Hue adjustment, as an integer phase angle in degrees */
1441 # define TV_HUE_MASK 0x000000ff
1442 # define TV_HUE_SHIFT 0
1444 #define TV_CLR_LEVEL 0x6802c
1445 /** Controls the DAC level for black */
1446 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1447 # define TV_BLACK_LEVEL_SHIFT 16
1448 /** Controls the DAC level for blanking */
1449 # define TV_BLANK_LEVEL_MASK 0x000001ff
1450 # define TV_BLANK_LEVEL_SHIFT 0
1452 #define TV_H_CTL_1 0x68030
1453 /** Number of pixels in the hsync. */
1454 # define TV_HSYNC_END_MASK 0x1fff0000
1455 # define TV_HSYNC_END_SHIFT 16
1456 /** Total number of pixels minus one in the line (display and blanking). */
1457 # define TV_HTOTAL_MASK 0x00001fff
1458 # define TV_HTOTAL_SHIFT 0
1460 #define TV_H_CTL_2 0x68034
1461 /** Enables the colorburst (needed for non-component color) */
1462 # define TV_BURST_ENA (1 << 31)
1463 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1464 # define TV_HBURST_START_SHIFT 16
1465 # define TV_HBURST_START_MASK 0x1fff0000
1466 /** Length of the colorburst */
1467 # define TV_HBURST_LEN_SHIFT 0
1468 # define TV_HBURST_LEN_MASK 0x0001fff
1470 #define TV_H_CTL_3 0x68038
1471 /** End of hblank, measured in pixels minus one from start of hsync */
1472 # define TV_HBLANK_END_SHIFT 16
1473 # define TV_HBLANK_END_MASK 0x1fff0000
1474 /** Start of hblank, measured in pixels minus one from start of hsync */
1475 # define TV_HBLANK_START_SHIFT 0
1476 # define TV_HBLANK_START_MASK 0x0001fff
1478 #define TV_V_CTL_1 0x6803c
1480 # define TV_NBR_END_SHIFT 16
1481 # define TV_NBR_END_MASK 0x07ff0000
1483 # define TV_VI_END_F1_SHIFT 8
1484 # define TV_VI_END_F1_MASK 0x00003f00
1486 # define TV_VI_END_F2_SHIFT 0
1487 # define TV_VI_END_F2_MASK 0x0000003f
1489 #define TV_V_CTL_2 0x68040
1490 /** Length of vsync, in half lines */
1491 # define TV_VSYNC_LEN_MASK 0x07ff0000
1492 # define TV_VSYNC_LEN_SHIFT 16
1493 /** Offset of the start of vsync in field 1, measured in one less than the
1494 * number of half lines.
1496 # define TV_VSYNC_START_F1_MASK 0x00007f00
1497 # define TV_VSYNC_START_F1_SHIFT 8
1499 * Offset of the start of vsync in field 2, measured in one less than the
1500 * number of half lines.
1502 # define TV_VSYNC_START_F2_MASK 0x0000007f
1503 # define TV_VSYNC_START_F2_SHIFT 0
1505 #define TV_V_CTL_3 0x68044
1506 /** Enables generation of the equalization signal */
1507 # define TV_EQUAL_ENA (1 << 31)
1508 /** Length of vsync, in half lines */
1509 # define TV_VEQ_LEN_MASK 0x007f0000
1510 # define TV_VEQ_LEN_SHIFT 16
1511 /** Offset of the start of equalization in field 1, measured in one less than
1512 * the number of half lines.
1514 # define TV_VEQ_START_F1_MASK 0x0007f00
1515 # define TV_VEQ_START_F1_SHIFT 8
1517 * Offset of the start of equalization in field 2, measured in one less than
1518 * the number of half lines.
1520 # define TV_VEQ_START_F2_MASK 0x000007f
1521 # define TV_VEQ_START_F2_SHIFT 0
1523 #define TV_V_CTL_4 0x68048
1525 * Offset to start of vertical colorburst, measured in one less than the
1526 * number of lines from vertical start.
1528 # define TV_VBURST_START_F1_MASK 0x003f0000
1529 # define TV_VBURST_START_F1_SHIFT 16
1531 * Offset to the end of vertical colorburst, measured in one less than the
1532 * number of lines from the start of NBR.
1534 # define TV_VBURST_END_F1_MASK 0x000000ff
1535 # define TV_VBURST_END_F1_SHIFT 0
1537 #define TV_V_CTL_5 0x6804c
1539 * Offset to start of vertical colorburst, measured in one less than the
1540 * number of lines from vertical start.
1542 # define TV_VBURST_START_F2_MASK 0x003f0000
1543 # define TV_VBURST_START_F2_SHIFT 16
1545 * Offset to the end of vertical colorburst, measured in one less than the
1546 * number of lines from the start of NBR.
1548 # define TV_VBURST_END_F2_MASK 0x000000ff
1549 # define TV_VBURST_END_F2_SHIFT 0
1551 #define TV_V_CTL_6 0x68050
1553 * Offset to start of vertical colorburst, measured in one less than the
1554 * number of lines from vertical start.
1556 # define TV_VBURST_START_F3_MASK 0x003f0000
1557 # define TV_VBURST_START_F3_SHIFT 16
1559 * Offset to the end of vertical colorburst, measured in one less than the
1560 * number of lines from the start of NBR.
1562 # define TV_VBURST_END_F3_MASK 0x000000ff
1563 # define TV_VBURST_END_F3_SHIFT 0
1565 #define TV_V_CTL_7 0x68054
1567 * Offset to start of vertical colorburst, measured in one less than the
1568 * number of lines from vertical start.
1570 # define TV_VBURST_START_F4_MASK 0x003f0000
1571 # define TV_VBURST_START_F4_SHIFT 16
1573 * Offset to the end of vertical colorburst, measured in one less than the
1574 * number of lines from the start of NBR.
1576 # define TV_VBURST_END_F4_MASK 0x000000ff
1577 # define TV_VBURST_END_F4_SHIFT 0
1579 #define TV_SC_CTL_1 0x68060
1580 /** Turns on the first subcarrier phase generation DDA */
1581 # define TV_SC_DDA1_EN (1 << 31)
1582 /** Turns on the first subcarrier phase generation DDA */
1583 # define TV_SC_DDA2_EN (1 << 30)
1584 /** Turns on the first subcarrier phase generation DDA */
1585 # define TV_SC_DDA3_EN (1 << 29)
1586 /** Sets the subcarrier DDA to reset frequency every other field */
1587 # define TV_SC_RESET_EVERY_2 (0 << 24)
1588 /** Sets the subcarrier DDA to reset frequency every fourth field */
1589 # define TV_SC_RESET_EVERY_4 (1 << 24)
1590 /** Sets the subcarrier DDA to reset frequency every eighth field */
1591 # define TV_SC_RESET_EVERY_8 (2 << 24)
1592 /** Sets the subcarrier DDA to never reset the frequency */
1593 # define TV_SC_RESET_NEVER (3 << 24)
1594 /** Sets the peak amplitude of the colorburst.*/
1595 # define TV_BURST_LEVEL_MASK 0x00ff0000
1596 # define TV_BURST_LEVEL_SHIFT 16
1597 /** Sets the increment of the first subcarrier phase generation DDA */
1598 # define TV_SCDDA1_INC_MASK 0x00000fff
1599 # define TV_SCDDA1_INC_SHIFT 0
1601 #define TV_SC_CTL_2 0x68064
1602 /** Sets the rollover for the second subcarrier phase generation DDA */
1603 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
1604 # define TV_SCDDA2_SIZE_SHIFT 16
1605 /** Sets the increent of the second subcarrier phase generation DDA */
1606 # define TV_SCDDA2_INC_MASK 0x00007fff
1607 # define TV_SCDDA2_INC_SHIFT 0
1609 #define TV_SC_CTL_3 0x68068
1610 /** Sets the rollover for the third subcarrier phase generation DDA */
1611 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
1612 # define TV_SCDDA3_SIZE_SHIFT 16
1613 /** Sets the increent of the third subcarrier phase generation DDA */
1614 # define TV_SCDDA3_INC_MASK 0x00007fff
1615 # define TV_SCDDA3_INC_SHIFT 0
1617 #define TV_WIN_POS 0x68070
1618 /** X coordinate of the display from the start of horizontal active */
1619 # define TV_XPOS_MASK 0x1fff0000
1620 # define TV_XPOS_SHIFT 16
1621 /** Y coordinate of the display from the start of vertical active (NBR) */
1622 # define TV_YPOS_MASK 0x00000fff
1623 # define TV_YPOS_SHIFT 0
1625 #define TV_WIN_SIZE 0x68074
1626 /** Horizontal size of the display window, measured in pixels*/
1627 # define TV_XSIZE_MASK 0x1fff0000
1628 # define TV_XSIZE_SHIFT 16
1630 * Vertical size of the display window, measured in pixels.
1632 * Must be even for interlaced modes.
1634 # define TV_YSIZE_MASK 0x00000fff
1635 # define TV_YSIZE_SHIFT 0
1637 #define TV_FILTER_CTL_1 0x68080
1639 * Enables automatic scaling calculation.
1641 * If set, the rest of the registers are ignored, and the calculated values can
1642 * be read back from the register.
1644 # define TV_AUTO_SCALE (1 << 31)
1646 * Disables the vertical filter.
1648 * This is required on modes more than 1024 pixels wide */
1649 # define TV_V_FILTER_BYPASS (1 << 29)
1650 /** Enables adaptive vertical filtering */
1651 # define TV_VADAPT (1 << 28)
1652 # define TV_VADAPT_MODE_MASK (3 << 26)
1653 /** Selects the least adaptive vertical filtering mode */
1654 # define TV_VADAPT_MODE_LEAST (0 << 26)
1655 /** Selects the moderately adaptive vertical filtering mode */
1656 # define TV_VADAPT_MODE_MODERATE (1 << 26)
1657 /** Selects the most adaptive vertical filtering mode */
1658 # define TV_VADAPT_MODE_MOST (3 << 26)
1660 * Sets the horizontal scaling factor.
1662 * This should be the fractional part of the horizontal scaling factor divided
1663 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1665 * (src width - 1) / ((oversample * dest width) - 1)
1667 # define TV_HSCALE_FRAC_MASK 0x00003fff
1668 # define TV_HSCALE_FRAC_SHIFT 0
1670 #define TV_FILTER_CTL_2 0x68084
1672 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1674 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1676 # define TV_VSCALE_INT_MASK 0x00038000
1677 # define TV_VSCALE_INT_SHIFT 15
1679 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1681 * \sa TV_VSCALE_INT_MASK
1683 # define TV_VSCALE_FRAC_MASK 0x00007fff
1684 # define TV_VSCALE_FRAC_SHIFT 0
1686 #define TV_FILTER_CTL_3 0x68088
1688 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1690 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1692 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1694 # define TV_VSCALE_IP_INT_MASK 0x00038000
1695 # define TV_VSCALE_IP_INT_SHIFT 15
1697 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1699 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1701 * \sa TV_VSCALE_IP_INT_MASK
1703 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1704 # define TV_VSCALE_IP_FRAC_SHIFT 0
1706 #define TV_CC_CONTROL 0x68090
1707 # define TV_CC_ENABLE (1 << 31)
1709 * Specifies which field to send the CC data in.
1711 * CC data is usually sent in field 0.
1713 # define TV_CC_FID_MASK (1 << 27)
1714 # define TV_CC_FID_SHIFT 27
1715 /** Sets the horizontal position of the CC data. Usually 135. */
1716 # define TV_CC_HOFF_MASK 0x03ff0000
1717 # define TV_CC_HOFF_SHIFT 16
1718 /** Sets the vertical position of the CC data. Usually 21 */
1719 # define TV_CC_LINE_MASK 0x0000003f
1720 # define TV_CC_LINE_SHIFT 0
1722 #define TV_CC_DATA 0x68094
1723 # define TV_CC_RDY (1 << 31)
1724 /** Second word of CC data to be transmitted. */
1725 # define TV_CC_DATA_2_MASK 0x007f0000
1726 # define TV_CC_DATA_2_SHIFT 16
1727 /** First word of CC data to be transmitted. */
1728 # define TV_CC_DATA_1_MASK 0x0000007f
1729 # define TV_CC_DATA_1_SHIFT 0
1731 #define TV_H_LUMA_0 0x68100
1732 #define TV_H_LUMA_59 0x681ec
1733 #define TV_H_CHROMA_0 0x68200
1734 #define TV_H_CHROMA_59 0x682ec
1735 #define TV_V_LUMA_0 0x68300
1736 #define TV_V_LUMA_42 0x683a8
1737 #define TV_V_CHROMA_0 0x68400
1738 #define TV_V_CHROMA_42 0x684a8
1741 #define DP_A 0x64000 /* eDP */
1742 #define DP_B 0x64100
1743 #define DP_C 0x64200
1744 #define DP_D 0x64300
1746 #define DP_PORT_EN (1 << 31)
1747 #define DP_PIPEB_SELECT (1 << 30)
1749 /* Link training mode - select a suitable mode for each stage */
1750 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1751 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
1752 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1753 #define DP_LINK_TRAIN_OFF (3 << 28)
1754 #define DP_LINK_TRAIN_MASK (3 << 28)
1755 #define DP_LINK_TRAIN_SHIFT 28
1757 /* Signal voltages. These are mostly controlled by the other end */
1758 #define DP_VOLTAGE_0_4 (0 << 25)
1759 #define DP_VOLTAGE_0_6 (1 << 25)
1760 #define DP_VOLTAGE_0_8 (2 << 25)
1761 #define DP_VOLTAGE_1_2 (3 << 25)
1762 #define DP_VOLTAGE_MASK (7 << 25)
1763 #define DP_VOLTAGE_SHIFT 25
1765 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1768 #define DP_PRE_EMPHASIS_0 (0 << 22)
1769 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
1770 #define DP_PRE_EMPHASIS_6 (2 << 22)
1771 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
1772 #define DP_PRE_EMPHASIS_MASK (7 << 22)
1773 #define DP_PRE_EMPHASIS_SHIFT 22
1775 /* How many wires to use. I guess 3 was too hard */
1776 #define DP_PORT_WIDTH_1 (0 << 19)
1777 #define DP_PORT_WIDTH_2 (1 << 19)
1778 #define DP_PORT_WIDTH_4 (3 << 19)
1779 #define DP_PORT_WIDTH_MASK (7 << 19)
1781 /* Mystic DPCD version 1.1 special mode */
1782 #define DP_ENHANCED_FRAMING (1 << 18)
1785 #define DP_PLL_FREQ_270MHZ (0 << 16)
1786 #define DP_PLL_FREQ_160MHZ (1 << 16)
1787 #define DP_PLL_FREQ_MASK (3 << 16)
1789 /** locked once port is enabled */
1790 #define DP_PORT_REVERSAL (1 << 15)
1793 #define DP_PLL_ENABLE (1 << 14)
1795 /** sends the clock on lane 15 of the PEG for debug */
1796 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1798 #define DP_SCRAMBLING_DISABLE (1 << 12)
1799 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1801 /** limit RGB values to avoid confusing TVs */
1802 #define DP_COLOR_RANGE_16_235 (1 << 8)
1804 /** Turn on the audio link */
1805 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1807 /** vs and hs sync polarity */
1808 #define DP_SYNC_VS_HIGH (1 << 4)
1809 #define DP_SYNC_HS_HIGH (1 << 3)
1812 #define DP_DETECTED (1 << 2)
1814 /** The aux channel provides a way to talk to the
1815 * signal sink for DDC etc. Max packet size supported
1816 * is 20 bytes in each direction, hence the 5 fixed
1819 #define DPA_AUX_CH_CTL 0x64010
1820 #define DPA_AUX_CH_DATA1 0x64014
1821 #define DPA_AUX_CH_DATA2 0x64018
1822 #define DPA_AUX_CH_DATA3 0x6401c
1823 #define DPA_AUX_CH_DATA4 0x64020
1824 #define DPA_AUX_CH_DATA5 0x64024
1826 #define DPB_AUX_CH_CTL 0x64110
1827 #define DPB_AUX_CH_DATA1 0x64114
1828 #define DPB_AUX_CH_DATA2 0x64118
1829 #define DPB_AUX_CH_DATA3 0x6411c
1830 #define DPB_AUX_CH_DATA4 0x64120
1831 #define DPB_AUX_CH_DATA5 0x64124
1833 #define DPC_AUX_CH_CTL 0x64210
1834 #define DPC_AUX_CH_DATA1 0x64214
1835 #define DPC_AUX_CH_DATA2 0x64218
1836 #define DPC_AUX_CH_DATA3 0x6421c
1837 #define DPC_AUX_CH_DATA4 0x64220
1838 #define DPC_AUX_CH_DATA5 0x64224
1840 #define DPD_AUX_CH_CTL 0x64310
1841 #define DPD_AUX_CH_DATA1 0x64314
1842 #define DPD_AUX_CH_DATA2 0x64318
1843 #define DPD_AUX_CH_DATA3 0x6431c
1844 #define DPD_AUX_CH_DATA4 0x64320
1845 #define DPD_AUX_CH_DATA5 0x64324
1847 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1848 #define DP_AUX_CH_CTL_DONE (1 << 30)
1849 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1850 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1851 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1852 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1853 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1854 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1855 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1856 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1857 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1858 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1859 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1860 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1861 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1862 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1863 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1864 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1865 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1866 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1867 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1870 * Computing GMCH M and N values for the Display Port link
1872 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1874 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1876 * The GMCH value is used internally
1878 * bytes_per_pixel is the number of bytes coming out of the plane,
1879 * which is after the LUTs, so we want the bytes for our color format.
1880 * For our current usage, this is always 3, one byte for R, G and B.
1882 #define PIPEA_GMCH_DATA_M 0x70050
1883 #define PIPEB_GMCH_DATA_M 0x71050
1885 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1886 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1887 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1889 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
1891 #define PIPEA_GMCH_DATA_N 0x70054
1892 #define PIPEB_GMCH_DATA_N 0x71054
1893 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
1896 * Computing Link M and N values for the Display Port link
1898 * Link M / N = pixel_clock / ls_clk
1900 * (the DP spec calls pixel_clock the 'strm_clk')
1902 * The Link value is transmitted in the Main Stream
1903 * Attributes and VB-ID.
1906 #define PIPEA_DP_LINK_M 0x70060
1907 #define PIPEB_DP_LINK_M 0x71060
1908 #define PIPEA_DP_LINK_M_MASK (0xffffff)
1910 #define PIPEA_DP_LINK_N 0x70064
1911 #define PIPEB_DP_LINK_N 0x71064
1912 #define PIPEA_DP_LINK_N_MASK (0xffffff)
1914 /* Display & cursor control */
1916 /* dithering flag on Ironlake */
1917 #define PIPE_ENABLE_DITHER (1 << 4)
1919 #define PIPEADSL 0x70000
1920 #define PIPEACONF 0x70008
1921 #define PIPEACONF_ENABLE (1<<31)
1922 #define PIPEACONF_DISABLE 0
1923 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1924 #define I965_PIPECONF_ACTIVE (1<<30)
1925 #define PIPEACONF_SINGLE_WIDE 0
1926 #define PIPEACONF_PIPE_UNLOCKED 0
1927 #define PIPEACONF_PIPE_LOCKED (1<<25)
1928 #define PIPEACONF_PALETTE 0
1929 #define PIPEACONF_GAMMA (1<<24)
1930 #define PIPECONF_FORCE_BORDER (1<<25)
1931 #define PIPECONF_PROGRESSIVE (0 << 21)
1932 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1933 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1934 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
1935 #define PIPEASTAT 0x70024
1936 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1937 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1938 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
1939 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1940 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1941 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1942 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1943 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1944 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1945 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1946 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1947 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1948 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1949 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1950 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1951 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1952 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1953 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1954 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1955 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1956 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1957 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
1958 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1959 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1960 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1961 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1962 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1963 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1964 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1965 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
1966 #define PIPE_8BPC (0 << 5)
1967 #define PIPE_10BPC (1 << 5)
1968 #define PIPE_6BPC (2 << 5)
1969 #define PIPE_12BPC (3 << 5)
1971 #define DSPARB 0x70030
1972 #define DSPARB_CSTART_MASK (0x7f << 7)
1973 #define DSPARB_CSTART_SHIFT 7
1974 #define DSPARB_BSTART_MASK (0x7f)
1975 #define DSPARB_BSTART_SHIFT 0
1976 #define DSPARB_BEND_SHIFT 9 /* on 855 */
1977 #define DSPARB_AEND_SHIFT 0
1979 #define DSPFW1 0x70034
1980 #define DSPFW_SR_SHIFT 23
1981 #define DSPFW_CURSORB_SHIFT 16
1982 #define DSPFW_PLANEB_SHIFT 8
1983 #define DSPFW2 0x70038
1984 #define DSPFW_CURSORA_MASK 0x00003f00
1985 #define DSPFW_CURSORA_SHIFT 8
1986 #define DSPFW3 0x7003c
1987 #define DSPFW_HPLL_SR_EN (1<<31)
1988 #define DSPFW_CURSOR_SR_SHIFT 24
1989 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
1991 /* FIFO watermark sizes etc */
1992 #define G4X_FIFO_LINE_SIZE 64
1993 #define I915_FIFO_LINE_SIZE 64
1994 #define I830_FIFO_LINE_SIZE 32
1996 #define G4X_FIFO_SIZE 127
1997 #define I945_FIFO_SIZE 127 /* 945 & 965 */
1998 #define I915_FIFO_SIZE 95
1999 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2000 #define I830_FIFO_SIZE 95
2002 #define G4X_MAX_WM 0x3f
2003 #define I915_MAX_WM 0x3f
2005 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2006 #define PINEVIEW_FIFO_LINE_SIZE 64
2007 #define PINEVIEW_MAX_WM 0x1ff
2008 #define PINEVIEW_DFT_WM 0x3f
2009 #define PINEVIEW_DFT_HPLLOFF_WM 0
2010 #define PINEVIEW_GUARD_WM 10
2011 #define PINEVIEW_CURSOR_FIFO 64
2012 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2013 #define PINEVIEW_CURSOR_DFT_WM 0
2014 #define PINEVIEW_CURSOR_GUARD_WM 5
2017 * The two pipe frame counter registers are not synchronized, so
2018 * reading a stable value is somewhat tricky. The following code
2022 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2023 * PIPE_FRAME_HIGH_SHIFT;
2024 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2025 * PIPE_FRAME_LOW_SHIFT);
2026 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2027 * PIPE_FRAME_HIGH_SHIFT);
2028 * } while (high1 != high2);
2029 * frame = (high1 << 8) | low1;
2031 #define PIPEAFRAMEHIGH 0x70040
2032 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2033 #define PIPE_FRAME_HIGH_SHIFT 0
2034 #define PIPEAFRAMEPIXEL 0x70044
2035 #define PIPE_FRAME_LOW_MASK 0xff000000
2036 #define PIPE_FRAME_LOW_SHIFT 24
2037 #define PIPE_PIXEL_MASK 0x00ffffff
2038 #define PIPE_PIXEL_SHIFT 0
2039 /* GM45+ just has to be different */
2040 #define PIPEA_FRMCOUNT_GM45 0x70040
2041 #define PIPEA_FLIPCOUNT_GM45 0x70044
2043 /* Cursor A & B regs */
2044 #define CURACNTR 0x70080
2045 /* Old style CUR*CNTR flags (desktop 8xx) */
2046 #define CURSOR_ENABLE 0x80000000
2047 #define CURSOR_GAMMA_ENABLE 0x40000000
2048 #define CURSOR_STRIDE_MASK 0x30000000
2049 #define CURSOR_FORMAT_SHIFT 24
2050 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2051 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2052 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2053 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2054 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2055 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2056 /* New style CUR*CNTR flags */
2057 #define CURSOR_MODE 0x27
2058 #define CURSOR_MODE_DISABLE 0x00
2059 #define CURSOR_MODE_64_32B_AX 0x07
2060 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2061 #define MCURSOR_PIPE_SELECT (1 << 28)
2062 #define MCURSOR_PIPE_A 0x00
2063 #define MCURSOR_PIPE_B (1 << 28)
2064 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2065 #define CURABASE 0x70084
2066 #define CURAPOS 0x70088
2067 #define CURSOR_POS_MASK 0x007FF
2068 #define CURSOR_POS_SIGN 0x8000
2069 #define CURSOR_X_SHIFT 0
2070 #define CURSOR_Y_SHIFT 16
2071 #define CURSIZE 0x700a0
2072 #define CURBCNTR 0x700c0
2073 #define CURBBASE 0x700c4
2074 #define CURBPOS 0x700c8
2076 /* Display A control */
2077 #define DSPACNTR 0x70180
2078 #define DISPLAY_PLANE_ENABLE (1<<31)
2079 #define DISPLAY_PLANE_DISABLE 0
2080 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2081 #define DISPPLANE_GAMMA_DISABLE 0
2082 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2083 #define DISPPLANE_8BPP (0x2<<26)
2084 #define DISPPLANE_15_16BPP (0x4<<26)
2085 #define DISPPLANE_16BPP (0x5<<26)
2086 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2087 #define DISPPLANE_32BPP (0x7<<26)
2088 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2089 #define DISPPLANE_STEREO_ENABLE (1<<25)
2090 #define DISPPLANE_STEREO_DISABLE 0
2091 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
2092 #define DISPPLANE_SEL_PIPE_A 0
2093 #define DISPPLANE_SEL_PIPE_B (1<<24)
2094 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2095 #define DISPPLANE_SRC_KEY_DISABLE 0
2096 #define DISPPLANE_LINE_DOUBLE (1<<20)
2097 #define DISPPLANE_NO_LINE_DOUBLE 0
2098 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2099 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2100 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2101 #define DISPPLANE_TILED (1<<10)
2102 #define DSPAADDR 0x70184
2103 #define DSPASTRIDE 0x70188
2104 #define DSPAPOS 0x7018C /* reserved */
2105 #define DSPASIZE 0x70190
2106 #define DSPASURF 0x7019C /* 965+ only */
2107 #define DSPATILEOFF 0x701A4 /* 965+ only */
2110 #define SWF00 0x71410
2111 #define SWF01 0x71414
2112 #define SWF02 0x71418
2113 #define SWF03 0x7141c
2114 #define SWF04 0x71420
2115 #define SWF05 0x71424
2116 #define SWF06 0x71428
2117 #define SWF10 0x70410
2118 #define SWF11 0x70414
2119 #define SWF14 0x71420
2120 #define SWF30 0x72414
2121 #define SWF31 0x72418
2122 #define SWF32 0x7241c
2125 #define PIPEBDSL 0x71000
2126 #define PIPEBCONF 0x71008
2127 #define PIPEBSTAT 0x71024
2128 #define PIPEBFRAMEHIGH 0x71040
2129 #define PIPEBFRAMEPIXEL 0x71044
2130 #define PIPEB_FRMCOUNT_GM45 0x71040
2131 #define PIPEB_FLIPCOUNT_GM45 0x71044
2134 /* Display B control */
2135 #define DSPBCNTR 0x71180
2136 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2137 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2138 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2139 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2140 #define DSPBADDR 0x71184
2141 #define DSPBSTRIDE 0x71188
2142 #define DSPBPOS 0x7118C
2143 #define DSPBSIZE 0x71190
2144 #define DSPBSURF 0x7119C
2145 #define DSPBTILEOFF 0x711A4
2148 #define VGACNTRL 0x71400
2149 # define VGA_DISP_DISABLE (1 << 31)
2150 # define VGA_2X_MODE (1 << 30)
2151 # define VGA_PIPE_B_SELECT (1 << 29)
2155 #define CPU_VGACNTRL 0x41000
2157 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2158 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2159 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2160 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2161 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2162 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2163 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2164 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2165 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2167 /* refresh rate hardware control */
2168 #define RR_HW_CTL 0x45300
2169 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2170 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2172 #define FDI_PLL_BIOS_0 0x46000
2173 #define FDI_PLL_BIOS_1 0x46004
2174 #define FDI_PLL_BIOS_2 0x46008
2175 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2176 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2177 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2179 #define PCH_DSPCLK_GATE_D 0x42020
2180 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2181 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2183 #define PCH_3DCGDIS0 0x46020
2184 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2185 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2187 #define FDI_PLL_FREQ_CTL 0x46030
2188 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2189 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2190 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2193 #define PIPEA_DATA_M1 0x60030
2194 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2195 #define TU_SIZE_MASK 0x7e000000
2196 #define PIPEA_DATA_M1_OFFSET 0
2197 #define PIPEA_DATA_N1 0x60034
2198 #define PIPEA_DATA_N1_OFFSET 0
2200 #define PIPEA_DATA_M2 0x60038
2201 #define PIPEA_DATA_M2_OFFSET 0
2202 #define PIPEA_DATA_N2 0x6003c
2203 #define PIPEA_DATA_N2_OFFSET 0
2205 #define PIPEA_LINK_M1 0x60040
2206 #define PIPEA_LINK_M1_OFFSET 0
2207 #define PIPEA_LINK_N1 0x60044
2208 #define PIPEA_LINK_N1_OFFSET 0
2210 #define PIPEA_LINK_M2 0x60048
2211 #define PIPEA_LINK_M2_OFFSET 0
2212 #define PIPEA_LINK_N2 0x6004c
2213 #define PIPEA_LINK_N2_OFFSET 0
2215 /* PIPEB timing regs are same start from 0x61000 */
2217 #define PIPEB_DATA_M1 0x61030
2218 #define PIPEB_DATA_M1_OFFSET 0
2219 #define PIPEB_DATA_N1 0x61034
2220 #define PIPEB_DATA_N1_OFFSET 0
2222 #define PIPEB_DATA_M2 0x61038
2223 #define PIPEB_DATA_M2_OFFSET 0
2224 #define PIPEB_DATA_N2 0x6103c
2225 #define PIPEB_DATA_N2_OFFSET 0
2227 #define PIPEB_LINK_M1 0x61040
2228 #define PIPEB_LINK_M1_OFFSET 0
2229 #define PIPEB_LINK_N1 0x61044
2230 #define PIPEB_LINK_N1_OFFSET 0
2232 #define PIPEB_LINK_M2 0x61048
2233 #define PIPEB_LINK_M2_OFFSET 0
2234 #define PIPEB_LINK_N2 0x6104c
2235 #define PIPEB_LINK_N2_OFFSET 0
2237 /* CPU panel fitter */
2238 #define PFA_CTL_1 0x68080
2239 #define PFB_CTL_1 0x68880
2240 #define PF_ENABLE (1<<31)
2241 #define PF_FILTER_MASK (3<<23)
2242 #define PF_FILTER_PROGRAMMED (0<<23)
2243 #define PF_FILTER_MED_3x3 (1<<23)
2244 #define PF_FILTER_EDGE_ENHANCE (2<<23)
2245 #define PF_FILTER_EDGE_SOFTEN (3<<23)
2246 #define PFA_WIN_SZ 0x68074
2247 #define PFB_WIN_SZ 0x68874
2248 #define PFA_WIN_POS 0x68070
2249 #define PFB_WIN_POS 0x68870
2251 /* legacy palette */
2252 #define LGC_PALETTE_A 0x4a000
2253 #define LGC_PALETTE_B 0x4a800
2256 #define DE_MASTER_IRQ_CONTROL (1 << 31)
2257 #define DE_SPRITEB_FLIP_DONE (1 << 29)
2258 #define DE_SPRITEA_FLIP_DONE (1 << 28)
2259 #define DE_PLANEB_FLIP_DONE (1 << 27)
2260 #define DE_PLANEA_FLIP_DONE (1 << 26)
2261 #define DE_PCU_EVENT (1 << 25)
2262 #define DE_GTT_FAULT (1 << 24)
2263 #define DE_POISON (1 << 23)
2264 #define DE_PERFORM_COUNTER (1 << 22)
2265 #define DE_PCH_EVENT (1 << 21)
2266 #define DE_AUX_CHANNEL_A (1 << 20)
2267 #define DE_DP_A_HOTPLUG (1 << 19)
2268 #define DE_GSE (1 << 18)
2269 #define DE_PIPEB_VBLANK (1 << 15)
2270 #define DE_PIPEB_EVEN_FIELD (1 << 14)
2271 #define DE_PIPEB_ODD_FIELD (1 << 13)
2272 #define DE_PIPEB_LINE_COMPARE (1 << 12)
2273 #define DE_PIPEB_VSYNC (1 << 11)
2274 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2275 #define DE_PIPEA_VBLANK (1 << 7)
2276 #define DE_PIPEA_EVEN_FIELD (1 << 6)
2277 #define DE_PIPEA_ODD_FIELD (1 << 5)
2278 #define DE_PIPEA_LINE_COMPARE (1 << 4)
2279 #define DE_PIPEA_VSYNC (1 << 3)
2280 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2282 #define DEISR 0x44000
2283 #define DEIMR 0x44004
2284 #define DEIIR 0x44008
2285 #define DEIER 0x4400c
2288 #define GT_SYNC_STATUS (1 << 2)
2289 #define GT_USER_INTERRUPT (1 << 0)
2291 #define GTISR 0x44010
2292 #define GTIMR 0x44014
2293 #define GTIIR 0x44018
2294 #define GTIER 0x4401c
2296 #define DISP_ARB_CTL 0x45000
2297 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2301 /* south display engine interrupt */
2302 #define SDE_CRT_HOTPLUG (1 << 11)
2303 #define SDE_PORTD_HOTPLUG (1 << 10)
2304 #define SDE_PORTC_HOTPLUG (1 << 9)
2305 #define SDE_PORTB_HOTPLUG (1 << 8)
2306 #define SDE_SDVOB_HOTPLUG (1 << 6)
2307 #define SDE_HOTPLUG_MASK (0xf << 8)
2309 #define SDEISR 0xc4000
2310 #define SDEIMR 0xc4004
2311 #define SDEIIR 0xc4008
2312 #define SDEIER 0xc400c
2314 /* digital port hotplug */
2315 #define PCH_PORT_HOTPLUG 0xc4030
2316 #define PORTD_HOTPLUG_ENABLE (1 << 20)
2317 #define PORTD_PULSE_DURATION_2ms (0)
2318 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2319 #define PORTD_PULSE_DURATION_6ms (2 << 18)
2320 #define PORTD_PULSE_DURATION_100ms (3 << 18)
2321 #define PORTD_HOTPLUG_NO_DETECT (0)
2322 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2323 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2324 #define PORTC_HOTPLUG_ENABLE (1 << 12)
2325 #define PORTC_PULSE_DURATION_2ms (0)
2326 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2327 #define PORTC_PULSE_DURATION_6ms (2 << 10)
2328 #define PORTC_PULSE_DURATION_100ms (3 << 10)
2329 #define PORTC_HOTPLUG_NO_DETECT (0)
2330 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2331 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2332 #define PORTB_HOTPLUG_ENABLE (1 << 4)
2333 #define PORTB_PULSE_DURATION_2ms (0)
2334 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2335 #define PORTB_PULSE_DURATION_6ms (2 << 2)
2336 #define PORTB_PULSE_DURATION_100ms (3 << 2)
2337 #define PORTB_HOTPLUG_NO_DETECT (0)
2338 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2339 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2341 #define PCH_GPIOA 0xc5010
2342 #define PCH_GPIOB 0xc5014
2343 #define PCH_GPIOC 0xc5018
2344 #define PCH_GPIOD 0xc501c
2345 #define PCH_GPIOE 0xc5020
2346 #define PCH_GPIOF 0xc5024
2348 #define PCH_GMBUS0 0xc5100
2349 #define PCH_GMBUS1 0xc5104
2350 #define PCH_GMBUS2 0xc5108
2351 #define PCH_GMBUS3 0xc510c
2352 #define PCH_GMBUS4 0xc5110
2353 #define PCH_GMBUS5 0xc5120
2355 #define PCH_DPLL_A 0xc6014
2356 #define PCH_DPLL_B 0xc6018
2358 #define PCH_FPA0 0xc6040
2359 #define PCH_FPA1 0xc6044
2360 #define PCH_FPB0 0xc6048
2361 #define PCH_FPB1 0xc604c
2363 #define PCH_DPLL_TEST 0xc606c
2365 #define PCH_DREF_CONTROL 0xC6200
2366 #define DREF_CONTROL_MASK 0x7fc3
2367 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2368 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2369 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2370 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2371 #define DREF_SSC_SOURCE_DISABLE (0<<11)
2372 #define DREF_SSC_SOURCE_ENABLE (2<<11)
2373 #define DREF_SSC_SOURCE_MASK (3<<11)
2374 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2375 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2376 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2377 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2378 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2379 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2380 #define DREF_SSC4_DOWNSPREAD (0<<6)
2381 #define DREF_SSC4_CENTERSPREAD (1<<6)
2382 #define DREF_SSC1_DISABLE (0<<1)
2383 #define DREF_SSC1_ENABLE (1<<1)
2384 #define DREF_SSC4_DISABLE (0)
2385 #define DREF_SSC4_ENABLE (1)
2387 #define PCH_RAWCLK_FREQ 0xc6204
2388 #define FDL_TP1_TIMER_SHIFT 12
2389 #define FDL_TP1_TIMER_MASK (3<<12)
2390 #define FDL_TP2_TIMER_SHIFT 10
2391 #define FDL_TP2_TIMER_MASK (3<<10)
2392 #define RAWCLK_FREQ_MASK 0x3ff
2394 #define PCH_DPLL_TMR_CFG 0xc6208
2396 #define PCH_SSC4_PARMS 0xc6210
2397 #define PCH_SSC4_AUX_PARMS 0xc6214
2401 #define TRANS_HTOTAL_A 0xe0000
2402 #define TRANS_HTOTAL_SHIFT 16
2403 #define TRANS_HACTIVE_SHIFT 0
2404 #define TRANS_HBLANK_A 0xe0004
2405 #define TRANS_HBLANK_END_SHIFT 16
2406 #define TRANS_HBLANK_START_SHIFT 0
2407 #define TRANS_HSYNC_A 0xe0008
2408 #define TRANS_HSYNC_END_SHIFT 16
2409 #define TRANS_HSYNC_START_SHIFT 0
2410 #define TRANS_VTOTAL_A 0xe000c
2411 #define TRANS_VTOTAL_SHIFT 16
2412 #define TRANS_VACTIVE_SHIFT 0
2413 #define TRANS_VBLANK_A 0xe0010
2414 #define TRANS_VBLANK_END_SHIFT 16
2415 #define TRANS_VBLANK_START_SHIFT 0
2416 #define TRANS_VSYNC_A 0xe0014
2417 #define TRANS_VSYNC_END_SHIFT 16
2418 #define TRANS_VSYNC_START_SHIFT 0
2420 #define TRANSA_DATA_M1 0xe0030
2421 #define TRANSA_DATA_N1 0xe0034
2422 #define TRANSA_DATA_M2 0xe0038
2423 #define TRANSA_DATA_N2 0xe003c
2424 #define TRANSA_DP_LINK_M1 0xe0040
2425 #define TRANSA_DP_LINK_N1 0xe0044
2426 #define TRANSA_DP_LINK_M2 0xe0048
2427 #define TRANSA_DP_LINK_N2 0xe004c
2429 #define TRANS_HTOTAL_B 0xe1000
2430 #define TRANS_HBLANK_B 0xe1004
2431 #define TRANS_HSYNC_B 0xe1008
2432 #define TRANS_VTOTAL_B 0xe100c
2433 #define TRANS_VBLANK_B 0xe1010
2434 #define TRANS_VSYNC_B 0xe1014
2436 #define TRANSB_DATA_M1 0xe1030
2437 #define TRANSB_DATA_N1 0xe1034
2438 #define TRANSB_DATA_M2 0xe1038
2439 #define TRANSB_DATA_N2 0xe103c
2440 #define TRANSB_DP_LINK_M1 0xe1040
2441 #define TRANSB_DP_LINK_N1 0xe1044
2442 #define TRANSB_DP_LINK_M2 0xe1048
2443 #define TRANSB_DP_LINK_N2 0xe104c
2445 #define TRANSACONF 0xf0008
2446 #define TRANSBCONF 0xf1008
2447 #define TRANS_DISABLE (0<<31)
2448 #define TRANS_ENABLE (1<<31)
2449 #define TRANS_STATE_MASK (1<<30)
2450 #define TRANS_STATE_DISABLE (0<<30)
2451 #define TRANS_STATE_ENABLE (1<<30)
2452 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
2453 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
2454 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
2455 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
2456 #define TRANS_DP_AUDIO_ONLY (1<<26)
2457 #define TRANS_DP_VIDEO_AUDIO (0<<26)
2458 #define TRANS_PROGRESSIVE (0<<21)
2459 #define TRANS_8BPC (0<<5)
2460 #define TRANS_10BPC (1<<5)
2461 #define TRANS_6BPC (2<<5)
2462 #define TRANS_12BPC (3<<5)
2464 #define FDI_RXA_CHICKEN 0xc200c
2465 #define FDI_RXB_CHICKEN 0xc2010
2466 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
2469 #define FDI_TXA_CTL 0x60100
2470 #define FDI_TXB_CTL 0x61100
2471 #define FDI_TX_DISABLE (0<<31)
2472 #define FDI_TX_ENABLE (1<<31)
2473 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
2474 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
2475 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
2476 #define FDI_LINK_TRAIN_NONE (3<<28)
2477 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
2478 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
2479 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
2480 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
2481 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
2482 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
2483 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
2484 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
2485 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
2486 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
2487 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
2488 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
2489 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
2490 /* Ironlake: hardwired to 1 */
2491 #define FDI_TX_PLL_ENABLE (1<<14)
2492 /* both Tx and Rx */
2493 #define FDI_SCRAMBLING_ENABLE (0<<7)
2494 #define FDI_SCRAMBLING_DISABLE (1<<7)
2496 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2497 #define FDI_RXA_CTL 0xf000c
2498 #define FDI_RXB_CTL 0xf100c
2499 #define FDI_RX_ENABLE (1<<31)
2500 #define FDI_RX_DISABLE (0<<31)
2501 /* train, dp width same as FDI_TX */
2502 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
2503 #define FDI_8BPC (0<<16)
2504 #define FDI_10BPC (1<<16)
2505 #define FDI_6BPC (2<<16)
2506 #define FDI_12BPC (3<<16)
2507 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2508 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2509 #define FDI_RX_PLL_ENABLE (1<<13)
2510 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2511 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2512 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2513 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2514 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2515 #define FDI_SEL_RAWCLK (0<<4)
2516 #define FDI_SEL_PCDCLK (1<<4)
2518 #define FDI_RXA_MISC 0xf0010
2519 #define FDI_RXB_MISC 0xf1010
2520 #define FDI_RXA_TUSIZE1 0xf0030
2521 #define FDI_RXA_TUSIZE2 0xf0038
2522 #define FDI_RXB_TUSIZE1 0xf1030
2523 #define FDI_RXB_TUSIZE2 0xf1038
2525 /* FDI_RX interrupt register format */
2526 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
2527 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2528 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2529 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2530 #define FDI_RX_FS_CODE_ERR (1<<6)
2531 #define FDI_RX_FE_CODE_ERR (1<<5)
2532 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2533 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
2534 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2535 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2536 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2538 #define FDI_RXA_IIR 0xf0014
2539 #define FDI_RXA_IMR 0xf0018
2540 #define FDI_RXB_IIR 0xf1014
2541 #define FDI_RXB_IMR 0xf1018
2543 #define FDI_PLL_CTL_1 0xfe000
2544 #define FDI_PLL_CTL_2 0xfe004
2547 #define PCH_ADPA 0xe1100
2548 #define ADPA_TRANS_SELECT_MASK (1<<30)
2549 #define ADPA_TRANS_A_SELECT 0
2550 #define ADPA_TRANS_B_SELECT (1<<30)
2551 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2552 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2553 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2554 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2555 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2556 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2557 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2558 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2559 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2560 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2561 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2562 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2563 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2564 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2565 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2566 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2567 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2568 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2569 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2572 #define HDMIB 0xe1140
2573 #define PORT_ENABLE (1 << 31)
2574 #define TRANSCODER_A (0)
2575 #define TRANSCODER_B (1 << 30)
2576 #define COLOR_FORMAT_8bpc (0)
2577 #define COLOR_FORMAT_12bpc (3 << 26)
2578 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
2579 #define SDVO_ENCODING (0)
2580 #define TMDS_ENCODING (2 << 10)
2581 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2582 #define SDVOB_BORDER_ENABLE (1 << 7)
2583 #define AUDIO_ENABLE (1 << 6)
2584 #define VSYNC_ACTIVE_HIGH (1 << 4)
2585 #define HSYNC_ACTIVE_HIGH (1 << 3)
2586 #define PORT_DETECTED (1 << 2)
2588 #define HDMIC 0xe1150
2589 #define HDMID 0xe1160
2591 #define PCH_LVDS 0xe1180
2592 #define LVDS_DETECTED (1 << 1)
2594 #define BLC_PWM_CPU_CTL2 0x48250
2595 #define PWM_ENABLE (1 << 31)
2596 #define PWM_PIPE_A (0 << 29)
2597 #define PWM_PIPE_B (1 << 29)
2598 #define BLC_PWM_CPU_CTL 0x48254
2600 #define BLC_PWM_PCH_CTL1 0xc8250
2601 #define PWM_PCH_ENABLE (1 << 31)
2602 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2603 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2604 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2605 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2607 #define BLC_PWM_PCH_CTL2 0xc8254
2609 #define PCH_PP_STATUS 0xc7200
2610 #define PCH_PP_CONTROL 0xc7204
2611 #define EDP_FORCE_VDD (1 << 3)
2612 #define EDP_BLC_ENABLE (1 << 2)
2613 #define PANEL_POWER_RESET (1 << 1)
2614 #define PANEL_POWER_OFF (0 << 0)
2615 #define PANEL_POWER_ON (1 << 0)
2616 #define PCH_PP_ON_DELAYS 0xc7208
2617 #define EDP_PANEL (1 << 30)
2618 #define PCH_PP_OFF_DELAYS 0xc720c
2619 #define PCH_PP_DIVISOR 0xc7210
2621 #define PCH_DP_B 0xe4100
2622 #define PCH_DPB_AUX_CH_CTL 0xe4110
2623 #define PCH_DPB_AUX_CH_DATA1 0xe4114
2624 #define PCH_DPB_AUX_CH_DATA2 0xe4118
2625 #define PCH_DPB_AUX_CH_DATA3 0xe411c
2626 #define PCH_DPB_AUX_CH_DATA4 0xe4120
2627 #define PCH_DPB_AUX_CH_DATA5 0xe4124
2629 #define PCH_DP_C 0xe4200
2630 #define PCH_DPC_AUX_CH_CTL 0xe4210
2631 #define PCH_DPC_AUX_CH_DATA1 0xe4214
2632 #define PCH_DPC_AUX_CH_DATA2 0xe4218
2633 #define PCH_DPC_AUX_CH_DATA3 0xe421c
2634 #define PCH_DPC_AUX_CH_DATA4 0xe4220
2635 #define PCH_DPC_AUX_CH_DATA5 0xe4224
2637 #define PCH_DP_D 0xe4300
2638 #define PCH_DPD_AUX_CH_CTL 0xe4310
2639 #define PCH_DPD_AUX_CH_DATA1 0xe4314
2640 #define PCH_DPD_AUX_CH_DATA2 0xe4318
2641 #define PCH_DPD_AUX_CH_DATA3 0xe431c
2642 #define PCH_DPD_AUX_CH_DATA4 0xe4320
2643 #define PCH_DPD_AUX_CH_DATA5 0xe4324
2645 #endif /* _I915_REG_H_ */
git.openpandora.org / pandora-kernel.git / blob