drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #define MAX_NOPID ((u32)~0)
  38
  39 /**
  40  * Interrupts that are always left unmasked.
  41  *
  42  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  43  * we leave them always unmasked in IMR and then control enabling them through
  44  * PIPESTAT alone.
  45  */
  46 #define I915_INTERRUPT_ENABLE_FIX                       \
  47         (I915_ASLE_INTERRUPT |                          \
  48          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  49          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  51          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  52          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  53
  54 /** Interrupts that we mask and unmask at runtime. */
  55 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  56
  57 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  58                                  PIPE_VBLANK_INTERRUPT_STATUS)
  59
  60 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  61                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  62
  63 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  64                                          DRM_I915_VBLANK_PIPE_B)
  65
  66 void
  67 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  68 {
  69         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  70                 dev_priv->gt_irq_mask_reg &= ~mask;
  71                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  72                 (void) I915_READ(GTIMR);
  73         }
  74 }
  75
  76 static inline void
  77 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  78 {
  79         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  80                 dev_priv->gt_irq_mask_reg |= mask;
  81                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  82                 (void) I915_READ(GTIMR);
  83         }
  84 }
  85
  86 /* For display hotplug interrupt */
  87 void
  88 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  89 {
  90         if ((dev_priv->irq_mask_reg & mask) != 0) {
  91                 dev_priv->irq_mask_reg &= ~mask;
  92                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  93                 (void) I915_READ(DEIMR);
  94         }
  95 }
  96
  97 static inline void
  98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  99 {
 100         if ((dev_priv->irq_mask_reg & mask) != mask) {
 101                 dev_priv->irq_mask_reg |= mask;
 102                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 103                 (void) I915_READ(DEIMR);
 104         }
 105 }
 106
 107 void
 108 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 109 {
 110         if ((dev_priv->irq_mask_reg & mask) != 0) {
 111                 dev_priv->irq_mask_reg &= ~mask;
 112                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 113                 (void) I915_READ(IMR);
 114         }
 115 }
 116
 117 static inline void
 118 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 119 {
 120         if ((dev_priv->irq_mask_reg & mask) != mask) {
 121                 dev_priv->irq_mask_reg |= mask;
 122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 123                 (void) I915_READ(IMR);
 124         }
 125 }
 126
 127 static inline u32
 128 i915_pipestat(int pipe)
 129 {
 130         if (pipe == 0)
 131                 return PIPEASTAT;
 132         if (pipe == 1)
 133                 return PIPEBSTAT;
 134         BUG();
 135 }
 136
 137 void
 138 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 139 {
 140         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 141                 u32 reg = i915_pipestat(pipe);
 142
 143                 dev_priv->pipestat[pipe] |= mask;
 144                 /* Enable the interrupt, clear any pending status */
 145                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 146                 (void) I915_READ(reg);
 147         }
 148 }
 149
 150 void
 151 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 152 {
 153         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 154                 u32 reg = i915_pipestat(pipe);
 155
 156                 dev_priv->pipestat[pipe] &= ~mask;
 157                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 158                 (void) I915_READ(reg);
 159         }
 160 }
 161
 162 /**
 163  * intel_enable_asle - enable ASLE interrupt for OpRegion
 164  */
 165 void intel_enable_asle (struct drm_device *dev)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168
 169         if (HAS_PCH_SPLIT(dev))
 170                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 171         else
 172                 i915_enable_pipestat(dev_priv, 1,
 173                                      I915_LEGACY_BLC_EVENT_ENABLE);
 174 }
 175
 176 /**
 177  * i915_pipe_enabled - check if a pipe is enabled
 178  * @dev: DRM device
 179  * @pipe: pipe to check
 180  *
 181  * Reading certain registers when the pipe is disabled can hang the chip.
 182  * Use this routine to make sure the PLL is running and the pipe is active
 183  * before reading such registers if unsure.
 184  */
 185 static int
 186 i915_pipe_enabled(struct drm_device *dev, int pipe)
 187 {
 188         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 189         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 190
 191         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 192                 return 1;
 193
 194         return 0;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low, count;
 206
 207         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 208         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 212                                 "pipe %d\n", pipe);
 213                 return 0;
 214         }
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 223                          PIPE_FRAME_HIGH_SHIFT);
 224                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 225                         PIPE_FRAME_LOW_SHIFT);
 226                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 227                          PIPE_FRAME_HIGH_SHIFT);
 228         } while (high1 != high2);
 229
 230         count = (high1 << 8) | low;
 231
 232         return count;
 233 }
 234
 235 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 236 {
 237         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 238         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 239
 240         if (!i915_pipe_enabled(dev, pipe)) {
 241                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 242                                         "pipe %d\n", pipe);
 243                 return 0;
 244         }
 245
 246         return I915_READ(reg);
 247 }
 248
 249 /*
 250  * Handle hotplug events outside the interrupt handler proper.
 251  */
 252 static void i915_hotplug_work_func(struct work_struct *work)
 253 {
 254         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 255                                                     hotplug_work);
 256         struct drm_device *dev = dev_priv->dev;
 257         struct drm_mode_config *mode_config = &dev->mode_config;
 258         struct drm_connector *connector;
 259
 260         if (mode_config->num_connector) {
 261                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 262                         struct intel_output *intel_output = to_intel_output(connector);
 263
 264                         if (intel_output->hot_plug)
 265                                 (*intel_output->hot_plug) (intel_output);
 266                 }
 267         }
 268         /* Just fire off a uevent and let userspace tell us what to do */
 269         drm_sysfs_hotplug_event(dev);
 270 }
 271
 272 static void i915_handle_rps_change(struct drm_device *dev)
 273 {
 274         drm_i915_private_t *dev_priv = dev->dev_private;
 275         u32 busy_up, busy_down, max_avg, min_avg;
 276         u16 rgvswctl;
 277         u8 new_delay = dev_priv->cur_delay;
 278
 279         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
 280         busy_up = I915_READ(RCPREVBSYTUPAVG);
 281         busy_down = I915_READ(RCPREVBSYTDNAVG);
 282         max_avg = I915_READ(RCBMAXAVG);
 283         min_avg = I915_READ(RCBMINAVG);
 284
 285         /* Handle RCS change request from hw */
 286         if (busy_up > max_avg) {
 287                 if (dev_priv->cur_delay != dev_priv->max_delay)
 288                         new_delay = dev_priv->cur_delay - 1;
 289                 if (new_delay < dev_priv->max_delay)
 290                         new_delay = dev_priv->max_delay;
 291         } else if (busy_down < min_avg) {
 292                 if (dev_priv->cur_delay != dev_priv->min_delay)
 293                         new_delay = dev_priv->cur_delay + 1;
 294                 if (new_delay > dev_priv->min_delay)
 295                         new_delay = dev_priv->min_delay;
 296         }
 297
 298         DRM_DEBUG("rps change requested: %d -> %d\n",
 299                   dev_priv->cur_delay, new_delay);
 300
 301         rgvswctl = I915_READ(MEMSWCTL);
 302         if (rgvswctl & MEMCTL_CMD_STS) {
 303                 DRM_ERROR("gpu busy, RCS change rejected\n");
 304                 return; /* still busy with another command */
 305         }
 306
 307         /* Program the new state */
 308         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 309                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 310         I915_WRITE(MEMSWCTL, rgvswctl);
 311         POSTING_READ(MEMSWCTL);
 312
 313         rgvswctl |= MEMCTL_CMD_STS;
 314         I915_WRITE(MEMSWCTL, rgvswctl);
 315
 316         dev_priv->cur_delay = new_delay;
 317
 318         DRM_DEBUG("rps changed\n");
 319
 320         return;
 321 }
 322
 323 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 324 {
 325         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 326         int ret = IRQ_NONE;
 327         u32 de_iir, gt_iir, de_ier, pch_iir;
 328         struct drm_i915_master_private *master_priv;
 329
 330         /* disable master interrupt before clearing iir  */
 331         de_ier = I915_READ(DEIER);
 332         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 333         (void)I915_READ(DEIER);
 334
 335         de_iir = I915_READ(DEIIR);
 336         gt_iir = I915_READ(GTIIR);
 337         pch_iir = I915_READ(SDEIIR);
 338
 339         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 340                 goto done;
 341
 342         ret = IRQ_HANDLED;
 343
 344         if (dev->primary->master) {
 345                 master_priv = dev->primary->master->driver_priv;
 346                 if (master_priv->sarea_priv)
 347                         master_priv->sarea_priv->last_dispatch =
 348                                 READ_BREADCRUMB(dev_priv);
 349         }
 350
 351         if (gt_iir & GT_USER_INTERRUPT) {
 352                 u32 seqno = i915_get_gem_seqno(dev);
 353                 dev_priv->mm.irq_gem_seqno = seqno;
 354                 trace_i915_gem_request_complete(dev, seqno);
 355                 DRM_WAKEUP(&dev_priv->irq_queue);
 356                 dev_priv->hangcheck_count = 0;
 357                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 358         }
 359
 360         if (de_iir & DE_GSE)
 361                 ironlake_opregion_gse_intr(dev);
 362
 363         if (de_iir & DE_PLANEA_FLIP_DONE) {
 364                 intel_prepare_page_flip(dev, 0);
 365                 intel_finish_page_flip(dev, 0);
 366         }
 367
 368         if (de_iir & DE_PLANEB_FLIP_DONE) {
 369                 intel_prepare_page_flip(dev, 1);
 370                 intel_finish_page_flip(dev, 1);
 371         }
 372
 373         if (de_iir & DE_PIPEA_VBLANK)
 374                 drm_handle_vblank(dev, 0);
 375
 376         if (de_iir & DE_PIPEB_VBLANK)
 377                 drm_handle_vblank(dev, 1);
 378
 379         /* check event from PCH */
 380         if ((de_iir & DE_PCH_EVENT) &&
 381             (pch_iir & SDE_HOTPLUG_MASK)) {
 382                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 383         }
 384
 385         if (de_iir & DE_PCU_EVENT) {
 386                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
 387                 i915_handle_rps_change(dev);
 388         }
 389
 390         /* should clear PCH hotplug event before clear CPU irq */
 391         I915_WRITE(SDEIIR, pch_iir);
 392         I915_WRITE(GTIIR, gt_iir);
 393         I915_WRITE(DEIIR, de_iir);
 394
 395 done:
 396         I915_WRITE(DEIER, de_ier);
 397         (void)I915_READ(DEIER);
 398
 399         return ret;
 400 }
 401
 402 /**
 403  * i915_error_work_func - do process context error handling work
 404  * @work: work struct
 405  *
 406  * Fire an error uevent so userspace can see that a hang or error
 407  * was detected.
 408  */
 409 static void i915_error_work_func(struct work_struct *work)
 410 {
 411         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 412                                                     error_work);
 413         struct drm_device *dev = dev_priv->dev;
 414         char *error_event[] = { "ERROR=1", NULL };
 415         char *reset_event[] = { "RESET=1", NULL };
 416         char *reset_done_event[] = { "ERROR=0", NULL };
 417
 418         DRM_DEBUG_DRIVER("generating error event\n");
 419         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 420
 421         if (atomic_read(&dev_priv->mm.wedged)) {
 422                 if (IS_I965G(dev)) {
 423                         DRM_DEBUG_DRIVER("resetting chip\n");
 424                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 425                         if (!i965_reset(dev, GDRST_RENDER)) {
 426                                 atomic_set(&dev_priv->mm.wedged, 0);
 427                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 428                         }
 429                 } else {
 430                         DRM_DEBUG_DRIVER("reboot required\n");
 431                 }
 432         }
 433 }
 434
 435 static struct drm_i915_error_object *
 436 i915_error_object_create(struct drm_device *dev,
 437                          struct drm_gem_object *src)
 438 {
 439         struct drm_i915_error_object *dst;
 440         struct drm_i915_gem_object *src_priv;
 441         int page, page_count;
 442
 443         if (src == NULL)
 444                 return NULL;
 445
 446         src_priv = src->driver_private;
 447         if (src_priv->pages == NULL)
 448                 return NULL;
 449
 450         page_count = src->size / PAGE_SIZE;
 451
 452         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 453         if (dst == NULL)
 454                 return NULL;
 455
 456         for (page = 0; page < page_count; page++) {
 457                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 458                 if (d == NULL)
 459                         goto unwind;
 460                 s = kmap_atomic(src_priv->pages[page], KM_USER0);
 461                 memcpy(d, s, PAGE_SIZE);
 462                 kunmap_atomic(s, KM_USER0);
 463                 dst->pages[page] = d;
 464         }
 465         dst->page_count = page_count;
 466         dst->gtt_offset = src_priv->gtt_offset;
 467
 468         return dst;
 469
 470 unwind:
 471         while (page--)
 472                 kfree(dst->pages[page]);
 473         kfree(dst);
 474         return NULL;
 475 }
 476
 477 static void
 478 i915_error_object_free(struct drm_i915_error_object *obj)
 479 {
 480         int page;
 481
 482         if (obj == NULL)
 483                 return;
 484
 485         for (page = 0; page < obj->page_count; page++)
 486                 kfree(obj->pages[page]);
 487
 488         kfree(obj);
 489 }
 490
 491 static void
 492 i915_error_state_free(struct drm_device *dev,
 493                       struct drm_i915_error_state *error)
 494 {
 495         i915_error_object_free(error->batchbuffer[0]);
 496         i915_error_object_free(error->batchbuffer[1]);
 497         i915_error_object_free(error->ringbuffer);
 498         kfree(error->active_bo);
 499         kfree(error);
 500 }
 501
 502 static u32
 503 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 504 {
 505         u32 cmd;
 506
 507         if (IS_I830(dev) || IS_845G(dev))
 508                 cmd = MI_BATCH_BUFFER;
 509         else if (IS_I965G(dev))
 510                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 511                        MI_BATCH_NON_SECURE_I965);
 512         else
 513                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 514
 515         return ring[0] == cmd ? ring[1] : 0;
 516 }
 517
 518 static u32
 519 i915_ringbuffer_last_batch(struct drm_device *dev)
 520 {
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         u32 head, bbaddr;
 523         u32 *ring;
 524
 525         /* Locate the current position in the ringbuffer and walk back
 526          * to find the most recently dispatched batch buffer.
 527          */
 528         bbaddr = 0;
 529         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 530         ring = (u32 *)(dev_priv->ring.virtual_start + head);
 531
 532         while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 533                 bbaddr = i915_get_bbaddr(dev, ring);
 534                 if (bbaddr)
 535                         break;
 536         }
 537
 538         if (bbaddr == 0) {
 539                 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
 540                 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 541                         bbaddr = i915_get_bbaddr(dev, ring);
 542                         if (bbaddr)
 543                                 break;
 544                 }
 545         }
 546
 547         return bbaddr;
 548 }
 549
 550 /**
 551  * i915_capture_error_state - capture an error record for later analysis
 552  * @dev: drm device
 553  *
 554  * Should be called when an error is detected (either a hang or an error
 555  * interrupt) to capture error state from the time of the error.  Fills
 556  * out a structure which becomes available in debugfs for user level tools
 557  * to pick up.
 558  */
 559 static void i915_capture_error_state(struct drm_device *dev)
 560 {
 561         struct drm_i915_private *dev_priv = dev->dev_private;
 562         struct drm_i915_gem_object *obj_priv;
 563         struct drm_i915_error_state *error;
 564         struct drm_gem_object *batchbuffer[2];
 565         unsigned long flags;
 566         u32 bbaddr;
 567         int count;
 568
 569         spin_lock_irqsave(&dev_priv->error_lock, flags);
 570         error = dev_priv->first_error;
 571         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 572         if (error)
 573                 return;
 574
 575         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 576         if (!error) {
 577                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 578                 return;
 579         }
 580
 581         error->seqno = i915_get_gem_seqno(dev);
 582         error->eir = I915_READ(EIR);
 583         error->pgtbl_er = I915_READ(PGTBL_ER);
 584         error->pipeastat = I915_READ(PIPEASTAT);
 585         error->pipebstat = I915_READ(PIPEBSTAT);
 586         error->instpm = I915_READ(INSTPM);
 587         if (!IS_I965G(dev)) {
 588                 error->ipeir = I915_READ(IPEIR);
 589                 error->ipehr = I915_READ(IPEHR);
 590                 error->instdone = I915_READ(INSTDONE);
 591                 error->acthd = I915_READ(ACTHD);
 592                 error->bbaddr = 0;
 593         } else {
 594                 error->ipeir = I915_READ(IPEIR_I965);
 595                 error->ipehr = I915_READ(IPEHR_I965);
 596                 error->instdone = I915_READ(INSTDONE_I965);
 597                 error->instps = I915_READ(INSTPS);
 598                 error->instdone1 = I915_READ(INSTDONE1);
 599                 error->acthd = I915_READ(ACTHD_I965);
 600                 error->bbaddr = I915_READ64(BB_ADDR);
 601         }
 602
 603         bbaddr = i915_ringbuffer_last_batch(dev);
 604
 605         /* Grab the current batchbuffer, most likely to have crashed. */
 606         batchbuffer[0] = NULL;
 607         batchbuffer[1] = NULL;
 608         count = 0;
 609         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 610                 struct drm_gem_object *obj = obj_priv->obj;
 611
 612                 if (batchbuffer[0] == NULL &&
 613                     bbaddr >= obj_priv->gtt_offset &&
 614                     bbaddr < obj_priv->gtt_offset + obj->size)
 615                         batchbuffer[0] = obj;
 616
 617                 if (batchbuffer[1] == NULL &&
 618                     error->acthd >= obj_priv->gtt_offset &&
 619                     error->acthd < obj_priv->gtt_offset + obj->size &&
 620                     batchbuffer[0] != obj)
 621                         batchbuffer[1] = obj;
 622
 623                 count++;
 624         }
 625
 626         /* We need to copy these to an anonymous buffer as the simplest
 627          * method to avoid being overwritten by userpace.
 628          */
 629         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 630         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 631
 632         /* Record the ringbuffer */
 633         error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
 634
 635         /* Record buffers on the active list. */
 636         error->active_bo = NULL;
 637         error->active_bo_count = 0;
 638
 639         if (count)
 640                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 641                                            GFP_ATOMIC);
 642
 643         if (error->active_bo) {
 644                 int i = 0;
 645                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 646                         struct drm_gem_object *obj = obj_priv->obj;
 647
 648                         error->active_bo[i].size = obj->size;
 649                         error->active_bo[i].name = obj->name;
 650                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 651                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 652                         error->active_bo[i].read_domains = obj->read_domains;
 653                         error->active_bo[i].write_domain = obj->write_domain;
 654                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 655                         error->active_bo[i].pinned = 0;
 656                         if (obj_priv->pin_count > 0)
 657                                 error->active_bo[i].pinned = 1;
 658                         if (obj_priv->user_pin_count > 0)
 659                                 error->active_bo[i].pinned = -1;
 660                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 661                         error->active_bo[i].dirty = obj_priv->dirty;
 662                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 663
 664                         if (++i == count)
 665                                 break;
 666                 }
 667                 error->active_bo_count = i;
 668         }
 669
 670         do_gettimeofday(&error->time);
 671
 672         spin_lock_irqsave(&dev_priv->error_lock, flags);
 673         if (dev_priv->first_error == NULL) {
 674                 dev_priv->first_error = error;
 675                 error = NULL;
 676         }
 677         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 678
 679         if (error)
 680                 i915_error_state_free(dev, error);
 681 }
 682
 683 void i915_destroy_error_state(struct drm_device *dev)
 684 {
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct drm_i915_error_state *error;
 687
 688         spin_lock(&dev_priv->error_lock);
 689         error = dev_priv->first_error;
 690         dev_priv->first_error = NULL;
 691         spin_unlock(&dev_priv->error_lock);
 692
 693         if (error)
 694                 i915_error_state_free(dev, error);
 695 }
 696
 697 /**
 698  * i915_handle_error - handle an error interrupt
 699  * @dev: drm device
 700  *
 701  * Do some basic checking of regsiter state at error interrupt time and
 702  * dump it to the syslog.  Also call i915_capture_error_state() to make
 703  * sure we get a record and make it available in debugfs.  Fire a uevent
 704  * so userspace knows something bad happened (should trigger collection
 705  * of a ring dump etc.).
 706  */
 707 static void i915_handle_error(struct drm_device *dev, bool wedged)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         u32 eir = I915_READ(EIR);
 711         u32 pipea_stats = I915_READ(PIPEASTAT);
 712         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 713
 714         i915_capture_error_state(dev);
 715
 716         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 717                eir);
 718
 719         if (IS_G4X(dev)) {
 720                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 721                         u32 ipeir = I915_READ(IPEIR_I965);
 722
 723                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 724                                I915_READ(IPEIR_I965));
 725                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 726                                I915_READ(IPEHR_I965));
 727                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 728                                I915_READ(INSTDONE_I965));
 729                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 730                                I915_READ(INSTPS));
 731                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 732                                I915_READ(INSTDONE1));
 733                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 734                                I915_READ(ACTHD_I965));
 735                         I915_WRITE(IPEIR_I965, ipeir);
 736                         (void)I915_READ(IPEIR_I965);
 737                 }
 738                 if (eir & GM45_ERROR_PAGE_TABLE) {
 739                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 740                         printk(KERN_ERR "page table error\n");
 741                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 742                                pgtbl_err);
 743                         I915_WRITE(PGTBL_ER, pgtbl_err);
 744                         (void)I915_READ(PGTBL_ER);
 745                 }
 746         }
 747
 748         if (IS_I9XX(dev)) {
 749                 if (eir & I915_ERROR_PAGE_TABLE) {
 750                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 751                         printk(KERN_ERR "page table error\n");
 752                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 753                                pgtbl_err);
 754                         I915_WRITE(PGTBL_ER, pgtbl_err);
 755                         (void)I915_READ(PGTBL_ER);
 756                 }
 757         }
 758
 759         if (eir & I915_ERROR_MEMORY_REFRESH) {
 760                 printk(KERN_ERR "memory refresh error\n");
 761                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 762                        pipea_stats);
 763                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 764                        pipeb_stats);
 765                 /* pipestat has already been acked */
 766         }
 767         if (eir & I915_ERROR_INSTRUCTION) {
 768                 printk(KERN_ERR "instruction error\n");
 769                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 770                        I915_READ(INSTPM));
 771                 if (!IS_I965G(dev)) {
 772                         u32 ipeir = I915_READ(IPEIR);
 773
 774                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 775                                I915_READ(IPEIR));
 776                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 777                                I915_READ(IPEHR));
 778                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 779                                I915_READ(INSTDONE));
 780                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 781                                I915_READ(ACTHD));
 782                         I915_WRITE(IPEIR, ipeir);
 783                         (void)I915_READ(IPEIR);
 784                 } else {
 785                         u32 ipeir = I915_READ(IPEIR_I965);
 786
 787                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 788                                I915_READ(IPEIR_I965));
 789                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 790                                I915_READ(IPEHR_I965));
 791                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 792                                I915_READ(INSTDONE_I965));
 793                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 794                                I915_READ(INSTPS));
 795                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 796                                I915_READ(INSTDONE1));
 797                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 798                                I915_READ(ACTHD_I965));
 799                         I915_WRITE(IPEIR_I965, ipeir);
 800                         (void)I915_READ(IPEIR_I965);
 801                 }
 802         }
 803
 804         I915_WRITE(EIR, eir);
 805         (void)I915_READ(EIR);
 806         eir = I915_READ(EIR);
 807         if (eir) {
 808                 /*
 809                  * some errors might have become stuck,
 810                  * mask them.
 811                  */
 812                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 813                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 814                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 815         }
 816
 817         if (wedged) {
 818                 atomic_set(&dev_priv->mm.wedged, 1);
 819
 820                 /*
 821                  * Wakeup waiting processes so they don't hang
 822                  */
 823                 DRM_WAKEUP(&dev_priv->irq_queue);
 824         }
 825
 826         queue_work(dev_priv->wq, &dev_priv->error_work);
 827 }
 828
 829 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 830 {
 831         struct drm_device *dev = (struct drm_device *) arg;
 832         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 833         struct drm_i915_master_private *master_priv;
 834         u32 iir, new_iir;
 835         u32 pipea_stats, pipeb_stats;
 836         u32 vblank_status;
 837         u32 vblank_enable;
 838         int vblank = 0;
 839         unsigned long irqflags;
 840         int irq_received;
 841         int ret = IRQ_NONE;
 842
 843         atomic_inc(&dev_priv->irq_received);
 844
 845         if (HAS_PCH_SPLIT(dev))
 846                 return ironlake_irq_handler(dev);
 847
 848         iir = I915_READ(IIR);
 849
 850         if (IS_I965G(dev)) {
 851                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 852                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 853         } else {
 854                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 855                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 856         }
 857
 858         for (;;) {
 859                 irq_received = iir != 0;
 860
 861                 /* Can't rely on pipestat interrupt bit in iir as it might
 862                  * have been cleared after the pipestat interrupt was received.
 863                  * It doesn't set the bit in iir again, but it still produces
 864                  * interrupts (for non-MSI).
 865                  */
 866                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 867                 pipea_stats = I915_READ(PIPEASTAT);
 868                 pipeb_stats = I915_READ(PIPEBSTAT);
 869
 870                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 871                         i915_handle_error(dev, false);
 872
 873                 /*
 874                  * Clear the PIPE(A|B)STAT regs before the IIR
 875                  */
 876                 if (pipea_stats & 0x8000ffff) {
 877                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 878                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 879                         I915_WRITE(PIPEASTAT, pipea_stats);
 880                         irq_received = 1;
 881                 }
 882
 883                 if (pipeb_stats & 0x8000ffff) {
 884                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 885                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 886                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 887                         irq_received = 1;
 888                 }
 889                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 890
 891                 if (!irq_received)
 892                         break;
 893
 894                 ret = IRQ_HANDLED;
 895
 896                 /* Consume port.  Then clear IIR or we'll miss events */
 897                 if ((I915_HAS_HOTPLUG(dev)) &&
 898                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 899                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 900
 901                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 902                                   hotplug_status);
 903                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 904                                 queue_work(dev_priv->wq,
 905                                            &dev_priv->hotplug_work);
 906
 907                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 908                         I915_READ(PORT_HOTPLUG_STAT);
 909                 }
 910
 911                 I915_WRITE(IIR, iir);
 912                 new_iir = I915_READ(IIR); /* Flush posted writes */
 913
 914                 if (dev->primary->master) {
 915                         master_priv = dev->primary->master->driver_priv;
 916                         if (master_priv->sarea_priv)
 917                                 master_priv->sarea_priv->last_dispatch =
 918                                         READ_BREADCRUMB(dev_priv);
 919                 }
 920
 921                 if (iir & I915_USER_INTERRUPT) {
 922                         u32 seqno = i915_get_gem_seqno(dev);
 923                         dev_priv->mm.irq_gem_seqno = seqno;
 924                         trace_i915_gem_request_complete(dev, seqno);
 925                         DRM_WAKEUP(&dev_priv->irq_queue);
 926                         dev_priv->hangcheck_count = 0;
 927                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 928                 }
 929
 930                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 931                         intel_prepare_page_flip(dev, 0);
 932
 933                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 934                         intel_prepare_page_flip(dev, 1);
 935
 936                 if (pipea_stats & vblank_status) {
 937                         vblank++;
 938                         drm_handle_vblank(dev, 0);
 939                         intel_finish_page_flip(dev, 0);
 940                 }
 941
 942                 if (pipeb_stats & vblank_status) {
 943                         vblank++;
 944                         drm_handle_vblank(dev, 1);
 945                         intel_finish_page_flip(dev, 1);
 946                 }
 947
 948                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 949                     (iir & I915_ASLE_INTERRUPT))
 950                         opregion_asle_intr(dev);
 951
 952                 /* With MSI, interrupts are only generated when iir
 953                  * transitions from zero to nonzero.  If another bit got
 954                  * set while we were handling the existing iir bits, then
 955                  * we would never get another interrupt.
 956                  *
 957                  * This is fine on non-MSI as well, as if we hit this path
 958                  * we avoid exiting the interrupt handler only to generate
 959                  * another one.
 960                  *
 961                  * Note that for MSI this could cause a stray interrupt report
 962                  * if an interrupt landed in the time between writing IIR and
 963                  * the posting read.  This should be rare enough to never
 964                  * trigger the 99% of 100,000 interrupts test for disabling
 965                  * stray interrupts.
 966                  */
 967                 iir = new_iir;
 968         }
 969
 970         return ret;
 971 }
 972
 973 static int i915_emit_irq(struct drm_device * dev)
 974 {
 975         drm_i915_private_t *dev_priv = dev->dev_private;
 976         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 977         RING_LOCALS;
 978
 979         i915_kernel_lost_context(dev);
 980
 981         DRM_DEBUG_DRIVER("\n");
 982
 983         dev_priv->counter++;
 984         if (dev_priv->counter > 0x7FFFFFFFUL)
 985                 dev_priv->counter = 1;
 986         if (master_priv->sarea_priv)
 987                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 988
 989         BEGIN_LP_RING(4);
 990         OUT_RING(MI_STORE_DWORD_INDEX);
 991         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 992         OUT_RING(dev_priv->counter);
 993         OUT_RING(MI_USER_INTERRUPT);
 994         ADVANCE_LP_RING();
 995
 996         return dev_priv->counter;
 997 }
 998
 999 void i915_user_irq_get(struct drm_device *dev)
1000 {
1001         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1002         unsigned long irqflags;
1003
1004         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1005         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
1006                 if (HAS_PCH_SPLIT(dev))
1007                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
1008                 else
1009                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1010         }
1011         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1012 }
1013
1014 void i915_user_irq_put(struct drm_device *dev)
1015 {
1016         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1017         unsigned long irqflags;
1018
1019         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1020         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
1021         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
1022                 if (HAS_PCH_SPLIT(dev))
1023                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
1024                 else
1025                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1026         }
1027         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1028 }
1029
1030 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1031 {
1032         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1033
1034         if (dev_priv->trace_irq_seqno == 0)
1035                 i915_user_irq_get(dev);
1036
1037         dev_priv->trace_irq_seqno = seqno;
1038 }
1039
1040 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1041 {
1042         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1043         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1044         int ret = 0;
1045
1046         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1047                   READ_BREADCRUMB(dev_priv));
1048
1049         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1050                 if (master_priv->sarea_priv)
1051                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1052                 return 0;
1053         }
1054
1055         if (master_priv->sarea_priv)
1056                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1057
1058         i915_user_irq_get(dev);
1059         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1060                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1061         i915_user_irq_put(dev);
1062
1063         if (ret == -EBUSY) {
1064                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1065                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1066         }
1067
1068         return ret;
1069 }
1070
1071 /* Needs the lock as it touches the ring.
1072  */
1073 int i915_irq_emit(struct drm_device *dev, void *data,
1074                          struct drm_file *file_priv)
1075 {
1076         drm_i915_private_t *dev_priv = dev->dev_private;
1077         drm_i915_irq_emit_t *emit = data;
1078         int result;
1079
1080         if (!dev_priv || !dev_priv->ring.virtual_start) {
1081                 DRM_ERROR("called with no initialization\n");
1082                 return -EINVAL;
1083         }
1084
1085         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1086
1087         mutex_lock(&dev->struct_mutex);
1088         result = i915_emit_irq(dev);
1089         mutex_unlock(&dev->struct_mutex);
1090
1091         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1092                 DRM_ERROR("copy_to_user\n");
1093                 return -EFAULT;
1094         }
1095
1096         return 0;
1097 }
1098
1099 /* Doesn't need the hardware lock.
1100  */
1101 int i915_irq_wait(struct drm_device *dev, void *data,
1102                          struct drm_file *file_priv)
1103 {
1104         drm_i915_private_t *dev_priv = dev->dev_private;
1105         drm_i915_irq_wait_t *irqwait = data;
1106
1107         if (!dev_priv) {
1108                 DRM_ERROR("called with no initialization\n");
1109                 return -EINVAL;
1110         }
1111
1112         return i915_wait_irq(dev, irqwait->irq_seq);
1113 }
1114
1115 /* Called from drm generic code, passed 'crtc' which
1116  * we use as a pipe index
1117  */
1118 int i915_enable_vblank(struct drm_device *dev, int pipe)
1119 {
1120         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1121         unsigned long irqflags;
1122         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1123         u32 pipeconf;
1124
1125         pipeconf = I915_READ(pipeconf_reg);
1126         if (!(pipeconf & PIPEACONF_ENABLE))
1127                 return -EINVAL;
1128
1129         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1130         if (HAS_PCH_SPLIT(dev))
1131                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1132                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1133         else if (IS_I965G(dev))
1134                 i915_enable_pipestat(dev_priv, pipe,
1135                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1136         else
1137                 i915_enable_pipestat(dev_priv, pipe,
1138                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1139         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1140         return 0;
1141 }
1142
1143 /* Called from drm generic code, passed 'crtc' which
1144  * we use as a pipe index
1145  */
1146 void i915_disable_vblank(struct drm_device *dev, int pipe)
1147 {
1148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1149         unsigned long irqflags;
1150
1151         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1152         if (HAS_PCH_SPLIT(dev))
1153                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1154                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1155         else
1156                 i915_disable_pipestat(dev_priv, pipe,
1157                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1158                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1159         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1160 }
1161
1162 void i915_enable_interrupt (struct drm_device *dev)
1163 {
1164         struct drm_i915_private *dev_priv = dev->dev_private;
1165
1166         if (!HAS_PCH_SPLIT(dev))
1167                 opregion_enable_asle(dev);
1168         dev_priv->irq_enabled = 1;
1169 }
1170
1171
1172 /* Set the vblank monitor pipe
1173  */
1174 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1175                          struct drm_file *file_priv)
1176 {
1177         drm_i915_private_t *dev_priv = dev->dev_private;
1178
1179         if (!dev_priv) {
1180                 DRM_ERROR("called with no initialization\n");
1181                 return -EINVAL;
1182         }
1183
1184         return 0;
1185 }
1186
1187 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1188                          struct drm_file *file_priv)
1189 {
1190         drm_i915_private_t *dev_priv = dev->dev_private;
1191         drm_i915_vblank_pipe_t *pipe = data;
1192
1193         if (!dev_priv) {
1194                 DRM_ERROR("called with no initialization\n");
1195                 return -EINVAL;
1196         }
1197
1198         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1199
1200         return 0;
1201 }
1202
1203 /**
1204  * Schedule buffer swap at given vertical blank.
1205  */
1206 int i915_vblank_swap(struct drm_device *dev, void *data,
1207                      struct drm_file *file_priv)
1208 {
1209         /* The delayed swap mechanism was fundamentally racy, and has been
1210          * removed.  The model was that the client requested a delayed flip/swap
1211          * from the kernel, then waited for vblank before continuing to perform
1212          * rendering.  The problem was that the kernel might wake the client
1213          * up before it dispatched the vblank swap (since the lock has to be
1214          * held while touching the ringbuffer), in which case the client would
1215          * clear and start the next frame before the swap occurred, and
1216          * flicker would occur in addition to likely missing the vblank.
1217          *
1218          * In the absence of this ioctl, userland falls back to a correct path
1219          * of waiting for a vblank, then dispatching the swap on its own.
1220          * Context switching to userland and back is plenty fast enough for
1221          * meeting the requirements of vblank swapping.
1222          */
1223         return -EINVAL;
1224 }
1225
1226 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1227         drm_i915_private_t *dev_priv = dev->dev_private;
1228         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1229 }
1230
1231 /**
1232  * This is called when the chip hasn't reported back with completed
1233  * batchbuffers in a long time. The first time this is called we simply record
1234  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1235  * again, we assume the chip is wedged and try to fix it.
1236  */
1237 void i915_hangcheck_elapsed(unsigned long data)
1238 {
1239         struct drm_device *dev = (struct drm_device *)data;
1240         drm_i915_private_t *dev_priv = dev->dev_private;
1241         uint32_t acthd;
1242
1243         /* No reset support on this chip yet. */
1244         if (IS_GEN6(dev))
1245                 return;
1246
1247         if (!IS_I965G(dev))
1248                 acthd = I915_READ(ACTHD);
1249         else
1250                 acthd = I915_READ(ACTHD_I965);
1251
1252         /* If all work is done then ACTHD clearly hasn't advanced. */
1253         if (list_empty(&dev_priv->mm.request_list) ||
1254                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1255                 dev_priv->hangcheck_count = 0;
1256                 return;
1257         }
1258
1259         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1260                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1261                 i915_handle_error(dev, true);
1262                 return;
1263         }
1264
1265         /* Reset timer case chip hangs without another request being added */
1266         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1267
1268         if (acthd != dev_priv->last_acthd)
1269                 dev_priv->hangcheck_count = 0;
1270         else
1271                 dev_priv->hangcheck_count++;
1272
1273         dev_priv->last_acthd = acthd;
1274 }
1275
1276 /* drm_dma.h hooks
1277 */
1278 static void ironlake_irq_preinstall(struct drm_device *dev)
1279 {
1280         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1281
1282         I915_WRITE(HWSTAM, 0xeffe);
1283
1284         /* XXX hotplug from PCH */
1285
1286         I915_WRITE(DEIMR, 0xffffffff);
1287         I915_WRITE(DEIER, 0x0);
1288         (void) I915_READ(DEIER);
1289
1290         /* and GT */
1291         I915_WRITE(GTIMR, 0xffffffff);
1292         I915_WRITE(GTIER, 0x0);
1293         (void) I915_READ(GTIER);
1294
1295         /* south display irq */
1296         I915_WRITE(SDEIMR, 0xffffffff);
1297         I915_WRITE(SDEIER, 0x0);
1298         (void) I915_READ(SDEIER);
1299 }
1300
1301 static int ironlake_irq_postinstall(struct drm_device *dev)
1302 {
1303         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1304         /* enable kind of interrupts always enabled */
1305         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1306                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1307         u32 render_mask = GT_USER_INTERRUPT;
1308         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1309                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1310
1311         dev_priv->irq_mask_reg = ~display_mask;
1312         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1313
1314         /* should always can generate irq */
1315         I915_WRITE(DEIIR, I915_READ(DEIIR));
1316         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1317         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1318         (void) I915_READ(DEIER);
1319
1320         /* user interrupt should be enabled, but masked initial */
1321         dev_priv->gt_irq_mask_reg = 0xffffffff;
1322         dev_priv->gt_irq_enable_reg = render_mask;
1323
1324         I915_WRITE(GTIIR, I915_READ(GTIIR));
1325         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1326         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1327         (void) I915_READ(GTIER);
1328
1329         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1330         dev_priv->pch_irq_enable_reg = hotplug_mask;
1331
1332         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1333         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1334         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1335         (void) I915_READ(SDEIER);
1336
1337         if (IS_IRONLAKE_M(dev)) {
1338                 /* Clear & enable PCU event interrupts */
1339                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1340                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1341                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1342         }
1343
1344         return 0;
1345 }
1346
1347 void i915_driver_irq_preinstall(struct drm_device * dev)
1348 {
1349         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1350
1351         atomic_set(&dev_priv->irq_received, 0);
1352
1353         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1354         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1355
1356         if (HAS_PCH_SPLIT(dev)) {
1357                 ironlake_irq_preinstall(dev);
1358                 return;
1359         }
1360
1361         if (I915_HAS_HOTPLUG(dev)) {
1362                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1363                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1364         }
1365
1366         I915_WRITE(HWSTAM, 0xeffe);
1367         I915_WRITE(PIPEASTAT, 0);
1368         I915_WRITE(PIPEBSTAT, 0);
1369         I915_WRITE(IMR, 0xffffffff);
1370         I915_WRITE(IER, 0x0);
1371         (void) I915_READ(IER);
1372 }
1373
1374 /*
1375  * Must be called after intel_modeset_init or hotplug interrupts won't be
1376  * enabled correctly.
1377  */
1378 int i915_driver_irq_postinstall(struct drm_device *dev)
1379 {
1380         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1381         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1382         u32 error_mask;
1383
1384         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1385
1386         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1387
1388         if (HAS_PCH_SPLIT(dev))
1389                 return ironlake_irq_postinstall(dev);
1390
1391         /* Unmask the interrupts that we always want on. */
1392         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1393
1394         dev_priv->pipestat[0] = 0;
1395         dev_priv->pipestat[1] = 0;
1396
1397         if (I915_HAS_HOTPLUG(dev)) {
1398                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1399
1400                 /* Note HDMI and DP share bits */
1401                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1402                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1403                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1404                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1405                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1406                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1407                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1408                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1409                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1410                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1411                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1412                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1413                 /* Ignore TV since it's buggy */
1414
1415                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1416
1417                 /* Enable in IER... */
1418                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1419                 /* and unmask in IMR */
1420                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1421         }
1422
1423         /*
1424          * Enable some error detection, note the instruction error mask
1425          * bit is reserved, so we leave it masked.
1426          */
1427         if (IS_G4X(dev)) {
1428                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1429                                GM45_ERROR_MEM_PRIV |
1430                                GM45_ERROR_CP_PRIV |
1431                                I915_ERROR_MEMORY_REFRESH);
1432         } else {
1433                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1434                                I915_ERROR_MEMORY_REFRESH);
1435         }
1436         I915_WRITE(EMR, error_mask);
1437
1438         /* Disable pipe interrupt enables, clear pending pipe status */
1439         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1440         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1441         /* Clear pending interrupt status */
1442         I915_WRITE(IIR, I915_READ(IIR));
1443
1444         I915_WRITE(IER, enable_mask);
1445         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1446         (void) I915_READ(IER);
1447
1448         opregion_enable_asle(dev);
1449
1450         return 0;
1451 }
1452
1453 static void ironlake_irq_uninstall(struct drm_device *dev)
1454 {
1455         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1456         I915_WRITE(HWSTAM, 0xffffffff);
1457
1458         I915_WRITE(DEIMR, 0xffffffff);
1459         I915_WRITE(DEIER, 0x0);
1460         I915_WRITE(DEIIR, I915_READ(DEIIR));
1461
1462         I915_WRITE(GTIMR, 0xffffffff);
1463         I915_WRITE(GTIER, 0x0);
1464         I915_WRITE(GTIIR, I915_READ(GTIIR));
1465 }
1466
1467 void i915_driver_irq_uninstall(struct drm_device * dev)
1468 {
1469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1470
1471         if (!dev_priv)
1472                 return;
1473
1474         dev_priv->vblank_pipe = 0;
1475
1476         if (HAS_PCH_SPLIT(dev)) {
1477                 ironlake_irq_uninstall(dev);
1478                 return;
1479         }
1480
1481         if (I915_HAS_HOTPLUG(dev)) {
1482                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1483                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1484         }
1485
1486         I915_WRITE(HWSTAM, 0xffffffff);
1487         I915_WRITE(PIPEASTAT, 0);
1488         I915_WRITE(PIPEBSTAT, 0);
1489         I915_WRITE(IMR, 0xffffffff);
1490         I915_WRITE(IER, 0x0);
1491
1492         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1493         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1494         I915_WRITE(IIR, I915_READ(IIR));
1495 }