drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 310
 311         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 312                 if (encoder->hot_plug)
 313                         encoder->hot_plug(encoder);
 314
 315         /* Just fire off a uevent and let userspace tell us what to do */
 316         drm_helper_hpd_irq_event(dev);
 317 }
 318
 319 static void i915_handle_rps_change(struct drm_device *dev)
 320 {
 321         drm_i915_private_t *dev_priv = dev->dev_private;
 322         u32 busy_up, busy_down, max_avg, min_avg;
 323         u8 new_delay = dev_priv->cur_delay;
 324
 325         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 326         busy_up = I915_READ(RCPREVBSYTUPAVG);
 327         busy_down = I915_READ(RCPREVBSYTDNAVG);
 328         max_avg = I915_READ(RCBMAXAVG);
 329         min_avg = I915_READ(RCBMINAVG);
 330
 331         /* Handle RCS change request from hw */
 332         if (busy_up > max_avg) {
 333                 if (dev_priv->cur_delay != dev_priv->max_delay)
 334                         new_delay = dev_priv->cur_delay - 1;
 335                 if (new_delay < dev_priv->max_delay)
 336                         new_delay = dev_priv->max_delay;
 337         } else if (busy_down < min_avg) {
 338                 if (dev_priv->cur_delay != dev_priv->min_delay)
 339                         new_delay = dev_priv->cur_delay + 1;
 340                 if (new_delay > dev_priv->min_delay)
 341                         new_delay = dev_priv->min_delay;
 342         }
 343
 344         if (ironlake_set_drps(dev, new_delay))
 345                 dev_priv->cur_delay = new_delay;
 346
 347         return;
 348 }
 349
 350 static void notify_ring(struct drm_device *dev,
 351                         struct intel_ring_buffer *ring)
 352 {
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354         u32 seqno;
 355
 356         if (ring->obj == NULL)
 357                 return;
 358
 359         seqno = ring->get_seqno(ring);
 360         trace_i915_gem_request_complete(ring, seqno);
 361
 362         ring->irq_seqno = seqno;
 363         wake_up_all(&ring->irq_queue);
 364
 365         dev_priv->hangcheck_count = 0;
 366         mod_timer(&dev_priv->hangcheck_timer,
 367                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 368 }
 369
 370 static void gen6_pm_rps_work(struct work_struct *work)
 371 {
 372         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 373                                                     rps_work);
 374         u8 new_delay = dev_priv->cur_delay;
 375         u32 pm_iir, pm_imr;
 376
 377         spin_lock_irq(&dev_priv->rps_lock);
 378         pm_iir = dev_priv->pm_iir;
 379         dev_priv->pm_iir = 0;
 380         pm_imr = I915_READ(GEN6_PMIMR);
 381         spin_unlock_irq(&dev_priv->rps_lock);
 382
 383         if (!pm_iir)
 384                 return;
 385
 386         mutex_lock(&dev_priv->dev->struct_mutex);
 387         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 388                 if (dev_priv->cur_delay != dev_priv->max_delay)
 389                         new_delay = dev_priv->cur_delay + 1;
 390                 if (new_delay > dev_priv->max_delay)
 391                         new_delay = dev_priv->max_delay;
 392         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 393                 gen6_gt_force_wake_get(dev_priv);
 394                 if (dev_priv->cur_delay != dev_priv->min_delay)
 395                         new_delay = dev_priv->cur_delay - 1;
 396                 if (new_delay < dev_priv->min_delay) {
 397                         new_delay = dev_priv->min_delay;
 398                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 399                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 400                                    ((new_delay << 16) & 0x3f0000));
 401                 } else {
 402                         /* Make sure we continue to get down interrupts
 403                          * until we hit the minimum frequency */
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 406                 }
 407                 gen6_gt_force_wake_put(dev_priv);
 408         }
 409
 410         gen6_set_rps(dev_priv->dev, new_delay);
 411         dev_priv->cur_delay = new_delay;
 412
 413         /*
 414          * rps_lock not held here because clearing is non-destructive. There is
 415          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 416          * by holding struct_mutex for the duration of the write.
 417          */
 418         I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
 419         mutex_unlock(&dev_priv->dev->struct_mutex);
 420 }
 421
 422 static void pch_irq_handler(struct drm_device *dev)
 423 {
 424         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 425         u32 pch_iir;
 426         int pipe;
 427
 428         pch_iir = I915_READ(SDEIIR);
 429
 430         if (pch_iir & SDE_AUDIO_POWER_MASK)
 431                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 432                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 433                                  SDE_AUDIO_POWER_SHIFT);
 434
 435         if (pch_iir & SDE_GMBUS)
 436                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 437
 438         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 439                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 440
 441         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 442                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 443
 444         if (pch_iir & SDE_POISON)
 445                 DRM_ERROR("PCH poison interrupt\n");
 446
 447         if (pch_iir & SDE_FDI_MASK)
 448                 for_each_pipe(pipe)
 449                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 450                                          pipe_name(pipe),
 451                                          I915_READ(FDI_RX_IIR(pipe)));
 452
 453         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 454                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 455
 456         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 457                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 458
 459         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 460                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 461         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 462                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 463 }
 464
 465 irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 466 {
 467         struct drm_device *dev = (struct drm_device *) arg;
 468         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 469         int ret = IRQ_NONE;
 470         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 471         u32 hotplug_mask;
 472         struct drm_i915_master_private *master_priv;
 473         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 474
 475         atomic_inc(&dev_priv->irq_received);
 476
 477         if (IS_GEN6(dev))
 478                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 479
 480         /* disable master interrupt before clearing iir  */
 481         de_ier = I915_READ(DEIER);
 482         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483         POSTING_READ(DEIER);
 484
 485         de_iir = I915_READ(DEIIR);
 486         gt_iir = I915_READ(GTIIR);
 487         pch_iir = I915_READ(SDEIIR);
 488         pm_iir = I915_READ(GEN6_PMIIR);
 489
 490         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 491             (!IS_GEN6(dev) || pm_iir == 0))
 492                 goto done;
 493
 494         if (HAS_PCH_CPT(dev))
 495                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 496         else
 497                 hotplug_mask = SDE_HOTPLUG_MASK;
 498
 499         ret = IRQ_HANDLED;
 500
 501         if (dev->primary->master) {
 502                 master_priv = dev->primary->master->driver_priv;
 503                 if (master_priv->sarea_priv)
 504                         master_priv->sarea_priv->last_dispatch =
 505                                 READ_BREADCRUMB(dev_priv);
 506         }
 507
 508         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 509                 notify_ring(dev, &dev_priv->ring[RCS]);
 510         if (gt_iir & bsd_usr_interrupt)
 511                 notify_ring(dev, &dev_priv->ring[VCS]);
 512         if (gt_iir & GT_BLT_USER_INTERRUPT)
 513                 notify_ring(dev, &dev_priv->ring[BCS]);
 514
 515         if (de_iir & DE_GSE)
 516                 intel_opregion_gse_intr(dev);
 517
 518         if (de_iir & DE_PLANEA_FLIP_DONE) {
 519                 intel_prepare_page_flip(dev, 0);
 520                 intel_finish_page_flip_plane(dev, 0);
 521         }
 522
 523         if (de_iir & DE_PLANEB_FLIP_DONE) {
 524                 intel_prepare_page_flip(dev, 1);
 525                 intel_finish_page_flip_plane(dev, 1);
 526         }
 527
 528         if (de_iir & DE_PIPEA_VBLANK)
 529                 drm_handle_vblank(dev, 0);
 530
 531         if (de_iir & DE_PIPEB_VBLANK)
 532                 drm_handle_vblank(dev, 1);
 533
 534         /* check event from PCH */
 535         if (de_iir & DE_PCH_EVENT) {
 536                 if (pch_iir & hotplug_mask)
 537                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 538                 pch_irq_handler(dev);
 539         }
 540
 541         if (de_iir & DE_PCU_EVENT) {
 542                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 543                 i915_handle_rps_change(dev);
 544         }
 545
 546         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 547                 /*
 548                  * IIR bits should never already be set because IMR should
 549                  * prevent an interrupt from being shown in IIR. The warning
 550                  * displays a case where we've unsafely cleared
 551                  * dev_priv->pm_iir. Although missing an interrupt of the same
 552                  * type is not a problem, it displays a problem in the logic.
 553                  *
 554                  * The mask bit in IMR is cleared by rps_work.
 555                  */
 556                 unsigned long flags;
 557                 spin_lock_irqsave(&dev_priv->rps_lock, flags);
 558                 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 559                 I915_WRITE(GEN6_PMIMR, pm_iir);
 560                 dev_priv->pm_iir |= pm_iir;
 561                 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 562                 queue_work(dev_priv->wq, &dev_priv->rps_work);
 563         }
 564
 565         /* should clear PCH hotplug event before clear CPU irq */
 566         I915_WRITE(SDEIIR, pch_iir);
 567         I915_WRITE(GTIIR, gt_iir);
 568         I915_WRITE(DEIIR, de_iir);
 569         I915_WRITE(GEN6_PMIIR, pm_iir);
 570
 571 done:
 572         I915_WRITE(DEIER, de_ier);
 573         POSTING_READ(DEIER);
 574
 575         return ret;
 576 }
 577
 578 /**
 579  * i915_error_work_func - do process context error handling work
 580  * @work: work struct
 581  *
 582  * Fire an error uevent so userspace can see that a hang or error
 583  * was detected.
 584  */
 585 static void i915_error_work_func(struct work_struct *work)
 586 {
 587         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 588                                                     error_work);
 589         struct drm_device *dev = dev_priv->dev;
 590         char *error_event[] = { "ERROR=1", NULL };
 591         char *reset_event[] = { "RESET=1", NULL };
 592         char *reset_done_event[] = { "ERROR=0", NULL };
 593
 594         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 595
 596         if (atomic_read(&dev_priv->mm.wedged)) {
 597                 DRM_DEBUG_DRIVER("resetting chip\n");
 598                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 599                 if (!i915_reset(dev, GRDOM_RENDER)) {
 600                         atomic_set(&dev_priv->mm.wedged, 0);
 601                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 602                 }
 603                 complete_all(&dev_priv->error_completion);
 604         }
 605 }
 606
 607 #ifdef CONFIG_DEBUG_FS
 608 static struct drm_i915_error_object *
 609 i915_error_object_create(struct drm_i915_private *dev_priv,
 610                          struct drm_i915_gem_object *src)
 611 {
 612         struct drm_i915_error_object *dst;
 613         int page, page_count;
 614         u32 reloc_offset;
 615
 616         if (src == NULL || src->pages == NULL)
 617                 return NULL;
 618
 619         page_count = src->base.size / PAGE_SIZE;
 620
 621         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 622         if (dst == NULL)
 623                 return NULL;
 624
 625         reloc_offset = src->gtt_offset;
 626         for (page = 0; page < page_count; page++) {
 627                 unsigned long flags;
 628                 void __iomem *s;
 629                 void *d;
 630
 631                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 632                 if (d == NULL)
 633                         goto unwind;
 634
 635                 local_irq_save(flags);
 636                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 637                                              reloc_offset);
 638                 memcpy_fromio(d, s, PAGE_SIZE);
 639                 io_mapping_unmap_atomic(s);
 640                 local_irq_restore(flags);
 641
 642                 dst->pages[page] = d;
 643
 644                 reloc_offset += PAGE_SIZE;
 645         }
 646         dst->page_count = page_count;
 647         dst->gtt_offset = src->gtt_offset;
 648
 649         return dst;
 650
 651 unwind:
 652         while (page--)
 653                 kfree(dst->pages[page]);
 654         kfree(dst);
 655         return NULL;
 656 }
 657
 658 static void
 659 i915_error_object_free(struct drm_i915_error_object *obj)
 660 {
 661         int page;
 662
 663         if (obj == NULL)
 664                 return;
 665
 666         for (page = 0; page < obj->page_count; page++)
 667                 kfree(obj->pages[page]);
 668
 669         kfree(obj);
 670 }
 671
 672 static void
 673 i915_error_state_free(struct drm_device *dev,
 674                       struct drm_i915_error_state *error)
 675 {
 676         int i;
 677
 678         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 679                 i915_error_object_free(error->batchbuffer[i]);
 680
 681         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 682                 i915_error_object_free(error->ringbuffer[i]);
 683
 684         kfree(error->active_bo);
 685         kfree(error->overlay);
 686         kfree(error);
 687 }
 688
 689 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 690                            int count,
 691                            struct list_head *head)
 692 {
 693         struct drm_i915_gem_object *obj;
 694         int i = 0;
 695
 696         list_for_each_entry(obj, head, mm_list) {
 697                 err->size = obj->base.size;
 698                 err->name = obj->base.name;
 699                 err->seqno = obj->last_rendering_seqno;
 700                 err->gtt_offset = obj->gtt_offset;
 701                 err->read_domains = obj->base.read_domains;
 702                 err->write_domain = obj->base.write_domain;
 703                 err->fence_reg = obj->fence_reg;
 704                 err->pinned = 0;
 705                 if (obj->pin_count > 0)
 706                         err->pinned = 1;
 707                 if (obj->user_pin_count > 0)
 708                         err->pinned = -1;
 709                 err->tiling = obj->tiling_mode;
 710                 err->dirty = obj->dirty;
 711                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 712                 err->ring = obj->ring ? obj->ring->id : 0;
 713                 err->cache_level = obj->cache_level;
 714
 715                 if (++i == count)
 716                         break;
 717
 718                 err++;
 719         }
 720
 721         return i;
 722 }
 723
 724 static void i915_gem_record_fences(struct drm_device *dev,
 725                                    struct drm_i915_error_state *error)
 726 {
 727         struct drm_i915_private *dev_priv = dev->dev_private;
 728         int i;
 729
 730         /* Fences */
 731         switch (INTEL_INFO(dev)->gen) {
 732         case 6:
 733                 for (i = 0; i < 16; i++)
 734                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 735                 break;
 736         case 5:
 737         case 4:
 738                 for (i = 0; i < 16; i++)
 739                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 740                 break;
 741         case 3:
 742                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 743                         for (i = 0; i < 8; i++)
 744                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 745         case 2:
 746                 for (i = 0; i < 8; i++)
 747                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 748                 break;
 749
 750         }
 751 }
 752
 753 static struct drm_i915_error_object *
 754 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 755                              struct intel_ring_buffer *ring)
 756 {
 757         struct drm_i915_gem_object *obj;
 758         u32 seqno;
 759
 760         if (!ring->get_seqno)
 761                 return NULL;
 762
 763         seqno = ring->get_seqno(ring);
 764         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 765                 if (obj->ring != ring)
 766                         continue;
 767
 768                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 769                         continue;
 770
 771                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 772                         continue;
 773
 774                 /* We need to copy these to an anonymous buffer as the simplest
 775                  * method to avoid being overwritten by userspace.
 776                  */
 777                 return i915_error_object_create(dev_priv, obj);
 778         }
 779
 780         return NULL;
 781 }
 782
 783 /**
 784  * i915_capture_error_state - capture an error record for later analysis
 785  * @dev: drm device
 786  *
 787  * Should be called when an error is detected (either a hang or an error
 788  * interrupt) to capture error state from the time of the error.  Fills
 789  * out a structure which becomes available in debugfs for user level tools
 790  * to pick up.
 791  */
 792 static void i915_capture_error_state(struct drm_device *dev)
 793 {
 794         struct drm_i915_private *dev_priv = dev->dev_private;
 795         struct drm_i915_gem_object *obj;
 796         struct drm_i915_error_state *error;
 797         unsigned long flags;
 798         int i, pipe;
 799
 800         spin_lock_irqsave(&dev_priv->error_lock, flags);
 801         error = dev_priv->first_error;
 802         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 803         if (error)
 804                 return;
 805
 806         /* Account for pipe specific data like PIPE*STAT */
 807         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 808         if (!error) {
 809                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 810                 return;
 811         }
 812
 813         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 814                  dev->primary->index);
 815
 816         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 817         error->eir = I915_READ(EIR);
 818         error->pgtbl_er = I915_READ(PGTBL_ER);
 819         for_each_pipe(pipe)
 820                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 821         error->instpm = I915_READ(INSTPM);
 822         error->error = 0;
 823         if (INTEL_INFO(dev)->gen >= 6) {
 824                 error->error = I915_READ(ERROR_GEN6);
 825
 826                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 827                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 828                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 829                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 830                 error->bcs_seqno = 0;
 831                 if (dev_priv->ring[BCS].get_seqno)
 832                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 833
 834                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 835                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 836                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 837                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 838                 error->vcs_seqno = 0;
 839                 if (dev_priv->ring[VCS].get_seqno)
 840                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 841         }
 842         if (INTEL_INFO(dev)->gen >= 4) {
 843                 error->ipeir = I915_READ(IPEIR_I965);
 844                 error->ipehr = I915_READ(IPEHR_I965);
 845                 error->instdone = I915_READ(INSTDONE_I965);
 846                 error->instps = I915_READ(INSTPS);
 847                 error->instdone1 = I915_READ(INSTDONE1);
 848                 error->acthd = I915_READ(ACTHD_I965);
 849                 error->bbaddr = I915_READ64(BB_ADDR);
 850         } else {
 851                 error->ipeir = I915_READ(IPEIR);
 852                 error->ipehr = I915_READ(IPEHR);
 853                 error->instdone = I915_READ(INSTDONE);
 854                 error->acthd = I915_READ(ACTHD);
 855                 error->bbaddr = 0;
 856         }
 857         i915_gem_record_fences(dev, error);
 858
 859         /* Record the active batch and ring buffers */
 860         for (i = 0; i < I915_NUM_RINGS; i++) {
 861                 error->batchbuffer[i] =
 862                         i915_error_first_batchbuffer(dev_priv,
 863                                                      &dev_priv->ring[i]);
 864
 865                 error->ringbuffer[i] =
 866                         i915_error_object_create(dev_priv,
 867                                                  dev_priv->ring[i].obj);
 868         }
 869
 870         /* Record buffers on the active and pinned lists. */
 871         error->active_bo = NULL;
 872         error->pinned_bo = NULL;
 873
 874         i = 0;
 875         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 876                 i++;
 877         error->active_bo_count = i;
 878         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 879                 i++;
 880         error->pinned_bo_count = i - error->active_bo_count;
 881
 882         error->active_bo = NULL;
 883         error->pinned_bo = NULL;
 884         if (i) {
 885                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 886                                            GFP_ATOMIC);
 887                 if (error->active_bo)
 888                         error->pinned_bo =
 889                                 error->active_bo + error->active_bo_count;
 890         }
 891
 892         if (error->active_bo)
 893                 error->active_bo_count =
 894                         capture_bo_list(error->active_bo,
 895                                         error->active_bo_count,
 896                                         &dev_priv->mm.active_list);
 897
 898         if (error->pinned_bo)
 899                 error->pinned_bo_count =
 900                         capture_bo_list(error->pinned_bo,
 901                                         error->pinned_bo_count,
 902                                         &dev_priv->mm.pinned_list);
 903
 904         do_gettimeofday(&error->time);
 905
 906         error->overlay = intel_overlay_capture_error_state(dev);
 907         error->display = intel_display_capture_error_state(dev);
 908
 909         spin_lock_irqsave(&dev_priv->error_lock, flags);
 910         if (dev_priv->first_error == NULL) {
 911                 dev_priv->first_error = error;
 912                 error = NULL;
 913         }
 914         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 915
 916         if (error)
 917                 i915_error_state_free(dev, error);
 918 }
 919
 920 void i915_destroy_error_state(struct drm_device *dev)
 921 {
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         struct drm_i915_error_state *error;
 924
 925         spin_lock(&dev_priv->error_lock);
 926         error = dev_priv->first_error;
 927         dev_priv->first_error = NULL;
 928         spin_unlock(&dev_priv->error_lock);
 929
 930         if (error)
 931                 i915_error_state_free(dev, error);
 932 }
 933 #else
 934 #define i915_capture_error_state(x)
 935 #endif
 936
 937 static void i915_report_and_clear_eir(struct drm_device *dev)
 938 {
 939         struct drm_i915_private *dev_priv = dev->dev_private;
 940         u32 eir = I915_READ(EIR);
 941         int pipe;
 942
 943         if (!eir)
 944                 return;
 945
 946         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 947                eir);
 948
 949         if (IS_G4X(dev)) {
 950                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 951                         u32 ipeir = I915_READ(IPEIR_I965);
 952
 953                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 954                                I915_READ(IPEIR_I965));
 955                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 956                                I915_READ(IPEHR_I965));
 957                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 958                                I915_READ(INSTDONE_I965));
 959                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 960                                I915_READ(INSTPS));
 961                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 962                                I915_READ(INSTDONE1));
 963                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 964                                I915_READ(ACTHD_I965));
 965                         I915_WRITE(IPEIR_I965, ipeir);
 966                         POSTING_READ(IPEIR_I965);
 967                 }
 968                 if (eir & GM45_ERROR_PAGE_TABLE) {
 969                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 970                         printk(KERN_ERR "page table error\n");
 971                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 972                                pgtbl_err);
 973                         I915_WRITE(PGTBL_ER, pgtbl_err);
 974                         POSTING_READ(PGTBL_ER);
 975                 }
 976         }
 977
 978         if (!IS_GEN2(dev)) {
 979                 if (eir & I915_ERROR_PAGE_TABLE) {
 980                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 981                         printk(KERN_ERR "page table error\n");
 982                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 983                                pgtbl_err);
 984                         I915_WRITE(PGTBL_ER, pgtbl_err);
 985                         POSTING_READ(PGTBL_ER);
 986                 }
 987         }
 988
 989         if (eir & I915_ERROR_MEMORY_REFRESH) {
 990                 printk(KERN_ERR "memory refresh error:\n");
 991                 for_each_pipe(pipe)
 992                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
 993                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
 994                 /* pipestat has already been acked */
 995         }
 996         if (eir & I915_ERROR_INSTRUCTION) {
 997                 printk(KERN_ERR "instruction error\n");
 998                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 999                        I915_READ(INSTPM));
1000                 if (INTEL_INFO(dev)->gen < 4) {
1001                         u32 ipeir = I915_READ(IPEIR);
1002
1003                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1004                                I915_READ(IPEIR));
1005                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1006                                I915_READ(IPEHR));
1007                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1008                                I915_READ(INSTDONE));
1009                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1010                                I915_READ(ACTHD));
1011                         I915_WRITE(IPEIR, ipeir);
1012                         POSTING_READ(IPEIR);
1013                 } else {
1014                         u32 ipeir = I915_READ(IPEIR_I965);
1015
1016                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1017                                I915_READ(IPEIR_I965));
1018                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1019                                I915_READ(IPEHR_I965));
1020                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1021                                I915_READ(INSTDONE_I965));
1022                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1023                                I915_READ(INSTPS));
1024                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1025                                I915_READ(INSTDONE1));
1026                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1027                                I915_READ(ACTHD_I965));
1028                         I915_WRITE(IPEIR_I965, ipeir);
1029                         POSTING_READ(IPEIR_I965);
1030                 }
1031         }
1032
1033         I915_WRITE(EIR, eir);
1034         POSTING_READ(EIR);
1035         eir = I915_READ(EIR);
1036         if (eir) {
1037                 /*
1038                  * some errors might have become stuck,
1039                  * mask them.
1040                  */
1041                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1042                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1043                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1044         }
1045 }
1046
1047 /**
1048  * i915_handle_error - handle an error interrupt
1049  * @dev: drm device
1050  *
1051  * Do some basic checking of regsiter state at error interrupt time and
1052  * dump it to the syslog.  Also call i915_capture_error_state() to make
1053  * sure we get a record and make it available in debugfs.  Fire a uevent
1054  * so userspace knows something bad happened (should trigger collection
1055  * of a ring dump etc.).
1056  */
1057 void i915_handle_error(struct drm_device *dev, bool wedged)
1058 {
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060
1061         i915_capture_error_state(dev);
1062         i915_report_and_clear_eir(dev);
1063
1064         if (wedged) {
1065                 INIT_COMPLETION(dev_priv->error_completion);
1066                 atomic_set(&dev_priv->mm.wedged, 1);
1067
1068                 /*
1069                  * Wakeup waiting processes so they don't hang
1070                  */
1071                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1072                 if (HAS_BSD(dev))
1073                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1074                 if (HAS_BLT(dev))
1075                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1076         }
1077
1078         queue_work(dev_priv->wq, &dev_priv->error_work);
1079 }
1080
1081 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1082 {
1083         drm_i915_private_t *dev_priv = dev->dev_private;
1084         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1086         struct drm_i915_gem_object *obj;
1087         struct intel_unpin_work *work;
1088         unsigned long flags;
1089         bool stall_detected;
1090
1091         /* Ignore early vblank irqs */
1092         if (intel_crtc == NULL)
1093                 return;
1094
1095         spin_lock_irqsave(&dev->event_lock, flags);
1096         work = intel_crtc->unpin_work;
1097
1098         if (work == NULL || work->pending || !work->enable_stall_check) {
1099                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1100                 spin_unlock_irqrestore(&dev->event_lock, flags);
1101                 return;
1102         }
1103
1104         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1105         obj = work->pending_flip_obj;
1106         if (INTEL_INFO(dev)->gen >= 4) {
1107                 int dspsurf = DSPSURF(intel_crtc->plane);
1108                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1109         } else {
1110                 int dspaddr = DSPADDR(intel_crtc->plane);
1111                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1112                                                         crtc->y * crtc->fb->pitch +
1113                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1114         }
1115
1116         spin_unlock_irqrestore(&dev->event_lock, flags);
1117
1118         if (stall_detected) {
1119                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1120                 intel_prepare_page_flip(dev, intel_crtc->plane);
1121         }
1122 }
1123
1124 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1125 {
1126         struct drm_device *dev = (struct drm_device *) arg;
1127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1128         struct drm_i915_master_private *master_priv;
1129         u32 iir, new_iir;
1130         u32 pipe_stats[I915_MAX_PIPES];
1131         u32 vblank_status;
1132         int vblank = 0;
1133         unsigned long irqflags;
1134         int irq_received;
1135         int ret = IRQ_NONE, pipe;
1136         bool blc_event = false;
1137
1138         atomic_inc(&dev_priv->irq_received);
1139
1140         iir = I915_READ(IIR);
1141
1142         if (INTEL_INFO(dev)->gen >= 4)
1143                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1144         else
1145                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1146
1147         for (;;) {
1148                 irq_received = iir != 0;
1149
1150                 /* Can't rely on pipestat interrupt bit in iir as it might
1151                  * have been cleared after the pipestat interrupt was received.
1152                  * It doesn't set the bit in iir again, but it still produces
1153                  * interrupts (for non-MSI).
1154                  */
1155                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1156                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1157                         i915_handle_error(dev, false);
1158
1159                 for_each_pipe(pipe) {
1160                         int reg = PIPESTAT(pipe);
1161                         pipe_stats[pipe] = I915_READ(reg);
1162
1163                         /*
1164                          * Clear the PIPE*STAT regs before the IIR
1165                          */
1166                         if (pipe_stats[pipe] & 0x8000ffff) {
1167                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1168                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1169                                                          pipe_name(pipe));
1170                                 I915_WRITE(reg, pipe_stats[pipe]);
1171                                 irq_received = 1;
1172                         }
1173                 }
1174                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1175
1176                 if (!irq_received)
1177                         break;
1178
1179                 ret = IRQ_HANDLED;
1180
1181                 /* Consume port.  Then clear IIR or we'll miss events */
1182                 if ((I915_HAS_HOTPLUG(dev)) &&
1183                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1184                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1185
1186                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1187                                   hotplug_status);
1188                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1189                                 queue_work(dev_priv->wq,
1190                                            &dev_priv->hotplug_work);
1191
1192                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1193                         I915_READ(PORT_HOTPLUG_STAT);
1194                 }
1195
1196                 I915_WRITE(IIR, iir);
1197                 new_iir = I915_READ(IIR); /* Flush posted writes */
1198
1199                 if (dev->primary->master) {
1200                         master_priv = dev->primary->master->driver_priv;
1201                         if (master_priv->sarea_priv)
1202                                 master_priv->sarea_priv->last_dispatch =
1203                                         READ_BREADCRUMB(dev_priv);
1204                 }
1205
1206                 if (iir & I915_USER_INTERRUPT)
1207                         notify_ring(dev, &dev_priv->ring[RCS]);
1208                 if (iir & I915_BSD_USER_INTERRUPT)
1209                         notify_ring(dev, &dev_priv->ring[VCS]);
1210
1211                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1212                         intel_prepare_page_flip(dev, 0);
1213                         if (dev_priv->flip_pending_is_done)
1214                                 intel_finish_page_flip_plane(dev, 0);
1215                 }
1216
1217                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1218                         intel_prepare_page_flip(dev, 1);
1219                         if (dev_priv->flip_pending_is_done)
1220                                 intel_finish_page_flip_plane(dev, 1);
1221                 }
1222
1223                 for_each_pipe(pipe) {
1224                         if (pipe_stats[pipe] & vblank_status &&
1225                             drm_handle_vblank(dev, pipe)) {
1226                                 vblank++;
1227                                 if (!dev_priv->flip_pending_is_done) {
1228                                         i915_pageflip_stall_check(dev, pipe);
1229                                         intel_finish_page_flip(dev, pipe);
1230                                 }
1231                         }
1232
1233                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1234                                 blc_event = true;
1235                 }
1236
1237
1238                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1239                         intel_opregion_asle_intr(dev);
1240
1241                 /* With MSI, interrupts are only generated when iir
1242                  * transitions from zero to nonzero.  If another bit got
1243                  * set while we were handling the existing iir bits, then
1244                  * we would never get another interrupt.
1245                  *
1246                  * This is fine on non-MSI as well, as if we hit this path
1247                  * we avoid exiting the interrupt handler only to generate
1248                  * another one.
1249                  *
1250                  * Note that for MSI this could cause a stray interrupt report
1251                  * if an interrupt landed in the time between writing IIR and
1252                  * the posting read.  This should be rare enough to never
1253                  * trigger the 99% of 100,000 interrupts test for disabling
1254                  * stray interrupts.
1255                  */
1256                 iir = new_iir;
1257         }
1258
1259         return ret;
1260 }
1261
1262 static int i915_emit_irq(struct drm_device * dev)
1263 {
1264         drm_i915_private_t *dev_priv = dev->dev_private;
1265         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1266
1267         i915_kernel_lost_context(dev);
1268
1269         DRM_DEBUG_DRIVER("\n");
1270
1271         dev_priv->counter++;
1272         if (dev_priv->counter > 0x7FFFFFFFUL)
1273                 dev_priv->counter = 1;
1274         if (master_priv->sarea_priv)
1275                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1276
1277         if (BEGIN_LP_RING(4) == 0) {
1278                 OUT_RING(MI_STORE_DWORD_INDEX);
1279                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1280                 OUT_RING(dev_priv->counter);
1281                 OUT_RING(MI_USER_INTERRUPT);
1282                 ADVANCE_LP_RING();
1283         }
1284
1285         return dev_priv->counter;
1286 }
1287
1288 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1289 {
1290         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1291         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1292         int ret = 0;
1293         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1294
1295         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1296                   READ_BREADCRUMB(dev_priv));
1297
1298         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1299                 if (master_priv->sarea_priv)
1300                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1301                 return 0;
1302         }
1303
1304         if (master_priv->sarea_priv)
1305                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1306
1307         if (ring->irq_get(ring)) {
1308                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1309                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1310                 ring->irq_put(ring);
1311         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1312                 ret = -EBUSY;
1313
1314         if (ret == -EBUSY) {
1315                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1316                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1317         }
1318
1319         return ret;
1320 }
1321
1322 /* Needs the lock as it touches the ring.
1323  */
1324 int i915_irq_emit(struct drm_device *dev, void *data,
1325                          struct drm_file *file_priv)
1326 {
1327         drm_i915_private_t *dev_priv = dev->dev_private;
1328         drm_i915_irq_emit_t *emit = data;
1329         int result;
1330
1331         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1332                 DRM_ERROR("called with no initialization\n");
1333                 return -EINVAL;
1334         }
1335
1336         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1337
1338         mutex_lock(&dev->struct_mutex);
1339         result = i915_emit_irq(dev);
1340         mutex_unlock(&dev->struct_mutex);
1341
1342         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1343                 DRM_ERROR("copy_to_user\n");
1344                 return -EFAULT;
1345         }
1346
1347         return 0;
1348 }
1349
1350 /* Doesn't need the hardware lock.
1351  */
1352 int i915_irq_wait(struct drm_device *dev, void *data,
1353                          struct drm_file *file_priv)
1354 {
1355         drm_i915_private_t *dev_priv = dev->dev_private;
1356         drm_i915_irq_wait_t *irqwait = data;
1357
1358         if (!dev_priv) {
1359                 DRM_ERROR("called with no initialization\n");
1360                 return -EINVAL;
1361         }
1362
1363         return i915_wait_irq(dev, irqwait->irq_seq);
1364 }
1365
1366 /* Called from drm generic code, passed 'crtc' which
1367  * we use as a pipe index
1368  */
1369 int i915_enable_vblank(struct drm_device *dev, int pipe)
1370 {
1371         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1372         unsigned long irqflags;
1373
1374         if (!i915_pipe_enabled(dev, pipe))
1375                 return -EINVAL;
1376
1377         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1378         if (HAS_PCH_SPLIT(dev))
1379                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1380                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1381         else if (INTEL_INFO(dev)->gen >= 4)
1382                 i915_enable_pipestat(dev_priv, pipe,
1383                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1384         else
1385                 i915_enable_pipestat(dev_priv, pipe,
1386                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1387
1388         /* maintain vblank delivery even in deep C-states */
1389         if (dev_priv->info->gen == 3)
1390                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1391         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1392
1393         return 0;
1394 }
1395
1396 /* Called from drm generic code, passed 'crtc' which
1397  * we use as a pipe index
1398  */
1399 void i915_disable_vblank(struct drm_device *dev, int pipe)
1400 {
1401         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1402         unsigned long irqflags;
1403
1404         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1405         if (dev_priv->info->gen == 3)
1406                 I915_WRITE(INSTPM,
1407                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1408
1409         if (HAS_PCH_SPLIT(dev))
1410                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1411                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1412         else
1413                 i915_disable_pipestat(dev_priv, pipe,
1414                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1415                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1416         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1417 }
1418
1419 /* Set the vblank monitor pipe
1420  */
1421 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1422                          struct drm_file *file_priv)
1423 {
1424         drm_i915_private_t *dev_priv = dev->dev_private;
1425
1426         if (!dev_priv) {
1427                 DRM_ERROR("called with no initialization\n");
1428                 return -EINVAL;
1429         }
1430
1431         return 0;
1432 }
1433
1434 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1435                          struct drm_file *file_priv)
1436 {
1437         drm_i915_private_t *dev_priv = dev->dev_private;
1438         drm_i915_vblank_pipe_t *pipe = data;
1439
1440         if (!dev_priv) {
1441                 DRM_ERROR("called with no initialization\n");
1442                 return -EINVAL;
1443         }
1444
1445         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1446
1447         return 0;
1448 }
1449
1450 /**
1451  * Schedule buffer swap at given vertical blank.
1452  */
1453 int i915_vblank_swap(struct drm_device *dev, void *data,
1454                      struct drm_file *file_priv)
1455 {
1456         /* The delayed swap mechanism was fundamentally racy, and has been
1457          * removed.  The model was that the client requested a delayed flip/swap
1458          * from the kernel, then waited for vblank before continuing to perform
1459          * rendering.  The problem was that the kernel might wake the client
1460          * up before it dispatched the vblank swap (since the lock has to be
1461          * held while touching the ringbuffer), in which case the client would
1462          * clear and start the next frame before the swap occurred, and
1463          * flicker would occur in addition to likely missing the vblank.
1464          *
1465          * In the absence of this ioctl, userland falls back to a correct path
1466          * of waiting for a vblank, then dispatching the swap on its own.
1467          * Context switching to userland and back is plenty fast enough for
1468          * meeting the requirements of vblank swapping.
1469          */
1470         return -EINVAL;
1471 }
1472
1473 static u32
1474 ring_last_seqno(struct intel_ring_buffer *ring)
1475 {
1476         return list_entry(ring->request_list.prev,
1477                           struct drm_i915_gem_request, list)->seqno;
1478 }
1479
1480 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1481 {
1482         if (list_empty(&ring->request_list) ||
1483             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1484                 /* Issue a wake-up to catch stuck h/w. */
1485                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1486                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1487                                   ring->name,
1488                                   ring->waiting_seqno,
1489                                   ring->get_seqno(ring));
1490                         wake_up_all(&ring->irq_queue);
1491                         *err = true;
1492                 }
1493                 return true;
1494         }
1495         return false;
1496 }
1497
1498 static bool kick_ring(struct intel_ring_buffer *ring)
1499 {
1500         struct drm_device *dev = ring->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         u32 tmp = I915_READ_CTL(ring);
1503         if (tmp & RING_WAIT) {
1504                 DRM_ERROR("Kicking stuck wait on %s\n",
1505                           ring->name);
1506                 I915_WRITE_CTL(ring, tmp);
1507                 return true;
1508         }
1509         if (IS_GEN6(dev) &&
1510             (tmp & RING_WAIT_SEMAPHORE)) {
1511                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1512                           ring->name);
1513                 I915_WRITE_CTL(ring, tmp);
1514                 return true;
1515         }
1516         return false;
1517 }
1518
1519 /**
1520  * This is called when the chip hasn't reported back with completed
1521  * batchbuffers in a long time. The first time this is called we simply record
1522  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1523  * again, we assume the chip is wedged and try to fix it.
1524  */
1525 void i915_hangcheck_elapsed(unsigned long data)
1526 {
1527         struct drm_device *dev = (struct drm_device *)data;
1528         drm_i915_private_t *dev_priv = dev->dev_private;
1529         uint32_t acthd, instdone, instdone1;
1530         bool err = false;
1531
1532         /* If all work is done then ACTHD clearly hasn't advanced. */
1533         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1534             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1535             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1536                 dev_priv->hangcheck_count = 0;
1537                 if (err)
1538                         goto repeat;
1539                 return;
1540         }
1541
1542         if (INTEL_INFO(dev)->gen < 4) {
1543                 acthd = I915_READ(ACTHD);
1544                 instdone = I915_READ(INSTDONE);
1545                 instdone1 = 0;
1546         } else {
1547                 acthd = I915_READ(ACTHD_I965);
1548                 instdone = I915_READ(INSTDONE_I965);
1549                 instdone1 = I915_READ(INSTDONE1);
1550         }
1551
1552         if (dev_priv->last_acthd == acthd &&
1553             dev_priv->last_instdone == instdone &&
1554             dev_priv->last_instdone1 == instdone1) {
1555                 if (dev_priv->hangcheck_count++ > 1) {
1556                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1557
1558                         if (!IS_GEN2(dev)) {
1559                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1560                                  * If so we can simply poke the RB_WAIT bit
1561                                  * and break the hang. This should work on
1562                                  * all but the second generation chipsets.
1563                                  */
1564
1565                                 if (kick_ring(&dev_priv->ring[RCS]))
1566                                         goto repeat;
1567
1568                                 if (HAS_BSD(dev) &&
1569                                     kick_ring(&dev_priv->ring[VCS]))
1570                                         goto repeat;
1571
1572                                 if (HAS_BLT(dev) &&
1573                                     kick_ring(&dev_priv->ring[BCS]))
1574                                         goto repeat;
1575                         }
1576
1577                         i915_handle_error(dev, true);
1578                         return;
1579                 }
1580         } else {
1581                 dev_priv->hangcheck_count = 0;
1582
1583                 dev_priv->last_acthd = acthd;
1584                 dev_priv->last_instdone = instdone;
1585                 dev_priv->last_instdone1 = instdone1;
1586         }
1587
1588 repeat:
1589         /* Reset timer case chip hangs without another request being added */
1590         mod_timer(&dev_priv->hangcheck_timer,
1591                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1592 }
1593
1594 /* drm_dma.h hooks
1595 */
1596 void ironlake_irq_preinstall(struct drm_device *dev)
1597 {
1598         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1599
1600         atomic_set(&dev_priv->irq_received, 0);
1601
1602         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1603         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1604
1605         I915_WRITE(HWSTAM, 0xeffe);
1606
1607         /* XXX hotplug from PCH */
1608
1609         I915_WRITE(DEIMR, 0xffffffff);
1610         I915_WRITE(DEIER, 0x0);
1611         POSTING_READ(DEIER);
1612
1613         /* and GT */
1614         I915_WRITE(GTIMR, 0xffffffff);
1615         I915_WRITE(GTIER, 0x0);
1616         POSTING_READ(GTIER);
1617
1618         /* south display irq */
1619         I915_WRITE(SDEIMR, 0xffffffff);
1620         I915_WRITE(SDEIER, 0x0);
1621         POSTING_READ(SDEIER);
1622 }
1623
1624 int ironlake_irq_postinstall(struct drm_device *dev)
1625 {
1626         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1627         /* enable kind of interrupts always enabled */
1628         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1629                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1630         u32 render_irqs;
1631         u32 hotplug_mask;
1632
1633         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1634         if (HAS_BSD(dev))
1635                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1636         if (HAS_BLT(dev))
1637                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1638
1639         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1640         dev_priv->irq_mask = ~display_mask;
1641
1642         /* should always can generate irq */
1643         I915_WRITE(DEIIR, I915_READ(DEIIR));
1644         I915_WRITE(DEIMR, dev_priv->irq_mask);
1645         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1646         POSTING_READ(DEIER);
1647
1648         dev_priv->gt_irq_mask = ~0;
1649
1650         I915_WRITE(GTIIR, I915_READ(GTIIR));
1651         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1652
1653         if (IS_GEN6(dev))
1654                 render_irqs =
1655                         GT_USER_INTERRUPT |
1656                         GT_GEN6_BSD_USER_INTERRUPT |
1657                         GT_BLT_USER_INTERRUPT;
1658         else
1659                 render_irqs =
1660                         GT_USER_INTERRUPT |
1661                         GT_PIPE_NOTIFY |
1662                         GT_BSD_USER_INTERRUPT;
1663         I915_WRITE(GTIER, render_irqs);
1664         POSTING_READ(GTIER);
1665
1666         if (HAS_PCH_CPT(dev)) {
1667                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1668                                 SDE_PORTB_HOTPLUG_CPT |
1669                                 SDE_PORTC_HOTPLUG_CPT |
1670                                 SDE_PORTD_HOTPLUG_CPT);
1671         } else {
1672                 hotplug_mask = (SDE_CRT_HOTPLUG |
1673                                 SDE_PORTB_HOTPLUG |
1674                                 SDE_PORTC_HOTPLUG |
1675                                 SDE_PORTD_HOTPLUG |
1676                                 SDE_AUX_MASK);
1677         }
1678
1679         dev_priv->pch_irq_mask = ~hotplug_mask;
1680
1681         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1682         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1683         I915_WRITE(SDEIER, hotplug_mask);
1684         POSTING_READ(SDEIER);
1685
1686         if (IS_IRONLAKE_M(dev)) {
1687                 /* Clear & enable PCU event interrupts */
1688                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1689                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1690                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1691         }
1692
1693         return 0;
1694 }
1695
1696 void i915_driver_irq_preinstall(struct drm_device * dev)
1697 {
1698         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1699         int pipe;
1700
1701         atomic_set(&dev_priv->irq_received, 0);
1702
1703         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1704         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1705         INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1706
1707         if (I915_HAS_HOTPLUG(dev)) {
1708                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1709                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1710         }
1711
1712         I915_WRITE(HWSTAM, 0xeffe);
1713         for_each_pipe(pipe)
1714                 I915_WRITE(PIPESTAT(pipe), 0);
1715         I915_WRITE(IMR, 0xffffffff);
1716         I915_WRITE(IER, 0x0);
1717         POSTING_READ(IER);
1718 }
1719
1720 /*
1721  * Must be called after intel_modeset_init or hotplug interrupts won't be
1722  * enabled correctly.
1723  */
1724 int i915_driver_irq_postinstall(struct drm_device *dev)
1725 {
1726         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1727         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1728         u32 error_mask;
1729
1730         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1731
1732         /* Unmask the interrupts that we always want on. */
1733         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1734
1735         dev_priv->pipestat[0] = 0;
1736         dev_priv->pipestat[1] = 0;
1737
1738         if (I915_HAS_HOTPLUG(dev)) {
1739                 /* Enable in IER... */
1740                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1741                 /* and unmask in IMR */
1742                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1743         }
1744
1745         /*
1746          * Enable some error detection, note the instruction error mask
1747          * bit is reserved, so we leave it masked.
1748          */
1749         if (IS_G4X(dev)) {
1750                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1751                                GM45_ERROR_MEM_PRIV |
1752                                GM45_ERROR_CP_PRIV |
1753                                I915_ERROR_MEMORY_REFRESH);
1754         } else {
1755                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1756                                I915_ERROR_MEMORY_REFRESH);
1757         }
1758         I915_WRITE(EMR, error_mask);
1759
1760         I915_WRITE(IMR, dev_priv->irq_mask);
1761         I915_WRITE(IER, enable_mask);
1762         POSTING_READ(IER);
1763
1764         if (I915_HAS_HOTPLUG(dev)) {
1765                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1766
1767                 /* Note HDMI and DP share bits */
1768                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1769                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1770                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1771                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1772                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1773                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1774                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1775                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1776                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1777                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1778                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1779                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1780
1781                         /* Programming the CRT detection parameters tends
1782                            to generate a spurious hotplug event about three
1783                            seconds later.  So just do it once.
1784                         */
1785                         if (IS_G4X(dev))
1786                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1787                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1788                 }
1789
1790                 /* Ignore TV since it's buggy */
1791
1792                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1793         }
1794
1795         intel_opregion_enable_asle(dev);
1796
1797         return 0;
1798 }
1799
1800 void ironlake_irq_uninstall(struct drm_device *dev)
1801 {
1802         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1803
1804         if (!dev_priv)
1805                 return;
1806
1807         dev_priv->vblank_pipe = 0;
1808
1809         I915_WRITE(HWSTAM, 0xffffffff);
1810
1811         I915_WRITE(DEIMR, 0xffffffff);
1812         I915_WRITE(DEIER, 0x0);
1813         I915_WRITE(DEIIR, I915_READ(DEIIR));
1814
1815         I915_WRITE(GTIMR, 0xffffffff);
1816         I915_WRITE(GTIER, 0x0);
1817         I915_WRITE(GTIIR, I915_READ(GTIIR));
1818 }
1819
1820 void i915_driver_irq_uninstall(struct drm_device * dev)
1821 {
1822         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1823         int pipe;
1824
1825         if (!dev_priv)
1826                 return;
1827
1828         dev_priv->vblank_pipe = 0;
1829
1830         if (I915_HAS_HOTPLUG(dev)) {
1831                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1832                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1833         }
1834
1835         I915_WRITE(HWSTAM, 0xffffffff);
1836         for_each_pipe(pipe)
1837                 I915_WRITE(PIPESTAT(pipe), 0);
1838         I915_WRITE(IMR, 0xffffffff);
1839         I915_WRITE(IER, 0x0);
1840
1841         for_each_pipe(pipe)
1842                 I915_WRITE(PIPESTAT(pipe),
1843                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
1844         I915_WRITE(IIR, I915_READ(IIR));
1845 }