drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 void
  89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92                 u32 reg = PIPESTAT(pipe);
  93
  94                 dev_priv->pipestat[pipe] |= mask;
  95                 /* Enable the interrupt, clear any pending status */
  96                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97                 POSTING_READ(reg);
  98         }
  99 }
 100
 101 void
 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = PIPESTAT(pipe);
 106
 107                 dev_priv->pipestat[pipe] &= ~mask;
 108                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109                 POSTING_READ(reg);
 110         }
 111 }
 112
 113 /**
 114  * intel_enable_asle - enable ASLE interrupt for OpRegion
 115  */
 116 void intel_enable_asle(struct drm_device *dev)
 117 {
 118         drm_i915_private_t *dev_priv = dev->dev_private;
 119         unsigned long irqflags;
 120
 121         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 122
 123         if (HAS_PCH_SPLIT(dev))
 124                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 125         else {
 126                 i915_enable_pipestat(dev_priv, 1,
 127                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 128                 if (INTEL_INFO(dev)->gen >= 4)
 129                         i915_enable_pipestat(dev_priv, 0,
 130                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 131         }
 132
 133         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 134 }
 135
 136 /**
 137  * i915_pipe_enabled - check if a pipe is enabled
 138  * @dev: DRM device
 139  * @pipe: pipe to check
 140  *
 141  * Reading certain registers when the pipe is disabled can hang the chip.
 142  * Use this routine to make sure the PLL is running and the pipe is active
 143  * before reading such registers if unsure.
 144  */
 145 static int
 146 i915_pipe_enabled(struct drm_device *dev, int pipe)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 150 }
 151
 152 /* Called from drm generic code, passed a 'crtc', which
 153  * we use as a pipe index
 154  */
 155 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156 {
 157         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158         unsigned long high_frame;
 159         unsigned long low_frame;
 160         u32 high1, high2, low;
 161
 162         if (!i915_pipe_enabled(dev, pipe)) {
 163                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164                                 "pipe %c\n", pipe_name(pipe));
 165                 return 0;
 166         }
 167
 168         high_frame = PIPEFRAME(pipe);
 169         low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171         /*
 172          * High & low register fields aren't synchronized, so make sure
 173          * we get a low value that's stable across two reads of the high
 174          * register.
 175          */
 176         do {
 177                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180         } while (high1 != high2);
 181
 182         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 183         low >>= PIPE_FRAME_LOW_SHIFT;
 184         return (high1 << 8) | low;
 185 }
 186
 187 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192         if (!i915_pipe_enabled(dev, pipe)) {
 193                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194                                  "pipe %c\n", pipe_name(pipe));
 195                 return 0;
 196         }
 197
 198         return I915_READ(reg);
 199 }
 200
 201 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202                              int *vpos, int *hpos)
 203 {
 204         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205         u32 vbl = 0, position = 0;
 206         int vbl_start, vbl_end, htotal, vtotal;
 207         bool in_vbl = true;
 208         int ret = 0;
 209
 210         if (!i915_pipe_enabled(dev, pipe)) {
 211                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212                                  "pipe %c\n", pipe_name(pipe));
 213                 return 0;
 214         }
 215
 216         /* Get vtotal. */
 217         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 218
 219         if (INTEL_INFO(dev)->gen >= 4) {
 220                 /* No obvious pixelcount register. Only query vertical
 221                  * scanout position from Display scan line register.
 222                  */
 223                 position = I915_READ(PIPEDSL(pipe));
 224
 225                 /* Decode into vertical scanout position. Don't have
 226                  * horizontal scanout position.
 227                  */
 228                 *vpos = position & 0x1fff;
 229                 *hpos = 0;
 230         } else {
 231                 /* Have access to pixelcount since start of frame.
 232                  * We can split this into vertical and horizontal
 233                  * scanout position.
 234                  */
 235                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238                 *vpos = position / htotal;
 239                 *hpos = position - (*vpos * htotal);
 240         }
 241
 242         /* Query vblank area. */
 243         vbl = I915_READ(VBLANK(pipe));
 244
 245         /* Test position against vblank region. */
 246         vbl_start = vbl & 0x1fff;
 247         vbl_end = (vbl >> 16) & 0x1fff;
 248
 249         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250                 in_vbl = false;
 251
 252         /* Inside "upper part" of vblank area? Apply corrective offset: */
 253         if (in_vbl && (*vpos >= vbl_start))
 254                 *vpos = *vpos - vtotal;
 255
 256         /* Readouts valid? */
 257         if (vbl > 0)
 258                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 259
 260         /* In vblank? */
 261         if (in_vbl)
 262                 ret |= DRM_SCANOUTPOS_INVBL;
 263
 264         return ret;
 265 }
 266
 267 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 268                               int *max_error,
 269                               struct timeval *vblank_time,
 270                               unsigned flags)
 271 {
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273         struct drm_crtc *crtc;
 274
 275         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276                 DRM_ERROR("Invalid crtc %d\n", pipe);
 277                 return -EINVAL;
 278         }
 279
 280         /* Get drm_crtc to timestamp: */
 281         crtc = intel_get_crtc_for_pipe(dev, pipe);
 282         if (crtc == NULL) {
 283                 DRM_ERROR("Invalid crtc %d\n", pipe);
 284                 return -EINVAL;
 285         }
 286
 287         if (!crtc->enabled) {
 288                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289                 return -EBUSY;
 290         }
 291
 292         /* Helper routine in DRM core does all the work: */
 293         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294                                                      vblank_time, flags,
 295                                                      crtc);
 296 }
 297
 298 /*
 299  * Handle hotplug events outside the interrupt handler proper.
 300  */
 301 static void i915_hotplug_work_func(struct work_struct *work)
 302 {
 303         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304                                                     hotplug_work);
 305         struct drm_device *dev = dev_priv->dev;
 306         struct drm_mode_config *mode_config = &dev->mode_config;
 307         struct intel_encoder *encoder;
 308
 309         mutex_lock(&mode_config->mutex);
 310         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313                 if (encoder->hot_plug)
 314                         encoder->hot_plug(encoder);
 315
 316         mutex_unlock(&mode_config->mutex);
 317
 318         /* Just fire off a uevent and let userspace tell us what to do */
 319         drm_helper_hpd_irq_event(dev);
 320 }
 321
 322 static void i915_handle_rps_change(struct drm_device *dev)
 323 {
 324         drm_i915_private_t *dev_priv = dev->dev_private;
 325         u32 busy_up, busy_down, max_avg, min_avg;
 326         u8 new_delay = dev_priv->cur_delay;
 327
 328         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329         busy_up = I915_READ(RCPREVBSYTUPAVG);
 330         busy_down = I915_READ(RCPREVBSYTDNAVG);
 331         max_avg = I915_READ(RCBMAXAVG);
 332         min_avg = I915_READ(RCBMINAVG);
 333
 334         /* Handle RCS change request from hw */
 335         if (busy_up > max_avg) {
 336                 if (dev_priv->cur_delay != dev_priv->max_delay)
 337                         new_delay = dev_priv->cur_delay - 1;
 338                 if (new_delay < dev_priv->max_delay)
 339                         new_delay = dev_priv->max_delay;
 340         } else if (busy_down < min_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->min_delay)
 342                         new_delay = dev_priv->cur_delay + 1;
 343                 if (new_delay > dev_priv->min_delay)
 344                         new_delay = dev_priv->min_delay;
 345         }
 346
 347         if (ironlake_set_drps(dev, new_delay))
 348                 dev_priv->cur_delay = new_delay;
 349
 350         return;
 351 }
 352
 353 static void notify_ring(struct drm_device *dev,
 354                         struct intel_ring_buffer *ring)
 355 {
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         u32 seqno;
 358
 359         if (ring->obj == NULL)
 360                 return;
 361
 362         seqno = ring->get_seqno(ring);
 363         trace_i915_gem_request_complete(ring, seqno);
 364
 365         ring->irq_seqno = seqno;
 366         wake_up_all(&ring->irq_queue);
 367         if (i915_enable_hangcheck) {
 368                 dev_priv->hangcheck_count = 0;
 369                 mod_timer(&dev_priv->hangcheck_timer,
 370                           jiffies +
 371                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 372         }
 373 }
 374
 375 static void gen6_pm_rps_work(struct work_struct *work)
 376 {
 377         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378                                                     rps_work);
 379         u8 new_delay = dev_priv->cur_delay;
 380         u32 pm_iir, pm_imr;
 381
 382         spin_lock_irq(&dev_priv->rps_lock);
 383         pm_iir = dev_priv->pm_iir;
 384         dev_priv->pm_iir = 0;
 385         pm_imr = I915_READ(GEN6_PMIMR);
 386         I915_WRITE(GEN6_PMIMR, 0);
 387         spin_unlock_irq(&dev_priv->rps_lock);
 388
 389         if (!pm_iir)
 390                 return;
 391
 392         mutex_lock(&dev_priv->dev->struct_mutex);
 393         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 394                 if (dev_priv->cur_delay != dev_priv->max_delay)
 395                         new_delay = dev_priv->cur_delay + 1;
 396                 if (new_delay > dev_priv->max_delay)
 397                         new_delay = dev_priv->max_delay;
 398         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 399                 gen6_gt_force_wake_get(dev_priv);
 400                 if (dev_priv->cur_delay != dev_priv->min_delay)
 401                         new_delay = dev_priv->cur_delay - 1;
 402                 if (new_delay < dev_priv->min_delay) {
 403                         new_delay = dev_priv->min_delay;
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 406                                    ((new_delay << 16) & 0x3f0000));
 407                 } else {
 408                         /* Make sure we continue to get down interrupts
 409                          * until we hit the minimum frequency */
 410                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 411                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 412                 }
 413                 gen6_gt_force_wake_put(dev_priv);
 414         }
 415
 416         gen6_set_rps(dev_priv->dev, new_delay);
 417         dev_priv->cur_delay = new_delay;
 418
 419         /*
 420          * rps_lock not held here because clearing is non-destructive. There is
 421          * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 422          * by holding struct_mutex for the duration of the write.
 423          */
 424         mutex_unlock(&dev_priv->dev->struct_mutex);
 425 }
 426
 427 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 428                                 u32 pm_iir)
 429 {
 430         unsigned long flags;
 431
 432         /*
 433          * IIR bits should never already be set because IMR should
 434          * prevent an interrupt from being shown in IIR. The warning
 435          * displays a case where we've unsafely cleared
 436          * dev_priv->pm_iir. Although missing an interrupt of the same
 437          * type is not a problem, it displays a problem in the logic.
 438          *
 439          * The mask bit in IMR is cleared by rps_work.
 440          */
 441
 442         spin_lock_irqsave(&dev_priv->rps_lock, flags);
 443         dev_priv->pm_iir |= pm_iir;
 444         I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
 445         POSTING_READ(GEN6_PMIMR);
 446         spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 447
 448         queue_work(dev_priv->wq, &dev_priv->rps_work);
 449 }
 450
 451 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
 452 {
 453         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 454         int pipe;
 455
 456         if (pch_iir & SDE_AUDIO_POWER_MASK)
 457                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 458                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 459                                  SDE_AUDIO_POWER_SHIFT);
 460
 461         if (pch_iir & SDE_GMBUS)
 462                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 463
 464         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 465                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 466
 467         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 468                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 469
 470         if (pch_iir & SDE_POISON)
 471                 DRM_ERROR("PCH poison interrupt\n");
 472
 473         if (pch_iir & SDE_FDI_MASK)
 474                 for_each_pipe(pipe)
 475                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 476                                          pipe_name(pipe),
 477                                          I915_READ(FDI_RX_IIR(pipe)));
 478
 479         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 480                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 481
 482         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 483                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 484
 485         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 486                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 487         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 488                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 489 }
 490
 491 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 492 {
 493         struct drm_device *dev = (struct drm_device *) arg;
 494         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 495         int ret = IRQ_NONE;
 496         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 497         struct drm_i915_master_private *master_priv;
 498
 499         atomic_inc(&dev_priv->irq_received);
 500
 501         /* disable master interrupt before clearing iir  */
 502         de_ier = I915_READ(DEIER);
 503         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 504         POSTING_READ(DEIER);
 505
 506         de_iir = I915_READ(DEIIR);
 507         gt_iir = I915_READ(GTIIR);
 508         pch_iir = I915_READ(SDEIIR);
 509         pm_iir = I915_READ(GEN6_PMIIR);
 510
 511         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 512                 goto done;
 513
 514         ret = IRQ_HANDLED;
 515
 516         if (dev->primary->master) {
 517                 master_priv = dev->primary->master->driver_priv;
 518                 if (master_priv->sarea_priv)
 519                         master_priv->sarea_priv->last_dispatch =
 520                                 READ_BREADCRUMB(dev_priv);
 521         }
 522
 523         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 524                 notify_ring(dev, &dev_priv->ring[RCS]);
 525         if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 526                 notify_ring(dev, &dev_priv->ring[VCS]);
 527         if (gt_iir & GT_BLT_USER_INTERRUPT)
 528                 notify_ring(dev, &dev_priv->ring[BCS]);
 529
 530         if (de_iir & DE_GSE_IVB)
 531                 intel_opregion_gse_intr(dev);
 532
 533         if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 534                 intel_prepare_page_flip(dev, 0);
 535                 intel_finish_page_flip_plane(dev, 0);
 536         }
 537
 538         if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 539                 intel_prepare_page_flip(dev, 1);
 540                 intel_finish_page_flip_plane(dev, 1);
 541         }
 542
 543         if (de_iir & DE_PIPEA_VBLANK_IVB)
 544                 drm_handle_vblank(dev, 0);
 545
 546         if (de_iir & DE_PIPEB_VBLANK_IVB)
 547                 drm_handle_vblank(dev, 1);
 548
 549         /* check event from PCH */
 550         if (de_iir & DE_PCH_EVENT_IVB) {
 551                 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 552                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 553                 pch_irq_handler(dev, pch_iir);
 554         }
 555
 556         if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 557                 gen6_queue_rps_work(dev_priv, pm_iir);
 558
 559         /* should clear PCH hotplug event before clear CPU irq */
 560         I915_WRITE(SDEIIR, pch_iir);
 561         I915_WRITE(GTIIR, gt_iir);
 562         I915_WRITE(DEIIR, de_iir);
 563         I915_WRITE(GEN6_PMIIR, pm_iir);
 564
 565 done:
 566         I915_WRITE(DEIER, de_ier);
 567         POSTING_READ(DEIER);
 568
 569         return ret;
 570 }
 571
 572 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 573 {
 574         struct drm_device *dev = (struct drm_device *) arg;
 575         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 576         int ret = IRQ_NONE;
 577         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 578         u32 hotplug_mask;
 579         struct drm_i915_master_private *master_priv;
 580         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 581
 582         atomic_inc(&dev_priv->irq_received);
 583
 584         if (IS_GEN6(dev))
 585                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 586
 587         /* disable master interrupt before clearing iir  */
 588         de_ier = I915_READ(DEIER);
 589         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 590         POSTING_READ(DEIER);
 591
 592         de_iir = I915_READ(DEIIR);
 593         gt_iir = I915_READ(GTIIR);
 594         pch_iir = I915_READ(SDEIIR);
 595         pm_iir = I915_READ(GEN6_PMIIR);
 596
 597         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 598             (!IS_GEN6(dev) || pm_iir == 0))
 599                 goto done;
 600
 601         if (HAS_PCH_CPT(dev))
 602                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 603         else
 604                 hotplug_mask = SDE_HOTPLUG_MASK;
 605
 606         ret = IRQ_HANDLED;
 607
 608         if (dev->primary->master) {
 609                 master_priv = dev->primary->master->driver_priv;
 610                 if (master_priv->sarea_priv)
 611                         master_priv->sarea_priv->last_dispatch =
 612                                 READ_BREADCRUMB(dev_priv);
 613         }
 614
 615         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 616                 notify_ring(dev, &dev_priv->ring[RCS]);
 617         if (gt_iir & bsd_usr_interrupt)
 618                 notify_ring(dev, &dev_priv->ring[VCS]);
 619         if (gt_iir & GT_BLT_USER_INTERRUPT)
 620                 notify_ring(dev, &dev_priv->ring[BCS]);
 621
 622         if (de_iir & DE_GSE)
 623                 intel_opregion_gse_intr(dev);
 624
 625         if (de_iir & DE_PLANEA_FLIP_DONE) {
 626                 intel_prepare_page_flip(dev, 0);
 627                 intel_finish_page_flip_plane(dev, 0);
 628         }
 629
 630         if (de_iir & DE_PLANEB_FLIP_DONE) {
 631                 intel_prepare_page_flip(dev, 1);
 632                 intel_finish_page_flip_plane(dev, 1);
 633         }
 634
 635         if (de_iir & DE_PIPEA_VBLANK)
 636                 drm_handle_vblank(dev, 0);
 637
 638         if (de_iir & DE_PIPEB_VBLANK)
 639                 drm_handle_vblank(dev, 1);
 640
 641         /* check event from PCH */
 642         if (de_iir & DE_PCH_EVENT) {
 643                 if (pch_iir & hotplug_mask)
 644                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 645                 pch_irq_handler(dev, pch_iir);
 646         }
 647
 648         if (de_iir & DE_PCU_EVENT) {
 649                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 650                 i915_handle_rps_change(dev);
 651         }
 652
 653         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 654                 gen6_queue_rps_work(dev_priv, pm_iir);
 655
 656         /* should clear PCH hotplug event before clear CPU irq */
 657         I915_WRITE(SDEIIR, pch_iir);
 658         I915_WRITE(GTIIR, gt_iir);
 659         I915_WRITE(DEIIR, de_iir);
 660         I915_WRITE(GEN6_PMIIR, pm_iir);
 661
 662 done:
 663         I915_WRITE(DEIER, de_ier);
 664         POSTING_READ(DEIER);
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * i915_error_work_func - do process context error handling work
 671  * @work: work struct
 672  *
 673  * Fire an error uevent so userspace can see that a hang or error
 674  * was detected.
 675  */
 676 static void i915_error_work_func(struct work_struct *work)
 677 {
 678         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 679                                                     error_work);
 680         struct drm_device *dev = dev_priv->dev;
 681         char *error_event[] = { "ERROR=1", NULL };
 682         char *reset_event[] = { "RESET=1", NULL };
 683         char *reset_done_event[] = { "ERROR=0", NULL };
 684
 685         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 686
 687         if (atomic_read(&dev_priv->mm.wedged)) {
 688                 DRM_DEBUG_DRIVER("resetting chip\n");
 689                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 690                 if (!i915_reset(dev, GRDOM_RENDER)) {
 691                         atomic_set(&dev_priv->mm.wedged, 0);
 692                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 693                 }
 694                 complete_all(&dev_priv->error_completion);
 695         }
 696 }
 697
 698 #ifdef CONFIG_DEBUG_FS
 699 static struct drm_i915_error_object *
 700 i915_error_object_create(struct drm_i915_private *dev_priv,
 701                          struct drm_i915_gem_object *src)
 702 {
 703         struct drm_i915_error_object *dst;
 704         int page, page_count;
 705         u32 reloc_offset;
 706
 707         if (src == NULL || src->pages == NULL)
 708                 return NULL;
 709
 710         page_count = src->base.size / PAGE_SIZE;
 711
 712         dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
 713         if (dst == NULL)
 714                 return NULL;
 715
 716         reloc_offset = src->gtt_offset;
 717         for (page = 0; page < page_count; page++) {
 718                 unsigned long flags;
 719                 void __iomem *s;
 720                 void *d;
 721
 722                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 723                 if (d == NULL)
 724                         goto unwind;
 725
 726                 local_irq_save(flags);
 727                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 728                                              reloc_offset);
 729                 memcpy_fromio(d, s, PAGE_SIZE);
 730                 io_mapping_unmap_atomic(s);
 731                 local_irq_restore(flags);
 732
 733                 dst->pages[page] = d;
 734
 735                 reloc_offset += PAGE_SIZE;
 736         }
 737         dst->page_count = page_count;
 738         dst->gtt_offset = src->gtt_offset;
 739
 740         return dst;
 741
 742 unwind:
 743         while (page--)
 744                 kfree(dst->pages[page]);
 745         kfree(dst);
 746         return NULL;
 747 }
 748
 749 static void
 750 i915_error_object_free(struct drm_i915_error_object *obj)
 751 {
 752         int page;
 753
 754         if (obj == NULL)
 755                 return;
 756
 757         for (page = 0; page < obj->page_count; page++)
 758                 kfree(obj->pages[page]);
 759
 760         kfree(obj);
 761 }
 762
 763 static void
 764 i915_error_state_free(struct drm_device *dev,
 765                       struct drm_i915_error_state *error)
 766 {
 767         int i;
 768
 769         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 770                 i915_error_object_free(error->batchbuffer[i]);
 771
 772         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 773                 i915_error_object_free(error->ringbuffer[i]);
 774
 775         kfree(error->active_bo);
 776         kfree(error->overlay);
 777         kfree(error);
 778 }
 779
 780 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 781                            int count,
 782                            struct list_head *head)
 783 {
 784         struct drm_i915_gem_object *obj;
 785         int i = 0;
 786
 787         list_for_each_entry(obj, head, mm_list) {
 788                 err->size = obj->base.size;
 789                 err->name = obj->base.name;
 790                 err->seqno = obj->last_rendering_seqno;
 791                 err->gtt_offset = obj->gtt_offset;
 792                 err->read_domains = obj->base.read_domains;
 793                 err->write_domain = obj->base.write_domain;
 794                 err->fence_reg = obj->fence_reg;
 795                 err->pinned = 0;
 796                 if (obj->pin_count > 0)
 797                         err->pinned = 1;
 798                 if (obj->user_pin_count > 0)
 799                         err->pinned = -1;
 800                 err->tiling = obj->tiling_mode;
 801                 err->dirty = obj->dirty;
 802                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 803                 err->ring = obj->ring ? obj->ring->id : 0;
 804                 err->cache_level = obj->cache_level;
 805
 806                 if (++i == count)
 807                         break;
 808
 809                 err++;
 810         }
 811
 812         return i;
 813 }
 814
 815 static void i915_gem_record_fences(struct drm_device *dev,
 816                                    struct drm_i915_error_state *error)
 817 {
 818         struct drm_i915_private *dev_priv = dev->dev_private;
 819         int i;
 820
 821         /* Fences */
 822         switch (INTEL_INFO(dev)->gen) {
 823         case 7:
 824         case 6:
 825                 for (i = 0; i < 16; i++)
 826                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 827                 break;
 828         case 5:
 829         case 4:
 830                 for (i = 0; i < 16; i++)
 831                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 832                 break;
 833         case 3:
 834                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 835                         for (i = 0; i < 8; i++)
 836                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 837         case 2:
 838                 for (i = 0; i < 8; i++)
 839                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 840                 break;
 841
 842         }
 843 }
 844
 845 static struct drm_i915_error_object *
 846 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 847                              struct intel_ring_buffer *ring)
 848 {
 849         struct drm_i915_gem_object *obj;
 850         u32 seqno;
 851
 852         if (!ring->get_seqno)
 853                 return NULL;
 854
 855         seqno = ring->get_seqno(ring);
 856         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 857                 if (obj->ring != ring)
 858                         continue;
 859
 860                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 861                         continue;
 862
 863                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 864                         continue;
 865
 866                 /* We need to copy these to an anonymous buffer as the simplest
 867                  * method to avoid being overwritten by userspace.
 868                  */
 869                 return i915_error_object_create(dev_priv, obj);
 870         }
 871
 872         return NULL;
 873 }
 874
 875 /**
 876  * i915_capture_error_state - capture an error record for later analysis
 877  * @dev: drm device
 878  *
 879  * Should be called when an error is detected (either a hang or an error
 880  * interrupt) to capture error state from the time of the error.  Fills
 881  * out a structure which becomes available in debugfs for user level tools
 882  * to pick up.
 883  */
 884 static void i915_capture_error_state(struct drm_device *dev)
 885 {
 886         struct drm_i915_private *dev_priv = dev->dev_private;
 887         struct drm_i915_gem_object *obj;
 888         struct drm_i915_error_state *error;
 889         unsigned long flags;
 890         int i, pipe;
 891
 892         spin_lock_irqsave(&dev_priv->error_lock, flags);
 893         error = dev_priv->first_error;
 894         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 895         if (error)
 896                 return;
 897
 898         /* Account for pipe specific data like PIPE*STAT */
 899         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 900         if (!error) {
 901                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 902                 return;
 903         }
 904
 905         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 906                  dev->primary->index);
 907
 908         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 909         error->eir = I915_READ(EIR);
 910         error->pgtbl_er = I915_READ(PGTBL_ER);
 911         for_each_pipe(pipe)
 912                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 913         error->instpm = I915_READ(INSTPM);
 914         error->error = 0;
 915         if (INTEL_INFO(dev)->gen >= 6) {
 916                 error->error = I915_READ(ERROR_GEN6);
 917
 918                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 919                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 920                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 921                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 922                 error->bcs_seqno = 0;
 923                 if (dev_priv->ring[BCS].get_seqno)
 924                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 925
 926                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 927                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 928                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 929                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 930                 error->vcs_seqno = 0;
 931                 if (dev_priv->ring[VCS].get_seqno)
 932                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 933         }
 934         if (INTEL_INFO(dev)->gen >= 4) {
 935                 error->ipeir = I915_READ(IPEIR_I965);
 936                 error->ipehr = I915_READ(IPEHR_I965);
 937                 error->instdone = I915_READ(INSTDONE_I965);
 938                 error->instps = I915_READ(INSTPS);
 939                 error->instdone1 = I915_READ(INSTDONE1);
 940                 error->acthd = I915_READ(ACTHD_I965);
 941                 error->bbaddr = I915_READ64(BB_ADDR);
 942         } else {
 943                 error->ipeir = I915_READ(IPEIR);
 944                 error->ipehr = I915_READ(IPEHR);
 945                 error->instdone = I915_READ(INSTDONE);
 946                 error->acthd = I915_READ(ACTHD);
 947                 error->bbaddr = 0;
 948         }
 949         i915_gem_record_fences(dev, error);
 950
 951         /* Record the active batch and ring buffers */
 952         for (i = 0; i < I915_NUM_RINGS; i++) {
 953                 error->batchbuffer[i] =
 954                         i915_error_first_batchbuffer(dev_priv,
 955                                                      &dev_priv->ring[i]);
 956
 957                 error->ringbuffer[i] =
 958                         i915_error_object_create(dev_priv,
 959                                                  dev_priv->ring[i].obj);
 960         }
 961
 962         /* Record buffers on the active and pinned lists. */
 963         error->active_bo = NULL;
 964         error->pinned_bo = NULL;
 965
 966         i = 0;
 967         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 968                 i++;
 969         error->active_bo_count = i;
 970         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 971                 i++;
 972         error->pinned_bo_count = i - error->active_bo_count;
 973
 974         error->active_bo = NULL;
 975         error->pinned_bo = NULL;
 976         if (i) {
 977                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 978                                            GFP_ATOMIC);
 979                 if (error->active_bo)
 980                         error->pinned_bo =
 981                                 error->active_bo + error->active_bo_count;
 982         }
 983
 984         if (error->active_bo)
 985                 error->active_bo_count =
 986                         capture_bo_list(error->active_bo,
 987                                         error->active_bo_count,
 988                                         &dev_priv->mm.active_list);
 989
 990         if (error->pinned_bo)
 991                 error->pinned_bo_count =
 992                         capture_bo_list(error->pinned_bo,
 993                                         error->pinned_bo_count,
 994                                         &dev_priv->mm.pinned_list);
 995
 996         do_gettimeofday(&error->time);
 997
 998         error->overlay = intel_overlay_capture_error_state(dev);
 999         error->display = intel_display_capture_error_state(dev);
1000
1001         spin_lock_irqsave(&dev_priv->error_lock, flags);
1002         if (dev_priv->first_error == NULL) {
1003                 dev_priv->first_error = error;
1004                 error = NULL;
1005         }
1006         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1007
1008         if (error)
1009                 i915_error_state_free(dev, error);
1010 }
1011
1012 void i915_destroy_error_state(struct drm_device *dev)
1013 {
1014         struct drm_i915_private *dev_priv = dev->dev_private;
1015         struct drm_i915_error_state *error;
1016
1017         spin_lock(&dev_priv->error_lock);
1018         error = dev_priv->first_error;
1019         dev_priv->first_error = NULL;
1020         spin_unlock(&dev_priv->error_lock);
1021
1022         if (error)
1023                 i915_error_state_free(dev, error);
1024 }
1025 #else
1026 #define i915_capture_error_state(x)
1027 #endif
1028
1029 static void i915_report_and_clear_eir(struct drm_device *dev)
1030 {
1031         struct drm_i915_private *dev_priv = dev->dev_private;
1032         u32 eir = I915_READ(EIR);
1033         int pipe;
1034
1035         if (!eir)
1036                 return;
1037
1038         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1039                eir);
1040
1041         if (IS_G4X(dev)) {
1042                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1043                         u32 ipeir = I915_READ(IPEIR_I965);
1044
1045                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1046                                I915_READ(IPEIR_I965));
1047                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1048                                I915_READ(IPEHR_I965));
1049                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1050                                I915_READ(INSTDONE_I965));
1051                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1052                                I915_READ(INSTPS));
1053                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1054                                I915_READ(INSTDONE1));
1055                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1056                                I915_READ(ACTHD_I965));
1057                         I915_WRITE(IPEIR_I965, ipeir);
1058                         POSTING_READ(IPEIR_I965);
1059                 }
1060                 if (eir & GM45_ERROR_PAGE_TABLE) {
1061                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1062                         printk(KERN_ERR "page table error\n");
1063                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1064                                pgtbl_err);
1065                         I915_WRITE(PGTBL_ER, pgtbl_err);
1066                         POSTING_READ(PGTBL_ER);
1067                 }
1068         }
1069
1070         if (!IS_GEN2(dev)) {
1071                 if (eir & I915_ERROR_PAGE_TABLE) {
1072                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1073                         printk(KERN_ERR "page table error\n");
1074                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1075                                pgtbl_err);
1076                         I915_WRITE(PGTBL_ER, pgtbl_err);
1077                         POSTING_READ(PGTBL_ER);
1078                 }
1079         }
1080
1081         if (eir & I915_ERROR_MEMORY_REFRESH) {
1082                 printk(KERN_ERR "memory refresh error:\n");
1083                 for_each_pipe(pipe)
1084                         printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1085                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1086                 /* pipestat has already been acked */
1087         }
1088         if (eir & I915_ERROR_INSTRUCTION) {
1089                 printk(KERN_ERR "instruction error\n");
1090                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
1091                        I915_READ(INSTPM));
1092                 if (INTEL_INFO(dev)->gen < 4) {
1093                         u32 ipeir = I915_READ(IPEIR);
1094
1095                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1096                                I915_READ(IPEIR));
1097                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1098                                I915_READ(IPEHR));
1099                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1100                                I915_READ(INSTDONE));
1101                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1102                                I915_READ(ACTHD));
1103                         I915_WRITE(IPEIR, ipeir);
1104                         POSTING_READ(IPEIR);
1105                 } else {
1106                         u32 ipeir = I915_READ(IPEIR_I965);
1107
1108                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
1109                                I915_READ(IPEIR_I965));
1110                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
1111                                I915_READ(IPEHR_I965));
1112                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1113                                I915_READ(INSTDONE_I965));
1114                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1115                                I915_READ(INSTPS));
1116                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1117                                I915_READ(INSTDONE1));
1118                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1119                                I915_READ(ACTHD_I965));
1120                         I915_WRITE(IPEIR_I965, ipeir);
1121                         POSTING_READ(IPEIR_I965);
1122                 }
1123         }
1124
1125         I915_WRITE(EIR, eir);
1126         POSTING_READ(EIR);
1127         eir = I915_READ(EIR);
1128         if (eir) {
1129                 /*
1130                  * some errors might have become stuck,
1131                  * mask them.
1132                  */
1133                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1134                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1135                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1136         }
1137 }
1138
1139 /**
1140  * i915_handle_error - handle an error interrupt
1141  * @dev: drm device
1142  *
1143  * Do some basic checking of regsiter state at error interrupt time and
1144  * dump it to the syslog.  Also call i915_capture_error_state() to make
1145  * sure we get a record and make it available in debugfs.  Fire a uevent
1146  * so userspace knows something bad happened (should trigger collection
1147  * of a ring dump etc.).
1148  */
1149 void i915_handle_error(struct drm_device *dev, bool wedged)
1150 {
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152
1153         i915_capture_error_state(dev);
1154         i915_report_and_clear_eir(dev);
1155
1156         if (wedged) {
1157                 INIT_COMPLETION(dev_priv->error_completion);
1158                 atomic_set(&dev_priv->mm.wedged, 1);
1159
1160                 /*
1161                  * Wakeup waiting processes so they don't hang
1162                  */
1163                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1164                 if (HAS_BSD(dev))
1165                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1166                 if (HAS_BLT(dev))
1167                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1168         }
1169
1170         queue_work(dev_priv->wq, &dev_priv->error_work);
1171 }
1172
1173 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1174 {
1175         drm_i915_private_t *dev_priv = dev->dev_private;
1176         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1178         struct drm_i915_gem_object *obj;
1179         struct intel_unpin_work *work;
1180         unsigned long flags;
1181         bool stall_detected;
1182
1183         /* Ignore early vblank irqs */
1184         if (intel_crtc == NULL)
1185                 return;
1186
1187         spin_lock_irqsave(&dev->event_lock, flags);
1188         work = intel_crtc->unpin_work;
1189
1190         if (work == NULL || work->pending || !work->enable_stall_check) {
1191                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1192                 spin_unlock_irqrestore(&dev->event_lock, flags);
1193                 return;
1194         }
1195
1196         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1197         obj = work->pending_flip_obj;
1198         if (INTEL_INFO(dev)->gen >= 4) {
1199                 int dspsurf = DSPSURF(intel_crtc->plane);
1200                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1201         } else {
1202                 int dspaddr = DSPADDR(intel_crtc->plane);
1203                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1204                                                         crtc->y * crtc->fb->pitch +
1205                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1206         }
1207
1208         spin_unlock_irqrestore(&dev->event_lock, flags);
1209
1210         if (stall_detected) {
1211                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1212                 intel_prepare_page_flip(dev, intel_crtc->plane);
1213         }
1214 }
1215
1216 static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1217 {
1218         struct drm_device *dev = (struct drm_device *) arg;
1219         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1220         struct drm_i915_master_private *master_priv;
1221         u32 iir, new_iir;
1222         u32 pipe_stats[I915_MAX_PIPES];
1223         u32 vblank_status;
1224         int vblank = 0;
1225         unsigned long irqflags;
1226         int irq_received;
1227         int ret = IRQ_NONE, pipe;
1228         bool blc_event = false;
1229
1230         atomic_inc(&dev_priv->irq_received);
1231
1232         iir = I915_READ(IIR);
1233
1234         if (INTEL_INFO(dev)->gen >= 4)
1235                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1236         else
1237                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1238
1239         for (;;) {
1240                 irq_received = iir != 0;
1241
1242                 /* Can't rely on pipestat interrupt bit in iir as it might
1243                  * have been cleared after the pipestat interrupt was received.
1244                  * It doesn't set the bit in iir again, but it still produces
1245                  * interrupts (for non-MSI).
1246                  */
1247                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1248                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1249                         i915_handle_error(dev, false);
1250
1251                 for_each_pipe(pipe) {
1252                         int reg = PIPESTAT(pipe);
1253                         pipe_stats[pipe] = I915_READ(reg);
1254
1255                         /*
1256                          * Clear the PIPE*STAT regs before the IIR
1257                          */
1258                         if (pipe_stats[pipe] & 0x8000ffff) {
1259                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1260                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1261                                                          pipe_name(pipe));
1262                                 I915_WRITE(reg, pipe_stats[pipe]);
1263                                 irq_received = 1;
1264                         }
1265                 }
1266                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1267
1268                 if (!irq_received)
1269                         break;
1270
1271                 ret = IRQ_HANDLED;
1272
1273                 /* Consume port.  Then clear IIR or we'll miss events */
1274                 if ((I915_HAS_HOTPLUG(dev)) &&
1275                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1276                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1277
1278                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1279                                   hotplug_status);
1280                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1281                                 queue_work(dev_priv->wq,
1282                                            &dev_priv->hotplug_work);
1283
1284                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1285                         I915_READ(PORT_HOTPLUG_STAT);
1286                 }
1287
1288                 I915_WRITE(IIR, iir);
1289                 new_iir = I915_READ(IIR); /* Flush posted writes */
1290
1291                 if (dev->primary->master) {
1292                         master_priv = dev->primary->master->driver_priv;
1293                         if (master_priv->sarea_priv)
1294                                 master_priv->sarea_priv->last_dispatch =
1295                                         READ_BREADCRUMB(dev_priv);
1296                 }
1297
1298                 if (iir & I915_USER_INTERRUPT)
1299                         notify_ring(dev, &dev_priv->ring[RCS]);
1300                 if (iir & I915_BSD_USER_INTERRUPT)
1301                         notify_ring(dev, &dev_priv->ring[VCS]);
1302
1303                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1304                         intel_prepare_page_flip(dev, 0);
1305                         if (dev_priv->flip_pending_is_done)
1306                                 intel_finish_page_flip_plane(dev, 0);
1307                 }
1308
1309                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1310                         intel_prepare_page_flip(dev, 1);
1311                         if (dev_priv->flip_pending_is_done)
1312                                 intel_finish_page_flip_plane(dev, 1);
1313                 }
1314
1315                 for_each_pipe(pipe) {
1316                         if (pipe_stats[pipe] & vblank_status &&
1317                             drm_handle_vblank(dev, pipe)) {
1318                                 vblank++;
1319                                 if (!dev_priv->flip_pending_is_done) {
1320                                         i915_pageflip_stall_check(dev, pipe);
1321                                         intel_finish_page_flip(dev, pipe);
1322                                 }
1323                         }
1324
1325                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1326                                 blc_event = true;
1327                 }
1328
1329
1330                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1331                         intel_opregion_asle_intr(dev);
1332
1333                 /* With MSI, interrupts are only generated when iir
1334                  * transitions from zero to nonzero.  If another bit got
1335                  * set while we were handling the existing iir bits, then
1336                  * we would never get another interrupt.
1337                  *
1338                  * This is fine on non-MSI as well, as if we hit this path
1339                  * we avoid exiting the interrupt handler only to generate
1340                  * another one.
1341                  *
1342                  * Note that for MSI this could cause a stray interrupt report
1343                  * if an interrupt landed in the time between writing IIR and
1344                  * the posting read.  This should be rare enough to never
1345                  * trigger the 99% of 100,000 interrupts test for disabling
1346                  * stray interrupts.
1347                  */
1348                 iir = new_iir;
1349         }
1350
1351         return ret;
1352 }
1353
1354 static int i915_emit_irq(struct drm_device * dev)
1355 {
1356         drm_i915_private_t *dev_priv = dev->dev_private;
1357         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1358
1359         i915_kernel_lost_context(dev);
1360
1361         DRM_DEBUG_DRIVER("\n");
1362
1363         dev_priv->counter++;
1364         if (dev_priv->counter > 0x7FFFFFFFUL)
1365                 dev_priv->counter = 1;
1366         if (master_priv->sarea_priv)
1367                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1368
1369         if (BEGIN_LP_RING(4) == 0) {
1370                 OUT_RING(MI_STORE_DWORD_INDEX);
1371                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1372                 OUT_RING(dev_priv->counter);
1373                 OUT_RING(MI_USER_INTERRUPT);
1374                 ADVANCE_LP_RING();
1375         }
1376
1377         return dev_priv->counter;
1378 }
1379
1380 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1381 {
1382         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1383         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1384         int ret = 0;
1385         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1386
1387         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1388                   READ_BREADCRUMB(dev_priv));
1389
1390         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1391                 if (master_priv->sarea_priv)
1392                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1393                 return 0;
1394         }
1395
1396         if (master_priv->sarea_priv)
1397                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1398
1399         if (ring->irq_get(ring)) {
1400                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1401                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1402                 ring->irq_put(ring);
1403         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1404                 ret = -EBUSY;
1405
1406         if (ret == -EBUSY) {
1407                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1408                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1409         }
1410
1411         return ret;
1412 }
1413
1414 /* Needs the lock as it touches the ring.
1415  */
1416 int i915_irq_emit(struct drm_device *dev, void *data,
1417                          struct drm_file *file_priv)
1418 {
1419         drm_i915_private_t *dev_priv = dev->dev_private;
1420         drm_i915_irq_emit_t *emit = data;
1421         int result;
1422
1423         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1424                 DRM_ERROR("called with no initialization\n");
1425                 return -EINVAL;
1426         }
1427
1428         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1429
1430         mutex_lock(&dev->struct_mutex);
1431         result = i915_emit_irq(dev);
1432         mutex_unlock(&dev->struct_mutex);
1433
1434         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1435                 DRM_ERROR("copy_to_user\n");
1436                 return -EFAULT;
1437         }
1438
1439         return 0;
1440 }
1441
1442 /* Doesn't need the hardware lock.
1443  */
1444 int i915_irq_wait(struct drm_device *dev, void *data,
1445                          struct drm_file *file_priv)
1446 {
1447         drm_i915_private_t *dev_priv = dev->dev_private;
1448         drm_i915_irq_wait_t *irqwait = data;
1449
1450         if (!dev_priv) {
1451                 DRM_ERROR("called with no initialization\n");
1452                 return -EINVAL;
1453         }
1454
1455         return i915_wait_irq(dev, irqwait->irq_seq);
1456 }
1457
1458 /* Called from drm generic code, passed 'crtc' which
1459  * we use as a pipe index
1460  */
1461 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1462 {
1463         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1464         unsigned long irqflags;
1465
1466         if (!i915_pipe_enabled(dev, pipe))
1467                 return -EINVAL;
1468
1469         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1470         if (INTEL_INFO(dev)->gen >= 4)
1471                 i915_enable_pipestat(dev_priv, pipe,
1472                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1473         else
1474                 i915_enable_pipestat(dev_priv, pipe,
1475                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1476
1477         /* maintain vblank delivery even in deep C-states */
1478         if (dev_priv->info->gen == 3)
1479                 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1480         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1481
1482         return 0;
1483 }
1484
1485 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1486 {
1487         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1488         unsigned long irqflags;
1489
1490         if (!i915_pipe_enabled(dev, pipe))
1491                 return -EINVAL;
1492
1493         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1494         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1495                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1496         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1497
1498         return 0;
1499 }
1500
1501 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1502 {
1503         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1504         unsigned long irqflags;
1505
1506         if (!i915_pipe_enabled(dev, pipe))
1507                 return -EINVAL;
1508
1509         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1510         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1511                                     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1513
1514         return 0;
1515 }
1516
1517 /* Called from drm generic code, passed 'crtc' which
1518  * we use as a pipe index
1519  */
1520 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1521 {
1522         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1523         unsigned long irqflags;
1524
1525         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1526         if (dev_priv->info->gen == 3)
1527                 I915_WRITE(INSTPM,
1528                            INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1529
1530         i915_disable_pipestat(dev_priv, pipe,
1531                               PIPE_VBLANK_INTERRUPT_ENABLE |
1532                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1533         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1534 }
1535
1536 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1537 {
1538         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1539         unsigned long irqflags;
1540
1541         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1542         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1543                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1544         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1545 }
1546
1547 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1548 {
1549         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1550         unsigned long irqflags;
1551
1552         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1553         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1554                                      DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1555         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1556 }
1557
1558 /* Set the vblank monitor pipe
1559  */
1560 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1561                          struct drm_file *file_priv)
1562 {
1563         drm_i915_private_t *dev_priv = dev->dev_private;
1564
1565         if (!dev_priv) {
1566                 DRM_ERROR("called with no initialization\n");
1567                 return -EINVAL;
1568         }
1569
1570         return 0;
1571 }
1572
1573 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1574                          struct drm_file *file_priv)
1575 {
1576         drm_i915_private_t *dev_priv = dev->dev_private;
1577         drm_i915_vblank_pipe_t *pipe = data;
1578
1579         if (!dev_priv) {
1580                 DRM_ERROR("called with no initialization\n");
1581                 return -EINVAL;
1582         }
1583
1584         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1585
1586         return 0;
1587 }
1588
1589 /**
1590  * Schedule buffer swap at given vertical blank.
1591  */
1592 int i915_vblank_swap(struct drm_device *dev, void *data,
1593                      struct drm_file *file_priv)
1594 {
1595         /* The delayed swap mechanism was fundamentally racy, and has been
1596          * removed.  The model was that the client requested a delayed flip/swap
1597          * from the kernel, then waited for vblank before continuing to perform
1598          * rendering.  The problem was that the kernel might wake the client
1599          * up before it dispatched the vblank swap (since the lock has to be
1600          * held while touching the ringbuffer), in which case the client would
1601          * clear and start the next frame before the swap occurred, and
1602          * flicker would occur in addition to likely missing the vblank.
1603          *
1604          * In the absence of this ioctl, userland falls back to a correct path
1605          * of waiting for a vblank, then dispatching the swap on its own.
1606          * Context switching to userland and back is plenty fast enough for
1607          * meeting the requirements of vblank swapping.
1608          */
1609         return -EINVAL;
1610 }
1611
1612 static u32
1613 ring_last_seqno(struct intel_ring_buffer *ring)
1614 {
1615         return list_entry(ring->request_list.prev,
1616                           struct drm_i915_gem_request, list)->seqno;
1617 }
1618
1619 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1620 {
1621         if (list_empty(&ring->request_list) ||
1622             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1623                 /* Issue a wake-up to catch stuck h/w. */
1624                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1625                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1626                                   ring->name,
1627                                   ring->waiting_seqno,
1628                                   ring->get_seqno(ring));
1629                         wake_up_all(&ring->irq_queue);
1630                         *err = true;
1631                 }
1632                 return true;
1633         }
1634         return false;
1635 }
1636
1637 static bool kick_ring(struct intel_ring_buffer *ring)
1638 {
1639         struct drm_device *dev = ring->dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         u32 tmp = I915_READ_CTL(ring);
1642         if (tmp & RING_WAIT) {
1643                 DRM_ERROR("Kicking stuck wait on %s\n",
1644                           ring->name);
1645                 I915_WRITE_CTL(ring, tmp);
1646                 return true;
1647         }
1648         if (IS_GEN6(dev) &&
1649             (tmp & RING_WAIT_SEMAPHORE)) {
1650                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1651                           ring->name);
1652                 I915_WRITE_CTL(ring, tmp);
1653                 return true;
1654         }
1655         return false;
1656 }
1657
1658 /**
1659  * This is called when the chip hasn't reported back with completed
1660  * batchbuffers in a long time. The first time this is called we simply record
1661  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1662  * again, we assume the chip is wedged and try to fix it.
1663  */
1664 void i915_hangcheck_elapsed(unsigned long data)
1665 {
1666         struct drm_device *dev = (struct drm_device *)data;
1667         drm_i915_private_t *dev_priv = dev->dev_private;
1668         uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
1669         bool err = false;
1670
1671         if (!i915_enable_hangcheck)
1672                 return;
1673
1674         /* If all work is done then ACTHD clearly hasn't advanced. */
1675         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1676             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1677             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1678                 dev_priv->hangcheck_count = 0;
1679                 if (err)
1680                         goto repeat;
1681                 return;
1682         }
1683
1684         if (INTEL_INFO(dev)->gen < 4) {
1685                 instdone = I915_READ(INSTDONE);
1686                 instdone1 = 0;
1687         } else {
1688                 instdone = I915_READ(INSTDONE_I965);
1689                 instdone1 = I915_READ(INSTDONE1);
1690         }
1691         acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1692         acthd_bsd = HAS_BSD(dev) ?
1693                 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1694         acthd_blt = HAS_BLT(dev) ?
1695                 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
1696
1697         if (dev_priv->last_acthd == acthd &&
1698             dev_priv->last_acthd_bsd == acthd_bsd &&
1699             dev_priv->last_acthd_blt == acthd_blt &&
1700             dev_priv->last_instdone == instdone &&
1701             dev_priv->last_instdone1 == instdone1) {
1702                 if (dev_priv->hangcheck_count++ > 1) {
1703                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1704
1705                         if (!IS_GEN2(dev)) {
1706                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1707                                  * If so we can simply poke the RB_WAIT bit
1708                                  * and break the hang. This should work on
1709                                  * all but the second generation chipsets.
1710                                  */
1711
1712                                 if (kick_ring(&dev_priv->ring[RCS]))
1713                                         goto repeat;
1714
1715                                 if (HAS_BSD(dev) &&
1716                                     kick_ring(&dev_priv->ring[VCS]))
1717                                         goto repeat;
1718
1719                                 if (HAS_BLT(dev) &&
1720                                     kick_ring(&dev_priv->ring[BCS]))
1721                                         goto repeat;
1722                         }
1723
1724                         i915_handle_error(dev, true);
1725                         return;
1726                 }
1727         } else {
1728                 dev_priv->hangcheck_count = 0;
1729
1730                 dev_priv->last_acthd = acthd;
1731                 dev_priv->last_acthd_bsd = acthd_bsd;
1732                 dev_priv->last_acthd_blt = acthd_blt;
1733                 dev_priv->last_instdone = instdone;
1734                 dev_priv->last_instdone1 = instdone1;
1735         }
1736
1737 repeat:
1738         /* Reset timer case chip hangs without another request being added */
1739         mod_timer(&dev_priv->hangcheck_timer,
1740                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1741 }
1742
1743 /* drm_dma.h hooks
1744 */
1745 static void ironlake_irq_preinstall(struct drm_device *dev)
1746 {
1747         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1748
1749         atomic_set(&dev_priv->irq_received, 0);
1750
1751         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1752         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1753         if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1754                 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1755
1756         I915_WRITE(HWSTAM, 0xeffe);
1757         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1758                 /* Workaround stalls observed on Sandy Bridge GPUs by
1759                  * making the blitter command streamer generate a
1760                  * write to the Hardware Status Page for
1761                  * MI_USER_INTERRUPT.  This appears to serialize the
1762                  * previous seqno write out before the interrupt
1763                  * happens.
1764                  */
1765                 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1766                 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1767         }
1768
1769         /* XXX hotplug from PCH */
1770
1771         I915_WRITE(DEIMR, 0xffffffff);
1772         I915_WRITE(DEIER, 0x0);
1773         POSTING_READ(DEIER);
1774
1775         /* and GT */
1776         I915_WRITE(GTIMR, 0xffffffff);
1777         I915_WRITE(GTIER, 0x0);
1778         POSTING_READ(GTIER);
1779
1780         /* south display irq */
1781         I915_WRITE(SDEIMR, 0xffffffff);
1782         I915_WRITE(SDEIER, 0x0);
1783         POSTING_READ(SDEIER);
1784 }
1785
1786 /*
1787  * Enable digital hotplug on the PCH, and configure the DP short pulse
1788  * duration to 2ms (which is the minimum in the Display Port spec)
1789  *
1790  * This register is the same on all known PCH chips.
1791  */
1792
1793 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1794 {
1795         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1796         u32     hotplug;
1797
1798         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1799         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1800         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1801         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1802         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1803         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1804 }
1805
1806 static int ironlake_irq_postinstall(struct drm_device *dev)
1807 {
1808         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1809         /* enable kind of interrupts always enabled */
1810         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1811                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1812         u32 render_irqs;
1813         u32 hotplug_mask;
1814
1815         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1816         if (HAS_BSD(dev))
1817                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1818         if (HAS_BLT(dev))
1819                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1820
1821         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1822         dev_priv->irq_mask = ~display_mask;
1823
1824         /* should always can generate irq */
1825         I915_WRITE(DEIIR, I915_READ(DEIIR));
1826         I915_WRITE(DEIMR, dev_priv->irq_mask);
1827         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1828         POSTING_READ(DEIER);
1829
1830         dev_priv->gt_irq_mask = ~0;
1831
1832         I915_WRITE(GTIIR, I915_READ(GTIIR));
1833         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1834
1835         if (IS_GEN6(dev))
1836                 render_irqs =
1837                         GT_USER_INTERRUPT |
1838                         GT_GEN6_BSD_USER_INTERRUPT |
1839                         GT_BLT_USER_INTERRUPT;
1840         else
1841                 render_irqs =
1842                         GT_USER_INTERRUPT |
1843                         GT_PIPE_NOTIFY |
1844                         GT_BSD_USER_INTERRUPT;
1845         I915_WRITE(GTIER, render_irqs);
1846         POSTING_READ(GTIER);
1847
1848         if (HAS_PCH_CPT(dev)) {
1849                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1850                                 SDE_PORTB_HOTPLUG_CPT |
1851                                 SDE_PORTC_HOTPLUG_CPT |
1852                                 SDE_PORTD_HOTPLUG_CPT);
1853         } else {
1854                 hotplug_mask = (SDE_CRT_HOTPLUG |
1855                                 SDE_PORTB_HOTPLUG |
1856                                 SDE_PORTC_HOTPLUG |
1857                                 SDE_PORTD_HOTPLUG |
1858                                 SDE_AUX_MASK);
1859         }
1860
1861         dev_priv->pch_irq_mask = ~hotplug_mask;
1862
1863         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1864         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1865         I915_WRITE(SDEIER, hotplug_mask);
1866         POSTING_READ(SDEIER);
1867
1868         ironlake_enable_pch_hotplug(dev);
1869
1870         if (IS_IRONLAKE_M(dev)) {
1871                 /* Clear & enable PCU event interrupts */
1872                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1873                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1874                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1875         }
1876
1877         return 0;
1878 }
1879
1880 static int ivybridge_irq_postinstall(struct drm_device *dev)
1881 {
1882         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1883         /* enable kind of interrupts always enabled */
1884         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1885                 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1886                 DE_PLANEB_FLIP_DONE_IVB;
1887         u32 render_irqs;
1888         u32 hotplug_mask;
1889
1890         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1891         if (HAS_BSD(dev))
1892                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1893         if (HAS_BLT(dev))
1894                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1895
1896         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1897         dev_priv->irq_mask = ~display_mask;
1898
1899         /* should always can generate irq */
1900         I915_WRITE(DEIIR, I915_READ(DEIIR));
1901         I915_WRITE(DEIMR, dev_priv->irq_mask);
1902         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1903                    DE_PIPEB_VBLANK_IVB);
1904         POSTING_READ(DEIER);
1905
1906         dev_priv->gt_irq_mask = ~0;
1907
1908         I915_WRITE(GTIIR, I915_READ(GTIIR));
1909         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1910
1911         render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1912                 GT_BLT_USER_INTERRUPT;
1913         I915_WRITE(GTIER, render_irqs);
1914         POSTING_READ(GTIER);
1915
1916         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1917                         SDE_PORTB_HOTPLUG_CPT |
1918                         SDE_PORTC_HOTPLUG_CPT |
1919                         SDE_PORTD_HOTPLUG_CPT);
1920         dev_priv->pch_irq_mask = ~hotplug_mask;
1921
1922         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1923         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1924         I915_WRITE(SDEIER, hotplug_mask);
1925         POSTING_READ(SDEIER);
1926
1927         ironlake_enable_pch_hotplug(dev);
1928
1929         return 0;
1930 }
1931
1932 static void i915_driver_irq_preinstall(struct drm_device * dev)
1933 {
1934         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1935         int pipe;
1936
1937         atomic_set(&dev_priv->irq_received, 0);
1938
1939         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1940         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1941
1942         if (I915_HAS_HOTPLUG(dev)) {
1943                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1944                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1945         }
1946
1947         I915_WRITE(HWSTAM, 0xeffe);
1948         for_each_pipe(pipe)
1949                 I915_WRITE(PIPESTAT(pipe), 0);
1950         I915_WRITE(IMR, 0xffffffff);
1951         I915_WRITE(IER, 0x0);
1952         POSTING_READ(IER);
1953 }
1954
1955 /*
1956  * Must be called after intel_modeset_init or hotplug interrupts won't be
1957  * enabled correctly.
1958  */
1959 static int i915_driver_irq_postinstall(struct drm_device *dev)
1960 {
1961         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1962         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1963         u32 error_mask;
1964
1965         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1966
1967         /* Unmask the interrupts that we always want on. */
1968         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1969
1970         dev_priv->pipestat[0] = 0;
1971         dev_priv->pipestat[1] = 0;
1972
1973         if (I915_HAS_HOTPLUG(dev)) {
1974                 /* Enable in IER... */
1975                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1976                 /* and unmask in IMR */
1977                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1978         }
1979
1980         /*
1981          * Enable some error detection, note the instruction error mask
1982          * bit is reserved, so we leave it masked.
1983          */
1984         if (IS_G4X(dev)) {
1985                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1986                                GM45_ERROR_MEM_PRIV |
1987                                GM45_ERROR_CP_PRIV |
1988                                I915_ERROR_MEMORY_REFRESH);
1989         } else {
1990                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1991                                I915_ERROR_MEMORY_REFRESH);
1992         }
1993         I915_WRITE(EMR, error_mask);
1994
1995         I915_WRITE(IMR, dev_priv->irq_mask);
1996         I915_WRITE(IER, enable_mask);
1997         POSTING_READ(IER);
1998
1999         if (I915_HAS_HOTPLUG(dev)) {
2000                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2001
2002                 /* Note HDMI and DP share bits */
2003                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2004                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2005                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2006                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2007                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2008                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2009                 if (IS_G4X(dev)) {
2010                         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2011                                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2012                         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2013                                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2014                 } else if (IS_GEN4(dev)) {
2015                         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2016                                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2017                         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2018                                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2019                 } else {
2020                         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2021                                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2022                         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2023                                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2024                 }
2025                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2026                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2027
2028                         /* Programming the CRT detection parameters tends
2029                            to generate a spurious hotplug event about three
2030                            seconds later.  So just do it once.
2031                         */
2032                         if (IS_G4X(dev))
2033                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2034                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2035                 }
2036
2037                 /* Ignore TV since it's buggy */
2038
2039                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2040         }
2041
2042         intel_opregion_enable_asle(dev);
2043
2044         return 0;
2045 }
2046
2047 static void ironlake_irq_uninstall(struct drm_device *dev)
2048 {
2049         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2050
2051         if (!dev_priv)
2052                 return;
2053
2054         dev_priv->vblank_pipe = 0;
2055
2056         I915_WRITE(HWSTAM, 0xffffffff);
2057
2058         I915_WRITE(DEIMR, 0xffffffff);
2059         I915_WRITE(DEIER, 0x0);
2060         I915_WRITE(DEIIR, I915_READ(DEIIR));
2061
2062         I915_WRITE(GTIMR, 0xffffffff);
2063         I915_WRITE(GTIER, 0x0);
2064         I915_WRITE(GTIIR, I915_READ(GTIIR));
2065
2066         I915_WRITE(SDEIMR, 0xffffffff);
2067         I915_WRITE(SDEIER, 0x0);
2068         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2069 }
2070
2071 static void i915_driver_irq_uninstall(struct drm_device * dev)
2072 {
2073         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2074         int pipe;
2075
2076         if (!dev_priv)
2077                 return;
2078
2079         dev_priv->vblank_pipe = 0;
2080
2081         if (I915_HAS_HOTPLUG(dev)) {
2082                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2083                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2084         }
2085
2086         I915_WRITE(HWSTAM, 0xffffffff);
2087         for_each_pipe(pipe)
2088                 I915_WRITE(PIPESTAT(pipe), 0);
2089         I915_WRITE(IMR, 0xffffffff);
2090         I915_WRITE(IER, 0x0);
2091
2092         for_each_pipe(pipe)
2093                 I915_WRITE(PIPESTAT(pipe),
2094                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2095         I915_WRITE(IIR, I915_READ(IIR));
2096 }
2097
2098 void intel_irq_init(struct drm_device *dev)
2099 {
2100         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2101         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2102         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2103                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2104                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2105         }
2106
2107         if (drm_core_check_feature(dev, DRIVER_MODESET))
2108                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2109         else
2110                 dev->driver->get_vblank_timestamp = NULL;
2111         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2112
2113         if (IS_IVYBRIDGE(dev)) {
2114                 /* Share pre & uninstall handlers with ILK/SNB */
2115                 dev->driver->irq_handler = ivybridge_irq_handler;
2116                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2117                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2118                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2119                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2120                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2121         } else if (HAS_PCH_SPLIT(dev)) {
2122                 dev->driver->irq_handler = ironlake_irq_handler;
2123                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2124                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2125                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2126                 dev->driver->enable_vblank = ironlake_enable_vblank;
2127                 dev->driver->disable_vblank = ironlake_disable_vblank;
2128         } else {
2129                 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2130                 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2131                 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2132                 dev->driver->irq_handler = i915_driver_irq_handler;
2133                 dev->driver->enable_vblank = i915_enable_vblank;
2134                 dev->driver->disable_vblank = i915_disable_vblank;
2135         }
2136 }