drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 static inline void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 static inline void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      I915_LEGACY_BLC_EVENT_ENABLE);
 175 }
 176
 177 /**
 178  * i915_pipe_enabled - check if a pipe is enabled
 179  * @dev: DRM device
 180  * @pipe: pipe to check
 181  *
 182  * Reading certain registers when the pipe is disabled can hang the chip.
 183  * Use this routine to make sure the PLL is running and the pipe is active
 184  * before reading such registers if unsure.
 185  */
 186 static int
 187 i915_pipe_enabled(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 191
 192         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 193                 return 1;
 194
 195         return 0;
 196 }
 197
 198 /* Called from drm generic code, passed a 'crtc', which
 199  * we use as a pipe index
 200  */
 201 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204         unsigned long high_frame;
 205         unsigned long low_frame;
 206         u32 high1, high2, low, count;
 207
 208         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 209         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 210
 211         if (!i915_pipe_enabled(dev, pipe)) {
 212                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 213                                 "pipe %d\n", pipe);
 214                 return 0;
 215         }
 216
 217         /*
 218          * High & low register fields aren't synchronized, so make sure
 219          * we get a low value that's stable across two reads of the high
 220          * register.
 221          */
 222         do {
 223                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 224                          PIPE_FRAME_HIGH_SHIFT);
 225                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 226                         PIPE_FRAME_LOW_SHIFT);
 227                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229         } while (high1 != high2);
 230
 231         count = (high1 << 8) | low;
 232
 233         return count;
 234 }
 235
 236 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 237 {
 238         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 239         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 240
 241         if (!i915_pipe_enabled(dev, pipe)) {
 242                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 243                                         "pipe %d\n", pipe);
 244                 return 0;
 245         }
 246
 247         return I915_READ(reg);
 248 }
 249
 250 /*
 251  * Handle hotplug events outside the interrupt handler proper.
 252  */
 253 static void i915_hotplug_work_func(struct work_struct *work)
 254 {
 255         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 256                                                     hotplug_work);
 257         struct drm_device *dev = dev_priv->dev;
 258         struct drm_mode_config *mode_config = &dev->mode_config;
 259         struct drm_connector *connector;
 260
 261         if (mode_config->num_connector) {
 262                 list_for_each_entry(connector, &mode_config->connector_list, head) {
 263                         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 264
 265                         if (intel_encoder->hot_plug)
 266                                 (*intel_encoder->hot_plug) (intel_encoder);
 267                 }
 268         }
 269         /* Just fire off a uevent and let userspace tell us what to do */
 270         drm_sysfs_hotplug_event(dev);
 271 }
 272
 273 static void i915_handle_rps_change(struct drm_device *dev)
 274 {
 275         drm_i915_private_t *dev_priv = dev->dev_private;
 276         u32 busy_up, busy_down, max_avg, min_avg;
 277         u16 rgvswctl;
 278         u8 new_delay = dev_priv->cur_delay;
 279
 280         I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
 281         busy_up = I915_READ(RCPREVBSYTUPAVG);
 282         busy_down = I915_READ(RCPREVBSYTDNAVG);
 283         max_avg = I915_READ(RCBMAXAVG);
 284         min_avg = I915_READ(RCBMINAVG);
 285
 286         /* Handle RCS change request from hw */
 287         if (busy_up > max_avg) {
 288                 if (dev_priv->cur_delay != dev_priv->max_delay)
 289                         new_delay = dev_priv->cur_delay - 1;
 290                 if (new_delay < dev_priv->max_delay)
 291                         new_delay = dev_priv->max_delay;
 292         } else if (busy_down < min_avg) {
 293                 if (dev_priv->cur_delay != dev_priv->min_delay)
 294                         new_delay = dev_priv->cur_delay + 1;
 295                 if (new_delay > dev_priv->min_delay)
 296                         new_delay = dev_priv->min_delay;
 297         }
 298
 299         DRM_DEBUG("rps change requested: %d -> %d\n",
 300                   dev_priv->cur_delay, new_delay);
 301
 302         rgvswctl = I915_READ(MEMSWCTL);
 303         if (rgvswctl & MEMCTL_CMD_STS) {
 304                 DRM_ERROR("gpu busy, RCS change rejected\n");
 305                 return; /* still busy with another command */
 306         }
 307
 308         /* Program the new state */
 309         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
 310                 (new_delay << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
 311         I915_WRITE(MEMSWCTL, rgvswctl);
 312         POSTING_READ(MEMSWCTL);
 313
 314         rgvswctl |= MEMCTL_CMD_STS;
 315         I915_WRITE(MEMSWCTL, rgvswctl);
 316
 317         dev_priv->cur_delay = new_delay;
 318
 319         DRM_DEBUG("rps changed\n");
 320
 321         return;
 322 }
 323
 324 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 325 {
 326         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 327         int ret = IRQ_NONE;
 328         u32 de_iir, gt_iir, de_ier, pch_iir;
 329         struct drm_i915_master_private *master_priv;
 330
 331         /* disable master interrupt before clearing iir  */
 332         de_ier = I915_READ(DEIER);
 333         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 334         (void)I915_READ(DEIER);
 335
 336         de_iir = I915_READ(DEIIR);
 337         gt_iir = I915_READ(GTIIR);
 338         pch_iir = I915_READ(SDEIIR);
 339
 340         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 341                 goto done;
 342
 343         ret = IRQ_HANDLED;
 344
 345         if (dev->primary->master) {
 346                 master_priv = dev->primary->master->driver_priv;
 347                 if (master_priv->sarea_priv)
 348                         master_priv->sarea_priv->last_dispatch =
 349                                 READ_BREADCRUMB(dev_priv);
 350         }
 351
 352         if (gt_iir & GT_USER_INTERRUPT) {
 353                 u32 seqno = i915_get_gem_seqno(dev);
 354                 dev_priv->mm.irq_gem_seqno = seqno;
 355                 trace_i915_gem_request_complete(dev, seqno);
 356                 DRM_WAKEUP(&dev_priv->irq_queue);
 357                 dev_priv->hangcheck_count = 0;
 358                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 359         }
 360
 361         if (de_iir & DE_GSE)
 362                 ironlake_opregion_gse_intr(dev);
 363
 364         if (de_iir & DE_PLANEA_FLIP_DONE) {
 365                 intel_prepare_page_flip(dev, 0);
 366                 intel_finish_page_flip(dev, 0);
 367         }
 368
 369         if (de_iir & DE_PLANEB_FLIP_DONE) {
 370                 intel_prepare_page_flip(dev, 1);
 371                 intel_finish_page_flip(dev, 1);
 372         }
 373
 374         if (de_iir & DE_PIPEA_VBLANK)
 375                 drm_handle_vblank(dev, 0);
 376
 377         if (de_iir & DE_PIPEB_VBLANK)
 378                 drm_handle_vblank(dev, 1);
 379
 380         /* check event from PCH */
 381         if ((de_iir & DE_PCH_EVENT) &&
 382             (pch_iir & SDE_HOTPLUG_MASK)) {
 383                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 384         }
 385
 386         if (de_iir & DE_PCU_EVENT) {
 387                 I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS));
 388                 i915_handle_rps_change(dev);
 389         }
 390
 391         /* should clear PCH hotplug event before clear CPU irq */
 392         I915_WRITE(SDEIIR, pch_iir);
 393         I915_WRITE(GTIIR, gt_iir);
 394         I915_WRITE(DEIIR, de_iir);
 395
 396 done:
 397         I915_WRITE(DEIER, de_ier);
 398         (void)I915_READ(DEIER);
 399
 400         return ret;
 401 }
 402
 403 /**
 404  * i915_error_work_func - do process context error handling work
 405  * @work: work struct
 406  *
 407  * Fire an error uevent so userspace can see that a hang or error
 408  * was detected.
 409  */
 410 static void i915_error_work_func(struct work_struct *work)
 411 {
 412         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 413                                                     error_work);
 414         struct drm_device *dev = dev_priv->dev;
 415         char *error_event[] = { "ERROR=1", NULL };
 416         char *reset_event[] = { "RESET=1", NULL };
 417         char *reset_done_event[] = { "ERROR=0", NULL };
 418
 419         DRM_DEBUG_DRIVER("generating error event\n");
 420         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 421
 422         if (atomic_read(&dev_priv->mm.wedged)) {
 423                 if (IS_I965G(dev)) {
 424                         DRM_DEBUG_DRIVER("resetting chip\n");
 425                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 426                         if (!i965_reset(dev, GDRST_RENDER)) {
 427                                 atomic_set(&dev_priv->mm.wedged, 0);
 428                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 429                         }
 430                 } else {
 431                         DRM_DEBUG_DRIVER("reboot required\n");
 432                 }
 433         }
 434 }
 435
 436 static struct drm_i915_error_object *
 437 i915_error_object_create(struct drm_device *dev,
 438                          struct drm_gem_object *src)
 439 {
 440         struct drm_i915_error_object *dst;
 441         struct drm_i915_gem_object *src_priv;
 442         int page, page_count;
 443
 444         if (src == NULL)
 445                 return NULL;
 446
 447         src_priv = to_intel_bo(src);
 448         if (src_priv->pages == NULL)
 449                 return NULL;
 450
 451         page_count = src->size / PAGE_SIZE;
 452
 453         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 454         if (dst == NULL)
 455                 return NULL;
 456
 457         for (page = 0; page < page_count; page++) {
 458                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 459                 if (d == NULL)
 460                         goto unwind;
 461                 s = kmap_atomic(src_priv->pages[page], KM_USER0);
 462                 memcpy(d, s, PAGE_SIZE);
 463                 kunmap_atomic(s, KM_USER0);
 464                 dst->pages[page] = d;
 465         }
 466         dst->page_count = page_count;
 467         dst->gtt_offset = src_priv->gtt_offset;
 468
 469         return dst;
 470
 471 unwind:
 472         while (page--)
 473                 kfree(dst->pages[page]);
 474         kfree(dst);
 475         return NULL;
 476 }
 477
 478 static void
 479 i915_error_object_free(struct drm_i915_error_object *obj)
 480 {
 481         int page;
 482
 483         if (obj == NULL)
 484                 return;
 485
 486         for (page = 0; page < obj->page_count; page++)
 487                 kfree(obj->pages[page]);
 488
 489         kfree(obj);
 490 }
 491
 492 static void
 493 i915_error_state_free(struct drm_device *dev,
 494                       struct drm_i915_error_state *error)
 495 {
 496         i915_error_object_free(error->batchbuffer[0]);
 497         i915_error_object_free(error->batchbuffer[1]);
 498         i915_error_object_free(error->ringbuffer);
 499         kfree(error->active_bo);
 500         kfree(error);
 501 }
 502
 503 static u32
 504 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 505 {
 506         u32 cmd;
 507
 508         if (IS_I830(dev) || IS_845G(dev))
 509                 cmd = MI_BATCH_BUFFER;
 510         else if (IS_I965G(dev))
 511                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 512                        MI_BATCH_NON_SECURE_I965);
 513         else
 514                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 515
 516         return ring[0] == cmd ? ring[1] : 0;
 517 }
 518
 519 static u32
 520 i915_ringbuffer_last_batch(struct drm_device *dev)
 521 {
 522         struct drm_i915_private *dev_priv = dev->dev_private;
 523         u32 head, bbaddr;
 524         u32 *ring;
 525
 526         /* Locate the current position in the ringbuffer and walk back
 527          * to find the most recently dispatched batch buffer.
 528          */
 529         bbaddr = 0;
 530         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 531         ring = (u32 *)(dev_priv->ring.virtual_start + head);
 532
 533         while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 534                 bbaddr = i915_get_bbaddr(dev, ring);
 535                 if (bbaddr)
 536                         break;
 537         }
 538
 539         if (bbaddr == 0) {
 540                 ring = (u32 *)(dev_priv->ring.virtual_start + dev_priv->ring.Size);
 541                 while (--ring >= (u32 *)dev_priv->ring.virtual_start) {
 542                         bbaddr = i915_get_bbaddr(dev, ring);
 543                         if (bbaddr)
 544                                 break;
 545                 }
 546         }
 547
 548         return bbaddr;
 549 }
 550
 551 /**
 552  * i915_capture_error_state - capture an error record for later analysis
 553  * @dev: drm device
 554  *
 555  * Should be called when an error is detected (either a hang or an error
 556  * interrupt) to capture error state from the time of the error.  Fills
 557  * out a structure which becomes available in debugfs for user level tools
 558  * to pick up.
 559  */
 560 static void i915_capture_error_state(struct drm_device *dev)
 561 {
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         struct drm_i915_gem_object *obj_priv;
 564         struct drm_i915_error_state *error;
 565         struct drm_gem_object *batchbuffer[2];
 566         unsigned long flags;
 567         u32 bbaddr;
 568         int count;
 569
 570         spin_lock_irqsave(&dev_priv->error_lock, flags);
 571         error = dev_priv->first_error;
 572         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 573         if (error)
 574                 return;
 575
 576         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 577         if (!error) {
 578                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 579                 return;
 580         }
 581
 582         error->seqno = i915_get_gem_seqno(dev);
 583         error->eir = I915_READ(EIR);
 584         error->pgtbl_er = I915_READ(PGTBL_ER);
 585         error->pipeastat = I915_READ(PIPEASTAT);
 586         error->pipebstat = I915_READ(PIPEBSTAT);
 587         error->instpm = I915_READ(INSTPM);
 588         if (!IS_I965G(dev)) {
 589                 error->ipeir = I915_READ(IPEIR);
 590                 error->ipehr = I915_READ(IPEHR);
 591                 error->instdone = I915_READ(INSTDONE);
 592                 error->acthd = I915_READ(ACTHD);
 593                 error->bbaddr = 0;
 594         } else {
 595                 error->ipeir = I915_READ(IPEIR_I965);
 596                 error->ipehr = I915_READ(IPEHR_I965);
 597                 error->instdone = I915_READ(INSTDONE_I965);
 598                 error->instps = I915_READ(INSTPS);
 599                 error->instdone1 = I915_READ(INSTDONE1);
 600                 error->acthd = I915_READ(ACTHD_I965);
 601                 error->bbaddr = I915_READ64(BB_ADDR);
 602         }
 603
 604         bbaddr = i915_ringbuffer_last_batch(dev);
 605
 606         /* Grab the current batchbuffer, most likely to have crashed. */
 607         batchbuffer[0] = NULL;
 608         batchbuffer[1] = NULL;
 609         count = 0;
 610         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 611                 struct drm_gem_object *obj = obj_priv->obj;
 612
 613                 if (batchbuffer[0] == NULL &&
 614                     bbaddr >= obj_priv->gtt_offset &&
 615                     bbaddr < obj_priv->gtt_offset + obj->size)
 616                         batchbuffer[0] = obj;
 617
 618                 if (batchbuffer[1] == NULL &&
 619                     error->acthd >= obj_priv->gtt_offset &&
 620                     error->acthd < obj_priv->gtt_offset + obj->size &&
 621                     batchbuffer[0] != obj)
 622                         batchbuffer[1] = obj;
 623
 624                 count++;
 625         }
 626
 627         /* We need to copy these to an anonymous buffer as the simplest
 628          * method to avoid being overwritten by userpace.
 629          */
 630         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 631         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 632
 633         /* Record the ringbuffer */
 634         error->ringbuffer = i915_error_object_create(dev, dev_priv->ring.ring_obj);
 635
 636         /* Record buffers on the active list. */
 637         error->active_bo = NULL;
 638         error->active_bo_count = 0;
 639
 640         if (count)
 641                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 642                                            GFP_ATOMIC);
 643
 644         if (error->active_bo) {
 645                 int i = 0;
 646                 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
 647                         struct drm_gem_object *obj = obj_priv->obj;
 648
 649                         error->active_bo[i].size = obj->size;
 650                         error->active_bo[i].name = obj->name;
 651                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 652                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 653                         error->active_bo[i].read_domains = obj->read_domains;
 654                         error->active_bo[i].write_domain = obj->write_domain;
 655                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 656                         error->active_bo[i].pinned = 0;
 657                         if (obj_priv->pin_count > 0)
 658                                 error->active_bo[i].pinned = 1;
 659                         if (obj_priv->user_pin_count > 0)
 660                                 error->active_bo[i].pinned = -1;
 661                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 662                         error->active_bo[i].dirty = obj_priv->dirty;
 663                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 664
 665                         if (++i == count)
 666                                 break;
 667                 }
 668                 error->active_bo_count = i;
 669         }
 670
 671         do_gettimeofday(&error->time);
 672
 673         spin_lock_irqsave(&dev_priv->error_lock, flags);
 674         if (dev_priv->first_error == NULL) {
 675                 dev_priv->first_error = error;
 676                 error = NULL;
 677         }
 678         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 679
 680         if (error)
 681                 i915_error_state_free(dev, error);
 682 }
 683
 684 void i915_destroy_error_state(struct drm_device *dev)
 685 {
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct drm_i915_error_state *error;
 688
 689         spin_lock(&dev_priv->error_lock);
 690         error = dev_priv->first_error;
 691         dev_priv->first_error = NULL;
 692         spin_unlock(&dev_priv->error_lock);
 693
 694         if (error)
 695                 i915_error_state_free(dev, error);
 696 }
 697
 698 /**
 699  * i915_handle_error - handle an error interrupt
 700  * @dev: drm device
 701  *
 702  * Do some basic checking of regsiter state at error interrupt time and
 703  * dump it to the syslog.  Also call i915_capture_error_state() to make
 704  * sure we get a record and make it available in debugfs.  Fire a uevent
 705  * so userspace knows something bad happened (should trigger collection
 706  * of a ring dump etc.).
 707  */
 708 static void i915_handle_error(struct drm_device *dev, bool wedged)
 709 {
 710         struct drm_i915_private *dev_priv = dev->dev_private;
 711         u32 eir = I915_READ(EIR);
 712         u32 pipea_stats = I915_READ(PIPEASTAT);
 713         u32 pipeb_stats = I915_READ(PIPEBSTAT);
 714
 715         i915_capture_error_state(dev);
 716
 717         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 718                eir);
 719
 720         if (IS_G4X(dev)) {
 721                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 722                         u32 ipeir = I915_READ(IPEIR_I965);
 723
 724                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 725                                I915_READ(IPEIR_I965));
 726                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 727                                I915_READ(IPEHR_I965));
 728                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 729                                I915_READ(INSTDONE_I965));
 730                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 731                                I915_READ(INSTPS));
 732                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 733                                I915_READ(INSTDONE1));
 734                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 735                                I915_READ(ACTHD_I965));
 736                         I915_WRITE(IPEIR_I965, ipeir);
 737                         (void)I915_READ(IPEIR_I965);
 738                 }
 739                 if (eir & GM45_ERROR_PAGE_TABLE) {
 740                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 741                         printk(KERN_ERR "page table error\n");
 742                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 743                                pgtbl_err);
 744                         I915_WRITE(PGTBL_ER, pgtbl_err);
 745                         (void)I915_READ(PGTBL_ER);
 746                 }
 747         }
 748
 749         if (IS_I9XX(dev)) {
 750                 if (eir & I915_ERROR_PAGE_TABLE) {
 751                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 752                         printk(KERN_ERR "page table error\n");
 753                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 754                                pgtbl_err);
 755                         I915_WRITE(PGTBL_ER, pgtbl_err);
 756                         (void)I915_READ(PGTBL_ER);
 757                 }
 758         }
 759
 760         if (eir & I915_ERROR_MEMORY_REFRESH) {
 761                 printk(KERN_ERR "memory refresh error\n");
 762                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 763                        pipea_stats);
 764                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 765                        pipeb_stats);
 766                 /* pipestat has already been acked */
 767         }
 768         if (eir & I915_ERROR_INSTRUCTION) {
 769                 printk(KERN_ERR "instruction error\n");
 770                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 771                        I915_READ(INSTPM));
 772                 if (!IS_I965G(dev)) {
 773                         u32 ipeir = I915_READ(IPEIR);
 774
 775                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 776                                I915_READ(IPEIR));
 777                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 778                                I915_READ(IPEHR));
 779                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 780                                I915_READ(INSTDONE));
 781                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 782                                I915_READ(ACTHD));
 783                         I915_WRITE(IPEIR, ipeir);
 784                         (void)I915_READ(IPEIR);
 785                 } else {
 786                         u32 ipeir = I915_READ(IPEIR_I965);
 787
 788                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 789                                I915_READ(IPEIR_I965));
 790                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 791                                I915_READ(IPEHR_I965));
 792                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 793                                I915_READ(INSTDONE_I965));
 794                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 795                                I915_READ(INSTPS));
 796                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 797                                I915_READ(INSTDONE1));
 798                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 799                                I915_READ(ACTHD_I965));
 800                         I915_WRITE(IPEIR_I965, ipeir);
 801                         (void)I915_READ(IPEIR_I965);
 802                 }
 803         }
 804
 805         I915_WRITE(EIR, eir);
 806         (void)I915_READ(EIR);
 807         eir = I915_READ(EIR);
 808         if (eir) {
 809                 /*
 810                  * some errors might have become stuck,
 811                  * mask them.
 812                  */
 813                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 814                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 815                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 816         }
 817
 818         if (wedged) {
 819                 atomic_set(&dev_priv->mm.wedged, 1);
 820
 821                 /*
 822                  * Wakeup waiting processes so they don't hang
 823                  */
 824                 DRM_WAKEUP(&dev_priv->irq_queue);
 825         }
 826
 827         queue_work(dev_priv->wq, &dev_priv->error_work);
 828 }
 829
 830 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 831 {
 832         struct drm_device *dev = (struct drm_device *) arg;
 833         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 834         struct drm_i915_master_private *master_priv;
 835         u32 iir, new_iir;
 836         u32 pipea_stats, pipeb_stats;
 837         u32 vblank_status;
 838         u32 vblank_enable;
 839         int vblank = 0;
 840         unsigned long irqflags;
 841         int irq_received;
 842         int ret = IRQ_NONE;
 843
 844         atomic_inc(&dev_priv->irq_received);
 845
 846         if (HAS_PCH_SPLIT(dev))
 847                 return ironlake_irq_handler(dev);
 848
 849         iir = I915_READ(IIR);
 850
 851         if (IS_I965G(dev)) {
 852                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 853                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 854         } else {
 855                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 856                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 857         }
 858
 859         for (;;) {
 860                 irq_received = iir != 0;
 861
 862                 /* Can't rely on pipestat interrupt bit in iir as it might
 863                  * have been cleared after the pipestat interrupt was received.
 864                  * It doesn't set the bit in iir again, but it still produces
 865                  * interrupts (for non-MSI).
 866                  */
 867                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 868                 pipea_stats = I915_READ(PIPEASTAT);
 869                 pipeb_stats = I915_READ(PIPEBSTAT);
 870
 871                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 872                         i915_handle_error(dev, false);
 873
 874                 /*
 875                  * Clear the PIPE(A|B)STAT regs before the IIR
 876                  */
 877                 if (pipea_stats & 0x8000ffff) {
 878                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 879                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 880                         I915_WRITE(PIPEASTAT, pipea_stats);
 881                         irq_received = 1;
 882                 }
 883
 884                 if (pipeb_stats & 0x8000ffff) {
 885                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 886                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 887                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 888                         irq_received = 1;
 889                 }
 890                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 891
 892                 if (!irq_received)
 893                         break;
 894
 895                 ret = IRQ_HANDLED;
 896
 897                 /* Consume port.  Then clear IIR or we'll miss events */
 898                 if ((I915_HAS_HOTPLUG(dev)) &&
 899                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 900                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 901
 902                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 903                                   hotplug_status);
 904                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 905                                 queue_work(dev_priv->wq,
 906                                            &dev_priv->hotplug_work);
 907
 908                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 909                         I915_READ(PORT_HOTPLUG_STAT);
 910                 }
 911
 912                 I915_WRITE(IIR, iir);
 913                 new_iir = I915_READ(IIR); /* Flush posted writes */
 914
 915                 if (dev->primary->master) {
 916                         master_priv = dev->primary->master->driver_priv;
 917                         if (master_priv->sarea_priv)
 918                                 master_priv->sarea_priv->last_dispatch =
 919                                         READ_BREADCRUMB(dev_priv);
 920                 }
 921
 922                 if (iir & I915_USER_INTERRUPT) {
 923                         u32 seqno = i915_get_gem_seqno(dev);
 924                         dev_priv->mm.irq_gem_seqno = seqno;
 925                         trace_i915_gem_request_complete(dev, seqno);
 926                         DRM_WAKEUP(&dev_priv->irq_queue);
 927                         dev_priv->hangcheck_count = 0;
 928                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 929                 }
 930
 931                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
 932                         intel_prepare_page_flip(dev, 0);
 933
 934                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
 935                         intel_prepare_page_flip(dev, 1);
 936
 937                 if (pipea_stats & vblank_status) {
 938                         vblank++;
 939                         drm_handle_vblank(dev, 0);
 940                         intel_finish_page_flip(dev, 0);
 941                 }
 942
 943                 if (pipeb_stats & vblank_status) {
 944                         vblank++;
 945                         drm_handle_vblank(dev, 1);
 946                         intel_finish_page_flip(dev, 1);
 947                 }
 948
 949                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 950                     (iir & I915_ASLE_INTERRUPT))
 951                         opregion_asle_intr(dev);
 952
 953                 /* With MSI, interrupts are only generated when iir
 954                  * transitions from zero to nonzero.  If another bit got
 955                  * set while we were handling the existing iir bits, then
 956                  * we would never get another interrupt.
 957                  *
 958                  * This is fine on non-MSI as well, as if we hit this path
 959                  * we avoid exiting the interrupt handler only to generate
 960                  * another one.
 961                  *
 962                  * Note that for MSI this could cause a stray interrupt report
 963                  * if an interrupt landed in the time between writing IIR and
 964                  * the posting read.  This should be rare enough to never
 965                  * trigger the 99% of 100,000 interrupts test for disabling
 966                  * stray interrupts.
 967                  */
 968                 iir = new_iir;
 969         }
 970
 971         return ret;
 972 }
 973
 974 static int i915_emit_irq(struct drm_device * dev)
 975 {
 976         drm_i915_private_t *dev_priv = dev->dev_private;
 977         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 978         RING_LOCALS;
 979
 980         i915_kernel_lost_context(dev);
 981
 982         DRM_DEBUG_DRIVER("\n");
 983
 984         dev_priv->counter++;
 985         if (dev_priv->counter > 0x7FFFFFFFUL)
 986                 dev_priv->counter = 1;
 987         if (master_priv->sarea_priv)
 988                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 989
 990         BEGIN_LP_RING(4);
 991         OUT_RING(MI_STORE_DWORD_INDEX);
 992         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 993         OUT_RING(dev_priv->counter);
 994         OUT_RING(MI_USER_INTERRUPT);
 995         ADVANCE_LP_RING();
 996
 997         return dev_priv->counter;
 998 }
 999
1000 void i915_user_irq_get(struct drm_device *dev)
1001 {
1002         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1003         unsigned long irqflags;
1004
1005         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1006         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
1007                 if (HAS_PCH_SPLIT(dev))
1008                         ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
1009                 else
1010                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1011         }
1012         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1013 }
1014
1015 void i915_user_irq_put(struct drm_device *dev)
1016 {
1017         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1018         unsigned long irqflags;
1019
1020         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1021         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
1022         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
1023                 if (HAS_PCH_SPLIT(dev))
1024                         ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
1025                 else
1026                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1027         }
1028         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1029 }
1030
1031 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1032 {
1033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1034
1035         if (dev_priv->trace_irq_seqno == 0)
1036                 i915_user_irq_get(dev);
1037
1038         dev_priv->trace_irq_seqno = seqno;
1039 }
1040
1041 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1042 {
1043         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1044         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1045         int ret = 0;
1046
1047         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1048                   READ_BREADCRUMB(dev_priv));
1049
1050         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1051                 if (master_priv->sarea_priv)
1052                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1053                 return 0;
1054         }
1055
1056         if (master_priv->sarea_priv)
1057                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1058
1059         i915_user_irq_get(dev);
1060         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
1061                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1062         i915_user_irq_put(dev);
1063
1064         if (ret == -EBUSY) {
1065                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1066                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1067         }
1068
1069         return ret;
1070 }
1071
1072 /* Needs the lock as it touches the ring.
1073  */
1074 int i915_irq_emit(struct drm_device *dev, void *data,
1075                          struct drm_file *file_priv)
1076 {
1077         drm_i915_private_t *dev_priv = dev->dev_private;
1078         drm_i915_irq_emit_t *emit = data;
1079         int result;
1080
1081         if (!dev_priv || !dev_priv->ring.virtual_start) {
1082                 DRM_ERROR("called with no initialization\n");
1083                 return -EINVAL;
1084         }
1085
1086         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1087
1088         mutex_lock(&dev->struct_mutex);
1089         result = i915_emit_irq(dev);
1090         mutex_unlock(&dev->struct_mutex);
1091
1092         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1093                 DRM_ERROR("copy_to_user\n");
1094                 return -EFAULT;
1095         }
1096
1097         return 0;
1098 }
1099
1100 /* Doesn't need the hardware lock.
1101  */
1102 int i915_irq_wait(struct drm_device *dev, void *data,
1103                          struct drm_file *file_priv)
1104 {
1105         drm_i915_private_t *dev_priv = dev->dev_private;
1106         drm_i915_irq_wait_t *irqwait = data;
1107
1108         if (!dev_priv) {
1109                 DRM_ERROR("called with no initialization\n");
1110                 return -EINVAL;
1111         }
1112
1113         return i915_wait_irq(dev, irqwait->irq_seq);
1114 }
1115
1116 /* Called from drm generic code, passed 'crtc' which
1117  * we use as a pipe index
1118  */
1119 int i915_enable_vblank(struct drm_device *dev, int pipe)
1120 {
1121         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1122         unsigned long irqflags;
1123         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1124         u32 pipeconf;
1125
1126         pipeconf = I915_READ(pipeconf_reg);
1127         if (!(pipeconf & PIPEACONF_ENABLE))
1128                 return -EINVAL;
1129
1130         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1131         if (HAS_PCH_SPLIT(dev))
1132                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1133                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1134         else if (IS_I965G(dev))
1135                 i915_enable_pipestat(dev_priv, pipe,
1136                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1137         else
1138                 i915_enable_pipestat(dev_priv, pipe,
1139                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1140         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1141         return 0;
1142 }
1143
1144 /* Called from drm generic code, passed 'crtc' which
1145  * we use as a pipe index
1146  */
1147 void i915_disable_vblank(struct drm_device *dev, int pipe)
1148 {
1149         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1150         unsigned long irqflags;
1151
1152         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1153         if (HAS_PCH_SPLIT(dev))
1154                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1155                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1156         else
1157                 i915_disable_pipestat(dev_priv, pipe,
1158                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1159                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1160         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1161 }
1162
1163 void i915_enable_interrupt (struct drm_device *dev)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166
1167         if (!HAS_PCH_SPLIT(dev))
1168                 opregion_enable_asle(dev);
1169         dev_priv->irq_enabled = 1;
1170 }
1171
1172
1173 /* Set the vblank monitor pipe
1174  */
1175 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1176                          struct drm_file *file_priv)
1177 {
1178         drm_i915_private_t *dev_priv = dev->dev_private;
1179
1180         if (!dev_priv) {
1181                 DRM_ERROR("called with no initialization\n");
1182                 return -EINVAL;
1183         }
1184
1185         return 0;
1186 }
1187
1188 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1189                          struct drm_file *file_priv)
1190 {
1191         drm_i915_private_t *dev_priv = dev->dev_private;
1192         drm_i915_vblank_pipe_t *pipe = data;
1193
1194         if (!dev_priv) {
1195                 DRM_ERROR("called with no initialization\n");
1196                 return -EINVAL;
1197         }
1198
1199         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1200
1201         return 0;
1202 }
1203
1204 /**
1205  * Schedule buffer swap at given vertical blank.
1206  */
1207 int i915_vblank_swap(struct drm_device *dev, void *data,
1208                      struct drm_file *file_priv)
1209 {
1210         /* The delayed swap mechanism was fundamentally racy, and has been
1211          * removed.  The model was that the client requested a delayed flip/swap
1212          * from the kernel, then waited for vblank before continuing to perform
1213          * rendering.  The problem was that the kernel might wake the client
1214          * up before it dispatched the vblank swap (since the lock has to be
1215          * held while touching the ringbuffer), in which case the client would
1216          * clear and start the next frame before the swap occurred, and
1217          * flicker would occur in addition to likely missing the vblank.
1218          *
1219          * In the absence of this ioctl, userland falls back to a correct path
1220          * of waiting for a vblank, then dispatching the swap on its own.
1221          * Context switching to userland and back is plenty fast enough for
1222          * meeting the requirements of vblank swapping.
1223          */
1224         return -EINVAL;
1225 }
1226
1227 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
1228         drm_i915_private_t *dev_priv = dev->dev_private;
1229         return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
1230 }
1231
1232 /**
1233  * This is called when the chip hasn't reported back with completed
1234  * batchbuffers in a long time. The first time this is called we simply record
1235  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1236  * again, we assume the chip is wedged and try to fix it.
1237  */
1238 void i915_hangcheck_elapsed(unsigned long data)
1239 {
1240         struct drm_device *dev = (struct drm_device *)data;
1241         drm_i915_private_t *dev_priv = dev->dev_private;
1242         uint32_t acthd;
1243
1244         /* No reset support on this chip yet. */
1245         if (IS_GEN6(dev))
1246                 return;
1247
1248         if (!IS_I965G(dev))
1249                 acthd = I915_READ(ACTHD);
1250         else
1251                 acthd = I915_READ(ACTHD_I965);
1252
1253         /* If all work is done then ACTHD clearly hasn't advanced. */
1254         if (list_empty(&dev_priv->mm.request_list) ||
1255                        i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
1256                 dev_priv->hangcheck_count = 0;
1257                 return;
1258         }
1259
1260         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1261                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1262                 i915_handle_error(dev, true);
1263                 return;
1264         }
1265
1266         /* Reset timer case chip hangs without another request being added */
1267         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1268
1269         if (acthd != dev_priv->last_acthd)
1270                 dev_priv->hangcheck_count = 0;
1271         else
1272                 dev_priv->hangcheck_count++;
1273
1274         dev_priv->last_acthd = acthd;
1275 }
1276
1277 /* drm_dma.h hooks
1278 */
1279 static void ironlake_irq_preinstall(struct drm_device *dev)
1280 {
1281         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1282
1283         I915_WRITE(HWSTAM, 0xeffe);
1284
1285         /* XXX hotplug from PCH */
1286
1287         I915_WRITE(DEIMR, 0xffffffff);
1288         I915_WRITE(DEIER, 0x0);
1289         (void) I915_READ(DEIER);
1290
1291         /* and GT */
1292         I915_WRITE(GTIMR, 0xffffffff);
1293         I915_WRITE(GTIER, 0x0);
1294         (void) I915_READ(GTIER);
1295
1296         /* south display irq */
1297         I915_WRITE(SDEIMR, 0xffffffff);
1298         I915_WRITE(SDEIER, 0x0);
1299         (void) I915_READ(SDEIER);
1300 }
1301
1302 static int ironlake_irq_postinstall(struct drm_device *dev)
1303 {
1304         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1305         /* enable kind of interrupts always enabled */
1306         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1307                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1308         u32 render_mask = GT_USER_INTERRUPT;
1309         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1310                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1311
1312         dev_priv->irq_mask_reg = ~display_mask;
1313         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1314
1315         /* should always can generate irq */
1316         I915_WRITE(DEIIR, I915_READ(DEIIR));
1317         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1318         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1319         (void) I915_READ(DEIER);
1320
1321         /* user interrupt should be enabled, but masked initial */
1322         dev_priv->gt_irq_mask_reg = 0xffffffff;
1323         dev_priv->gt_irq_enable_reg = render_mask;
1324
1325         I915_WRITE(GTIIR, I915_READ(GTIIR));
1326         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1327         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1328         (void) I915_READ(GTIER);
1329
1330         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1331         dev_priv->pch_irq_enable_reg = hotplug_mask;
1332
1333         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1334         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1335         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1336         (void) I915_READ(SDEIER);
1337
1338         if (IS_IRONLAKE_M(dev)) {
1339                 /* Clear & enable PCU event interrupts */
1340                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1341                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1342                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1343         }
1344
1345         return 0;
1346 }
1347
1348 void i915_driver_irq_preinstall(struct drm_device * dev)
1349 {
1350         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1351
1352         atomic_set(&dev_priv->irq_received, 0);
1353
1354         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1355         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1356
1357         if (HAS_PCH_SPLIT(dev)) {
1358                 ironlake_irq_preinstall(dev);
1359                 return;
1360         }
1361
1362         if (I915_HAS_HOTPLUG(dev)) {
1363                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1364                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1365         }
1366
1367         I915_WRITE(HWSTAM, 0xeffe);
1368         I915_WRITE(PIPEASTAT, 0);
1369         I915_WRITE(PIPEBSTAT, 0);
1370         I915_WRITE(IMR, 0xffffffff);
1371         I915_WRITE(IER, 0x0);
1372         (void) I915_READ(IER);
1373 }
1374
1375 /*
1376  * Must be called after intel_modeset_init or hotplug interrupts won't be
1377  * enabled correctly.
1378  */
1379 int i915_driver_irq_postinstall(struct drm_device *dev)
1380 {
1381         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1382         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1383         u32 error_mask;
1384
1385         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1386
1387         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1388
1389         if (HAS_PCH_SPLIT(dev))
1390                 return ironlake_irq_postinstall(dev);
1391
1392         /* Unmask the interrupts that we always want on. */
1393         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1394
1395         dev_priv->pipestat[0] = 0;
1396         dev_priv->pipestat[1] = 0;
1397
1398         if (I915_HAS_HOTPLUG(dev)) {
1399                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1400
1401                 /* Note HDMI and DP share bits */
1402                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1403                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1404                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1405                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1406                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1407                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1408                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1409                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1410                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1411                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1412                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1413                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1414                 /* Ignore TV since it's buggy */
1415
1416                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1417
1418                 /* Enable in IER... */
1419                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1420                 /* and unmask in IMR */
1421                 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1422         }
1423
1424         /*
1425          * Enable some error detection, note the instruction error mask
1426          * bit is reserved, so we leave it masked.
1427          */
1428         if (IS_G4X(dev)) {
1429                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1430                                GM45_ERROR_MEM_PRIV |
1431                                GM45_ERROR_CP_PRIV |
1432                                I915_ERROR_MEMORY_REFRESH);
1433         } else {
1434                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1435                                I915_ERROR_MEMORY_REFRESH);
1436         }
1437         I915_WRITE(EMR, error_mask);
1438
1439         /* Disable pipe interrupt enables, clear pending pipe status */
1440         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1441         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1442         /* Clear pending interrupt status */
1443         I915_WRITE(IIR, I915_READ(IIR));
1444
1445         I915_WRITE(IER, enable_mask);
1446         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1447         (void) I915_READ(IER);
1448
1449         opregion_enable_asle(dev);
1450
1451         return 0;
1452 }
1453
1454 static void ironlake_irq_uninstall(struct drm_device *dev)
1455 {
1456         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1457         I915_WRITE(HWSTAM, 0xffffffff);
1458
1459         I915_WRITE(DEIMR, 0xffffffff);
1460         I915_WRITE(DEIER, 0x0);
1461         I915_WRITE(DEIIR, I915_READ(DEIIR));
1462
1463         I915_WRITE(GTIMR, 0xffffffff);
1464         I915_WRITE(GTIER, 0x0);
1465         I915_WRITE(GTIIR, I915_READ(GTIIR));
1466 }
1467
1468 void i915_driver_irq_uninstall(struct drm_device * dev)
1469 {
1470         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1471
1472         if (!dev_priv)
1473                 return;
1474
1475         dev_priv->vblank_pipe = 0;
1476
1477         if (HAS_PCH_SPLIT(dev)) {
1478                 ironlake_irq_uninstall(dev);
1479                 return;
1480         }
1481
1482         if (I915_HAS_HOTPLUG(dev)) {
1483                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1484                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1485         }
1486
1487         I915_WRITE(HWSTAM, 0xffffffff);
1488         I915_WRITE(PIPEASTAT, 0);
1489         I915_WRITE(PIPEBSTAT, 0);
1490         I915_WRITE(IMR, 0xffffffff);
1491         I915_WRITE(IER, 0x0);
1492
1493         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1494         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1495         I915_WRITE(IIR, I915_READ(IIR));
1496 }