drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 struct change_domains {
  37         uint32_t invalidate_domains;
  38         uint32_t flush_domains;
  39         uint32_t flush_rings;
  40         uint32_t flips;
  41 };
  42
  43 /*
  44  * Set the next domain for the specified object. This
  45  * may not actually perform the necessary flushing/invaliding though,
  46  * as that may want to be batched with other set_domain operations
  47  *
  48  * This is (we hope) the only really tricky part of gem. The goal
  49  * is fairly simple -- track which caches hold bits of the object
  50  * and make sure they remain coherent. A few concrete examples may
  51  * help to explain how it works. For shorthand, we use the notation
  52  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
  53  * a pair of read and write domain masks.
  54  *
  55  * Case 1: the batch buffer
  56  *
  57  *      1. Allocated
  58  *      2. Written by CPU
  59  *      3. Mapped to GTT
  60  *      4. Read by GPU
  61  *      5. Unmapped from GTT
  62  *      6. Freed
  63  *
  64  *      Let's take these a step at a time
  65  *
  66  *      1. Allocated
  67  *              Pages allocated from the kernel may still have
  68  *              cache contents, so we set them to (CPU, CPU) always.
  69  *      2. Written by CPU (using pwrite)
  70  *              The pwrite function calls set_domain (CPU, CPU) and
  71  *              this function does nothing (as nothing changes)
  72  *      3. Mapped by GTT
  73  *              This function asserts that the object is not
  74  *              currently in any GPU-based read or write domains
  75  *      4. Read by GPU
  76  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
  77  *              As write_domain is zero, this function adds in the
  78  *              current read domains (CPU+COMMAND, 0).
  79  *              flush_domains is set to CPU.
  80  *              invalidate_domains is set to COMMAND
  81  *              clflush is run to get data out of the CPU caches
  82  *              then i915_dev_set_domain calls i915_gem_flush to
  83  *              emit an MI_FLUSH and drm_agp_chipset_flush
  84  *      5. Unmapped from GTT
  85  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
  86  *              flush_domains and invalidate_domains end up both zero
  87  *              so no flushing/invalidating happens
  88  *      6. Freed
  89  *              yay, done
  90  *
  91  * Case 2: The shared render buffer
  92  *
  93  *      1. Allocated
  94  *      2. Mapped to GTT
  95  *      3. Read/written by GPU
  96  *      4. set_domain to (CPU,CPU)
  97  *      5. Read/written by CPU
  98  *      6. Read/written by GPU
  99  *
 100  *      1. Allocated
 101  *              Same as last example, (CPU, CPU)
 102  *      2. Mapped to GTT
 103  *              Nothing changes (assertions find that it is not in the GPU)
 104  *      3. Read/written by GPU
 105  *              execbuffer calls set_domain (RENDER, RENDER)
 106  *              flush_domains gets CPU
 107  *              invalidate_domains gets GPU
 108  *              clflush (obj)
 109  *              MI_FLUSH and drm_agp_chipset_flush
 110  *      4. set_domain (CPU, CPU)
 111  *              flush_domains gets GPU
 112  *              invalidate_domains gets CPU
 113  *              wait_rendering (obj) to make sure all drawing is complete.
 114  *              This will include an MI_FLUSH to get the data from GPU
 115  *              to memory
 116  *              clflush (obj) to invalidate the CPU cache
 117  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
 118  *      5. Read/written by CPU
 119  *              cache lines are loaded and dirtied
 120  *      6. Read written by GPU
 121  *              Same as last GPU access
 122  *
 123  * Case 3: The constant buffer
 124  *
 125  *      1. Allocated
 126  *      2. Written by CPU
 127  *      3. Read by GPU
 128  *      4. Updated (written) by CPU again
 129  *      5. Read by GPU
 130  *
 131  *      1. Allocated
 132  *              (CPU, CPU)
 133  *      2. Written by CPU
 134  *              (CPU, CPU)
 135  *      3. Read by GPU
 136  *              (CPU+RENDER, 0)
 137  *              flush_domains = CPU
 138  *              invalidate_domains = RENDER
 139  *              clflush (obj)
 140  *              MI_FLUSH
 141  *              drm_agp_chipset_flush
 142  *      4. Updated (written) by CPU again
 143  *              (CPU, CPU)
 144  *              flush_domains = 0 (no previous write domain)
 145  *              invalidate_domains = 0 (no new read domains)
 146  *      5. Read by GPU
 147  *              (CPU+RENDER, 0)
 148  *              flush_domains = CPU
 149  *              invalidate_domains = RENDER
 150  *              clflush (obj)
 151  *              MI_FLUSH
 152  *              drm_agp_chipset_flush
 153  */
 154 static void
 155 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
 156                                   struct intel_ring_buffer *ring,
 157                                   struct change_domains *cd)
 158 {
 159         uint32_t invalidate_domains = 0, flush_domains = 0;
 160
 161         /*
 162          * If the object isn't moving to a new write domain,
 163          * let the object stay in multiple read domains
 164          */
 165         if (obj->base.pending_write_domain == 0)
 166                 obj->base.pending_read_domains |= obj->base.read_domains;
 167
 168         /*
 169          * Flush the current write domain if
 170          * the new read domains don't match. Invalidate
 171          * any read domains which differ from the old
 172          * write domain
 173          */
 174         if (obj->base.write_domain &&
 175             (((obj->base.write_domain != obj->base.pending_read_domains ||
 176                obj->ring != ring)) ||
 177              (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
 178                 flush_domains |= obj->base.write_domain;
 179                 invalidate_domains |=
 180                         obj->base.pending_read_domains & ~obj->base.write_domain;
 181         }
 182         /*
 183          * Invalidate any read caches which may have
 184          * stale data. That is, any new read domains.
 185          */
 186         invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
 187         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
 188                 i915_gem_clflush_object(obj);
 189
 190         if (obj->base.pending_write_domain)
 191                 cd->flips |= atomic_read(&obj->pending_flip);
 192
 193         /* The actual obj->write_domain will be updated with
 194          * pending_write_domain after we emit the accumulated flush for all
 195          * of our domain changes in execbuffers (which clears objects'
 196          * write_domains).  So if we have a current write domain that we
 197          * aren't changing, set pending_write_domain to that.
 198          */
 199         if (flush_domains == 0 && obj->base.pending_write_domain == 0)
 200                 obj->base.pending_write_domain = obj->base.write_domain;
 201
 202         cd->invalidate_domains |= invalidate_domains;
 203         cd->flush_domains |= flush_domains;
 204         if (flush_domains & I915_GEM_GPU_DOMAINS)
 205                 cd->flush_rings |= obj->ring->id;
 206         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
 207                 cd->flush_rings |= ring->id;
 208 }
 209
 210 struct eb_objects {
 211         int and;
 212         struct hlist_head buckets[0];
 213 };
 214
 215 static struct eb_objects *
 216 eb_create(int size)
 217 {
 218         struct eb_objects *eb;
 219         int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
 220         while (count > size)
 221                 count >>= 1;
 222         eb = kzalloc(count*sizeof(struct hlist_head) +
 223                      sizeof(struct eb_objects),
 224                      GFP_KERNEL);
 225         if (eb == NULL)
 226                 return eb;
 227
 228         eb->and = count - 1;
 229         return eb;
 230 }
 231
 232 static void
 233 eb_reset(struct eb_objects *eb)
 234 {
 235         memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
 236 }
 237
 238 static void
 239 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
 240 {
 241         hlist_add_head(&obj->exec_node,
 242                        &eb->buckets[obj->exec_handle & eb->and]);
 243 }
 244
 245 static struct drm_i915_gem_object *
 246 eb_get_object(struct eb_objects *eb, unsigned long handle)
 247 {
 248         struct hlist_head *head;
 249         struct hlist_node *node;
 250         struct drm_i915_gem_object *obj;
 251
 252         head = &eb->buckets[handle & eb->and];
 253         hlist_for_each(node, head) {
 254                 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
 255                 if (obj->exec_handle == handle)
 256                         return obj;
 257         }
 258
 259         return NULL;
 260 }
 261
 262 static void
 263 eb_destroy(struct eb_objects *eb)
 264 {
 265         kfree(eb);
 266 }
 267
 268 static int
 269 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 270                                    struct eb_objects *eb,
 271                                    struct drm_i915_gem_relocation_entry *reloc)
 272 {
 273         struct drm_device *dev = obj->base.dev;
 274         struct drm_gem_object *target_obj;
 275         uint32_t target_offset;
 276         int ret = -EINVAL;
 277
 278         /* we've already hold a reference to all valid objects */
 279         target_obj = &eb_get_object(eb, reloc->target_handle)->base;
 280         if (unlikely(target_obj == NULL))
 281                 return -ENOENT;
 282
 283         target_offset = to_intel_bo(target_obj)->gtt_offset;
 284
 285         /* The target buffer should have appeared before us in the
 286          * exec_object list, so it should have a GTT space bound by now.
 287          */
 288         if (unlikely(target_offset == 0)) {
 289                 DRM_ERROR("No GTT space found for object %d\n",
 290                           reloc->target_handle);
 291                 return ret;
 292         }
 293
 294         /* Validate that the target is in a valid r/w GPU domain */
 295         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 296                 DRM_ERROR("reloc with multiple write domains: "
 297                           "obj %p target %d offset %d "
 298                           "read %08x write %08x",
 299                           obj, reloc->target_handle,
 300                           (int) reloc->offset,
 301                           reloc->read_domains,
 302                           reloc->write_domain);
 303                 return ret;
 304         }
 305         if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) {
 306                 DRM_ERROR("reloc with read/write CPU domains: "
 307                           "obj %p target %d offset %d "
 308                           "read %08x write %08x",
 309                           obj, reloc->target_handle,
 310                           (int) reloc->offset,
 311                           reloc->read_domains,
 312                           reloc->write_domain);
 313                 return ret;
 314         }
 315         if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
 316                      reloc->write_domain != target_obj->pending_write_domain)) {
 317                 DRM_ERROR("Write domain conflict: "
 318                           "obj %p target %d offset %d "
 319                           "new %08x old %08x\n",
 320                           obj, reloc->target_handle,
 321                           (int) reloc->offset,
 322                           reloc->write_domain,
 323                           target_obj->pending_write_domain);
 324                 return ret;
 325         }
 326
 327         target_obj->pending_read_domains |= reloc->read_domains;
 328         target_obj->pending_write_domain |= reloc->write_domain;
 329
 330         /* If the relocation already has the right value in it, no
 331          * more work needs to be done.
 332          */
 333         if (target_offset == reloc->presumed_offset)
 334                 return 0;
 335
 336         /* Check that the relocation address is valid... */
 337         if (unlikely(reloc->offset > obj->base.size - 4)) {
 338                 DRM_ERROR("Relocation beyond object bounds: "
 339                           "obj %p target %d offset %d size %d.\n",
 340                           obj, reloc->target_handle,
 341                           (int) reloc->offset,
 342                           (int) obj->base.size);
 343                 return ret;
 344         }
 345         if (unlikely(reloc->offset & 3)) {
 346                 DRM_ERROR("Relocation not 4-byte aligned: "
 347                           "obj %p target %d offset %d.\n",
 348                           obj, reloc->target_handle,
 349                           (int) reloc->offset);
 350                 return ret;
 351         }
 352
 353         reloc->delta += target_offset;
 354         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
 355                 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
 356                 char *vaddr;
 357
 358                 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
 359                 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
 360                 kunmap_atomic(vaddr);
 361         } else {
 362                 struct drm_i915_private *dev_priv = dev->dev_private;
 363                 uint32_t __iomem *reloc_entry;
 364                 void __iomem *reloc_page;
 365
 366                 /* We can't wait for rendering with pagefaults disabled */
 367                 if (obj->active && in_atomic())
 368                         return -EFAULT;
 369
 370                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 371                 if (ret)
 372                         return ret;
 373
 374                 /* Map the page containing the relocation we're going to perform.  */
 375                 reloc->offset += obj->gtt_offset;
 376                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 377                                                       reloc->offset & PAGE_MASK);
 378                 reloc_entry = (uint32_t __iomem *)
 379                         (reloc_page + (reloc->offset & ~PAGE_MASK));
 380                 iowrite32(reloc->delta, reloc_entry);
 381                 io_mapping_unmap_atomic(reloc_page);
 382         }
 383
 384         /* and update the user's relocation entry */
 385         reloc->presumed_offset = target_offset;
 386
 387         return 0;
 388 }
 389
 390 static int
 391 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
 392                                     struct eb_objects *eb)
 393 {
 394         struct drm_i915_gem_relocation_entry __user *user_relocs;
 395         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 396         int i, ret;
 397
 398         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
 399         for (i = 0; i < entry->relocation_count; i++) {
 400                 struct drm_i915_gem_relocation_entry reloc;
 401
 402                 if (__copy_from_user_inatomic(&reloc,
 403                                               user_relocs+i,
 404                                               sizeof(reloc)))
 405                         return -EFAULT;
 406
 407                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
 408                 if (ret)
 409                         return ret;
 410
 411                 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
 412                                             &reloc.presumed_offset,
 413                                             sizeof(reloc.presumed_offset)))
 414                         return -EFAULT;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int
 421 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
 422                                          struct eb_objects *eb,
 423                                          struct drm_i915_gem_relocation_entry *relocs)
 424 {
 425         const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 426         int i, ret;
 427
 428         for (i = 0; i < entry->relocation_count; i++) {
 429                 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
 430                 if (ret)
 431                         return ret;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int
 438 i915_gem_execbuffer_relocate(struct drm_device *dev,
 439                              struct eb_objects *eb,
 440                              struct list_head *objects)
 441 {
 442         struct drm_i915_gem_object *obj;
 443         int ret = 0;
 444
 445         /* This is the fast path and we cannot handle a pagefault whilst
 446          * holding the struct mutex lest the user pass in the relocations
 447          * contained within a mmaped bo. For in such a case we, the page
 448          * fault handler would call i915_gem_fault() and we would try to
 449          * acquire the struct mutex again. Obviously this is bad and so
 450          * lockdep complains vehemently.
 451          */
 452         pagefault_disable();
 453         list_for_each_entry(obj, objects, exec_list) {
 454                 ret = i915_gem_execbuffer_relocate_object(obj, eb);
 455                 if (ret)
 456                         break;
 457         }
 458         pagefault_enable();
 459
 460         return ret;
 461 }
 462
 463 static int
 464 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
 465                             struct drm_file *file,
 466                             struct list_head *objects)
 467 {
 468         struct drm_i915_gem_object *obj;
 469         int ret, retry;
 470         bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
 471         struct list_head ordered_objects;
 472
 473         INIT_LIST_HEAD(&ordered_objects);
 474         while (!list_empty(objects)) {
 475                 struct drm_i915_gem_exec_object2 *entry;
 476                 bool need_fence, need_mappable;
 477
 478                 obj = list_first_entry(objects,
 479                                        struct drm_i915_gem_object,
 480                                        exec_list);
 481                 entry = obj->exec_entry;
 482
 483                 need_fence =
 484                         has_fenced_gpu_access &&
 485                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 486                         obj->tiling_mode != I915_TILING_NONE;
 487                 need_mappable =
 488                         entry->relocation_count ? true : need_fence;
 489
 490                 if (need_mappable)
 491                         list_move(&obj->exec_list, &ordered_objects);
 492                 else
 493                         list_move_tail(&obj->exec_list, &ordered_objects);
 494
 495                 obj->base.pending_read_domains = 0;
 496                 obj->base.pending_write_domain = 0;
 497         }
 498         list_splice(&ordered_objects, objects);
 499
 500         /* Attempt to pin all of the buffers into the GTT.
 501          * This is done in 3 phases:
 502          *
 503          * 1a. Unbind all objects that do not match the GTT constraints for
 504          *     the execbuffer (fenceable, mappable, alignment etc).
 505          * 1b. Increment pin count for already bound objects.
 506          * 2.  Bind new objects.
 507          * 3.  Decrement pin count.
 508          *
 509          * This avoid unnecessary unbinding of later objects in order to makr
 510          * room for the earlier objects *unless* we need to defragment.
 511          */
 512         retry = 0;
 513         do {
 514                 ret = 0;
 515
 516                 /* Unbind any ill-fitting objects or pin. */
 517                 list_for_each_entry(obj, objects, exec_list) {
 518                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 519                         bool need_fence, need_mappable;
 520                         if (!obj->gtt_space)
 521                                 continue;
 522
 523                         need_fence =
 524                                 has_fenced_gpu_access &&
 525                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 526                                 obj->tiling_mode != I915_TILING_NONE;
 527                         need_mappable =
 528                                 entry->relocation_count ? true : need_fence;
 529
 530                         if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
 531                             (need_mappable && !obj->map_and_fenceable))
 532                                 ret = i915_gem_object_unbind(obj);
 533                         else
 534                                 ret = i915_gem_object_pin(obj,
 535                                                           entry->alignment,
 536                                                           need_mappable);
 537                         if (ret)
 538                                 goto err;
 539
 540                         entry++;
 541                 }
 542
 543                 /* Bind fresh objects */
 544                 list_for_each_entry(obj, objects, exec_list) {
 545                         struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
 546                         bool need_fence;
 547
 548                         need_fence =
 549                                 has_fenced_gpu_access &&
 550                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 551                                 obj->tiling_mode != I915_TILING_NONE;
 552
 553                         if (!obj->gtt_space) {
 554                                 bool need_mappable =
 555                                         entry->relocation_count ? true : need_fence;
 556
 557                                 ret = i915_gem_object_pin(obj,
 558                                                           entry->alignment,
 559                                                           need_mappable);
 560                                 if (ret)
 561                                         break;
 562                         }
 563
 564                         if (has_fenced_gpu_access) {
 565                                 if (need_fence) {
 566                                         ret = i915_gem_object_get_fence(obj, ring);
 567                                         if (ret)
 568                                                 break;
 569                                 } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 570                                            obj->tiling_mode == I915_TILING_NONE) {
 571                                         /* XXX pipelined! */
 572                                         ret = i915_gem_object_put_fence(obj);
 573                                         if (ret)
 574                                                 break;
 575                                 }
 576                                 obj->pending_fenced_gpu_access = need_fence;
 577                         }
 578
 579                         entry->offset = obj->gtt_offset;
 580                 }
 581
 582                 /* Decrement pin count for bound objects */
 583                 list_for_each_entry(obj, objects, exec_list) {
 584                         if (obj->gtt_space)
 585                                 i915_gem_object_unpin(obj);
 586                 }
 587
 588                 if (ret != -ENOSPC || retry > 1)
 589                         return ret;
 590
 591                 /* First attempt, just clear anything that is purgeable.
 592                  * Second attempt, clear the entire GTT.
 593                  */
 594                 ret = i915_gem_evict_everything(ring->dev, retry == 0);
 595                 if (ret)
 596                         return ret;
 597
 598                 retry++;
 599         } while (1);
 600
 601 err:
 602         obj = list_entry(obj->exec_list.prev,
 603                          struct drm_i915_gem_object,
 604                          exec_list);
 605         while (objects != &obj->exec_list) {
 606                 if (obj->gtt_space)
 607                         i915_gem_object_unpin(obj);
 608
 609                 obj = list_entry(obj->exec_list.prev,
 610                                  struct drm_i915_gem_object,
 611                                  exec_list);
 612         }
 613
 614         return ret;
 615 }
 616
 617 static int
 618 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 619                                   struct drm_file *file,
 620                                   struct intel_ring_buffer *ring,
 621                                   struct list_head *objects,
 622                                   struct eb_objects *eb,
 623                                   struct drm_i915_gem_exec_object2 *exec,
 624                                   int count)
 625 {
 626         struct drm_i915_gem_relocation_entry *reloc;
 627         struct drm_i915_gem_object *obj;
 628         int *reloc_offset;
 629         int i, total, ret;
 630
 631         /* We may process another execbuffer during the unlock... */
 632         while (!list_empty(objects)) {
 633                 obj = list_first_entry(objects,
 634                                        struct drm_i915_gem_object,
 635                                        exec_list);
 636                 list_del_init(&obj->exec_list);
 637                 drm_gem_object_unreference(&obj->base);
 638         }
 639
 640         mutex_unlock(&dev->struct_mutex);
 641
 642         total = 0;
 643         for (i = 0; i < count; i++)
 644                 total += exec[i].relocation_count;
 645
 646         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 647         reloc = drm_malloc_ab(total, sizeof(*reloc));
 648         if (reloc == NULL || reloc_offset == NULL) {
 649                 drm_free_large(reloc);
 650                 drm_free_large(reloc_offset);
 651                 mutex_lock(&dev->struct_mutex);
 652                 return -ENOMEM;
 653         }
 654
 655         total = 0;
 656         for (i = 0; i < count; i++) {
 657                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 658
 659                 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
 660
 661                 if (copy_from_user(reloc+total, user_relocs,
 662                                    exec[i].relocation_count * sizeof(*reloc))) {
 663                         ret = -EFAULT;
 664                         mutex_lock(&dev->struct_mutex);
 665                         goto err;
 666                 }
 667
 668                 reloc_offset[i] = total;
 669                 total += exec[i].relocation_count;
 670         }
 671
 672         ret = i915_mutex_lock_interruptible(dev);
 673         if (ret) {
 674                 mutex_lock(&dev->struct_mutex);
 675                 goto err;
 676         }
 677
 678         /* reacquire the objects */
 679         eb_reset(eb);
 680         for (i = 0; i < count; i++) {
 681                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
 682                                                         exec[i].handle));
 683                 if (&obj->base == NULL) {
 684                         DRM_ERROR("Invalid object handle %d at index %d\n",
 685                                    exec[i].handle, i);
 686                         ret = -ENOENT;
 687                         goto err;
 688                 }
 689
 690                 list_add_tail(&obj->exec_list, objects);
 691                 obj->exec_handle = exec[i].handle;
 692                 obj->exec_entry = &exec[i];
 693                 eb_add_object(eb, obj);
 694         }
 695
 696         ret = i915_gem_execbuffer_reserve(ring, file, objects);
 697         if (ret)
 698                 goto err;
 699
 700         list_for_each_entry(obj, objects, exec_list) {
 701                 int offset = obj->exec_entry - exec;
 702                 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
 703                                                                reloc + reloc_offset[offset]);
 704                 if (ret)
 705                         goto err;
 706         }
 707
 708         /* Leave the user relocations as are, this is the painfully slow path,
 709          * and we want to avoid the complication of dropping the lock whilst
 710          * having buffers reserved in the aperture and so causing spurious
 711          * ENOSPC for random operations.
 712          */
 713
 714 err:
 715         drm_free_large(reloc);
 716         drm_free_large(reloc_offset);
 717         return ret;
 718 }
 719
 720 static int
 721 i915_gem_execbuffer_flush(struct drm_device *dev,
 722                           uint32_t invalidate_domains,
 723                           uint32_t flush_domains,
 724                           uint32_t flush_rings)
 725 {
 726         drm_i915_private_t *dev_priv = dev->dev_private;
 727         int i, ret;
 728
 729         if (flush_domains & I915_GEM_DOMAIN_CPU)
 730                 intel_gtt_chipset_flush();
 731
 732         if (flush_domains & I915_GEM_DOMAIN_GTT)
 733                 wmb();
 734
 735         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
 736                 for (i = 0; i < I915_NUM_RINGS; i++)
 737                         if (flush_rings & (1 << i)) {
 738                                 ret = i915_gem_flush_ring(&dev_priv->ring[i],
 739                                                           invalidate_domains,
 740                                                           flush_domains);
 741                                 if (ret)
 742                                         return ret;
 743                         }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
 751                                struct intel_ring_buffer *to)
 752 {
 753         struct intel_ring_buffer *from = obj->ring;
 754         u32 seqno;
 755         int ret, idx;
 756
 757         if (from == NULL || to == from)
 758                 return 0;
 759
 760         /* XXX gpu semaphores are implicated in various hard hangs on SNB */
 761         if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
 762                 return i915_gem_object_wait_rendering(obj);
 763
 764         idx = intel_ring_sync_index(from, to);
 765
 766         seqno = obj->last_rendering_seqno;
 767         if (seqno <= from->sync_seqno[idx])
 768                 return 0;
 769
 770         if (seqno == from->outstanding_lazy_request) {
 771                 struct drm_i915_gem_request *request;
 772
 773                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 774                 if (request == NULL)
 775                         return -ENOMEM;
 776
 777                 ret = i915_add_request(from, NULL, request);
 778                 if (ret) {
 779                         kfree(request);
 780                         return ret;
 781                 }
 782
 783                 seqno = request->seqno;
 784         }
 785
 786         from->sync_seqno[idx] = seqno;
 787
 788         return to->sync_to(to, from, seqno - 1);
 789 }
 790
 791 static int
 792 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
 793 {
 794         u32 plane, flip_mask;
 795         int ret;
 796
 797         /* Check for any pending flips. As we only maintain a flip queue depth
 798          * of 1, we can simply insert a WAIT for the next display flip prior
 799          * to executing the batch and avoid stalling the CPU.
 800          */
 801
 802         for (plane = 0; flips >> plane; plane++) {
 803                 if (((flips >> plane) & 1) == 0)
 804                         continue;
 805
 806                 if (plane)
 807                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
 808                 else
 809                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
 810
 811                 ret = intel_ring_begin(ring, 2);
 812                 if (ret)
 813                         return ret;
 814
 815                 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
 816                 intel_ring_emit(ring, MI_NOOP);
 817                 intel_ring_advance(ring);
 818         }
 819
 820         return 0;
 821 }
 822
 823
 824 static int
 825 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
 826                                 struct list_head *objects)
 827 {
 828         struct drm_i915_gem_object *obj;
 829         struct change_domains cd;
 830         int ret;
 831
 832         memset(&cd, 0, sizeof(cd));
 833         list_for_each_entry(obj, objects, exec_list)
 834                 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
 835
 836         if (cd.invalidate_domains | cd.flush_domains) {
 837                 ret = i915_gem_execbuffer_flush(ring->dev,
 838                                                 cd.invalidate_domains,
 839                                                 cd.flush_domains,
 840                                                 cd.flush_rings);
 841                 if (ret)
 842                         return ret;
 843         }
 844
 845         if (cd.flips) {
 846                 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
 847                 if (ret)
 848                         return ret;
 849         }
 850
 851         list_for_each_entry(obj, objects, exec_list) {
 852                 ret = i915_gem_execbuffer_sync_rings(obj, ring);
 853                 if (ret)
 854                         return ret;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static bool
 861 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 862 {
 863         return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
 864 }
 865
 866 static int
 867 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 868                    int count)
 869 {
 870         int i;
 871
 872         for (i = 0; i < count; i++) {
 873                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
 874                 int length; /* limited by fault_in_pages_readable() */
 875
 876                 /* First check for malicious input causing overflow */
 877                 if (exec[i].relocation_count >
 878                     INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
 879                         return -EINVAL;
 880
 881                 length = exec[i].relocation_count *
 882                         sizeof(struct drm_i915_gem_relocation_entry);
 883                 if (!access_ok(VERIFY_READ, ptr, length))
 884                         return -EFAULT;
 885
 886                 /* we may also need to update the presumed offsets */
 887                 if (!access_ok(VERIFY_WRITE, ptr, length))
 888                         return -EFAULT;
 889
 890                 if (fault_in_pages_readable(ptr, length))
 891                         return -EFAULT;
 892         }
 893
 894         return 0;
 895 }
 896
 897 static void
 898 i915_gem_execbuffer_move_to_active(struct list_head *objects,
 899                                    struct intel_ring_buffer *ring,
 900                                    u32 seqno)
 901 {
 902         struct drm_i915_gem_object *obj;
 903
 904         list_for_each_entry(obj, objects, exec_list) {
 905                   u32 old_read = obj->base.read_domains;
 906                   u32 old_write = obj->base.write_domain;
 907
 908
 909                 obj->base.read_domains = obj->base.pending_read_domains;
 910                 obj->base.write_domain = obj->base.pending_write_domain;
 911                 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
 912
 913                 i915_gem_object_move_to_active(obj, ring, seqno);
 914                 if (obj->base.write_domain) {
 915                         obj->dirty = 1;
 916                         obj->pending_gpu_write = true;
 917                         list_move_tail(&obj->gpu_write_list,
 918                                        &ring->gpu_write_list);
 919                         intel_mark_busy(ring->dev, obj);
 920                 }
 921
 922                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
 923         }
 924 }
 925
 926 static void
 927 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
 928                                     struct drm_file *file,
 929                                     struct intel_ring_buffer *ring)
 930 {
 931         struct drm_i915_gem_request *request;
 932         u32 invalidate;
 933
 934         /*
 935          * Ensure that the commands in the batch buffer are
 936          * finished before the interrupt fires.
 937          *
 938          * The sampler always gets flushed on i965 (sigh).
 939          */
 940         invalidate = I915_GEM_DOMAIN_COMMAND;
 941         if (INTEL_INFO(dev)->gen >= 4)
 942                 invalidate |= I915_GEM_DOMAIN_SAMPLER;
 943         if (ring->flush(ring, invalidate, 0)) {
 944                 i915_gem_next_request_seqno(ring);
 945                 return;
 946         }
 947
 948         /* Add a breadcrumb for the completion of the batch buffer */
 949         request = kzalloc(sizeof(*request), GFP_KERNEL);
 950         if (request == NULL || i915_add_request(ring, file, request)) {
 951                 i915_gem_next_request_seqno(ring);
 952                 kfree(request);
 953         }
 954 }
 955
 956 static int
 957 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 958                        struct drm_file *file,
 959                        struct drm_i915_gem_execbuffer2 *args,
 960                        struct drm_i915_gem_exec_object2 *exec)
 961 {
 962         drm_i915_private_t *dev_priv = dev->dev_private;
 963         struct list_head objects;
 964         struct eb_objects *eb;
 965         struct drm_i915_gem_object *batch_obj;
 966         struct drm_clip_rect *cliprects = NULL;
 967         struct intel_ring_buffer *ring;
 968         u32 exec_start, exec_len;
 969         u32 seqno;
 970         int ret, mode, i;
 971
 972         if (!i915_gem_check_execbuffer(args)) {
 973                 DRM_ERROR("execbuf with invalid offset/length\n");
 974                 return -EINVAL;
 975         }
 976
 977         ret = validate_exec_list(exec, args->buffer_count);
 978         if (ret)
 979                 return ret;
 980
 981         switch (args->flags & I915_EXEC_RING_MASK) {
 982         case I915_EXEC_DEFAULT:
 983         case I915_EXEC_RENDER:
 984                 ring = &dev_priv->ring[RCS];
 985                 break;
 986         case I915_EXEC_BSD:
 987                 if (!HAS_BSD(dev)) {
 988                         DRM_ERROR("execbuf with invalid ring (BSD)\n");
 989                         return -EINVAL;
 990                 }
 991                 ring = &dev_priv->ring[VCS];
 992                 break;
 993         case I915_EXEC_BLT:
 994                 if (!HAS_BLT(dev)) {
 995                         DRM_ERROR("execbuf with invalid ring (BLT)\n");
 996                         return -EINVAL;
 997                 }
 998                 ring = &dev_priv->ring[BCS];
 999                 break;
1000         default:
1001                 DRM_ERROR("execbuf with unknown ring: %d\n",
1002                           (int)(args->flags & I915_EXEC_RING_MASK));
1003                 return -EINVAL;
1004         }
1005
1006         mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1007         switch (mode) {
1008         case I915_EXEC_CONSTANTS_REL_GENERAL:
1009         case I915_EXEC_CONSTANTS_ABSOLUTE:
1010         case I915_EXEC_CONSTANTS_REL_SURFACE:
1011                 if (ring == &dev_priv->ring[RCS] &&
1012                     mode != dev_priv->relative_constants_mode) {
1013                         if (INTEL_INFO(dev)->gen < 4)
1014                                 return -EINVAL;
1015
1016                         if (INTEL_INFO(dev)->gen > 5 &&
1017                             mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1018                                 return -EINVAL;
1019
1020                         ret = intel_ring_begin(ring, 4);
1021                         if (ret)
1022                                 return ret;
1023
1024                         intel_ring_emit(ring, MI_NOOP);
1025                         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1026                         intel_ring_emit(ring, INSTPM);
1027                         intel_ring_emit(ring,
1028                                         I915_EXEC_CONSTANTS_MASK << 16 | mode);
1029                         intel_ring_advance(ring);
1030
1031                         dev_priv->relative_constants_mode = mode;
1032                 }
1033                 break;
1034         default:
1035                 DRM_ERROR("execbuf with unknown constants: %d\n", mode);
1036                 return -EINVAL;
1037         }
1038
1039         if (args->buffer_count < 1) {
1040                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1041                 return -EINVAL;
1042         }
1043
1044         if (args->num_cliprects != 0) {
1045                 if (ring != &dev_priv->ring[RCS]) {
1046                         DRM_ERROR("clip rectangles are only valid with the render ring\n");
1047                         return -EINVAL;
1048                 }
1049
1050                 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1051                                     GFP_KERNEL);
1052                 if (cliprects == NULL) {
1053                         ret = -ENOMEM;
1054                         goto pre_mutex_err;
1055                 }
1056
1057                 if (copy_from_user(cliprects,
1058                                      (struct drm_clip_rect __user *)(uintptr_t)
1059                                      args->cliprects_ptr,
1060                                      sizeof(*cliprects)*args->num_cliprects)) {
1061                         ret = -EFAULT;
1062                         goto pre_mutex_err;
1063                 }
1064         }
1065
1066         ret = i915_mutex_lock_interruptible(dev);
1067         if (ret)
1068                 goto pre_mutex_err;
1069
1070         if (dev_priv->mm.suspended) {
1071                 mutex_unlock(&dev->struct_mutex);
1072                 ret = -EBUSY;
1073                 goto pre_mutex_err;
1074         }
1075
1076         eb = eb_create(args->buffer_count);
1077         if (eb == NULL) {
1078                 mutex_unlock(&dev->struct_mutex);
1079                 ret = -ENOMEM;
1080                 goto pre_mutex_err;
1081         }
1082
1083         /* Look up object handles */
1084         INIT_LIST_HEAD(&objects);
1085         for (i = 0; i < args->buffer_count; i++) {
1086                 struct drm_i915_gem_object *obj;
1087
1088                 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1089                                                         exec[i].handle));
1090                 if (&obj->base == NULL) {
1091                         DRM_ERROR("Invalid object handle %d at index %d\n",
1092                                    exec[i].handle, i);
1093                         /* prevent error path from reading uninitialized data */
1094                         ret = -ENOENT;
1095                         goto err;
1096                 }
1097
1098                 if (!list_empty(&obj->exec_list)) {
1099                         DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1100                                    obj, exec[i].handle, i);
1101                         ret = -EINVAL;
1102                         goto err;
1103                 }
1104
1105                 list_add_tail(&obj->exec_list, &objects);
1106                 obj->exec_handle = exec[i].handle;
1107                 obj->exec_entry = &exec[i];
1108                 eb_add_object(eb, obj);
1109         }
1110
1111         /* take note of the batch buffer before we might reorder the lists */
1112         batch_obj = list_entry(objects.prev,
1113                                struct drm_i915_gem_object,
1114                                exec_list);
1115
1116         /* Move the objects en-masse into the GTT, evicting if necessary. */
1117         ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1118         if (ret)
1119                 goto err;
1120
1121         /* The objects are in their final locations, apply the relocations. */
1122         ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1123         if (ret) {
1124                 if (ret == -EFAULT) {
1125                         ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1126                                                                 &objects, eb,
1127                                                                 exec,
1128                                                                 args->buffer_count);
1129                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1130                 }
1131                 if (ret)
1132                         goto err;
1133         }
1134
1135         /* Set the pending read domains for the batch buffer to COMMAND */
1136         if (batch_obj->base.pending_write_domain) {
1137                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1138                 ret = -EINVAL;
1139                 goto err;
1140         }
1141         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1142
1143         ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1144         if (ret)
1145                 goto err;
1146
1147         seqno = i915_gem_next_request_seqno(ring);
1148         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1149                 if (seqno < ring->sync_seqno[i]) {
1150                         /* The GPU can not handle its semaphore value wrapping,
1151                          * so every billion or so execbuffers, we need to stall
1152                          * the GPU in order to reset the counters.
1153                          */
1154                         ret = i915_gpu_idle(dev);
1155                         if (ret)
1156                                 goto err;
1157
1158                         BUG_ON(ring->sync_seqno[i]);
1159                 }
1160         }
1161
1162         trace_i915_gem_ring_dispatch(ring, seqno);
1163
1164         exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1165         exec_len = args->batch_len;
1166         if (cliprects) {
1167                 for (i = 0; i < args->num_cliprects; i++) {
1168                         ret = i915_emit_box(dev, &cliprects[i],
1169                                             args->DR1, args->DR4);
1170                         if (ret)
1171                                 goto err;
1172
1173                         ret = ring->dispatch_execbuffer(ring,
1174                                                         exec_start, exec_len);
1175                         if (ret)
1176                                 goto err;
1177                 }
1178         } else {
1179                 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1180                 if (ret)
1181                         goto err;
1182         }
1183
1184         i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1185         i915_gem_execbuffer_retire_commands(dev, file, ring);
1186
1187 err:
1188         eb_destroy(eb);
1189         while (!list_empty(&objects)) {
1190                 struct drm_i915_gem_object *obj;
1191
1192                 obj = list_first_entry(&objects,
1193                                        struct drm_i915_gem_object,
1194                                        exec_list);
1195                 list_del_init(&obj->exec_list);
1196                 drm_gem_object_unreference(&obj->base);
1197         }
1198
1199         mutex_unlock(&dev->struct_mutex);
1200
1201 pre_mutex_err:
1202         kfree(cliprects);
1203         return ret;
1204 }
1205
1206 /*
1207  * Legacy execbuffer just creates an exec2 list from the original exec object
1208  * list array and passes it to the real function.
1209  */
1210 int
1211 i915_gem_execbuffer(struct drm_device *dev, void *data,
1212                     struct drm_file *file)
1213 {
1214         struct drm_i915_gem_execbuffer *args = data;
1215         struct drm_i915_gem_execbuffer2 exec2;
1216         struct drm_i915_gem_exec_object *exec_list = NULL;
1217         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1218         int ret, i;
1219
1220         if (args->buffer_count < 1) {
1221                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1222                 return -EINVAL;
1223         }
1224
1225         /* Copy in the exec list from userland */
1226         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1227         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1228         if (exec_list == NULL || exec2_list == NULL) {
1229                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1230                           args->buffer_count);
1231                 drm_free_large(exec_list);
1232                 drm_free_large(exec2_list);
1233                 return -ENOMEM;
1234         }
1235         ret = copy_from_user(exec_list,
1236                              (struct drm_i915_relocation_entry __user *)
1237                              (uintptr_t) args->buffers_ptr,
1238                              sizeof(*exec_list) * args->buffer_count);
1239         if (ret != 0) {
1240                 DRM_ERROR("copy %d exec entries failed %d\n",
1241                           args->buffer_count, ret);
1242                 drm_free_large(exec_list);
1243                 drm_free_large(exec2_list);
1244                 return -EFAULT;
1245         }
1246
1247         for (i = 0; i < args->buffer_count; i++) {
1248                 exec2_list[i].handle = exec_list[i].handle;
1249                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1250                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1251                 exec2_list[i].alignment = exec_list[i].alignment;
1252                 exec2_list[i].offset = exec_list[i].offset;
1253                 if (INTEL_INFO(dev)->gen < 4)
1254                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1255                 else
1256                         exec2_list[i].flags = 0;
1257         }
1258
1259         exec2.buffers_ptr = args->buffers_ptr;
1260         exec2.buffer_count = args->buffer_count;
1261         exec2.batch_start_offset = args->batch_start_offset;
1262         exec2.batch_len = args->batch_len;
1263         exec2.DR1 = args->DR1;
1264         exec2.DR4 = args->DR4;
1265         exec2.num_cliprects = args->num_cliprects;
1266         exec2.cliprects_ptr = args->cliprects_ptr;
1267         exec2.flags = I915_EXEC_RENDER;
1268
1269         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1270         if (!ret) {
1271                 /* Copy the new buffer offsets back to the user's exec list. */
1272                 for (i = 0; i < args->buffer_count; i++)
1273                         exec_list[i].offset = exec2_list[i].offset;
1274                 /* ... and back out to userspace */
1275                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1276                                    (uintptr_t) args->buffers_ptr,
1277                                    exec_list,
1278                                    sizeof(*exec_list) * args->buffer_count);
1279                 if (ret) {
1280                         ret = -EFAULT;
1281                         DRM_ERROR("failed to copy %d exec entries "
1282                                   "back to user (%d)\n",
1283                                   args->buffer_count, ret);
1284                 }
1285         }
1286
1287         drm_free_large(exec_list);
1288         drm_free_large(exec2_list);
1289         return ret;
1290 }
1291
1292 int
1293 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1294                      struct drm_file *file)
1295 {
1296         struct drm_i915_gem_execbuffer2 *args = data;
1297         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1298         int ret;
1299
1300         if (args->buffer_count < 1) {
1301                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1302                 return -EINVAL;
1303         }
1304
1305         exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1306                              GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1307         if (exec2_list == NULL)
1308                 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1309                                            args->buffer_count);
1310         if (exec2_list == NULL) {
1311                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1312                           args->buffer_count);
1313                 return -ENOMEM;
1314         }
1315         ret = copy_from_user(exec2_list,
1316                              (struct drm_i915_relocation_entry __user *)
1317                              (uintptr_t) args->buffers_ptr,
1318                              sizeof(*exec2_list) * args->buffer_count);
1319         if (ret != 0) {
1320                 DRM_ERROR("copy %d exec entries failed %d\n",
1321                           args->buffer_count, ret);
1322                 drm_free_large(exec2_list);
1323                 return -EFAULT;
1324         }
1325
1326         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1327         if (!ret) {
1328                 /* Copy the new buffer offsets back to the user's exec list. */
1329                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1330                                    (uintptr_t) args->buffers_ptr,
1331                                    exec2_list,
1332                                    sizeof(*exec2_list) * args->buffer_count);
1333                 if (ret) {
1334                         ret = -EFAULT;
1335                         DRM_ERROR("failed to copy %d exec entries "
1336                                   "back to user (%d)\n",
1337                                   args->buffer_count, ret);
1338                 }
1339         }
1340
1341         drm_free_large(exec2_list);
1342         return ret;
1343 }