2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 struct change_domains {
37 uint32_t invalidate_domains;
38 uint32_t flush_domains;
43 * Set the next domain for the specified object. This
44 * may not actually perform the necessary flushing/invaliding though,
45 * as that may want to be batched with other set_domain operations
47 * This is (we hope) the only really tricky part of gem. The goal
48 * is fairly simple -- track which caches hold bits of the object
49 * and make sure they remain coherent. A few concrete examples may
50 * help to explain how it works. For shorthand, we use the notation
51 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
52 * a pair of read and write domain masks.
54 * Case 1: the batch buffer
60 * 5. Unmapped from GTT
63 * Let's take these a step at a time
66 * Pages allocated from the kernel may still have
67 * cache contents, so we set them to (CPU, CPU) always.
68 * 2. Written by CPU (using pwrite)
69 * The pwrite function calls set_domain (CPU, CPU) and
70 * this function does nothing (as nothing changes)
72 * This function asserts that the object is not
73 * currently in any GPU-based read or write domains
75 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
76 * As write_domain is zero, this function adds in the
77 * current read domains (CPU+COMMAND, 0).
78 * flush_domains is set to CPU.
79 * invalidate_domains is set to COMMAND
80 * clflush is run to get data out of the CPU caches
81 * then i915_dev_set_domain calls i915_gem_flush to
82 * emit an MI_FLUSH and drm_agp_chipset_flush
83 * 5. Unmapped from GTT
84 * i915_gem_object_unbind calls set_domain (CPU, CPU)
85 * flush_domains and invalidate_domains end up both zero
86 * so no flushing/invalidating happens
90 * Case 2: The shared render buffer
94 * 3. Read/written by GPU
95 * 4. set_domain to (CPU,CPU)
96 * 5. Read/written by CPU
97 * 6. Read/written by GPU
100 * Same as last example, (CPU, CPU)
102 * Nothing changes (assertions find that it is not in the GPU)
103 * 3. Read/written by GPU
104 * execbuffer calls set_domain (RENDER, RENDER)
105 * flush_domains gets CPU
106 * invalidate_domains gets GPU
108 * MI_FLUSH and drm_agp_chipset_flush
109 * 4. set_domain (CPU, CPU)
110 * flush_domains gets GPU
111 * invalidate_domains gets CPU
112 * wait_rendering (obj) to make sure all drawing is complete.
113 * This will include an MI_FLUSH to get the data from GPU
115 * clflush (obj) to invalidate the CPU cache
116 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
117 * 5. Read/written by CPU
118 * cache lines are loaded and dirtied
119 * 6. Read written by GPU
120 * Same as last GPU access
122 * Case 3: The constant buffer
127 * 4. Updated (written) by CPU again
136 * flush_domains = CPU
137 * invalidate_domains = RENDER
140 * drm_agp_chipset_flush
141 * 4. Updated (written) by CPU again
143 * flush_domains = 0 (no previous write domain)
144 * invalidate_domains = 0 (no new read domains)
147 * flush_domains = CPU
148 * invalidate_domains = RENDER
151 * drm_agp_chipset_flush
154 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
155 struct intel_ring_buffer *ring,
156 struct change_domains *cd)
158 uint32_t invalidate_domains = 0, flush_domains = 0;
161 * If the object isn't moving to a new write domain,
162 * let the object stay in multiple read domains
164 if (obj->base.pending_write_domain == 0)
165 obj->base.pending_read_domains |= obj->base.read_domains;
168 * Flush the current write domain if
169 * the new read domains don't match. Invalidate
170 * any read domains which differ from the old
173 if (obj->base.write_domain &&
174 (((obj->base.write_domain != obj->base.pending_read_domains ||
175 obj->ring != ring)) ||
176 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
177 flush_domains |= obj->base.write_domain;
178 invalidate_domains |=
179 obj->base.pending_read_domains & ~obj->base.write_domain;
182 * Invalidate any read caches which may have
183 * stale data. That is, any new read domains.
185 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
186 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
187 i915_gem_clflush_object(obj);
189 /* blow away mappings if mapped through GTT */
190 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT)
191 i915_gem_release_mmap(obj);
193 /* The actual obj->write_domain will be updated with
194 * pending_write_domain after we emit the accumulated flush for all
195 * of our domain changes in execbuffers (which clears objects'
196 * write_domains). So if we have a current write domain that we
197 * aren't changing, set pending_write_domain to that.
199 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
200 obj->base.pending_write_domain = obj->base.write_domain;
202 cd->invalidate_domains |= invalidate_domains;
203 cd->flush_domains |= flush_domains;
204 if (flush_domains & I915_GEM_GPU_DOMAINS)
205 cd->flush_rings |= obj->ring->id;
206 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
207 cd->flush_rings |= ring->id;
212 struct hlist_head buckets[0];
215 static struct eb_objects *
218 struct eb_objects *eb;
219 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
222 eb = kzalloc(count*sizeof(struct hlist_head) +
223 sizeof(struct eb_objects),
233 eb_reset(struct eb_objects *eb)
235 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
239 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
241 hlist_add_head(&obj->exec_node,
242 &eb->buckets[obj->exec_handle & eb->and]);
245 static struct drm_i915_gem_object *
246 eb_get_object(struct eb_objects *eb, unsigned long handle)
248 struct hlist_head *head;
249 struct hlist_node *node;
250 struct drm_i915_gem_object *obj;
252 head = &eb->buckets[handle & eb->and];
253 hlist_for_each(node, head) {
254 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
255 if (obj->exec_handle == handle)
263 eb_destroy(struct eb_objects *eb)
269 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
270 struct eb_objects *eb,
271 struct drm_i915_gem_exec_object2 *entry,
272 struct drm_i915_gem_relocation_entry *reloc)
274 struct drm_device *dev = obj->base.dev;
275 struct drm_gem_object *target_obj;
276 uint32_t target_offset;
279 /* we've already hold a reference to all valid objects */
280 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
281 if (unlikely(target_obj == NULL))
284 target_offset = to_intel_bo(target_obj)->gtt_offset;
287 DRM_INFO("%s: obj %p offset %08x target %d "
288 "read %08x write %08x gtt %08x "
289 "presumed %08x delta %08x\n",
293 (int) reloc->target_handle,
294 (int) reloc->read_domains,
295 (int) reloc->write_domain,
297 (int) reloc->presumed_offset,
301 /* The target buffer should have appeared before us in the
302 * exec_object list, so it should have a GTT space bound by now.
304 if (unlikely(target_offset == 0)) {
305 DRM_ERROR("No GTT space found for object %d\n",
306 reloc->target_handle);
310 /* Validate that the target is in a valid r/w GPU domain */
311 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
312 DRM_ERROR("reloc with multiple write domains: "
313 "obj %p target %d offset %d "
314 "read %08x write %08x",
315 obj, reloc->target_handle,
318 reloc->write_domain);
321 if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) {
322 DRM_ERROR("reloc with read/write CPU domains: "
323 "obj %p target %d offset %d "
324 "read %08x write %08x",
325 obj, reloc->target_handle,
328 reloc->write_domain);
331 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
332 reloc->write_domain != target_obj->pending_write_domain)) {
333 DRM_ERROR("Write domain conflict: "
334 "obj %p target %d offset %d "
335 "new %08x old %08x\n",
336 obj, reloc->target_handle,
339 target_obj->pending_write_domain);
343 target_obj->pending_read_domains |= reloc->read_domains;
344 target_obj->pending_write_domain |= reloc->write_domain;
346 /* If the relocation already has the right value in it, no
347 * more work needs to be done.
349 if (target_offset == reloc->presumed_offset)
352 /* Check that the relocation address is valid... */
353 if (unlikely(reloc->offset > obj->base.size - 4)) {
354 DRM_ERROR("Relocation beyond object bounds: "
355 "obj %p target %d offset %d size %d.\n",
356 obj, reloc->target_handle,
358 (int) obj->base.size);
361 if (unlikely(reloc->offset & 3)) {
362 DRM_ERROR("Relocation not 4-byte aligned: "
363 "obj %p target %d offset %d.\n",
364 obj, reloc->target_handle,
365 (int) reloc->offset);
369 /* and points to somewhere within the target object. */
370 if (unlikely(reloc->delta >= target_obj->size)) {
371 DRM_ERROR("Relocation beyond target object bounds: "
372 "obj %p target %d delta %d size %d.\n",
373 obj, reloc->target_handle,
375 (int) target_obj->size);
379 reloc->delta += target_offset;
380 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
381 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
384 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
385 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
386 kunmap_atomic(vaddr);
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 uint32_t __iomem *reloc_entry;
390 void __iomem *reloc_page;
392 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
396 /* Map the page containing the relocation we're going to perform. */
397 reloc->offset += obj->gtt_offset;
398 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
399 reloc->offset & PAGE_MASK);
400 reloc_entry = (uint32_t __iomem *)
401 (reloc_page + (reloc->offset & ~PAGE_MASK));
402 iowrite32(reloc->delta, reloc_entry);
403 io_mapping_unmap_atomic(reloc_page);
406 /* and update the user's relocation entry */
407 reloc->presumed_offset = target_offset;
413 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
414 struct eb_objects *eb,
415 struct drm_i915_gem_exec_object2 *entry)
417 struct drm_i915_gem_relocation_entry __user *user_relocs;
420 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
421 for (i = 0; i < entry->relocation_count; i++) {
422 struct drm_i915_gem_relocation_entry reloc;
424 if (__copy_from_user_inatomic(&reloc,
429 ret = i915_gem_execbuffer_relocate_entry(obj, eb, entry, &reloc);
433 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
434 &reloc.presumed_offset,
435 sizeof(reloc.presumed_offset)))
443 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
444 struct eb_objects *eb,
445 struct drm_i915_gem_exec_object2 *entry,
446 struct drm_i915_gem_relocation_entry *relocs)
450 for (i = 0; i < entry->relocation_count; i++) {
451 ret = i915_gem_execbuffer_relocate_entry(obj, eb, entry, &relocs[i]);
460 i915_gem_execbuffer_relocate(struct drm_device *dev,
461 struct eb_objects *eb,
462 struct list_head *objects,
463 struct drm_i915_gem_exec_object2 *exec)
465 struct drm_i915_gem_object *obj;
468 list_for_each_entry(obj, objects, exec_list) {
469 obj->base.pending_read_domains = 0;
470 obj->base.pending_write_domain = 0;
471 ret = i915_gem_execbuffer_relocate_object(obj, eb, exec++);
480 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
481 struct drm_file *file,
482 struct list_head *objects,
483 struct drm_i915_gem_exec_object2 *exec)
485 struct drm_i915_gem_object *obj;
486 struct drm_i915_gem_exec_object2 *entry;
488 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
490 /* Attempt to pin all of the buffers into the GTT.
491 * This is done in 3 phases:
493 * 1a. Unbind all objects that do not match the GTT constraints for
494 * the execbuffer (fenceable, mappable, alignment etc).
495 * 1b. Increment pin count for already bound objects.
496 * 2. Bind new objects.
497 * 3. Decrement pin count.
499 * This avoid unnecessary unbinding of later objects in order to makr
500 * room for the earlier objects *unless* we need to defragment.
506 /* Unbind any ill-fitting objects or pin. */
508 list_for_each_entry(obj, objects, exec_list) {
509 bool need_fence, need_mappable;
511 if (!obj->gtt_space) {
517 has_fenced_gpu_access &&
518 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
519 obj->tiling_mode != I915_TILING_NONE;
521 entry->relocation_count ? true : need_fence;
523 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
524 (need_mappable && !obj->map_and_fenceable))
525 ret = i915_gem_object_unbind(obj);
527 ret = i915_gem_object_pin(obj,
536 /* Bind fresh objects */
538 list_for_each_entry(obj, objects, exec_list) {
542 has_fenced_gpu_access &&
543 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
544 obj->tiling_mode != I915_TILING_NONE;
546 if (!obj->gtt_space) {
548 entry->relocation_count ? true : need_fence;
550 ret = i915_gem_object_pin(obj,
557 if (has_fenced_gpu_access) {
559 ret = i915_gem_object_get_fence(obj, ring, 1);
562 } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
563 obj->tiling_mode == I915_TILING_NONE) {
565 ret = i915_gem_object_put_fence(obj);
569 obj->pending_fenced_gpu_access = need_fence;
572 entry->offset = obj->gtt_offset;
576 /* Decrement pin count for bound objects */
577 list_for_each_entry(obj, objects, exec_list) {
579 i915_gem_object_unpin(obj);
582 if (ret != -ENOSPC || retry > 1)
585 /* First attempt, just clear anything that is purgeable.
586 * Second attempt, clear the entire GTT.
588 ret = i915_gem_evict_everything(ring->dev, retry == 0);
596 obj = list_entry(obj->exec_list.prev,
597 struct drm_i915_gem_object,
599 while (objects != &obj->exec_list) {
601 i915_gem_object_unpin(obj);
603 obj = list_entry(obj->exec_list.prev,
604 struct drm_i915_gem_object,
612 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
613 struct drm_file *file,
614 struct intel_ring_buffer *ring,
615 struct list_head *objects,
616 struct eb_objects *eb,
617 struct drm_i915_gem_exec_object2 *exec,
620 struct drm_i915_gem_relocation_entry *reloc;
621 struct drm_i915_gem_object *obj;
624 /* We may process another execbuffer during the unlock... */
625 while (!list_empty(objects)) {
626 obj = list_first_entry(objects,
627 struct drm_i915_gem_object,
629 list_del_init(&obj->exec_list);
630 drm_gem_object_unreference(&obj->base);
633 mutex_unlock(&dev->struct_mutex);
636 for (i = 0; i < count; i++)
637 total += exec[i].relocation_count;
639 reloc = drm_malloc_ab(total, sizeof(*reloc));
641 mutex_lock(&dev->struct_mutex);
646 for (i = 0; i < count; i++) {
647 struct drm_i915_gem_relocation_entry __user *user_relocs;
649 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
651 if (copy_from_user(reloc+total, user_relocs,
652 exec[i].relocation_count * sizeof(*reloc))) {
654 mutex_lock(&dev->struct_mutex);
658 total += exec[i].relocation_count;
661 ret = i915_mutex_lock_interruptible(dev);
663 mutex_lock(&dev->struct_mutex);
667 /* reacquire the objects */
669 for (i = 0; i < count; i++) {
670 struct drm_i915_gem_object *obj;
672 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
675 DRM_ERROR("Invalid object handle %d at index %d\n",
681 list_add_tail(&obj->exec_list, objects);
682 obj->exec_handle = exec[i].handle;
683 eb_add_object(eb, obj);
686 ret = i915_gem_execbuffer_reserve(ring, file, objects, exec);
691 list_for_each_entry(obj, objects, exec_list) {
692 obj->base.pending_read_domains = 0;
693 obj->base.pending_write_domain = 0;
694 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
700 total += exec->relocation_count;
704 /* Leave the user relocations as are, this is the painfully slow path,
705 * and we want to avoid the complication of dropping the lock whilst
706 * having buffers reserved in the aperture and so causing spurious
707 * ENOSPC for random operations.
711 drm_free_large(reloc);
716 i915_gem_execbuffer_flush(struct drm_device *dev,
717 uint32_t invalidate_domains,
718 uint32_t flush_domains,
719 uint32_t flush_rings)
721 drm_i915_private_t *dev_priv = dev->dev_private;
724 if (flush_domains & I915_GEM_DOMAIN_CPU)
725 intel_gtt_chipset_flush();
727 if (flush_domains & I915_GEM_DOMAIN_GTT)
730 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
731 for (i = 0; i < I915_NUM_RINGS; i++)
732 if (flush_rings & (1 << i)) {
733 ret = i915_gem_flush_ring(dev,
746 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
747 struct intel_ring_buffer *to)
749 struct intel_ring_buffer *from = obj->ring;
753 if (from == NULL || to == from)
756 if (INTEL_INFO(obj->base.dev)->gen < 6)
757 return i915_gem_object_wait_rendering(obj, true);
759 idx = intel_ring_sync_index(from, to);
761 seqno = obj->last_rendering_seqno;
762 if (seqno <= from->sync_seqno[idx])
765 if (seqno == from->outstanding_lazy_request) {
766 struct drm_i915_gem_request *request;
768 request = kzalloc(sizeof(*request), GFP_KERNEL);
772 ret = i915_add_request(obj->base.dev, NULL, request, from);
778 seqno = request->seqno;
781 from->sync_seqno[idx] = seqno;
782 return intel_ring_sync(to, from, seqno - 1);
786 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
787 struct list_head *objects)
789 struct drm_i915_gem_object *obj;
790 struct change_domains cd;
793 cd.invalidate_domains = 0;
794 cd.flush_domains = 0;
796 list_for_each_entry(obj, objects, exec_list)
797 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
799 if (cd.invalidate_domains | cd.flush_domains) {
801 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
803 cd.invalidate_domains,
806 ret = i915_gem_execbuffer_flush(ring->dev,
807 cd.invalidate_domains,
814 list_for_each_entry(obj, objects, exec_list) {
815 ret = i915_gem_execbuffer_sync_rings(obj, ring);
824 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
826 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
830 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
835 for (i = 0; i < count; i++) {
836 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
837 int length; /* limited by fault_in_pages_readable() */
839 /* First check for malicious input causing overflow */
840 if (exec[i].relocation_count >
841 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
844 length = exec[i].relocation_count *
845 sizeof(struct drm_i915_gem_relocation_entry);
846 if (!access_ok(VERIFY_READ, ptr, length))
849 /* we may also need to update the presumed offsets */
850 if (!access_ok(VERIFY_WRITE, ptr, length))
853 if (fault_in_pages_readable(ptr, length))
861 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring,
862 struct list_head *objects)
864 struct drm_i915_gem_object *obj;
867 /* Check for any pending flips. As we only maintain a flip queue depth
868 * of 1, we can simply insert a WAIT for the next display flip prior
869 * to executing the batch and avoid stalling the CPU.
872 list_for_each_entry(obj, objects, exec_list) {
873 if (obj->base.write_domain)
874 flips |= atomic_read(&obj->pending_flip);
877 int plane, flip_mask, ret;
879 for (plane = 0; flips >> plane; plane++) {
880 if (((flips >> plane) & 1) == 0)
884 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
886 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
888 ret = intel_ring_begin(ring, 2);
892 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
893 intel_ring_emit(ring, MI_NOOP);
894 intel_ring_advance(ring);
902 i915_gem_execbuffer_move_to_active(struct list_head *objects,
903 struct intel_ring_buffer *ring,
906 struct drm_i915_gem_object *obj;
908 list_for_each_entry(obj, objects, exec_list) {
909 obj->base.read_domains = obj->base.pending_read_domains;
910 obj->base.write_domain = obj->base.pending_write_domain;
911 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
913 i915_gem_object_move_to_active(obj, ring, seqno);
914 if (obj->base.write_domain) {
916 obj->pending_gpu_write = true;
917 list_move_tail(&obj->gpu_write_list,
918 &ring->gpu_write_list);
919 intel_mark_busy(ring->dev, obj);
922 trace_i915_gem_object_change_domain(obj,
923 obj->base.read_domains,
924 obj->base.write_domain);
929 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
930 struct drm_file *file,
931 struct intel_ring_buffer *ring)
933 struct drm_i915_gem_request *request;
937 * Ensure that the commands in the batch buffer are
938 * finished before the interrupt fires.
940 * The sampler always gets flushed on i965 (sigh).
942 invalidate = I915_GEM_DOMAIN_COMMAND;
943 if (INTEL_INFO(dev)->gen >= 4)
944 invalidate |= I915_GEM_DOMAIN_SAMPLER;
945 if (ring->flush(ring, invalidate, 0)) {
946 i915_gem_next_request_seqno(dev, ring);
950 /* Add a breadcrumb for the completion of the batch buffer */
951 request = kzalloc(sizeof(*request), GFP_KERNEL);
952 if (request == NULL || i915_add_request(dev, file, request, ring)) {
953 i915_gem_next_request_seqno(dev, ring);
959 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
960 struct drm_file *file,
961 struct drm_i915_gem_execbuffer2 *args,
962 struct drm_i915_gem_exec_object2 *exec)
964 drm_i915_private_t *dev_priv = dev->dev_private;
965 struct list_head objects;
966 struct eb_objects *eb;
967 struct drm_i915_gem_object *batch_obj;
968 struct drm_clip_rect *cliprects = NULL;
969 struct intel_ring_buffer *ring;
970 u32 exec_start, exec_len;
974 if (!i915_gem_check_execbuffer(args)) {
975 DRM_ERROR("execbuf with invalid offset/length\n");
979 ret = validate_exec_list(exec, args->buffer_count);
984 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
985 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
987 switch (args->flags & I915_EXEC_RING_MASK) {
988 case I915_EXEC_DEFAULT:
989 case I915_EXEC_RENDER:
990 ring = &dev_priv->ring[RCS];
994 DRM_ERROR("execbuf with invalid ring (BSD)\n");
997 ring = &dev_priv->ring[VCS];
1000 if (!HAS_BLT(dev)) {
1001 DRM_ERROR("execbuf with invalid ring (BLT)\n");
1004 ring = &dev_priv->ring[BCS];
1007 DRM_ERROR("execbuf with unknown ring: %d\n",
1008 (int)(args->flags & I915_EXEC_RING_MASK));
1012 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1014 case I915_EXEC_CONSTANTS_REL_GENERAL:
1015 case I915_EXEC_CONSTANTS_ABSOLUTE:
1016 case I915_EXEC_CONSTANTS_REL_SURFACE:
1017 if (ring == &dev_priv->ring[RCS] &&
1018 mode != dev_priv->relative_constants_mode) {
1019 if (INTEL_INFO(dev)->gen < 4)
1022 if (INTEL_INFO(dev)->gen > 5 &&
1023 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1026 ret = intel_ring_begin(ring, 4);
1030 intel_ring_emit(ring, MI_NOOP);
1031 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1032 intel_ring_emit(ring, INSTPM);
1033 intel_ring_emit(ring,
1034 I915_EXEC_CONSTANTS_MASK << 16 | mode);
1035 intel_ring_advance(ring);
1037 dev_priv->relative_constants_mode = mode;
1041 DRM_ERROR("execbuf with unknown constants: %d\n", mode);
1045 if (args->buffer_count < 1) {
1046 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1050 if (args->num_cliprects != 0) {
1051 if (ring != &dev_priv->ring[RCS]) {
1052 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1056 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1058 if (cliprects == NULL) {
1063 if (copy_from_user(cliprects,
1064 (struct drm_clip_rect __user *)(uintptr_t)
1065 args->cliprects_ptr,
1066 sizeof(*cliprects)*args->num_cliprects)) {
1072 ret = i915_mutex_lock_interruptible(dev);
1076 if (dev_priv->mm.suspended) {
1077 mutex_unlock(&dev->struct_mutex);
1082 eb = eb_create(args->buffer_count);
1084 mutex_unlock(&dev->struct_mutex);
1089 /* Look up object handles */
1090 INIT_LIST_HEAD(&objects);
1091 for (i = 0; i < args->buffer_count; i++) {
1092 struct drm_i915_gem_object *obj;
1094 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1097 DRM_ERROR("Invalid object handle %d at index %d\n",
1099 /* prevent error path from reading uninitialized data */
1104 if (!list_empty(&obj->exec_list)) {
1105 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1106 obj, exec[i].handle, i);
1111 list_add_tail(&obj->exec_list, &objects);
1112 obj->exec_handle = exec[i].handle;
1113 eb_add_object(eb, obj);
1116 /* Move the objects en-masse into the GTT, evicting if necessary. */
1117 ret = i915_gem_execbuffer_reserve(ring, file, &objects, exec);
1121 /* The objects are in their final locations, apply the relocations. */
1122 ret = i915_gem_execbuffer_relocate(dev, eb, &objects, exec);
1124 if (ret == -EFAULT) {
1125 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1128 args->buffer_count);
1129 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1135 /* Set the pending read domains for the batch buffer to COMMAND */
1136 batch_obj = list_entry(objects.prev,
1137 struct drm_i915_gem_object,
1139 if (batch_obj->base.pending_write_domain) {
1140 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1144 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1146 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1150 ret = i915_gem_execbuffer_wait_for_flips(ring, &objects);
1154 seqno = i915_gem_next_request_seqno(dev, ring);
1155 for (i = 0; i < I915_NUM_RINGS-1; i++) {
1156 if (seqno < ring->sync_seqno[i]) {
1157 /* The GPU can not handle its semaphore value wrapping,
1158 * so every billion or so execbuffers, we need to stall
1159 * the GPU in order to reset the counters.
1161 ret = i915_gpu_idle(dev);
1165 BUG_ON(ring->sync_seqno[i]);
1169 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1170 exec_len = args->batch_len;
1172 for (i = 0; i < args->num_cliprects; i++) {
1173 ret = i915_emit_box(dev, &cliprects[i],
1174 args->DR1, args->DR4);
1178 ret = ring->dispatch_execbuffer(ring,
1179 exec_start, exec_len);
1184 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1189 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1190 i915_gem_execbuffer_retire_commands(dev, file, ring);
1194 while (!list_empty(&objects)) {
1195 struct drm_i915_gem_object *obj;
1197 obj = list_first_entry(&objects,
1198 struct drm_i915_gem_object,
1200 list_del_init(&obj->exec_list);
1201 drm_gem_object_unreference(&obj->base);
1204 mutex_unlock(&dev->struct_mutex);
1212 * Legacy execbuffer just creates an exec2 list from the original exec object
1213 * list array and passes it to the real function.
1216 i915_gem_execbuffer(struct drm_device *dev, void *data,
1217 struct drm_file *file)
1219 struct drm_i915_gem_execbuffer *args = data;
1220 struct drm_i915_gem_execbuffer2 exec2;
1221 struct drm_i915_gem_exec_object *exec_list = NULL;
1222 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1226 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1227 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1230 if (args->buffer_count < 1) {
1231 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1235 /* Copy in the exec list from userland */
1236 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1237 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1238 if (exec_list == NULL || exec2_list == NULL) {
1239 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1240 args->buffer_count);
1241 drm_free_large(exec_list);
1242 drm_free_large(exec2_list);
1245 ret = copy_from_user(exec_list,
1246 (struct drm_i915_relocation_entry __user *)
1247 (uintptr_t) args->buffers_ptr,
1248 sizeof(*exec_list) * args->buffer_count);
1250 DRM_ERROR("copy %d exec entries failed %d\n",
1251 args->buffer_count, ret);
1252 drm_free_large(exec_list);
1253 drm_free_large(exec2_list);
1257 for (i = 0; i < args->buffer_count; i++) {
1258 exec2_list[i].handle = exec_list[i].handle;
1259 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1260 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1261 exec2_list[i].alignment = exec_list[i].alignment;
1262 exec2_list[i].offset = exec_list[i].offset;
1263 if (INTEL_INFO(dev)->gen < 4)
1264 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1266 exec2_list[i].flags = 0;
1269 exec2.buffers_ptr = args->buffers_ptr;
1270 exec2.buffer_count = args->buffer_count;
1271 exec2.batch_start_offset = args->batch_start_offset;
1272 exec2.batch_len = args->batch_len;
1273 exec2.DR1 = args->DR1;
1274 exec2.DR4 = args->DR4;
1275 exec2.num_cliprects = args->num_cliprects;
1276 exec2.cliprects_ptr = args->cliprects_ptr;
1277 exec2.flags = I915_EXEC_RENDER;
1279 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1281 /* Copy the new buffer offsets back to the user's exec list. */
1282 for (i = 0; i < args->buffer_count; i++)
1283 exec_list[i].offset = exec2_list[i].offset;
1284 /* ... and back out to userspace */
1285 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1286 (uintptr_t) args->buffers_ptr,
1288 sizeof(*exec_list) * args->buffer_count);
1291 DRM_ERROR("failed to copy %d exec entries "
1292 "back to user (%d)\n",
1293 args->buffer_count, ret);
1297 drm_free_large(exec_list);
1298 drm_free_large(exec2_list);
1303 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1304 struct drm_file *file)
1306 struct drm_i915_gem_execbuffer2 *args = data;
1307 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1311 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1312 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1315 if (args->buffer_count < 1) {
1316 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1320 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1321 if (exec2_list == NULL) {
1322 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1323 args->buffer_count);
1326 ret = copy_from_user(exec2_list,
1327 (struct drm_i915_relocation_entry __user *)
1328 (uintptr_t) args->buffers_ptr,
1329 sizeof(*exec2_list) * args->buffer_count);
1331 DRM_ERROR("copy %d exec entries failed %d\n",
1332 args->buffer_count, ret);
1333 drm_free_large(exec2_list);
1337 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1339 /* Copy the new buffer offsets back to the user's exec list. */
1340 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1341 (uintptr_t) args->buffers_ptr,
1343 sizeof(*exec2_list) * args->buffer_count);
1346 DRM_ERROR("failed to copy %d exec entries "
1347 "back to user (%d)\n",
1348 args->buffer_count, ret);
1352 drm_free_large(exec2_list);