drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     int nr_to_scan,
  60                                     gfp_t gfp_mask);
  61
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         dev_priv->mm.object_count++;
  68         dev_priv->mm.object_memory += size;
  69 }
  70
  71 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  72                                      size_t size)
  73 {
  74         dev_priv->mm.object_count--;
  75         dev_priv->mm.object_memory -= size;
  76 }
  77
  78 static int
  79 i915_gem_wait_for_error(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         struct completion *x = &dev_priv->error_completion;
  83         unsigned long flags;
  84         int ret;
  85
  86         if (!atomic_read(&dev_priv->mm.wedged))
  87                 return 0;
  88
  89         ret = wait_for_completion_interruptible(x);
  90         if (ret)
  91                 return ret;
  92
  93         if (atomic_read(&dev_priv->mm.wedged)) {
  94                 /* GPU is hung, bump the completion count to account for
  95                  * the token we just consumed so that we never hit zero and
  96                  * end up waiting upon a subsequent completion event that
  97                  * will never happen.
  98                  */
  99                 spin_lock_irqsave(&x->wait.lock, flags);
 100                 x->done++;
 101                 spin_unlock_irqrestore(&x->wait.lock, flags);
 102         }
 103         return 0;
 104 }
 105
 106 int i915_mutex_lock_interruptible(struct drm_device *dev)
 107 {
 108         int ret;
 109
 110         ret = i915_gem_wait_for_error(dev);
 111         if (ret)
 112                 return ret;
 113
 114         ret = mutex_lock_interruptible(&dev->struct_mutex);
 115         if (ret)
 116                 return ret;
 117
 118         WARN_ON(i915_verify_lists(dev));
 119         return 0;
 120 }
 121
 122 static inline bool
 123 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 124 {
 125         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 126 }
 127
 128 void i915_gem_do_init(struct drm_device *dev,
 129                       unsigned long start,
 130                       unsigned long mappable_end,
 131                       unsigned long end)
 132 {
 133         drm_i915_private_t *dev_priv = dev->dev_private;
 134
 135         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 136
 137         dev_priv->mm.gtt_start = start;
 138         dev_priv->mm.gtt_mappable_end = mappable_end;
 139         dev_priv->mm.gtt_end = end;
 140         dev_priv->mm.gtt_total = end - start;
 141         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 142
 143         /* Take over this portion of the GTT */
 144         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 145 }
 146
 147 int
 148 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 149                     struct drm_file *file)
 150 {
 151         struct drm_i915_gem_init *args = data;
 152
 153         if (args->gtt_start >= args->gtt_end ||
 154             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 155                 return -EINVAL;
 156
 157         mutex_lock(&dev->struct_mutex);
 158         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 159         mutex_unlock(&dev->struct_mutex);
 160
 161         return 0;
 162 }
 163
 164 int
 165 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 166                             struct drm_file *file)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         struct drm_i915_gem_get_aperture *args = data;
 170         struct drm_i915_gem_object *obj;
 171         size_t pinned;
 172
 173         if (!(dev->driver->driver_features & DRIVER_GEM))
 174                 return -ENODEV;
 175
 176         pinned = 0;
 177         mutex_lock(&dev->struct_mutex);
 178         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 179                 pinned += obj->gtt_space->size;
 180         mutex_unlock(&dev->struct_mutex);
 181
 182         args->aper_size = dev_priv->mm.gtt_total;
 183         args->aper_available_size = args->aper_size -pinned;
 184
 185         return 0;
 186 }
 187
 188 static int
 189 i915_gem_create(struct drm_file *file,
 190                 struct drm_device *dev,
 191                 uint64_t size,
 192                 uint32_t *handle_p)
 193 {
 194         struct drm_i915_gem_object *obj;
 195         int ret;
 196         u32 handle;
 197
 198         size = roundup(size, PAGE_SIZE);
 199
 200         /* Allocate the new object */
 201         obj = i915_gem_alloc_object(dev, size);
 202         if (obj == NULL)
 203                 return -ENOMEM;
 204
 205         ret = drm_gem_handle_create(file, &obj->base, &handle);
 206         if (ret) {
 207                 drm_gem_object_release(&obj->base);
 208                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 209                 kfree(obj);
 210                 return ret;
 211         }
 212
 213         /* drop reference from allocate - handle holds it now */
 214         drm_gem_object_unreference(&obj->base);
 215         trace_i915_gem_object_create(obj);
 216
 217         *handle_p = handle;
 218         return 0;
 219 }
 220
 221 int
 222 i915_gem_dumb_create(struct drm_file *file,
 223                      struct drm_device *dev,
 224                      struct drm_mode_create_dumb *args)
 225 {
 226         /* have to work out size/pitch and return them */
 227         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 228         args->size = args->pitch * args->height;
 229         return i915_gem_create(file, dev,
 230                                args->size, &args->handle);
 231 }
 232
 233 int i915_gem_dumb_destroy(struct drm_file *file,
 234                           struct drm_device *dev,
 235                           uint32_t handle)
 236 {
 237         return drm_gem_handle_delete(file, handle);
 238 }
 239
 240 /**
 241  * Creates a new mm object and returns a handle to it.
 242  */
 243 int
 244 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 245                       struct drm_file *file)
 246 {
 247         struct drm_i915_gem_create *args = data;
 248         return i915_gem_create(file, dev,
 249                                args->size, &args->handle);
 250 }
 251
 252 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 253 {
 254         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 255
 256         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 257                 obj->tiling_mode != I915_TILING_NONE;
 258 }
 259
 260 static inline void
 261 slow_shmem_copy(struct page *dst_page,
 262                 int dst_offset,
 263                 struct page *src_page,
 264                 int src_offset,
 265                 int length)
 266 {
 267         char *dst_vaddr, *src_vaddr;
 268
 269         dst_vaddr = kmap(dst_page);
 270         src_vaddr = kmap(src_page);
 271
 272         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 273
 274         kunmap(src_page);
 275         kunmap(dst_page);
 276 }
 277
 278 static inline void
 279 slow_shmem_bit17_copy(struct page *gpu_page,
 280                       int gpu_offset,
 281                       struct page *cpu_page,
 282                       int cpu_offset,
 283                       int length,
 284                       int is_read)
 285 {
 286         char *gpu_vaddr, *cpu_vaddr;
 287
 288         /* Use the unswizzled path if this page isn't affected. */
 289         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 290                 if (is_read)
 291                         return slow_shmem_copy(cpu_page, cpu_offset,
 292                                                gpu_page, gpu_offset, length);
 293                 else
 294                         return slow_shmem_copy(gpu_page, gpu_offset,
 295                                                cpu_page, cpu_offset, length);
 296         }
 297
 298         gpu_vaddr = kmap(gpu_page);
 299         cpu_vaddr = kmap(cpu_page);
 300
 301         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 302          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 303          */
 304         while (length > 0) {
 305                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 306                 int this_length = min(cacheline_end - gpu_offset, length);
 307                 int swizzled_gpu_offset = gpu_offset ^ 64;
 308
 309                 if (is_read) {
 310                         memcpy(cpu_vaddr + cpu_offset,
 311                                gpu_vaddr + swizzled_gpu_offset,
 312                                this_length);
 313                 } else {
 314                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 315                                cpu_vaddr + cpu_offset,
 316                                this_length);
 317                 }
 318                 cpu_offset += this_length;
 319                 gpu_offset += this_length;
 320                 length -= this_length;
 321         }
 322
 323         kunmap(cpu_page);
 324         kunmap(gpu_page);
 325 }
 326
 327 /**
 328  * This is the fast shmem pread path, which attempts to copy_from_user directly
 329  * from the backing pages of the object to the user's address space.  On a
 330  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 331  */
 332 static int
 333 i915_gem_shmem_pread_fast(struct drm_device *dev,
 334                           struct drm_i915_gem_object *obj,
 335                           struct drm_i915_gem_pread *args,
 336                           struct drm_file *file)
 337 {
 338         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 339         ssize_t remain;
 340         loff_t offset;
 341         char __user *user_data;
 342         int page_offset, page_length;
 343
 344         user_data = (char __user *) (uintptr_t) args->data_ptr;
 345         remain = args->size;
 346
 347         offset = args->offset;
 348
 349         while (remain > 0) {
 350                 struct page *page;
 351                 char *vaddr;
 352                 int ret;
 353
 354                 /* Operation in this page
 355                  *
 356                  * page_offset = offset within page
 357                  * page_length = bytes to copy for this page
 358                  */
 359                 page_offset = offset & (PAGE_SIZE-1);
 360                 page_length = remain;
 361                 if ((page_offset + remain) > PAGE_SIZE)
 362                         page_length = PAGE_SIZE - page_offset;
 363
 364                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 365                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 366                 if (IS_ERR(page))
 367                         return PTR_ERR(page);
 368
 369                 vaddr = kmap_atomic(page);
 370                 ret = __copy_to_user_inatomic(user_data,
 371                                               vaddr + page_offset,
 372                                               page_length);
 373                 kunmap_atomic(vaddr);
 374
 375                 mark_page_accessed(page);
 376                 page_cache_release(page);
 377                 if (ret)
 378                         return -EFAULT;
 379
 380                 remain -= page_length;
 381                 user_data += page_length;
 382                 offset += page_length;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * This is the fallback shmem pread path, which allocates temporary storage
 390  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 391  * can copy out of the object's backing pages while holding the struct mutex
 392  * and not take page faults.
 393  */
 394 static int
 395 i915_gem_shmem_pread_slow(struct drm_device *dev,
 396                           struct drm_i915_gem_object *obj,
 397                           struct drm_i915_gem_pread *args,
 398                           struct drm_file *file)
 399 {
 400         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 401         struct mm_struct *mm = current->mm;
 402         struct page **user_pages;
 403         ssize_t remain;
 404         loff_t offset, pinned_pages, i;
 405         loff_t first_data_page, last_data_page, num_pages;
 406         int shmem_page_offset;
 407         int data_page_index, data_page_offset;
 408         int page_length;
 409         int ret;
 410         uint64_t data_ptr = args->data_ptr;
 411         int do_bit17_swizzling;
 412
 413         remain = args->size;
 414
 415         /* Pin the user pages containing the data.  We can't fault while
 416          * holding the struct mutex, yet we want to hold it while
 417          * dereferencing the user data.
 418          */
 419         first_data_page = data_ptr / PAGE_SIZE;
 420         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 421         num_pages = last_data_page - first_data_page + 1;
 422
 423         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 424         if (user_pages == NULL)
 425                 return -ENOMEM;
 426
 427         mutex_unlock(&dev->struct_mutex);
 428         down_read(&mm->mmap_sem);
 429         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 430                                       num_pages, 1, 0, user_pages, NULL);
 431         up_read(&mm->mmap_sem);
 432         mutex_lock(&dev->struct_mutex);
 433         if (pinned_pages < num_pages) {
 434                 ret = -EFAULT;
 435                 goto out;
 436         }
 437
 438         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 439                                                         args->offset,
 440                                                         args->size);
 441         if (ret)
 442                 goto out;
 443
 444         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 445
 446         offset = args->offset;
 447
 448         while (remain > 0) {
 449                 struct page *page;
 450
 451                 /* Operation in this page
 452                  *
 453                  * shmem_page_offset = offset within page in shmem file
 454                  * data_page_index = page number in get_user_pages return
 455                  * data_page_offset = offset with data_page_index page.
 456                  * page_length = bytes to copy for this page
 457                  */
 458                 shmem_page_offset = offset & ~PAGE_MASK;
 459                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 460                 data_page_offset = data_ptr & ~PAGE_MASK;
 461
 462                 page_length = remain;
 463                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - shmem_page_offset;
 465                 if ((data_page_offset + page_length) > PAGE_SIZE)
 466                         page_length = PAGE_SIZE - data_page_offset;
 467
 468                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 469                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 470                 if (IS_ERR(page))
 471                         return PTR_ERR(page);
 472
 473                 if (do_bit17_swizzling) {
 474                         slow_shmem_bit17_copy(page,
 475                                               shmem_page_offset,
 476                                               user_pages[data_page_index],
 477                                               data_page_offset,
 478                                               page_length,
 479                                               1);
 480                 } else {
 481                         slow_shmem_copy(user_pages[data_page_index],
 482                                         data_page_offset,
 483                                         page,
 484                                         shmem_page_offset,
 485                                         page_length);
 486                 }
 487
 488                 mark_page_accessed(page);
 489                 page_cache_release(page);
 490
 491                 remain -= page_length;
 492                 data_ptr += page_length;
 493                 offset += page_length;
 494         }
 495
 496 out:
 497         for (i = 0; i < pinned_pages; i++) {
 498                 SetPageDirty(user_pages[i]);
 499                 mark_page_accessed(user_pages[i]);
 500                 page_cache_release(user_pages[i]);
 501         }
 502         drm_free_large(user_pages);
 503
 504         return ret;
 505 }
 506
 507 /**
 508  * Reads data from the object referenced by handle.
 509  *
 510  * On error, the contents of *data are undefined.
 511  */
 512 int
 513 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 514                      struct drm_file *file)
 515 {
 516         struct drm_i915_gem_pread *args = data;
 517         struct drm_i915_gem_object *obj;
 518         int ret = 0;
 519
 520         if (args->size == 0)
 521                 return 0;
 522
 523         if (!access_ok(VERIFY_WRITE,
 524                        (char __user *)(uintptr_t)args->data_ptr,
 525                        args->size))
 526                 return -EFAULT;
 527
 528         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 529                                        args->size);
 530         if (ret)
 531                 return -EFAULT;
 532
 533         ret = i915_mutex_lock_interruptible(dev);
 534         if (ret)
 535                 return ret;
 536
 537         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 538         if (&obj->base == NULL) {
 539                 ret = -ENOENT;
 540                 goto unlock;
 541         }
 542
 543         /* Bounds check source.  */
 544         if (args->offset > obj->base.size ||
 545             args->size > obj->base.size - args->offset) {
 546                 ret = -EINVAL;
 547                 goto out;
 548         }
 549
 550         trace_i915_gem_object_pread(obj, args->offset, args->size);
 551
 552         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 553                                                         args->offset,
 554                                                         args->size);
 555         if (ret)
 556                 goto out;
 557
 558         ret = -EFAULT;
 559         if (!i915_gem_object_needs_bit17_swizzle(obj))
 560                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 561         if (ret == -EFAULT)
 562                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 563
 564 out:
 565         drm_gem_object_unreference(&obj->base);
 566 unlock:
 567         mutex_unlock(&dev->struct_mutex);
 568         return ret;
 569 }
 570
 571 /* This is the fast write path which cannot handle
 572  * page faults in the source data
 573  */
 574
 575 static inline int
 576 fast_user_write(struct io_mapping *mapping,
 577                 loff_t page_base, int page_offset,
 578                 char __user *user_data,
 579                 int length)
 580 {
 581         char *vaddr_atomic;
 582         unsigned long unwritten;
 583
 584         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 585         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 586                                                       user_data, length);
 587         io_mapping_unmap_atomic(vaddr_atomic);
 588         return unwritten;
 589 }
 590
 591 /* Here's the write path which can sleep for
 592  * page faults
 593  */
 594
 595 static inline void
 596 slow_kernel_write(struct io_mapping *mapping,
 597                   loff_t gtt_base, int gtt_offset,
 598                   struct page *user_page, int user_offset,
 599                   int length)
 600 {
 601         char __iomem *dst_vaddr;
 602         char *src_vaddr;
 603
 604         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 605         src_vaddr = kmap(user_page);
 606
 607         memcpy_toio(dst_vaddr + gtt_offset,
 608                     src_vaddr + user_offset,
 609                     length);
 610
 611         kunmap(user_page);
 612         io_mapping_unmap(dst_vaddr);
 613 }
 614
 615 /**
 616  * This is the fast pwrite path, where we copy the data directly from the
 617  * user into the GTT, uncached.
 618  */
 619 static int
 620 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 621                          struct drm_i915_gem_object *obj,
 622                          struct drm_i915_gem_pwrite *args,
 623                          struct drm_file *file)
 624 {
 625         drm_i915_private_t *dev_priv = dev->dev_private;
 626         ssize_t remain;
 627         loff_t offset, page_base;
 628         char __user *user_data;
 629         int page_offset, page_length;
 630
 631         user_data = (char __user *) (uintptr_t) args->data_ptr;
 632         remain = args->size;
 633
 634         offset = obj->gtt_offset + args->offset;
 635
 636         while (remain > 0) {
 637                 /* Operation in this page
 638                  *
 639                  * page_base = page offset within aperture
 640                  * page_offset = offset within page
 641                  * page_length = bytes to copy for this page
 642                  */
 643                 page_base = (offset & ~(PAGE_SIZE-1));
 644                 page_offset = offset & (PAGE_SIZE-1);
 645                 page_length = remain;
 646                 if ((page_offset + remain) > PAGE_SIZE)
 647                         page_length = PAGE_SIZE - page_offset;
 648
 649                 /* If we get a fault while copying data, then (presumably) our
 650                  * source page isn't available.  Return the error and we'll
 651                  * retry in the slow path.
 652                  */
 653                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 654                                     page_offset, user_data, page_length))
 655
 656                         return -EFAULT;
 657
 658                 remain -= page_length;
 659                 user_data += page_length;
 660                 offset += page_length;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 668  * the memory and maps it using kmap_atomic for copying.
 669  *
 670  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 671  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 672  */
 673 static int
 674 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 675                          struct drm_i915_gem_object *obj,
 676                          struct drm_i915_gem_pwrite *args,
 677                          struct drm_file *file)
 678 {
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         ssize_t remain;
 681         loff_t gtt_page_base, offset;
 682         loff_t first_data_page, last_data_page, num_pages;
 683         loff_t pinned_pages, i;
 684         struct page **user_pages;
 685         struct mm_struct *mm = current->mm;
 686         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 687         int ret;
 688         uint64_t data_ptr = args->data_ptr;
 689
 690         remain = args->size;
 691
 692         /* Pin the user pages containing the data.  We can't fault while
 693          * holding the struct mutex, and all of the pwrite implementations
 694          * want to hold it while dereferencing the user data.
 695          */
 696         first_data_page = data_ptr / PAGE_SIZE;
 697         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 698         num_pages = last_data_page - first_data_page + 1;
 699
 700         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 701         if (user_pages == NULL)
 702                 return -ENOMEM;
 703
 704         mutex_unlock(&dev->struct_mutex);
 705         down_read(&mm->mmap_sem);
 706         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 707                                       num_pages, 0, 0, user_pages, NULL);
 708         up_read(&mm->mmap_sem);
 709         mutex_lock(&dev->struct_mutex);
 710         if (pinned_pages < num_pages) {
 711                 ret = -EFAULT;
 712                 goto out_unpin_pages;
 713         }
 714
 715         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 716         if (ret)
 717                 goto out_unpin_pages;
 718
 719         ret = i915_gem_object_put_fence(obj);
 720         if (ret)
 721                 goto out_unpin_pages;
 722
 723         offset = obj->gtt_offset + args->offset;
 724
 725         while (remain > 0) {
 726                 /* Operation in this page
 727                  *
 728                  * gtt_page_base = page offset within aperture
 729                  * gtt_page_offset = offset within page in aperture
 730                  * data_page_index = page number in get_user_pages return
 731                  * data_page_offset = offset with data_page_index page.
 732                  * page_length = bytes to copy for this page
 733                  */
 734                 gtt_page_base = offset & PAGE_MASK;
 735                 gtt_page_offset = offset & ~PAGE_MASK;
 736                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 737                 data_page_offset = data_ptr & ~PAGE_MASK;
 738
 739                 page_length = remain;
 740                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 741                         page_length = PAGE_SIZE - gtt_page_offset;
 742                 if ((data_page_offset + page_length) > PAGE_SIZE)
 743                         page_length = PAGE_SIZE - data_page_offset;
 744
 745                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 746                                   gtt_page_base, gtt_page_offset,
 747                                   user_pages[data_page_index],
 748                                   data_page_offset,
 749                                   page_length);
 750
 751                 remain -= page_length;
 752                 offset += page_length;
 753                 data_ptr += page_length;
 754         }
 755
 756 out_unpin_pages:
 757         for (i = 0; i < pinned_pages; i++)
 758                 page_cache_release(user_pages[i]);
 759         drm_free_large(user_pages);
 760
 761         return ret;
 762 }
 763
 764 /**
 765  * This is the fast shmem pwrite path, which attempts to directly
 766  * copy_from_user into the kmapped pages backing the object.
 767  */
 768 static int
 769 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 770                            struct drm_i915_gem_object *obj,
 771                            struct drm_i915_gem_pwrite *args,
 772                            struct drm_file *file)
 773 {
 774         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 775         ssize_t remain;
 776         loff_t offset;
 777         char __user *user_data;
 778         int page_offset, page_length;
 779
 780         user_data = (char __user *) (uintptr_t) args->data_ptr;
 781         remain = args->size;
 782
 783         offset = args->offset;
 784         obj->dirty = 1;
 785
 786         while (remain > 0) {
 787                 struct page *page;
 788                 char *vaddr;
 789                 int ret;
 790
 791                 /* Operation in this page
 792                  *
 793                  * page_offset = offset within page
 794                  * page_length = bytes to copy for this page
 795                  */
 796                 page_offset = offset & (PAGE_SIZE-1);
 797                 page_length = remain;
 798                 if ((page_offset + remain) > PAGE_SIZE)
 799                         page_length = PAGE_SIZE - page_offset;
 800
 801                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 802                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 803                 if (IS_ERR(page))
 804                         return PTR_ERR(page);
 805
 806                 vaddr = kmap_atomic(page, KM_USER0);
 807                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 808                                                 user_data,
 809                                                 page_length);
 810                 kunmap_atomic(vaddr, KM_USER0);
 811
 812                 set_page_dirty(page);
 813                 mark_page_accessed(page);
 814                 page_cache_release(page);
 815
 816                 /* If we get a fault while copying data, then (presumably) our
 817                  * source page isn't available.  Return the error and we'll
 818                  * retry in the slow path.
 819                  */
 820                 if (ret)
 821                         return -EFAULT;
 822
 823                 remain -= page_length;
 824                 user_data += page_length;
 825                 offset += page_length;
 826         }
 827
 828         return 0;
 829 }
 830
 831 /**
 832  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 833  * the memory and maps it using kmap_atomic for copying.
 834  *
 835  * This avoids taking mmap_sem for faulting on the user's address while the
 836  * struct_mutex is held.
 837  */
 838 static int
 839 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 840                            struct drm_i915_gem_object *obj,
 841                            struct drm_i915_gem_pwrite *args,
 842                            struct drm_file *file)
 843 {
 844         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 845         struct mm_struct *mm = current->mm;
 846         struct page **user_pages;
 847         ssize_t remain;
 848         loff_t offset, pinned_pages, i;
 849         loff_t first_data_page, last_data_page, num_pages;
 850         int shmem_page_offset;
 851         int data_page_index,  data_page_offset;
 852         int page_length;
 853         int ret;
 854         uint64_t data_ptr = args->data_ptr;
 855         int do_bit17_swizzling;
 856
 857         remain = args->size;
 858
 859         /* Pin the user pages containing the data.  We can't fault while
 860          * holding the struct mutex, and all of the pwrite implementations
 861          * want to hold it while dereferencing the user data.
 862          */
 863         first_data_page = data_ptr / PAGE_SIZE;
 864         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 865         num_pages = last_data_page - first_data_page + 1;
 866
 867         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 868         if (user_pages == NULL)
 869                 return -ENOMEM;
 870
 871         mutex_unlock(&dev->struct_mutex);
 872         down_read(&mm->mmap_sem);
 873         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 874                                       num_pages, 0, 0, user_pages, NULL);
 875         up_read(&mm->mmap_sem);
 876         mutex_lock(&dev->struct_mutex);
 877         if (pinned_pages < num_pages) {
 878                 ret = -EFAULT;
 879                 goto out;
 880         }
 881
 882         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 883         if (ret)
 884                 goto out;
 885
 886         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 887
 888         offset = args->offset;
 889         obj->dirty = 1;
 890
 891         while (remain > 0) {
 892                 struct page *page;
 893
 894                 /* Operation in this page
 895                  *
 896                  * shmem_page_offset = offset within page in shmem file
 897                  * data_page_index = page number in get_user_pages return
 898                  * data_page_offset = offset with data_page_index page.
 899                  * page_length = bytes to copy for this page
 900                  */
 901                 shmem_page_offset = offset & ~PAGE_MASK;
 902                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 903                 data_page_offset = data_ptr & ~PAGE_MASK;
 904
 905                 page_length = remain;
 906                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 907                         page_length = PAGE_SIZE - shmem_page_offset;
 908                 if ((data_page_offset + page_length) > PAGE_SIZE)
 909                         page_length = PAGE_SIZE - data_page_offset;
 910
 911                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 912                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 913                 if (IS_ERR(page)) {
 914                         ret = PTR_ERR(page);
 915                         goto out;
 916                 }
 917
 918                 if (do_bit17_swizzling) {
 919                         slow_shmem_bit17_copy(page,
 920                                               shmem_page_offset,
 921                                               user_pages[data_page_index],
 922                                               data_page_offset,
 923                                               page_length,
 924                                               0);
 925                 } else {
 926                         slow_shmem_copy(page,
 927                                         shmem_page_offset,
 928                                         user_pages[data_page_index],
 929                                         data_page_offset,
 930                                         page_length);
 931                 }
 932
 933                 set_page_dirty(page);
 934                 mark_page_accessed(page);
 935                 page_cache_release(page);
 936
 937                 remain -= page_length;
 938                 data_ptr += page_length;
 939                 offset += page_length;
 940         }
 941
 942 out:
 943         for (i = 0; i < pinned_pages; i++)
 944                 page_cache_release(user_pages[i]);
 945         drm_free_large(user_pages);
 946
 947         return ret;
 948 }
 949
 950 /**
 951  * Writes data to the object referenced by handle.
 952  *
 953  * On error, the contents of the buffer that were to be modified are undefined.
 954  */
 955 int
 956 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 957                       struct drm_file *file)
 958 {
 959         struct drm_i915_gem_pwrite *args = data;
 960         struct drm_i915_gem_object *obj;
 961         int ret;
 962
 963         if (args->size == 0)
 964                 return 0;
 965
 966         if (!access_ok(VERIFY_READ,
 967                        (char __user *)(uintptr_t)args->data_ptr,
 968                        args->size))
 969                 return -EFAULT;
 970
 971         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 972                                       args->size);
 973         if (ret)
 974                 return -EFAULT;
 975
 976         ret = i915_mutex_lock_interruptible(dev);
 977         if (ret)
 978                 return ret;
 979
 980         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 981         if (&obj->base == NULL) {
 982                 ret = -ENOENT;
 983                 goto unlock;
 984         }
 985
 986         /* Bounds check destination. */
 987         if (args->offset > obj->base.size ||
 988             args->size > obj->base.size - args->offset) {
 989                 ret = -EINVAL;
 990                 goto out;
 991         }
 992
 993         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 994
 995         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 996          * it would end up going through the fenced access, and we'll get
 997          * different detiling behavior between reading and writing.
 998          * pread/pwrite currently are reading and writing from the CPU
 999          * perspective, requiring manual detiling by the client.
1000          */
1001         if (obj->phys_obj)
1002                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1003         else if (obj->gtt_space &&
1004                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1005                 ret = i915_gem_object_pin(obj, 0, true);
1006                 if (ret)
1007                         goto out;
1008
1009                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1010                 if (ret)
1011                         goto out_unpin;
1012
1013                 ret = i915_gem_object_put_fence(obj);
1014                 if (ret)
1015                         goto out_unpin;
1016
1017                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1018                 if (ret == -EFAULT)
1019                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1020
1021 out_unpin:
1022                 i915_gem_object_unpin(obj);
1023         } else {
1024                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1025                 if (ret)
1026                         goto out;
1027
1028                 ret = -EFAULT;
1029                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1030                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1031                 if (ret == -EFAULT)
1032                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1033         }
1034
1035 out:
1036         drm_gem_object_unreference(&obj->base);
1037 unlock:
1038         mutex_unlock(&dev->struct_mutex);
1039         return ret;
1040 }
1041
1042 /**
1043  * Called when user space prepares to use an object with the CPU, either
1044  * through the mmap ioctl's mapping or a GTT mapping.
1045  */
1046 int
1047 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1048                           struct drm_file *file)
1049 {
1050         struct drm_i915_gem_set_domain *args = data;
1051         struct drm_i915_gem_object *obj;
1052         uint32_t read_domains = args->read_domains;
1053         uint32_t write_domain = args->write_domain;
1054         int ret;
1055
1056         if (!(dev->driver->driver_features & DRIVER_GEM))
1057                 return -ENODEV;
1058
1059         /* Only handle setting domains to types used by the CPU. */
1060         if (write_domain & I915_GEM_GPU_DOMAINS)
1061                 return -EINVAL;
1062
1063         if (read_domains & I915_GEM_GPU_DOMAINS)
1064                 return -EINVAL;
1065
1066         /* Having something in the write domain implies it's in the read
1067          * domain, and only that read domain.  Enforce that in the request.
1068          */
1069         if (write_domain != 0 && read_domains != write_domain)
1070                 return -EINVAL;
1071
1072         ret = i915_mutex_lock_interruptible(dev);
1073         if (ret)
1074                 return ret;
1075
1076         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1077         if (&obj->base == NULL) {
1078                 ret = -ENOENT;
1079                 goto unlock;
1080         }
1081
1082         if (read_domains & I915_GEM_DOMAIN_GTT) {
1083                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1084
1085                 /* Silently promote "you're not bound, there was nothing to do"
1086                  * to success, since the client was just asking us to
1087                  * make sure everything was done.
1088                  */
1089                 if (ret == -EINVAL)
1090                         ret = 0;
1091         } else {
1092                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1093         }
1094
1095         drm_gem_object_unreference(&obj->base);
1096 unlock:
1097         mutex_unlock(&dev->struct_mutex);
1098         return ret;
1099 }
1100
1101 /**
1102  * Called when user space has done writes to this buffer
1103  */
1104 int
1105 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1106                          struct drm_file *file)
1107 {
1108         struct drm_i915_gem_sw_finish *args = data;
1109         struct drm_i915_gem_object *obj;
1110         int ret = 0;
1111
1112         if (!(dev->driver->driver_features & DRIVER_GEM))
1113                 return -ENODEV;
1114
1115         ret = i915_mutex_lock_interruptible(dev);
1116         if (ret)
1117                 return ret;
1118
1119         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1120         if (&obj->base == NULL) {
1121                 ret = -ENOENT;
1122                 goto unlock;
1123         }
1124
1125         /* Pinned buffers may be scanout, so flush the cache */
1126         if (obj->pin_count)
1127                 i915_gem_object_flush_cpu_write_domain(obj);
1128
1129         drm_gem_object_unreference(&obj->base);
1130 unlock:
1131         mutex_unlock(&dev->struct_mutex);
1132         return ret;
1133 }
1134
1135 /**
1136  * Maps the contents of an object, returning the address it is mapped
1137  * into.
1138  *
1139  * While the mapping holds a reference on the contents of the object, it doesn't
1140  * imply a ref on the object itself.
1141  */
1142 int
1143 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1144                     struct drm_file *file)
1145 {
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         struct drm_i915_gem_mmap *args = data;
1148         struct drm_gem_object *obj;
1149         unsigned long addr;
1150
1151         if (!(dev->driver->driver_features & DRIVER_GEM))
1152                 return -ENODEV;
1153
1154         obj = drm_gem_object_lookup(dev, file, args->handle);
1155         if (obj == NULL)
1156                 return -ENOENT;
1157
1158         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1159                 drm_gem_object_unreference_unlocked(obj);
1160                 return -E2BIG;
1161         }
1162
1163         down_write(&current->mm->mmap_sem);
1164         addr = do_mmap(obj->filp, 0, args->size,
1165                        PROT_READ | PROT_WRITE, MAP_SHARED,
1166                        args->offset);
1167         up_write(&current->mm->mmap_sem);
1168         drm_gem_object_unreference_unlocked(obj);
1169         if (IS_ERR((void *)addr))
1170                 return addr;
1171
1172         args->addr_ptr = (uint64_t) addr;
1173
1174         return 0;
1175 }
1176
1177 /**
1178  * i915_gem_fault - fault a page into the GTT
1179  * vma: VMA in question
1180  * vmf: fault info
1181  *
1182  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1183  * from userspace.  The fault handler takes care of binding the object to
1184  * the GTT (if needed), allocating and programming a fence register (again,
1185  * only if needed based on whether the old reg is still valid or the object
1186  * is tiled) and inserting a new PTE into the faulting process.
1187  *
1188  * Note that the faulting process may involve evicting existing objects
1189  * from the GTT and/or fence registers to make room.  So performance may
1190  * suffer if the GTT working set is large or there are few fence registers
1191  * left.
1192  */
1193 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1194 {
1195         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1196         struct drm_device *dev = obj->base.dev;
1197         drm_i915_private_t *dev_priv = dev->dev_private;
1198         pgoff_t page_offset;
1199         unsigned long pfn;
1200         int ret = 0;
1201         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1202
1203         /* We don't use vmf->pgoff since that has the fake offset */
1204         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1205                 PAGE_SHIFT;
1206
1207         ret = i915_mutex_lock_interruptible(dev);
1208         if (ret)
1209                 goto out;
1210
1211         trace_i915_gem_object_fault(obj, page_offset, true, write);
1212
1213         /* Now bind it into the GTT if needed */
1214         if (!obj->map_and_fenceable) {
1215                 ret = i915_gem_object_unbind(obj);
1216                 if (ret)
1217                         goto unlock;
1218         }
1219         if (!obj->gtt_space) {
1220                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1221                 if (ret)
1222                         goto unlock;
1223         }
1224
1225         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1226         if (ret)
1227                 goto unlock;
1228
1229         if (obj->tiling_mode == I915_TILING_NONE)
1230                 ret = i915_gem_object_put_fence(obj);
1231         else
1232                 ret = i915_gem_object_get_fence(obj, NULL);
1233         if (ret)
1234                 goto unlock;
1235
1236         if (i915_gem_object_is_inactive(obj))
1237                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1238
1239         obj->fault_mappable = true;
1240
1241         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1242                 page_offset;
1243
1244         /* Finally, remap it using the new GTT offset */
1245         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1246 unlock:
1247         mutex_unlock(&dev->struct_mutex);
1248 out:
1249         switch (ret) {
1250         case -EIO:
1251         case -EAGAIN:
1252                 /* Give the error handler a chance to run and move the
1253                  * objects off the GPU active list. Next time we service the
1254                  * fault, we should be able to transition the page into the
1255                  * GTT without touching the GPU (and so avoid further
1256                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1257                  * with coherency, just lost writes.
1258                  */
1259                 set_need_resched();
1260         case 0:
1261         case -ERESTARTSYS:
1262         case -EINTR:
1263                 return VM_FAULT_NOPAGE;
1264         case -ENOMEM:
1265                 return VM_FAULT_OOM;
1266         default:
1267                 return VM_FAULT_SIGBUS;
1268         }
1269 }
1270
1271 /**
1272  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1273  * @obj: obj in question
1274  *
1275  * GEM memory mapping works by handing back to userspace a fake mmap offset
1276  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1277  * up the object based on the offset and sets up the various memory mapping
1278  * structures.
1279  *
1280  * This routine allocates and attaches a fake offset for @obj.
1281  */
1282 static int
1283 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1284 {
1285         struct drm_device *dev = obj->base.dev;
1286         struct drm_gem_mm *mm = dev->mm_private;
1287         struct drm_map_list *list;
1288         struct drm_local_map *map;
1289         int ret = 0;
1290
1291         /* Set the object up for mmap'ing */
1292         list = &obj->base.map_list;
1293         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1294         if (!list->map)
1295                 return -ENOMEM;
1296
1297         map = list->map;
1298         map->type = _DRM_GEM;
1299         map->size = obj->base.size;
1300         map->handle = obj;
1301
1302         /* Get a DRM GEM mmap offset allocated... */
1303         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1304                                                     obj->base.size / PAGE_SIZE,
1305                                                     0, 0);
1306         if (!list->file_offset_node) {
1307                 DRM_ERROR("failed to allocate offset for bo %d\n",
1308                           obj->base.name);
1309                 ret = -ENOSPC;
1310                 goto out_free_list;
1311         }
1312
1313         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1314                                                   obj->base.size / PAGE_SIZE,
1315                                                   0);
1316         if (!list->file_offset_node) {
1317                 ret = -ENOMEM;
1318                 goto out_free_list;
1319         }
1320
1321         list->hash.key = list->file_offset_node->start;
1322         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1323         if (ret) {
1324                 DRM_ERROR("failed to add to map hash\n");
1325                 goto out_free_mm;
1326         }
1327
1328         return 0;
1329
1330 out_free_mm:
1331         drm_mm_put_block(list->file_offset_node);
1332 out_free_list:
1333         kfree(list->map);
1334         list->map = NULL;
1335
1336         return ret;
1337 }
1338
1339 /**
1340  * i915_gem_release_mmap - remove physical page mappings
1341  * @obj: obj in question
1342  *
1343  * Preserve the reservation of the mmapping with the DRM core code, but
1344  * relinquish ownership of the pages back to the system.
1345  *
1346  * It is vital that we remove the page mapping if we have mapped a tiled
1347  * object through the GTT and then lose the fence register due to
1348  * resource pressure. Similarly if the object has been moved out of the
1349  * aperture, than pages mapped into userspace must be revoked. Removing the
1350  * mapping will then trigger a page fault on the next user access, allowing
1351  * fixup by i915_gem_fault().
1352  */
1353 void
1354 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1355 {
1356         if (!obj->fault_mappable)
1357                 return;
1358
1359         if (obj->base.dev->dev_mapping)
1360                 unmap_mapping_range(obj->base.dev->dev_mapping,
1361                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1362                                     obj->base.size, 1);
1363
1364         obj->fault_mappable = false;
1365 }
1366
1367 static void
1368 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1369 {
1370         struct drm_device *dev = obj->base.dev;
1371         struct drm_gem_mm *mm = dev->mm_private;
1372         struct drm_map_list *list = &obj->base.map_list;
1373
1374         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1375         drm_mm_put_block(list->file_offset_node);
1376         kfree(list->map);
1377         list->map = NULL;
1378 }
1379
1380 static uint32_t
1381 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1382 {
1383         struct drm_device *dev = obj->base.dev;
1384         uint32_t size;
1385
1386         if (INTEL_INFO(dev)->gen >= 4 ||
1387             obj->tiling_mode == I915_TILING_NONE)
1388                 return obj->base.size;
1389
1390         /* Previous chips need a power-of-two fence region when tiling */
1391         if (INTEL_INFO(dev)->gen == 3)
1392                 size = 1024*1024;
1393         else
1394                 size = 512*1024;
1395
1396         while (size < obj->base.size)
1397                 size <<= 1;
1398
1399         return size;
1400 }
1401
1402 /**
1403  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1404  * @obj: object to check
1405  *
1406  * Return the required GTT alignment for an object, taking into account
1407  * potential fence register mapping.
1408  */
1409 static uint32_t
1410 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1411 {
1412         struct drm_device *dev = obj->base.dev;
1413
1414         /*
1415          * Minimum alignment is 4k (GTT page size), but might be greater
1416          * if a fence register is needed for the object.
1417          */
1418         if (INTEL_INFO(dev)->gen >= 4 ||
1419             obj->tiling_mode == I915_TILING_NONE)
1420                 return 4096;
1421
1422         /*
1423          * Previous chips need to be aligned to the size of the smallest
1424          * fence register that can contain the object.
1425          */
1426         return i915_gem_get_gtt_size(obj);
1427 }
1428
1429 /**
1430  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1431  *                                       unfenced object
1432  * @obj: object to check
1433  *
1434  * Return the required GTT alignment for an object, only taking into account
1435  * unfenced tiled surface requirements.
1436  */
1437 uint32_t
1438 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1439 {
1440         struct drm_device *dev = obj->base.dev;
1441         int tile_height;
1442
1443         /*
1444          * Minimum alignment is 4k (GTT page size) for sane hw.
1445          */
1446         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1447             obj->tiling_mode == I915_TILING_NONE)
1448                 return 4096;
1449
1450         /*
1451          * Older chips need unfenced tiled buffers to be aligned to the left
1452          * edge of an even tile row (where tile rows are counted as if the bo is
1453          * placed in a fenced gtt region).
1454          */
1455         if (IS_GEN2(dev) ||
1456             (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
1457                 tile_height = 32;
1458         else
1459                 tile_height = 8;
1460
1461         return tile_height * obj->stride * 2;
1462 }
1463
1464 int
1465 i915_gem_mmap_gtt(struct drm_file *file,
1466                   struct drm_device *dev,
1467                   uint32_t handle,
1468                   uint64_t *offset)
1469 {
1470         struct drm_i915_private *dev_priv = dev->dev_private;
1471         struct drm_i915_gem_object *obj;
1472         int ret;
1473
1474         if (!(dev->driver->driver_features & DRIVER_GEM))
1475                 return -ENODEV;
1476
1477         ret = i915_mutex_lock_interruptible(dev);
1478         if (ret)
1479                 return ret;
1480
1481         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1482         if (&obj->base == NULL) {
1483                 ret = -ENOENT;
1484                 goto unlock;
1485         }
1486
1487         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1488                 ret = -E2BIG;
1489                 goto unlock;
1490         }
1491
1492         if (obj->madv != I915_MADV_WILLNEED) {
1493                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1494                 ret = -EINVAL;
1495                 goto out;
1496         }
1497
1498         if (!obj->base.map_list.map) {
1499                 ret = i915_gem_create_mmap_offset(obj);
1500                 if (ret)
1501                         goto out;
1502         }
1503
1504         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1505
1506 out:
1507         drm_gem_object_unreference(&obj->base);
1508 unlock:
1509         mutex_unlock(&dev->struct_mutex);
1510         return ret;
1511 }
1512
1513 /**
1514  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1515  * @dev: DRM device
1516  * @data: GTT mapping ioctl data
1517  * @file: GEM object info
1518  *
1519  * Simply returns the fake offset to userspace so it can mmap it.
1520  * The mmap call will end up in drm_gem_mmap(), which will set things
1521  * up so we can get faults in the handler above.
1522  *
1523  * The fault handler will take care of binding the object into the GTT
1524  * (since it may have been evicted to make room for something), allocating
1525  * a fence register, and mapping the appropriate aperture address into
1526  * userspace.
1527  */
1528 int
1529 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1530                         struct drm_file *file)
1531 {
1532         struct drm_i915_gem_mmap_gtt *args = data;
1533
1534         if (!(dev->driver->driver_features & DRIVER_GEM))
1535                 return -ENODEV;
1536
1537         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1538 }
1539
1540
1541 static int
1542 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1543                               gfp_t gfpmask)
1544 {
1545         int page_count, i;
1546         struct address_space *mapping;
1547         struct inode *inode;
1548         struct page *page;
1549
1550         /* Get the list of pages out of our struct file.  They'll be pinned
1551          * at this point until we release them.
1552          */
1553         page_count = obj->base.size / PAGE_SIZE;
1554         BUG_ON(obj->pages != NULL);
1555         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1556         if (obj->pages == NULL)
1557                 return -ENOMEM;
1558
1559         inode = obj->base.filp->f_path.dentry->d_inode;
1560         mapping = inode->i_mapping;
1561         for (i = 0; i < page_count; i++) {
1562                 page = read_cache_page_gfp(mapping, i,
1563                                            GFP_HIGHUSER |
1564                                            __GFP_COLD |
1565                                            __GFP_RECLAIMABLE |
1566                                            gfpmask);
1567                 if (IS_ERR(page))
1568                         goto err_pages;
1569
1570                 obj->pages[i] = page;
1571         }
1572
1573         if (obj->tiling_mode != I915_TILING_NONE)
1574                 i915_gem_object_do_bit_17_swizzle(obj);
1575
1576         return 0;
1577
1578 err_pages:
1579         while (i--)
1580                 page_cache_release(obj->pages[i]);
1581
1582         drm_free_large(obj->pages);
1583         obj->pages = NULL;
1584         return PTR_ERR(page);
1585 }
1586
1587 static void
1588 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1589 {
1590         int page_count = obj->base.size / PAGE_SIZE;
1591         int i;
1592
1593         BUG_ON(obj->madv == __I915_MADV_PURGED);
1594
1595         if (obj->tiling_mode != I915_TILING_NONE)
1596                 i915_gem_object_save_bit_17_swizzle(obj);
1597
1598         if (obj->madv == I915_MADV_DONTNEED)
1599                 obj->dirty = 0;
1600
1601         for (i = 0; i < page_count; i++) {
1602                 if (obj->dirty)
1603                         set_page_dirty(obj->pages[i]);
1604
1605                 if (obj->madv == I915_MADV_WILLNEED)
1606                         mark_page_accessed(obj->pages[i]);
1607
1608                 page_cache_release(obj->pages[i]);
1609         }
1610         obj->dirty = 0;
1611
1612         drm_free_large(obj->pages);
1613         obj->pages = NULL;
1614 }
1615
1616 void
1617 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1618                                struct intel_ring_buffer *ring,
1619                                u32 seqno)
1620 {
1621         struct drm_device *dev = obj->base.dev;
1622         struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624         BUG_ON(ring == NULL);
1625         obj->ring = ring;
1626
1627         /* Add a reference if we're newly entering the active list. */
1628         if (!obj->active) {
1629                 drm_gem_object_reference(&obj->base);
1630                 obj->active = 1;
1631         }
1632
1633         /* Move from whatever list we were on to the tail of execution. */
1634         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1635         list_move_tail(&obj->ring_list, &ring->active_list);
1636
1637         obj->last_rendering_seqno = seqno;
1638         if (obj->fenced_gpu_access) {
1639                 struct drm_i915_fence_reg *reg;
1640
1641                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1642
1643                 obj->last_fenced_seqno = seqno;
1644                 obj->last_fenced_ring = ring;
1645
1646                 reg = &dev_priv->fence_regs[obj->fence_reg];
1647                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1648         }
1649 }
1650
1651 static void
1652 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1653 {
1654         list_del_init(&obj->ring_list);
1655         obj->last_rendering_seqno = 0;
1656 }
1657
1658 static void
1659 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1660 {
1661         struct drm_device *dev = obj->base.dev;
1662         drm_i915_private_t *dev_priv = dev->dev_private;
1663
1664         BUG_ON(!obj->active);
1665         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1666
1667         i915_gem_object_move_off_active(obj);
1668 }
1669
1670 static void
1671 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1672 {
1673         struct drm_device *dev = obj->base.dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675
1676         if (obj->pin_count != 0)
1677                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1678         else
1679                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1680
1681         BUG_ON(!list_empty(&obj->gpu_write_list));
1682         BUG_ON(!obj->active);
1683         obj->ring = NULL;
1684
1685         i915_gem_object_move_off_active(obj);
1686         obj->fenced_gpu_access = false;
1687
1688         obj->active = 0;
1689         obj->pending_gpu_write = false;
1690         drm_gem_object_unreference(&obj->base);
1691
1692         WARN_ON(i915_verify_lists(dev));
1693 }
1694
1695 /* Immediately discard the backing storage */
1696 static void
1697 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1698 {
1699         struct inode *inode;
1700
1701         /* Our goal here is to return as much of the memory as
1702          * is possible back to the system as we are called from OOM.
1703          * To do this we must instruct the shmfs to drop all of its
1704          * backing pages, *now*. Here we mirror the actions taken
1705          * when by shmem_delete_inode() to release the backing store.
1706          */
1707         inode = obj->base.filp->f_path.dentry->d_inode;
1708         truncate_inode_pages(inode->i_mapping, 0);
1709         if (inode->i_op->truncate_range)
1710                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1711
1712         obj->madv = __I915_MADV_PURGED;
1713 }
1714
1715 static inline int
1716 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1717 {
1718         return obj->madv == I915_MADV_DONTNEED;
1719 }
1720
1721 static void
1722 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1723                                uint32_t flush_domains)
1724 {
1725         struct drm_i915_gem_object *obj, *next;
1726
1727         list_for_each_entry_safe(obj, next,
1728                                  &ring->gpu_write_list,
1729                                  gpu_write_list) {
1730                 if (obj->base.write_domain & flush_domains) {
1731                         uint32_t old_write_domain = obj->base.write_domain;
1732
1733                         obj->base.write_domain = 0;
1734                         list_del_init(&obj->gpu_write_list);
1735                         i915_gem_object_move_to_active(obj, ring,
1736                                                        i915_gem_next_request_seqno(ring));
1737
1738                         trace_i915_gem_object_change_domain(obj,
1739                                                             obj->base.read_domains,
1740                                                             old_write_domain);
1741                 }
1742         }
1743 }
1744
1745 int
1746 i915_add_request(struct intel_ring_buffer *ring,
1747                  struct drm_file *file,
1748                  struct drm_i915_gem_request *request)
1749 {
1750         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1751         uint32_t seqno;
1752         int was_empty;
1753         int ret;
1754
1755         BUG_ON(request == NULL);
1756
1757         ret = ring->add_request(ring, &seqno);
1758         if (ret)
1759             return ret;
1760
1761         trace_i915_gem_request_add(ring, seqno);
1762
1763         request->seqno = seqno;
1764         request->ring = ring;
1765         request->emitted_jiffies = jiffies;
1766         was_empty = list_empty(&ring->request_list);
1767         list_add_tail(&request->list, &ring->request_list);
1768
1769         if (file) {
1770                 struct drm_i915_file_private *file_priv = file->driver_priv;
1771
1772                 spin_lock(&file_priv->mm.lock);
1773                 request->file_priv = file_priv;
1774                 list_add_tail(&request->client_list,
1775                               &file_priv->mm.request_list);
1776                 spin_unlock(&file_priv->mm.lock);
1777         }
1778
1779         ring->outstanding_lazy_request = false;
1780
1781         if (!dev_priv->mm.suspended) {
1782                 mod_timer(&dev_priv->hangcheck_timer,
1783                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1784                 if (was_empty)
1785                         queue_delayed_work(dev_priv->wq,
1786                                            &dev_priv->mm.retire_work, HZ);
1787         }
1788         return 0;
1789 }
1790
1791 static inline void
1792 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1793 {
1794         struct drm_i915_file_private *file_priv = request->file_priv;
1795
1796         if (!file_priv)
1797                 return;
1798
1799         spin_lock(&file_priv->mm.lock);
1800         if (request->file_priv) {
1801                 list_del(&request->client_list);
1802                 request->file_priv = NULL;
1803         }
1804         spin_unlock(&file_priv->mm.lock);
1805 }
1806
1807 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1808                                       struct intel_ring_buffer *ring)
1809 {
1810         while (!list_empty(&ring->request_list)) {
1811                 struct drm_i915_gem_request *request;
1812
1813                 request = list_first_entry(&ring->request_list,
1814                                            struct drm_i915_gem_request,
1815                                            list);
1816
1817                 list_del(&request->list);
1818                 i915_gem_request_remove_from_client(request);
1819                 kfree(request);
1820         }
1821
1822         while (!list_empty(&ring->active_list)) {
1823                 struct drm_i915_gem_object *obj;
1824
1825                 obj = list_first_entry(&ring->active_list,
1826                                        struct drm_i915_gem_object,
1827                                        ring_list);
1828
1829                 obj->base.write_domain = 0;
1830                 list_del_init(&obj->gpu_write_list);
1831                 i915_gem_object_move_to_inactive(obj);
1832         }
1833 }
1834
1835 static void i915_gem_reset_fences(struct drm_device *dev)
1836 {
1837         struct drm_i915_private *dev_priv = dev->dev_private;
1838         int i;
1839
1840         for (i = 0; i < 16; i++) {
1841                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1842                 struct drm_i915_gem_object *obj = reg->obj;
1843
1844                 if (!obj)
1845                         continue;
1846
1847                 if (obj->tiling_mode)
1848                         i915_gem_release_mmap(obj);
1849
1850                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1851                 reg->obj->fenced_gpu_access = false;
1852                 reg->obj->last_fenced_seqno = 0;
1853                 reg->obj->last_fenced_ring = NULL;
1854                 i915_gem_clear_fence_reg(dev, reg);
1855         }
1856 }
1857
1858 void i915_gem_reset(struct drm_device *dev)
1859 {
1860         struct drm_i915_private *dev_priv = dev->dev_private;
1861         struct drm_i915_gem_object *obj;
1862         int i;
1863
1864         for (i = 0; i < I915_NUM_RINGS; i++)
1865                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1866
1867         /* Remove anything from the flushing lists. The GPU cache is likely
1868          * to be lost on reset along with the data, so simply move the
1869          * lost bo to the inactive list.
1870          */
1871         while (!list_empty(&dev_priv->mm.flushing_list)) {
1872                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1873                                       struct drm_i915_gem_object,
1874                                       mm_list);
1875
1876                 obj->base.write_domain = 0;
1877                 list_del_init(&obj->gpu_write_list);
1878                 i915_gem_object_move_to_inactive(obj);
1879         }
1880
1881         /* Move everything out of the GPU domains to ensure we do any
1882          * necessary invalidation upon reuse.
1883          */
1884         list_for_each_entry(obj,
1885                             &dev_priv->mm.inactive_list,
1886                             mm_list)
1887         {
1888                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1889         }
1890
1891         /* The fence registers are invalidated so clear them out */
1892         i915_gem_reset_fences(dev);
1893 }
1894
1895 /**
1896  * This function clears the request list as sequence numbers are passed.
1897  */
1898 static void
1899 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1900 {
1901         uint32_t seqno;
1902         int i;
1903
1904         if (list_empty(&ring->request_list))
1905                 return;
1906
1907         WARN_ON(i915_verify_lists(ring->dev));
1908
1909         seqno = ring->get_seqno(ring);
1910
1911         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1912                 if (seqno >= ring->sync_seqno[i])
1913                         ring->sync_seqno[i] = 0;
1914
1915         while (!list_empty(&ring->request_list)) {
1916                 struct drm_i915_gem_request *request;
1917
1918                 request = list_first_entry(&ring->request_list,
1919                                            struct drm_i915_gem_request,
1920                                            list);
1921
1922                 if (!i915_seqno_passed(seqno, request->seqno))
1923                         break;
1924
1925                 trace_i915_gem_request_retire(ring, request->seqno);
1926
1927                 list_del(&request->list);
1928                 i915_gem_request_remove_from_client(request);
1929                 kfree(request);
1930         }
1931
1932         /* Move any buffers on the active list that are no longer referenced
1933          * by the ringbuffer to the flushing/inactive lists as appropriate.
1934          */
1935         while (!list_empty(&ring->active_list)) {
1936                 struct drm_i915_gem_object *obj;
1937
1938                 obj= list_first_entry(&ring->active_list,
1939                                       struct drm_i915_gem_object,
1940                                       ring_list);
1941
1942                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1943                         break;
1944
1945                 if (obj->base.write_domain != 0)
1946                         i915_gem_object_move_to_flushing(obj);
1947                 else
1948                         i915_gem_object_move_to_inactive(obj);
1949         }
1950
1951         if (unlikely(ring->trace_irq_seqno &&
1952                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1953                 ring->irq_put(ring);
1954                 ring->trace_irq_seqno = 0;
1955         }
1956
1957         WARN_ON(i915_verify_lists(ring->dev));
1958 }
1959
1960 void
1961 i915_gem_retire_requests(struct drm_device *dev)
1962 {
1963         drm_i915_private_t *dev_priv = dev->dev_private;
1964         int i;
1965
1966         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1967             struct drm_i915_gem_object *obj, *next;
1968
1969             /* We must be careful that during unbind() we do not
1970              * accidentally infinitely recurse into retire requests.
1971              * Currently:
1972              *   retire -> free -> unbind -> wait -> retire_ring
1973              */
1974             list_for_each_entry_safe(obj, next,
1975                                      &dev_priv->mm.deferred_free_list,
1976                                      mm_list)
1977                     i915_gem_free_object_tail(obj);
1978         }
1979
1980         for (i = 0; i < I915_NUM_RINGS; i++)
1981                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1982 }
1983
1984 static void
1985 i915_gem_retire_work_handler(struct work_struct *work)
1986 {
1987         drm_i915_private_t *dev_priv;
1988         struct drm_device *dev;
1989         bool idle;
1990         int i;
1991
1992         dev_priv = container_of(work, drm_i915_private_t,
1993                                 mm.retire_work.work);
1994         dev = dev_priv->dev;
1995
1996         /* Come back later if the device is busy... */
1997         if (!mutex_trylock(&dev->struct_mutex)) {
1998                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1999                 return;
2000         }
2001
2002         i915_gem_retire_requests(dev);
2003
2004         /* Send a periodic flush down the ring so we don't hold onto GEM
2005          * objects indefinitely.
2006          */
2007         idle = true;
2008         for (i = 0; i < I915_NUM_RINGS; i++) {
2009                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2010
2011                 if (!list_empty(&ring->gpu_write_list)) {
2012                         struct drm_i915_gem_request *request;
2013                         int ret;
2014
2015                         ret = i915_gem_flush_ring(ring,
2016                                                   0, I915_GEM_GPU_DOMAINS);
2017                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2018                         if (ret || request == NULL ||
2019                             i915_add_request(ring, NULL, request))
2020                             kfree(request);
2021                 }
2022
2023                 idle &= list_empty(&ring->request_list);
2024         }
2025
2026         if (!dev_priv->mm.suspended && !idle)
2027                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2028
2029         mutex_unlock(&dev->struct_mutex);
2030 }
2031
2032 /**
2033  * Waits for a sequence number to be signaled, and cleans up the
2034  * request and object lists appropriately for that event.
2035  */
2036 int
2037 i915_wait_request(struct intel_ring_buffer *ring,
2038                   uint32_t seqno)
2039 {
2040         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2041         u32 ier;
2042         int ret = 0;
2043
2044         BUG_ON(seqno == 0);
2045
2046         if (atomic_read(&dev_priv->mm.wedged)) {
2047                 struct completion *x = &dev_priv->error_completion;
2048                 bool recovery_complete;
2049                 unsigned long flags;
2050
2051                 /* Give the error handler a chance to run. */
2052                 spin_lock_irqsave(&x->wait.lock, flags);
2053                 recovery_complete = x->done > 0;
2054                 spin_unlock_irqrestore(&x->wait.lock, flags);
2055
2056                 return recovery_complete ? -EIO : -EAGAIN;
2057         }
2058
2059         if (seqno == ring->outstanding_lazy_request) {
2060                 struct drm_i915_gem_request *request;
2061
2062                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2063                 if (request == NULL)
2064                         return -ENOMEM;
2065
2066                 ret = i915_add_request(ring, NULL, request);
2067                 if (ret) {
2068                         kfree(request);
2069                         return ret;
2070                 }
2071
2072                 seqno = request->seqno;
2073         }
2074
2075         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2076                 if (HAS_PCH_SPLIT(ring->dev))
2077                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2078                 else
2079                         ier = I915_READ(IER);
2080                 if (!ier) {
2081                         DRM_ERROR("something (likely vbetool) disabled "
2082                                   "interrupts, re-enabling\n");
2083                         i915_driver_irq_preinstall(ring->dev);
2084                         i915_driver_irq_postinstall(ring->dev);
2085                 }
2086
2087                 trace_i915_gem_request_wait_begin(ring, seqno);
2088
2089                 ring->waiting_seqno = seqno;
2090                 if (ring->irq_get(ring)) {
2091                         if (dev_priv->mm.interruptible)
2092                                 ret = wait_event_interruptible(ring->irq_queue,
2093                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2094                                                                || atomic_read(&dev_priv->mm.wedged));
2095                         else
2096                                 wait_event(ring->irq_queue,
2097                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2098                                            || atomic_read(&dev_priv->mm.wedged));
2099
2100                         ring->irq_put(ring);
2101                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2102                                                       seqno) ||
2103                                     atomic_read(&dev_priv->mm.wedged), 3000))
2104                         ret = -EBUSY;
2105                 ring->waiting_seqno = 0;
2106
2107                 trace_i915_gem_request_wait_end(ring, seqno);
2108         }
2109         if (atomic_read(&dev_priv->mm.wedged))
2110                 ret = -EAGAIN;
2111
2112         if (ret && ret != -ERESTARTSYS)
2113                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2114                           __func__, ret, seqno, ring->get_seqno(ring),
2115                           dev_priv->next_seqno);
2116
2117         /* Directly dispatch request retiring.  While we have the work queue
2118          * to handle this, the waiter on a request often wants an associated
2119          * buffer to have made it to the inactive list, and we would need
2120          * a separate wait queue to handle that.
2121          */
2122         if (ret == 0)
2123                 i915_gem_retire_requests_ring(ring);
2124
2125         return ret;
2126 }
2127
2128 /**
2129  * Ensures that all rendering to the object has completed and the object is
2130  * safe to unbind from the GTT or access from the CPU.
2131  */
2132 int
2133 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2134 {
2135         int ret;
2136
2137         /* This function only exists to support waiting for existing rendering,
2138          * not for emitting required flushes.
2139          */
2140         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2141
2142         /* If there is rendering queued on the buffer being evicted, wait for
2143          * it.
2144          */
2145         if (obj->active) {
2146                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2147                 if (ret)
2148                         return ret;
2149         }
2150
2151         return 0;
2152 }
2153
2154 /**
2155  * Unbinds an object from the GTT aperture.
2156  */
2157 int
2158 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2159 {
2160         int ret = 0;
2161
2162         if (obj->gtt_space == NULL)
2163                 return 0;
2164
2165         if (obj->pin_count != 0) {
2166                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2167                 return -EINVAL;
2168         }
2169
2170         /* blow away mappings if mapped through GTT */
2171         i915_gem_release_mmap(obj);
2172
2173         /* Move the object to the CPU domain to ensure that
2174          * any possible CPU writes while it's not in the GTT
2175          * are flushed when we go to remap it. This will
2176          * also ensure that all pending GPU writes are finished
2177          * before we unbind.
2178          */
2179         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2180         if (ret == -ERESTARTSYS)
2181                 return ret;
2182         /* Continue on if we fail due to EIO, the GPU is hung so we
2183          * should be safe and we need to cleanup or else we might
2184          * cause memory corruption through use-after-free.
2185          */
2186         if (ret) {
2187                 i915_gem_clflush_object(obj);
2188                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2189         }
2190
2191         /* release the fence reg _after_ flushing */
2192         ret = i915_gem_object_put_fence(obj);
2193         if (ret == -ERESTARTSYS)
2194                 return ret;
2195
2196         trace_i915_gem_object_unbind(obj);
2197
2198         i915_gem_gtt_unbind_object(obj);
2199         i915_gem_object_put_pages_gtt(obj);
2200
2201         list_del_init(&obj->gtt_list);
2202         list_del_init(&obj->mm_list);
2203         /* Avoid an unnecessary call to unbind on rebind. */
2204         obj->map_and_fenceable = true;
2205
2206         drm_mm_put_block(obj->gtt_space);
2207         obj->gtt_space = NULL;
2208         obj->gtt_offset = 0;
2209
2210         if (i915_gem_object_is_purgeable(obj))
2211                 i915_gem_object_truncate(obj);
2212
2213         return ret;
2214 }
2215
2216 int
2217 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2218                     uint32_t invalidate_domains,
2219                     uint32_t flush_domains)
2220 {
2221         int ret;
2222
2223         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2224                 return 0;
2225
2226         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2227
2228         ret = ring->flush(ring, invalidate_domains, flush_domains);
2229         if (ret)
2230                 return ret;
2231
2232         if (flush_domains & I915_GEM_GPU_DOMAINS)
2233                 i915_gem_process_flushing_list(ring, flush_domains);
2234
2235         return 0;
2236 }
2237
2238 static int i915_ring_idle(struct intel_ring_buffer *ring)
2239 {
2240         int ret;
2241
2242         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2243                 return 0;
2244
2245         if (!list_empty(&ring->gpu_write_list)) {
2246                 ret = i915_gem_flush_ring(ring,
2247                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2248                 if (ret)
2249                         return ret;
2250         }
2251
2252         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2253 }
2254
2255 int
2256 i915_gpu_idle(struct drm_device *dev)
2257 {
2258         drm_i915_private_t *dev_priv = dev->dev_private;
2259         bool lists_empty;
2260         int ret, i;
2261
2262         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2263                        list_empty(&dev_priv->mm.active_list));
2264         if (lists_empty)
2265                 return 0;
2266
2267         /* Flush everything onto the inactive list. */
2268         for (i = 0; i < I915_NUM_RINGS; i++) {
2269                 ret = i915_ring_idle(&dev_priv->ring[i]);
2270                 if (ret)
2271                         return ret;
2272         }
2273
2274         return 0;
2275 }
2276
2277 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2278                                        struct intel_ring_buffer *pipelined)
2279 {
2280         struct drm_device *dev = obj->base.dev;
2281         drm_i915_private_t *dev_priv = dev->dev_private;
2282         u32 size = obj->gtt_space->size;
2283         int regnum = obj->fence_reg;
2284         uint64_t val;
2285
2286         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2287                          0xfffff000) << 32;
2288         val |= obj->gtt_offset & 0xfffff000;
2289         val |= (uint64_t)((obj->stride / 128) - 1) <<
2290                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2291
2292         if (obj->tiling_mode == I915_TILING_Y)
2293                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2294         val |= I965_FENCE_REG_VALID;
2295
2296         if (pipelined) {
2297                 int ret = intel_ring_begin(pipelined, 6);
2298                 if (ret)
2299                         return ret;
2300
2301                 intel_ring_emit(pipelined, MI_NOOP);
2302                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2303                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2304                 intel_ring_emit(pipelined, (u32)val);
2305                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2306                 intel_ring_emit(pipelined, (u32)(val >> 32));
2307                 intel_ring_advance(pipelined);
2308         } else
2309                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2310
2311         return 0;
2312 }
2313
2314 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2315                                 struct intel_ring_buffer *pipelined)
2316 {
2317         struct drm_device *dev = obj->base.dev;
2318         drm_i915_private_t *dev_priv = dev->dev_private;
2319         u32 size = obj->gtt_space->size;
2320         int regnum = obj->fence_reg;
2321         uint64_t val;
2322
2323         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2324                     0xfffff000) << 32;
2325         val |= obj->gtt_offset & 0xfffff000;
2326         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2327         if (obj->tiling_mode == I915_TILING_Y)
2328                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2329         val |= I965_FENCE_REG_VALID;
2330
2331         if (pipelined) {
2332                 int ret = intel_ring_begin(pipelined, 6);
2333                 if (ret)
2334                         return ret;
2335
2336                 intel_ring_emit(pipelined, MI_NOOP);
2337                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2338                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2339                 intel_ring_emit(pipelined, (u32)val);
2340                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2341                 intel_ring_emit(pipelined, (u32)(val >> 32));
2342                 intel_ring_advance(pipelined);
2343         } else
2344                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2345
2346         return 0;
2347 }
2348
2349 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2350                                 struct intel_ring_buffer *pipelined)
2351 {
2352         struct drm_device *dev = obj->base.dev;
2353         drm_i915_private_t *dev_priv = dev->dev_private;
2354         u32 size = obj->gtt_space->size;
2355         u32 fence_reg, val, pitch_val;
2356         int tile_width;
2357
2358         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2359                  (size & -size) != size ||
2360                  (obj->gtt_offset & (size - 1)),
2361                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2362                  obj->gtt_offset, obj->map_and_fenceable, size))
2363                 return -EINVAL;
2364
2365         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2366                 tile_width = 128;
2367         else
2368                 tile_width = 512;
2369
2370         /* Note: pitch better be a power of two tile widths */
2371         pitch_val = obj->stride / tile_width;
2372         pitch_val = ffs(pitch_val) - 1;
2373
2374         val = obj->gtt_offset;
2375         if (obj->tiling_mode == I915_TILING_Y)
2376                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2377         val |= I915_FENCE_SIZE_BITS(size);
2378         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2379         val |= I830_FENCE_REG_VALID;
2380
2381         fence_reg = obj->fence_reg;
2382         if (fence_reg < 8)
2383                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2384         else
2385                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2386
2387         if (pipelined) {
2388                 int ret = intel_ring_begin(pipelined, 4);
2389                 if (ret)
2390                         return ret;
2391
2392                 intel_ring_emit(pipelined, MI_NOOP);
2393                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2394                 intel_ring_emit(pipelined, fence_reg);
2395                 intel_ring_emit(pipelined, val);
2396                 intel_ring_advance(pipelined);
2397         } else
2398                 I915_WRITE(fence_reg, val);
2399
2400         return 0;
2401 }
2402
2403 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2404                                 struct intel_ring_buffer *pipelined)
2405 {
2406         struct drm_device *dev = obj->base.dev;
2407         drm_i915_private_t *dev_priv = dev->dev_private;
2408         u32 size = obj->gtt_space->size;
2409         int regnum = obj->fence_reg;
2410         uint32_t val;
2411         uint32_t pitch_val;
2412
2413         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2414                  (size & -size) != size ||
2415                  (obj->gtt_offset & (size - 1)),
2416                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2417                  obj->gtt_offset, size))
2418                 return -EINVAL;
2419
2420         pitch_val = obj->stride / 128;
2421         pitch_val = ffs(pitch_val) - 1;
2422
2423         val = obj->gtt_offset;
2424         if (obj->tiling_mode == I915_TILING_Y)
2425                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2426         val |= I830_FENCE_SIZE_BITS(size);
2427         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2428         val |= I830_FENCE_REG_VALID;
2429
2430         if (pipelined) {
2431                 int ret = intel_ring_begin(pipelined, 4);
2432                 if (ret)
2433                         return ret;
2434
2435                 intel_ring_emit(pipelined, MI_NOOP);
2436                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2437                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2438                 intel_ring_emit(pipelined, val);
2439                 intel_ring_advance(pipelined);
2440         } else
2441                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2442
2443         return 0;
2444 }
2445
2446 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2447 {
2448         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2449 }
2450
2451 static int
2452 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2453                             struct intel_ring_buffer *pipelined)
2454 {
2455         int ret;
2456
2457         if (obj->fenced_gpu_access) {
2458                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2459                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2460                                                   0, obj->base.write_domain);
2461                         if (ret)
2462                                 return ret;
2463                 }
2464
2465                 obj->fenced_gpu_access = false;
2466         }
2467
2468         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2469                 if (!ring_passed_seqno(obj->last_fenced_ring,
2470                                        obj->last_fenced_seqno)) {
2471                         ret = i915_wait_request(obj->last_fenced_ring,
2472                                                 obj->last_fenced_seqno);
2473                         if (ret)
2474                                 return ret;
2475                 }
2476
2477                 obj->last_fenced_seqno = 0;
2478                 obj->last_fenced_ring = NULL;
2479         }
2480
2481         /* Ensure that all CPU reads are completed before installing a fence
2482          * and all writes before removing the fence.
2483          */
2484         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2485                 mb();
2486
2487         return 0;
2488 }
2489
2490 int
2491 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2492 {
2493         int ret;
2494
2495         if (obj->tiling_mode)
2496                 i915_gem_release_mmap(obj);
2497
2498         ret = i915_gem_object_flush_fence(obj, NULL);
2499         if (ret)
2500                 return ret;
2501
2502         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2503                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2504                 i915_gem_clear_fence_reg(obj->base.dev,
2505                                          &dev_priv->fence_regs[obj->fence_reg]);
2506
2507                 obj->fence_reg = I915_FENCE_REG_NONE;
2508         }
2509
2510         return 0;
2511 }
2512
2513 static struct drm_i915_fence_reg *
2514 i915_find_fence_reg(struct drm_device *dev,
2515                     struct intel_ring_buffer *pipelined)
2516 {
2517         struct drm_i915_private *dev_priv = dev->dev_private;
2518         struct drm_i915_fence_reg *reg, *first, *avail;
2519         int i;
2520
2521         /* First try to find a free reg */
2522         avail = NULL;
2523         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2524                 reg = &dev_priv->fence_regs[i];
2525                 if (!reg->obj)
2526                         return reg;
2527
2528                 if (!reg->obj->pin_count)
2529                         avail = reg;
2530         }
2531
2532         if (avail == NULL)
2533                 return NULL;
2534
2535         /* None available, try to steal one or wait for a user to finish */
2536         avail = first = NULL;
2537         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2538                 if (reg->obj->pin_count)
2539                         continue;
2540
2541                 if (first == NULL)
2542                         first = reg;
2543
2544                 if (!pipelined ||
2545                     !reg->obj->last_fenced_ring ||
2546                     reg->obj->last_fenced_ring == pipelined) {
2547                         avail = reg;
2548                         break;
2549                 }
2550         }
2551
2552         if (avail == NULL)
2553                 avail = first;
2554
2555         return avail;
2556 }
2557
2558 /**
2559  * i915_gem_object_get_fence - set up a fence reg for an object
2560  * @obj: object to map through a fence reg
2561  * @pipelined: ring on which to queue the change, or NULL for CPU access
2562  * @interruptible: must we wait uninterruptibly for the register to retire?
2563  *
2564  * When mapping objects through the GTT, userspace wants to be able to write
2565  * to them without having to worry about swizzling if the object is tiled.
2566  *
2567  * This function walks the fence regs looking for a free one for @obj,
2568  * stealing one if it can't find any.
2569  *
2570  * It then sets up the reg based on the object's properties: address, pitch
2571  * and tiling format.
2572  */
2573 int
2574 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2575                           struct intel_ring_buffer *pipelined)
2576 {
2577         struct drm_device *dev = obj->base.dev;
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         struct drm_i915_fence_reg *reg;
2580         int ret;
2581
2582         /* XXX disable pipelining. There are bugs. Shocking. */
2583         pipelined = NULL;
2584
2585         /* Just update our place in the LRU if our fence is getting reused. */
2586         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2587                 reg = &dev_priv->fence_regs[obj->fence_reg];
2588                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2589
2590                 if (obj->tiling_changed) {
2591                         ret = i915_gem_object_flush_fence(obj, pipelined);
2592                         if (ret)
2593                                 return ret;
2594
2595                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2596                                 pipelined = NULL;
2597
2598                         if (pipelined) {
2599                                 reg->setup_seqno =
2600                                         i915_gem_next_request_seqno(pipelined);
2601                                 obj->last_fenced_seqno = reg->setup_seqno;
2602                                 obj->last_fenced_ring = pipelined;
2603                         }
2604
2605                         goto update;
2606                 }
2607
2608                 if (!pipelined) {
2609                         if (reg->setup_seqno) {
2610                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2611                                                        reg->setup_seqno)) {
2612                                         ret = i915_wait_request(obj->last_fenced_ring,
2613                                                                 reg->setup_seqno);
2614                                         if (ret)
2615                                                 return ret;
2616                                 }
2617
2618                                 reg->setup_seqno = 0;
2619                         }
2620                 } else if (obj->last_fenced_ring &&
2621                            obj->last_fenced_ring != pipelined) {
2622                         ret = i915_gem_object_flush_fence(obj, pipelined);
2623                         if (ret)
2624                                 return ret;
2625                 }
2626
2627                 return 0;
2628         }
2629
2630         reg = i915_find_fence_reg(dev, pipelined);
2631         if (reg == NULL)
2632                 return -ENOSPC;
2633
2634         ret = i915_gem_object_flush_fence(obj, pipelined);
2635         if (ret)
2636                 return ret;
2637
2638         if (reg->obj) {
2639                 struct drm_i915_gem_object *old = reg->obj;
2640
2641                 drm_gem_object_reference(&old->base);
2642
2643                 if (old->tiling_mode)
2644                         i915_gem_release_mmap(old);
2645
2646                 ret = i915_gem_object_flush_fence(old, pipelined);
2647                 if (ret) {
2648                         drm_gem_object_unreference(&old->base);
2649                         return ret;
2650                 }
2651
2652                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2653                         pipelined = NULL;
2654
2655                 old->fence_reg = I915_FENCE_REG_NONE;
2656                 old->last_fenced_ring = pipelined;
2657                 old->last_fenced_seqno =
2658                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2659
2660                 drm_gem_object_unreference(&old->base);
2661         } else if (obj->last_fenced_seqno == 0)
2662                 pipelined = NULL;
2663
2664         reg->obj = obj;
2665         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2666         obj->fence_reg = reg - dev_priv->fence_regs;
2667         obj->last_fenced_ring = pipelined;
2668
2669         reg->setup_seqno =
2670                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2671         obj->last_fenced_seqno = reg->setup_seqno;
2672
2673 update:
2674         obj->tiling_changed = false;
2675         switch (INTEL_INFO(dev)->gen) {
2676         case 6:
2677                 ret = sandybridge_write_fence_reg(obj, pipelined);
2678                 break;
2679         case 5:
2680         case 4:
2681                 ret = i965_write_fence_reg(obj, pipelined);
2682                 break;
2683         case 3:
2684                 ret = i915_write_fence_reg(obj, pipelined);
2685                 break;
2686         case 2:
2687                 ret = i830_write_fence_reg(obj, pipelined);
2688                 break;
2689         }
2690
2691         return ret;
2692 }
2693
2694 /**
2695  * i915_gem_clear_fence_reg - clear out fence register info
2696  * @obj: object to clear
2697  *
2698  * Zeroes out the fence register itself and clears out the associated
2699  * data structures in dev_priv and obj.
2700  */
2701 static void
2702 i915_gem_clear_fence_reg(struct drm_device *dev,
2703                          struct drm_i915_fence_reg *reg)
2704 {
2705         drm_i915_private_t *dev_priv = dev->dev_private;
2706         uint32_t fence_reg = reg - dev_priv->fence_regs;
2707
2708         switch (INTEL_INFO(dev)->gen) {
2709         case 6:
2710                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2711                 break;
2712         case 5:
2713         case 4:
2714                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2715                 break;
2716         case 3:
2717                 if (fence_reg >= 8)
2718                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2719                 else
2720         case 2:
2721                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2722
2723                 I915_WRITE(fence_reg, 0);
2724                 break;
2725         }
2726
2727         list_del_init(&reg->lru_list);
2728         reg->obj = NULL;
2729         reg->setup_seqno = 0;
2730 }
2731
2732 /**
2733  * Finds free space in the GTT aperture and binds the object there.
2734  */
2735 static int
2736 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2737                             unsigned alignment,
2738                             bool map_and_fenceable)
2739 {
2740         struct drm_device *dev = obj->base.dev;
2741         drm_i915_private_t *dev_priv = dev->dev_private;
2742         struct drm_mm_node *free_space;
2743         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2744         u32 size, fence_size, fence_alignment, unfenced_alignment;
2745         bool mappable, fenceable;
2746         int ret;
2747
2748         if (obj->madv != I915_MADV_WILLNEED) {
2749                 DRM_ERROR("Attempting to bind a purgeable object\n");
2750                 return -EINVAL;
2751         }
2752
2753         fence_size = i915_gem_get_gtt_size(obj);
2754         fence_alignment = i915_gem_get_gtt_alignment(obj);
2755         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2756
2757         if (alignment == 0)
2758                 alignment = map_and_fenceable ? fence_alignment :
2759                                                 unfenced_alignment;
2760         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2761                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2762                 return -EINVAL;
2763         }
2764
2765         size = map_and_fenceable ? fence_size : obj->base.size;
2766
2767         /* If the object is bigger than the entire aperture, reject it early
2768          * before evicting everything in a vain attempt to find space.
2769          */
2770         if (obj->base.size >
2771             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2772                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2773                 return -E2BIG;
2774         }
2775
2776  search_free:
2777         if (map_and_fenceable)
2778                 free_space =
2779                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2780                                                     size, alignment, 0,
2781                                                     dev_priv->mm.gtt_mappable_end,
2782                                                     0);
2783         else
2784                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2785                                                 size, alignment, 0);
2786
2787         if (free_space != NULL) {
2788                 if (map_and_fenceable)
2789                         obj->gtt_space =
2790                                 drm_mm_get_block_range_generic(free_space,
2791                                                                size, alignment, 0,
2792                                                                dev_priv->mm.gtt_mappable_end,
2793                                                                0);
2794                 else
2795                         obj->gtt_space =
2796                                 drm_mm_get_block(free_space, size, alignment);
2797         }
2798         if (obj->gtt_space == NULL) {
2799                 /* If the gtt is empty and we're still having trouble
2800                  * fitting our object in, we're out of memory.
2801                  */
2802                 ret = i915_gem_evict_something(dev, size, alignment,
2803                                                map_and_fenceable);
2804                 if (ret)
2805                         return ret;
2806
2807                 goto search_free;
2808         }
2809
2810         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2811         if (ret) {
2812                 drm_mm_put_block(obj->gtt_space);
2813                 obj->gtt_space = NULL;
2814
2815                 if (ret == -ENOMEM) {
2816                         /* first try to reclaim some memory by clearing the GTT */
2817                         ret = i915_gem_evict_everything(dev, false);
2818                         if (ret) {
2819                                 /* now try to shrink everyone else */
2820                                 if (gfpmask) {
2821                                         gfpmask = 0;
2822                                         goto search_free;
2823                                 }
2824
2825                                 return -ENOMEM;
2826                         }
2827
2828                         goto search_free;
2829                 }
2830
2831                 return ret;
2832         }
2833
2834         ret = i915_gem_gtt_bind_object(obj);
2835         if (ret) {
2836                 i915_gem_object_put_pages_gtt(obj);
2837                 drm_mm_put_block(obj->gtt_space);
2838                 obj->gtt_space = NULL;
2839
2840                 if (i915_gem_evict_everything(dev, false))
2841                         return ret;
2842
2843                 goto search_free;
2844         }
2845
2846         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2847         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2848
2849         /* Assert that the object is not currently in any GPU domain. As it
2850          * wasn't in the GTT, there shouldn't be any way it could have been in
2851          * a GPU cache
2852          */
2853         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2854         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2855
2856         obj->gtt_offset = obj->gtt_space->start;
2857
2858         fenceable =
2859                 obj->gtt_space->size == fence_size &&
2860                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2861
2862         mappable =
2863                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2864
2865         obj->map_and_fenceable = mappable && fenceable;
2866
2867         trace_i915_gem_object_bind(obj, map_and_fenceable);
2868         return 0;
2869 }
2870
2871 void
2872 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2873 {
2874         /* If we don't have a page list set up, then we're not pinned
2875          * to GPU, and we can ignore the cache flush because it'll happen
2876          * again at bind time.
2877          */
2878         if (obj->pages == NULL)
2879                 return;
2880
2881         trace_i915_gem_object_clflush(obj);
2882
2883         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2884 }
2885
2886 /** Flushes any GPU write domain for the object if it's dirty. */
2887 static int
2888 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2889 {
2890         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2891                 return 0;
2892
2893         /* Queue the GPU write cache flushing we need. */
2894         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2895 }
2896
2897 /** Flushes the GTT write domain for the object if it's dirty. */
2898 static void
2899 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2900 {
2901         uint32_t old_write_domain;
2902
2903         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2904                 return;
2905
2906         /* No actual flushing is required for the GTT write domain.  Writes
2907          * to it immediately go to main memory as far as we know, so there's
2908          * no chipset flush.  It also doesn't land in render cache.
2909          *
2910          * However, we do have to enforce the order so that all writes through
2911          * the GTT land before any writes to the device, such as updates to
2912          * the GATT itself.
2913          */
2914         wmb();
2915
2916         i915_gem_release_mmap(obj);
2917
2918         old_write_domain = obj->base.write_domain;
2919         obj->base.write_domain = 0;
2920
2921         trace_i915_gem_object_change_domain(obj,
2922                                             obj->base.read_domains,
2923                                             old_write_domain);
2924 }
2925
2926 /** Flushes the CPU write domain for the object if it's dirty. */
2927 static void
2928 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2929 {
2930         uint32_t old_write_domain;
2931
2932         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2933                 return;
2934
2935         i915_gem_clflush_object(obj);
2936         intel_gtt_chipset_flush();
2937         old_write_domain = obj->base.write_domain;
2938         obj->base.write_domain = 0;
2939
2940         trace_i915_gem_object_change_domain(obj,
2941                                             obj->base.read_domains,
2942                                             old_write_domain);
2943 }
2944
2945 /**
2946  * Moves a single object to the GTT read, and possibly write domain.
2947  *
2948  * This function returns when the move is complete, including waiting on
2949  * flushes to occur.
2950  */
2951 int
2952 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2953 {
2954         uint32_t old_write_domain, old_read_domains;
2955         int ret;
2956
2957         /* Not valid to be called on unbound objects. */
2958         if (obj->gtt_space == NULL)
2959                 return -EINVAL;
2960
2961         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2962                 return 0;
2963
2964         ret = i915_gem_object_flush_gpu_write_domain(obj);
2965         if (ret)
2966                 return ret;
2967
2968         if (obj->pending_gpu_write || write) {
2969                 ret = i915_gem_object_wait_rendering(obj);
2970                 if (ret)
2971                         return ret;
2972         }
2973
2974         i915_gem_object_flush_cpu_write_domain(obj);
2975
2976         old_write_domain = obj->base.write_domain;
2977         old_read_domains = obj->base.read_domains;
2978
2979         /* It should now be out of any other write domains, and we can update
2980          * the domain values for our changes.
2981          */
2982         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2983         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2984         if (write) {
2985                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2986                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2987                 obj->dirty = 1;
2988         }
2989
2990         trace_i915_gem_object_change_domain(obj,
2991                                             old_read_domains,
2992                                             old_write_domain);
2993
2994         return 0;
2995 }
2996
2997 /*
2998  * Prepare buffer for display plane. Use uninterruptible for possible flush
2999  * wait, as in modesetting process we're not supposed to be interrupted.
3000  */
3001 int
3002 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
3003                                      struct intel_ring_buffer *pipelined)
3004 {
3005         uint32_t old_read_domains;
3006         int ret;
3007
3008         /* Not valid to be called on unbound objects. */
3009         if (obj->gtt_space == NULL)
3010                 return -EINVAL;
3011
3012         ret = i915_gem_object_flush_gpu_write_domain(obj);
3013         if (ret)
3014                 return ret;
3015
3016
3017         /* Currently, we are always called from an non-interruptible context. */
3018         if (pipelined != obj->ring) {
3019                 ret = i915_gem_object_wait_rendering(obj);
3020                 if (ret)
3021                         return ret;
3022         }
3023
3024         i915_gem_object_flush_cpu_write_domain(obj);
3025
3026         old_read_domains = obj->base.read_domains;
3027         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3028
3029         trace_i915_gem_object_change_domain(obj,
3030                                             old_read_domains,
3031                                             obj->base.write_domain);
3032
3033         return 0;
3034 }
3035
3036 int
3037 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
3038 {
3039         int ret;
3040
3041         if (!obj->active)
3042                 return 0;
3043
3044         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3045                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3046                 if (ret)
3047                         return ret;
3048         }
3049
3050         return i915_gem_object_wait_rendering(obj);
3051 }
3052
3053 /**
3054  * Moves a single object to the CPU read, and possibly write domain.
3055  *
3056  * This function returns when the move is complete, including waiting on
3057  * flushes to occur.
3058  */
3059 static int
3060 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3061 {
3062         uint32_t old_write_domain, old_read_domains;
3063         int ret;
3064
3065         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3066                 return 0;
3067
3068         ret = i915_gem_object_flush_gpu_write_domain(obj);
3069         if (ret)
3070                 return ret;
3071
3072         ret = i915_gem_object_wait_rendering(obj);
3073         if (ret)
3074                 return ret;
3075
3076         i915_gem_object_flush_gtt_write_domain(obj);
3077
3078         /* If we have a partially-valid cache of the object in the CPU,
3079          * finish invalidating it and free the per-page flags.
3080          */
3081         i915_gem_object_set_to_full_cpu_read_domain(obj);
3082
3083         old_write_domain = obj->base.write_domain;
3084         old_read_domains = obj->base.read_domains;
3085
3086         /* Flush the CPU cache if it's still invalid. */
3087         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3088                 i915_gem_clflush_object(obj);
3089
3090                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3091         }
3092
3093         /* It should now be out of any other write domains, and we can update
3094          * the domain values for our changes.
3095          */
3096         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3097
3098         /* If we're writing through the CPU, then the GPU read domains will
3099          * need to be invalidated at next use.
3100          */
3101         if (write) {
3102                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3103                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3104         }
3105
3106         trace_i915_gem_object_change_domain(obj,
3107                                             old_read_domains,
3108                                             old_write_domain);
3109
3110         return 0;
3111 }
3112
3113 /**
3114  * Moves the object from a partially CPU read to a full one.
3115  *
3116  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3117  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3118  */
3119 static void
3120 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3121 {
3122         if (!obj->page_cpu_valid)
3123                 return;
3124
3125         /* If we're partially in the CPU read domain, finish moving it in.
3126          */
3127         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3128                 int i;
3129
3130                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3131                         if (obj->page_cpu_valid[i])
3132                                 continue;
3133                         drm_clflush_pages(obj->pages + i, 1);
3134                 }
3135         }
3136
3137         /* Free the page_cpu_valid mappings which are now stale, whether
3138          * or not we've got I915_GEM_DOMAIN_CPU.
3139          */
3140         kfree(obj->page_cpu_valid);
3141         obj->page_cpu_valid = NULL;
3142 }
3143
3144 /**
3145  * Set the CPU read domain on a range of the object.
3146  *
3147  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3148  * not entirely valid.  The page_cpu_valid member of the object flags which
3149  * pages have been flushed, and will be respected by
3150  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3151  * of the whole object.
3152  *
3153  * This function returns when the move is complete, including waiting on
3154  * flushes to occur.
3155  */
3156 static int
3157 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3158                                           uint64_t offset, uint64_t size)
3159 {
3160         uint32_t old_read_domains;
3161         int i, ret;
3162
3163         if (offset == 0 && size == obj->base.size)
3164                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3165
3166         ret = i915_gem_object_flush_gpu_write_domain(obj);
3167         if (ret)
3168                 return ret;
3169
3170         ret = i915_gem_object_wait_rendering(obj);
3171         if (ret)
3172                 return ret;
3173
3174         i915_gem_object_flush_gtt_write_domain(obj);
3175
3176         /* If we're already fully in the CPU read domain, we're done. */
3177         if (obj->page_cpu_valid == NULL &&
3178             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3179                 return 0;
3180
3181         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3182          * newly adding I915_GEM_DOMAIN_CPU
3183          */
3184         if (obj->page_cpu_valid == NULL) {
3185                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3186                                               GFP_KERNEL);
3187                 if (obj->page_cpu_valid == NULL)
3188                         return -ENOMEM;
3189         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3190                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3191
3192         /* Flush the cache on any pages that are still invalid from the CPU's
3193          * perspective.
3194          */
3195         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3196              i++) {
3197                 if (obj->page_cpu_valid[i])
3198                         continue;
3199
3200                 drm_clflush_pages(obj->pages + i, 1);
3201
3202                 obj->page_cpu_valid[i] = 1;
3203         }
3204
3205         /* It should now be out of any other write domains, and we can update
3206          * the domain values for our changes.
3207          */
3208         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3209
3210         old_read_domains = obj->base.read_domains;
3211         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3212
3213         trace_i915_gem_object_change_domain(obj,
3214                                             old_read_domains,
3215                                             obj->base.write_domain);
3216
3217         return 0;
3218 }
3219
3220 /* Throttle our rendering by waiting until the ring has completed our requests
3221  * emitted over 20 msec ago.
3222  *
3223  * Note that if we were to use the current jiffies each time around the loop,
3224  * we wouldn't escape the function with any frames outstanding if the time to
3225  * render a frame was over 20ms.
3226  *
3227  * This should get us reasonable parallelism between CPU and GPU but also
3228  * relatively low latency when blocking on a particular request to finish.
3229  */
3230 static int
3231 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3232 {
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         struct drm_i915_file_private *file_priv = file->driver_priv;
3235         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3236         struct drm_i915_gem_request *request;
3237         struct intel_ring_buffer *ring = NULL;
3238         u32 seqno = 0;
3239         int ret;
3240
3241         if (atomic_read(&dev_priv->mm.wedged))
3242                 return -EIO;
3243
3244         spin_lock(&file_priv->mm.lock);
3245         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3246                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3247                         break;
3248
3249                 ring = request->ring;
3250                 seqno = request->seqno;
3251         }
3252         spin_unlock(&file_priv->mm.lock);
3253
3254         if (seqno == 0)
3255                 return 0;
3256
3257         ret = 0;
3258         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3259                 /* And wait for the seqno passing without holding any locks and
3260                  * causing extra latency for others. This is safe as the irq
3261                  * generation is designed to be run atomically and so is
3262                  * lockless.
3263                  */
3264                 if (ring->irq_get(ring)) {
3265                         ret = wait_event_interruptible(ring->irq_queue,
3266                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3267                                                        || atomic_read(&dev_priv->mm.wedged));
3268                         ring->irq_put(ring);
3269
3270                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3271                                 ret = -EIO;
3272                 }
3273         }
3274
3275         if (ret == 0)
3276                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3277
3278         return ret;
3279 }
3280
3281 int
3282 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3283                     uint32_t alignment,
3284                     bool map_and_fenceable)
3285 {
3286         struct drm_device *dev = obj->base.dev;
3287         struct drm_i915_private *dev_priv = dev->dev_private;
3288         int ret;
3289
3290         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3291         WARN_ON(i915_verify_lists(dev));
3292
3293         if (obj->gtt_space != NULL) {
3294                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3295                     (map_and_fenceable && !obj->map_and_fenceable)) {
3296                         WARN(obj->pin_count,
3297                              "bo is already pinned with incorrect alignment:"
3298                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3299                              " obj->map_and_fenceable=%d\n",
3300                              obj->gtt_offset, alignment,
3301                              map_and_fenceable,
3302                              obj->map_and_fenceable);
3303                         ret = i915_gem_object_unbind(obj);
3304                         if (ret)
3305                                 return ret;
3306                 }
3307         }
3308
3309         if (obj->gtt_space == NULL) {
3310                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3311                                                   map_and_fenceable);
3312                 if (ret)
3313                         return ret;
3314         }
3315
3316         if (obj->pin_count++ == 0) {
3317                 if (!obj->active)
3318                         list_move_tail(&obj->mm_list,
3319                                        &dev_priv->mm.pinned_list);
3320         }
3321         obj->pin_mappable |= map_and_fenceable;
3322
3323         WARN_ON(i915_verify_lists(dev));
3324         return 0;
3325 }
3326
3327 void
3328 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3329 {
3330         struct drm_device *dev = obj->base.dev;
3331         drm_i915_private_t *dev_priv = dev->dev_private;
3332
3333         WARN_ON(i915_verify_lists(dev));
3334         BUG_ON(obj->pin_count == 0);
3335         BUG_ON(obj->gtt_space == NULL);
3336
3337         if (--obj->pin_count == 0) {
3338                 if (!obj->active)
3339                         list_move_tail(&obj->mm_list,
3340                                        &dev_priv->mm.inactive_list);
3341                 obj->pin_mappable = false;
3342         }
3343         WARN_ON(i915_verify_lists(dev));
3344 }
3345
3346 int
3347 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3348                    struct drm_file *file)
3349 {
3350         struct drm_i915_gem_pin *args = data;
3351         struct drm_i915_gem_object *obj;
3352         int ret;
3353
3354         ret = i915_mutex_lock_interruptible(dev);
3355         if (ret)
3356                 return ret;
3357
3358         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3359         if (&obj->base == NULL) {
3360                 ret = -ENOENT;
3361                 goto unlock;
3362         }
3363
3364         if (obj->madv != I915_MADV_WILLNEED) {
3365                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3366                 ret = -EINVAL;
3367                 goto out;
3368         }
3369
3370         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3371                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3372                           args->handle);
3373                 ret = -EINVAL;
3374                 goto out;
3375         }
3376
3377         obj->user_pin_count++;
3378         obj->pin_filp = file;
3379         if (obj->user_pin_count == 1) {
3380                 ret = i915_gem_object_pin(obj, args->alignment, true);
3381                 if (ret)
3382                         goto out;
3383         }
3384
3385         /* XXX - flush the CPU caches for pinned objects
3386          * as the X server doesn't manage domains yet
3387          */
3388         i915_gem_object_flush_cpu_write_domain(obj);
3389         args->offset = obj->gtt_offset;
3390 out:
3391         drm_gem_object_unreference(&obj->base);
3392 unlock:
3393         mutex_unlock(&dev->struct_mutex);
3394         return ret;
3395 }
3396
3397 int
3398 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3399                      struct drm_file *file)
3400 {
3401         struct drm_i915_gem_pin *args = data;
3402         struct drm_i915_gem_object *obj;
3403         int ret;
3404
3405         ret = i915_mutex_lock_interruptible(dev);
3406         if (ret)
3407                 return ret;
3408
3409         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3410         if (&obj->base == NULL) {
3411                 ret = -ENOENT;
3412                 goto unlock;
3413         }
3414
3415         if (obj->pin_filp != file) {
3416                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3417                           args->handle);
3418                 ret = -EINVAL;
3419                 goto out;
3420         }
3421         obj->user_pin_count--;
3422         if (obj->user_pin_count == 0) {
3423                 obj->pin_filp = NULL;
3424                 i915_gem_object_unpin(obj);
3425         }
3426
3427 out:
3428         drm_gem_object_unreference(&obj->base);
3429 unlock:
3430         mutex_unlock(&dev->struct_mutex);
3431         return ret;
3432 }
3433
3434 int
3435 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3436                     struct drm_file *file)
3437 {
3438         struct drm_i915_gem_busy *args = data;
3439         struct drm_i915_gem_object *obj;
3440         int ret;
3441
3442         ret = i915_mutex_lock_interruptible(dev);
3443         if (ret)
3444                 return ret;
3445
3446         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3447         if (&obj->base == NULL) {
3448                 ret = -ENOENT;
3449                 goto unlock;
3450         }
3451
3452         /* Count all active objects as busy, even if they are currently not used
3453          * by the gpu. Users of this interface expect objects to eventually
3454          * become non-busy without any further actions, therefore emit any
3455          * necessary flushes here.
3456          */
3457         args->busy = obj->active;
3458         if (args->busy) {
3459                 /* Unconditionally flush objects, even when the gpu still uses this
3460                  * object. Userspace calling this function indicates that it wants to
3461                  * use this buffer rather sooner than later, so issuing the required
3462                  * flush earlier is beneficial.
3463                  */
3464                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3465                         ret = i915_gem_flush_ring(obj->ring,
3466                                                   0, obj->base.write_domain);
3467                 } else if (obj->ring->outstanding_lazy_request ==
3468                            obj->last_rendering_seqno) {
3469                         struct drm_i915_gem_request *request;
3470
3471                         /* This ring is not being cleared by active usage,
3472                          * so emit a request to do so.
3473                          */
3474                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3475                         if (request)
3476                                 ret = i915_add_request(obj->ring, NULL,request);
3477                         else
3478                                 ret = -ENOMEM;
3479                 }
3480
3481                 /* Update the active list for the hardware's current position.
3482                  * Otherwise this only updates on a delayed timer or when irqs
3483                  * are actually unmasked, and our working set ends up being
3484                  * larger than required.
3485                  */
3486                 i915_gem_retire_requests_ring(obj->ring);
3487
3488                 args->busy = obj->active;
3489         }
3490
3491         drm_gem_object_unreference(&obj->base);
3492 unlock:
3493         mutex_unlock(&dev->struct_mutex);
3494         return ret;
3495 }
3496
3497 int
3498 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3499                         struct drm_file *file_priv)
3500 {
3501     return i915_gem_ring_throttle(dev, file_priv);
3502 }
3503
3504 int
3505 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3506                        struct drm_file *file_priv)
3507 {
3508         struct drm_i915_gem_madvise *args = data;
3509         struct drm_i915_gem_object *obj;
3510         int ret;
3511
3512         switch (args->madv) {
3513         case I915_MADV_DONTNEED:
3514         case I915_MADV_WILLNEED:
3515             break;
3516         default:
3517             return -EINVAL;
3518         }
3519
3520         ret = i915_mutex_lock_interruptible(dev);
3521         if (ret)
3522                 return ret;
3523
3524         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3525         if (&obj->base == NULL) {
3526                 ret = -ENOENT;
3527                 goto unlock;
3528         }
3529
3530         if (obj->pin_count) {
3531                 ret = -EINVAL;
3532                 goto out;
3533         }
3534
3535         if (obj->madv != __I915_MADV_PURGED)
3536                 obj->madv = args->madv;
3537
3538         /* if the object is no longer bound, discard its backing storage */
3539         if (i915_gem_object_is_purgeable(obj) &&
3540             obj->gtt_space == NULL)
3541                 i915_gem_object_truncate(obj);
3542
3543         args->retained = obj->madv != __I915_MADV_PURGED;
3544
3545 out:
3546         drm_gem_object_unreference(&obj->base);
3547 unlock:
3548         mutex_unlock(&dev->struct_mutex);
3549         return ret;
3550 }
3551
3552 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3553                                                   size_t size)
3554 {
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556         struct drm_i915_gem_object *obj;
3557
3558         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3559         if (obj == NULL)
3560                 return NULL;
3561
3562         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3563                 kfree(obj);
3564                 return NULL;
3565         }
3566
3567         i915_gem_info_add_obj(dev_priv, size);
3568
3569         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3570         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3571
3572         obj->agp_type = AGP_USER_MEMORY;
3573         obj->base.driver_private = NULL;
3574         obj->fence_reg = I915_FENCE_REG_NONE;
3575         INIT_LIST_HEAD(&obj->mm_list);
3576         INIT_LIST_HEAD(&obj->gtt_list);
3577         INIT_LIST_HEAD(&obj->ring_list);
3578         INIT_LIST_HEAD(&obj->exec_list);
3579         INIT_LIST_HEAD(&obj->gpu_write_list);
3580         obj->madv = I915_MADV_WILLNEED;
3581         /* Avoid an unnecessary call to unbind on the first bind. */
3582         obj->map_and_fenceable = true;
3583
3584         return obj;
3585 }
3586
3587 int i915_gem_init_object(struct drm_gem_object *obj)
3588 {
3589         BUG();
3590
3591         return 0;
3592 }
3593
3594 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3595 {
3596         struct drm_device *dev = obj->base.dev;
3597         drm_i915_private_t *dev_priv = dev->dev_private;
3598         int ret;
3599
3600         ret = i915_gem_object_unbind(obj);
3601         if (ret == -ERESTARTSYS) {
3602                 list_move(&obj->mm_list,
3603                           &dev_priv->mm.deferred_free_list);
3604                 return;
3605         }
3606
3607         trace_i915_gem_object_destroy(obj);
3608
3609         if (obj->base.map_list.map)
3610                 i915_gem_free_mmap_offset(obj);
3611
3612         drm_gem_object_release(&obj->base);
3613         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3614
3615         kfree(obj->page_cpu_valid);
3616         kfree(obj->bit_17);
3617         kfree(obj);
3618 }
3619
3620 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3621 {
3622         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3623         struct drm_device *dev = obj->base.dev;
3624
3625         while (obj->pin_count > 0)
3626                 i915_gem_object_unpin(obj);
3627
3628         if (obj->phys_obj)
3629                 i915_gem_detach_phys_object(dev, obj);
3630
3631         i915_gem_free_object_tail(obj);
3632 }
3633
3634 int
3635 i915_gem_idle(struct drm_device *dev)
3636 {
3637         drm_i915_private_t *dev_priv = dev->dev_private;
3638         int ret;
3639
3640         mutex_lock(&dev->struct_mutex);
3641
3642         if (dev_priv->mm.suspended) {
3643                 mutex_unlock(&dev->struct_mutex);
3644                 return 0;
3645         }
3646
3647         ret = i915_gpu_idle(dev);
3648         if (ret) {
3649                 mutex_unlock(&dev->struct_mutex);
3650                 return ret;
3651         }
3652
3653         /* Under UMS, be paranoid and evict. */
3654         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3655                 ret = i915_gem_evict_inactive(dev, false);
3656                 if (ret) {
3657                         mutex_unlock(&dev->struct_mutex);
3658                         return ret;
3659                 }
3660         }
3661
3662         i915_gem_reset_fences(dev);
3663
3664         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3665          * We need to replace this with a semaphore, or something.
3666          * And not confound mm.suspended!
3667          */
3668         dev_priv->mm.suspended = 1;
3669         del_timer_sync(&dev_priv->hangcheck_timer);
3670
3671         i915_kernel_lost_context(dev);
3672         i915_gem_cleanup_ringbuffer(dev);
3673
3674         mutex_unlock(&dev->struct_mutex);
3675
3676         /* Cancel the retire work handler, which should be idle now. */
3677         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3678
3679         return 0;
3680 }
3681
3682 int
3683 i915_gem_init_ringbuffer(struct drm_device *dev)
3684 {
3685         drm_i915_private_t *dev_priv = dev->dev_private;
3686         int ret;
3687
3688         ret = intel_init_render_ring_buffer(dev);
3689         if (ret)
3690                 return ret;
3691
3692         if (HAS_BSD(dev)) {
3693                 ret = intel_init_bsd_ring_buffer(dev);
3694                 if (ret)
3695                         goto cleanup_render_ring;
3696         }
3697
3698         if (HAS_BLT(dev)) {
3699                 ret = intel_init_blt_ring_buffer(dev);
3700                 if (ret)
3701                         goto cleanup_bsd_ring;
3702         }
3703
3704         dev_priv->next_seqno = 1;
3705
3706         return 0;
3707
3708 cleanup_bsd_ring:
3709         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3710 cleanup_render_ring:
3711         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3712         return ret;
3713 }
3714
3715 void
3716 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3717 {
3718         drm_i915_private_t *dev_priv = dev->dev_private;
3719         int i;
3720
3721         for (i = 0; i < I915_NUM_RINGS; i++)
3722                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3723 }
3724
3725 int
3726 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3727                        struct drm_file *file_priv)
3728 {
3729         drm_i915_private_t *dev_priv = dev->dev_private;
3730         int ret, i;
3731
3732         if (drm_core_check_feature(dev, DRIVER_MODESET))
3733                 return 0;
3734
3735         if (atomic_read(&dev_priv->mm.wedged)) {
3736                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3737                 atomic_set(&dev_priv->mm.wedged, 0);
3738         }
3739
3740         mutex_lock(&dev->struct_mutex);
3741         dev_priv->mm.suspended = 0;
3742
3743         ret = i915_gem_init_ringbuffer(dev);
3744         if (ret != 0) {
3745                 mutex_unlock(&dev->struct_mutex);
3746                 return ret;
3747         }
3748
3749         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3750         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3751         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3752         for (i = 0; i < I915_NUM_RINGS; i++) {
3753                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3754                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3755         }
3756         mutex_unlock(&dev->struct_mutex);
3757
3758         ret = drm_irq_install(dev);
3759         if (ret)
3760                 goto cleanup_ringbuffer;
3761
3762         return 0;
3763
3764 cleanup_ringbuffer:
3765         mutex_lock(&dev->struct_mutex);
3766         i915_gem_cleanup_ringbuffer(dev);
3767         dev_priv->mm.suspended = 1;
3768         mutex_unlock(&dev->struct_mutex);
3769
3770         return ret;
3771 }
3772
3773 int
3774 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3775                        struct drm_file *file_priv)
3776 {
3777         if (drm_core_check_feature(dev, DRIVER_MODESET))
3778                 return 0;
3779
3780         drm_irq_uninstall(dev);
3781         return i915_gem_idle(dev);
3782 }
3783
3784 void
3785 i915_gem_lastclose(struct drm_device *dev)
3786 {
3787         int ret;
3788
3789         if (drm_core_check_feature(dev, DRIVER_MODESET))
3790                 return;
3791
3792         ret = i915_gem_idle(dev);
3793         if (ret)
3794                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3795 }
3796
3797 static void
3798 init_ring_lists(struct intel_ring_buffer *ring)
3799 {
3800         INIT_LIST_HEAD(&ring->active_list);
3801         INIT_LIST_HEAD(&ring->request_list);
3802         INIT_LIST_HEAD(&ring->gpu_write_list);
3803 }
3804
3805 void
3806 i915_gem_load(struct drm_device *dev)
3807 {
3808         int i;
3809         drm_i915_private_t *dev_priv = dev->dev_private;
3810
3811         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3812         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3813         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3814         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3815         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3816         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3817         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3818         for (i = 0; i < I915_NUM_RINGS; i++)
3819                 init_ring_lists(&dev_priv->ring[i]);
3820         for (i = 0; i < 16; i++)
3821                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3822         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3823                           i915_gem_retire_work_handler);
3824         init_completion(&dev_priv->error_completion);
3825
3826         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3827         if (IS_GEN3(dev)) {
3828                 u32 tmp = I915_READ(MI_ARB_STATE);
3829                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3830                         /* arb state is a masked write, so set bit + bit in mask */
3831                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3832                         I915_WRITE(MI_ARB_STATE, tmp);
3833                 }
3834         }
3835
3836         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3837
3838         /* Old X drivers will take 0-2 for front, back, depth buffers */
3839         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3840                 dev_priv->fence_reg_start = 3;
3841
3842         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3843                 dev_priv->num_fence_regs = 16;
3844         else
3845                 dev_priv->num_fence_regs = 8;
3846
3847         /* Initialize fence registers to zero */
3848         switch (INTEL_INFO(dev)->gen) {
3849         case 6:
3850                 for (i = 0; i < 16; i++)
3851                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3852                 break;
3853         case 5:
3854         case 4:
3855                 for (i = 0; i < 16; i++)
3856                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3857                 break;
3858         case 3:
3859                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3860                         for (i = 0; i < 8; i++)
3861                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3862         case 2:
3863                 for (i = 0; i < 8; i++)
3864                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3865                 break;
3866         }
3867         i915_gem_detect_bit_6_swizzle(dev);
3868         init_waitqueue_head(&dev_priv->pending_flip_queue);
3869
3870         dev_priv->mm.interruptible = true;
3871
3872         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3873         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3874         register_shrinker(&dev_priv->mm.inactive_shrinker);
3875 }
3876
3877 /*
3878  * Create a physically contiguous memory object for this object
3879  * e.g. for cursor + overlay regs
3880  */
3881 static int i915_gem_init_phys_object(struct drm_device *dev,
3882                                      int id, int size, int align)
3883 {
3884         drm_i915_private_t *dev_priv = dev->dev_private;
3885         struct drm_i915_gem_phys_object *phys_obj;
3886         int ret;
3887
3888         if (dev_priv->mm.phys_objs[id - 1] || !size)
3889                 return 0;
3890
3891         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3892         if (!phys_obj)
3893                 return -ENOMEM;
3894
3895         phys_obj->id = id;
3896
3897         phys_obj->handle = drm_pci_alloc(dev, size, align);
3898         if (!phys_obj->handle) {
3899                 ret = -ENOMEM;
3900                 goto kfree_obj;
3901         }
3902 #ifdef CONFIG_X86
3903         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3904 #endif
3905
3906         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3907
3908         return 0;
3909 kfree_obj:
3910         kfree(phys_obj);
3911         return ret;
3912 }
3913
3914 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3915 {
3916         drm_i915_private_t *dev_priv = dev->dev_private;
3917         struct drm_i915_gem_phys_object *phys_obj;
3918
3919         if (!dev_priv->mm.phys_objs[id - 1])
3920                 return;
3921
3922         phys_obj = dev_priv->mm.phys_objs[id - 1];
3923         if (phys_obj->cur_obj) {
3924                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3925         }
3926
3927 #ifdef CONFIG_X86
3928         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3929 #endif
3930         drm_pci_free(dev, phys_obj->handle);
3931         kfree(phys_obj);
3932         dev_priv->mm.phys_objs[id - 1] = NULL;
3933 }
3934
3935 void i915_gem_free_all_phys_object(struct drm_device *dev)
3936 {
3937         int i;
3938
3939         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3940                 i915_gem_free_phys_object(dev, i);
3941 }
3942
3943 void i915_gem_detach_phys_object(struct drm_device *dev,
3944                                  struct drm_i915_gem_object *obj)
3945 {
3946         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3947         char *vaddr;
3948         int i;
3949         int page_count;
3950
3951         if (!obj->phys_obj)
3952                 return;
3953         vaddr = obj->phys_obj->handle->vaddr;
3954
3955         page_count = obj->base.size / PAGE_SIZE;
3956         for (i = 0; i < page_count; i++) {
3957                 struct page *page = read_cache_page_gfp(mapping, i,
3958                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3959                 if (!IS_ERR(page)) {
3960                         char *dst = kmap_atomic(page);
3961                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3962                         kunmap_atomic(dst);
3963
3964                         drm_clflush_pages(&page, 1);
3965
3966                         set_page_dirty(page);
3967                         mark_page_accessed(page);
3968                         page_cache_release(page);
3969                 }
3970         }
3971         intel_gtt_chipset_flush();
3972
3973         obj->phys_obj->cur_obj = NULL;
3974         obj->phys_obj = NULL;
3975 }
3976
3977 int
3978 i915_gem_attach_phys_object(struct drm_device *dev,
3979                             struct drm_i915_gem_object *obj,
3980                             int id,
3981                             int align)
3982 {
3983         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3984         drm_i915_private_t *dev_priv = dev->dev_private;
3985         int ret = 0;
3986         int page_count;
3987         int i;
3988
3989         if (id > I915_MAX_PHYS_OBJECT)
3990                 return -EINVAL;
3991
3992         if (obj->phys_obj) {
3993                 if (obj->phys_obj->id == id)
3994                         return 0;
3995                 i915_gem_detach_phys_object(dev, obj);
3996         }
3997
3998         /* create a new object */
3999         if (!dev_priv->mm.phys_objs[id - 1]) {
4000                 ret = i915_gem_init_phys_object(dev, id,
4001                                                 obj->base.size, align);
4002                 if (ret) {
4003                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4004                                   id, obj->base.size);
4005                         return ret;
4006                 }
4007         }
4008
4009         /* bind to the object */
4010         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4011         obj->phys_obj->cur_obj = obj;
4012
4013         page_count = obj->base.size / PAGE_SIZE;
4014
4015         for (i = 0; i < page_count; i++) {
4016                 struct page *page;
4017                 char *dst, *src;
4018
4019                 page = read_cache_page_gfp(mapping, i,
4020                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
4021                 if (IS_ERR(page))
4022                         return PTR_ERR(page);
4023
4024                 src = kmap_atomic(page);
4025                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4026                 memcpy(dst, src, PAGE_SIZE);
4027                 kunmap_atomic(src);
4028
4029                 mark_page_accessed(page);
4030                 page_cache_release(page);
4031         }
4032
4033         return 0;
4034 }
4035
4036 static int
4037 i915_gem_phys_pwrite(struct drm_device *dev,
4038                      struct drm_i915_gem_object *obj,
4039                      struct drm_i915_gem_pwrite *args,
4040                      struct drm_file *file_priv)
4041 {
4042         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4043         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4044
4045         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4046                 unsigned long unwritten;
4047
4048                 /* The physical object once assigned is fixed for the lifetime
4049                  * of the obj, so we can safely drop the lock and continue
4050                  * to access vaddr.
4051                  */
4052                 mutex_unlock(&dev->struct_mutex);
4053                 unwritten = copy_from_user(vaddr, user_data, args->size);
4054                 mutex_lock(&dev->struct_mutex);
4055                 if (unwritten)
4056                         return -EFAULT;
4057         }
4058
4059         intel_gtt_chipset_flush();
4060         return 0;
4061 }
4062
4063 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4064 {
4065         struct drm_i915_file_private *file_priv = file->driver_priv;
4066
4067         /* Clean up our request list when the client is going away, so that
4068          * later retire_requests won't dereference our soon-to-be-gone
4069          * file_priv.
4070          */
4071         spin_lock(&file_priv->mm.lock);
4072         while (!list_empty(&file_priv->mm.request_list)) {
4073                 struct drm_i915_gem_request *request;
4074
4075                 request = list_first_entry(&file_priv->mm.request_list,
4076                                            struct drm_i915_gem_request,
4077                                            client_list);
4078                 list_del(&request->client_list);
4079                 request->file_priv = NULL;
4080         }
4081         spin_unlock(&file_priv->mm.lock);
4082 }
4083
4084 static int
4085 i915_gpu_is_active(struct drm_device *dev)
4086 {
4087         drm_i915_private_t *dev_priv = dev->dev_private;
4088         int lists_empty;
4089
4090         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4091                       list_empty(&dev_priv->mm.active_list);
4092
4093         return !lists_empty;
4094 }
4095
4096 static int
4097 i915_gem_inactive_shrink(struct shrinker *shrinker,
4098                          int nr_to_scan,
4099                          gfp_t gfp_mask)
4100 {
4101         struct drm_i915_private *dev_priv =
4102                 container_of(shrinker,
4103                              struct drm_i915_private,
4104                              mm.inactive_shrinker);
4105         struct drm_device *dev = dev_priv->dev;
4106         struct drm_i915_gem_object *obj, *next;
4107         int cnt;
4108
4109         if (!mutex_trylock(&dev->struct_mutex))
4110                 return 0;
4111
4112         /* "fast-path" to count number of available objects */
4113         if (nr_to_scan == 0) {
4114                 cnt = 0;
4115                 list_for_each_entry(obj,
4116                                     &dev_priv->mm.inactive_list,
4117                                     mm_list)
4118                         cnt++;
4119                 mutex_unlock(&dev->struct_mutex);
4120                 return cnt / 100 * sysctl_vfs_cache_pressure;
4121         }
4122
4123 rescan:
4124         /* first scan for clean buffers */
4125         i915_gem_retire_requests(dev);
4126
4127         list_for_each_entry_safe(obj, next,
4128                                  &dev_priv->mm.inactive_list,
4129                                  mm_list) {
4130                 if (i915_gem_object_is_purgeable(obj)) {
4131                         if (i915_gem_object_unbind(obj) == 0 &&
4132                             --nr_to_scan == 0)
4133                                 break;
4134                 }
4135         }
4136
4137         /* second pass, evict/count anything still on the inactive list */
4138         cnt = 0;
4139         list_for_each_entry_safe(obj, next,
4140                                  &dev_priv->mm.inactive_list,
4141                                  mm_list) {
4142                 if (nr_to_scan &&
4143                     i915_gem_object_unbind(obj) == 0)
4144                         nr_to_scan--;
4145                 else
4146                         cnt++;
4147         }
4148
4149         if (nr_to_scan && i915_gpu_is_active(dev)) {
4150                 /*
4151                  * We are desperate for pages, so as a last resort, wait
4152                  * for the GPU to finish and discard whatever we can.
4153                  * This has a dramatic impact to reduce the number of
4154                  * OOM-killer events whilst running the GPU aggressively.
4155                  */
4156                 if (i915_gpu_idle(dev) == 0)
4157                         goto rescan;
4158         }
4159         mutex_unlock(&dev->struct_mutex);
4160         return cnt / 100 * sysctl_vfs_cache_pressure;
4161 }