drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/swap.h>
  35 #include <linux/pci.h>
  36
  37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  38
  39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  43                                              int write);
  44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  45                                                      uint64_t offset,
  46                                                      uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  50                                            unsigned alignment);
  51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
  53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
  54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file_priv);
  57
  58 static LIST_HEAD(shrink_list);
  59 static DEFINE_SPINLOCK(shrink_list_lock);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, start,
  73                     end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94 int
  95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  96                             struct drm_file *file_priv)
  97 {
  98         struct drm_i915_gem_get_aperture *args = data;
  99
 100         if (!(dev->driver->driver_features & DRIVER_GEM))
 101                 return -ENODEV;
 102
 103         args->aper_size = dev->gtt_total;
 104         args->aper_available_size = (args->aper_size -
 105                                      atomic_read(&dev->pin_memory));
 106
 107         return 0;
 108 }
 109
 110
 111 /**
 112  * Creates a new mm object and returns a handle to it.
 113  */
 114 int
 115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 116                       struct drm_file *file_priv)
 117 {
 118         struct drm_i915_gem_create *args = data;
 119         struct drm_gem_object *obj;
 120         int ret;
 121         u32 handle;
 122
 123         args->size = roundup(args->size, PAGE_SIZE);
 124
 125         /* Allocate the new object */
 126         obj = drm_gem_object_alloc(dev, args->size);
 127         if (obj == NULL)
 128                 return -ENOMEM;
 129
 130         ret = drm_gem_handle_create(file_priv, obj, &handle);
 131         drm_gem_object_handle_unreference_unlocked(obj);
 132
 133         if (ret)
 134                 return ret;
 135
 136         args->handle = handle;
 137
 138         return 0;
 139 }
 140
 141 static inline int
 142 fast_shmem_read(struct page **pages,
 143                 loff_t page_base, int page_offset,
 144                 char __user *data,
 145                 int length)
 146 {
 147         char __iomem *vaddr;
 148         int unwritten;
 149
 150         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 151         if (vaddr == NULL)
 152                 return -ENOMEM;
 153         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 154         kunmap_atomic(vaddr, KM_USER0);
 155
 156         if (unwritten)
 157                 return -EFAULT;
 158
 159         return 0;
 160 }
 161
 162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 163 {
 164         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 165         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 166
 167         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 168                 obj_priv->tiling_mode != I915_TILING_NONE;
 169 }
 170
 171 static inline int
 172 slow_shmem_copy(struct page *dst_page,
 173                 int dst_offset,
 174                 struct page *src_page,
 175                 int src_offset,
 176                 int length)
 177 {
 178         char *dst_vaddr, *src_vaddr;
 179
 180         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
 181         if (dst_vaddr == NULL)
 182                 return -ENOMEM;
 183
 184         src_vaddr = kmap_atomic(src_page, KM_USER1);
 185         if (src_vaddr == NULL) {
 186                 kunmap_atomic(dst_vaddr, KM_USER0);
 187                 return -ENOMEM;
 188         }
 189
 190         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 191
 192         kunmap_atomic(src_vaddr, KM_USER1);
 193         kunmap_atomic(dst_vaddr, KM_USER0);
 194
 195         return 0;
 196 }
 197
 198 static inline int
 199 slow_shmem_bit17_copy(struct page *gpu_page,
 200                       int gpu_offset,
 201                       struct page *cpu_page,
 202                       int cpu_offset,
 203                       int length,
 204                       int is_read)
 205 {
 206         char *gpu_vaddr, *cpu_vaddr;
 207
 208         /* Use the unswizzled path if this page isn't affected. */
 209         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 210                 if (is_read)
 211                         return slow_shmem_copy(cpu_page, cpu_offset,
 212                                                gpu_page, gpu_offset, length);
 213                 else
 214                         return slow_shmem_copy(gpu_page, gpu_offset,
 215                                                cpu_page, cpu_offset, length);
 216         }
 217
 218         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
 219         if (gpu_vaddr == NULL)
 220                 return -ENOMEM;
 221
 222         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
 223         if (cpu_vaddr == NULL) {
 224                 kunmap_atomic(gpu_vaddr, KM_USER0);
 225                 return -ENOMEM;
 226         }
 227
 228         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 229          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 230          */
 231         while (length > 0) {
 232                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 233                 int this_length = min(cacheline_end - gpu_offset, length);
 234                 int swizzled_gpu_offset = gpu_offset ^ 64;
 235
 236                 if (is_read) {
 237                         memcpy(cpu_vaddr + cpu_offset,
 238                                gpu_vaddr + swizzled_gpu_offset,
 239                                this_length);
 240                 } else {
 241                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 242                                cpu_vaddr + cpu_offset,
 243                                this_length);
 244                 }
 245                 cpu_offset += this_length;
 246                 gpu_offset += this_length;
 247                 length -= this_length;
 248         }
 249
 250         kunmap_atomic(cpu_vaddr, KM_USER1);
 251         kunmap_atomic(gpu_vaddr, KM_USER0);
 252
 253         return 0;
 254 }
 255
 256 /**
 257  * This is the fast shmem pread path, which attempts to copy_from_user directly
 258  * from the backing pages of the object to the user's address space.  On a
 259  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 260  */
 261 static int
 262 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 263                           struct drm_i915_gem_pread *args,
 264                           struct drm_file *file_priv)
 265 {
 266         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 267         ssize_t remain;
 268         loff_t offset, page_base;
 269         char __user *user_data;
 270         int page_offset, page_length;
 271         int ret;
 272
 273         user_data = (char __user *) (uintptr_t) args->data_ptr;
 274         remain = args->size;
 275
 276         mutex_lock(&dev->struct_mutex);
 277
 278         ret = i915_gem_object_get_pages(obj, 0);
 279         if (ret != 0)
 280                 goto fail_unlock;
 281
 282         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 283                                                         args->size);
 284         if (ret != 0)
 285                 goto fail_put_pages;
 286
 287         obj_priv = obj->driver_private;
 288         offset = args->offset;
 289
 290         while (remain > 0) {
 291                 /* Operation in this page
 292                  *
 293                  * page_base = page offset within aperture
 294                  * page_offset = offset within page
 295                  * page_length = bytes to copy for this page
 296                  */
 297                 page_base = (offset & ~(PAGE_SIZE-1));
 298                 page_offset = offset & (PAGE_SIZE-1);
 299                 page_length = remain;
 300                 if ((page_offset + remain) > PAGE_SIZE)
 301                         page_length = PAGE_SIZE - page_offset;
 302
 303                 ret = fast_shmem_read(obj_priv->pages,
 304                                       page_base, page_offset,
 305                                       user_data, page_length);
 306                 if (ret)
 307                         goto fail_put_pages;
 308
 309                 remain -= page_length;
 310                 user_data += page_length;
 311                 offset += page_length;
 312         }
 313
 314 fail_put_pages:
 315         i915_gem_object_put_pages(obj);
 316 fail_unlock:
 317         mutex_unlock(&dev->struct_mutex);
 318
 319         return ret;
 320 }
 321
 322 static int
 323 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 324 {
 325         int ret;
 326
 327         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 328
 329         /* If we've insufficient memory to map in the pages, attempt
 330          * to make some space by throwing out some old buffers.
 331          */
 332         if (ret == -ENOMEM) {
 333                 struct drm_device *dev = obj->dev;
 334
 335                 ret = i915_gem_evict_something(dev, obj->size);
 336                 if (ret)
 337                         return ret;
 338
 339                 ret = i915_gem_object_get_pages(obj, 0);
 340         }
 341
 342         return ret;
 343 }
 344
 345 /**
 346  * This is the fallback shmem pread path, which allocates temporary storage
 347  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 348  * can copy out of the object's backing pages while holding the struct mutex
 349  * and not take page faults.
 350  */
 351 static int
 352 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 353                           struct drm_i915_gem_pread *args,
 354                           struct drm_file *file_priv)
 355 {
 356         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 357         struct mm_struct *mm = current->mm;
 358         struct page **user_pages;
 359         ssize_t remain;
 360         loff_t offset, pinned_pages, i;
 361         loff_t first_data_page, last_data_page, num_pages;
 362         int shmem_page_index, shmem_page_offset;
 363         int data_page_index,  data_page_offset;
 364         int page_length;
 365         int ret;
 366         uint64_t data_ptr = args->data_ptr;
 367         int do_bit17_swizzling;
 368
 369         remain = args->size;
 370
 371         /* Pin the user pages containing the data.  We can't fault while
 372          * holding the struct mutex, yet we want to hold it while
 373          * dereferencing the user data.
 374          */
 375         first_data_page = data_ptr / PAGE_SIZE;
 376         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 377         num_pages = last_data_page - first_data_page + 1;
 378
 379         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 380         if (user_pages == NULL)
 381                 return -ENOMEM;
 382
 383         down_read(&mm->mmap_sem);
 384         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 385                                       num_pages, 1, 0, user_pages, NULL);
 386         up_read(&mm->mmap_sem);
 387         if (pinned_pages < num_pages) {
 388                 ret = -EFAULT;
 389                 goto fail_put_user_pages;
 390         }
 391
 392         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 393
 394         mutex_lock(&dev->struct_mutex);
 395
 396         ret = i915_gem_object_get_pages_or_evict(obj);
 397         if (ret)
 398                 goto fail_unlock;
 399
 400         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 401                                                         args->size);
 402         if (ret != 0)
 403                 goto fail_put_pages;
 404
 405         obj_priv = obj->driver_private;
 406         offset = args->offset;
 407
 408         while (remain > 0) {
 409                 /* Operation in this page
 410                  *
 411                  * shmem_page_index = page number within shmem file
 412                  * shmem_page_offset = offset within page in shmem file
 413                  * data_page_index = page number in get_user_pages return
 414                  * data_page_offset = offset with data_page_index page.
 415                  * page_length = bytes to copy for this page
 416                  */
 417                 shmem_page_index = offset / PAGE_SIZE;
 418                 shmem_page_offset = offset & ~PAGE_MASK;
 419                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 420                 data_page_offset = data_ptr & ~PAGE_MASK;
 421
 422                 page_length = remain;
 423                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 424                         page_length = PAGE_SIZE - shmem_page_offset;
 425                 if ((data_page_offset + page_length) > PAGE_SIZE)
 426                         page_length = PAGE_SIZE - data_page_offset;
 427
 428                 if (do_bit17_swizzling) {
 429                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 430                                                     shmem_page_offset,
 431                                                     user_pages[data_page_index],
 432                                                     data_page_offset,
 433                                                     page_length,
 434                                                     1);
 435                 } else {
 436                         ret = slow_shmem_copy(user_pages[data_page_index],
 437                                               data_page_offset,
 438                                               obj_priv->pages[shmem_page_index],
 439                                               shmem_page_offset,
 440                                               page_length);
 441                 }
 442                 if (ret)
 443                         goto fail_put_pages;
 444
 445                 remain -= page_length;
 446                 data_ptr += page_length;
 447                 offset += page_length;
 448         }
 449
 450 fail_put_pages:
 451         i915_gem_object_put_pages(obj);
 452 fail_unlock:
 453         mutex_unlock(&dev->struct_mutex);
 454 fail_put_user_pages:
 455         for (i = 0; i < pinned_pages; i++) {
 456                 SetPageDirty(user_pages[i]);
 457                 page_cache_release(user_pages[i]);
 458         }
 459         drm_free_large(user_pages);
 460
 461         return ret;
 462 }
 463
 464 /**
 465  * Reads data from the object referenced by handle.
 466  *
 467  * On error, the contents of *data are undefined.
 468  */
 469 int
 470 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 471                      struct drm_file *file_priv)
 472 {
 473         struct drm_i915_gem_pread *args = data;
 474         struct drm_gem_object *obj;
 475         struct drm_i915_gem_object *obj_priv;
 476         int ret;
 477
 478         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 479         if (obj == NULL)
 480                 return -EBADF;
 481         obj_priv = obj->driver_private;
 482
 483         /* Bounds check source.
 484          *
 485          * XXX: This could use review for overflow issues...
 486          */
 487         if (args->offset > obj->size || args->size > obj->size ||
 488             args->offset + args->size > obj->size) {
 489                 drm_gem_object_unreference_unlocked(obj);
 490                 return -EINVAL;
 491         }
 492
 493         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 494                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 495         } else {
 496                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 497                 if (ret != 0)
 498                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 499                                                         file_priv);
 500         }
 501
 502         drm_gem_object_unreference_unlocked(obj);
 503
 504         return ret;
 505 }
 506
 507 /* This is the fast write path which cannot handle
 508  * page faults in the source data
 509  */
 510
 511 static inline int
 512 fast_user_write(struct io_mapping *mapping,
 513                 loff_t page_base, int page_offset,
 514                 char __user *user_data,
 515                 int length)
 516 {
 517         char *vaddr_atomic;
 518         unsigned long unwritten;
 519
 520         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 521         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 522                                                       user_data, length);
 523         io_mapping_unmap_atomic(vaddr_atomic);
 524         if (unwritten)
 525                 return -EFAULT;
 526         return 0;
 527 }
 528
 529 /* Here's the write path which can sleep for
 530  * page faults
 531  */
 532
 533 static inline int
 534 slow_kernel_write(struct io_mapping *mapping,
 535                   loff_t gtt_base, int gtt_offset,
 536                   struct page *user_page, int user_offset,
 537                   int length)
 538 {
 539         char *src_vaddr, *dst_vaddr;
 540         unsigned long unwritten;
 541
 542         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
 543         src_vaddr = kmap_atomic(user_page, KM_USER1);
 544         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
 545                                                       src_vaddr + user_offset,
 546                                                       length);
 547         kunmap_atomic(src_vaddr, KM_USER1);
 548         io_mapping_unmap_atomic(dst_vaddr);
 549         if (unwritten)
 550                 return -EFAULT;
 551         return 0;
 552 }
 553
 554 static inline int
 555 fast_shmem_write(struct page **pages,
 556                  loff_t page_base, int page_offset,
 557                  char __user *data,
 558                  int length)
 559 {
 560         char __iomem *vaddr;
 561         unsigned long unwritten;
 562
 563         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 564         if (vaddr == NULL)
 565                 return -ENOMEM;
 566         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 567         kunmap_atomic(vaddr, KM_USER0);
 568
 569         if (unwritten)
 570                 return -EFAULT;
 571         return 0;
 572 }
 573
 574 /**
 575  * This is the fast pwrite path, where we copy the data directly from the
 576  * user into the GTT, uncached.
 577  */
 578 static int
 579 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 580                          struct drm_i915_gem_pwrite *args,
 581                          struct drm_file *file_priv)
 582 {
 583         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 584         drm_i915_private_t *dev_priv = dev->dev_private;
 585         ssize_t remain;
 586         loff_t offset, page_base;
 587         char __user *user_data;
 588         int page_offset, page_length;
 589         int ret;
 590
 591         user_data = (char __user *) (uintptr_t) args->data_ptr;
 592         remain = args->size;
 593         if (!access_ok(VERIFY_READ, user_data, remain))
 594                 return -EFAULT;
 595
 596
 597         mutex_lock(&dev->struct_mutex);
 598         ret = i915_gem_object_pin(obj, 0);
 599         if (ret) {
 600                 mutex_unlock(&dev->struct_mutex);
 601                 return ret;
 602         }
 603         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 604         if (ret)
 605                 goto fail;
 606
 607         obj_priv = obj->driver_private;
 608         offset = obj_priv->gtt_offset + args->offset;
 609
 610         while (remain > 0) {
 611                 /* Operation in this page
 612                  *
 613                  * page_base = page offset within aperture
 614                  * page_offset = offset within page
 615                  * page_length = bytes to copy for this page
 616                  */
 617                 page_base = (offset & ~(PAGE_SIZE-1));
 618                 page_offset = offset & (PAGE_SIZE-1);
 619                 page_length = remain;
 620                 if ((page_offset + remain) > PAGE_SIZE)
 621                         page_length = PAGE_SIZE - page_offset;
 622
 623                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 624                                        page_offset, user_data, page_length);
 625
 626                 /* If we get a fault while copying data, then (presumably) our
 627                  * source page isn't available.  Return the error and we'll
 628                  * retry in the slow path.
 629                  */
 630                 if (ret)
 631                         goto fail;
 632
 633                 remain -= page_length;
 634                 user_data += page_length;
 635                 offset += page_length;
 636         }
 637
 638 fail:
 639         i915_gem_object_unpin(obj);
 640         mutex_unlock(&dev->struct_mutex);
 641
 642         return ret;
 643 }
 644
 645 /**
 646  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 647  * the memory and maps it using kmap_atomic for copying.
 648  *
 649  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 650  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 651  */
 652 static int
 653 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 654                          struct drm_i915_gem_pwrite *args,
 655                          struct drm_file *file_priv)
 656 {
 657         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 658         drm_i915_private_t *dev_priv = dev->dev_private;
 659         ssize_t remain;
 660         loff_t gtt_page_base, offset;
 661         loff_t first_data_page, last_data_page, num_pages;
 662         loff_t pinned_pages, i;
 663         struct page **user_pages;
 664         struct mm_struct *mm = current->mm;
 665         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 666         int ret;
 667         uint64_t data_ptr = args->data_ptr;
 668
 669         remain = args->size;
 670
 671         /* Pin the user pages containing the data.  We can't fault while
 672          * holding the struct mutex, and all of the pwrite implementations
 673          * want to hold it while dereferencing the user data.
 674          */
 675         first_data_page = data_ptr / PAGE_SIZE;
 676         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 677         num_pages = last_data_page - first_data_page + 1;
 678
 679         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 680         if (user_pages == NULL)
 681                 return -ENOMEM;
 682
 683         down_read(&mm->mmap_sem);
 684         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 685                                       num_pages, 0, 0, user_pages, NULL);
 686         up_read(&mm->mmap_sem);
 687         if (pinned_pages < num_pages) {
 688                 ret = -EFAULT;
 689                 goto out_unpin_pages;
 690         }
 691
 692         mutex_lock(&dev->struct_mutex);
 693         ret = i915_gem_object_pin(obj, 0);
 694         if (ret)
 695                 goto out_unlock;
 696
 697         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 698         if (ret)
 699                 goto out_unpin_object;
 700
 701         obj_priv = obj->driver_private;
 702         offset = obj_priv->gtt_offset + args->offset;
 703
 704         while (remain > 0) {
 705                 /* Operation in this page
 706                  *
 707                  * gtt_page_base = page offset within aperture
 708                  * gtt_page_offset = offset within page in aperture
 709                  * data_page_index = page number in get_user_pages return
 710                  * data_page_offset = offset with data_page_index page.
 711                  * page_length = bytes to copy for this page
 712                  */
 713                 gtt_page_base = offset & PAGE_MASK;
 714                 gtt_page_offset = offset & ~PAGE_MASK;
 715                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 716                 data_page_offset = data_ptr & ~PAGE_MASK;
 717
 718                 page_length = remain;
 719                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 720                         page_length = PAGE_SIZE - gtt_page_offset;
 721                 if ((data_page_offset + page_length) > PAGE_SIZE)
 722                         page_length = PAGE_SIZE - data_page_offset;
 723
 724                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
 725                                         gtt_page_base, gtt_page_offset,
 726                                         user_pages[data_page_index],
 727                                         data_page_offset,
 728                                         page_length);
 729
 730                 /* If we get a fault while copying data, then (presumably) our
 731                  * source page isn't available.  Return the error and we'll
 732                  * retry in the slow path.
 733                  */
 734                 if (ret)
 735                         goto out_unpin_object;
 736
 737                 remain -= page_length;
 738                 offset += page_length;
 739                 data_ptr += page_length;
 740         }
 741
 742 out_unpin_object:
 743         i915_gem_object_unpin(obj);
 744 out_unlock:
 745         mutex_unlock(&dev->struct_mutex);
 746 out_unpin_pages:
 747         for (i = 0; i < pinned_pages; i++)
 748                 page_cache_release(user_pages[i]);
 749         drm_free_large(user_pages);
 750
 751         return ret;
 752 }
 753
 754 /**
 755  * This is the fast shmem pwrite path, which attempts to directly
 756  * copy_from_user into the kmapped pages backing the object.
 757  */
 758 static int
 759 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 760                            struct drm_i915_gem_pwrite *args,
 761                            struct drm_file *file_priv)
 762 {
 763         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 764         ssize_t remain;
 765         loff_t offset, page_base;
 766         char __user *user_data;
 767         int page_offset, page_length;
 768         int ret;
 769
 770         user_data = (char __user *) (uintptr_t) args->data_ptr;
 771         remain = args->size;
 772
 773         mutex_lock(&dev->struct_mutex);
 774
 775         ret = i915_gem_object_get_pages(obj, 0);
 776         if (ret != 0)
 777                 goto fail_unlock;
 778
 779         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 780         if (ret != 0)
 781                 goto fail_put_pages;
 782
 783         obj_priv = obj->driver_private;
 784         offset = args->offset;
 785         obj_priv->dirty = 1;
 786
 787         while (remain > 0) {
 788                 /* Operation in this page
 789                  *
 790                  * page_base = page offset within aperture
 791                  * page_offset = offset within page
 792                  * page_length = bytes to copy for this page
 793                  */
 794                 page_base = (offset & ~(PAGE_SIZE-1));
 795                 page_offset = offset & (PAGE_SIZE-1);
 796                 page_length = remain;
 797                 if ((page_offset + remain) > PAGE_SIZE)
 798                         page_length = PAGE_SIZE - page_offset;
 799
 800                 ret = fast_shmem_write(obj_priv->pages,
 801                                        page_base, page_offset,
 802                                        user_data, page_length);
 803                 if (ret)
 804                         goto fail_put_pages;
 805
 806                 remain -= page_length;
 807                 user_data += page_length;
 808                 offset += page_length;
 809         }
 810
 811 fail_put_pages:
 812         i915_gem_object_put_pages(obj);
 813 fail_unlock:
 814         mutex_unlock(&dev->struct_mutex);
 815
 816         return ret;
 817 }
 818
 819 /**
 820  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 821  * the memory and maps it using kmap_atomic for copying.
 822  *
 823  * This avoids taking mmap_sem for faulting on the user's address while the
 824  * struct_mutex is held.
 825  */
 826 static int
 827 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 828                            struct drm_i915_gem_pwrite *args,
 829                            struct drm_file *file_priv)
 830 {
 831         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 832         struct mm_struct *mm = current->mm;
 833         struct page **user_pages;
 834         ssize_t remain;
 835         loff_t offset, pinned_pages, i;
 836         loff_t first_data_page, last_data_page, num_pages;
 837         int shmem_page_index, shmem_page_offset;
 838         int data_page_index,  data_page_offset;
 839         int page_length;
 840         int ret;
 841         uint64_t data_ptr = args->data_ptr;
 842         int do_bit17_swizzling;
 843
 844         remain = args->size;
 845
 846         /* Pin the user pages containing the data.  We can't fault while
 847          * holding the struct mutex, and all of the pwrite implementations
 848          * want to hold it while dereferencing the user data.
 849          */
 850         first_data_page = data_ptr / PAGE_SIZE;
 851         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 852         num_pages = last_data_page - first_data_page + 1;
 853
 854         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 855         if (user_pages == NULL)
 856                 return -ENOMEM;
 857
 858         down_read(&mm->mmap_sem);
 859         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 860                                       num_pages, 0, 0, user_pages, NULL);
 861         up_read(&mm->mmap_sem);
 862         if (pinned_pages < num_pages) {
 863                 ret = -EFAULT;
 864                 goto fail_put_user_pages;
 865         }
 866
 867         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 868
 869         mutex_lock(&dev->struct_mutex);
 870
 871         ret = i915_gem_object_get_pages_or_evict(obj);
 872         if (ret)
 873                 goto fail_unlock;
 874
 875         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 876         if (ret != 0)
 877                 goto fail_put_pages;
 878
 879         obj_priv = obj->driver_private;
 880         offset = args->offset;
 881         obj_priv->dirty = 1;
 882
 883         while (remain > 0) {
 884                 /* Operation in this page
 885                  *
 886                  * shmem_page_index = page number within shmem file
 887                  * shmem_page_offset = offset within page in shmem file
 888                  * data_page_index = page number in get_user_pages return
 889                  * data_page_offset = offset with data_page_index page.
 890                  * page_length = bytes to copy for this page
 891                  */
 892                 shmem_page_index = offset / PAGE_SIZE;
 893                 shmem_page_offset = offset & ~PAGE_MASK;
 894                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 895                 data_page_offset = data_ptr & ~PAGE_MASK;
 896
 897                 page_length = remain;
 898                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 899                         page_length = PAGE_SIZE - shmem_page_offset;
 900                 if ((data_page_offset + page_length) > PAGE_SIZE)
 901                         page_length = PAGE_SIZE - data_page_offset;
 902
 903                 if (do_bit17_swizzling) {
 904                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 905                                                     shmem_page_offset,
 906                                                     user_pages[data_page_index],
 907                                                     data_page_offset,
 908                                                     page_length,
 909                                                     0);
 910                 } else {
 911                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
 912                                               shmem_page_offset,
 913                                               user_pages[data_page_index],
 914                                               data_page_offset,
 915                                               page_length);
 916                 }
 917                 if (ret)
 918                         goto fail_put_pages;
 919
 920                 remain -= page_length;
 921                 data_ptr += page_length;
 922                 offset += page_length;
 923         }
 924
 925 fail_put_pages:
 926         i915_gem_object_put_pages(obj);
 927 fail_unlock:
 928         mutex_unlock(&dev->struct_mutex);
 929 fail_put_user_pages:
 930         for (i = 0; i < pinned_pages; i++)
 931                 page_cache_release(user_pages[i]);
 932         drm_free_large(user_pages);
 933
 934         return ret;
 935 }
 936
 937 /**
 938  * Writes data to the object referenced by handle.
 939  *
 940  * On error, the contents of the buffer that were to be modified are undefined.
 941  */
 942 int
 943 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 944                       struct drm_file *file_priv)
 945 {
 946         struct drm_i915_gem_pwrite *args = data;
 947         struct drm_gem_object *obj;
 948         struct drm_i915_gem_object *obj_priv;
 949         int ret = 0;
 950
 951         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 952         if (obj == NULL)
 953                 return -EBADF;
 954         obj_priv = obj->driver_private;
 955
 956         /* Bounds check destination.
 957          *
 958          * XXX: This could use review for overflow issues...
 959          */
 960         if (args->offset > obj->size || args->size > obj->size ||
 961             args->offset + args->size > obj->size) {
 962                 drm_gem_object_unreference_unlocked(obj);
 963                 return -EINVAL;
 964         }
 965
 966         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 967          * it would end up going through the fenced access, and we'll get
 968          * different detiling behavior between reading and writing.
 969          * pread/pwrite currently are reading and writing from the CPU
 970          * perspective, requiring manual detiling by the client.
 971          */
 972         if (obj_priv->phys_obj)
 973                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 974         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 975                  dev->gtt_total != 0) {
 976                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 977                 if (ret == -EFAULT) {
 978                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 979                                                        file_priv);
 980                 }
 981         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 982                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 983         } else {
 984                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 985                 if (ret == -EFAULT) {
 986                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 987                                                          file_priv);
 988                 }
 989         }
 990
 991 #if WATCH_PWRITE
 992         if (ret)
 993                 DRM_INFO("pwrite failed %d\n", ret);
 994 #endif
 995
 996         drm_gem_object_unreference_unlocked(obj);
 997
 998         return ret;
 999 }
1000
1001 /**
1002  * Called when user space prepares to use an object with the CPU, either
1003  * through the mmap ioctl's mapping or a GTT mapping.
1004  */
1005 int
1006 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1007                           struct drm_file *file_priv)
1008 {
1009         struct drm_i915_private *dev_priv = dev->dev_private;
1010         struct drm_i915_gem_set_domain *args = data;
1011         struct drm_gem_object *obj;
1012         struct drm_i915_gem_object *obj_priv;
1013         uint32_t read_domains = args->read_domains;
1014         uint32_t write_domain = args->write_domain;
1015         int ret;
1016
1017         if (!(dev->driver->driver_features & DRIVER_GEM))
1018                 return -ENODEV;
1019
1020         /* Only handle setting domains to types used by the CPU. */
1021         if (write_domain & I915_GEM_GPU_DOMAINS)
1022                 return -EINVAL;
1023
1024         if (read_domains & I915_GEM_GPU_DOMAINS)
1025                 return -EINVAL;
1026
1027         /* Having something in the write domain implies it's in the read
1028          * domain, and only that read domain.  Enforce that in the request.
1029          */
1030         if (write_domain != 0 && read_domains != write_domain)
1031                 return -EINVAL;
1032
1033         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1034         if (obj == NULL)
1035                 return -EBADF;
1036         obj_priv = obj->driver_private;
1037
1038         mutex_lock(&dev->struct_mutex);
1039
1040         intel_mark_busy(dev, obj);
1041
1042 #if WATCH_BUF
1043         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044                  obj, obj->size, read_domains, write_domain);
1045 #endif
1046         if (read_domains & I915_GEM_DOMAIN_GTT) {
1047                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1048
1049                 /* Update the LRU on the fence for the CPU access that's
1050                  * about to occur.
1051                  */
1052                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1053                         list_move_tail(&obj_priv->fence_list,
1054                                        &dev_priv->mm.fence_list);
1055                 }
1056
1057                 /* Silently promote "you're not bound, there was nothing to do"
1058                  * to success, since the client was just asking us to
1059                  * make sure everything was done.
1060                  */
1061                 if (ret == -EINVAL)
1062                         ret = 0;
1063         } else {
1064                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1065         }
1066
1067         drm_gem_object_unreference(obj);
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space has done writes to this buffer
1074  */
1075 int
1076 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1077                       struct drm_file *file_priv)
1078 {
1079         struct drm_i915_gem_sw_finish *args = data;
1080         struct drm_gem_object *obj;
1081         struct drm_i915_gem_object *obj_priv;
1082         int ret = 0;
1083
1084         if (!(dev->driver->driver_features & DRIVER_GEM))
1085                 return -ENODEV;
1086
1087         mutex_lock(&dev->struct_mutex);
1088         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1089         if (obj == NULL) {
1090                 mutex_unlock(&dev->struct_mutex);
1091                 return -EBADF;
1092         }
1093
1094 #if WATCH_BUF
1095         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096                  __func__, args->handle, obj, obj->size);
1097 #endif
1098         obj_priv = obj->driver_private;
1099
1100         /* Pinned buffers may be scanout, so flush the cache */
1101         if (obj_priv->pin_count)
1102                 i915_gem_object_flush_cpu_write_domain(obj);
1103
1104         drm_gem_object_unreference(obj);
1105         mutex_unlock(&dev->struct_mutex);
1106         return ret;
1107 }
1108
1109 /**
1110  * Maps the contents of an object, returning the address it is mapped
1111  * into.
1112  *
1113  * While the mapping holds a reference on the contents of the object, it doesn't
1114  * imply a ref on the object itself.
1115  */
1116 int
1117 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1118                    struct drm_file *file_priv)
1119 {
1120         struct drm_i915_gem_mmap *args = data;
1121         struct drm_gem_object *obj;
1122         loff_t offset;
1123         unsigned long addr;
1124
1125         if (!(dev->driver->driver_features & DRIVER_GEM))
1126                 return -ENODEV;
1127
1128         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1129         if (obj == NULL)
1130                 return -EBADF;
1131
1132         offset = args->offset;
1133
1134         down_write(&current->mm->mmap_sem);
1135         addr = do_mmap(obj->filp, 0, args->size,
1136                        PROT_READ | PROT_WRITE, MAP_SHARED,
1137                        args->offset);
1138         up_write(&current->mm->mmap_sem);
1139         drm_gem_object_unreference_unlocked(obj);
1140         if (IS_ERR((void *)addr))
1141                 return addr;
1142
1143         args->addr_ptr = (uint64_t) addr;
1144
1145         return 0;
1146 }
1147
1148 /**
1149  * i915_gem_fault - fault a page into the GTT
1150  * vma: VMA in question
1151  * vmf: fault info
1152  *
1153  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154  * from userspace.  The fault handler takes care of binding the object to
1155  * the GTT (if needed), allocating and programming a fence register (again,
1156  * only if needed based on whether the old reg is still valid or the object
1157  * is tiled) and inserting a new PTE into the faulting process.
1158  *
1159  * Note that the faulting process may involve evicting existing objects
1160  * from the GTT and/or fence registers to make room.  So performance may
1161  * suffer if the GTT working set is large or there are few fence registers
1162  * left.
1163  */
1164 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1165 {
1166         struct drm_gem_object *obj = vma->vm_private_data;
1167         struct drm_device *dev = obj->dev;
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1170         pgoff_t page_offset;
1171         unsigned long pfn;
1172         int ret = 0;
1173         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1174
1175         /* We don't use vmf->pgoff since that has the fake offset */
1176         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1177                 PAGE_SHIFT;
1178
1179         /* Now bind it into the GTT if needed */
1180         mutex_lock(&dev->struct_mutex);
1181         if (!obj_priv->gtt_space) {
1182                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1183                 if (ret)
1184                         goto unlock;
1185
1186                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1187
1188                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1189                 if (ret)
1190                         goto unlock;
1191         }
1192
1193         /* Need a new fence register? */
1194         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1195                 ret = i915_gem_object_get_fence_reg(obj);
1196                 if (ret)
1197                         goto unlock;
1198         }
1199
1200         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1201                 page_offset;
1202
1203         /* Finally, remap it using the new GTT offset */
1204         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1205 unlock:
1206         mutex_unlock(&dev->struct_mutex);
1207
1208         switch (ret) {
1209         case 0:
1210         case -ERESTARTSYS:
1211                 return VM_FAULT_NOPAGE;
1212         case -ENOMEM:
1213         case -EAGAIN:
1214                 return VM_FAULT_OOM;
1215         default:
1216                 return VM_FAULT_SIGBUS;
1217         }
1218 }
1219
1220 /**
1221  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222  * @obj: obj in question
1223  *
1224  * GEM memory mapping works by handing back to userspace a fake mmap offset
1225  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1226  * up the object based on the offset and sets up the various memory mapping
1227  * structures.
1228  *
1229  * This routine allocates and attaches a fake offset for @obj.
1230  */
1231 static int
1232 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1233 {
1234         struct drm_device *dev = obj->dev;
1235         struct drm_gem_mm *mm = dev->mm_private;
1236         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1237         struct drm_map_list *list;
1238         struct drm_local_map *map;
1239         int ret = 0;
1240
1241         /* Set the object up for mmap'ing */
1242         list = &obj->map_list;
1243         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1244         if (!list->map)
1245                 return -ENOMEM;
1246
1247         map = list->map;
1248         map->type = _DRM_GEM;
1249         map->size = obj->size;
1250         map->handle = obj;
1251
1252         /* Get a DRM GEM mmap offset allocated... */
1253         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1254                                                     obj->size / PAGE_SIZE, 0, 0);
1255         if (!list->file_offset_node) {
1256                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1257                 ret = -ENOMEM;
1258                 goto out_free_list;
1259         }
1260
1261         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1262                                                   obj->size / PAGE_SIZE, 0);
1263         if (!list->file_offset_node) {
1264                 ret = -ENOMEM;
1265                 goto out_free_list;
1266         }
1267
1268         list->hash.key = list->file_offset_node->start;
1269         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1270                 DRM_ERROR("failed to add to map hash\n");
1271                 ret = -ENOMEM;
1272                 goto out_free_mm;
1273         }
1274
1275         /* By now we should be all set, any drm_mmap request on the offset
1276          * below will get to our mmap & fault handler */
1277         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1278
1279         return 0;
1280
1281 out_free_mm:
1282         drm_mm_put_block(list->file_offset_node);
1283 out_free_list:
1284         kfree(list->map);
1285
1286         return ret;
1287 }
1288
1289 /**
1290  * i915_gem_release_mmap - remove physical page mappings
1291  * @obj: obj in question
1292  *
1293  * Preserve the reservation of the mmapping with the DRM core code, but
1294  * relinquish ownership of the pages back to the system.
1295  *
1296  * It is vital that we remove the page mapping if we have mapped a tiled
1297  * object through the GTT and then lose the fence register due to
1298  * resource pressure. Similarly if the object has been moved out of the
1299  * aperture, than pages mapped into userspace must be revoked. Removing the
1300  * mapping will then trigger a page fault on the next user access, allowing
1301  * fixup by i915_gem_fault().
1302  */
1303 void
1304 i915_gem_release_mmap(struct drm_gem_object *obj)
1305 {
1306         struct drm_device *dev = obj->dev;
1307         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1308
1309         if (dev->dev_mapping)
1310                 unmap_mapping_range(dev->dev_mapping,
1311                                     obj_priv->mmap_offset, obj->size, 1);
1312 }
1313
1314 static void
1315 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1316 {
1317         struct drm_device *dev = obj->dev;
1318         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1319         struct drm_gem_mm *mm = dev->mm_private;
1320         struct drm_map_list *list;
1321
1322         list = &obj->map_list;
1323         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1324
1325         if (list->file_offset_node) {
1326                 drm_mm_put_block(list->file_offset_node);
1327                 list->file_offset_node = NULL;
1328         }
1329
1330         if (list->map) {
1331                 kfree(list->map);
1332                 list->map = NULL;
1333         }
1334
1335         obj_priv->mmap_offset = 0;
1336 }
1337
1338 /**
1339  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340  * @obj: object to check
1341  *
1342  * Return the required GTT alignment for an object, taking into account
1343  * potential fence register mapping if needed.
1344  */
1345 static uint32_t
1346 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1347 {
1348         struct drm_device *dev = obj->dev;
1349         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1350         int start, i;
1351
1352         /*
1353          * Minimum alignment is 4k (GTT page size), but might be greater
1354          * if a fence register is needed for the object.
1355          */
1356         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1357                 return 4096;
1358
1359         /*
1360          * Previous chips need to be aligned to the size of the smallest
1361          * fence register that can contain the object.
1362          */
1363         if (IS_I9XX(dev))
1364                 start = 1024*1024;
1365         else
1366                 start = 512*1024;
1367
1368         for (i = start; i < obj->size; i <<= 1)
1369                 ;
1370
1371         return i;
1372 }
1373
1374 /**
1375  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1376  * @dev: DRM device
1377  * @data: GTT mapping ioctl data
1378  * @file_priv: GEM object info
1379  *
1380  * Simply returns the fake offset to userspace so it can mmap it.
1381  * The mmap call will end up in drm_gem_mmap(), which will set things
1382  * up so we can get faults in the handler above.
1383  *
1384  * The fault handler will take care of binding the object into the GTT
1385  * (since it may have been evicted to make room for something), allocating
1386  * a fence register, and mapping the appropriate aperture address into
1387  * userspace.
1388  */
1389 int
1390 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1391                         struct drm_file *file_priv)
1392 {
1393         struct drm_i915_gem_mmap_gtt *args = data;
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         struct drm_gem_object *obj;
1396         struct drm_i915_gem_object *obj_priv;
1397         int ret;
1398
1399         if (!(dev->driver->driver_features & DRIVER_GEM))
1400                 return -ENODEV;
1401
1402         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1403         if (obj == NULL)
1404                 return -EBADF;
1405
1406         mutex_lock(&dev->struct_mutex);
1407
1408         obj_priv = obj->driver_private;
1409
1410         if (obj_priv->madv != I915_MADV_WILLNEED) {
1411                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412                 drm_gem_object_unreference(obj);
1413                 mutex_unlock(&dev->struct_mutex);
1414                 return -EINVAL;
1415         }
1416
1417
1418         if (!obj_priv->mmap_offset) {
1419                 ret = i915_gem_create_mmap_offset(obj);
1420                 if (ret) {
1421                         drm_gem_object_unreference(obj);
1422                         mutex_unlock(&dev->struct_mutex);
1423                         return ret;
1424                 }
1425         }
1426
1427         args->offset = obj_priv->mmap_offset;
1428
1429         /*
1430          * Pull it into the GTT so that we have a page list (makes the
1431          * initial fault faster and any subsequent flushing possible).
1432          */
1433         if (!obj_priv->agp_mem) {
1434                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1435                 if (ret) {
1436                         drm_gem_object_unreference(obj);
1437                         mutex_unlock(&dev->struct_mutex);
1438                         return ret;
1439                 }
1440                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1441         }
1442
1443         drm_gem_object_unreference(obj);
1444         mutex_unlock(&dev->struct_mutex);
1445
1446         return 0;
1447 }
1448
1449 void
1450 i915_gem_object_put_pages(struct drm_gem_object *obj)
1451 {
1452         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1453         int page_count = obj->size / PAGE_SIZE;
1454         int i;
1455
1456         BUG_ON(obj_priv->pages_refcount == 0);
1457         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1458
1459         if (--obj_priv->pages_refcount != 0)
1460                 return;
1461
1462         if (obj_priv->tiling_mode != I915_TILING_NONE)
1463                 i915_gem_object_save_bit_17_swizzle(obj);
1464
1465         if (obj_priv->madv == I915_MADV_DONTNEED)
1466                 obj_priv->dirty = 0;
1467
1468         for (i = 0; i < page_count; i++) {
1469                 if (obj_priv->pages[i] == NULL)
1470                         break;
1471
1472                 if (obj_priv->dirty)
1473                         set_page_dirty(obj_priv->pages[i]);
1474
1475                 if (obj_priv->madv == I915_MADV_WILLNEED)
1476                         mark_page_accessed(obj_priv->pages[i]);
1477
1478                 page_cache_release(obj_priv->pages[i]);
1479         }
1480         obj_priv->dirty = 0;
1481
1482         drm_free_large(obj_priv->pages);
1483         obj_priv->pages = NULL;
1484 }
1485
1486 static void
1487 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1488 {
1489         struct drm_device *dev = obj->dev;
1490         drm_i915_private_t *dev_priv = dev->dev_private;
1491         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1492
1493         /* Add a reference if we're newly entering the active list. */
1494         if (!obj_priv->active) {
1495                 drm_gem_object_reference(obj);
1496                 obj_priv->active = 1;
1497         }
1498         /* Move from whatever list we were on to the tail of execution. */
1499         spin_lock(&dev_priv->mm.active_list_lock);
1500         list_move_tail(&obj_priv->list,
1501                        &dev_priv->mm.active_list);
1502         spin_unlock(&dev_priv->mm.active_list_lock);
1503         obj_priv->last_rendering_seqno = seqno;
1504 }
1505
1506 static void
1507 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1508 {
1509         struct drm_device *dev = obj->dev;
1510         drm_i915_private_t *dev_priv = dev->dev_private;
1511         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1512
1513         BUG_ON(!obj_priv->active);
1514         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1515         obj_priv->last_rendering_seqno = 0;
1516 }
1517
1518 /* Immediately discard the backing storage */
1519 static void
1520 i915_gem_object_truncate(struct drm_gem_object *obj)
1521 {
1522         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1523         struct inode *inode;
1524
1525         inode = obj->filp->f_path.dentry->d_inode;
1526         if (inode->i_op->truncate)
1527                 inode->i_op->truncate (inode);
1528
1529         obj_priv->madv = __I915_MADV_PURGED;
1530 }
1531
1532 static inline int
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1534 {
1535         return obj_priv->madv == I915_MADV_DONTNEED;
1536 }
1537
1538 static void
1539 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1540 {
1541         struct drm_device *dev = obj->dev;
1542         drm_i915_private_t *dev_priv = dev->dev_private;
1543         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1544
1545         i915_verify_inactive(dev, __FILE__, __LINE__);
1546         if (obj_priv->pin_count != 0)
1547                 list_del_init(&obj_priv->list);
1548         else
1549                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1550
1551         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1552
1553         obj_priv->last_rendering_seqno = 0;
1554         if (obj_priv->active) {
1555                 obj_priv->active = 0;
1556                 drm_gem_object_unreference(obj);
1557         }
1558         i915_verify_inactive(dev, __FILE__, __LINE__);
1559 }
1560
1561 static void
1562 i915_gem_process_flushing_list(struct drm_device *dev,
1563                                uint32_t flush_domains, uint32_t seqno)
1564 {
1565         drm_i915_private_t *dev_priv = dev->dev_private;
1566         struct drm_i915_gem_object *obj_priv, *next;
1567
1568         list_for_each_entry_safe(obj_priv, next,
1569                                  &dev_priv->mm.gpu_write_list,
1570                                  gpu_write_list) {
1571                 struct drm_gem_object *obj = obj_priv->obj;
1572
1573                 if ((obj->write_domain & flush_domains) ==
1574                     obj->write_domain) {
1575                         uint32_t old_write_domain = obj->write_domain;
1576
1577                         obj->write_domain = 0;
1578                         list_del_init(&obj_priv->gpu_write_list);
1579                         i915_gem_object_move_to_active(obj, seqno);
1580
1581                         /* update the fence lru list */
1582                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1583                                 list_move_tail(&obj_priv->fence_list,
1584                                                 &dev_priv->mm.fence_list);
1585
1586                         trace_i915_gem_object_change_domain(obj,
1587                                                             obj->read_domains,
1588                                                             old_write_domain);
1589                 }
1590         }
1591 }
1592
1593 /**
1594  * Creates a new sequence number, emitting a write of it to the status page
1595  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1596  *
1597  * Must be called with struct_lock held.
1598  *
1599  * Returned sequence numbers are nonzero on success.
1600  */
1601 uint32_t
1602 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1603                  uint32_t flush_domains)
1604 {
1605         drm_i915_private_t *dev_priv = dev->dev_private;
1606         struct drm_i915_file_private *i915_file_priv = NULL;
1607         struct drm_i915_gem_request *request;
1608         uint32_t seqno;
1609         int was_empty;
1610         RING_LOCALS;
1611
1612         if (file_priv != NULL)
1613                 i915_file_priv = file_priv->driver_priv;
1614
1615         request = kzalloc(sizeof(*request), GFP_KERNEL);
1616         if (request == NULL)
1617                 return 0;
1618
1619         /* Grab the seqno we're going to make this request be, and bump the
1620          * next (skipping 0 so it can be the reserved no-seqno value).
1621          */
1622         seqno = dev_priv->mm.next_gem_seqno;
1623         dev_priv->mm.next_gem_seqno++;
1624         if (dev_priv->mm.next_gem_seqno == 0)
1625                 dev_priv->mm.next_gem_seqno++;
1626
1627         BEGIN_LP_RING(4);
1628         OUT_RING(MI_STORE_DWORD_INDEX);
1629         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1630         OUT_RING(seqno);
1631
1632         OUT_RING(MI_USER_INTERRUPT);
1633         ADVANCE_LP_RING();
1634
1635         DRM_DEBUG_DRIVER("%d\n", seqno);
1636
1637         request->seqno = seqno;
1638         request->emitted_jiffies = jiffies;
1639         was_empty = list_empty(&dev_priv->mm.request_list);
1640         list_add_tail(&request->list, &dev_priv->mm.request_list);
1641         if (i915_file_priv) {
1642                 list_add_tail(&request->client_list,
1643                               &i915_file_priv->mm.request_list);
1644         } else {
1645                 INIT_LIST_HEAD(&request->client_list);
1646         }
1647
1648         /* Associate any objects on the flushing list matching the write
1649          * domain we're flushing with our flush.
1650          */
1651         if (flush_domains != 0)
1652                 i915_gem_process_flushing_list(dev, flush_domains, seqno);
1653
1654         if (!dev_priv->mm.suspended) {
1655                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1656                 if (was_empty)
1657                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1658         }
1659         return seqno;
1660 }
1661
1662 /**
1663  * Command execution barrier
1664  *
1665  * Ensures that all commands in the ring are finished
1666  * before signalling the CPU
1667  */
1668 static uint32_t
1669 i915_retire_commands(struct drm_device *dev)
1670 {
1671         drm_i915_private_t *dev_priv = dev->dev_private;
1672         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1673         uint32_t flush_domains = 0;
1674         RING_LOCALS;
1675
1676         /* The sampler always gets flushed on i965 (sigh) */
1677         if (IS_I965G(dev))
1678                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1679         BEGIN_LP_RING(2);
1680         OUT_RING(cmd);
1681         OUT_RING(0); /* noop */
1682         ADVANCE_LP_RING();
1683         return flush_domains;
1684 }
1685
1686 /**
1687  * Moves buffers associated only with the given active seqno from the active
1688  * to inactive list, potentially freeing them.
1689  */
1690 static void
1691 i915_gem_retire_request(struct drm_device *dev,
1692                         struct drm_i915_gem_request *request)
1693 {
1694         drm_i915_private_t *dev_priv = dev->dev_private;
1695
1696         trace_i915_gem_request_retire(dev, request->seqno);
1697
1698         /* Move any buffers on the active list that are no longer referenced
1699          * by the ringbuffer to the flushing/inactive lists as appropriate.
1700          */
1701         spin_lock(&dev_priv->mm.active_list_lock);
1702         while (!list_empty(&dev_priv->mm.active_list)) {
1703                 struct drm_gem_object *obj;
1704                 struct drm_i915_gem_object *obj_priv;
1705
1706                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1707                                             struct drm_i915_gem_object,
1708                                             list);
1709                 obj = obj_priv->obj;
1710
1711                 /* If the seqno being retired doesn't match the oldest in the
1712                  * list, then the oldest in the list must still be newer than
1713                  * this seqno.
1714                  */
1715                 if (obj_priv->last_rendering_seqno != request->seqno)
1716                         goto out;
1717
1718 #if WATCH_LRU
1719                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1720                          __func__, request->seqno, obj);
1721 #endif
1722
1723                 if (obj->write_domain != 0)
1724                         i915_gem_object_move_to_flushing(obj);
1725                 else {
1726                         /* Take a reference on the object so it won't be
1727                          * freed while the spinlock is held.  The list
1728                          * protection for this spinlock is safe when breaking
1729                          * the lock like this since the next thing we do
1730                          * is just get the head of the list again.
1731                          */
1732                         drm_gem_object_reference(obj);
1733                         i915_gem_object_move_to_inactive(obj);
1734                         spin_unlock(&dev_priv->mm.active_list_lock);
1735                         drm_gem_object_unreference(obj);
1736                         spin_lock(&dev_priv->mm.active_list_lock);
1737                 }
1738         }
1739 out:
1740         spin_unlock(&dev_priv->mm.active_list_lock);
1741 }
1742
1743 /**
1744  * Returns true if seq1 is later than seq2.
1745  */
1746 bool
1747 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1748 {
1749         return (int32_t)(seq1 - seq2) >= 0;
1750 }
1751
1752 uint32_t
1753 i915_get_gem_seqno(struct drm_device *dev)
1754 {
1755         drm_i915_private_t *dev_priv = dev->dev_private;
1756
1757         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1758 }
1759
1760 /**
1761  * This function clears the request list as sequence numbers are passed.
1762  */
1763 void
1764 i915_gem_retire_requests(struct drm_device *dev)
1765 {
1766         drm_i915_private_t *dev_priv = dev->dev_private;
1767         uint32_t seqno;
1768
1769         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1770                 return;
1771
1772         seqno = i915_get_gem_seqno(dev);
1773
1774         while (!list_empty(&dev_priv->mm.request_list)) {
1775                 struct drm_i915_gem_request *request;
1776                 uint32_t retiring_seqno;
1777
1778                 request = list_first_entry(&dev_priv->mm.request_list,
1779                                            struct drm_i915_gem_request,
1780                                            list);
1781                 retiring_seqno = request->seqno;
1782
1783                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1784                     atomic_read(&dev_priv->mm.wedged)) {
1785                         i915_gem_retire_request(dev, request);
1786
1787                         list_del(&request->list);
1788                         list_del(&request->client_list);
1789                         kfree(request);
1790                 } else
1791                         break;
1792         }
1793
1794         if (unlikely (dev_priv->trace_irq_seqno &&
1795                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1796                 i915_user_irq_put(dev);
1797                 dev_priv->trace_irq_seqno = 0;
1798         }
1799 }
1800
1801 void
1802 i915_gem_retire_work_handler(struct work_struct *work)
1803 {
1804         drm_i915_private_t *dev_priv;
1805         struct drm_device *dev;
1806
1807         dev_priv = container_of(work, drm_i915_private_t,
1808                                 mm.retire_work.work);
1809         dev = dev_priv->dev;
1810
1811         mutex_lock(&dev->struct_mutex);
1812         i915_gem_retire_requests(dev);
1813         if (!dev_priv->mm.suspended &&
1814             !list_empty(&dev_priv->mm.request_list))
1815                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1816         mutex_unlock(&dev->struct_mutex);
1817 }
1818
1819 int
1820 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1821 {
1822         drm_i915_private_t *dev_priv = dev->dev_private;
1823         u32 ier;
1824         int ret = 0;
1825
1826         BUG_ON(seqno == 0);
1827
1828         if (atomic_read(&dev_priv->mm.wedged))
1829                 return -EIO;
1830
1831         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1832                 if (HAS_PCH_SPLIT(dev))
1833                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1834                 else
1835                         ier = I915_READ(IER);
1836                 if (!ier) {
1837                         DRM_ERROR("something (likely vbetool) disabled "
1838                                   "interrupts, re-enabling\n");
1839                         i915_driver_irq_preinstall(dev);
1840                         i915_driver_irq_postinstall(dev);
1841                 }
1842
1843                 trace_i915_gem_request_wait_begin(dev, seqno);
1844
1845                 dev_priv->mm.waiting_gem_seqno = seqno;
1846                 i915_user_irq_get(dev);
1847                 if (interruptible)
1848                         ret = wait_event_interruptible(dev_priv->irq_queue,
1849                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1850                                 atomic_read(&dev_priv->mm.wedged));
1851                 else
1852                         wait_event(dev_priv->irq_queue,
1853                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1854                                 atomic_read(&dev_priv->mm.wedged));
1855
1856                 i915_user_irq_put(dev);
1857                 dev_priv->mm.waiting_gem_seqno = 0;
1858
1859                 trace_i915_gem_request_wait_end(dev, seqno);
1860         }
1861         if (atomic_read(&dev_priv->mm.wedged))
1862                 ret = -EIO;
1863
1864         if (ret && ret != -ERESTARTSYS)
1865                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1866                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1867
1868         /* Directly dispatch request retiring.  While we have the work queue
1869          * to handle this, the waiter on a request often wants an associated
1870          * buffer to have made it to the inactive list, and we would need
1871          * a separate wait queue to handle that.
1872          */
1873         if (ret == 0)
1874                 i915_gem_retire_requests(dev);
1875
1876         return ret;
1877 }
1878
1879 /**
1880  * Waits for a sequence number to be signaled, and cleans up the
1881  * request and object lists appropriately for that event.
1882  */
1883 static int
1884 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1885 {
1886         return i915_do_wait_request(dev, seqno, 1);
1887 }
1888
1889 static void
1890 i915_gem_flush(struct drm_device *dev,
1891                uint32_t invalidate_domains,
1892                uint32_t flush_domains)
1893 {
1894         drm_i915_private_t *dev_priv = dev->dev_private;
1895         uint32_t cmd;
1896         RING_LOCALS;
1897
1898 #if WATCH_EXEC
1899         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1900                   invalidate_domains, flush_domains);
1901 #endif
1902         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1903                                      invalidate_domains, flush_domains);
1904
1905         if (flush_domains & I915_GEM_DOMAIN_CPU)
1906                 drm_agp_chipset_flush(dev);
1907
1908         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1909                 /*
1910                  * read/write caches:
1911                  *
1912                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1913                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1914                  * also flushed at 2d versus 3d pipeline switches.
1915                  *
1916                  * read-only caches:
1917                  *
1918                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1919                  * MI_READ_FLUSH is set, and is always flushed on 965.
1920                  *
1921                  * I915_GEM_DOMAIN_COMMAND may not exist?
1922                  *
1923                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1924                  * invalidated when MI_EXE_FLUSH is set.
1925                  *
1926                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1927                  * invalidated with every MI_FLUSH.
1928                  *
1929                  * TLBs:
1930                  *
1931                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1932                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1933                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1934                  * are flushed at any MI_FLUSH.
1935                  */
1936
1937                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1938                 if ((invalidate_domains|flush_domains) &
1939                     I915_GEM_DOMAIN_RENDER)
1940                         cmd &= ~MI_NO_WRITE_FLUSH;
1941                 if (!IS_I965G(dev)) {
1942                         /*
1943                          * On the 965, the sampler cache always gets flushed
1944                          * and this bit is reserved.
1945                          */
1946                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1947                                 cmd |= MI_READ_FLUSH;
1948                 }
1949                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1950                         cmd |= MI_EXE_FLUSH;
1951
1952 #if WATCH_EXEC
1953                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1954 #endif
1955                 BEGIN_LP_RING(2);
1956                 OUT_RING(cmd);
1957                 OUT_RING(MI_NOOP);
1958                 ADVANCE_LP_RING();
1959         }
1960 }
1961
1962 /**
1963  * Ensures that all rendering to the object has completed and the object is
1964  * safe to unbind from the GTT or access from the CPU.
1965  */
1966 static int
1967 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1968 {
1969         struct drm_device *dev = obj->dev;
1970         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1971         int ret;
1972
1973         /* This function only exists to support waiting for existing rendering,
1974          * not for emitting required flushes.
1975          */
1976         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1977
1978         /* If there is rendering queued on the buffer being evicted, wait for
1979          * it.
1980          */
1981         if (obj_priv->active) {
1982 #if WATCH_BUF
1983                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1984                           __func__, obj, obj_priv->last_rendering_seqno);
1985 #endif
1986                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1987                 if (ret != 0)
1988                         return ret;
1989         }
1990
1991         return 0;
1992 }
1993
1994 /**
1995  * Unbinds an object from the GTT aperture.
1996  */
1997 int
1998 i915_gem_object_unbind(struct drm_gem_object *obj)
1999 {
2000         struct drm_device *dev = obj->dev;
2001         drm_i915_private_t *dev_priv = dev->dev_private;
2002         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2003         int ret = 0;
2004
2005 #if WATCH_BUF
2006         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2007         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2008 #endif
2009         if (obj_priv->gtt_space == NULL)
2010                 return 0;
2011
2012         if (obj_priv->pin_count != 0) {
2013                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2014                 return -EINVAL;
2015         }
2016
2017         /* blow away mappings if mapped through GTT */
2018         i915_gem_release_mmap(obj);
2019
2020         /* Move the object to the CPU domain to ensure that
2021          * any possible CPU writes while it's not in the GTT
2022          * are flushed when we go to remap it. This will
2023          * also ensure that all pending GPU writes are finished
2024          * before we unbind.
2025          */
2026         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2027         if (ret) {
2028                 if (ret != -ERESTARTSYS)
2029                         DRM_ERROR("set_domain failed: %d\n", ret);
2030                 return ret;
2031         }
2032
2033         BUG_ON(obj_priv->active);
2034
2035         /* release the fence reg _after_ flushing */
2036         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2037                 i915_gem_clear_fence_reg(obj);
2038
2039         if (obj_priv->agp_mem != NULL) {
2040                 drm_unbind_agp(obj_priv->agp_mem);
2041                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2042                 obj_priv->agp_mem = NULL;
2043         }
2044
2045         i915_gem_object_put_pages(obj);
2046         BUG_ON(obj_priv->pages_refcount);
2047
2048         if (obj_priv->gtt_space) {
2049                 atomic_dec(&dev->gtt_count);
2050                 atomic_sub(obj->size, &dev->gtt_memory);
2051
2052                 drm_mm_put_block(obj_priv->gtt_space);
2053                 obj_priv->gtt_space = NULL;
2054         }
2055
2056         /* Remove ourselves from the LRU list if present. */
2057         spin_lock(&dev_priv->mm.active_list_lock);
2058         if (!list_empty(&obj_priv->list))
2059                 list_del_init(&obj_priv->list);
2060         spin_unlock(&dev_priv->mm.active_list_lock);
2061
2062         if (i915_gem_object_is_purgeable(obj_priv))
2063                 i915_gem_object_truncate(obj);
2064
2065         trace_i915_gem_object_unbind(obj);
2066
2067         return 0;
2068 }
2069
2070 static struct drm_gem_object *
2071 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2072 {
2073         drm_i915_private_t *dev_priv = dev->dev_private;
2074         struct drm_i915_gem_object *obj_priv;
2075         struct drm_gem_object *best = NULL;
2076         struct drm_gem_object *first = NULL;
2077
2078         /* Try to find the smallest clean object */
2079         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2080                 struct drm_gem_object *obj = obj_priv->obj;
2081                 if (obj->size >= min_size) {
2082                         if ((!obj_priv->dirty ||
2083                              i915_gem_object_is_purgeable(obj_priv)) &&
2084                             (!best || obj->size < best->size)) {
2085                                 best = obj;
2086                                 if (best->size == min_size)
2087                                         return best;
2088                         }
2089                         if (!first)
2090                             first = obj;
2091                 }
2092         }
2093
2094         return best ? best : first;
2095 }
2096
2097 static int
2098 i915_gpu_idle(struct drm_device *dev)
2099 {
2100         drm_i915_private_t *dev_priv = dev->dev_private;
2101         bool lists_empty;
2102         uint32_t seqno;
2103
2104         spin_lock(&dev_priv->mm.active_list_lock);
2105         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2106                       list_empty(&dev_priv->mm.active_list);
2107         spin_unlock(&dev_priv->mm.active_list_lock);
2108
2109         if (lists_empty)
2110                 return 0;
2111
2112         /* Flush everything onto the inactive list. */
2113         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2114         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2115         if (seqno == 0)
2116                 return -ENOMEM;
2117
2118         return i915_wait_request(dev, seqno);
2119 }
2120
2121 static int
2122 i915_gem_evict_everything(struct drm_device *dev)
2123 {
2124         drm_i915_private_t *dev_priv = dev->dev_private;
2125         int ret;
2126         bool lists_empty;
2127
2128         spin_lock(&dev_priv->mm.active_list_lock);
2129         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2130                        list_empty(&dev_priv->mm.flushing_list) &&
2131                        list_empty(&dev_priv->mm.active_list));
2132         spin_unlock(&dev_priv->mm.active_list_lock);
2133
2134         if (lists_empty)
2135                 return -ENOSPC;
2136
2137         /* Flush everything (on to the inactive lists) and evict */
2138         ret = i915_gpu_idle(dev);
2139         if (ret)
2140                 return ret;
2141
2142         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2143
2144         ret = i915_gem_evict_from_inactive_list(dev);
2145         if (ret)
2146                 return ret;
2147
2148         spin_lock(&dev_priv->mm.active_list_lock);
2149         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2150                        list_empty(&dev_priv->mm.flushing_list) &&
2151                        list_empty(&dev_priv->mm.active_list));
2152         spin_unlock(&dev_priv->mm.active_list_lock);
2153         BUG_ON(!lists_empty);
2154
2155         return 0;
2156 }
2157
2158 static int
2159 i915_gem_evict_something(struct drm_device *dev, int min_size)
2160 {
2161         drm_i915_private_t *dev_priv = dev->dev_private;
2162         struct drm_gem_object *obj;
2163         int ret;
2164
2165         for (;;) {
2166                 i915_gem_retire_requests(dev);
2167
2168                 /* If there's an inactive buffer available now, grab it
2169                  * and be done.
2170                  */
2171                 obj = i915_gem_find_inactive_object(dev, min_size);
2172                 if (obj) {
2173                         struct drm_i915_gem_object *obj_priv;
2174
2175 #if WATCH_LRU
2176                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2177 #endif
2178                         obj_priv = obj->driver_private;
2179                         BUG_ON(obj_priv->pin_count != 0);
2180                         BUG_ON(obj_priv->active);
2181
2182                         /* Wait on the rendering and unbind the buffer. */
2183                         return i915_gem_object_unbind(obj);
2184                 }
2185
2186                 /* If we didn't get anything, but the ring is still processing
2187                  * things, wait for the next to finish and hopefully leave us
2188                  * a buffer to evict.
2189                  */
2190                 if (!list_empty(&dev_priv->mm.request_list)) {
2191                         struct drm_i915_gem_request *request;
2192
2193                         request = list_first_entry(&dev_priv->mm.request_list,
2194                                                    struct drm_i915_gem_request,
2195                                                    list);
2196
2197                         ret = i915_wait_request(dev, request->seqno);
2198                         if (ret)
2199                                 return ret;
2200
2201                         continue;
2202                 }
2203
2204                 /* If we didn't have anything on the request list but there
2205                  * are buffers awaiting a flush, emit one and try again.
2206                  * When we wait on it, those buffers waiting for that flush
2207                  * will get moved to inactive.
2208                  */
2209                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2210                         struct drm_i915_gem_object *obj_priv;
2211
2212                         /* Find an object that we can immediately reuse */
2213                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2214                                 obj = obj_priv->obj;
2215                                 if (obj->size >= min_size)
2216                                         break;
2217
2218                                 obj = NULL;
2219                         }
2220
2221                         if (obj != NULL) {
2222                                 uint32_t seqno;
2223
2224                                 i915_gem_flush(dev,
2225                                                obj->write_domain,
2226                                                obj->write_domain);
2227                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2228                                 if (seqno == 0)
2229                                         return -ENOMEM;
2230                                 continue;
2231                         }
2232                 }
2233
2234                 /* If we didn't do any of the above, there's no single buffer
2235                  * large enough to swap out for the new one, so just evict
2236                  * everything and start again. (This should be rare.)
2237                  */
2238                 if (!list_empty (&dev_priv->mm.inactive_list))
2239                         return i915_gem_evict_from_inactive_list(dev);
2240                 else
2241                         return i915_gem_evict_everything(dev);
2242         }
2243 }
2244
2245 int
2246 i915_gem_object_get_pages(struct drm_gem_object *obj,
2247                           gfp_t gfpmask)
2248 {
2249         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2250         int page_count, i;
2251         struct address_space *mapping;
2252         struct inode *inode;
2253         struct page *page;
2254         int ret;
2255
2256         if (obj_priv->pages_refcount++ != 0)
2257                 return 0;
2258
2259         /* Get the list of pages out of our struct file.  They'll be pinned
2260          * at this point until we release them.
2261          */
2262         page_count = obj->size / PAGE_SIZE;
2263         BUG_ON(obj_priv->pages != NULL);
2264         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2265         if (obj_priv->pages == NULL) {
2266                 obj_priv->pages_refcount--;
2267                 return -ENOMEM;
2268         }
2269
2270         inode = obj->filp->f_path.dentry->d_inode;
2271         mapping = inode->i_mapping;
2272         for (i = 0; i < page_count; i++) {
2273                 page = read_cache_page_gfp(mapping, i,
2274                                            mapping_gfp_mask (mapping) |
2275                                            __GFP_COLD |
2276                                            gfpmask);
2277                 if (IS_ERR(page)) {
2278                         ret = PTR_ERR(page);
2279                         i915_gem_object_put_pages(obj);
2280                         return ret;
2281                 }
2282                 obj_priv->pages[i] = page;
2283         }
2284
2285         if (obj_priv->tiling_mode != I915_TILING_NONE)
2286                 i915_gem_object_do_bit_17_swizzle(obj);
2287
2288         return 0;
2289 }
2290
2291 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2292 {
2293         struct drm_gem_object *obj = reg->obj;
2294         struct drm_device *dev = obj->dev;
2295         drm_i915_private_t *dev_priv = dev->dev_private;
2296         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2297         int regnum = obj_priv->fence_reg;
2298         uint64_t val;
2299
2300         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2301                     0xfffff000) << 32;
2302         val |= obj_priv->gtt_offset & 0xfffff000;
2303         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2304                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2305
2306         if (obj_priv->tiling_mode == I915_TILING_Y)
2307                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2308         val |= I965_FENCE_REG_VALID;
2309
2310         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2311 }
2312
2313 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2314 {
2315         struct drm_gem_object *obj = reg->obj;
2316         struct drm_device *dev = obj->dev;
2317         drm_i915_private_t *dev_priv = dev->dev_private;
2318         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2319         int regnum = obj_priv->fence_reg;
2320         uint64_t val;
2321
2322         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2323                     0xfffff000) << 32;
2324         val |= obj_priv->gtt_offset & 0xfffff000;
2325         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2326         if (obj_priv->tiling_mode == I915_TILING_Y)
2327                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2328         val |= I965_FENCE_REG_VALID;
2329
2330         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2331 }
2332
2333 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2334 {
2335         struct drm_gem_object *obj = reg->obj;
2336         struct drm_device *dev = obj->dev;
2337         drm_i915_private_t *dev_priv = dev->dev_private;
2338         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2339         int regnum = obj_priv->fence_reg;
2340         int tile_width;
2341         uint32_t fence_reg, val;
2342         uint32_t pitch_val;
2343
2344         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2345             (obj_priv->gtt_offset & (obj->size - 1))) {
2346                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2347                      __func__, obj_priv->gtt_offset, obj->size);
2348                 return;
2349         }
2350
2351         if (obj_priv->tiling_mode == I915_TILING_Y &&
2352             HAS_128_BYTE_Y_TILING(dev))
2353                 tile_width = 128;
2354         else
2355                 tile_width = 512;
2356
2357         /* Note: pitch better be a power of two tile widths */
2358         pitch_val = obj_priv->stride / tile_width;
2359         pitch_val = ffs(pitch_val) - 1;
2360
2361         val = obj_priv->gtt_offset;
2362         if (obj_priv->tiling_mode == I915_TILING_Y)
2363                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2364         val |= I915_FENCE_SIZE_BITS(obj->size);
2365         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2366         val |= I830_FENCE_REG_VALID;
2367
2368         if (regnum < 8)
2369                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2370         else
2371                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2372         I915_WRITE(fence_reg, val);
2373 }
2374
2375 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2376 {
2377         struct drm_gem_object *obj = reg->obj;
2378         struct drm_device *dev = obj->dev;
2379         drm_i915_private_t *dev_priv = dev->dev_private;
2380         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2381         int regnum = obj_priv->fence_reg;
2382         uint32_t val;
2383         uint32_t pitch_val;
2384         uint32_t fence_size_bits;
2385
2386         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2387             (obj_priv->gtt_offset & (obj->size - 1))) {
2388                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2389                      __func__, obj_priv->gtt_offset);
2390                 return;
2391         }
2392
2393         pitch_val = obj_priv->stride / 128;
2394         pitch_val = ffs(pitch_val) - 1;
2395         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2396
2397         val = obj_priv->gtt_offset;
2398         if (obj_priv->tiling_mode == I915_TILING_Y)
2399                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2400         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2401         WARN_ON(fence_size_bits & ~0x00000f00);
2402         val |= fence_size_bits;
2403         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2404         val |= I830_FENCE_REG_VALID;
2405
2406         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2407 }
2408
2409 static int i915_find_fence_reg(struct drm_device *dev)
2410 {
2411         struct drm_i915_fence_reg *reg = NULL;
2412         struct drm_i915_gem_object *obj_priv = NULL;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct drm_gem_object *obj = NULL;
2415         int i, avail, ret;
2416
2417         /* First try to find a free reg */
2418         avail = 0;
2419         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2420                 reg = &dev_priv->fence_regs[i];
2421                 if (!reg->obj)
2422                         return i;
2423
2424                 obj_priv = reg->obj->driver_private;
2425                 if (!obj_priv->pin_count)
2426                     avail++;
2427         }
2428
2429         if (avail == 0)
2430                 return -ENOSPC;
2431
2432         /* None available, try to steal one or wait for a user to finish */
2433         i = I915_FENCE_REG_NONE;
2434         list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2435                             fence_list) {
2436                 obj = obj_priv->obj;
2437
2438                 if (obj_priv->pin_count)
2439                         continue;
2440
2441                 /* found one! */
2442                 i = obj_priv->fence_reg;
2443                 break;
2444         }
2445
2446         BUG_ON(i == I915_FENCE_REG_NONE);
2447
2448         /* We only have a reference on obj from the active list. put_fence_reg
2449          * might drop that one, causing a use-after-free in it. So hold a
2450          * private reference to obj like the other callers of put_fence_reg
2451          * (set_tiling ioctl) do. */
2452         drm_gem_object_reference(obj);
2453         ret = i915_gem_object_put_fence_reg(obj);
2454         drm_gem_object_unreference(obj);
2455         if (ret != 0)
2456                 return ret;
2457
2458         return i;
2459 }
2460
2461 /**
2462  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2463  * @obj: object to map through a fence reg
2464  *
2465  * When mapping objects through the GTT, userspace wants to be able to write
2466  * to them without having to worry about swizzling if the object is tiled.
2467  *
2468  * This function walks the fence regs looking for a free one for @obj,
2469  * stealing one if it can't find any.
2470  *
2471  * It then sets up the reg based on the object's properties: address, pitch
2472  * and tiling format.
2473  */
2474 int
2475 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2476 {
2477         struct drm_device *dev = obj->dev;
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2480         struct drm_i915_fence_reg *reg = NULL;
2481         int ret;
2482
2483         /* Just update our place in the LRU if our fence is getting used. */
2484         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2485                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2486                 return 0;
2487         }
2488
2489         switch (obj_priv->tiling_mode) {
2490         case I915_TILING_NONE:
2491                 WARN(1, "allocating a fence for non-tiled object?\n");
2492                 break;
2493         case I915_TILING_X:
2494                 if (!obj_priv->stride)
2495                         return -EINVAL;
2496                 WARN((obj_priv->stride & (512 - 1)),
2497                      "object 0x%08x is X tiled but has non-512B pitch\n",
2498                      obj_priv->gtt_offset);
2499                 break;
2500         case I915_TILING_Y:
2501                 if (!obj_priv->stride)
2502                         return -EINVAL;
2503                 WARN((obj_priv->stride & (128 - 1)),
2504                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2505                      obj_priv->gtt_offset);
2506                 break;
2507         }
2508
2509         ret = i915_find_fence_reg(dev);
2510         if (ret < 0)
2511                 return ret;
2512
2513         obj_priv->fence_reg = ret;
2514         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2515         list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2516
2517         reg->obj = obj;
2518
2519         if (IS_GEN6(dev))
2520                 sandybridge_write_fence_reg(reg);
2521         else if (IS_I965G(dev))
2522                 i965_write_fence_reg(reg);
2523         else if (IS_I9XX(dev))
2524                 i915_write_fence_reg(reg);
2525         else
2526                 i830_write_fence_reg(reg);
2527
2528         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2529                         obj_priv->tiling_mode);
2530
2531         return 0;
2532 }
2533
2534 /**
2535  * i915_gem_clear_fence_reg - clear out fence register info
2536  * @obj: object to clear
2537  *
2538  * Zeroes out the fence register itself and clears out the associated
2539  * data structures in dev_priv and obj_priv.
2540  */
2541 static void
2542 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2543 {
2544         struct drm_device *dev = obj->dev;
2545         drm_i915_private_t *dev_priv = dev->dev_private;
2546         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2547
2548         if (IS_GEN6(dev)) {
2549                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2550                              (obj_priv->fence_reg * 8), 0);
2551         } else if (IS_I965G(dev)) {
2552                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2553         } else {
2554                 uint32_t fence_reg;
2555
2556                 if (obj_priv->fence_reg < 8)
2557                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2558                 else
2559                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2560                                                        8) * 4;
2561
2562                 I915_WRITE(fence_reg, 0);
2563         }
2564
2565         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2566         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2567         list_del_init(&obj_priv->fence_list);
2568 }
2569
2570 /**
2571  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2572  * to the buffer to finish, and then resets the fence register.
2573  * @obj: tiled object holding a fence register.
2574  *
2575  * Zeroes out the fence register itself and clears out the associated
2576  * data structures in dev_priv and obj_priv.
2577  */
2578 int
2579 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2580 {
2581         struct drm_device *dev = obj->dev;
2582         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2583
2584         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2585                 return 0;
2586
2587         /* If we've changed tiling, GTT-mappings of the object
2588          * need to re-fault to ensure that the correct fence register
2589          * setup is in place.
2590          */
2591         i915_gem_release_mmap(obj);
2592
2593         /* On the i915, GPU access to tiled buffers is via a fence,
2594          * therefore we must wait for any outstanding access to complete
2595          * before clearing the fence.
2596          */
2597         if (!IS_I965G(dev)) {
2598                 int ret;
2599
2600                 i915_gem_object_flush_gpu_write_domain(obj);
2601                 ret = i915_gem_object_wait_rendering(obj);
2602                 if (ret != 0)
2603                         return ret;
2604         }
2605
2606         i915_gem_object_flush_gtt_write_domain(obj);
2607         i915_gem_clear_fence_reg (obj);
2608
2609         return 0;
2610 }
2611
2612 /**
2613  * Finds free space in the GTT aperture and binds the object there.
2614  */
2615 static int
2616 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2617 {
2618         struct drm_device *dev = obj->dev;
2619         drm_i915_private_t *dev_priv = dev->dev_private;
2620         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2621         struct drm_mm_node *free_space;
2622         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2623         int ret;
2624
2625         if (obj_priv->madv != I915_MADV_WILLNEED) {
2626                 DRM_ERROR("Attempting to bind a purgeable object\n");
2627                 return -EINVAL;
2628         }
2629
2630         if (alignment == 0)
2631                 alignment = i915_gem_get_gtt_alignment(obj);
2632         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2633                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2634                 return -EINVAL;
2635         }
2636
2637  search_free:
2638         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2639                                         obj->size, alignment, 0);
2640         if (free_space != NULL) {
2641                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2642                                                        alignment);
2643                 if (obj_priv->gtt_space != NULL) {
2644                         obj_priv->gtt_space->private = obj;
2645                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2646                 }
2647         }
2648         if (obj_priv->gtt_space == NULL) {
2649                 /* If the gtt is empty and we're still having trouble
2650                  * fitting our object in, we're out of memory.
2651                  */
2652 #if WATCH_LRU
2653                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2654 #endif
2655                 ret = i915_gem_evict_something(dev, obj->size);
2656                 if (ret)
2657                         return ret;
2658
2659                 goto search_free;
2660         }
2661
2662 #if WATCH_BUF
2663         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2664                  obj->size, obj_priv->gtt_offset);
2665 #endif
2666         ret = i915_gem_object_get_pages(obj, gfpmask);
2667         if (ret) {
2668                 drm_mm_put_block(obj_priv->gtt_space);
2669                 obj_priv->gtt_space = NULL;
2670
2671                 if (ret == -ENOMEM) {
2672                         /* first try to clear up some space from the GTT */
2673                         ret = i915_gem_evict_something(dev, obj->size);
2674                         if (ret) {
2675                                 /* now try to shrink everyone else */
2676                                 if (gfpmask) {
2677                                         gfpmask = 0;
2678                                         goto search_free;
2679                                 }
2680
2681                                 return ret;
2682                         }
2683
2684                         goto search_free;
2685                 }
2686
2687                 return ret;
2688         }
2689
2690         /* Create an AGP memory structure pointing at our pages, and bind it
2691          * into the GTT.
2692          */
2693         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2694                                                obj_priv->pages,
2695                                                obj->size >> PAGE_SHIFT,
2696                                                obj_priv->gtt_offset,
2697                                                obj_priv->agp_type);
2698         if (obj_priv->agp_mem == NULL) {
2699                 i915_gem_object_put_pages(obj);
2700                 drm_mm_put_block(obj_priv->gtt_space);
2701                 obj_priv->gtt_space = NULL;
2702
2703                 ret = i915_gem_evict_something(dev, obj->size);
2704                 if (ret)
2705                         return ret;
2706
2707                 goto search_free;
2708         }
2709         atomic_inc(&dev->gtt_count);
2710         atomic_add(obj->size, &dev->gtt_memory);
2711
2712         /* Assert that the object is not currently in any GPU domain. As it
2713          * wasn't in the GTT, there shouldn't be any way it could have been in
2714          * a GPU cache
2715          */
2716         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2717         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2718
2719         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2720
2721         return 0;
2722 }
2723
2724 void
2725 i915_gem_clflush_object(struct drm_gem_object *obj)
2726 {
2727         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2728
2729         /* If we don't have a page list set up, then we're not pinned
2730          * to GPU, and we can ignore the cache flush because it'll happen
2731          * again at bind time.
2732          */
2733         if (obj_priv->pages == NULL)
2734                 return;
2735
2736         trace_i915_gem_object_clflush(obj);
2737
2738         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2739 }
2740
2741 /** Flushes any GPU write domain for the object if it's dirty. */
2742 static void
2743 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2744 {
2745         struct drm_device *dev = obj->dev;
2746         uint32_t old_write_domain;
2747
2748         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2749                 return;
2750
2751         /* Queue the GPU write cache flushing we need. */
2752         old_write_domain = obj->write_domain;
2753         i915_gem_flush(dev, 0, obj->write_domain);
2754         (void) i915_add_request(dev, NULL, obj->write_domain);
2755         BUG_ON(obj->write_domain);
2756
2757         trace_i915_gem_object_change_domain(obj,
2758                                             obj->read_domains,
2759                                             old_write_domain);
2760 }
2761
2762 /** Flushes the GTT write domain for the object if it's dirty. */
2763 static void
2764 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2765 {
2766         uint32_t old_write_domain;
2767
2768         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2769                 return;
2770
2771         /* No actual flushing is required for the GTT write domain.   Writes
2772          * to it immediately go to main memory as far as we know, so there's
2773          * no chipset flush.  It also doesn't land in render cache.
2774          */
2775         old_write_domain = obj->write_domain;
2776         obj->write_domain = 0;
2777
2778         trace_i915_gem_object_change_domain(obj,
2779                                             obj->read_domains,
2780                                             old_write_domain);
2781 }
2782
2783 /** Flushes the CPU write domain for the object if it's dirty. */
2784 static void
2785 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2786 {
2787         struct drm_device *dev = obj->dev;
2788         uint32_t old_write_domain;
2789
2790         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2791                 return;
2792
2793         i915_gem_clflush_object(obj);
2794         drm_agp_chipset_flush(dev);
2795         old_write_domain = obj->write_domain;
2796         obj->write_domain = 0;
2797
2798         trace_i915_gem_object_change_domain(obj,
2799                                             obj->read_domains,
2800                                             old_write_domain);
2801 }
2802
2803 void
2804 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2805 {
2806         switch (obj->write_domain) {
2807         case I915_GEM_DOMAIN_GTT:
2808                 i915_gem_object_flush_gtt_write_domain(obj);
2809                 break;
2810         case I915_GEM_DOMAIN_CPU:
2811                 i915_gem_object_flush_cpu_write_domain(obj);
2812                 break;
2813         default:
2814                 i915_gem_object_flush_gpu_write_domain(obj);
2815                 break;
2816         }
2817 }
2818
2819 /**
2820  * Moves a single object to the GTT read, and possibly write domain.
2821  *
2822  * This function returns when the move is complete, including waiting on
2823  * flushes to occur.
2824  */
2825 int
2826 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2827 {
2828         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2829         uint32_t old_write_domain, old_read_domains;
2830         int ret;
2831
2832         /* Not valid to be called on unbound objects. */
2833         if (obj_priv->gtt_space == NULL)
2834                 return -EINVAL;
2835
2836         i915_gem_object_flush_gpu_write_domain(obj);
2837         /* Wait on any GPU rendering and flushing to occur. */
2838         ret = i915_gem_object_wait_rendering(obj);
2839         if (ret != 0)
2840                 return ret;
2841
2842         old_write_domain = obj->write_domain;
2843         old_read_domains = obj->read_domains;
2844
2845         /* If we're writing through the GTT domain, then CPU and GPU caches
2846          * will need to be invalidated at next use.
2847          */
2848         if (write)
2849                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2850
2851         i915_gem_object_flush_cpu_write_domain(obj);
2852
2853         /* It should now be out of any other write domains, and we can update
2854          * the domain values for our changes.
2855          */
2856         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2857         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2858         if (write) {
2859                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2860                 obj_priv->dirty = 1;
2861         }
2862
2863         trace_i915_gem_object_change_domain(obj,
2864                                             old_read_domains,
2865                                             old_write_domain);
2866
2867         return 0;
2868 }
2869
2870 /*
2871  * Prepare buffer for display plane. Use uninterruptible for possible flush
2872  * wait, as in modesetting process we're not supposed to be interrupted.
2873  */
2874 int
2875 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2876 {
2877         struct drm_device *dev = obj->dev;
2878         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2879         uint32_t old_write_domain, old_read_domains;
2880         int ret;
2881
2882         /* Not valid to be called on unbound objects. */
2883         if (obj_priv->gtt_space == NULL)
2884                 return -EINVAL;
2885
2886         i915_gem_object_flush_gpu_write_domain(obj);
2887
2888         /* Wait on any GPU rendering and flushing to occur. */
2889         if (obj_priv->active) {
2890 #if WATCH_BUF
2891                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2892                           __func__, obj, obj_priv->last_rendering_seqno);
2893 #endif
2894                 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2895                 if (ret != 0)
2896                         return ret;
2897         }
2898
2899         old_write_domain = obj->write_domain;
2900         old_read_domains = obj->read_domains;
2901
2902         obj->read_domains &= I915_GEM_DOMAIN_GTT;
2903
2904         i915_gem_object_flush_cpu_write_domain(obj);
2905
2906         /* It should now be out of any other write domains, and we can update
2907          * the domain values for our changes.
2908          */
2909         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2910         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2911         obj->write_domain = I915_GEM_DOMAIN_GTT;
2912         obj_priv->dirty = 1;
2913
2914         trace_i915_gem_object_change_domain(obj,
2915                                             old_read_domains,
2916                                             old_write_domain);
2917
2918         return 0;
2919 }
2920
2921 /**
2922  * Moves a single object to the CPU read, and possibly write domain.
2923  *
2924  * This function returns when the move is complete, including waiting on
2925  * flushes to occur.
2926  */
2927 static int
2928 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2929 {
2930         uint32_t old_write_domain, old_read_domains;
2931         int ret;
2932
2933         i915_gem_object_flush_gpu_write_domain(obj);
2934         /* Wait on any GPU rendering and flushing to occur. */
2935         ret = i915_gem_object_wait_rendering(obj);
2936         if (ret != 0)
2937                 return ret;
2938
2939         i915_gem_object_flush_gtt_write_domain(obj);
2940
2941         /* If we have a partially-valid cache of the object in the CPU,
2942          * finish invalidating it and free the per-page flags.
2943          */
2944         i915_gem_object_set_to_full_cpu_read_domain(obj);
2945
2946         old_write_domain = obj->write_domain;
2947         old_read_domains = obj->read_domains;
2948
2949         /* Flush the CPU cache if it's still invalid. */
2950         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2951                 i915_gem_clflush_object(obj);
2952
2953                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2954         }
2955
2956         /* It should now be out of any other write domains, and we can update
2957          * the domain values for our changes.
2958          */
2959         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2960
2961         /* If we're writing through the CPU, then the GPU read domains will
2962          * need to be invalidated at next use.
2963          */
2964         if (write) {
2965                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2966                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2967         }
2968
2969         trace_i915_gem_object_change_domain(obj,
2970                                             old_read_domains,
2971                                             old_write_domain);
2972
2973         return 0;
2974 }
2975
2976 /*
2977  * Set the next domain for the specified object. This
2978  * may not actually perform the necessary flushing/invaliding though,
2979  * as that may want to be batched with other set_domain operations
2980  *
2981  * This is (we hope) the only really tricky part of gem. The goal
2982  * is fairly simple -- track which caches hold bits of the object
2983  * and make sure they remain coherent. A few concrete examples may
2984  * help to explain how it works. For shorthand, we use the notation
2985  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2986  * a pair of read and write domain masks.
2987  *
2988  * Case 1: the batch buffer
2989  *
2990  *      1. Allocated
2991  *      2. Written by CPU
2992  *      3. Mapped to GTT
2993  *      4. Read by GPU
2994  *      5. Unmapped from GTT
2995  *      6. Freed
2996  *
2997  *      Let's take these a step at a time
2998  *
2999  *      1. Allocated
3000  *              Pages allocated from the kernel may still have
3001  *              cache contents, so we set them to (CPU, CPU) always.
3002  *      2. Written by CPU (using pwrite)
3003  *              The pwrite function calls set_domain (CPU, CPU) and
3004  *              this function does nothing (as nothing changes)
3005  *      3. Mapped by GTT
3006  *              This function asserts that the object is not
3007  *              currently in any GPU-based read or write domains
3008  *      4. Read by GPU
3009  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3010  *              As write_domain is zero, this function adds in the
3011  *              current read domains (CPU+COMMAND, 0).
3012  *              flush_domains is set to CPU.
3013  *              invalidate_domains is set to COMMAND
3014  *              clflush is run to get data out of the CPU caches
3015  *              then i915_dev_set_domain calls i915_gem_flush to
3016  *              emit an MI_FLUSH and drm_agp_chipset_flush
3017  *      5. Unmapped from GTT
3018  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3019  *              flush_domains and invalidate_domains end up both zero
3020  *              so no flushing/invalidating happens
3021  *      6. Freed
3022  *              yay, done
3023  *
3024  * Case 2: The shared render buffer
3025  *
3026  *      1. Allocated
3027  *      2. Mapped to GTT
3028  *      3. Read/written by GPU
3029  *      4. set_domain to (CPU,CPU)
3030  *      5. Read/written by CPU
3031  *      6. Read/written by GPU
3032  *
3033  *      1. Allocated
3034  *              Same as last example, (CPU, CPU)
3035  *      2. Mapped to GTT
3036  *              Nothing changes (assertions find that it is not in the GPU)
3037  *      3. Read/written by GPU
3038  *              execbuffer calls set_domain (RENDER, RENDER)
3039  *              flush_domains gets CPU
3040  *              invalidate_domains gets GPU
3041  *              clflush (obj)
3042  *              MI_FLUSH and drm_agp_chipset_flush
3043  *      4. set_domain (CPU, CPU)
3044  *              flush_domains gets GPU
3045  *              invalidate_domains gets CPU
3046  *              wait_rendering (obj) to make sure all drawing is complete.
3047  *              This will include an MI_FLUSH to get the data from GPU
3048  *              to memory
3049  *              clflush (obj) to invalidate the CPU cache
3050  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3051  *      5. Read/written by CPU
3052  *              cache lines are loaded and dirtied
3053  *      6. Read written by GPU
3054  *              Same as last GPU access
3055  *
3056  * Case 3: The constant buffer
3057  *
3058  *      1. Allocated
3059  *      2. Written by CPU
3060  *      3. Read by GPU
3061  *      4. Updated (written) by CPU again
3062  *      5. Read by GPU
3063  *
3064  *      1. Allocated
3065  *              (CPU, CPU)
3066  *      2. Written by CPU
3067  *              (CPU, CPU)
3068  *      3. Read by GPU
3069  *              (CPU+RENDER, 0)
3070  *              flush_domains = CPU
3071  *              invalidate_domains = RENDER
3072  *              clflush (obj)
3073  *              MI_FLUSH
3074  *              drm_agp_chipset_flush
3075  *      4. Updated (written) by CPU again
3076  *              (CPU, CPU)
3077  *              flush_domains = 0 (no previous write domain)
3078  *              invalidate_domains = 0 (no new read domains)
3079  *      5. Read by GPU
3080  *              (CPU+RENDER, 0)
3081  *              flush_domains = CPU
3082  *              invalidate_domains = RENDER
3083  *              clflush (obj)
3084  *              MI_FLUSH
3085  *              drm_agp_chipset_flush
3086  */
3087 static void
3088 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3089 {
3090         struct drm_device               *dev = obj->dev;
3091         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
3092         uint32_t                        invalidate_domains = 0;
3093         uint32_t                        flush_domains = 0;
3094         uint32_t                        old_read_domains;
3095
3096         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3097         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3098
3099         intel_mark_busy(dev, obj);
3100
3101 #if WATCH_BUF
3102         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3103                  __func__, obj,
3104                  obj->read_domains, obj->pending_read_domains,
3105                  obj->write_domain, obj->pending_write_domain);
3106 #endif
3107         /*
3108          * If the object isn't moving to a new write domain,
3109          * let the object stay in multiple read domains
3110          */
3111         if (obj->pending_write_domain == 0)
3112                 obj->pending_read_domains |= obj->read_domains;
3113         else
3114                 obj_priv->dirty = 1;
3115
3116         /*
3117          * Flush the current write domain if
3118          * the new read domains don't match. Invalidate
3119          * any read domains which differ from the old
3120          * write domain
3121          */
3122         if (obj->write_domain &&
3123             obj->write_domain != obj->pending_read_domains) {
3124                 flush_domains |= obj->write_domain;
3125                 invalidate_domains |=
3126                         obj->pending_read_domains & ~obj->write_domain;
3127         }
3128         /*
3129          * Invalidate any read caches which may have
3130          * stale data. That is, any new read domains.
3131          */
3132         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3133         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3134 #if WATCH_BUF
3135                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3136                          __func__, flush_domains, invalidate_domains);
3137 #endif
3138                 i915_gem_clflush_object(obj);
3139         }
3140
3141         old_read_domains = obj->read_domains;
3142
3143         /* The actual obj->write_domain will be updated with
3144          * pending_write_domain after we emit the accumulated flush for all
3145          * of our domain changes in execbuffers (which clears objects'
3146          * write_domains).  So if we have a current write domain that we
3147          * aren't changing, set pending_write_domain to that.
3148          */
3149         if (flush_domains == 0 && obj->pending_write_domain == 0)
3150                 obj->pending_write_domain = obj->write_domain;
3151         obj->read_domains = obj->pending_read_domains;
3152
3153         dev->invalidate_domains |= invalidate_domains;
3154         dev->flush_domains |= flush_domains;
3155 #if WATCH_BUF
3156         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3157                  __func__,
3158                  obj->read_domains, obj->write_domain,
3159                  dev->invalidate_domains, dev->flush_domains);
3160 #endif
3161
3162         trace_i915_gem_object_change_domain(obj,
3163                                             old_read_domains,
3164                                             obj->write_domain);
3165 }
3166
3167 /**
3168  * Moves the object from a partially CPU read to a full one.
3169  *
3170  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3171  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3172  */
3173 static void
3174 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3175 {
3176         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3177
3178         if (!obj_priv->page_cpu_valid)
3179                 return;
3180
3181         /* If we're partially in the CPU read domain, finish moving it in.
3182          */
3183         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3184                 int i;
3185
3186                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3187                         if (obj_priv->page_cpu_valid[i])
3188                                 continue;
3189                         drm_clflush_pages(obj_priv->pages + i, 1);
3190                 }
3191         }
3192
3193         /* Free the page_cpu_valid mappings which are now stale, whether
3194          * or not we've got I915_GEM_DOMAIN_CPU.
3195          */
3196         kfree(obj_priv->page_cpu_valid);
3197         obj_priv->page_cpu_valid = NULL;
3198 }
3199
3200 /**
3201  * Set the CPU read domain on a range of the object.
3202  *
3203  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3204  * not entirely valid.  The page_cpu_valid member of the object flags which
3205  * pages have been flushed, and will be respected by
3206  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3207  * of the whole object.
3208  *
3209  * This function returns when the move is complete, including waiting on
3210  * flushes to occur.
3211  */
3212 static int
3213 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3214                                           uint64_t offset, uint64_t size)
3215 {
3216         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3217         uint32_t old_read_domains;
3218         int i, ret;
3219
3220         if (offset == 0 && size == obj->size)
3221                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3222
3223         i915_gem_object_flush_gpu_write_domain(obj);
3224         /* Wait on any GPU rendering and flushing to occur. */
3225         ret = i915_gem_object_wait_rendering(obj);
3226         if (ret != 0)
3227                 return ret;
3228         i915_gem_object_flush_gtt_write_domain(obj);
3229
3230         /* If we're already fully in the CPU read domain, we're done. */
3231         if (obj_priv->page_cpu_valid == NULL &&
3232             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3233                 return 0;
3234
3235         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3236          * newly adding I915_GEM_DOMAIN_CPU
3237          */
3238         if (obj_priv->page_cpu_valid == NULL) {
3239                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3240                                                    GFP_KERNEL);
3241                 if (obj_priv->page_cpu_valid == NULL)
3242                         return -ENOMEM;
3243         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3244                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3245
3246         /* Flush the cache on any pages that are still invalid from the CPU's
3247          * perspective.
3248          */
3249         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3250              i++) {
3251                 if (obj_priv->page_cpu_valid[i])
3252                         continue;
3253
3254                 drm_clflush_pages(obj_priv->pages + i, 1);
3255
3256                 obj_priv->page_cpu_valid[i] = 1;
3257         }
3258
3259         /* It should now be out of any other write domains, and we can update
3260          * the domain values for our changes.
3261          */
3262         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3263
3264         old_read_domains = obj->read_domains;
3265         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3266
3267         trace_i915_gem_object_change_domain(obj,
3268                                             old_read_domains,
3269                                             obj->write_domain);
3270
3271         return 0;
3272 }
3273
3274 /**
3275  * Pin an object to the GTT and evaluate the relocations landing in it.
3276  */
3277 static int
3278 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3279                                  struct drm_file *file_priv,
3280                                  struct drm_i915_gem_exec_object2 *entry,
3281                                  struct drm_i915_gem_relocation_entry *relocs)
3282 {
3283         struct drm_device *dev = obj->dev;
3284         drm_i915_private_t *dev_priv = dev->dev_private;
3285         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3286         int i, ret;
3287         void __iomem *reloc_page;
3288         bool need_fence;
3289
3290         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3291                      obj_priv->tiling_mode != I915_TILING_NONE;
3292
3293         /* Check fence reg constraints and rebind if necessary */
3294         if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3295             obj_priv->tiling_mode))
3296                 i915_gem_object_unbind(obj);
3297
3298         /* Choose the GTT offset for our buffer and put it there. */
3299         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3300         if (ret)
3301                 return ret;
3302
3303         /*
3304          * Pre-965 chips need a fence register set up in order to
3305          * properly handle blits to/from tiled surfaces.
3306          */
3307         if (need_fence) {
3308                 ret = i915_gem_object_get_fence_reg(obj);
3309                 if (ret != 0) {
3310                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3311                                 DRM_ERROR("Failure to install fence: %d\n",
3312                                           ret);
3313                         i915_gem_object_unpin(obj);
3314                         return ret;
3315                 }
3316         }
3317
3318         entry->offset = obj_priv->gtt_offset;
3319
3320         /* Apply the relocations, using the GTT aperture to avoid cache
3321          * flushing requirements.
3322          */
3323         for (i = 0; i < entry->relocation_count; i++) {
3324                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3325                 struct drm_gem_object *target_obj;
3326                 struct drm_i915_gem_object *target_obj_priv;
3327                 uint32_t reloc_val, reloc_offset;
3328                 uint32_t __iomem *reloc_entry;
3329
3330                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3331                                                    reloc->target_handle);
3332                 if (target_obj == NULL) {
3333                         i915_gem_object_unpin(obj);
3334                         return -EBADF;
3335                 }
3336                 target_obj_priv = target_obj->driver_private;
3337
3338 #if WATCH_RELOC
3339                 DRM_INFO("%s: obj %p offset %08x target %d "
3340                          "read %08x write %08x gtt %08x "
3341                          "presumed %08x delta %08x\n",
3342                          __func__,
3343                          obj,
3344                          (int) reloc->offset,
3345                          (int) reloc->target_handle,
3346                          (int) reloc->read_domains,
3347                          (int) reloc->write_domain,
3348                          (int) target_obj_priv->gtt_offset,
3349                          (int) reloc->presumed_offset,
3350                          reloc->delta);
3351 #endif
3352
3353                 /* The target buffer should have appeared before us in the
3354                  * exec_object list, so it should have a GTT space bound by now.
3355                  */
3356                 if (target_obj_priv->gtt_space == NULL) {
3357                         DRM_ERROR("No GTT space found for object %d\n",
3358                                   reloc->target_handle);
3359                         drm_gem_object_unreference(target_obj);
3360                         i915_gem_object_unpin(obj);
3361                         return -EINVAL;
3362                 }
3363
3364                 /* Validate that the target is in a valid r/w GPU domain */
3365                 if (reloc->write_domain & (reloc->write_domain - 1)) {
3366                         DRM_ERROR("reloc with multiple write domains: "
3367                                   "obj %p target %d offset %d "
3368                                   "read %08x write %08x",
3369                                   obj, reloc->target_handle,
3370                                   (int) reloc->offset,
3371                                   reloc->read_domains,
3372                                   reloc->write_domain);
3373                         return -EINVAL;
3374                 }
3375                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3376                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3377                         DRM_ERROR("reloc with read/write CPU domains: "
3378                                   "obj %p target %d offset %d "
3379                                   "read %08x write %08x",
3380                                   obj, reloc->target_handle,
3381                                   (int) reloc->offset,
3382                                   reloc->read_domains,
3383                                   reloc->write_domain);
3384                         drm_gem_object_unreference(target_obj);
3385                         i915_gem_object_unpin(obj);
3386                         return -EINVAL;
3387                 }
3388                 if (reloc->write_domain && target_obj->pending_write_domain &&
3389                     reloc->write_domain != target_obj->pending_write_domain) {
3390                         DRM_ERROR("Write domain conflict: "
3391                                   "obj %p target %d offset %d "
3392                                   "new %08x old %08x\n",
3393                                   obj, reloc->target_handle,
3394                                   (int) reloc->offset,
3395                                   reloc->write_domain,
3396                                   target_obj->pending_write_domain);
3397                         drm_gem_object_unreference(target_obj);
3398                         i915_gem_object_unpin(obj);
3399                         return -EINVAL;
3400                 }
3401
3402                 target_obj->pending_read_domains |= reloc->read_domains;
3403                 target_obj->pending_write_domain |= reloc->write_domain;
3404
3405                 /* If the relocation already has the right value in it, no
3406                  * more work needs to be done.
3407                  */
3408                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3409                         drm_gem_object_unreference(target_obj);
3410                         continue;
3411                 }
3412
3413                 /* Check that the relocation address is valid... */
3414                 if (reloc->offset > obj->size - 4) {
3415                         DRM_ERROR("Relocation beyond object bounds: "
3416                                   "obj %p target %d offset %d size %d.\n",
3417                                   obj, reloc->target_handle,
3418                                   (int) reloc->offset, (int) obj->size);
3419                         drm_gem_object_unreference(target_obj);
3420                         i915_gem_object_unpin(obj);
3421                         return -EINVAL;
3422                 }
3423                 if (reloc->offset & 3) {
3424                         DRM_ERROR("Relocation not 4-byte aligned: "
3425                                   "obj %p target %d offset %d.\n",
3426                                   obj, reloc->target_handle,
3427                                   (int) reloc->offset);
3428                         drm_gem_object_unreference(target_obj);
3429                         i915_gem_object_unpin(obj);
3430                         return -EINVAL;
3431                 }
3432
3433                 /* and points to somewhere within the target object. */
3434                 if (reloc->delta >= target_obj->size) {
3435                         DRM_ERROR("Relocation beyond target object bounds: "
3436                                   "obj %p target %d delta %d size %d.\n",
3437                                   obj, reloc->target_handle,
3438                                   (int) reloc->delta, (int) target_obj->size);
3439                         drm_gem_object_unreference(target_obj);
3440                         i915_gem_object_unpin(obj);
3441                         return -EINVAL;
3442                 }
3443
3444                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3445                 if (ret != 0) {
3446                         drm_gem_object_unreference(target_obj);
3447                         i915_gem_object_unpin(obj);
3448                         return -EINVAL;
3449                 }
3450
3451                 /* Map the page containing the relocation we're going to
3452                  * perform.
3453                  */
3454                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3455                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3456                                                       (reloc_offset &
3457                                                        ~(PAGE_SIZE - 1)));
3458                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3459                                                    (reloc_offset & (PAGE_SIZE - 1)));
3460                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3461
3462 #if WATCH_BUF
3463                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3464                           obj, (unsigned int) reloc->offset,
3465                           readl(reloc_entry), reloc_val);
3466 #endif
3467                 writel(reloc_val, reloc_entry);
3468                 io_mapping_unmap_atomic(reloc_page);
3469
3470                 /* The updated presumed offset for this entry will be
3471                  * copied back out to the user.
3472                  */
3473                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3474
3475                 drm_gem_object_unreference(target_obj);
3476         }
3477
3478 #if WATCH_BUF
3479         if (0)
3480                 i915_gem_dump_object(obj, 128, __func__, ~0);
3481 #endif
3482         return 0;
3483 }
3484
3485 /** Dispatch a batchbuffer to the ring
3486  */
3487 static int
3488 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3489                               struct drm_i915_gem_execbuffer2 *exec,
3490                               struct drm_clip_rect *cliprects,
3491                               uint64_t exec_offset)
3492 {
3493         drm_i915_private_t *dev_priv = dev->dev_private;
3494         int nbox = exec->num_cliprects;
3495         int i = 0, count;
3496         uint32_t exec_start, exec_len;
3497         RING_LOCALS;
3498
3499         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3500         exec_len = (uint32_t) exec->batch_len;
3501
3502         trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3503
3504         count = nbox ? nbox : 1;
3505
3506         for (i = 0; i < count; i++) {
3507                 if (i < nbox) {
3508                         int ret = i915_emit_box(dev, cliprects, i,
3509                                                 exec->DR1, exec->DR4);
3510                         if (ret)
3511                                 return ret;
3512                 }
3513
3514                 if (IS_I830(dev) || IS_845G(dev)) {
3515                         BEGIN_LP_RING(4);
3516                         OUT_RING(MI_BATCH_BUFFER);
3517                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3518                         OUT_RING(exec_start + exec_len - 4);
3519                         OUT_RING(0);
3520                         ADVANCE_LP_RING();
3521                 } else {
3522                         BEGIN_LP_RING(2);
3523                         if (IS_I965G(dev)) {
3524                                 OUT_RING(MI_BATCH_BUFFER_START |
3525                                          (2 << 6) |
3526                                          MI_BATCH_NON_SECURE_I965);
3527                                 OUT_RING(exec_start);
3528                         } else {
3529                                 OUT_RING(MI_BATCH_BUFFER_START |
3530                                          (2 << 6));
3531                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3532                         }
3533                         ADVANCE_LP_RING();
3534                 }
3535         }
3536
3537         /* XXX breadcrumb */
3538         return 0;
3539 }
3540
3541 /* Throttle our rendering by waiting until the ring has completed our requests
3542  * emitted over 20 msec ago.
3543  *
3544  * Note that if we were to use the current jiffies each time around the loop,
3545  * we wouldn't escape the function with any frames outstanding if the time to
3546  * render a frame was over 20ms.
3547  *
3548  * This should get us reasonable parallelism between CPU and GPU but also
3549  * relatively low latency when blocking on a particular request to finish.
3550  */
3551 static int
3552 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3553 {
3554         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3555         int ret = 0;
3556         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3557
3558         mutex_lock(&dev->struct_mutex);
3559         while (!list_empty(&i915_file_priv->mm.request_list)) {
3560                 struct drm_i915_gem_request *request;
3561
3562                 request = list_first_entry(&i915_file_priv->mm.request_list,
3563                                            struct drm_i915_gem_request,
3564                                            client_list);
3565
3566                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3567                         break;
3568
3569                 ret = i915_wait_request(dev, request->seqno);
3570                 if (ret != 0)
3571                         break;
3572         }
3573         mutex_unlock(&dev->struct_mutex);
3574
3575         return ret;
3576 }
3577
3578 static int
3579 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3580                               uint32_t buffer_count,
3581                               struct drm_i915_gem_relocation_entry **relocs)
3582 {
3583         uint32_t reloc_count = 0, reloc_index = 0, i;
3584         int ret;
3585
3586         *relocs = NULL;
3587         for (i = 0; i < buffer_count; i++) {
3588                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3589                         return -EINVAL;
3590                 reloc_count += exec_list[i].relocation_count;
3591         }
3592
3593         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3594         if (*relocs == NULL) {
3595                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3596                 return -ENOMEM;
3597         }
3598
3599         for (i = 0; i < buffer_count; i++) {
3600                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3601
3602                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3603
3604                 ret = copy_from_user(&(*relocs)[reloc_index],
3605                                      user_relocs,
3606                                      exec_list[i].relocation_count *
3607                                      sizeof(**relocs));
3608                 if (ret != 0) {
3609                         drm_free_large(*relocs);
3610                         *relocs = NULL;
3611                         return -EFAULT;
3612                 }
3613
3614                 reloc_index += exec_list[i].relocation_count;
3615         }
3616
3617         return 0;
3618 }
3619
3620 static int
3621 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3622                             uint32_t buffer_count,
3623                             struct drm_i915_gem_relocation_entry *relocs)
3624 {
3625         uint32_t reloc_count = 0, i;
3626         int ret = 0;
3627
3628         if (relocs == NULL)
3629             return 0;
3630
3631         for (i = 0; i < buffer_count; i++) {
3632                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3633                 int unwritten;
3634
3635                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3636
3637                 unwritten = copy_to_user(user_relocs,
3638                                          &relocs[reloc_count],
3639                                          exec_list[i].relocation_count *
3640                                          sizeof(*relocs));
3641
3642                 if (unwritten) {
3643                         ret = -EFAULT;
3644                         goto err;
3645                 }
3646
3647                 reloc_count += exec_list[i].relocation_count;
3648         }
3649
3650 err:
3651         drm_free_large(relocs);
3652
3653         return ret;
3654 }
3655
3656 static int
3657 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3658                            uint64_t exec_offset)
3659 {
3660         uint32_t exec_start, exec_len;
3661
3662         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3663         exec_len = (uint32_t) exec->batch_len;
3664
3665         if ((exec_start | exec_len) & 0x7)
3666                 return -EINVAL;
3667
3668         if (!exec_start)
3669                 return -EINVAL;
3670
3671         return 0;
3672 }
3673
3674 static int
3675 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3676                                struct drm_gem_object **object_list,
3677                                int count)
3678 {
3679         drm_i915_private_t *dev_priv = dev->dev_private;
3680         struct drm_i915_gem_object *obj_priv;
3681         DEFINE_WAIT(wait);
3682         int i, ret = 0;
3683
3684         for (;;) {
3685                 prepare_to_wait(&dev_priv->pending_flip_queue,
3686                                 &wait, TASK_INTERRUPTIBLE);
3687                 for (i = 0; i < count; i++) {
3688                         obj_priv = object_list[i]->driver_private;
3689                         if (atomic_read(&obj_priv->pending_flip) > 0)
3690                                 break;
3691                 }
3692                 if (i == count)
3693                         break;
3694
3695                 if (!signal_pending(current)) {
3696                         mutex_unlock(&dev->struct_mutex);
3697                         schedule();
3698                         mutex_lock(&dev->struct_mutex);
3699                         continue;
3700                 }
3701                 ret = -ERESTARTSYS;
3702                 break;
3703         }
3704         finish_wait(&dev_priv->pending_flip_queue, &wait);
3705
3706         return ret;
3707 }
3708
3709 int
3710 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3711                        struct drm_file *file_priv,
3712                        struct drm_i915_gem_execbuffer2 *args,
3713                        struct drm_i915_gem_exec_object2 *exec_list)
3714 {
3715         drm_i915_private_t *dev_priv = dev->dev_private;
3716         struct drm_gem_object **object_list = NULL;
3717         struct drm_gem_object *batch_obj;
3718         struct drm_i915_gem_object *obj_priv;
3719         struct drm_clip_rect *cliprects = NULL;
3720         struct drm_i915_gem_relocation_entry *relocs = NULL;
3721         int ret = 0, ret2, i, pinned = 0;
3722         uint64_t exec_offset;
3723         uint32_t seqno, flush_domains, reloc_index;
3724         int pin_tries, flips;
3725
3726 #if WATCH_EXEC
3727         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3728                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3729 #endif
3730
3731         if (args->buffer_count < 1) {
3732                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3733                 return -EINVAL;
3734         }
3735         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3736         if (object_list == NULL) {
3737                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3738                           args->buffer_count);
3739                 ret = -ENOMEM;
3740                 goto pre_mutex_err;
3741         }
3742
3743         if (args->num_cliprects != 0) {
3744                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3745                                     GFP_KERNEL);
3746                 if (cliprects == NULL) {
3747                         ret = -ENOMEM;
3748                         goto pre_mutex_err;
3749                 }
3750
3751                 ret = copy_from_user(cliprects,
3752                                      (struct drm_clip_rect __user *)
3753                                      (uintptr_t) args->cliprects_ptr,
3754                                      sizeof(*cliprects) * args->num_cliprects);
3755                 if (ret != 0) {
3756                         DRM_ERROR("copy %d cliprects failed: %d\n",
3757                                   args->num_cliprects, ret);
3758                         goto pre_mutex_err;
3759                 }
3760         }
3761
3762         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3763                                             &relocs);
3764         if (ret != 0)
3765                 goto pre_mutex_err;
3766
3767         mutex_lock(&dev->struct_mutex);
3768
3769         i915_verify_inactive(dev, __FILE__, __LINE__);
3770
3771         if (atomic_read(&dev_priv->mm.wedged)) {
3772                 mutex_unlock(&dev->struct_mutex);
3773                 ret = -EIO;
3774                 goto pre_mutex_err;
3775         }
3776
3777         if (dev_priv->mm.suspended) {
3778                 mutex_unlock(&dev->struct_mutex);
3779                 ret = -EBUSY;
3780                 goto pre_mutex_err;
3781         }
3782
3783         /* Look up object handles */
3784         flips = 0;
3785         for (i = 0; i < args->buffer_count; i++) {
3786                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3787                                                        exec_list[i].handle);
3788                 if (object_list[i] == NULL) {
3789                         DRM_ERROR("Invalid object handle %d at index %d\n",
3790                                    exec_list[i].handle, i);
3791                         /* prevent error path from reading uninitialized data */
3792                         args->buffer_count = i + 1;
3793                         ret = -EBADF;
3794                         goto err;
3795                 }
3796
3797                 obj_priv = object_list[i]->driver_private;
3798                 if (obj_priv->in_execbuffer) {
3799                         DRM_ERROR("Object %p appears more than once in object list\n",
3800                                    object_list[i]);
3801                         /* prevent error path from reading uninitialized data */
3802                         args->buffer_count = i + 1;
3803                         ret = -EBADF;
3804                         goto err;
3805                 }
3806                 obj_priv->in_execbuffer = true;
3807                 flips += atomic_read(&obj_priv->pending_flip);
3808         }
3809
3810         if (flips > 0) {
3811                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3812                                                      args->buffer_count);
3813                 if (ret)
3814                         goto err;
3815         }
3816
3817         /* Pin and relocate */
3818         for (pin_tries = 0; ; pin_tries++) {
3819                 ret = 0;
3820                 reloc_index = 0;
3821
3822                 for (i = 0; i < args->buffer_count; i++) {
3823                         object_list[i]->pending_read_domains = 0;
3824                         object_list[i]->pending_write_domain = 0;
3825                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3826                                                                file_priv,
3827                                                                &exec_list[i],
3828                                                                &relocs[reloc_index]);
3829                         if (ret)
3830                                 break;
3831                         pinned = i + 1;
3832                         reloc_index += exec_list[i].relocation_count;
3833                 }
3834                 /* success */
3835                 if (ret == 0)
3836                         break;
3837
3838                 /* error other than GTT full, or we've already tried again */
3839                 if (ret != -ENOSPC || pin_tries >= 1) {
3840                         if (ret != -ERESTARTSYS) {
3841                                 unsigned long long total_size = 0;
3842                                 for (i = 0; i < args->buffer_count; i++)
3843                                         total_size += object_list[i]->size;
3844                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3845                                           pinned+1, args->buffer_count,
3846                                           total_size, ret);
3847                                 DRM_ERROR("%d objects [%d pinned], "
3848                                           "%d object bytes [%d pinned], "
3849                                           "%d/%d gtt bytes\n",
3850                                           atomic_read(&dev->object_count),
3851                                           atomic_read(&dev->pin_count),
3852                                           atomic_read(&dev->object_memory),
3853                                           atomic_read(&dev->pin_memory),
3854                                           atomic_read(&dev->gtt_memory),
3855                                           dev->gtt_total);
3856                         }
3857                         goto err;
3858                 }
3859
3860                 /* unpin all of our buffers */
3861                 for (i = 0; i < pinned; i++)
3862                         i915_gem_object_unpin(object_list[i]);
3863                 pinned = 0;
3864
3865                 /* evict everyone we can from the aperture */
3866                 ret = i915_gem_evict_everything(dev);
3867                 if (ret && ret != -ENOSPC)
3868                         goto err;
3869         }
3870
3871         /* Set the pending read domains for the batch buffer to COMMAND */
3872         batch_obj = object_list[args->buffer_count-1];
3873         if (batch_obj->pending_write_domain) {
3874                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3875                 ret = -EINVAL;
3876                 goto err;
3877         }
3878         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3879
3880         /* Sanity check the batch buffer, prior to moving objects */
3881         exec_offset = exec_list[args->buffer_count - 1].offset;
3882         ret = i915_gem_check_execbuffer (args, exec_offset);
3883         if (ret != 0) {
3884                 DRM_ERROR("execbuf with invalid offset/length\n");
3885                 goto err;
3886         }
3887
3888         i915_verify_inactive(dev, __FILE__, __LINE__);
3889
3890         /* Zero the global flush/invalidate flags. These
3891          * will be modified as new domains are computed
3892          * for each object
3893          */
3894         dev->invalidate_domains = 0;
3895         dev->flush_domains = 0;
3896
3897         for (i = 0; i < args->buffer_count; i++) {
3898                 struct drm_gem_object *obj = object_list[i];
3899
3900                 /* Compute new gpu domains and update invalidate/flush */
3901                 i915_gem_object_set_to_gpu_domain(obj);
3902         }
3903
3904         i915_verify_inactive(dev, __FILE__, __LINE__);
3905
3906         if (dev->invalidate_domains | dev->flush_domains) {
3907 #if WATCH_EXEC
3908                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3909                           __func__,
3910                          dev->invalidate_domains,
3911                          dev->flush_domains);
3912 #endif
3913                 i915_gem_flush(dev,
3914                                dev->invalidate_domains,
3915                                dev->flush_domains);
3916                 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3917                         (void)i915_add_request(dev, file_priv,
3918                                                dev->flush_domains);
3919         }
3920
3921         for (i = 0; i < args->buffer_count; i++) {
3922                 struct drm_gem_object *obj = object_list[i];
3923                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3924                 uint32_t old_write_domain = obj->write_domain;
3925
3926                 obj->write_domain = obj->pending_write_domain;
3927                 if (obj->write_domain)
3928                         list_move_tail(&obj_priv->gpu_write_list,
3929                                        &dev_priv->mm.gpu_write_list);
3930                 else
3931                         list_del_init(&obj_priv->gpu_write_list);
3932
3933                 trace_i915_gem_object_change_domain(obj,
3934                                                     obj->read_domains,
3935                                                     old_write_domain);
3936         }
3937
3938         i915_verify_inactive(dev, __FILE__, __LINE__);
3939
3940 #if WATCH_COHERENCY
3941         for (i = 0; i < args->buffer_count; i++) {
3942                 i915_gem_object_check_coherency(object_list[i],
3943                                                 exec_list[i].handle);
3944         }
3945 #endif
3946
3947 #if WATCH_EXEC
3948         i915_gem_dump_object(batch_obj,
3949                               args->batch_len,
3950                               __func__,
3951                               ~0);
3952 #endif
3953
3954         /* Exec the batchbuffer */
3955         ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3956         if (ret) {
3957                 DRM_ERROR("dispatch failed %d\n", ret);
3958                 goto err;
3959         }
3960
3961         /*
3962          * Ensure that the commands in the batch buffer are
3963          * finished before the interrupt fires
3964          */
3965         flush_domains = i915_retire_commands(dev);
3966
3967         i915_verify_inactive(dev, __FILE__, __LINE__);
3968
3969         /*
3970          * Get a seqno representing the execution of the current buffer,
3971          * which we can wait on.  We would like to mitigate these interrupts,
3972          * likely by only creating seqnos occasionally (so that we have
3973          * *some* interrupts representing completion of buffers that we can
3974          * wait on when trying to clear up gtt space).
3975          */
3976         seqno = i915_add_request(dev, file_priv, flush_domains);
3977         BUG_ON(seqno == 0);
3978         for (i = 0; i < args->buffer_count; i++) {
3979                 struct drm_gem_object *obj = object_list[i];
3980
3981                 i915_gem_object_move_to_active(obj, seqno);
3982 #if WATCH_LRU
3983                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3984 #endif
3985         }
3986 #if WATCH_LRU
3987         i915_dump_lru(dev, __func__);
3988 #endif
3989
3990         i915_verify_inactive(dev, __FILE__, __LINE__);
3991
3992 err:
3993         for (i = 0; i < pinned; i++)
3994                 i915_gem_object_unpin(object_list[i]);
3995
3996         for (i = 0; i < args->buffer_count; i++) {
3997                 if (object_list[i]) {
3998                         obj_priv = object_list[i]->driver_private;
3999                         obj_priv->in_execbuffer = false;
4000                 }
4001                 drm_gem_object_unreference(object_list[i]);
4002         }
4003
4004         mutex_unlock(&dev->struct_mutex);
4005
4006 pre_mutex_err:
4007         /* Copy the updated relocations out regardless of current error
4008          * state.  Failure to update the relocs would mean that the next
4009          * time userland calls execbuf, it would do so with presumed offset
4010          * state that didn't match the actual object state.
4011          */
4012         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4013                                            relocs);
4014         if (ret2 != 0) {
4015                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4016
4017                 if (ret == 0)
4018                         ret = ret2;
4019         }
4020
4021         drm_free_large(object_list);
4022         kfree(cliprects);
4023
4024         return ret;
4025 }
4026
4027 /*
4028  * Legacy execbuffer just creates an exec2 list from the original exec object
4029  * list array and passes it to the real function.
4030  */
4031 int
4032 i915_gem_execbuffer(struct drm_device *dev, void *data,
4033                     struct drm_file *file_priv)
4034 {
4035         struct drm_i915_gem_execbuffer *args = data;
4036         struct drm_i915_gem_execbuffer2 exec2;
4037         struct drm_i915_gem_exec_object *exec_list = NULL;
4038         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4039         int ret, i;
4040
4041 #if WATCH_EXEC
4042         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4043                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4044 #endif
4045
4046         if (args->buffer_count < 1) {
4047                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4048                 return -EINVAL;
4049         }
4050
4051         /* Copy in the exec list from userland */
4052         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4053         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4054         if (exec_list == NULL || exec2_list == NULL) {
4055                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4056                           args->buffer_count);
4057                 drm_free_large(exec_list);
4058                 drm_free_large(exec2_list);
4059                 return -ENOMEM;
4060         }
4061         ret = copy_from_user(exec_list,
4062                              (struct drm_i915_relocation_entry __user *)
4063                              (uintptr_t) args->buffers_ptr,
4064                              sizeof(*exec_list) * args->buffer_count);
4065         if (ret != 0) {
4066                 DRM_ERROR("copy %d exec entries failed %d\n",
4067                           args->buffer_count, ret);
4068                 drm_free_large(exec_list);
4069                 drm_free_large(exec2_list);
4070                 return -EFAULT;
4071         }
4072
4073         for (i = 0; i < args->buffer_count; i++) {
4074                 exec2_list[i].handle = exec_list[i].handle;
4075                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4076                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4077                 exec2_list[i].alignment = exec_list[i].alignment;
4078                 exec2_list[i].offset = exec_list[i].offset;
4079                 if (!IS_I965G(dev))
4080                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4081                 else
4082                         exec2_list[i].flags = 0;
4083         }
4084
4085         exec2.buffers_ptr = args->buffers_ptr;
4086         exec2.buffer_count = args->buffer_count;
4087         exec2.batch_start_offset = args->batch_start_offset;
4088         exec2.batch_len = args->batch_len;
4089         exec2.DR1 = args->DR1;
4090         exec2.DR4 = args->DR4;
4091         exec2.num_cliprects = args->num_cliprects;
4092         exec2.cliprects_ptr = args->cliprects_ptr;
4093         exec2.flags = 0;
4094
4095         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4096         if (!ret) {
4097                 /* Copy the new buffer offsets back to the user's exec list. */
4098                 for (i = 0; i < args->buffer_count; i++)
4099                         exec_list[i].offset = exec2_list[i].offset;
4100                 /* ... and back out to userspace */
4101                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4102                                    (uintptr_t) args->buffers_ptr,
4103                                    exec_list,
4104                                    sizeof(*exec_list) * args->buffer_count);
4105                 if (ret) {
4106                         ret = -EFAULT;
4107                         DRM_ERROR("failed to copy %d exec entries "
4108                                   "back to user (%d)\n",
4109                                   args->buffer_count, ret);
4110                 }
4111         }
4112
4113         drm_free_large(exec_list);
4114         drm_free_large(exec2_list);
4115         return ret;
4116 }
4117
4118 int
4119 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4120                      struct drm_file *file_priv)
4121 {
4122         struct drm_i915_gem_execbuffer2 *args = data;
4123         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4124         int ret;
4125
4126 #if WATCH_EXEC
4127         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4128                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4129 #endif
4130
4131         if (args->buffer_count < 1) {
4132                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4133                 return -EINVAL;
4134         }
4135
4136         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4137         if (exec2_list == NULL) {
4138                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4139                           args->buffer_count);
4140                 return -ENOMEM;
4141         }
4142         ret = copy_from_user(exec2_list,
4143                              (struct drm_i915_relocation_entry __user *)
4144                              (uintptr_t) args->buffers_ptr,
4145                              sizeof(*exec2_list) * args->buffer_count);
4146         if (ret != 0) {
4147                 DRM_ERROR("copy %d exec entries failed %d\n",
4148                           args->buffer_count, ret);
4149                 drm_free_large(exec2_list);
4150                 return -EFAULT;
4151         }
4152
4153         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4154         if (!ret) {
4155                 /* Copy the new buffer offsets back to the user's exec list. */
4156                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4157                                    (uintptr_t) args->buffers_ptr,
4158                                    exec2_list,
4159                                    sizeof(*exec2_list) * args->buffer_count);
4160                 if (ret) {
4161                         ret = -EFAULT;
4162                         DRM_ERROR("failed to copy %d exec entries "
4163                                   "back to user (%d)\n",
4164                                   args->buffer_count, ret);
4165                 }
4166         }
4167
4168         drm_free_large(exec2_list);
4169         return ret;
4170 }
4171
4172 int
4173 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4174 {
4175         struct drm_device *dev = obj->dev;
4176         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4177         int ret;
4178
4179         i915_verify_inactive(dev, __FILE__, __LINE__);
4180         if (obj_priv->gtt_space == NULL) {
4181                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4182                 if (ret)
4183                         return ret;
4184         }
4185
4186         obj_priv->pin_count++;
4187
4188         /* If the object is not active and not pending a flush,
4189          * remove it from the inactive list
4190          */
4191         if (obj_priv->pin_count == 1) {
4192                 atomic_inc(&dev->pin_count);
4193                 atomic_add(obj->size, &dev->pin_memory);
4194                 if (!obj_priv->active &&
4195                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4196                     !list_empty(&obj_priv->list))
4197                         list_del_init(&obj_priv->list);
4198         }
4199         i915_verify_inactive(dev, __FILE__, __LINE__);
4200
4201         return 0;
4202 }
4203
4204 void
4205 i915_gem_object_unpin(struct drm_gem_object *obj)
4206 {
4207         struct drm_device *dev = obj->dev;
4208         drm_i915_private_t *dev_priv = dev->dev_private;
4209         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4210
4211         i915_verify_inactive(dev, __FILE__, __LINE__);
4212         obj_priv->pin_count--;
4213         BUG_ON(obj_priv->pin_count < 0);
4214         BUG_ON(obj_priv->gtt_space == NULL);
4215
4216         /* If the object is no longer pinned, and is
4217          * neither active nor being flushed, then stick it on
4218          * the inactive list
4219          */
4220         if (obj_priv->pin_count == 0) {
4221                 if (!obj_priv->active &&
4222                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4223                         list_move_tail(&obj_priv->list,
4224                                        &dev_priv->mm.inactive_list);
4225                 atomic_dec(&dev->pin_count);
4226                 atomic_sub(obj->size, &dev->pin_memory);
4227         }
4228         i915_verify_inactive(dev, __FILE__, __LINE__);
4229 }
4230
4231 int
4232 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4233                    struct drm_file *file_priv)
4234 {
4235         struct drm_i915_gem_pin *args = data;
4236         struct drm_gem_object *obj;
4237         struct drm_i915_gem_object *obj_priv;
4238         int ret;
4239
4240         mutex_lock(&dev->struct_mutex);
4241
4242         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4243         if (obj == NULL) {
4244                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4245                           args->handle);
4246                 mutex_unlock(&dev->struct_mutex);
4247                 return -EBADF;
4248         }
4249         obj_priv = obj->driver_private;
4250
4251         if (obj_priv->madv != I915_MADV_WILLNEED) {
4252                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4253                 drm_gem_object_unreference(obj);
4254                 mutex_unlock(&dev->struct_mutex);
4255                 return -EINVAL;
4256         }
4257
4258         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4259                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4260                           args->handle);
4261                 drm_gem_object_unreference(obj);
4262                 mutex_unlock(&dev->struct_mutex);
4263                 return -EINVAL;
4264         }
4265
4266         obj_priv->user_pin_count++;
4267         obj_priv->pin_filp = file_priv;
4268         if (obj_priv->user_pin_count == 1) {
4269                 ret = i915_gem_object_pin(obj, args->alignment);
4270                 if (ret != 0) {
4271                         drm_gem_object_unreference(obj);
4272                         mutex_unlock(&dev->struct_mutex);
4273                         return ret;
4274                 }
4275         }
4276
4277         /* XXX - flush the CPU caches for pinned objects
4278          * as the X server doesn't manage domains yet
4279          */
4280         i915_gem_object_flush_cpu_write_domain(obj);
4281         args->offset = obj_priv->gtt_offset;
4282         drm_gem_object_unreference(obj);
4283         mutex_unlock(&dev->struct_mutex);
4284
4285         return 0;
4286 }
4287
4288 int
4289 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4290                      struct drm_file *file_priv)
4291 {
4292         struct drm_i915_gem_pin *args = data;
4293         struct drm_gem_object *obj;
4294         struct drm_i915_gem_object *obj_priv;
4295
4296         mutex_lock(&dev->struct_mutex);
4297
4298         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4299         if (obj == NULL) {
4300                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4301                           args->handle);
4302                 mutex_unlock(&dev->struct_mutex);
4303                 return -EBADF;
4304         }
4305
4306         obj_priv = obj->driver_private;
4307         if (obj_priv->pin_filp != file_priv) {
4308                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4309                           args->handle);
4310                 drm_gem_object_unreference(obj);
4311                 mutex_unlock(&dev->struct_mutex);
4312                 return -EINVAL;
4313         }
4314         obj_priv->user_pin_count--;
4315         if (obj_priv->user_pin_count == 0) {
4316                 obj_priv->pin_filp = NULL;
4317                 i915_gem_object_unpin(obj);
4318         }
4319
4320         drm_gem_object_unreference(obj);
4321         mutex_unlock(&dev->struct_mutex);
4322         return 0;
4323 }
4324
4325 int
4326 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4327                     struct drm_file *file_priv)
4328 {
4329         struct drm_i915_gem_busy *args = data;
4330         struct drm_gem_object *obj;
4331         struct drm_i915_gem_object *obj_priv;
4332
4333         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4334         if (obj == NULL) {
4335                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4336                           args->handle);
4337                 return -EBADF;
4338         }
4339
4340         mutex_lock(&dev->struct_mutex);
4341         /* Update the active list for the hardware's current position.
4342          * Otherwise this only updates on a delayed timer or when irqs are
4343          * actually unmasked, and our working set ends up being larger than
4344          * required.
4345          */
4346         i915_gem_retire_requests(dev);
4347
4348         obj_priv = obj->driver_private;
4349         /* Don't count being on the flushing list against the object being
4350          * done.  Otherwise, a buffer left on the flushing list but not getting
4351          * flushed (because nobody's flushing that domain) won't ever return
4352          * unbusy and get reused by libdrm's bo cache.  The other expected
4353          * consumer of this interface, OpenGL's occlusion queries, also specs
4354          * that the objects get unbusy "eventually" without any interference.
4355          */
4356         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4357
4358         drm_gem_object_unreference(obj);
4359         mutex_unlock(&dev->struct_mutex);
4360         return 0;
4361 }
4362
4363 int
4364 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4365                         struct drm_file *file_priv)
4366 {
4367     return i915_gem_ring_throttle(dev, file_priv);
4368 }
4369
4370 int
4371 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4372                        struct drm_file *file_priv)
4373 {
4374         struct drm_i915_gem_madvise *args = data;
4375         struct drm_gem_object *obj;
4376         struct drm_i915_gem_object *obj_priv;
4377
4378         switch (args->madv) {
4379         case I915_MADV_DONTNEED:
4380         case I915_MADV_WILLNEED:
4381             break;
4382         default:
4383             return -EINVAL;
4384         }
4385
4386         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4387         if (obj == NULL) {
4388                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4389                           args->handle);
4390                 return -EBADF;
4391         }
4392
4393         mutex_lock(&dev->struct_mutex);
4394         obj_priv = obj->driver_private;
4395
4396         if (obj_priv->pin_count) {
4397                 drm_gem_object_unreference(obj);
4398                 mutex_unlock(&dev->struct_mutex);
4399
4400                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4401                 return -EINVAL;
4402         }
4403
4404         if (obj_priv->madv != __I915_MADV_PURGED)
4405                 obj_priv->madv = args->madv;
4406
4407         /* if the object is no longer bound, discard its backing storage */
4408         if (i915_gem_object_is_purgeable(obj_priv) &&
4409             obj_priv->gtt_space == NULL)
4410                 i915_gem_object_truncate(obj);
4411
4412         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4413
4414         drm_gem_object_unreference(obj);
4415         mutex_unlock(&dev->struct_mutex);
4416
4417         return 0;
4418 }
4419
4420 int i915_gem_init_object(struct drm_gem_object *obj)
4421 {
4422         struct drm_i915_gem_object *obj_priv;
4423
4424         obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4425         if (obj_priv == NULL)
4426                 return -ENOMEM;
4427
4428         /*
4429          * We've just allocated pages from the kernel,
4430          * so they've just been written by the CPU with
4431          * zeros. They'll need to be clflushed before we
4432          * use them with the GPU.
4433          */
4434         obj->write_domain = I915_GEM_DOMAIN_CPU;
4435         obj->read_domains = I915_GEM_DOMAIN_CPU;
4436
4437         obj_priv->agp_type = AGP_USER_MEMORY;
4438
4439         obj->driver_private = obj_priv;
4440         obj_priv->obj = obj;
4441         obj_priv->fence_reg = I915_FENCE_REG_NONE;
4442         INIT_LIST_HEAD(&obj_priv->list);
4443         INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4444         INIT_LIST_HEAD(&obj_priv->fence_list);
4445         obj_priv->madv = I915_MADV_WILLNEED;
4446
4447         trace_i915_gem_object_create(obj);
4448
4449         return 0;
4450 }
4451
4452 void i915_gem_free_object(struct drm_gem_object *obj)
4453 {
4454         struct drm_device *dev = obj->dev;
4455         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4456
4457         trace_i915_gem_object_destroy(obj);
4458
4459         while (obj_priv->pin_count > 0)
4460                 i915_gem_object_unpin(obj);
4461
4462         if (obj_priv->phys_obj)
4463                 i915_gem_detach_phys_object(dev, obj);
4464
4465         i915_gem_object_unbind(obj);
4466
4467         if (obj_priv->mmap_offset)
4468                 i915_gem_free_mmap_offset(obj);
4469
4470         kfree(obj_priv->page_cpu_valid);
4471         kfree(obj_priv->bit_17);
4472         kfree(obj->driver_private);
4473 }
4474
4475 /** Unbinds all inactive objects. */
4476 static int
4477 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4478 {
4479         drm_i915_private_t *dev_priv = dev->dev_private;
4480
4481         while (!list_empty(&dev_priv->mm.inactive_list)) {
4482                 struct drm_gem_object *obj;
4483                 int ret;
4484
4485                 obj = list_first_entry(&dev_priv->mm.inactive_list,
4486                                        struct drm_i915_gem_object,
4487                                        list)->obj;
4488
4489                 ret = i915_gem_object_unbind(obj);
4490                 if (ret != 0) {
4491                         DRM_ERROR("Error unbinding object: %d\n", ret);
4492                         return ret;
4493                 }
4494         }
4495
4496         return 0;
4497 }
4498
4499 int
4500 i915_gem_idle(struct drm_device *dev)
4501 {
4502         drm_i915_private_t *dev_priv = dev->dev_private;
4503         int ret;
4504
4505         mutex_lock(&dev->struct_mutex);
4506
4507         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4508                 mutex_unlock(&dev->struct_mutex);
4509                 return 0;
4510         }
4511
4512         ret = i915_gpu_idle(dev);
4513         if (ret) {
4514                 mutex_unlock(&dev->struct_mutex);
4515                 return ret;
4516         }
4517
4518         /* Under UMS, be paranoid and evict. */
4519         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4520                 ret = i915_gem_evict_from_inactive_list(dev);
4521                 if (ret) {
4522                         mutex_unlock(&dev->struct_mutex);
4523                         return ret;
4524                 }
4525         }
4526
4527         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4528          * We need to replace this with a semaphore, or something.
4529          * And not confound mm.suspended!
4530          */
4531         dev_priv->mm.suspended = 1;
4532         del_timer(&dev_priv->hangcheck_timer);
4533
4534         i915_kernel_lost_context(dev);
4535         i915_gem_cleanup_ringbuffer(dev);
4536
4537         mutex_unlock(&dev->struct_mutex);
4538
4539         /* Cancel the retire work handler, which should be idle now. */
4540         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4541
4542         return 0;
4543 }
4544
4545 static int
4546 i915_gem_init_hws(struct drm_device *dev)
4547 {
4548         drm_i915_private_t *dev_priv = dev->dev_private;
4549         struct drm_gem_object *obj;
4550         struct drm_i915_gem_object *obj_priv;
4551         int ret;
4552
4553         /* If we need a physical address for the status page, it's already
4554          * initialized at driver load time.
4555          */
4556         if (!I915_NEED_GFX_HWS(dev))
4557                 return 0;
4558
4559         obj = drm_gem_object_alloc(dev, 4096);
4560         if (obj == NULL) {
4561                 DRM_ERROR("Failed to allocate status page\n");
4562                 return -ENOMEM;
4563         }
4564         obj_priv = obj->driver_private;
4565         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4566
4567         ret = i915_gem_object_pin(obj, 4096);
4568         if (ret != 0) {
4569                 drm_gem_object_unreference(obj);
4570                 return ret;
4571         }
4572
4573         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4574
4575         dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4576         if (dev_priv->hw_status_page == NULL) {
4577                 DRM_ERROR("Failed to map status page.\n");
4578                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4579                 i915_gem_object_unpin(obj);
4580                 drm_gem_object_unreference(obj);
4581                 return -EINVAL;
4582         }
4583         dev_priv->hws_obj = obj;
4584         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4585         if (IS_GEN6(dev)) {
4586                 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4587                 I915_READ(HWS_PGA_GEN6); /* posting read */
4588         } else {
4589                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4590                 I915_READ(HWS_PGA); /* posting read */
4591         }
4592         DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4593
4594         return 0;
4595 }
4596
4597 static void
4598 i915_gem_cleanup_hws(struct drm_device *dev)
4599 {
4600         drm_i915_private_t *dev_priv = dev->dev_private;
4601         struct drm_gem_object *obj;
4602         struct drm_i915_gem_object *obj_priv;
4603
4604         if (dev_priv->hws_obj == NULL)
4605                 return;
4606
4607         obj = dev_priv->hws_obj;
4608         obj_priv = obj->driver_private;
4609
4610         kunmap(obj_priv->pages[0]);
4611         i915_gem_object_unpin(obj);
4612         drm_gem_object_unreference(obj);
4613         dev_priv->hws_obj = NULL;
4614
4615         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4616         dev_priv->hw_status_page = NULL;
4617
4618         /* Write high address into HWS_PGA when disabling. */
4619         I915_WRITE(HWS_PGA, 0x1ffff000);
4620 }
4621
4622 int
4623 i915_gem_init_ringbuffer(struct drm_device *dev)
4624 {
4625         drm_i915_private_t *dev_priv = dev->dev_private;
4626         struct drm_gem_object *obj;
4627         struct drm_i915_gem_object *obj_priv;
4628         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4629         int ret;
4630         u32 head;
4631
4632         ret = i915_gem_init_hws(dev);
4633         if (ret != 0)
4634                 return ret;
4635
4636         obj = drm_gem_object_alloc(dev, 128 * 1024);
4637         if (obj == NULL) {
4638                 DRM_ERROR("Failed to allocate ringbuffer\n");
4639                 i915_gem_cleanup_hws(dev);
4640                 return -ENOMEM;
4641         }
4642         obj_priv = obj->driver_private;
4643
4644         ret = i915_gem_object_pin(obj, 4096);
4645         if (ret != 0) {
4646                 drm_gem_object_unreference(obj);
4647                 i915_gem_cleanup_hws(dev);
4648                 return ret;
4649         }
4650
4651         /* Set up the kernel mapping for the ring. */
4652         ring->Size = obj->size;
4653
4654         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4655         ring->map.size = obj->size;
4656         ring->map.type = 0;
4657         ring->map.flags = 0;
4658         ring->map.mtrr = 0;
4659
4660         drm_core_ioremap_wc(&ring->map, dev);
4661         if (ring->map.handle == NULL) {
4662                 DRM_ERROR("Failed to map ringbuffer.\n");
4663                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4664                 i915_gem_object_unpin(obj);
4665                 drm_gem_object_unreference(obj);
4666                 i915_gem_cleanup_hws(dev);
4667                 return -EINVAL;
4668         }
4669         ring->ring_obj = obj;
4670         ring->virtual_start = ring->map.handle;
4671
4672         /* Stop the ring if it's running. */
4673         I915_WRITE(PRB0_CTL, 0);
4674         I915_WRITE(PRB0_TAIL, 0);
4675         I915_WRITE(PRB0_HEAD, 0);
4676
4677         /* Initialize the ring. */
4678         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4679         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4680
4681         /* G45 ring initialization fails to reset head to zero */
4682         if (head != 0) {
4683                 DRM_ERROR("Ring head not reset to zero "
4684                           "ctl %08x head %08x tail %08x start %08x\n",
4685                           I915_READ(PRB0_CTL),
4686                           I915_READ(PRB0_HEAD),
4687                           I915_READ(PRB0_TAIL),
4688                           I915_READ(PRB0_START));
4689                 I915_WRITE(PRB0_HEAD, 0);
4690
4691                 DRM_ERROR("Ring head forced to zero "
4692                           "ctl %08x head %08x tail %08x start %08x\n",
4693                           I915_READ(PRB0_CTL),
4694                           I915_READ(PRB0_HEAD),
4695                           I915_READ(PRB0_TAIL),
4696                           I915_READ(PRB0_START));
4697         }
4698
4699         I915_WRITE(PRB0_CTL,
4700                    ((obj->size - 4096) & RING_NR_PAGES) |
4701                    RING_NO_REPORT |
4702                    RING_VALID);
4703
4704         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4705
4706         /* If the head is still not zero, the ring is dead */
4707         if (head != 0) {
4708                 DRM_ERROR("Ring initialization failed "
4709                           "ctl %08x head %08x tail %08x start %08x\n",
4710                           I915_READ(PRB0_CTL),
4711                           I915_READ(PRB0_HEAD),
4712                           I915_READ(PRB0_TAIL),
4713                           I915_READ(PRB0_START));
4714                 return -EIO;
4715         }
4716
4717         /* Update our cache of the ring state */
4718         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4719                 i915_kernel_lost_context(dev);
4720         else {
4721                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4722                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4723                 ring->space = ring->head - (ring->tail + 8);
4724                 if (ring->space < 0)
4725                         ring->space += ring->Size;
4726         }
4727
4728         return 0;
4729 }
4730
4731 void
4732 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4733 {
4734         drm_i915_private_t *dev_priv = dev->dev_private;
4735
4736         if (dev_priv->ring.ring_obj == NULL)
4737                 return;
4738
4739         drm_core_ioremapfree(&dev_priv->ring.map, dev);
4740
4741         i915_gem_object_unpin(dev_priv->ring.ring_obj);
4742         drm_gem_object_unreference(dev_priv->ring.ring_obj);
4743         dev_priv->ring.ring_obj = NULL;
4744         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4745
4746         i915_gem_cleanup_hws(dev);
4747 }
4748
4749 int
4750 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4751                        struct drm_file *file_priv)
4752 {
4753         drm_i915_private_t *dev_priv = dev->dev_private;
4754         int ret;
4755
4756         if (drm_core_check_feature(dev, DRIVER_MODESET))
4757                 return 0;
4758
4759         if (atomic_read(&dev_priv->mm.wedged)) {
4760                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4761                 atomic_set(&dev_priv->mm.wedged, 0);
4762         }
4763
4764         mutex_lock(&dev->struct_mutex);
4765         dev_priv->mm.suspended = 0;
4766
4767         ret = i915_gem_init_ringbuffer(dev);
4768         if (ret != 0) {
4769                 mutex_unlock(&dev->struct_mutex);
4770                 return ret;
4771         }
4772
4773         spin_lock(&dev_priv->mm.active_list_lock);
4774         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4775         spin_unlock(&dev_priv->mm.active_list_lock);
4776
4777         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4778         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4779         BUG_ON(!list_empty(&dev_priv->mm.request_list));
4780         mutex_unlock(&dev->struct_mutex);
4781
4782         drm_irq_install(dev);
4783
4784         return 0;
4785 }
4786
4787 int
4788 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4789                        struct drm_file *file_priv)
4790 {
4791         if (drm_core_check_feature(dev, DRIVER_MODESET))
4792                 return 0;
4793
4794         drm_irq_uninstall(dev);
4795         return i915_gem_idle(dev);
4796 }
4797
4798 void
4799 i915_gem_lastclose(struct drm_device *dev)
4800 {
4801         int ret;
4802
4803         if (drm_core_check_feature(dev, DRIVER_MODESET))
4804                 return;
4805
4806         ret = i915_gem_idle(dev);
4807         if (ret)
4808                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4809 }
4810
4811 void
4812 i915_gem_load(struct drm_device *dev)
4813 {
4814         int i;
4815         drm_i915_private_t *dev_priv = dev->dev_private;
4816
4817         spin_lock_init(&dev_priv->mm.active_list_lock);
4818         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4819         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4820         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4821         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4822         INIT_LIST_HEAD(&dev_priv->mm.request_list);
4823         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4824         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4825                           i915_gem_retire_work_handler);
4826         dev_priv->mm.next_gem_seqno = 1;
4827
4828         spin_lock(&shrink_list_lock);
4829         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4830         spin_unlock(&shrink_list_lock);
4831
4832         /* Old X drivers will take 0-2 for front, back, depth buffers */
4833         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4834                 dev_priv->fence_reg_start = 3;
4835
4836         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4837                 dev_priv->num_fence_regs = 16;
4838         else
4839                 dev_priv->num_fence_regs = 8;
4840
4841         /* Initialize fence registers to zero */
4842         if (IS_I965G(dev)) {
4843                 for (i = 0; i < 16; i++)
4844                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4845         } else {
4846                 for (i = 0; i < 8; i++)
4847                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4848                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4849                         for (i = 0; i < 8; i++)
4850                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4851         }
4852         i915_gem_detect_bit_6_swizzle(dev);
4853         init_waitqueue_head(&dev_priv->pending_flip_queue);
4854 }
4855
4856 /*
4857  * Create a physically contiguous memory object for this object
4858  * e.g. for cursor + overlay regs
4859  */
4860 int i915_gem_init_phys_object(struct drm_device *dev,
4861                               int id, int size)
4862 {
4863         drm_i915_private_t *dev_priv = dev->dev_private;
4864         struct drm_i915_gem_phys_object *phys_obj;
4865         int ret;
4866
4867         if (dev_priv->mm.phys_objs[id - 1] || !size)
4868                 return 0;
4869
4870         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4871         if (!phys_obj)
4872                 return -ENOMEM;
4873
4874         phys_obj->id = id;
4875
4876         phys_obj->handle = drm_pci_alloc(dev, size, 0);
4877         if (!phys_obj->handle) {
4878                 ret = -ENOMEM;
4879                 goto kfree_obj;
4880         }
4881 #ifdef CONFIG_X86
4882         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4883 #endif
4884
4885         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4886
4887         return 0;
4888 kfree_obj:
4889         kfree(phys_obj);
4890         return ret;
4891 }
4892
4893 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4894 {
4895         drm_i915_private_t *dev_priv = dev->dev_private;
4896         struct drm_i915_gem_phys_object *phys_obj;
4897
4898         if (!dev_priv->mm.phys_objs[id - 1])
4899                 return;
4900
4901         phys_obj = dev_priv->mm.phys_objs[id - 1];
4902         if (phys_obj->cur_obj) {
4903                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4904         }
4905
4906 #ifdef CONFIG_X86
4907         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4908 #endif
4909         drm_pci_free(dev, phys_obj->handle);
4910         kfree(phys_obj);
4911         dev_priv->mm.phys_objs[id - 1] = NULL;
4912 }
4913
4914 void i915_gem_free_all_phys_object(struct drm_device *dev)
4915 {
4916         int i;
4917
4918         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4919                 i915_gem_free_phys_object(dev, i);
4920 }
4921
4922 void i915_gem_detach_phys_object(struct drm_device *dev,
4923                                  struct drm_gem_object *obj)
4924 {
4925         struct drm_i915_gem_object *obj_priv;
4926         int i;
4927         int ret;
4928         int page_count;
4929
4930         obj_priv = obj->driver_private;
4931         if (!obj_priv->phys_obj)
4932                 return;
4933
4934         ret = i915_gem_object_get_pages(obj, 0);
4935         if (ret)
4936                 goto out;
4937
4938         page_count = obj->size / PAGE_SIZE;
4939
4940         for (i = 0; i < page_count; i++) {
4941                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4942                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4943
4944                 memcpy(dst, src, PAGE_SIZE);
4945                 kunmap_atomic(dst, KM_USER0);
4946         }
4947         drm_clflush_pages(obj_priv->pages, page_count);
4948         drm_agp_chipset_flush(dev);
4949
4950         i915_gem_object_put_pages(obj);
4951 out:
4952         obj_priv->phys_obj->cur_obj = NULL;
4953         obj_priv->phys_obj = NULL;
4954 }
4955
4956 int
4957 i915_gem_attach_phys_object(struct drm_device *dev,
4958                             struct drm_gem_object *obj, int id)
4959 {
4960         drm_i915_private_t *dev_priv = dev->dev_private;
4961         struct drm_i915_gem_object *obj_priv;
4962         int ret = 0;
4963         int page_count;
4964         int i;
4965
4966         if (id > I915_MAX_PHYS_OBJECT)
4967                 return -EINVAL;
4968
4969         obj_priv = obj->driver_private;
4970
4971         if (obj_priv->phys_obj) {
4972                 if (obj_priv->phys_obj->id == id)
4973                         return 0;
4974                 i915_gem_detach_phys_object(dev, obj);
4975         }
4976
4977
4978         /* create a new object */
4979         if (!dev_priv->mm.phys_objs[id - 1]) {
4980                 ret = i915_gem_init_phys_object(dev, id,
4981                                                 obj->size);
4982                 if (ret) {
4983                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4984                         goto out;
4985                 }
4986         }
4987
4988         /* bind to the object */
4989         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4990         obj_priv->phys_obj->cur_obj = obj;
4991
4992         ret = i915_gem_object_get_pages(obj, 0);
4993         if (ret) {
4994                 DRM_ERROR("failed to get page list\n");
4995                 goto out;
4996         }
4997
4998         page_count = obj->size / PAGE_SIZE;
4999
5000         for (i = 0; i < page_count; i++) {
5001                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5002                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5003
5004                 memcpy(dst, src, PAGE_SIZE);
5005                 kunmap_atomic(src, KM_USER0);
5006         }
5007
5008         i915_gem_object_put_pages(obj);
5009
5010         return 0;
5011 out:
5012         return ret;
5013 }
5014
5015 static int
5016 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5017                      struct drm_i915_gem_pwrite *args,
5018                      struct drm_file *file_priv)
5019 {
5020         struct drm_i915_gem_object *obj_priv = obj->driver_private;
5021         void *obj_addr;
5022         int ret;
5023         char __user *user_data;
5024
5025         user_data = (char __user *) (uintptr_t) args->data_ptr;
5026         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5027
5028         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5029         ret = copy_from_user(obj_addr, user_data, args->size);
5030         if (ret)
5031                 return -EFAULT;
5032
5033         drm_agp_chipset_flush(dev);
5034         return 0;
5035 }
5036
5037 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5038 {
5039         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5040
5041         /* Clean up our request list when the client is going away, so that
5042          * later retire_requests won't dereference our soon-to-be-gone
5043          * file_priv.
5044          */
5045         mutex_lock(&dev->struct_mutex);
5046         while (!list_empty(&i915_file_priv->mm.request_list))
5047                 list_del_init(i915_file_priv->mm.request_list.next);
5048         mutex_unlock(&dev->struct_mutex);
5049 }
5050
5051 static int
5052 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5053 {
5054         drm_i915_private_t *dev_priv, *next_dev;
5055         struct drm_i915_gem_object *obj_priv, *next_obj;
5056         int cnt = 0;
5057         int would_deadlock = 1;
5058
5059         /* "fast-path" to count number of available objects */
5060         if (nr_to_scan == 0) {
5061                 spin_lock(&shrink_list_lock);
5062                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5063                         struct drm_device *dev = dev_priv->dev;
5064
5065                         if (mutex_trylock(&dev->struct_mutex)) {
5066                                 list_for_each_entry(obj_priv,
5067                                                     &dev_priv->mm.inactive_list,
5068                                                     list)
5069                                         cnt++;
5070                                 mutex_unlock(&dev->struct_mutex);
5071                         }
5072                 }
5073                 spin_unlock(&shrink_list_lock);
5074
5075                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5076         }
5077
5078         spin_lock(&shrink_list_lock);
5079
5080         /* first scan for clean buffers */
5081         list_for_each_entry_safe(dev_priv, next_dev,
5082                                  &shrink_list, mm.shrink_list) {
5083                 struct drm_device *dev = dev_priv->dev;
5084
5085                 if (! mutex_trylock(&dev->struct_mutex))
5086                         continue;
5087
5088                 spin_unlock(&shrink_list_lock);
5089
5090                 i915_gem_retire_requests(dev);
5091
5092                 list_for_each_entry_safe(obj_priv, next_obj,
5093                                          &dev_priv->mm.inactive_list,
5094                                          list) {
5095                         if (i915_gem_object_is_purgeable(obj_priv)) {
5096                                 i915_gem_object_unbind(obj_priv->obj);
5097                                 if (--nr_to_scan <= 0)
5098                                         break;
5099                         }
5100                 }
5101
5102                 spin_lock(&shrink_list_lock);
5103                 mutex_unlock(&dev->struct_mutex);
5104
5105                 would_deadlock = 0;
5106
5107                 if (nr_to_scan <= 0)
5108                         break;
5109         }
5110
5111         /* second pass, evict/count anything still on the inactive list */
5112         list_for_each_entry_safe(dev_priv, next_dev,
5113                                  &shrink_list, mm.shrink_list) {
5114                 struct drm_device *dev = dev_priv->dev;
5115
5116                 if (! mutex_trylock(&dev->struct_mutex))
5117                         continue;
5118
5119                 spin_unlock(&shrink_list_lock);
5120
5121                 list_for_each_entry_safe(obj_priv, next_obj,
5122                                          &dev_priv->mm.inactive_list,
5123                                          list) {
5124                         if (nr_to_scan > 0) {
5125                                 i915_gem_object_unbind(obj_priv->obj);
5126                                 nr_to_scan--;
5127                         } else
5128                                 cnt++;
5129                 }
5130
5131                 spin_lock(&shrink_list_lock);
5132                 mutex_unlock(&dev->struct_mutex);
5133
5134                 would_deadlock = 0;
5135         }
5136
5137         spin_unlock(&shrink_list_lock);
5138
5139         if (would_deadlock)
5140                 return -1;
5141         else if (cnt > 0)
5142                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5143         else
5144                 return 0;
5145 }
5146
5147 static struct shrinker shrinker = {
5148         .shrink = i915_gem_shrink,
5149         .seeks = DEFAULT_SEEKS,
5150 };
5151
5152 __init void
5153 i915_gem_shrinker_init(void)
5154 {
5155     register_shrinker(&shrinker);
5156 }
5157
5158 __exit void
5159 i915_gem_shrinker_exit(void)
5160 {
5161     unregister_shrinker(&shrinker);
5162 }