drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  42                                                           bool write);
  43 static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
  44                                                                   uint64_t offset,
  45                                                                   uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
  47 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  48                                                     unsigned alignment,
  49                                                     bool map_and_fenceable);
  50 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  51                                      struct drm_i915_fence_reg *reg);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev,
  53                                 struct drm_i915_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file);
  56 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
  57
  58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  59                                     struct shrink_control *sc);
  60
  61 /* some bookkeeping */
  62 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  63                                   size_t size)
  64 {
  65         dev_priv->mm.object_count++;
  66         dev_priv->mm.object_memory += size;
  67 }
  68
  69 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  70                                      size_t size)
  71 {
  72         dev_priv->mm.object_count--;
  73         dev_priv->mm.object_memory -= size;
  74 }
  75
  76 static int
  77 i915_gem_wait_for_error(struct drm_device *dev)
  78 {
  79         struct drm_i915_private *dev_priv = dev->dev_private;
  80         struct completion *x = &dev_priv->error_completion;
  81         unsigned long flags;
  82         int ret;
  83
  84         if (!atomic_read(&dev_priv->mm.wedged))
  85                 return 0;
  86
  87         ret = wait_for_completion_interruptible(x);
  88         if (ret)
  89                 return ret;
  90
  91         if (atomic_read(&dev_priv->mm.wedged)) {
  92                 /* GPU is hung, bump the completion count to account for
  93                  * the token we just consumed so that we never hit zero and
  94                  * end up waiting upon a subsequent completion event that
  95                  * will never happen.
  96                  */
  97                 spin_lock_irqsave(&x->wait.lock, flags);
  98                 x->done++;
  99                 spin_unlock_irqrestore(&x->wait.lock, flags);
 100         }
 101         return 0;
 102 }
 103
 104 int i915_mutex_lock_interruptible(struct drm_device *dev)
 105 {
 106         int ret;
 107
 108         ret = i915_gem_wait_for_error(dev);
 109         if (ret)
 110                 return ret;
 111
 112         ret = mutex_lock_interruptible(&dev->struct_mutex);
 113         if (ret)
 114                 return ret;
 115
 116         WARN_ON(i915_verify_lists(dev));
 117         return 0;
 118 }
 119
 120 static inline bool
 121 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 122 {
 123         return obj->gtt_space && !obj->active && obj->pin_count == 0;
 124 }
 125
 126 void i915_gem_do_init(struct drm_device *dev,
 127                       unsigned long start,
 128                       unsigned long mappable_end,
 129                       unsigned long end)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132
 133         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 134
 135         dev_priv->mm.gtt_start = start;
 136         dev_priv->mm.gtt_mappable_end = mappable_end;
 137         dev_priv->mm.gtt_end = end;
 138         dev_priv->mm.gtt_total = end - start;
 139         dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
 140
 141         /* Take over this portion of the GTT */
 142         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 143 }
 144
 145 int
 146 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 147                     struct drm_file *file)
 148 {
 149         struct drm_i915_gem_init *args = data;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         mutex_lock(&dev->struct_mutex);
 156         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 157         mutex_unlock(&dev->struct_mutex);
 158
 159         return 0;
 160 }
 161
 162 int
 163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 164                             struct drm_file *file)
 165 {
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct drm_i915_gem_get_aperture *args = data;
 168         struct drm_i915_gem_object *obj;
 169         size_t pinned;
 170
 171         if (!(dev->driver->driver_features & DRIVER_GEM))
 172                 return -ENODEV;
 173
 174         pinned = 0;
 175         mutex_lock(&dev->struct_mutex);
 176         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 177                 pinned += obj->gtt_space->size;
 178         mutex_unlock(&dev->struct_mutex);
 179
 180         args->aper_size = dev_priv->mm.gtt_total;
 181         args->aper_available_size = args->aper_size -pinned;
 182
 183         return 0;
 184 }
 185
 186 static int
 187 i915_gem_create(struct drm_file *file,
 188                 struct drm_device *dev,
 189                 uint64_t size,
 190                 uint32_t *handle_p)
 191 {
 192         struct drm_i915_gem_object *obj;
 193         int ret;
 194         u32 handle;
 195
 196         size = roundup(size, PAGE_SIZE);
 197
 198         /* Allocate the new object */
 199         obj = i915_gem_alloc_object(dev, size);
 200         if (obj == NULL)
 201                 return -ENOMEM;
 202
 203         ret = drm_gem_handle_create(file, &obj->base, &handle);
 204         if (ret) {
 205                 drm_gem_object_release(&obj->base);
 206                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 207                 kfree(obj);
 208                 return ret;
 209         }
 210
 211         /* drop reference from allocate - handle holds it now */
 212         drm_gem_object_unreference(&obj->base);
 213         trace_i915_gem_object_create(obj);
 214
 215         *handle_p = handle;
 216         return 0;
 217 }
 218
 219 int
 220 i915_gem_dumb_create(struct drm_file *file,
 221                      struct drm_device *dev,
 222                      struct drm_mode_create_dumb *args)
 223 {
 224         /* have to work out size/pitch and return them */
 225         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 226         args->size = args->pitch * args->height;
 227         return i915_gem_create(file, dev,
 228                                args->size, &args->handle);
 229 }
 230
 231 int i915_gem_dumb_destroy(struct drm_file *file,
 232                           struct drm_device *dev,
 233                           uint32_t handle)
 234 {
 235         return drm_gem_handle_delete(file, handle);
 236 }
 237
 238 /**
 239  * Creates a new mm object and returns a handle to it.
 240  */
 241 int
 242 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 243                       struct drm_file *file)
 244 {
 245         struct drm_i915_gem_create *args = data;
 246         return i915_gem_create(file, dev,
 247                                args->size, &args->handle);
 248 }
 249
 250 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
 251 {
 252         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
 253
 254         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 255                 obj->tiling_mode != I915_TILING_NONE;
 256 }
 257
 258 static inline void
 259 slow_shmem_copy(struct page *dst_page,
 260                 int dst_offset,
 261                 struct page *src_page,
 262                 int src_offset,
 263                 int length)
 264 {
 265         char *dst_vaddr, *src_vaddr;
 266
 267         dst_vaddr = kmap(dst_page);
 268         src_vaddr = kmap(src_page);
 269
 270         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 271
 272         kunmap(src_page);
 273         kunmap(dst_page);
 274 }
 275
 276 static inline void
 277 slow_shmem_bit17_copy(struct page *gpu_page,
 278                       int gpu_offset,
 279                       struct page *cpu_page,
 280                       int cpu_offset,
 281                       int length,
 282                       int is_read)
 283 {
 284         char *gpu_vaddr, *cpu_vaddr;
 285
 286         /* Use the unswizzled path if this page isn't affected. */
 287         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 288                 if (is_read)
 289                         return slow_shmem_copy(cpu_page, cpu_offset,
 290                                                gpu_page, gpu_offset, length);
 291                 else
 292                         return slow_shmem_copy(gpu_page, gpu_offset,
 293                                                cpu_page, cpu_offset, length);
 294         }
 295
 296         gpu_vaddr = kmap(gpu_page);
 297         cpu_vaddr = kmap(cpu_page);
 298
 299         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 300          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 301          */
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 if (is_read) {
 308                         memcpy(cpu_vaddr + cpu_offset,
 309                                gpu_vaddr + swizzled_gpu_offset,
 310                                this_length);
 311                 } else {
 312                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 313                                cpu_vaddr + cpu_offset,
 314                                this_length);
 315                 }
 316                 cpu_offset += this_length;
 317                 gpu_offset += this_length;
 318                 length -= this_length;
 319         }
 320
 321         kunmap(cpu_page);
 322         kunmap(gpu_page);
 323 }
 324
 325 /**
 326  * This is the fast shmem pread path, which attempts to copy_from_user directly
 327  * from the backing pages of the object to the user's address space.  On a
 328  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 329  */
 330 static int
 331 i915_gem_shmem_pread_fast(struct drm_device *dev,
 332                           struct drm_i915_gem_object *obj,
 333                           struct drm_i915_gem_pread *args,
 334                           struct drm_file *file)
 335 {
 336         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 337         ssize_t remain;
 338         loff_t offset;
 339         char __user *user_data;
 340         int page_offset, page_length;
 341
 342         user_data = (char __user *) (uintptr_t) args->data_ptr;
 343         remain = args->size;
 344
 345         offset = args->offset;
 346
 347         while (remain > 0) {
 348                 struct page *page;
 349                 char *vaddr;
 350                 int ret;
 351
 352                 /* Operation in this page
 353                  *
 354                  * page_offset = offset within page
 355                  * page_length = bytes to copy for this page
 356                  */
 357                 page_offset = offset_in_page(offset);
 358                 page_length = remain;
 359                 if ((page_offset + remain) > PAGE_SIZE)
 360                         page_length = PAGE_SIZE - page_offset;
 361
 362                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 363                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 364                 if (IS_ERR(page))
 365                         return PTR_ERR(page);
 366
 367                 vaddr = kmap_atomic(page);
 368                 ret = __copy_to_user_inatomic(user_data,
 369                                               vaddr + page_offset,
 370                                               page_length);
 371                 kunmap_atomic(vaddr);
 372
 373                 mark_page_accessed(page);
 374                 page_cache_release(page);
 375                 if (ret)
 376                         return -EFAULT;
 377
 378                 remain -= page_length;
 379                 user_data += page_length;
 380                 offset += page_length;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * This is the fallback shmem pread path, which allocates temporary storage
 388  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 389  * can copy out of the object's backing pages while holding the struct mutex
 390  * and not take page faults.
 391  */
 392 static int
 393 i915_gem_shmem_pread_slow(struct drm_device *dev,
 394                           struct drm_i915_gem_object *obj,
 395                           struct drm_i915_gem_pread *args,
 396                           struct drm_file *file)
 397 {
 398         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 399         struct mm_struct *mm = current->mm;
 400         struct page **user_pages;
 401         ssize_t remain;
 402         loff_t offset, pinned_pages, i;
 403         loff_t first_data_page, last_data_page, num_pages;
 404         int shmem_page_offset;
 405         int data_page_index, data_page_offset;
 406         int page_length;
 407         int ret;
 408         uint64_t data_ptr = args->data_ptr;
 409         int do_bit17_swizzling;
 410
 411         remain = args->size;
 412
 413         /* Pin the user pages containing the data.  We can't fault while
 414          * holding the struct mutex, yet we want to hold it while
 415          * dereferencing the user data.
 416          */
 417         first_data_page = data_ptr / PAGE_SIZE;
 418         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 419         num_pages = last_data_page - first_data_page + 1;
 420
 421         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 422         if (user_pages == NULL)
 423                 return -ENOMEM;
 424
 425         mutex_unlock(&dev->struct_mutex);
 426         down_read(&mm->mmap_sem);
 427         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 428                                       num_pages, 1, 0, user_pages, NULL);
 429         up_read(&mm->mmap_sem);
 430         mutex_lock(&dev->struct_mutex);
 431         if (pinned_pages < num_pages) {
 432                 ret = -EFAULT;
 433                 goto out;
 434         }
 435
 436         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 437                                                         args->offset,
 438                                                         args->size);
 439         if (ret)
 440                 goto out;
 441
 442         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 443
 444         offset = args->offset;
 445
 446         while (remain > 0) {
 447                 struct page *page;
 448
 449                 /* Operation in this page
 450                  *
 451                  * shmem_page_offset = offset within page in shmem file
 452                  * data_page_index = page number in get_user_pages return
 453                  * data_page_offset = offset with data_page_index page.
 454                  * page_length = bytes to copy for this page
 455                  */
 456                 shmem_page_offset = offset_in_page(offset);
 457                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 458                 data_page_offset = offset_in_page(data_ptr);
 459
 460                 page_length = remain;
 461                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 462                         page_length = PAGE_SIZE - shmem_page_offset;
 463                 if ((data_page_offset + page_length) > PAGE_SIZE)
 464                         page_length = PAGE_SIZE - data_page_offset;
 465
 466                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 467                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 468                 if (IS_ERR(page))
 469                         return PTR_ERR(page);
 470
 471                 if (do_bit17_swizzling) {
 472                         slow_shmem_bit17_copy(page,
 473                                               shmem_page_offset,
 474                                               user_pages[data_page_index],
 475                                               data_page_offset,
 476                                               page_length,
 477                                               1);
 478                 } else {
 479                         slow_shmem_copy(user_pages[data_page_index],
 480                                         data_page_offset,
 481                                         page,
 482                                         shmem_page_offset,
 483                                         page_length);
 484                 }
 485
 486                 mark_page_accessed(page);
 487                 page_cache_release(page);
 488
 489                 remain -= page_length;
 490                 data_ptr += page_length;
 491                 offset += page_length;
 492         }
 493
 494 out:
 495         for (i = 0; i < pinned_pages; i++) {
 496                 SetPageDirty(user_pages[i]);
 497                 mark_page_accessed(user_pages[i]);
 498                 page_cache_release(user_pages[i]);
 499         }
 500         drm_free_large(user_pages);
 501
 502         return ret;
 503 }
 504
 505 /**
 506  * Reads data from the object referenced by handle.
 507  *
 508  * On error, the contents of *data are undefined.
 509  */
 510 int
 511 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 512                      struct drm_file *file)
 513 {
 514         struct drm_i915_gem_pread *args = data;
 515         struct drm_i915_gem_object *obj;
 516         int ret = 0;
 517
 518         if (args->size == 0)
 519                 return 0;
 520
 521         if (!access_ok(VERIFY_WRITE,
 522                        (char __user *)(uintptr_t)args->data_ptr,
 523                        args->size))
 524                 return -EFAULT;
 525
 526         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 527                                        args->size);
 528         if (ret)
 529                 return -EFAULT;
 530
 531         ret = i915_mutex_lock_interruptible(dev);
 532         if (ret)
 533                 return ret;
 534
 535         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 536         if (&obj->base == NULL) {
 537                 ret = -ENOENT;
 538                 goto unlock;
 539         }
 540
 541         /* Bounds check source.  */
 542         if (args->offset > obj->base.size ||
 543             args->size > obj->base.size - args->offset) {
 544                 ret = -EINVAL;
 545                 goto out;
 546         }
 547
 548         trace_i915_gem_object_pread(obj, args->offset, args->size);
 549
 550         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 551                                                         args->offset,
 552                                                         args->size);
 553         if (ret)
 554                 goto out;
 555
 556         ret = -EFAULT;
 557         if (!i915_gem_object_needs_bit17_swizzle(obj))
 558                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
 559         if (ret == -EFAULT)
 560                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
 561
 562 out:
 563         drm_gem_object_unreference(&obj->base);
 564 unlock:
 565         mutex_unlock(&dev->struct_mutex);
 566         return ret;
 567 }
 568
 569 /* This is the fast write path which cannot handle
 570  * page faults in the source data
 571  */
 572
 573 static inline int
 574 fast_user_write(struct io_mapping *mapping,
 575                 loff_t page_base, int page_offset,
 576                 char __user *user_data,
 577                 int length)
 578 {
 579         char *vaddr_atomic;
 580         unsigned long unwritten;
 581
 582         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 583         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 584                                                       user_data, length);
 585         io_mapping_unmap_atomic(vaddr_atomic);
 586         return unwritten;
 587 }
 588
 589 /* Here's the write path which can sleep for
 590  * page faults
 591  */
 592
 593 static inline void
 594 slow_kernel_write(struct io_mapping *mapping,
 595                   loff_t gtt_base, int gtt_offset,
 596                   struct page *user_page, int user_offset,
 597                   int length)
 598 {
 599         char __iomem *dst_vaddr;
 600         char *src_vaddr;
 601
 602         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 603         src_vaddr = kmap(user_page);
 604
 605         memcpy_toio(dst_vaddr + gtt_offset,
 606                     src_vaddr + user_offset,
 607                     length);
 608
 609         kunmap(user_page);
 610         io_mapping_unmap(dst_vaddr);
 611 }
 612
 613 /**
 614  * This is the fast pwrite path, where we copy the data directly from the
 615  * user into the GTT, uncached.
 616  */
 617 static int
 618 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 619                          struct drm_i915_gem_object *obj,
 620                          struct drm_i915_gem_pwrite *args,
 621                          struct drm_file *file)
 622 {
 623         drm_i915_private_t *dev_priv = dev->dev_private;
 624         ssize_t remain;
 625         loff_t offset, page_base;
 626         char __user *user_data;
 627         int page_offset, page_length;
 628
 629         user_data = (char __user *) (uintptr_t) args->data_ptr;
 630         remain = args->size;
 631
 632         offset = obj->gtt_offset + args->offset;
 633
 634         while (remain > 0) {
 635                 /* Operation in this page
 636                  *
 637                  * page_base = page offset within aperture
 638                  * page_offset = offset within page
 639                  * page_length = bytes to copy for this page
 640                  */
 641                 page_base = offset & PAGE_MASK;
 642                 page_offset = offset_in_page(offset);
 643                 page_length = remain;
 644                 if ((page_offset + remain) > PAGE_SIZE)
 645                         page_length = PAGE_SIZE - page_offset;
 646
 647                 /* If we get a fault while copying data, then (presumably) our
 648                  * source page isn't available.  Return the error and we'll
 649                  * retry in the slow path.
 650                  */
 651                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 652                                     page_offset, user_data, page_length))
 653                         return -EFAULT;
 654
 655                 remain -= page_length;
 656                 user_data += page_length;
 657                 offset += page_length;
 658         }
 659
 660         return 0;
 661 }
 662
 663 /**
 664  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 665  * the memory and maps it using kmap_atomic for copying.
 666  *
 667  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 668  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 669  */
 670 static int
 671 i915_gem_gtt_pwrite_slow(struct drm_device *dev,
 672                          struct drm_i915_gem_object *obj,
 673                          struct drm_i915_gem_pwrite *args,
 674                          struct drm_file *file)
 675 {
 676         drm_i915_private_t *dev_priv = dev->dev_private;
 677         ssize_t remain;
 678         loff_t gtt_page_base, offset;
 679         loff_t first_data_page, last_data_page, num_pages;
 680         loff_t pinned_pages, i;
 681         struct page **user_pages;
 682         struct mm_struct *mm = current->mm;
 683         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 684         int ret;
 685         uint64_t data_ptr = args->data_ptr;
 686
 687         remain = args->size;
 688
 689         /* Pin the user pages containing the data.  We can't fault while
 690          * holding the struct mutex, and all of the pwrite implementations
 691          * want to hold it while dereferencing the user data.
 692          */
 693         first_data_page = data_ptr / PAGE_SIZE;
 694         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 695         num_pages = last_data_page - first_data_page + 1;
 696
 697         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 698         if (user_pages == NULL)
 699                 return -ENOMEM;
 700
 701         mutex_unlock(&dev->struct_mutex);
 702         down_read(&mm->mmap_sem);
 703         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 704                                       num_pages, 0, 0, user_pages, NULL);
 705         up_read(&mm->mmap_sem);
 706         mutex_lock(&dev->struct_mutex);
 707         if (pinned_pages < num_pages) {
 708                 ret = -EFAULT;
 709                 goto out_unpin_pages;
 710         }
 711
 712         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 713         if (ret)
 714                 goto out_unpin_pages;
 715
 716         ret = i915_gem_object_put_fence(obj);
 717         if (ret)
 718                 goto out_unpin_pages;
 719
 720         offset = obj->gtt_offset + args->offset;
 721
 722         while (remain > 0) {
 723                 /* Operation in this page
 724                  *
 725                  * gtt_page_base = page offset within aperture
 726                  * gtt_page_offset = offset within page in aperture
 727                  * data_page_index = page number in get_user_pages return
 728                  * data_page_offset = offset with data_page_index page.
 729                  * page_length = bytes to copy for this page
 730                  */
 731                 gtt_page_base = offset & PAGE_MASK;
 732                 gtt_page_offset = offset_in_page(offset);
 733                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 734                 data_page_offset = offset_in_page(data_ptr);
 735
 736                 page_length = remain;
 737                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 738                         page_length = PAGE_SIZE - gtt_page_offset;
 739                 if ((data_page_offset + page_length) > PAGE_SIZE)
 740                         page_length = PAGE_SIZE - data_page_offset;
 741
 742                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 743                                   gtt_page_base, gtt_page_offset,
 744                                   user_pages[data_page_index],
 745                                   data_page_offset,
 746                                   page_length);
 747
 748                 remain -= page_length;
 749                 offset += page_length;
 750                 data_ptr += page_length;
 751         }
 752
 753 out_unpin_pages:
 754         for (i = 0; i < pinned_pages; i++)
 755                 page_cache_release(user_pages[i]);
 756         drm_free_large(user_pages);
 757
 758         return ret;
 759 }
 760
 761 /**
 762  * This is the fast shmem pwrite path, which attempts to directly
 763  * copy_from_user into the kmapped pages backing the object.
 764  */
 765 static int
 766 i915_gem_shmem_pwrite_fast(struct drm_device *dev,
 767                            struct drm_i915_gem_object *obj,
 768                            struct drm_i915_gem_pwrite *args,
 769                            struct drm_file *file)
 770 {
 771         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 772         ssize_t remain;
 773         loff_t offset;
 774         char __user *user_data;
 775         int page_offset, page_length;
 776
 777         user_data = (char __user *) (uintptr_t) args->data_ptr;
 778         remain = args->size;
 779
 780         offset = args->offset;
 781         obj->dirty = 1;
 782
 783         while (remain > 0) {
 784                 struct page *page;
 785                 char *vaddr;
 786                 int ret;
 787
 788                 /* Operation in this page
 789                  *
 790                  * page_offset = offset within page
 791                  * page_length = bytes to copy for this page
 792                  */
 793                 page_offset = offset_in_page(offset);
 794                 page_length = remain;
 795                 if ((page_offset + remain) > PAGE_SIZE)
 796                         page_length = PAGE_SIZE - page_offset;
 797
 798                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 799                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 800                 if (IS_ERR(page))
 801                         return PTR_ERR(page);
 802
 803                 vaddr = kmap_atomic(page, KM_USER0);
 804                 ret = __copy_from_user_inatomic(vaddr + page_offset,
 805                                                 user_data,
 806                                                 page_length);
 807                 kunmap_atomic(vaddr, KM_USER0);
 808
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811                 page_cache_release(page);
 812
 813                 /* If we get a fault while copying data, then (presumably) our
 814                  * source page isn't available.  Return the error and we'll
 815                  * retry in the slow path.
 816                  */
 817                 if (ret)
 818                         return -EFAULT;
 819
 820                 remain -= page_length;
 821                 user_data += page_length;
 822                 offset += page_length;
 823         }
 824
 825         return 0;
 826 }
 827
 828 /**
 829  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 830  * the memory and maps it using kmap_atomic for copying.
 831  *
 832  * This avoids taking mmap_sem for faulting on the user's address while the
 833  * struct_mutex is held.
 834  */
 835 static int
 836 i915_gem_shmem_pwrite_slow(struct drm_device *dev,
 837                            struct drm_i915_gem_object *obj,
 838                            struct drm_i915_gem_pwrite *args,
 839                            struct drm_file *file)
 840 {
 841         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
 842         struct mm_struct *mm = current->mm;
 843         struct page **user_pages;
 844         ssize_t remain;
 845         loff_t offset, pinned_pages, i;
 846         loff_t first_data_page, last_data_page, num_pages;
 847         int shmem_page_offset;
 848         int data_page_index,  data_page_offset;
 849         int page_length;
 850         int ret;
 851         uint64_t data_ptr = args->data_ptr;
 852         int do_bit17_swizzling;
 853
 854         remain = args->size;
 855
 856         /* Pin the user pages containing the data.  We can't fault while
 857          * holding the struct mutex, and all of the pwrite implementations
 858          * want to hold it while dereferencing the user data.
 859          */
 860         first_data_page = data_ptr / PAGE_SIZE;
 861         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 862         num_pages = last_data_page - first_data_page + 1;
 863
 864         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 865         if (user_pages == NULL)
 866                 return -ENOMEM;
 867
 868         mutex_unlock(&dev->struct_mutex);
 869         down_read(&mm->mmap_sem);
 870         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 871                                       num_pages, 0, 0, user_pages, NULL);
 872         up_read(&mm->mmap_sem);
 873         mutex_lock(&dev->struct_mutex);
 874         if (pinned_pages < num_pages) {
 875                 ret = -EFAULT;
 876                 goto out;
 877         }
 878
 879         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 880         if (ret)
 881                 goto out;
 882
 883         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         offset = args->offset;
 886         obj->dirty = 1;
 887
 888         while (remain > 0) {
 889                 struct page *page;
 890
 891                 /* Operation in this page
 892                  *
 893                  * shmem_page_offset = offset within page in shmem file
 894                  * data_page_index = page number in get_user_pages return
 895                  * data_page_offset = offset with data_page_index page.
 896                  * page_length = bytes to copy for this page
 897                  */
 898                 shmem_page_offset = offset_in_page(offset);
 899                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 900                 data_page_offset = offset_in_page(data_ptr);
 901
 902                 page_length = remain;
 903                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 904                         page_length = PAGE_SIZE - shmem_page_offset;
 905                 if ((data_page_offset + page_length) > PAGE_SIZE)
 906                         page_length = PAGE_SIZE - data_page_offset;
 907
 908                 page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT,
 909                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
 910                 if (IS_ERR(page)) {
 911                         ret = PTR_ERR(page);
 912                         goto out;
 913                 }
 914
 915                 if (do_bit17_swizzling) {
 916                         slow_shmem_bit17_copy(page,
 917                                               shmem_page_offset,
 918                                               user_pages[data_page_index],
 919                                               data_page_offset,
 920                                               page_length,
 921                                               0);
 922                 } else {
 923                         slow_shmem_copy(page,
 924                                         shmem_page_offset,
 925                                         user_pages[data_page_index],
 926                                         data_page_offset,
 927                                         page_length);
 928                 }
 929
 930                 set_page_dirty(page);
 931                 mark_page_accessed(page);
 932                 page_cache_release(page);
 933
 934                 remain -= page_length;
 935                 data_ptr += page_length;
 936                 offset += page_length;
 937         }
 938
 939 out:
 940         for (i = 0; i < pinned_pages; i++)
 941                 page_cache_release(user_pages[i]);
 942         drm_free_large(user_pages);
 943
 944         return ret;
 945 }
 946
 947 /**
 948  * Writes data to the object referenced by handle.
 949  *
 950  * On error, the contents of the buffer that were to be modified are undefined.
 951  */
 952 int
 953 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 954                       struct drm_file *file)
 955 {
 956         struct drm_i915_gem_pwrite *args = data;
 957         struct drm_i915_gem_object *obj;
 958         int ret;
 959
 960         if (args->size == 0)
 961                 return 0;
 962
 963         if (!access_ok(VERIFY_READ,
 964                        (char __user *)(uintptr_t)args->data_ptr,
 965                        args->size))
 966                 return -EFAULT;
 967
 968         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
 969                                       args->size);
 970         if (ret)
 971                 return -EFAULT;
 972
 973         ret = i915_mutex_lock_interruptible(dev);
 974         if (ret)
 975                 return ret;
 976
 977         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 978         if (&obj->base == NULL) {
 979                 ret = -ENOENT;
 980                 goto unlock;
 981         }
 982
 983         /* Bounds check destination. */
 984         if (args->offset > obj->base.size ||
 985             args->size > obj->base.size - args->offset) {
 986                 ret = -EINVAL;
 987                 goto out;
 988         }
 989
 990         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 991
 992         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 993          * it would end up going through the fenced access, and we'll get
 994          * different detiling behavior between reading and writing.
 995          * pread/pwrite currently are reading and writing from the CPU
 996          * perspective, requiring manual detiling by the client.
 997          */
 998         if (obj->phys_obj)
 999                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1000         else if (obj->gtt_space &&
1001                  obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1002                 ret = i915_gem_object_pin(obj, 0, true);
1003                 if (ret)
1004                         goto out;
1005
1006                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1007                 if (ret)
1008                         goto out_unpin;
1009
1010                 ret = i915_gem_object_put_fence(obj);
1011                 if (ret)
1012                         goto out_unpin;
1013
1014                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1015                 if (ret == -EFAULT)
1016                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1017
1018 out_unpin:
1019                 i915_gem_object_unpin(obj);
1020         } else {
1021                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1022                 if (ret)
1023                         goto out;
1024
1025                 ret = -EFAULT;
1026                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1027                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1028                 if (ret == -EFAULT)
1029                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1030         }
1031
1032 out:
1033         drm_gem_object_unreference(&obj->base);
1034 unlock:
1035         mutex_unlock(&dev->struct_mutex);
1036         return ret;
1037 }
1038
1039 /**
1040  * Called when user space prepares to use an object with the CPU, either
1041  * through the mmap ioctl's mapping or a GTT mapping.
1042  */
1043 int
1044 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1045                           struct drm_file *file)
1046 {
1047         struct drm_i915_gem_set_domain *args = data;
1048         struct drm_i915_gem_object *obj;
1049         uint32_t read_domains = args->read_domains;
1050         uint32_t write_domain = args->write_domain;
1051         int ret;
1052
1053         if (!(dev->driver->driver_features & DRIVER_GEM))
1054                 return -ENODEV;
1055
1056         /* Only handle setting domains to types used by the CPU. */
1057         if (write_domain & I915_GEM_GPU_DOMAINS)
1058                 return -EINVAL;
1059
1060         if (read_domains & I915_GEM_GPU_DOMAINS)
1061                 return -EINVAL;
1062
1063         /* Having something in the write domain implies it's in the read
1064          * domain, and only that read domain.  Enforce that in the request.
1065          */
1066         if (write_domain != 0 && read_domains != write_domain)
1067                 return -EINVAL;
1068
1069         ret = i915_mutex_lock_interruptible(dev);
1070         if (ret)
1071                 return ret;
1072
1073         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1074         if (&obj->base == NULL) {
1075                 ret = -ENOENT;
1076                 goto unlock;
1077         }
1078
1079         if (read_domains & I915_GEM_DOMAIN_GTT) {
1080                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1081
1082                 /* Silently promote "you're not bound, there was nothing to do"
1083                  * to success, since the client was just asking us to
1084                  * make sure everything was done.
1085                  */
1086                 if (ret == -EINVAL)
1087                         ret = 0;
1088         } else {
1089                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1090         }
1091
1092         drm_gem_object_unreference(&obj->base);
1093 unlock:
1094         mutex_unlock(&dev->struct_mutex);
1095         return ret;
1096 }
1097
1098 /**
1099  * Called when user space has done writes to this buffer
1100  */
1101 int
1102 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1103                          struct drm_file *file)
1104 {
1105         struct drm_i915_gem_sw_finish *args = data;
1106         struct drm_i915_gem_object *obj;
1107         int ret = 0;
1108
1109         if (!(dev->driver->driver_features & DRIVER_GEM))
1110                 return -ENODEV;
1111
1112         ret = i915_mutex_lock_interruptible(dev);
1113         if (ret)
1114                 return ret;
1115
1116         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1117         if (&obj->base == NULL) {
1118                 ret = -ENOENT;
1119                 goto unlock;
1120         }
1121
1122         /* Pinned buffers may be scanout, so flush the cache */
1123         if (obj->pin_count)
1124                 i915_gem_object_flush_cpu_write_domain(obj);
1125
1126         drm_gem_object_unreference(&obj->base);
1127 unlock:
1128         mutex_unlock(&dev->struct_mutex);
1129         return ret;
1130 }
1131
1132 /**
1133  * Maps the contents of an object, returning the address it is mapped
1134  * into.
1135  *
1136  * While the mapping holds a reference on the contents of the object, it doesn't
1137  * imply a ref on the object itself.
1138  */
1139 int
1140 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1141                     struct drm_file *file)
1142 {
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144         struct drm_i915_gem_mmap *args = data;
1145         struct drm_gem_object *obj;
1146         unsigned long addr;
1147
1148         if (!(dev->driver->driver_features & DRIVER_GEM))
1149                 return -ENODEV;
1150
1151         obj = drm_gem_object_lookup(dev, file, args->handle);
1152         if (obj == NULL)
1153                 return -ENOENT;
1154
1155         if (obj->size > dev_priv->mm.gtt_mappable_end) {
1156                 drm_gem_object_unreference_unlocked(obj);
1157                 return -E2BIG;
1158         }
1159
1160         down_write(&current->mm->mmap_sem);
1161         addr = do_mmap(obj->filp, 0, args->size,
1162                        PROT_READ | PROT_WRITE, MAP_SHARED,
1163                        args->offset);
1164         up_write(&current->mm->mmap_sem);
1165         drm_gem_object_unreference_unlocked(obj);
1166         if (IS_ERR((void *)addr))
1167                 return addr;
1168
1169         args->addr_ptr = (uint64_t) addr;
1170
1171         return 0;
1172 }
1173
1174 /**
1175  * i915_gem_fault - fault a page into the GTT
1176  * vma: VMA in question
1177  * vmf: fault info
1178  *
1179  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1180  * from userspace.  The fault handler takes care of binding the object to
1181  * the GTT (if needed), allocating and programming a fence register (again,
1182  * only if needed based on whether the old reg is still valid or the object
1183  * is tiled) and inserting a new PTE into the faulting process.
1184  *
1185  * Note that the faulting process may involve evicting existing objects
1186  * from the GTT and/or fence registers to make room.  So performance may
1187  * suffer if the GTT working set is large or there are few fence registers
1188  * left.
1189  */
1190 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1191 {
1192         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1193         struct drm_device *dev = obj->base.dev;
1194         drm_i915_private_t *dev_priv = dev->dev_private;
1195         pgoff_t page_offset;
1196         unsigned long pfn;
1197         int ret = 0;
1198         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1199
1200         /* We don't use vmf->pgoff since that has the fake offset */
1201         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1202                 PAGE_SHIFT;
1203
1204         ret = i915_mutex_lock_interruptible(dev);
1205         if (ret)
1206                 goto out;
1207
1208         trace_i915_gem_object_fault(obj, page_offset, true, write);
1209
1210         /* Now bind it into the GTT if needed */
1211         if (!obj->map_and_fenceable) {
1212                 ret = i915_gem_object_unbind(obj);
1213                 if (ret)
1214                         goto unlock;
1215         }
1216         if (!obj->gtt_space) {
1217                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1218                 if (ret)
1219                         goto unlock;
1220         }
1221
1222         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1223         if (ret)
1224                 goto unlock;
1225
1226         if (obj->tiling_mode == I915_TILING_NONE)
1227                 ret = i915_gem_object_put_fence(obj);
1228         else
1229                 ret = i915_gem_object_get_fence(obj, NULL);
1230         if (ret)
1231                 goto unlock;
1232
1233         if (i915_gem_object_is_inactive(obj))
1234                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1235
1236         obj->fault_mappable = true;
1237
1238         pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1239                 page_offset;
1240
1241         /* Finally, remap it using the new GTT offset */
1242         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1243 unlock:
1244         mutex_unlock(&dev->struct_mutex);
1245 out:
1246         switch (ret) {
1247         case -EIO:
1248         case -EAGAIN:
1249                 /* Give the error handler a chance to run and move the
1250                  * objects off the GPU active list. Next time we service the
1251                  * fault, we should be able to transition the page into the
1252                  * GTT without touching the GPU (and so avoid further
1253                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1254                  * with coherency, just lost writes.
1255                  */
1256                 set_need_resched();
1257         case 0:
1258         case -ERESTARTSYS:
1259         case -EINTR:
1260                 return VM_FAULT_NOPAGE;
1261         case -ENOMEM:
1262                 return VM_FAULT_OOM;
1263         default:
1264                 return VM_FAULT_SIGBUS;
1265         }
1266 }
1267
1268 /**
1269  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1270  * @obj: obj in question
1271  *
1272  * GEM memory mapping works by handing back to userspace a fake mmap offset
1273  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1274  * up the object based on the offset and sets up the various memory mapping
1275  * structures.
1276  *
1277  * This routine allocates and attaches a fake offset for @obj.
1278  */
1279 static int
1280 i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1281 {
1282         struct drm_device *dev = obj->base.dev;
1283         struct drm_gem_mm *mm = dev->mm_private;
1284         struct drm_map_list *list;
1285         struct drm_local_map *map;
1286         int ret = 0;
1287
1288         /* Set the object up for mmap'ing */
1289         list = &obj->base.map_list;
1290         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1291         if (!list->map)
1292                 return -ENOMEM;
1293
1294         map = list->map;
1295         map->type = _DRM_GEM;
1296         map->size = obj->base.size;
1297         map->handle = obj;
1298
1299         /* Get a DRM GEM mmap offset allocated... */
1300         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1301                                                     obj->base.size / PAGE_SIZE,
1302                                                     0, 0);
1303         if (!list->file_offset_node) {
1304                 DRM_ERROR("failed to allocate offset for bo %d\n",
1305                           obj->base.name);
1306                 ret = -ENOSPC;
1307                 goto out_free_list;
1308         }
1309
1310         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1311                                                   obj->base.size / PAGE_SIZE,
1312                                                   0);
1313         if (!list->file_offset_node) {
1314                 ret = -ENOMEM;
1315                 goto out_free_list;
1316         }
1317
1318         list->hash.key = list->file_offset_node->start;
1319         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1320         if (ret) {
1321                 DRM_ERROR("failed to add to map hash\n");
1322                 goto out_free_mm;
1323         }
1324
1325         return 0;
1326
1327 out_free_mm:
1328         drm_mm_put_block(list->file_offset_node);
1329 out_free_list:
1330         kfree(list->map);
1331         list->map = NULL;
1332
1333         return ret;
1334 }
1335
1336 /**
1337  * i915_gem_release_mmap - remove physical page mappings
1338  * @obj: obj in question
1339  *
1340  * Preserve the reservation of the mmapping with the DRM core code, but
1341  * relinquish ownership of the pages back to the system.
1342  *
1343  * It is vital that we remove the page mapping if we have mapped a tiled
1344  * object through the GTT and then lose the fence register due to
1345  * resource pressure. Similarly if the object has been moved out of the
1346  * aperture, than pages mapped into userspace must be revoked. Removing the
1347  * mapping will then trigger a page fault on the next user access, allowing
1348  * fixup by i915_gem_fault().
1349  */
1350 void
1351 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1352 {
1353         if (!obj->fault_mappable)
1354                 return;
1355
1356         if (obj->base.dev->dev_mapping)
1357                 unmap_mapping_range(obj->base.dev->dev_mapping,
1358                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1359                                     obj->base.size, 1);
1360
1361         obj->fault_mappable = false;
1362 }
1363
1364 static void
1365 i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1366 {
1367         struct drm_device *dev = obj->base.dev;
1368         struct drm_gem_mm *mm = dev->mm_private;
1369         struct drm_map_list *list = &obj->base.map_list;
1370
1371         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1372         drm_mm_put_block(list->file_offset_node);
1373         kfree(list->map);
1374         list->map = NULL;
1375 }
1376
1377 static uint32_t
1378 i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
1379 {
1380         struct drm_device *dev = obj->base.dev;
1381         uint32_t size;
1382
1383         if (INTEL_INFO(dev)->gen >= 4 ||
1384             obj->tiling_mode == I915_TILING_NONE)
1385                 return obj->base.size;
1386
1387         /* Previous chips need a power-of-two fence region when tiling */
1388         if (INTEL_INFO(dev)->gen == 3)
1389                 size = 1024*1024;
1390         else
1391                 size = 512*1024;
1392
1393         while (size < obj->base.size)
1394                 size <<= 1;
1395
1396         return size;
1397 }
1398
1399 /**
1400  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1401  * @obj: object to check
1402  *
1403  * Return the required GTT alignment for an object, taking into account
1404  * potential fence register mapping.
1405  */
1406 static uint32_t
1407 i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
1408 {
1409         struct drm_device *dev = obj->base.dev;
1410
1411         /*
1412          * Minimum alignment is 4k (GTT page size), but might be greater
1413          * if a fence register is needed for the object.
1414          */
1415         if (INTEL_INFO(dev)->gen >= 4 ||
1416             obj->tiling_mode == I915_TILING_NONE)
1417                 return 4096;
1418
1419         /*
1420          * Previous chips need to be aligned to the size of the smallest
1421          * fence register that can contain the object.
1422          */
1423         return i915_gem_get_gtt_size(obj);
1424 }
1425
1426 /**
1427  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1428  *                                       unfenced object
1429  * @obj: object to check
1430  *
1431  * Return the required GTT alignment for an object, only taking into account
1432  * unfenced tiled surface requirements.
1433  */
1434 uint32_t
1435 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
1436 {
1437         struct drm_device *dev = obj->base.dev;
1438         int tile_height;
1439
1440         /*
1441          * Minimum alignment is 4k (GTT page size) for sane hw.
1442          */
1443         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1444             obj->tiling_mode == I915_TILING_NONE)
1445                 return 4096;
1446
1447         /*
1448          * Older chips need unfenced tiled buffers to be aligned to the left
1449          * edge of an even tile row (where tile rows are counted as if the bo is
1450          * placed in a fenced gtt region).
1451          */
1452         if (IS_GEN2(dev))
1453                 tile_height = 16;
1454         else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
1455                 tile_height = 32;
1456         else
1457                 tile_height = 8;
1458
1459         return tile_height * obj->stride * 2;
1460 }
1461
1462 int
1463 i915_gem_mmap_gtt(struct drm_file *file,
1464                   struct drm_device *dev,
1465                   uint32_t handle,
1466                   uint64_t *offset)
1467 {
1468         struct drm_i915_private *dev_priv = dev->dev_private;
1469         struct drm_i915_gem_object *obj;
1470         int ret;
1471
1472         if (!(dev->driver->driver_features & DRIVER_GEM))
1473                 return -ENODEV;
1474
1475         ret = i915_mutex_lock_interruptible(dev);
1476         if (ret)
1477                 return ret;
1478
1479         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1480         if (&obj->base == NULL) {
1481                 ret = -ENOENT;
1482                 goto unlock;
1483         }
1484
1485         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1486                 ret = -E2BIG;
1487                 goto unlock;
1488         }
1489
1490         if (obj->madv != I915_MADV_WILLNEED) {
1491                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1492                 ret = -EINVAL;
1493                 goto out;
1494         }
1495
1496         if (!obj->base.map_list.map) {
1497                 ret = i915_gem_create_mmap_offset(obj);
1498                 if (ret)
1499                         goto out;
1500         }
1501
1502         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1503
1504 out:
1505         drm_gem_object_unreference(&obj->base);
1506 unlock:
1507         mutex_unlock(&dev->struct_mutex);
1508         return ret;
1509 }
1510
1511 /**
1512  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1513  * @dev: DRM device
1514  * @data: GTT mapping ioctl data
1515  * @file: GEM object info
1516  *
1517  * Simply returns the fake offset to userspace so it can mmap it.
1518  * The mmap call will end up in drm_gem_mmap(), which will set things
1519  * up so we can get faults in the handler above.
1520  *
1521  * The fault handler will take care of binding the object into the GTT
1522  * (since it may have been evicted to make room for something), allocating
1523  * a fence register, and mapping the appropriate aperture address into
1524  * userspace.
1525  */
1526 int
1527 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1528                         struct drm_file *file)
1529 {
1530         struct drm_i915_gem_mmap_gtt *args = data;
1531
1532         if (!(dev->driver->driver_features & DRIVER_GEM))
1533                 return -ENODEV;
1534
1535         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1536 }
1537
1538
1539 static int
1540 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1541                               gfp_t gfpmask)
1542 {
1543         int page_count, i;
1544         struct address_space *mapping;
1545         struct inode *inode;
1546         struct page *page;
1547
1548         /* Get the list of pages out of our struct file.  They'll be pinned
1549          * at this point until we release them.
1550          */
1551         page_count = obj->base.size / PAGE_SIZE;
1552         BUG_ON(obj->pages != NULL);
1553         obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1554         if (obj->pages == NULL)
1555                 return -ENOMEM;
1556
1557         inode = obj->base.filp->f_path.dentry->d_inode;
1558         mapping = inode->i_mapping;
1559         for (i = 0; i < page_count; i++) {
1560                 page = read_cache_page_gfp(mapping, i,
1561                                            GFP_HIGHUSER |
1562                                            __GFP_COLD |
1563                                            __GFP_RECLAIMABLE |
1564                                            gfpmask);
1565                 if (IS_ERR(page))
1566                         goto err_pages;
1567
1568                 obj->pages[i] = page;
1569         }
1570
1571         if (obj->tiling_mode != I915_TILING_NONE)
1572                 i915_gem_object_do_bit_17_swizzle(obj);
1573
1574         return 0;
1575
1576 err_pages:
1577         while (i--)
1578                 page_cache_release(obj->pages[i]);
1579
1580         drm_free_large(obj->pages);
1581         obj->pages = NULL;
1582         return PTR_ERR(page);
1583 }
1584
1585 static void
1586 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1587 {
1588         int page_count = obj->base.size / PAGE_SIZE;
1589         int i;
1590
1591         BUG_ON(obj->madv == __I915_MADV_PURGED);
1592
1593         if (obj->tiling_mode != I915_TILING_NONE)
1594                 i915_gem_object_save_bit_17_swizzle(obj);
1595
1596         if (obj->madv == I915_MADV_DONTNEED)
1597                 obj->dirty = 0;
1598
1599         for (i = 0; i < page_count; i++) {
1600                 if (obj->dirty)
1601                         set_page_dirty(obj->pages[i]);
1602
1603                 if (obj->madv == I915_MADV_WILLNEED)
1604                         mark_page_accessed(obj->pages[i]);
1605
1606                 page_cache_release(obj->pages[i]);
1607         }
1608         obj->dirty = 0;
1609
1610         drm_free_large(obj->pages);
1611         obj->pages = NULL;
1612 }
1613
1614 void
1615 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1616                                struct intel_ring_buffer *ring,
1617                                u32 seqno)
1618 {
1619         struct drm_device *dev = obj->base.dev;
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621
1622         BUG_ON(ring == NULL);
1623         obj->ring = ring;
1624
1625         /* Add a reference if we're newly entering the active list. */
1626         if (!obj->active) {
1627                 drm_gem_object_reference(&obj->base);
1628                 obj->active = 1;
1629         }
1630
1631         /* Move from whatever list we were on to the tail of execution. */
1632         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1633         list_move_tail(&obj->ring_list, &ring->active_list);
1634
1635         obj->last_rendering_seqno = seqno;
1636         if (obj->fenced_gpu_access) {
1637                 struct drm_i915_fence_reg *reg;
1638
1639                 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1640
1641                 obj->last_fenced_seqno = seqno;
1642                 obj->last_fenced_ring = ring;
1643
1644                 reg = &dev_priv->fence_regs[obj->fence_reg];
1645                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1646         }
1647 }
1648
1649 static void
1650 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1651 {
1652         list_del_init(&obj->ring_list);
1653         obj->last_rendering_seqno = 0;
1654 }
1655
1656 static void
1657 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1658 {
1659         struct drm_device *dev = obj->base.dev;
1660         drm_i915_private_t *dev_priv = dev->dev_private;
1661
1662         BUG_ON(!obj->active);
1663         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1664
1665         i915_gem_object_move_off_active(obj);
1666 }
1667
1668 static void
1669 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1670 {
1671         struct drm_device *dev = obj->base.dev;
1672         struct drm_i915_private *dev_priv = dev->dev_private;
1673
1674         if (obj->pin_count != 0)
1675                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1676         else
1677                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1678
1679         BUG_ON(!list_empty(&obj->gpu_write_list));
1680         BUG_ON(!obj->active);
1681         obj->ring = NULL;
1682
1683         i915_gem_object_move_off_active(obj);
1684         obj->fenced_gpu_access = false;
1685
1686         obj->active = 0;
1687         obj->pending_gpu_write = false;
1688         drm_gem_object_unreference(&obj->base);
1689
1690         WARN_ON(i915_verify_lists(dev));
1691 }
1692
1693 /* Immediately discard the backing storage */
1694 static void
1695 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1696 {
1697         struct inode *inode;
1698
1699         /* Our goal here is to return as much of the memory as
1700          * is possible back to the system as we are called from OOM.
1701          * To do this we must instruct the shmfs to drop all of its
1702          * backing pages, *now*. Here we mirror the actions taken
1703          * when by shmem_delete_inode() to release the backing store.
1704          */
1705         inode = obj->base.filp->f_path.dentry->d_inode;
1706         truncate_inode_pages(inode->i_mapping, 0);
1707         if (inode->i_op->truncate_range)
1708                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1709
1710         obj->madv = __I915_MADV_PURGED;
1711 }
1712
1713 static inline int
1714 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1715 {
1716         return obj->madv == I915_MADV_DONTNEED;
1717 }
1718
1719 static void
1720 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1721                                uint32_t flush_domains)
1722 {
1723         struct drm_i915_gem_object *obj, *next;
1724
1725         list_for_each_entry_safe(obj, next,
1726                                  &ring->gpu_write_list,
1727                                  gpu_write_list) {
1728                 if (obj->base.write_domain & flush_domains) {
1729                         uint32_t old_write_domain = obj->base.write_domain;
1730
1731                         obj->base.write_domain = 0;
1732                         list_del_init(&obj->gpu_write_list);
1733                         i915_gem_object_move_to_active(obj, ring,
1734                                                        i915_gem_next_request_seqno(ring));
1735
1736                         trace_i915_gem_object_change_domain(obj,
1737                                                             obj->base.read_domains,
1738                                                             old_write_domain);
1739                 }
1740         }
1741 }
1742
1743 int
1744 i915_add_request(struct intel_ring_buffer *ring,
1745                  struct drm_file *file,
1746                  struct drm_i915_gem_request *request)
1747 {
1748         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1749         uint32_t seqno;
1750         int was_empty;
1751         int ret;
1752
1753         BUG_ON(request == NULL);
1754
1755         ret = ring->add_request(ring, &seqno);
1756         if (ret)
1757             return ret;
1758
1759         trace_i915_gem_request_add(ring, seqno);
1760
1761         request->seqno = seqno;
1762         request->ring = ring;
1763         request->emitted_jiffies = jiffies;
1764         was_empty = list_empty(&ring->request_list);
1765         list_add_tail(&request->list, &ring->request_list);
1766
1767         if (file) {
1768                 struct drm_i915_file_private *file_priv = file->driver_priv;
1769
1770                 spin_lock(&file_priv->mm.lock);
1771                 request->file_priv = file_priv;
1772                 list_add_tail(&request->client_list,
1773                               &file_priv->mm.request_list);
1774                 spin_unlock(&file_priv->mm.lock);
1775         }
1776
1777         ring->outstanding_lazy_request = false;
1778
1779         if (!dev_priv->mm.suspended) {
1780                 mod_timer(&dev_priv->hangcheck_timer,
1781                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1782                 if (was_empty)
1783                         queue_delayed_work(dev_priv->wq,
1784                                            &dev_priv->mm.retire_work, HZ);
1785         }
1786         return 0;
1787 }
1788
1789 static inline void
1790 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1791 {
1792         struct drm_i915_file_private *file_priv = request->file_priv;
1793
1794         if (!file_priv)
1795                 return;
1796
1797         spin_lock(&file_priv->mm.lock);
1798         if (request->file_priv) {
1799                 list_del(&request->client_list);
1800                 request->file_priv = NULL;
1801         }
1802         spin_unlock(&file_priv->mm.lock);
1803 }
1804
1805 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1806                                       struct intel_ring_buffer *ring)
1807 {
1808         while (!list_empty(&ring->request_list)) {
1809                 struct drm_i915_gem_request *request;
1810
1811                 request = list_first_entry(&ring->request_list,
1812                                            struct drm_i915_gem_request,
1813                                            list);
1814
1815                 list_del(&request->list);
1816                 i915_gem_request_remove_from_client(request);
1817                 kfree(request);
1818         }
1819
1820         while (!list_empty(&ring->active_list)) {
1821                 struct drm_i915_gem_object *obj;
1822
1823                 obj = list_first_entry(&ring->active_list,
1824                                        struct drm_i915_gem_object,
1825                                        ring_list);
1826
1827                 obj->base.write_domain = 0;
1828                 list_del_init(&obj->gpu_write_list);
1829                 i915_gem_object_move_to_inactive(obj);
1830         }
1831 }
1832
1833 static void i915_gem_reset_fences(struct drm_device *dev)
1834 {
1835         struct drm_i915_private *dev_priv = dev->dev_private;
1836         int i;
1837
1838         for (i = 0; i < 16; i++) {
1839                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1840                 struct drm_i915_gem_object *obj = reg->obj;
1841
1842                 if (!obj)
1843                         continue;
1844
1845                 if (obj->tiling_mode)
1846                         i915_gem_release_mmap(obj);
1847
1848                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1849                 reg->obj->fenced_gpu_access = false;
1850                 reg->obj->last_fenced_seqno = 0;
1851                 reg->obj->last_fenced_ring = NULL;
1852                 i915_gem_clear_fence_reg(dev, reg);
1853         }
1854 }
1855
1856 void i915_gem_reset(struct drm_device *dev)
1857 {
1858         struct drm_i915_private *dev_priv = dev->dev_private;
1859         struct drm_i915_gem_object *obj;
1860         int i;
1861
1862         for (i = 0; i < I915_NUM_RINGS; i++)
1863                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1864
1865         /* Remove anything from the flushing lists. The GPU cache is likely
1866          * to be lost on reset along with the data, so simply move the
1867          * lost bo to the inactive list.
1868          */
1869         while (!list_empty(&dev_priv->mm.flushing_list)) {
1870                 obj= list_first_entry(&dev_priv->mm.flushing_list,
1871                                       struct drm_i915_gem_object,
1872                                       mm_list);
1873
1874                 obj->base.write_domain = 0;
1875                 list_del_init(&obj->gpu_write_list);
1876                 i915_gem_object_move_to_inactive(obj);
1877         }
1878
1879         /* Move everything out of the GPU domains to ensure we do any
1880          * necessary invalidation upon reuse.
1881          */
1882         list_for_each_entry(obj,
1883                             &dev_priv->mm.inactive_list,
1884                             mm_list)
1885         {
1886                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1887         }
1888
1889         /* The fence registers are invalidated so clear them out */
1890         i915_gem_reset_fences(dev);
1891 }
1892
1893 /**
1894  * This function clears the request list as sequence numbers are passed.
1895  */
1896 static void
1897 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1898 {
1899         uint32_t seqno;
1900         int i;
1901
1902         if (list_empty(&ring->request_list))
1903                 return;
1904
1905         WARN_ON(i915_verify_lists(ring->dev));
1906
1907         seqno = ring->get_seqno(ring);
1908
1909         for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1910                 if (seqno >= ring->sync_seqno[i])
1911                         ring->sync_seqno[i] = 0;
1912
1913         while (!list_empty(&ring->request_list)) {
1914                 struct drm_i915_gem_request *request;
1915
1916                 request = list_first_entry(&ring->request_list,
1917                                            struct drm_i915_gem_request,
1918                                            list);
1919
1920                 if (!i915_seqno_passed(seqno, request->seqno))
1921                         break;
1922
1923                 trace_i915_gem_request_retire(ring, request->seqno);
1924
1925                 list_del(&request->list);
1926                 i915_gem_request_remove_from_client(request);
1927                 kfree(request);
1928         }
1929
1930         /* Move any buffers on the active list that are no longer referenced
1931          * by the ringbuffer to the flushing/inactive lists as appropriate.
1932          */
1933         while (!list_empty(&ring->active_list)) {
1934                 struct drm_i915_gem_object *obj;
1935
1936                 obj= list_first_entry(&ring->active_list,
1937                                       struct drm_i915_gem_object,
1938                                       ring_list);
1939
1940                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1941                         break;
1942
1943                 if (obj->base.write_domain != 0)
1944                         i915_gem_object_move_to_flushing(obj);
1945                 else
1946                         i915_gem_object_move_to_inactive(obj);
1947         }
1948
1949         if (unlikely(ring->trace_irq_seqno &&
1950                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1951                 ring->irq_put(ring);
1952                 ring->trace_irq_seqno = 0;
1953         }
1954
1955         WARN_ON(i915_verify_lists(ring->dev));
1956 }
1957
1958 void
1959 i915_gem_retire_requests(struct drm_device *dev)
1960 {
1961         drm_i915_private_t *dev_priv = dev->dev_private;
1962         int i;
1963
1964         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1965             struct drm_i915_gem_object *obj, *next;
1966
1967             /* We must be careful that during unbind() we do not
1968              * accidentally infinitely recurse into retire requests.
1969              * Currently:
1970              *   retire -> free -> unbind -> wait -> retire_ring
1971              */
1972             list_for_each_entry_safe(obj, next,
1973                                      &dev_priv->mm.deferred_free_list,
1974                                      mm_list)
1975                     i915_gem_free_object_tail(obj);
1976         }
1977
1978         for (i = 0; i < I915_NUM_RINGS; i++)
1979                 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1980 }
1981
1982 static void
1983 i915_gem_retire_work_handler(struct work_struct *work)
1984 {
1985         drm_i915_private_t *dev_priv;
1986         struct drm_device *dev;
1987         bool idle;
1988         int i;
1989
1990         dev_priv = container_of(work, drm_i915_private_t,
1991                                 mm.retire_work.work);
1992         dev = dev_priv->dev;
1993
1994         /* Come back later if the device is busy... */
1995         if (!mutex_trylock(&dev->struct_mutex)) {
1996                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1997                 return;
1998         }
1999
2000         i915_gem_retire_requests(dev);
2001
2002         /* Send a periodic flush down the ring so we don't hold onto GEM
2003          * objects indefinitely.
2004          */
2005         idle = true;
2006         for (i = 0; i < I915_NUM_RINGS; i++) {
2007                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
2008
2009                 if (!list_empty(&ring->gpu_write_list)) {
2010                         struct drm_i915_gem_request *request;
2011                         int ret;
2012
2013                         ret = i915_gem_flush_ring(ring,
2014                                                   0, I915_GEM_GPU_DOMAINS);
2015                         request = kzalloc(sizeof(*request), GFP_KERNEL);
2016                         if (ret || request == NULL ||
2017                             i915_add_request(ring, NULL, request))
2018                             kfree(request);
2019                 }
2020
2021                 idle &= list_empty(&ring->request_list);
2022         }
2023
2024         if (!dev_priv->mm.suspended && !idle)
2025                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2026
2027         mutex_unlock(&dev->struct_mutex);
2028 }
2029
2030 /**
2031  * Waits for a sequence number to be signaled, and cleans up the
2032  * request and object lists appropriately for that event.
2033  */
2034 int
2035 i915_wait_request(struct intel_ring_buffer *ring,
2036                   uint32_t seqno)
2037 {
2038         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2039         u32 ier;
2040         int ret = 0;
2041
2042         BUG_ON(seqno == 0);
2043
2044         if (atomic_read(&dev_priv->mm.wedged)) {
2045                 struct completion *x = &dev_priv->error_completion;
2046                 bool recovery_complete;
2047                 unsigned long flags;
2048
2049                 /* Give the error handler a chance to run. */
2050                 spin_lock_irqsave(&x->wait.lock, flags);
2051                 recovery_complete = x->done > 0;
2052                 spin_unlock_irqrestore(&x->wait.lock, flags);
2053
2054                 return recovery_complete ? -EIO : -EAGAIN;
2055         }
2056
2057         if (seqno == ring->outstanding_lazy_request) {
2058                 struct drm_i915_gem_request *request;
2059
2060                 request = kzalloc(sizeof(*request), GFP_KERNEL);
2061                 if (request == NULL)
2062                         return -ENOMEM;
2063
2064                 ret = i915_add_request(ring, NULL, request);
2065                 if (ret) {
2066                         kfree(request);
2067                         return ret;
2068                 }
2069
2070                 seqno = request->seqno;
2071         }
2072
2073         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2074                 if (HAS_PCH_SPLIT(ring->dev))
2075                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2076                 else
2077                         ier = I915_READ(IER);
2078                 if (!ier) {
2079                         DRM_ERROR("something (likely vbetool) disabled "
2080                                   "interrupts, re-enabling\n");
2081                         i915_driver_irq_preinstall(ring->dev);
2082                         i915_driver_irq_postinstall(ring->dev);
2083                 }
2084
2085                 trace_i915_gem_request_wait_begin(ring, seqno);
2086
2087                 ring->waiting_seqno = seqno;
2088                 if (ring->irq_get(ring)) {
2089                         if (dev_priv->mm.interruptible)
2090                                 ret = wait_event_interruptible(ring->irq_queue,
2091                                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
2092                                                                || atomic_read(&dev_priv->mm.wedged));
2093                         else
2094                                 wait_event(ring->irq_queue,
2095                                            i915_seqno_passed(ring->get_seqno(ring), seqno)
2096                                            || atomic_read(&dev_priv->mm.wedged));
2097
2098                         ring->irq_put(ring);
2099                 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2100                                                       seqno) ||
2101                                     atomic_read(&dev_priv->mm.wedged), 3000))
2102                         ret = -EBUSY;
2103                 ring->waiting_seqno = 0;
2104
2105                 trace_i915_gem_request_wait_end(ring, seqno);
2106         }
2107         if (atomic_read(&dev_priv->mm.wedged))
2108                 ret = -EAGAIN;
2109
2110         if (ret && ret != -ERESTARTSYS)
2111                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2112                           __func__, ret, seqno, ring->get_seqno(ring),
2113                           dev_priv->next_seqno);
2114
2115         /* Directly dispatch request retiring.  While we have the work queue
2116          * to handle this, the waiter on a request often wants an associated
2117          * buffer to have made it to the inactive list, and we would need
2118          * a separate wait queue to handle that.
2119          */
2120         if (ret == 0)
2121                 i915_gem_retire_requests_ring(ring);
2122
2123         return ret;
2124 }
2125
2126 /**
2127  * Ensures that all rendering to the object has completed and the object is
2128  * safe to unbind from the GTT or access from the CPU.
2129  */
2130 int
2131 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2132 {
2133         int ret;
2134
2135         /* This function only exists to support waiting for existing rendering,
2136          * not for emitting required flushes.
2137          */
2138         BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2139
2140         /* If there is rendering queued on the buffer being evicted, wait for
2141          * it.
2142          */
2143         if (obj->active) {
2144                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2145                 if (ret)
2146                         return ret;
2147         }
2148
2149         return 0;
2150 }
2151
2152 /**
2153  * Unbinds an object from the GTT aperture.
2154  */
2155 int
2156 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2157 {
2158         int ret = 0;
2159
2160         if (obj->gtt_space == NULL)
2161                 return 0;
2162
2163         if (obj->pin_count != 0) {
2164                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2165                 return -EINVAL;
2166         }
2167
2168         /* blow away mappings if mapped through GTT */
2169         i915_gem_release_mmap(obj);
2170
2171         /* Move the object to the CPU domain to ensure that
2172          * any possible CPU writes while it's not in the GTT
2173          * are flushed when we go to remap it. This will
2174          * also ensure that all pending GPU writes are finished
2175          * before we unbind.
2176          */
2177         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2178         if (ret == -ERESTARTSYS)
2179                 return ret;
2180         /* Continue on if we fail due to EIO, the GPU is hung so we
2181          * should be safe and we need to cleanup or else we might
2182          * cause memory corruption through use-after-free.
2183          */
2184         if (ret) {
2185                 i915_gem_clflush_object(obj);
2186                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2187         }
2188
2189         /* release the fence reg _after_ flushing */
2190         ret = i915_gem_object_put_fence(obj);
2191         if (ret == -ERESTARTSYS)
2192                 return ret;
2193
2194         trace_i915_gem_object_unbind(obj);
2195
2196         i915_gem_gtt_unbind_object(obj);
2197         i915_gem_object_put_pages_gtt(obj);
2198
2199         list_del_init(&obj->gtt_list);
2200         list_del_init(&obj->mm_list);
2201         /* Avoid an unnecessary call to unbind on rebind. */
2202         obj->map_and_fenceable = true;
2203
2204         drm_mm_put_block(obj->gtt_space);
2205         obj->gtt_space = NULL;
2206         obj->gtt_offset = 0;
2207
2208         if (i915_gem_object_is_purgeable(obj))
2209                 i915_gem_object_truncate(obj);
2210
2211         return ret;
2212 }
2213
2214 int
2215 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2216                     uint32_t invalidate_domains,
2217                     uint32_t flush_domains)
2218 {
2219         int ret;
2220
2221         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2222                 return 0;
2223
2224         trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2225
2226         ret = ring->flush(ring, invalidate_domains, flush_domains);
2227         if (ret)
2228                 return ret;
2229
2230         if (flush_domains & I915_GEM_GPU_DOMAINS)
2231                 i915_gem_process_flushing_list(ring, flush_domains);
2232
2233         return 0;
2234 }
2235
2236 static int i915_ring_idle(struct intel_ring_buffer *ring)
2237 {
2238         int ret;
2239
2240         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2241                 return 0;
2242
2243         if (!list_empty(&ring->gpu_write_list)) {
2244                 ret = i915_gem_flush_ring(ring,
2245                                     I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2246                 if (ret)
2247                         return ret;
2248         }
2249
2250         return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2251 }
2252
2253 int
2254 i915_gpu_idle(struct drm_device *dev)
2255 {
2256         drm_i915_private_t *dev_priv = dev->dev_private;
2257         bool lists_empty;
2258         int ret, i;
2259
2260         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2261                        list_empty(&dev_priv->mm.active_list));
2262         if (lists_empty)
2263                 return 0;
2264
2265         /* Flush everything onto the inactive list. */
2266         for (i = 0; i < I915_NUM_RINGS; i++) {
2267                 ret = i915_ring_idle(&dev_priv->ring[i]);
2268                 if (ret)
2269                         return ret;
2270         }
2271
2272         return 0;
2273 }
2274
2275 static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2276                                        struct intel_ring_buffer *pipelined)
2277 {
2278         struct drm_device *dev = obj->base.dev;
2279         drm_i915_private_t *dev_priv = dev->dev_private;
2280         u32 size = obj->gtt_space->size;
2281         int regnum = obj->fence_reg;
2282         uint64_t val;
2283
2284         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2285                          0xfffff000) << 32;
2286         val |= obj->gtt_offset & 0xfffff000;
2287         val |= (uint64_t)((obj->stride / 128) - 1) <<
2288                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2289
2290         if (obj->tiling_mode == I915_TILING_Y)
2291                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2292         val |= I965_FENCE_REG_VALID;
2293
2294         if (pipelined) {
2295                 int ret = intel_ring_begin(pipelined, 6);
2296                 if (ret)
2297                         return ret;
2298
2299                 intel_ring_emit(pipelined, MI_NOOP);
2300                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2301                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2302                 intel_ring_emit(pipelined, (u32)val);
2303                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2304                 intel_ring_emit(pipelined, (u32)(val >> 32));
2305                 intel_ring_advance(pipelined);
2306         } else
2307                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2308
2309         return 0;
2310 }
2311
2312 static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2313                                 struct intel_ring_buffer *pipelined)
2314 {
2315         struct drm_device *dev = obj->base.dev;
2316         drm_i915_private_t *dev_priv = dev->dev_private;
2317         u32 size = obj->gtt_space->size;
2318         int regnum = obj->fence_reg;
2319         uint64_t val;
2320
2321         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2322                     0xfffff000) << 32;
2323         val |= obj->gtt_offset & 0xfffff000;
2324         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2325         if (obj->tiling_mode == I915_TILING_Y)
2326                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2327         val |= I965_FENCE_REG_VALID;
2328
2329         if (pipelined) {
2330                 int ret = intel_ring_begin(pipelined, 6);
2331                 if (ret)
2332                         return ret;
2333
2334                 intel_ring_emit(pipelined, MI_NOOP);
2335                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2336                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2337                 intel_ring_emit(pipelined, (u32)val);
2338                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2339                 intel_ring_emit(pipelined, (u32)(val >> 32));
2340                 intel_ring_advance(pipelined);
2341         } else
2342                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2343
2344         return 0;
2345 }
2346
2347 static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2348                                 struct intel_ring_buffer *pipelined)
2349 {
2350         struct drm_device *dev = obj->base.dev;
2351         drm_i915_private_t *dev_priv = dev->dev_private;
2352         u32 size = obj->gtt_space->size;
2353         u32 fence_reg, val, pitch_val;
2354         int tile_width;
2355
2356         if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2357                  (size & -size) != size ||
2358                  (obj->gtt_offset & (size - 1)),
2359                  "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2360                  obj->gtt_offset, obj->map_and_fenceable, size))
2361                 return -EINVAL;
2362
2363         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2364                 tile_width = 128;
2365         else
2366                 tile_width = 512;
2367
2368         /* Note: pitch better be a power of two tile widths */
2369         pitch_val = obj->stride / tile_width;
2370         pitch_val = ffs(pitch_val) - 1;
2371
2372         val = obj->gtt_offset;
2373         if (obj->tiling_mode == I915_TILING_Y)
2374                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2375         val |= I915_FENCE_SIZE_BITS(size);
2376         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2377         val |= I830_FENCE_REG_VALID;
2378
2379         fence_reg = obj->fence_reg;
2380         if (fence_reg < 8)
2381                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2382         else
2383                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2384
2385         if (pipelined) {
2386                 int ret = intel_ring_begin(pipelined, 4);
2387                 if (ret)
2388                         return ret;
2389
2390                 intel_ring_emit(pipelined, MI_NOOP);
2391                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2392                 intel_ring_emit(pipelined, fence_reg);
2393                 intel_ring_emit(pipelined, val);
2394                 intel_ring_advance(pipelined);
2395         } else
2396                 I915_WRITE(fence_reg, val);
2397
2398         return 0;
2399 }
2400
2401 static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2402                                 struct intel_ring_buffer *pipelined)
2403 {
2404         struct drm_device *dev = obj->base.dev;
2405         drm_i915_private_t *dev_priv = dev->dev_private;
2406         u32 size = obj->gtt_space->size;
2407         int regnum = obj->fence_reg;
2408         uint32_t val;
2409         uint32_t pitch_val;
2410
2411         if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2412                  (size & -size) != size ||
2413                  (obj->gtt_offset & (size - 1)),
2414                  "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2415                  obj->gtt_offset, size))
2416                 return -EINVAL;
2417
2418         pitch_val = obj->stride / 128;
2419         pitch_val = ffs(pitch_val) - 1;
2420
2421         val = obj->gtt_offset;
2422         if (obj->tiling_mode == I915_TILING_Y)
2423                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2424         val |= I830_FENCE_SIZE_BITS(size);
2425         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2426         val |= I830_FENCE_REG_VALID;
2427
2428         if (pipelined) {
2429                 int ret = intel_ring_begin(pipelined, 4);
2430                 if (ret)
2431                         return ret;
2432
2433                 intel_ring_emit(pipelined, MI_NOOP);
2434                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2435                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2436                 intel_ring_emit(pipelined, val);
2437                 intel_ring_advance(pipelined);
2438         } else
2439                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2440
2441         return 0;
2442 }
2443
2444 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2445 {
2446         return i915_seqno_passed(ring->get_seqno(ring), seqno);
2447 }
2448
2449 static int
2450 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2451                             struct intel_ring_buffer *pipelined)
2452 {
2453         int ret;
2454
2455         if (obj->fenced_gpu_access) {
2456                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2457                         ret = i915_gem_flush_ring(obj->last_fenced_ring,
2458                                                   0, obj->base.write_domain);
2459                         if (ret)
2460                                 return ret;
2461                 }
2462
2463                 obj->fenced_gpu_access = false;
2464         }
2465
2466         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2467                 if (!ring_passed_seqno(obj->last_fenced_ring,
2468                                        obj->last_fenced_seqno)) {
2469                         ret = i915_wait_request(obj->last_fenced_ring,
2470                                                 obj->last_fenced_seqno);
2471                         if (ret)
2472                                 return ret;
2473                 }
2474
2475                 obj->last_fenced_seqno = 0;
2476                 obj->last_fenced_ring = NULL;
2477         }
2478
2479         /* Ensure that all CPU reads are completed before installing a fence
2480          * and all writes before removing the fence.
2481          */
2482         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2483                 mb();
2484
2485         return 0;
2486 }
2487
2488 int
2489 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2490 {
2491         int ret;
2492
2493         if (obj->tiling_mode)
2494                 i915_gem_release_mmap(obj);
2495
2496         ret = i915_gem_object_flush_fence(obj, NULL);
2497         if (ret)
2498                 return ret;
2499
2500         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2501                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2502                 i915_gem_clear_fence_reg(obj->base.dev,
2503                                          &dev_priv->fence_regs[obj->fence_reg]);
2504
2505                 obj->fence_reg = I915_FENCE_REG_NONE;
2506         }
2507
2508         return 0;
2509 }
2510
2511 static struct drm_i915_fence_reg *
2512 i915_find_fence_reg(struct drm_device *dev,
2513                     struct intel_ring_buffer *pipelined)
2514 {
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct drm_i915_fence_reg *reg, *first, *avail;
2517         int i;
2518
2519         /* First try to find a free reg */
2520         avail = NULL;
2521         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2522                 reg = &dev_priv->fence_regs[i];
2523                 if (!reg->obj)
2524                         return reg;
2525
2526                 if (!reg->obj->pin_count)
2527                         avail = reg;
2528         }
2529
2530         if (avail == NULL)
2531                 return NULL;
2532
2533         /* None available, try to steal one or wait for a user to finish */
2534         avail = first = NULL;
2535         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2536                 if (reg->obj->pin_count)
2537                         continue;
2538
2539                 if (first == NULL)
2540                         first = reg;
2541
2542                 if (!pipelined ||
2543                     !reg->obj->last_fenced_ring ||
2544                     reg->obj->last_fenced_ring == pipelined) {
2545                         avail = reg;
2546                         break;
2547                 }
2548         }
2549
2550         if (avail == NULL)
2551                 avail = first;
2552
2553         return avail;
2554 }
2555
2556 /**
2557  * i915_gem_object_get_fence - set up a fence reg for an object
2558  * @obj: object to map through a fence reg
2559  * @pipelined: ring on which to queue the change, or NULL for CPU access
2560  * @interruptible: must we wait uninterruptibly for the register to retire?
2561  *
2562  * When mapping objects through the GTT, userspace wants to be able to write
2563  * to them without having to worry about swizzling if the object is tiled.
2564  *
2565  * This function walks the fence regs looking for a free one for @obj,
2566  * stealing one if it can't find any.
2567  *
2568  * It then sets up the reg based on the object's properties: address, pitch
2569  * and tiling format.
2570  */
2571 int
2572 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2573                           struct intel_ring_buffer *pipelined)
2574 {
2575         struct drm_device *dev = obj->base.dev;
2576         struct drm_i915_private *dev_priv = dev->dev_private;
2577         struct drm_i915_fence_reg *reg;
2578         int ret;
2579
2580         /* XXX disable pipelining. There are bugs. Shocking. */
2581         pipelined = NULL;
2582
2583         /* Just update our place in the LRU if our fence is getting reused. */
2584         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2585                 reg = &dev_priv->fence_regs[obj->fence_reg];
2586                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2587
2588                 if (obj->tiling_changed) {
2589                         ret = i915_gem_object_flush_fence(obj, pipelined);
2590                         if (ret)
2591                                 return ret;
2592
2593                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2594                                 pipelined = NULL;
2595
2596                         if (pipelined) {
2597                                 reg->setup_seqno =
2598                                         i915_gem_next_request_seqno(pipelined);
2599                                 obj->last_fenced_seqno = reg->setup_seqno;
2600                                 obj->last_fenced_ring = pipelined;
2601                         }
2602
2603                         goto update;
2604                 }
2605
2606                 if (!pipelined) {
2607                         if (reg->setup_seqno) {
2608                                 if (!ring_passed_seqno(obj->last_fenced_ring,
2609                                                        reg->setup_seqno)) {
2610                                         ret = i915_wait_request(obj->last_fenced_ring,
2611                                                                 reg->setup_seqno);
2612                                         if (ret)
2613                                                 return ret;
2614                                 }
2615
2616                                 reg->setup_seqno = 0;
2617                         }
2618                 } else if (obj->last_fenced_ring &&
2619                            obj->last_fenced_ring != pipelined) {
2620                         ret = i915_gem_object_flush_fence(obj, pipelined);
2621                         if (ret)
2622                                 return ret;
2623                 }
2624
2625                 return 0;
2626         }
2627
2628         reg = i915_find_fence_reg(dev, pipelined);
2629         if (reg == NULL)
2630                 return -ENOSPC;
2631
2632         ret = i915_gem_object_flush_fence(obj, pipelined);
2633         if (ret)
2634                 return ret;
2635
2636         if (reg->obj) {
2637                 struct drm_i915_gem_object *old = reg->obj;
2638
2639                 drm_gem_object_reference(&old->base);
2640
2641                 if (old->tiling_mode)
2642                         i915_gem_release_mmap(old);
2643
2644                 ret = i915_gem_object_flush_fence(old, pipelined);
2645                 if (ret) {
2646                         drm_gem_object_unreference(&old->base);
2647                         return ret;
2648                 }
2649
2650                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2651                         pipelined = NULL;
2652
2653                 old->fence_reg = I915_FENCE_REG_NONE;
2654                 old->last_fenced_ring = pipelined;
2655                 old->last_fenced_seqno =
2656                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2657
2658                 drm_gem_object_unreference(&old->base);
2659         } else if (obj->last_fenced_seqno == 0)
2660                 pipelined = NULL;
2661
2662         reg->obj = obj;
2663         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2664         obj->fence_reg = reg - dev_priv->fence_regs;
2665         obj->last_fenced_ring = pipelined;
2666
2667         reg->setup_seqno =
2668                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2669         obj->last_fenced_seqno = reg->setup_seqno;
2670
2671 update:
2672         obj->tiling_changed = false;
2673         switch (INTEL_INFO(dev)->gen) {
2674         case 7:
2675         case 6:
2676                 ret = sandybridge_write_fence_reg(obj, pipelined);
2677                 break;
2678         case 5:
2679         case 4:
2680                 ret = i965_write_fence_reg(obj, pipelined);
2681                 break;
2682         case 3:
2683                 ret = i915_write_fence_reg(obj, pipelined);
2684                 break;
2685         case 2:
2686                 ret = i830_write_fence_reg(obj, pipelined);
2687                 break;
2688         }
2689
2690         return ret;
2691 }
2692
2693 /**
2694  * i915_gem_clear_fence_reg - clear out fence register info
2695  * @obj: object to clear
2696  *
2697  * Zeroes out the fence register itself and clears out the associated
2698  * data structures in dev_priv and obj.
2699  */
2700 static void
2701 i915_gem_clear_fence_reg(struct drm_device *dev,
2702                          struct drm_i915_fence_reg *reg)
2703 {
2704         drm_i915_private_t *dev_priv = dev->dev_private;
2705         uint32_t fence_reg = reg - dev_priv->fence_regs;
2706
2707         switch (INTEL_INFO(dev)->gen) {
2708         case 7:
2709         case 6:
2710                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2711                 break;
2712         case 5:
2713         case 4:
2714                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2715                 break;
2716         case 3:
2717                 if (fence_reg >= 8)
2718                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2719                 else
2720         case 2:
2721                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2722
2723                 I915_WRITE(fence_reg, 0);
2724                 break;
2725         }
2726
2727         list_del_init(&reg->lru_list);
2728         reg->obj = NULL;
2729         reg->setup_seqno = 0;
2730 }
2731
2732 /**
2733  * Finds free space in the GTT aperture and binds the object there.
2734  */
2735 static int
2736 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2737                             unsigned alignment,
2738                             bool map_and_fenceable)
2739 {
2740         struct drm_device *dev = obj->base.dev;
2741         drm_i915_private_t *dev_priv = dev->dev_private;
2742         struct drm_mm_node *free_space;
2743         gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2744         u32 size, fence_size, fence_alignment, unfenced_alignment;
2745         bool mappable, fenceable;
2746         int ret;
2747
2748         if (obj->madv != I915_MADV_WILLNEED) {
2749                 DRM_ERROR("Attempting to bind a purgeable object\n");
2750                 return -EINVAL;
2751         }
2752
2753         fence_size = i915_gem_get_gtt_size(obj);
2754         fence_alignment = i915_gem_get_gtt_alignment(obj);
2755         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
2756
2757         if (alignment == 0)
2758                 alignment = map_and_fenceable ? fence_alignment :
2759                                                 unfenced_alignment;
2760         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2761                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2762                 return -EINVAL;
2763         }
2764
2765         size = map_and_fenceable ? fence_size : obj->base.size;
2766
2767         /* If the object is bigger than the entire aperture, reject it early
2768          * before evicting everything in a vain attempt to find space.
2769          */
2770         if (obj->base.size >
2771             (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2772                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2773                 return -E2BIG;
2774         }
2775
2776  search_free:
2777         if (map_and_fenceable)
2778                 free_space =
2779                         drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2780                                                     size, alignment, 0,
2781                                                     dev_priv->mm.gtt_mappable_end,
2782                                                     0);
2783         else
2784                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2785                                                 size, alignment, 0);
2786
2787         if (free_space != NULL) {
2788                 if (map_and_fenceable)
2789                         obj->gtt_space =
2790                                 drm_mm_get_block_range_generic(free_space,
2791                                                                size, alignment, 0,
2792                                                                dev_priv->mm.gtt_mappable_end,
2793                                                                0);
2794                 else
2795                         obj->gtt_space =
2796                                 drm_mm_get_block(free_space, size, alignment);
2797         }
2798         if (obj->gtt_space == NULL) {
2799                 /* If the gtt is empty and we're still having trouble
2800                  * fitting our object in, we're out of memory.
2801                  */
2802                 ret = i915_gem_evict_something(dev, size, alignment,
2803                                                map_and_fenceable);
2804                 if (ret)
2805                         return ret;
2806
2807                 goto search_free;
2808         }
2809
2810         ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2811         if (ret) {
2812                 drm_mm_put_block(obj->gtt_space);
2813                 obj->gtt_space = NULL;
2814
2815                 if (ret == -ENOMEM) {
2816                         /* first try to reclaim some memory by clearing the GTT */
2817                         ret = i915_gem_evict_everything(dev, false);
2818                         if (ret) {
2819                                 /* now try to shrink everyone else */
2820                                 if (gfpmask) {
2821                                         gfpmask = 0;
2822                                         goto search_free;
2823                                 }
2824
2825                                 return -ENOMEM;
2826                         }
2827
2828                         goto search_free;
2829                 }
2830
2831                 return ret;
2832         }
2833
2834         ret = i915_gem_gtt_bind_object(obj);
2835         if (ret) {
2836                 i915_gem_object_put_pages_gtt(obj);
2837                 drm_mm_put_block(obj->gtt_space);
2838                 obj->gtt_space = NULL;
2839
2840                 if (i915_gem_evict_everything(dev, false))
2841                         return ret;
2842
2843                 goto search_free;
2844         }
2845
2846         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2847         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2848
2849         /* Assert that the object is not currently in any GPU domain. As it
2850          * wasn't in the GTT, there shouldn't be any way it could have been in
2851          * a GPU cache
2852          */
2853         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2854         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2855
2856         obj->gtt_offset = obj->gtt_space->start;
2857
2858         fenceable =
2859                 obj->gtt_space->size == fence_size &&
2860                 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2861
2862         mappable =
2863                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2864
2865         obj->map_and_fenceable = mappable && fenceable;
2866
2867         trace_i915_gem_object_bind(obj, map_and_fenceable);
2868         return 0;
2869 }
2870
2871 void
2872 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2873 {
2874         /* If we don't have a page list set up, then we're not pinned
2875          * to GPU, and we can ignore the cache flush because it'll happen
2876          * again at bind time.
2877          */
2878         if (obj->pages == NULL)
2879                 return;
2880
2881         /* If the GPU is snooping the contents of the CPU cache,
2882          * we do not need to manually clear the CPU cache lines.  However,
2883          * the caches are only snooped when the render cache is
2884          * flushed/invalidated.  As we always have to emit invalidations
2885          * and flushes when moving into and out of the RENDER domain, correct
2886          * snooping behaviour occurs naturally as the result of our domain
2887          * tracking.
2888          */
2889         if (obj->cache_level != I915_CACHE_NONE)
2890                 return;
2891
2892         trace_i915_gem_object_clflush(obj);
2893
2894         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2895 }
2896
2897 /** Flushes any GPU write domain for the object if it's dirty. */
2898 static int
2899 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2900 {
2901         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2902                 return 0;
2903
2904         /* Queue the GPU write cache flushing we need. */
2905         return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2906 }
2907
2908 /** Flushes the GTT write domain for the object if it's dirty. */
2909 static void
2910 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2911 {
2912         uint32_t old_write_domain;
2913
2914         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2915                 return;
2916
2917         /* No actual flushing is required for the GTT write domain.  Writes
2918          * to it immediately go to main memory as far as we know, so there's
2919          * no chipset flush.  It also doesn't land in render cache.
2920          *
2921          * However, we do have to enforce the order so that all writes through
2922          * the GTT land before any writes to the device, such as updates to
2923          * the GATT itself.
2924          */
2925         wmb();
2926
2927         i915_gem_release_mmap(obj);
2928
2929         old_write_domain = obj->base.write_domain;
2930         obj->base.write_domain = 0;
2931
2932         trace_i915_gem_object_change_domain(obj,
2933                                             obj->base.read_domains,
2934                                             old_write_domain);
2935 }
2936
2937 /** Flushes the CPU write domain for the object if it's dirty. */
2938 static void
2939 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2940 {
2941         uint32_t old_write_domain;
2942
2943         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2944                 return;
2945
2946         i915_gem_clflush_object(obj);
2947         intel_gtt_chipset_flush();
2948         old_write_domain = obj->base.write_domain;
2949         obj->base.write_domain = 0;
2950
2951         trace_i915_gem_object_change_domain(obj,
2952                                             obj->base.read_domains,
2953                                             old_write_domain);
2954 }
2955
2956 /**
2957  * Moves a single object to the GTT read, and possibly write domain.
2958  *
2959  * This function returns when the move is complete, including waiting on
2960  * flushes to occur.
2961  */
2962 int
2963 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2964 {
2965         uint32_t old_write_domain, old_read_domains;
2966         int ret;
2967
2968         /* Not valid to be called on unbound objects. */
2969         if (obj->gtt_space == NULL)
2970                 return -EINVAL;
2971
2972         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2973                 return 0;
2974
2975         ret = i915_gem_object_flush_gpu_write_domain(obj);
2976         if (ret)
2977                 return ret;
2978
2979         if (obj->pending_gpu_write || write) {
2980                 ret = i915_gem_object_wait_rendering(obj);
2981                 if (ret)
2982                         return ret;
2983         }
2984
2985         i915_gem_object_flush_cpu_write_domain(obj);
2986
2987         old_write_domain = obj->base.write_domain;
2988         old_read_domains = obj->base.read_domains;
2989
2990         /* It should now be out of any other write domains, and we can update
2991          * the domain values for our changes.
2992          */
2993         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2994         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2995         if (write) {
2996                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2997                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2998                 obj->dirty = 1;
2999         }
3000
3001         trace_i915_gem_object_change_domain(obj,
3002                                             old_read_domains,
3003                                             old_write_domain);
3004
3005         return 0;
3006 }
3007
3008 /*
3009  * Prepare buffer for display plane. Use uninterruptible for possible flush
3010  * wait, as in modesetting process we're not supposed to be interrupted.
3011  */
3012 int
3013 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
3014                                      struct intel_ring_buffer *pipelined)
3015 {
3016         uint32_t old_read_domains;
3017         int ret;
3018
3019         /* Not valid to be called on unbound objects. */
3020         if (obj->gtt_space == NULL)
3021                 return -EINVAL;
3022
3023         ret = i915_gem_object_flush_gpu_write_domain(obj);
3024         if (ret)
3025                 return ret;
3026
3027
3028         /* Currently, we are always called from an non-interruptible context. */
3029         if (pipelined != obj->ring) {
3030                 ret = i915_gem_object_wait_rendering(obj);
3031                 if (ret)
3032                         return ret;
3033         }
3034
3035         i915_gem_object_flush_cpu_write_domain(obj);
3036
3037         old_read_domains = obj->base.read_domains;
3038         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3039
3040         trace_i915_gem_object_change_domain(obj,
3041                                             old_read_domains,
3042                                             obj->base.write_domain);
3043
3044         return 0;
3045 }
3046
3047 int
3048 i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj)
3049 {
3050         int ret;
3051
3052         if (!obj->active)
3053                 return 0;
3054
3055         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3056                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3057                 if (ret)
3058                         return ret;
3059         }
3060
3061         return i915_gem_object_wait_rendering(obj);
3062 }
3063
3064 /**
3065  * Moves a single object to the CPU read, and possibly write domain.
3066  *
3067  * This function returns when the move is complete, including waiting on
3068  * flushes to occur.
3069  */
3070 static int
3071 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3072 {
3073         uint32_t old_write_domain, old_read_domains;
3074         int ret;
3075
3076         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3077                 return 0;
3078
3079         ret = i915_gem_object_flush_gpu_write_domain(obj);
3080         if (ret)
3081                 return ret;
3082
3083         ret = i915_gem_object_wait_rendering(obj);
3084         if (ret)
3085                 return ret;
3086
3087         i915_gem_object_flush_gtt_write_domain(obj);
3088
3089         /* If we have a partially-valid cache of the object in the CPU,
3090          * finish invalidating it and free the per-page flags.
3091          */
3092         i915_gem_object_set_to_full_cpu_read_domain(obj);
3093
3094         old_write_domain = obj->base.write_domain;
3095         old_read_domains = obj->base.read_domains;
3096
3097         /* Flush the CPU cache if it's still invalid. */
3098         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3099                 i915_gem_clflush_object(obj);
3100
3101                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3102         }
3103
3104         /* It should now be out of any other write domains, and we can update
3105          * the domain values for our changes.
3106          */
3107         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3108
3109         /* If we're writing through the CPU, then the GPU read domains will
3110          * need to be invalidated at next use.
3111          */
3112         if (write) {
3113                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3114                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3115         }
3116
3117         trace_i915_gem_object_change_domain(obj,
3118                                             old_read_domains,
3119                                             old_write_domain);
3120
3121         return 0;
3122 }
3123
3124 /**
3125  * Moves the object from a partially CPU read to a full one.
3126  *
3127  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3128  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3129  */
3130 static void
3131 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3132 {
3133         if (!obj->page_cpu_valid)
3134                 return;
3135
3136         /* If we're partially in the CPU read domain, finish moving it in.
3137          */
3138         if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3139                 int i;
3140
3141                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3142                         if (obj->page_cpu_valid[i])
3143                                 continue;
3144                         drm_clflush_pages(obj->pages + i, 1);
3145                 }
3146         }
3147
3148         /* Free the page_cpu_valid mappings which are now stale, whether
3149          * or not we've got I915_GEM_DOMAIN_CPU.
3150          */
3151         kfree(obj->page_cpu_valid);
3152         obj->page_cpu_valid = NULL;
3153 }
3154
3155 /**
3156  * Set the CPU read domain on a range of the object.
3157  *
3158  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3159  * not entirely valid.  The page_cpu_valid member of the object flags which
3160  * pages have been flushed, and will be respected by
3161  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3162  * of the whole object.
3163  *
3164  * This function returns when the move is complete, including waiting on
3165  * flushes to occur.
3166  */
3167 static int
3168 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3169                                           uint64_t offset, uint64_t size)
3170 {
3171         uint32_t old_read_domains;
3172         int i, ret;
3173
3174         if (offset == 0 && size == obj->base.size)
3175                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3176
3177         ret = i915_gem_object_flush_gpu_write_domain(obj);
3178         if (ret)
3179                 return ret;
3180
3181         ret = i915_gem_object_wait_rendering(obj);
3182         if (ret)
3183                 return ret;
3184
3185         i915_gem_object_flush_gtt_write_domain(obj);
3186
3187         /* If we're already fully in the CPU read domain, we're done. */
3188         if (obj->page_cpu_valid == NULL &&
3189             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3190                 return 0;
3191
3192         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3193          * newly adding I915_GEM_DOMAIN_CPU
3194          */
3195         if (obj->page_cpu_valid == NULL) {
3196                 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3197                                               GFP_KERNEL);
3198                 if (obj->page_cpu_valid == NULL)
3199                         return -ENOMEM;
3200         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3201                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3202
3203         /* Flush the cache on any pages that are still invalid from the CPU's
3204          * perspective.
3205          */
3206         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3207              i++) {
3208                 if (obj->page_cpu_valid[i])
3209                         continue;
3210
3211                 drm_clflush_pages(obj->pages + i, 1);
3212
3213                 obj->page_cpu_valid[i] = 1;
3214         }
3215
3216         /* It should now be out of any other write domains, and we can update
3217          * the domain values for our changes.
3218          */
3219         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3220
3221         old_read_domains = obj->base.read_domains;
3222         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3223
3224         trace_i915_gem_object_change_domain(obj,
3225                                             old_read_domains,
3226                                             obj->base.write_domain);
3227
3228         return 0;
3229 }
3230
3231 /* Throttle our rendering by waiting until the ring has completed our requests
3232  * emitted over 20 msec ago.
3233  *
3234  * Note that if we were to use the current jiffies each time around the loop,
3235  * we wouldn't escape the function with any frames outstanding if the time to
3236  * render a frame was over 20ms.
3237  *
3238  * This should get us reasonable parallelism between CPU and GPU but also
3239  * relatively low latency when blocking on a particular request to finish.
3240  */
3241 static int
3242 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3243 {
3244         struct drm_i915_private *dev_priv = dev->dev_private;
3245         struct drm_i915_file_private *file_priv = file->driver_priv;
3246         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3247         struct drm_i915_gem_request *request;
3248         struct intel_ring_buffer *ring = NULL;
3249         u32 seqno = 0;
3250         int ret;
3251
3252         if (atomic_read(&dev_priv->mm.wedged))
3253                 return -EIO;
3254
3255         spin_lock(&file_priv->mm.lock);
3256         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3257                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3258                         break;
3259
3260                 ring = request->ring;
3261                 seqno = request->seqno;
3262         }
3263         spin_unlock(&file_priv->mm.lock);
3264
3265         if (seqno == 0)
3266                 return 0;
3267
3268         ret = 0;
3269         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3270                 /* And wait for the seqno passing without holding any locks and
3271                  * causing extra latency for others. This is safe as the irq
3272                  * generation is designed to be run atomically and so is
3273                  * lockless.
3274                  */
3275                 if (ring->irq_get(ring)) {
3276                         ret = wait_event_interruptible(ring->irq_queue,
3277                                                        i915_seqno_passed(ring->get_seqno(ring), seqno)
3278                                                        || atomic_read(&dev_priv->mm.wedged));
3279                         ring->irq_put(ring);
3280
3281                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3282                                 ret = -EIO;
3283                 }
3284         }
3285
3286         if (ret == 0)
3287                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3288
3289         return ret;
3290 }
3291
3292 int
3293 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3294                     uint32_t alignment,
3295                     bool map_and_fenceable)
3296 {
3297         struct drm_device *dev = obj->base.dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         int ret;
3300
3301         BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3302         WARN_ON(i915_verify_lists(dev));
3303
3304         if (obj->gtt_space != NULL) {
3305                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3306                     (map_and_fenceable && !obj->map_and_fenceable)) {
3307                         WARN(obj->pin_count,
3308                              "bo is already pinned with incorrect alignment:"
3309                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3310                              " obj->map_and_fenceable=%d\n",
3311                              obj->gtt_offset, alignment,
3312                              map_and_fenceable,
3313                              obj->map_and_fenceable);
3314                         ret = i915_gem_object_unbind(obj);
3315                         if (ret)
3316                                 return ret;
3317                 }
3318         }
3319
3320         if (obj->gtt_space == NULL) {
3321                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3322                                                   map_and_fenceable);
3323                 if (ret)
3324                         return ret;
3325         }
3326
3327         if (obj->pin_count++ == 0) {
3328                 if (!obj->active)
3329                         list_move_tail(&obj->mm_list,
3330                                        &dev_priv->mm.pinned_list);
3331         }
3332         obj->pin_mappable |= map_and_fenceable;
3333
3334         WARN_ON(i915_verify_lists(dev));
3335         return 0;
3336 }
3337
3338 void
3339 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3340 {
3341         struct drm_device *dev = obj->base.dev;
3342         drm_i915_private_t *dev_priv = dev->dev_private;
3343
3344         WARN_ON(i915_verify_lists(dev));
3345         BUG_ON(obj->pin_count == 0);
3346         BUG_ON(obj->gtt_space == NULL);
3347
3348         if (--obj->pin_count == 0) {
3349                 if (!obj->active)
3350                         list_move_tail(&obj->mm_list,
3351                                        &dev_priv->mm.inactive_list);
3352                 obj->pin_mappable = false;
3353         }
3354         WARN_ON(i915_verify_lists(dev));
3355 }
3356
3357 int
3358 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3359                    struct drm_file *file)
3360 {
3361         struct drm_i915_gem_pin *args = data;
3362         struct drm_i915_gem_object *obj;
3363         int ret;
3364
3365         ret = i915_mutex_lock_interruptible(dev);
3366         if (ret)
3367                 return ret;
3368
3369         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3370         if (&obj->base == NULL) {
3371                 ret = -ENOENT;
3372                 goto unlock;
3373         }
3374
3375         if (obj->madv != I915_MADV_WILLNEED) {
3376                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3377                 ret = -EINVAL;
3378                 goto out;
3379         }
3380
3381         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3382                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3383                           args->handle);
3384                 ret = -EINVAL;
3385                 goto out;
3386         }
3387
3388         obj->user_pin_count++;
3389         obj->pin_filp = file;
3390         if (obj->user_pin_count == 1) {
3391                 ret = i915_gem_object_pin(obj, args->alignment, true);
3392                 if (ret)
3393                         goto out;
3394         }
3395
3396         /* XXX - flush the CPU caches for pinned objects
3397          * as the X server doesn't manage domains yet
3398          */
3399         i915_gem_object_flush_cpu_write_domain(obj);
3400         args->offset = obj->gtt_offset;
3401 out:
3402         drm_gem_object_unreference(&obj->base);
3403 unlock:
3404         mutex_unlock(&dev->struct_mutex);
3405         return ret;
3406 }
3407
3408 int
3409 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3410                      struct drm_file *file)
3411 {
3412         struct drm_i915_gem_pin *args = data;
3413         struct drm_i915_gem_object *obj;
3414         int ret;
3415
3416         ret = i915_mutex_lock_interruptible(dev);
3417         if (ret)
3418                 return ret;
3419
3420         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3421         if (&obj->base == NULL) {
3422                 ret = -ENOENT;
3423                 goto unlock;
3424         }
3425
3426         if (obj->pin_filp != file) {
3427                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3428                           args->handle);
3429                 ret = -EINVAL;
3430                 goto out;
3431         }
3432         obj->user_pin_count--;
3433         if (obj->user_pin_count == 0) {
3434                 obj->pin_filp = NULL;
3435                 i915_gem_object_unpin(obj);
3436         }
3437
3438 out:
3439         drm_gem_object_unreference(&obj->base);
3440 unlock:
3441         mutex_unlock(&dev->struct_mutex);
3442         return ret;
3443 }
3444
3445 int
3446 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3447                     struct drm_file *file)
3448 {
3449         struct drm_i915_gem_busy *args = data;
3450         struct drm_i915_gem_object *obj;
3451         int ret;
3452
3453         ret = i915_mutex_lock_interruptible(dev);
3454         if (ret)
3455                 return ret;
3456
3457         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3458         if (&obj->base == NULL) {
3459                 ret = -ENOENT;
3460                 goto unlock;
3461         }
3462
3463         /* Count all active objects as busy, even if they are currently not used
3464          * by the gpu. Users of this interface expect objects to eventually
3465          * become non-busy without any further actions, therefore emit any
3466          * necessary flushes here.
3467          */
3468         args->busy = obj->active;
3469         if (args->busy) {
3470                 /* Unconditionally flush objects, even when the gpu still uses this
3471                  * object. Userspace calling this function indicates that it wants to
3472                  * use this buffer rather sooner than later, so issuing the required
3473                  * flush earlier is beneficial.
3474                  */
3475                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3476                         ret = i915_gem_flush_ring(obj->ring,
3477                                                   0, obj->base.write_domain);
3478                 } else if (obj->ring->outstanding_lazy_request ==
3479                            obj->last_rendering_seqno) {
3480                         struct drm_i915_gem_request *request;
3481
3482                         /* This ring is not being cleared by active usage,
3483                          * so emit a request to do so.
3484                          */
3485                         request = kzalloc(sizeof(*request), GFP_KERNEL);
3486                         if (request)
3487                                 ret = i915_add_request(obj->ring, NULL,request);
3488                         else
3489                                 ret = -ENOMEM;
3490                 }
3491
3492                 /* Update the active list for the hardware's current position.
3493                  * Otherwise this only updates on a delayed timer or when irqs
3494                  * are actually unmasked, and our working set ends up being
3495                  * larger than required.
3496                  */
3497                 i915_gem_retire_requests_ring(obj->ring);
3498
3499                 args->busy = obj->active;
3500         }
3501
3502         drm_gem_object_unreference(&obj->base);
3503 unlock:
3504         mutex_unlock(&dev->struct_mutex);
3505         return ret;
3506 }
3507
3508 int
3509 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3510                         struct drm_file *file_priv)
3511 {
3512     return i915_gem_ring_throttle(dev, file_priv);
3513 }
3514
3515 int
3516 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3517                        struct drm_file *file_priv)
3518 {
3519         struct drm_i915_gem_madvise *args = data;
3520         struct drm_i915_gem_object *obj;
3521         int ret;
3522
3523         switch (args->madv) {
3524         case I915_MADV_DONTNEED:
3525         case I915_MADV_WILLNEED:
3526             break;
3527         default:
3528             return -EINVAL;
3529         }
3530
3531         ret = i915_mutex_lock_interruptible(dev);
3532         if (ret)
3533                 return ret;
3534
3535         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3536         if (&obj->base == NULL) {
3537                 ret = -ENOENT;
3538                 goto unlock;
3539         }
3540
3541         if (obj->pin_count) {
3542                 ret = -EINVAL;
3543                 goto out;
3544         }
3545
3546         if (obj->madv != __I915_MADV_PURGED)
3547                 obj->madv = args->madv;
3548
3549         /* if the object is no longer bound, discard its backing storage */
3550         if (i915_gem_object_is_purgeable(obj) &&
3551             obj->gtt_space == NULL)
3552                 i915_gem_object_truncate(obj);
3553
3554         args->retained = obj->madv != __I915_MADV_PURGED;
3555
3556 out:
3557         drm_gem_object_unreference(&obj->base);
3558 unlock:
3559         mutex_unlock(&dev->struct_mutex);
3560         return ret;
3561 }
3562
3563 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3564                                                   size_t size)
3565 {
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         struct drm_i915_gem_object *obj;
3568
3569         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3570         if (obj == NULL)
3571                 return NULL;
3572
3573         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3574                 kfree(obj);
3575                 return NULL;
3576         }
3577
3578         i915_gem_info_add_obj(dev_priv, size);
3579
3580         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3581         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3582
3583         obj->cache_level = I915_CACHE_NONE;
3584         obj->base.driver_private = NULL;
3585         obj->fence_reg = I915_FENCE_REG_NONE;
3586         INIT_LIST_HEAD(&obj->mm_list);
3587         INIT_LIST_HEAD(&obj->gtt_list);
3588         INIT_LIST_HEAD(&obj->ring_list);
3589         INIT_LIST_HEAD(&obj->exec_list);
3590         INIT_LIST_HEAD(&obj->gpu_write_list);
3591         obj->madv = I915_MADV_WILLNEED;
3592         /* Avoid an unnecessary call to unbind on the first bind. */
3593         obj->map_and_fenceable = true;
3594
3595         return obj;
3596 }
3597
3598 int i915_gem_init_object(struct drm_gem_object *obj)
3599 {
3600         BUG();
3601
3602         return 0;
3603 }
3604
3605 static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3606 {
3607         struct drm_device *dev = obj->base.dev;
3608         drm_i915_private_t *dev_priv = dev->dev_private;
3609         int ret;
3610
3611         ret = i915_gem_object_unbind(obj);
3612         if (ret == -ERESTARTSYS) {
3613                 list_move(&obj->mm_list,
3614                           &dev_priv->mm.deferred_free_list);
3615                 return;
3616         }
3617
3618         trace_i915_gem_object_destroy(obj);
3619
3620         if (obj->base.map_list.map)
3621                 i915_gem_free_mmap_offset(obj);
3622
3623         drm_gem_object_release(&obj->base);
3624         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3625
3626         kfree(obj->page_cpu_valid);
3627         kfree(obj->bit_17);
3628         kfree(obj);
3629 }
3630
3631 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3632 {
3633         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3634         struct drm_device *dev = obj->base.dev;
3635
3636         while (obj->pin_count > 0)
3637                 i915_gem_object_unpin(obj);
3638
3639         if (obj->phys_obj)
3640                 i915_gem_detach_phys_object(dev, obj);
3641
3642         i915_gem_free_object_tail(obj);
3643 }
3644
3645 int
3646 i915_gem_idle(struct drm_device *dev)
3647 {
3648         drm_i915_private_t *dev_priv = dev->dev_private;
3649         int ret;
3650
3651         mutex_lock(&dev->struct_mutex);
3652
3653         if (dev_priv->mm.suspended) {
3654                 mutex_unlock(&dev->struct_mutex);
3655                 return 0;
3656         }
3657
3658         ret = i915_gpu_idle(dev);
3659         if (ret) {
3660                 mutex_unlock(&dev->struct_mutex);
3661                 return ret;
3662         }
3663
3664         /* Under UMS, be paranoid and evict. */
3665         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3666                 ret = i915_gem_evict_inactive(dev, false);
3667                 if (ret) {
3668                         mutex_unlock(&dev->struct_mutex);
3669                         return ret;
3670                 }
3671         }
3672
3673         i915_gem_reset_fences(dev);
3674
3675         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3676          * We need to replace this with a semaphore, or something.
3677          * And not confound mm.suspended!
3678          */
3679         dev_priv->mm.suspended = 1;
3680         del_timer_sync(&dev_priv->hangcheck_timer);
3681
3682         i915_kernel_lost_context(dev);
3683         i915_gem_cleanup_ringbuffer(dev);
3684
3685         mutex_unlock(&dev->struct_mutex);
3686
3687         /* Cancel the retire work handler, which should be idle now. */
3688         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3689
3690         return 0;
3691 }
3692
3693 int
3694 i915_gem_init_ringbuffer(struct drm_device *dev)
3695 {
3696         drm_i915_private_t *dev_priv = dev->dev_private;
3697         int ret;
3698
3699         ret = intel_init_render_ring_buffer(dev);
3700         if (ret)
3701                 return ret;
3702
3703         if (HAS_BSD(dev)) {
3704                 ret = intel_init_bsd_ring_buffer(dev);
3705                 if (ret)
3706                         goto cleanup_render_ring;
3707         }
3708
3709         if (HAS_BLT(dev)) {
3710                 ret = intel_init_blt_ring_buffer(dev);
3711                 if (ret)
3712                         goto cleanup_bsd_ring;
3713         }
3714
3715         dev_priv->next_seqno = 1;
3716
3717         return 0;
3718
3719 cleanup_bsd_ring:
3720         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3721 cleanup_render_ring:
3722         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3723         return ret;
3724 }
3725
3726 void
3727 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3728 {
3729         drm_i915_private_t *dev_priv = dev->dev_private;
3730         int i;
3731
3732         for (i = 0; i < I915_NUM_RINGS; i++)
3733                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3734 }
3735
3736 int
3737 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3738                        struct drm_file *file_priv)
3739 {
3740         drm_i915_private_t *dev_priv = dev->dev_private;
3741         int ret, i;
3742
3743         if (drm_core_check_feature(dev, DRIVER_MODESET))
3744                 return 0;
3745
3746         if (atomic_read(&dev_priv->mm.wedged)) {
3747                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3748                 atomic_set(&dev_priv->mm.wedged, 0);
3749         }
3750
3751         mutex_lock(&dev->struct_mutex);
3752         dev_priv->mm.suspended = 0;
3753
3754         ret = i915_gem_init_ringbuffer(dev);
3755         if (ret != 0) {
3756                 mutex_unlock(&dev->struct_mutex);
3757                 return ret;
3758         }
3759
3760         BUG_ON(!list_empty(&dev_priv->mm.active_list));
3761         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3762         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3763         for (i = 0; i < I915_NUM_RINGS; i++) {
3764                 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3765                 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3766         }
3767         mutex_unlock(&dev->struct_mutex);
3768
3769         ret = drm_irq_install(dev);
3770         if (ret)
3771                 goto cleanup_ringbuffer;
3772
3773         return 0;
3774
3775 cleanup_ringbuffer:
3776         mutex_lock(&dev->struct_mutex);
3777         i915_gem_cleanup_ringbuffer(dev);
3778         dev_priv->mm.suspended = 1;
3779         mutex_unlock(&dev->struct_mutex);
3780
3781         return ret;
3782 }
3783
3784 int
3785 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3786                        struct drm_file *file_priv)
3787 {
3788         if (drm_core_check_feature(dev, DRIVER_MODESET))
3789                 return 0;
3790
3791         drm_irq_uninstall(dev);
3792         return i915_gem_idle(dev);
3793 }
3794
3795 void
3796 i915_gem_lastclose(struct drm_device *dev)
3797 {
3798         int ret;
3799
3800         if (drm_core_check_feature(dev, DRIVER_MODESET))
3801                 return;
3802
3803         ret = i915_gem_idle(dev);
3804         if (ret)
3805                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3806 }
3807
3808 static void
3809 init_ring_lists(struct intel_ring_buffer *ring)
3810 {
3811         INIT_LIST_HEAD(&ring->active_list);
3812         INIT_LIST_HEAD(&ring->request_list);
3813         INIT_LIST_HEAD(&ring->gpu_write_list);
3814 }
3815
3816 void
3817 i915_gem_load(struct drm_device *dev)
3818 {
3819         int i;
3820         drm_i915_private_t *dev_priv = dev->dev_private;
3821
3822         INIT_LIST_HEAD(&dev_priv->mm.active_list);
3823         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3824         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3825         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3826         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3827         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3828         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3829         for (i = 0; i < I915_NUM_RINGS; i++)
3830                 init_ring_lists(&dev_priv->ring[i]);
3831         for (i = 0; i < 16; i++)
3832                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3833         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3834                           i915_gem_retire_work_handler);
3835         init_completion(&dev_priv->error_completion);
3836
3837         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3838         if (IS_GEN3(dev)) {
3839                 u32 tmp = I915_READ(MI_ARB_STATE);
3840                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3841                         /* arb state is a masked write, so set bit + bit in mask */
3842                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3843                         I915_WRITE(MI_ARB_STATE, tmp);
3844                 }
3845         }
3846
3847         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3848
3849         /* Old X drivers will take 0-2 for front, back, depth buffers */
3850         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3851                 dev_priv->fence_reg_start = 3;
3852
3853         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3854                 dev_priv->num_fence_regs = 16;
3855         else
3856                 dev_priv->num_fence_regs = 8;
3857
3858         /* Initialize fence registers to zero */
3859         for (i = 0; i < dev_priv->num_fence_regs; i++) {
3860                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3861         }
3862
3863         i915_gem_detect_bit_6_swizzle(dev);
3864         init_waitqueue_head(&dev_priv->pending_flip_queue);
3865
3866         dev_priv->mm.interruptible = true;
3867
3868         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3869         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3870         register_shrinker(&dev_priv->mm.inactive_shrinker);
3871 }
3872
3873 /*
3874  * Create a physically contiguous memory object for this object
3875  * e.g. for cursor + overlay regs
3876  */
3877 static int i915_gem_init_phys_object(struct drm_device *dev,
3878                                      int id, int size, int align)
3879 {
3880         drm_i915_private_t *dev_priv = dev->dev_private;
3881         struct drm_i915_gem_phys_object *phys_obj;
3882         int ret;
3883
3884         if (dev_priv->mm.phys_objs[id - 1] || !size)
3885                 return 0;
3886
3887         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3888         if (!phys_obj)
3889                 return -ENOMEM;
3890
3891         phys_obj->id = id;
3892
3893         phys_obj->handle = drm_pci_alloc(dev, size, align);
3894         if (!phys_obj->handle) {
3895                 ret = -ENOMEM;
3896                 goto kfree_obj;
3897         }
3898 #ifdef CONFIG_X86
3899         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3900 #endif
3901
3902         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3903
3904         return 0;
3905 kfree_obj:
3906         kfree(phys_obj);
3907         return ret;
3908 }
3909
3910 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3911 {
3912         drm_i915_private_t *dev_priv = dev->dev_private;
3913         struct drm_i915_gem_phys_object *phys_obj;
3914
3915         if (!dev_priv->mm.phys_objs[id - 1])
3916                 return;
3917
3918         phys_obj = dev_priv->mm.phys_objs[id - 1];
3919         if (phys_obj->cur_obj) {
3920                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3921         }
3922
3923 #ifdef CONFIG_X86
3924         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3925 #endif
3926         drm_pci_free(dev, phys_obj->handle);
3927         kfree(phys_obj);
3928         dev_priv->mm.phys_objs[id - 1] = NULL;
3929 }
3930
3931 void i915_gem_free_all_phys_object(struct drm_device *dev)
3932 {
3933         int i;
3934
3935         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3936                 i915_gem_free_phys_object(dev, i);
3937 }
3938
3939 void i915_gem_detach_phys_object(struct drm_device *dev,
3940                                  struct drm_i915_gem_object *obj)
3941 {
3942         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3943         char *vaddr;
3944         int i;
3945         int page_count;
3946
3947         if (!obj->phys_obj)
3948                 return;
3949         vaddr = obj->phys_obj->handle->vaddr;
3950
3951         page_count = obj->base.size / PAGE_SIZE;
3952         for (i = 0; i < page_count; i++) {
3953                 struct page *page = read_cache_page_gfp(mapping, i,
3954                                                         GFP_HIGHUSER | __GFP_RECLAIMABLE);
3955                 if (!IS_ERR(page)) {
3956                         char *dst = kmap_atomic(page);
3957                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3958                         kunmap_atomic(dst);
3959
3960                         drm_clflush_pages(&page, 1);
3961
3962                         set_page_dirty(page);
3963                         mark_page_accessed(page);
3964                         page_cache_release(page);
3965                 }
3966         }
3967         intel_gtt_chipset_flush();
3968
3969         obj->phys_obj->cur_obj = NULL;
3970         obj->phys_obj = NULL;
3971 }
3972
3973 int
3974 i915_gem_attach_phys_object(struct drm_device *dev,
3975                             struct drm_i915_gem_object *obj,
3976                             int id,
3977                             int align)
3978 {
3979         struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3980         drm_i915_private_t *dev_priv = dev->dev_private;
3981         int ret = 0;
3982         int page_count;
3983         int i;
3984
3985         if (id > I915_MAX_PHYS_OBJECT)
3986                 return -EINVAL;
3987
3988         if (obj->phys_obj) {
3989                 if (obj->phys_obj->id == id)
3990                         return 0;
3991                 i915_gem_detach_phys_object(dev, obj);
3992         }
3993
3994         /* create a new object */
3995         if (!dev_priv->mm.phys_objs[id - 1]) {
3996                 ret = i915_gem_init_phys_object(dev, id,
3997                                                 obj->base.size, align);
3998                 if (ret) {
3999                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4000                                   id, obj->base.size);
4001                         return ret;
4002                 }
4003         }
4004
4005         /* bind to the object */
4006         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4007         obj->phys_obj->cur_obj = obj;
4008
4009         page_count = obj->base.size / PAGE_SIZE;
4010
4011         for (i = 0; i < page_count; i++) {
4012                 struct page *page;
4013                 char *dst, *src;
4014
4015                 page = read_cache_page_gfp(mapping, i,
4016                                            GFP_HIGHUSER | __GFP_RECLAIMABLE);
4017                 if (IS_ERR(page))
4018                         return PTR_ERR(page);
4019
4020                 src = kmap_atomic(page);
4021                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4022                 memcpy(dst, src, PAGE_SIZE);
4023                 kunmap_atomic(src);
4024
4025                 mark_page_accessed(page);
4026                 page_cache_release(page);
4027         }
4028
4029         return 0;
4030 }
4031
4032 static int
4033 i915_gem_phys_pwrite(struct drm_device *dev,
4034                      struct drm_i915_gem_object *obj,
4035                      struct drm_i915_gem_pwrite *args,
4036                      struct drm_file *file_priv)
4037 {
4038         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4039         char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4040
4041         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4042                 unsigned long unwritten;
4043
4044                 /* The physical object once assigned is fixed for the lifetime
4045                  * of the obj, so we can safely drop the lock and continue
4046                  * to access vaddr.
4047                  */
4048                 mutex_unlock(&dev->struct_mutex);
4049                 unwritten = copy_from_user(vaddr, user_data, args->size);
4050                 mutex_lock(&dev->struct_mutex);
4051                 if (unwritten)
4052                         return -EFAULT;
4053         }
4054
4055         intel_gtt_chipset_flush();
4056         return 0;
4057 }
4058
4059 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4060 {
4061         struct drm_i915_file_private *file_priv = file->driver_priv;
4062
4063         /* Clean up our request list when the client is going away, so that
4064          * later retire_requests won't dereference our soon-to-be-gone
4065          * file_priv.
4066          */
4067         spin_lock(&file_priv->mm.lock);
4068         while (!list_empty(&file_priv->mm.request_list)) {
4069                 struct drm_i915_gem_request *request;
4070
4071                 request = list_first_entry(&file_priv->mm.request_list,
4072                                            struct drm_i915_gem_request,
4073                                            client_list);
4074                 list_del(&request->client_list);
4075                 request->file_priv = NULL;
4076         }
4077         spin_unlock(&file_priv->mm.lock);
4078 }
4079
4080 static int
4081 i915_gpu_is_active(struct drm_device *dev)
4082 {
4083         drm_i915_private_t *dev_priv = dev->dev_private;
4084         int lists_empty;
4085
4086         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4087                       list_empty(&dev_priv->mm.active_list);
4088
4089         return !lists_empty;
4090 }
4091
4092 static int
4093 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4094 {
4095         struct drm_i915_private *dev_priv =
4096                 container_of(shrinker,
4097                              struct drm_i915_private,
4098                              mm.inactive_shrinker);
4099         struct drm_device *dev = dev_priv->dev;
4100         struct drm_i915_gem_object *obj, *next;
4101         int nr_to_scan = sc->nr_to_scan;
4102         int cnt;
4103
4104         if (!mutex_trylock(&dev->struct_mutex))
4105                 return 0;
4106
4107         /* "fast-path" to count number of available objects */
4108         if (nr_to_scan == 0) {
4109                 cnt = 0;
4110                 list_for_each_entry(obj,
4111                                     &dev_priv->mm.inactive_list,
4112                                     mm_list)
4113                         cnt++;
4114                 mutex_unlock(&dev->struct_mutex);
4115                 return cnt / 100 * sysctl_vfs_cache_pressure;
4116         }
4117
4118 rescan:
4119         /* first scan for clean buffers */
4120         i915_gem_retire_requests(dev);
4121
4122         list_for_each_entry_safe(obj, next,
4123                                  &dev_priv->mm.inactive_list,
4124                                  mm_list) {
4125                 if (i915_gem_object_is_purgeable(obj)) {
4126                         if (i915_gem_object_unbind(obj) == 0 &&
4127                             --nr_to_scan == 0)
4128                                 break;
4129                 }
4130         }
4131
4132         /* second pass, evict/count anything still on the inactive list */
4133         cnt = 0;
4134         list_for_each_entry_safe(obj, next,
4135                                  &dev_priv->mm.inactive_list,
4136                                  mm_list) {
4137                 if (nr_to_scan &&
4138                     i915_gem_object_unbind(obj) == 0)
4139                         nr_to_scan--;
4140                 else
4141                         cnt++;
4142         }
4143
4144         if (nr_to_scan && i915_gpu_is_active(dev)) {
4145                 /*
4146                  * We are desperate for pages, so as a last resort, wait
4147                  * for the GPU to finish and discard whatever we can.
4148                  * This has a dramatic impact to reduce the number of
4149                  * OOM-killer events whilst running the GPU aggressively.
4150                  */
4151                 if (i915_gpu_idle(dev) == 0)
4152                         goto rescan;
4153         }
4154         mutex_unlock(&dev->struct_mutex);
4155         return cnt / 100 * sysctl_vfs_cache_pressure;
4156 }