2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
57 struct drm_i915_gem_pwrite *args,
58 struct drm_file *file_priv);
59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
61 static LIST_HEAD(shrink_list);
62 static DEFINE_SPINLOCK(shrink_list_lock);
65 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
67 return obj_priv->gtt_space &&
69 obj_priv->pin_count == 0;
72 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
75 drm_i915_private_t *dev_priv = dev->dev_private;
78 (start & (PAGE_SIZE - 1)) != 0 ||
79 (end & (PAGE_SIZE - 1)) != 0) {
83 drm_mm_init(&dev_priv->mm.gtt_space, start,
86 dev->gtt_total = (uint32_t) (end - start);
92 i915_gem_init_ioctl(struct drm_device *dev, void *data,
93 struct drm_file *file_priv)
95 struct drm_i915_gem_init *args = data;
98 mutex_lock(&dev->struct_mutex);
99 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
100 mutex_unlock(&dev->struct_mutex);
106 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
107 struct drm_file *file_priv)
109 struct drm_i915_gem_get_aperture *args = data;
111 if (!(dev->driver->driver_features & DRIVER_GEM))
114 args->aper_size = dev->gtt_total;
115 args->aper_available_size = (args->aper_size -
116 atomic_read(&dev->pin_memory));
123 * Creates a new mm object and returns a handle to it.
126 i915_gem_create_ioctl(struct drm_device *dev, void *data,
127 struct drm_file *file_priv)
129 struct drm_i915_gem_create *args = data;
130 struct drm_gem_object *obj;
134 args->size = roundup(args->size, PAGE_SIZE);
136 /* Allocate the new object */
137 obj = i915_gem_alloc_object(dev, args->size);
141 ret = drm_gem_handle_create(file_priv, obj, &handle);
143 drm_gem_object_unreference_unlocked(obj);
147 /* Sink the floating reference from kref_init(handlecount) */
148 drm_gem_object_handle_unreference_unlocked(obj);
150 args->handle = handle;
155 fast_shmem_read(struct page **pages,
156 loff_t page_base, int page_offset,
163 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
166 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
167 kunmap_atomic(vaddr, KM_USER0);
175 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
177 drm_i915_private_t *dev_priv = obj->dev->dev_private;
178 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
180 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
181 obj_priv->tiling_mode != I915_TILING_NONE;
185 slow_shmem_copy(struct page *dst_page,
187 struct page *src_page,
191 char *dst_vaddr, *src_vaddr;
193 dst_vaddr = kmap(dst_page);
194 src_vaddr = kmap(src_page);
196 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
203 slow_shmem_bit17_copy(struct page *gpu_page,
205 struct page *cpu_page,
210 char *gpu_vaddr, *cpu_vaddr;
212 /* Use the unswizzled path if this page isn't affected. */
213 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
215 return slow_shmem_copy(cpu_page, cpu_offset,
216 gpu_page, gpu_offset, length);
218 return slow_shmem_copy(gpu_page, gpu_offset,
219 cpu_page, cpu_offset, length);
222 gpu_vaddr = kmap(gpu_page);
223 cpu_vaddr = kmap(cpu_page);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end = ALIGN(gpu_offset + 1, 64);
230 int this_length = min(cacheline_end - gpu_offset, length);
231 int swizzled_gpu_offset = gpu_offset ^ 64;
234 memcpy(cpu_vaddr + cpu_offset,
235 gpu_vaddr + swizzled_gpu_offset,
238 memcpy(gpu_vaddr + swizzled_gpu_offset,
239 cpu_vaddr + cpu_offset,
242 cpu_offset += this_length;
243 gpu_offset += this_length;
244 length -= this_length;
252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
257 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
258 struct drm_i915_gem_pread *args,
259 struct drm_file *file_priv)
261 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
263 loff_t offset, page_base;
264 char __user *user_data;
265 int page_offset, page_length;
268 user_data = (char __user *) (uintptr_t) args->data_ptr;
271 mutex_lock(&dev->struct_mutex);
273 ret = i915_gem_object_get_pages(obj, 0);
277 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
282 obj_priv = to_intel_bo(obj);
283 offset = args->offset;
286 /* Operation in this page
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
292 page_base = (offset & ~(PAGE_SIZE-1));
293 page_offset = offset & (PAGE_SIZE-1);
294 page_length = remain;
295 if ((page_offset + remain) > PAGE_SIZE)
296 page_length = PAGE_SIZE - page_offset;
298 ret = fast_shmem_read(obj_priv->pages,
299 page_base, page_offset,
300 user_data, page_length);
304 remain -= page_length;
305 user_data += page_length;
306 offset += page_length;
310 i915_gem_object_put_pages(obj);
312 mutex_unlock(&dev->struct_mutex);
318 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
322 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
324 /* If we've insufficient memory to map in the pages, attempt
325 * to make some space by throwing out some old buffers.
327 if (ret == -ENOMEM) {
328 struct drm_device *dev = obj->dev;
330 ret = i915_gem_evict_something(dev, obj->size,
331 i915_gem_get_gtt_alignment(obj));
335 ret = i915_gem_object_get_pages(obj, 0);
342 * This is the fallback shmem pread path, which allocates temporary storage
343 * in kernel space to copy_to_user into outside of the struct_mutex, so we
344 * can copy out of the object's backing pages while holding the struct mutex
345 * and not take page faults.
348 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
349 struct drm_i915_gem_pread *args,
350 struct drm_file *file_priv)
352 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
353 struct mm_struct *mm = current->mm;
354 struct page **user_pages;
356 loff_t offset, pinned_pages, i;
357 loff_t first_data_page, last_data_page, num_pages;
358 int shmem_page_index, shmem_page_offset;
359 int data_page_index, data_page_offset;
362 uint64_t data_ptr = args->data_ptr;
363 int do_bit17_swizzling;
367 /* Pin the user pages containing the data. We can't fault while
368 * holding the struct mutex, yet we want to hold it while
369 * dereferencing the user data.
371 first_data_page = data_ptr / PAGE_SIZE;
372 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
373 num_pages = last_data_page - first_data_page + 1;
375 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
376 if (user_pages == NULL)
379 down_read(&mm->mmap_sem);
380 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
381 num_pages, 1, 0, user_pages, NULL);
382 up_read(&mm->mmap_sem);
383 if (pinned_pages < num_pages) {
385 goto fail_put_user_pages;
388 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
390 mutex_lock(&dev->struct_mutex);
392 ret = i915_gem_object_get_pages_or_evict(obj);
396 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
401 obj_priv = to_intel_bo(obj);
402 offset = args->offset;
405 /* Operation in this page
407 * shmem_page_index = page number within shmem file
408 * shmem_page_offset = offset within page in shmem file
409 * data_page_index = page number in get_user_pages return
410 * data_page_offset = offset with data_page_index page.
411 * page_length = bytes to copy for this page
413 shmem_page_index = offset / PAGE_SIZE;
414 shmem_page_offset = offset & ~PAGE_MASK;
415 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
416 data_page_offset = data_ptr & ~PAGE_MASK;
418 page_length = remain;
419 if ((shmem_page_offset + page_length) > PAGE_SIZE)
420 page_length = PAGE_SIZE - shmem_page_offset;
421 if ((data_page_offset + page_length) > PAGE_SIZE)
422 page_length = PAGE_SIZE - data_page_offset;
424 if (do_bit17_swizzling) {
425 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
427 user_pages[data_page_index],
432 slow_shmem_copy(user_pages[data_page_index],
434 obj_priv->pages[shmem_page_index],
439 remain -= page_length;
440 data_ptr += page_length;
441 offset += page_length;
445 i915_gem_object_put_pages(obj);
447 mutex_unlock(&dev->struct_mutex);
449 for (i = 0; i < pinned_pages; i++) {
450 SetPageDirty(user_pages[i]);
451 page_cache_release(user_pages[i]);
453 drm_free_large(user_pages);
459 * Reads data from the object referenced by handle.
461 * On error, the contents of *data are undefined.
464 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
465 struct drm_file *file_priv)
467 struct drm_i915_gem_pread *args = data;
468 struct drm_gem_object *obj;
469 struct drm_i915_gem_object *obj_priv;
472 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
475 obj_priv = to_intel_bo(obj);
477 /* Bounds check source.
479 * XXX: This could use review for overflow issues...
481 if (args->offset > obj->size || args->size > obj->size ||
482 args->offset + args->size > obj->size) {
483 drm_gem_object_unreference_unlocked(obj);
487 if (i915_gem_object_needs_bit17_swizzle(obj)) {
488 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
490 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
492 ret = i915_gem_shmem_pread_slow(dev, obj, args,
496 drm_gem_object_unreference_unlocked(obj);
501 /* This is the fast write path which cannot handle
502 * page faults in the source data
506 fast_user_write(struct io_mapping *mapping,
507 loff_t page_base, int page_offset,
508 char __user *user_data,
512 unsigned long unwritten;
514 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
515 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
517 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
523 /* Here's the write path which can sleep for
528 slow_kernel_write(struct io_mapping *mapping,
529 loff_t gtt_base, int gtt_offset,
530 struct page *user_page, int user_offset,
533 char __iomem *dst_vaddr;
536 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
537 src_vaddr = kmap(user_page);
539 memcpy_toio(dst_vaddr + gtt_offset,
540 src_vaddr + user_offset,
544 io_mapping_unmap(dst_vaddr);
548 fast_shmem_write(struct page **pages,
549 loff_t page_base, int page_offset,
554 unsigned long unwritten;
556 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
559 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
560 kunmap_atomic(vaddr, KM_USER0);
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
572 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
573 struct drm_i915_gem_pwrite *args,
574 struct drm_file *file_priv)
576 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
577 drm_i915_private_t *dev_priv = dev->dev_private;
579 loff_t offset, page_base;
580 char __user *user_data;
581 int page_offset, page_length;
584 user_data = (char __user *) (uintptr_t) args->data_ptr;
586 if (!access_ok(VERIFY_READ, user_data, remain))
590 mutex_lock(&dev->struct_mutex);
591 ret = i915_gem_object_pin(obj, 0);
593 mutex_unlock(&dev->struct_mutex);
596 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
600 obj_priv = to_intel_bo(obj);
601 offset = obj_priv->gtt_offset + args->offset;
604 /* Operation in this page
606 * page_base = page offset within aperture
607 * page_offset = offset within page
608 * page_length = bytes to copy for this page
610 page_base = (offset & ~(PAGE_SIZE-1));
611 page_offset = offset & (PAGE_SIZE-1);
612 page_length = remain;
613 if ((page_offset + remain) > PAGE_SIZE)
614 page_length = PAGE_SIZE - page_offset;
616 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
617 page_offset, user_data, page_length);
619 /* If we get a fault while copying data, then (presumably) our
620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
626 remain -= page_length;
627 user_data += page_length;
628 offset += page_length;
632 i915_gem_object_unpin(obj);
633 mutex_unlock(&dev->struct_mutex);
639 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
640 * the memory and maps it using kmap_atomic for copying.
642 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
643 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
646 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
647 struct drm_i915_gem_pwrite *args,
648 struct drm_file *file_priv)
650 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
651 drm_i915_private_t *dev_priv = dev->dev_private;
653 loff_t gtt_page_base, offset;
654 loff_t first_data_page, last_data_page, num_pages;
655 loff_t pinned_pages, i;
656 struct page **user_pages;
657 struct mm_struct *mm = current->mm;
658 int gtt_page_offset, data_page_offset, data_page_index, page_length;
660 uint64_t data_ptr = args->data_ptr;
664 /* Pin the user pages containing the data. We can't fault while
665 * holding the struct mutex, and all of the pwrite implementations
666 * want to hold it while dereferencing the user data.
668 first_data_page = data_ptr / PAGE_SIZE;
669 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
670 num_pages = last_data_page - first_data_page + 1;
672 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
673 if (user_pages == NULL)
676 down_read(&mm->mmap_sem);
677 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
678 num_pages, 0, 0, user_pages, NULL);
679 up_read(&mm->mmap_sem);
680 if (pinned_pages < num_pages) {
682 goto out_unpin_pages;
685 mutex_lock(&dev->struct_mutex);
686 ret = i915_gem_object_pin(obj, 0);
690 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
692 goto out_unpin_object;
694 obj_priv = to_intel_bo(obj);
695 offset = obj_priv->gtt_offset + args->offset;
698 /* Operation in this page
700 * gtt_page_base = page offset within aperture
701 * gtt_page_offset = offset within page in aperture
702 * data_page_index = page number in get_user_pages return
703 * data_page_offset = offset with data_page_index page.
704 * page_length = bytes to copy for this page
706 gtt_page_base = offset & PAGE_MASK;
707 gtt_page_offset = offset & ~PAGE_MASK;
708 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
709 data_page_offset = data_ptr & ~PAGE_MASK;
711 page_length = remain;
712 if ((gtt_page_offset + page_length) > PAGE_SIZE)
713 page_length = PAGE_SIZE - gtt_page_offset;
714 if ((data_page_offset + page_length) > PAGE_SIZE)
715 page_length = PAGE_SIZE - data_page_offset;
717 slow_kernel_write(dev_priv->mm.gtt_mapping,
718 gtt_page_base, gtt_page_offset,
719 user_pages[data_page_index],
723 remain -= page_length;
724 offset += page_length;
725 data_ptr += page_length;
729 i915_gem_object_unpin(obj);
731 mutex_unlock(&dev->struct_mutex);
733 for (i = 0; i < pinned_pages; i++)
734 page_cache_release(user_pages[i]);
735 drm_free_large(user_pages);
741 * This is the fast shmem pwrite path, which attempts to directly
742 * copy_from_user into the kmapped pages backing the object.
745 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
746 struct drm_i915_gem_pwrite *args,
747 struct drm_file *file_priv)
749 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
751 loff_t offset, page_base;
752 char __user *user_data;
753 int page_offset, page_length;
756 user_data = (char __user *) (uintptr_t) args->data_ptr;
759 mutex_lock(&dev->struct_mutex);
761 ret = i915_gem_object_get_pages(obj, 0);
765 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
769 obj_priv = to_intel_bo(obj);
770 offset = args->offset;
774 /* Operation in this page
776 * page_base = page offset within aperture
777 * page_offset = offset within page
778 * page_length = bytes to copy for this page
780 page_base = (offset & ~(PAGE_SIZE-1));
781 page_offset = offset & (PAGE_SIZE-1);
782 page_length = remain;
783 if ((page_offset + remain) > PAGE_SIZE)
784 page_length = PAGE_SIZE - page_offset;
786 ret = fast_shmem_write(obj_priv->pages,
787 page_base, page_offset,
788 user_data, page_length);
792 remain -= page_length;
793 user_data += page_length;
794 offset += page_length;
798 i915_gem_object_put_pages(obj);
800 mutex_unlock(&dev->struct_mutex);
806 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
807 * the memory and maps it using kmap_atomic for copying.
809 * This avoids taking mmap_sem for faulting on the user's address while the
810 * struct_mutex is held.
813 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
814 struct drm_i915_gem_pwrite *args,
815 struct drm_file *file_priv)
817 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
818 struct mm_struct *mm = current->mm;
819 struct page **user_pages;
821 loff_t offset, pinned_pages, i;
822 loff_t first_data_page, last_data_page, num_pages;
823 int shmem_page_index, shmem_page_offset;
824 int data_page_index, data_page_offset;
827 uint64_t data_ptr = args->data_ptr;
828 int do_bit17_swizzling;
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
836 first_data_page = data_ptr / PAGE_SIZE;
837 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
838 num_pages = last_data_page - first_data_page + 1;
840 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
841 if (user_pages == NULL)
844 down_read(&mm->mmap_sem);
845 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
846 num_pages, 0, 0, user_pages, NULL);
847 up_read(&mm->mmap_sem);
848 if (pinned_pages < num_pages) {
850 goto fail_put_user_pages;
853 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
855 mutex_lock(&dev->struct_mutex);
857 ret = i915_gem_object_get_pages_or_evict(obj);
861 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
865 obj_priv = to_intel_bo(obj);
866 offset = args->offset;
870 /* Operation in this page
872 * shmem_page_index = page number within shmem file
873 * shmem_page_offset = offset within page in shmem file
874 * data_page_index = page number in get_user_pages return
875 * data_page_offset = offset with data_page_index page.
876 * page_length = bytes to copy for this page
878 shmem_page_index = offset / PAGE_SIZE;
879 shmem_page_offset = offset & ~PAGE_MASK;
880 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
881 data_page_offset = data_ptr & ~PAGE_MASK;
883 page_length = remain;
884 if ((shmem_page_offset + page_length) > PAGE_SIZE)
885 page_length = PAGE_SIZE - shmem_page_offset;
886 if ((data_page_offset + page_length) > PAGE_SIZE)
887 page_length = PAGE_SIZE - data_page_offset;
889 if (do_bit17_swizzling) {
890 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
892 user_pages[data_page_index],
897 slow_shmem_copy(obj_priv->pages[shmem_page_index],
899 user_pages[data_page_index],
904 remain -= page_length;
905 data_ptr += page_length;
906 offset += page_length;
910 i915_gem_object_put_pages(obj);
912 mutex_unlock(&dev->struct_mutex);
914 for (i = 0; i < pinned_pages; i++)
915 page_cache_release(user_pages[i]);
916 drm_free_large(user_pages);
922 * Writes data to the object referenced by handle.
924 * On error, the contents of the buffer that were to be modified are undefined.
927 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *file_priv)
930 struct drm_i915_gem_pwrite *args = data;
931 struct drm_gem_object *obj;
932 struct drm_i915_gem_object *obj_priv;
935 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
938 obj_priv = to_intel_bo(obj);
940 /* Bounds check destination.
942 * XXX: This could use review for overflow issues...
944 if (args->offset > obj->size || args->size > obj->size ||
945 args->offset + args->size > obj->size) {
946 drm_gem_object_unreference_unlocked(obj);
950 /* We can only do the GTT pwrite on untiled buffers, as otherwise
951 * it would end up going through the fenced access, and we'll get
952 * different detiling behavior between reading and writing.
953 * pread/pwrite currently are reading and writing from the CPU
954 * perspective, requiring manual detiling by the client.
956 if (obj_priv->phys_obj)
957 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
958 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
959 dev->gtt_total != 0 &&
960 obj->write_domain != I915_GEM_DOMAIN_CPU) {
961 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
962 if (ret == -EFAULT) {
963 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
966 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
967 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
969 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
970 if (ret == -EFAULT) {
971 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
978 DRM_INFO("pwrite failed %d\n", ret);
981 drm_gem_object_unreference_unlocked(obj);
987 * Called when user space prepares to use an object with the CPU, either
988 * through the mmap ioctl's mapping or a GTT mapping.
991 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *file_priv)
994 struct drm_i915_private *dev_priv = dev->dev_private;
995 struct drm_i915_gem_set_domain *args = data;
996 struct drm_gem_object *obj;
997 struct drm_i915_gem_object *obj_priv;
998 uint32_t read_domains = args->read_domains;
999 uint32_t write_domain = args->write_domain;
1002 if (!(dev->driver->driver_features & DRIVER_GEM))
1005 /* Only handle setting domains to types used by the CPU. */
1006 if (write_domain & I915_GEM_GPU_DOMAINS)
1009 if (read_domains & I915_GEM_GPU_DOMAINS)
1012 /* Having something in the write domain implies it's in the read
1013 * domain, and only that read domain. Enforce that in the request.
1015 if (write_domain != 0 && read_domains != write_domain)
1018 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1021 obj_priv = to_intel_bo(obj);
1023 mutex_lock(&dev->struct_mutex);
1025 intel_mark_busy(dev, obj);
1028 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1029 obj, obj->size, read_domains, write_domain);
1031 if (read_domains & I915_GEM_DOMAIN_GTT) {
1032 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1034 /* Update the LRU on the fence for the CPU access that's
1037 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1038 struct drm_i915_fence_reg *reg =
1039 &dev_priv->fence_regs[obj_priv->fence_reg];
1040 list_move_tail(®->lru_list,
1041 &dev_priv->mm.fence_list);
1044 /* Silently promote "you're not bound, there was nothing to do"
1045 * to success, since the client was just asking us to
1046 * make sure everything was done.
1051 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1055 /* Maintain LRU order of "inactive" objects */
1056 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1057 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1059 drm_gem_object_unreference(obj);
1060 mutex_unlock(&dev->struct_mutex);
1065 * Called when user space has done writes to this buffer
1068 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069 struct drm_file *file_priv)
1071 struct drm_i915_gem_sw_finish *args = data;
1072 struct drm_gem_object *obj;
1073 struct drm_i915_gem_object *obj_priv;
1076 if (!(dev->driver->driver_features & DRIVER_GEM))
1079 mutex_lock(&dev->struct_mutex);
1080 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1082 mutex_unlock(&dev->struct_mutex);
1087 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1088 __func__, args->handle, obj, obj->size);
1090 obj_priv = to_intel_bo(obj);
1092 /* Pinned buffers may be scanout, so flush the cache */
1093 if (obj_priv->pin_count)
1094 i915_gem_object_flush_cpu_write_domain(obj);
1096 drm_gem_object_unreference(obj);
1097 mutex_unlock(&dev->struct_mutex);
1102 * Maps the contents of an object, returning the address it is mapped
1105 * While the mapping holds a reference on the contents of the object, it doesn't
1106 * imply a ref on the object itself.
1109 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1112 struct drm_i915_gem_mmap *args = data;
1113 struct drm_gem_object *obj;
1117 if (!(dev->driver->driver_features & DRIVER_GEM))
1120 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1124 offset = args->offset;
1126 down_write(¤t->mm->mmap_sem);
1127 addr = do_mmap(obj->filp, 0, args->size,
1128 PROT_READ | PROT_WRITE, MAP_SHARED,
1130 up_write(¤t->mm->mmap_sem);
1131 drm_gem_object_unreference_unlocked(obj);
1132 if (IS_ERR((void *)addr))
1135 args->addr_ptr = (uint64_t) addr;
1141 * i915_gem_fault - fault a page into the GTT
1142 * vma: VMA in question
1145 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146 * from userspace. The fault handler takes care of binding the object to
1147 * the GTT (if needed), allocating and programming a fence register (again,
1148 * only if needed based on whether the old reg is still valid or the object
1149 * is tiled) and inserting a new PTE into the faulting process.
1151 * Note that the faulting process may involve evicting existing objects
1152 * from the GTT and/or fence registers to make room. So performance may
1153 * suffer if the GTT working set is large or there are few fence registers
1156 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1158 struct drm_gem_object *obj = vma->vm_private_data;
1159 struct drm_device *dev = obj->dev;
1160 drm_i915_private_t *dev_priv = dev->dev_private;
1161 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1162 pgoff_t page_offset;
1165 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1167 /* We don't use vmf->pgoff since that has the fake offset */
1168 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1171 /* Now bind it into the GTT if needed */
1172 mutex_lock(&dev->struct_mutex);
1173 if (!obj_priv->gtt_space) {
1174 ret = i915_gem_object_bind_to_gtt(obj, 0);
1178 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1183 /* Need a new fence register? */
1184 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1185 ret = i915_gem_object_get_fence_reg(obj, true);
1190 if (i915_gem_object_is_inactive(obj_priv))
1191 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1193 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1196 /* Finally, remap it using the new GTT offset */
1197 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1199 mutex_unlock(&dev->struct_mutex);
1204 return VM_FAULT_NOPAGE;
1207 return VM_FAULT_OOM;
1209 return VM_FAULT_SIGBUS;
1214 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215 * @obj: obj in question
1217 * GEM memory mapping works by handing back to userspace a fake mmap offset
1218 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1219 * up the object based on the offset and sets up the various memory mapping
1222 * This routine allocates and attaches a fake offset for @obj.
1225 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1227 struct drm_device *dev = obj->dev;
1228 struct drm_gem_mm *mm = dev->mm_private;
1229 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1230 struct drm_map_list *list;
1231 struct drm_local_map *map;
1234 /* Set the object up for mmap'ing */
1235 list = &obj->map_list;
1236 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1241 map->type = _DRM_GEM;
1242 map->size = obj->size;
1245 /* Get a DRM GEM mmap offset allocated... */
1246 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1247 obj->size / PAGE_SIZE, 0, 0);
1248 if (!list->file_offset_node) {
1249 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1254 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1255 obj->size / PAGE_SIZE, 0);
1256 if (!list->file_offset_node) {
1261 list->hash.key = list->file_offset_node->start;
1262 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1263 DRM_ERROR("failed to add to map hash\n");
1268 /* By now we should be all set, any drm_mmap request on the offset
1269 * below will get to our mmap & fault handler */
1270 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1275 drm_mm_put_block(list->file_offset_node);
1283 * i915_gem_release_mmap - remove physical page mappings
1284 * @obj: obj in question
1286 * Preserve the reservation of the mmapping with the DRM core code, but
1287 * relinquish ownership of the pages back to the system.
1289 * It is vital that we remove the page mapping if we have mapped a tiled
1290 * object through the GTT and then lose the fence register due to
1291 * resource pressure. Similarly if the object has been moved out of the
1292 * aperture, than pages mapped into userspace must be revoked. Removing the
1293 * mapping will then trigger a page fault on the next user access, allowing
1294 * fixup by i915_gem_fault().
1297 i915_gem_release_mmap(struct drm_gem_object *obj)
1299 struct drm_device *dev = obj->dev;
1300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1302 if (dev->dev_mapping)
1303 unmap_mapping_range(dev->dev_mapping,
1304 obj_priv->mmap_offset, obj->size, 1);
1308 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1310 struct drm_device *dev = obj->dev;
1311 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1312 struct drm_gem_mm *mm = dev->mm_private;
1313 struct drm_map_list *list;
1315 list = &obj->map_list;
1316 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1318 if (list->file_offset_node) {
1319 drm_mm_put_block(list->file_offset_node);
1320 list->file_offset_node = NULL;
1328 obj_priv->mmap_offset = 0;
1332 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333 * @obj: object to check
1335 * Return the required GTT alignment for an object, taking into account
1336 * potential fence register mapping if needed.
1339 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1346 * Minimum alignment is 4k (GTT page size), but might be greater
1347 * if a fence register is needed for the object.
1349 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1353 * Previous chips need to be aligned to the size of the smallest
1354 * fence register that can contain the object.
1361 for (i = start; i < obj->size; i <<= 1)
1368 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1370 * @data: GTT mapping ioctl data
1371 * @file_priv: GEM object info
1373 * Simply returns the fake offset to userspace so it can mmap it.
1374 * The mmap call will end up in drm_gem_mmap(), which will set things
1375 * up so we can get faults in the handler above.
1377 * The fault handler will take care of binding the object into the GTT
1378 * (since it may have been evicted to make room for something), allocating
1379 * a fence register, and mapping the appropriate aperture address into
1383 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1384 struct drm_file *file_priv)
1386 struct drm_i915_gem_mmap_gtt *args = data;
1387 struct drm_gem_object *obj;
1388 struct drm_i915_gem_object *obj_priv;
1391 if (!(dev->driver->driver_features & DRIVER_GEM))
1394 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1398 mutex_lock(&dev->struct_mutex);
1400 obj_priv = to_intel_bo(obj);
1402 if (obj_priv->madv != I915_MADV_WILLNEED) {
1403 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404 drm_gem_object_unreference(obj);
1405 mutex_unlock(&dev->struct_mutex);
1410 if (!obj_priv->mmap_offset) {
1411 ret = i915_gem_create_mmap_offset(obj);
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1419 args->offset = obj_priv->mmap_offset;
1422 * Pull it into the GTT so that we have a page list (makes the
1423 * initial fault faster and any subsequent flushing possible).
1425 if (!obj_priv->agp_mem) {
1426 ret = i915_gem_object_bind_to_gtt(obj, 0);
1428 drm_gem_object_unreference(obj);
1429 mutex_unlock(&dev->struct_mutex);
1434 drm_gem_object_unreference(obj);
1435 mutex_unlock(&dev->struct_mutex);
1441 i915_gem_object_put_pages(struct drm_gem_object *obj)
1443 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1444 int page_count = obj->size / PAGE_SIZE;
1447 BUG_ON(obj_priv->pages_refcount == 0);
1448 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1450 if (--obj_priv->pages_refcount != 0)
1453 if (obj_priv->tiling_mode != I915_TILING_NONE)
1454 i915_gem_object_save_bit_17_swizzle(obj);
1456 if (obj_priv->madv == I915_MADV_DONTNEED)
1457 obj_priv->dirty = 0;
1459 for (i = 0; i < page_count; i++) {
1460 if (obj_priv->dirty)
1461 set_page_dirty(obj_priv->pages[i]);
1463 if (obj_priv->madv == I915_MADV_WILLNEED)
1464 mark_page_accessed(obj_priv->pages[i]);
1466 page_cache_release(obj_priv->pages[i]);
1468 obj_priv->dirty = 0;
1470 drm_free_large(obj_priv->pages);
1471 obj_priv->pages = NULL;
1475 i915_gem_next_request_seqno(struct drm_device *dev,
1476 struct intel_ring_buffer *ring)
1478 drm_i915_private_t *dev_priv = dev->dev_private;
1480 ring->outstanding_lazy_request = true;
1482 return dev_priv->next_seqno;
1486 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1487 struct intel_ring_buffer *ring)
1489 struct drm_device *dev = obj->dev;
1490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1493 BUG_ON(ring == NULL);
1494 obj_priv->ring = ring;
1496 /* Add a reference if we're newly entering the active list. */
1497 if (!obj_priv->active) {
1498 drm_gem_object_reference(obj);
1499 obj_priv->active = 1;
1502 /* Move from whatever list we were on to the tail of execution. */
1503 list_move_tail(&obj_priv->list, &ring->active_list);
1504 obj_priv->last_rendering_seqno = seqno;
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1510 struct drm_device *dev = obj->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1514 BUG_ON(!obj_priv->active);
1515 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516 obj_priv->last_rendering_seqno = 0;
1519 /* Immediately discard the backing storage */
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1523 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1524 struct inode *inode;
1526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1532 inode = obj->filp->f_path.dentry->d_inode;
1533 truncate_inode_pages(inode->i_mapping, 0);
1534 if (inode->i_op->truncate_range)
1535 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1537 obj_priv->madv = __I915_MADV_PURGED;
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1543 return obj_priv->madv == I915_MADV_DONTNEED;
1547 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1549 struct drm_device *dev = obj->dev;
1550 drm_i915_private_t *dev_priv = dev->dev_private;
1551 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1553 i915_verify_inactive(dev, __FILE__, __LINE__);
1554 if (obj_priv->pin_count != 0)
1555 list_del_init(&obj_priv->list);
1557 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1559 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1561 obj_priv->last_rendering_seqno = 0;
1562 obj_priv->ring = NULL;
1563 if (obj_priv->active) {
1564 obj_priv->active = 0;
1565 drm_gem_object_unreference(obj);
1567 i915_verify_inactive(dev, __FILE__, __LINE__);
1571 i915_gem_process_flushing_list(struct drm_device *dev,
1572 uint32_t flush_domains,
1573 struct intel_ring_buffer *ring)
1575 drm_i915_private_t *dev_priv = dev->dev_private;
1576 struct drm_i915_gem_object *obj_priv, *next;
1578 list_for_each_entry_safe(obj_priv, next,
1579 &dev_priv->mm.gpu_write_list,
1581 struct drm_gem_object *obj = &obj_priv->base;
1583 if (obj->write_domain & flush_domains &&
1584 obj_priv->ring == ring) {
1585 uint32_t old_write_domain = obj->write_domain;
1587 obj->write_domain = 0;
1588 list_del_init(&obj_priv->gpu_write_list);
1589 i915_gem_object_move_to_active(obj, ring);
1591 /* update the fence lru list */
1592 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1593 struct drm_i915_fence_reg *reg =
1594 &dev_priv->fence_regs[obj_priv->fence_reg];
1595 list_move_tail(®->lru_list,
1596 &dev_priv->mm.fence_list);
1599 trace_i915_gem_object_change_domain(obj,
1607 i915_add_request(struct drm_device *dev,
1608 struct drm_file *file_priv,
1609 struct drm_i915_gem_request *request,
1610 struct intel_ring_buffer *ring)
1612 drm_i915_private_t *dev_priv = dev->dev_private;
1613 struct drm_i915_file_private *i915_file_priv = NULL;
1617 if (file_priv != NULL)
1618 i915_file_priv = file_priv->driver_priv;
1620 if (request == NULL) {
1621 request = kzalloc(sizeof(*request), GFP_KERNEL);
1622 if (request == NULL)
1626 seqno = ring->add_request(dev, ring, file_priv, 0);
1628 request->seqno = seqno;
1629 request->ring = ring;
1630 request->emitted_jiffies = jiffies;
1631 was_empty = list_empty(&ring->request_list);
1632 list_add_tail(&request->list, &ring->request_list);
1634 if (i915_file_priv) {
1635 list_add_tail(&request->client_list,
1636 &i915_file_priv->mm.request_list);
1638 INIT_LIST_HEAD(&request->client_list);
1641 if (!dev_priv->mm.suspended) {
1642 mod_timer(&dev_priv->hangcheck_timer,
1643 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1645 queue_delayed_work(dev_priv->wq,
1646 &dev_priv->mm.retire_work, HZ);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1660 uint32_t flush_domains = 0;
1662 /* The sampler always gets flushed on i965 (sigh) */
1664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
1671 * Moves buffers associated only with the given active seqno from the active
1672 * to inactive list, potentially freeing them.
1675 i915_gem_retire_request(struct drm_device *dev,
1676 struct drm_i915_gem_request *request)
1678 trace_i915_gem_request_retire(dev, request->seqno);
1680 /* Move any buffers on the active list that are no longer referenced
1681 * by the ringbuffer to the flushing/inactive lists as appropriate.
1683 while (!list_empty(&request->ring->active_list)) {
1684 struct drm_gem_object *obj;
1685 struct drm_i915_gem_object *obj_priv;
1687 obj_priv = list_first_entry(&request->ring->active_list,
1688 struct drm_i915_gem_object,
1690 obj = &obj_priv->base;
1692 /* If the seqno being retired doesn't match the oldest in the
1693 * list, then the oldest in the list must still be newer than
1696 if (obj_priv->last_rendering_seqno != request->seqno)
1700 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1701 __func__, request->seqno, obj);
1704 if (obj->write_domain != 0)
1705 i915_gem_object_move_to_flushing(obj);
1707 i915_gem_object_move_to_inactive(obj);
1712 * Returns true if seq1 is later than seq2.
1715 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1717 return (int32_t)(seq1 - seq2) >= 0;
1721 i915_get_gem_seqno(struct drm_device *dev,
1722 struct intel_ring_buffer *ring)
1724 return ring->get_gem_seqno(dev, ring);
1728 * This function clears the request list as sequence numbers are passed.
1731 i915_gem_retire_requests_ring(struct drm_device *dev,
1732 struct intel_ring_buffer *ring)
1734 drm_i915_private_t *dev_priv = dev->dev_private;
1737 if (!ring->status_page.page_addr
1738 || list_empty(&ring->request_list))
1741 seqno = i915_get_gem_seqno(dev, ring);
1743 while (!list_empty(&ring->request_list)) {
1744 struct drm_i915_gem_request *request;
1745 uint32_t retiring_seqno;
1747 request = list_first_entry(&ring->request_list,
1748 struct drm_i915_gem_request,
1750 retiring_seqno = request->seqno;
1752 if (i915_seqno_passed(seqno, retiring_seqno) ||
1753 atomic_read(&dev_priv->mm.wedged)) {
1754 i915_gem_retire_request(dev, request);
1756 list_del(&request->list);
1757 list_del(&request->client_list);
1763 if (unlikely (dev_priv->trace_irq_seqno &&
1764 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1766 ring->user_irq_put(dev, ring);
1767 dev_priv->trace_irq_seqno = 0;
1772 i915_gem_retire_requests(struct drm_device *dev)
1774 drm_i915_private_t *dev_priv = dev->dev_private;
1776 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1777 struct drm_i915_gem_object *obj_priv, *tmp;
1779 /* We must be careful that during unbind() we do not
1780 * accidentally infinitely recurse into retire requests.
1782 * retire -> free -> unbind -> wait -> retire_ring
1784 list_for_each_entry_safe(obj_priv, tmp,
1785 &dev_priv->mm.deferred_free_list,
1787 i915_gem_free_object_tail(&obj_priv->base);
1790 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1792 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1796 i915_gem_retire_work_handler(struct work_struct *work)
1798 drm_i915_private_t *dev_priv;
1799 struct drm_device *dev;
1801 dev_priv = container_of(work, drm_i915_private_t,
1802 mm.retire_work.work);
1803 dev = dev_priv->dev;
1805 mutex_lock(&dev->struct_mutex);
1806 i915_gem_retire_requests(dev);
1808 if (!dev_priv->mm.suspended &&
1809 (!list_empty(&dev_priv->render_ring.request_list) ||
1811 !list_empty(&dev_priv->bsd_ring.request_list))))
1812 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1813 mutex_unlock(&dev->struct_mutex);
1817 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1818 bool interruptible, struct intel_ring_buffer *ring)
1820 drm_i915_private_t *dev_priv = dev->dev_private;
1826 if (seqno == dev_priv->next_seqno) {
1827 seqno = i915_add_request(dev, NULL, NULL, ring);
1832 if (atomic_read(&dev_priv->mm.wedged))
1835 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1836 if (HAS_PCH_SPLIT(dev))
1837 ier = I915_READ(DEIER) | I915_READ(GTIER);
1839 ier = I915_READ(IER);
1841 DRM_ERROR("something (likely vbetool) disabled "
1842 "interrupts, re-enabling\n");
1843 i915_driver_irq_preinstall(dev);
1844 i915_driver_irq_postinstall(dev);
1847 trace_i915_gem_request_wait_begin(dev, seqno);
1849 ring->waiting_gem_seqno = seqno;
1850 ring->user_irq_get(dev, ring);
1852 ret = wait_event_interruptible(ring->irq_queue,
1854 ring->get_gem_seqno(dev, ring), seqno)
1855 || atomic_read(&dev_priv->mm.wedged));
1857 wait_event(ring->irq_queue,
1859 ring->get_gem_seqno(dev, ring), seqno)
1860 || atomic_read(&dev_priv->mm.wedged));
1862 ring->user_irq_put(dev, ring);
1863 ring->waiting_gem_seqno = 0;
1865 trace_i915_gem_request_wait_end(dev, seqno);
1867 if (atomic_read(&dev_priv->mm.wedged))
1870 if (ret && ret != -ERESTARTSYS)
1871 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1872 __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1873 dev_priv->next_seqno);
1875 /* Directly dispatch request retiring. While we have the work queue
1876 * to handle this, the waiter on a request often wants an associated
1877 * buffer to have made it to the inactive list, and we would need
1878 * a separate wait queue to handle that.
1881 i915_gem_retire_requests_ring(dev, ring);
1887 * Waits for a sequence number to be signaled, and cleans up the
1888 * request and object lists appropriately for that event.
1891 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1892 struct intel_ring_buffer *ring)
1894 return i915_do_wait_request(dev, seqno, 1, ring);
1898 i915_gem_flush(struct drm_device *dev,
1899 uint32_t invalidate_domains,
1900 uint32_t flush_domains)
1902 drm_i915_private_t *dev_priv = dev->dev_private;
1904 if (flush_domains & I915_GEM_DOMAIN_CPU)
1905 drm_agp_chipset_flush(dev);
1907 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1912 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1918 * Ensures that all rendering to the object has completed and the object is
1919 * safe to unbind from the GTT or access from the CPU.
1922 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1925 struct drm_device *dev = obj->dev;
1926 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1929 /* This function only exists to support waiting for existing rendering,
1930 * not for emitting required flushes.
1932 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1934 /* If there is rendering queued on the buffer being evicted, wait for
1937 if (obj_priv->active) {
1939 DRM_INFO("%s: object %p wait for seqno %08x\n",
1940 __func__, obj, obj_priv->last_rendering_seqno);
1942 ret = i915_do_wait_request(dev,
1943 obj_priv->last_rendering_seqno,
1954 * Unbinds an object from the GTT aperture.
1957 i915_gem_object_unbind(struct drm_gem_object *obj)
1959 struct drm_device *dev = obj->dev;
1960 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1964 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1965 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1967 if (obj_priv->gtt_space == NULL)
1970 if (obj_priv->pin_count != 0) {
1971 DRM_ERROR("Attempting to unbind pinned buffer\n");
1975 /* blow away mappings if mapped through GTT */
1976 i915_gem_release_mmap(obj);
1978 /* Move the object to the CPU domain to ensure that
1979 * any possible CPU writes while it's not in the GTT
1980 * are flushed when we go to remap it. This will
1981 * also ensure that all pending GPU writes are finished
1984 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1985 if (ret == -ERESTARTSYS)
1987 /* Continue on if we fail due to EIO, the GPU is hung so we
1988 * should be safe and we need to cleanup or else we might
1989 * cause memory corruption through use-after-free.
1992 /* release the fence reg _after_ flushing */
1993 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1994 i915_gem_clear_fence_reg(obj);
1996 if (obj_priv->agp_mem != NULL) {
1997 drm_unbind_agp(obj_priv->agp_mem);
1998 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1999 obj_priv->agp_mem = NULL;
2002 i915_gem_object_put_pages(obj);
2003 BUG_ON(obj_priv->pages_refcount);
2005 if (obj_priv->gtt_space) {
2006 atomic_dec(&dev->gtt_count);
2007 atomic_sub(obj->size, &dev->gtt_memory);
2009 drm_mm_put_block(obj_priv->gtt_space);
2010 obj_priv->gtt_space = NULL;
2013 /* Remove ourselves from the LRU list if present. */
2014 if (!list_empty(&obj_priv->list))
2015 list_del_init(&obj_priv->list);
2017 if (i915_gem_object_is_purgeable(obj_priv))
2018 i915_gem_object_truncate(obj);
2020 trace_i915_gem_object_unbind(obj);
2026 i915_gpu_idle(struct drm_device *dev)
2028 drm_i915_private_t *dev_priv = dev->dev_private;
2032 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2033 list_empty(&dev_priv->render_ring.active_list) &&
2035 list_empty(&dev_priv->bsd_ring.active_list)));
2039 /* Flush everything onto the inactive list. */
2040 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2042 ret = i915_wait_request(dev,
2043 i915_gem_next_request_seqno(dev, &dev_priv->render_ring),
2044 &dev_priv->render_ring);
2049 ret = i915_wait_request(dev,
2050 i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring),
2051 &dev_priv->bsd_ring);
2060 i915_gem_object_get_pages(struct drm_gem_object *obj,
2063 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2065 struct address_space *mapping;
2066 struct inode *inode;
2069 BUG_ON(obj_priv->pages_refcount
2070 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2072 if (obj_priv->pages_refcount++ != 0)
2075 /* Get the list of pages out of our struct file. They'll be pinned
2076 * at this point until we release them.
2078 page_count = obj->size / PAGE_SIZE;
2079 BUG_ON(obj_priv->pages != NULL);
2080 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2081 if (obj_priv->pages == NULL) {
2082 obj_priv->pages_refcount--;
2086 inode = obj->filp->f_path.dentry->d_inode;
2087 mapping = inode->i_mapping;
2088 for (i = 0; i < page_count; i++) {
2089 page = read_cache_page_gfp(mapping, i,
2097 obj_priv->pages[i] = page;
2100 if (obj_priv->tiling_mode != I915_TILING_NONE)
2101 i915_gem_object_do_bit_17_swizzle(obj);
2107 page_cache_release(obj_priv->pages[i]);
2109 drm_free_large(obj_priv->pages);
2110 obj_priv->pages = NULL;
2111 obj_priv->pages_refcount--;
2112 return PTR_ERR(page);
2115 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2117 struct drm_gem_object *obj = reg->obj;
2118 struct drm_device *dev = obj->dev;
2119 drm_i915_private_t *dev_priv = dev->dev_private;
2120 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2121 int regnum = obj_priv->fence_reg;
2124 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2126 val |= obj_priv->gtt_offset & 0xfffff000;
2127 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2128 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2130 if (obj_priv->tiling_mode == I915_TILING_Y)
2131 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2132 val |= I965_FENCE_REG_VALID;
2134 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2137 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2139 struct drm_gem_object *obj = reg->obj;
2140 struct drm_device *dev = obj->dev;
2141 drm_i915_private_t *dev_priv = dev->dev_private;
2142 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2143 int regnum = obj_priv->fence_reg;
2146 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2148 val |= obj_priv->gtt_offset & 0xfffff000;
2149 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2150 if (obj_priv->tiling_mode == I915_TILING_Y)
2151 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2152 val |= I965_FENCE_REG_VALID;
2154 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2157 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2159 struct drm_gem_object *obj = reg->obj;
2160 struct drm_device *dev = obj->dev;
2161 drm_i915_private_t *dev_priv = dev->dev_private;
2162 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2163 int regnum = obj_priv->fence_reg;
2165 uint32_t fence_reg, val;
2168 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2169 (obj_priv->gtt_offset & (obj->size - 1))) {
2170 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2171 __func__, obj_priv->gtt_offset, obj->size);
2175 if (obj_priv->tiling_mode == I915_TILING_Y &&
2176 HAS_128_BYTE_Y_TILING(dev))
2181 /* Note: pitch better be a power of two tile widths */
2182 pitch_val = obj_priv->stride / tile_width;
2183 pitch_val = ffs(pitch_val) - 1;
2185 if (obj_priv->tiling_mode == I915_TILING_Y &&
2186 HAS_128_BYTE_Y_TILING(dev))
2187 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2189 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2191 val = obj_priv->gtt_offset;
2192 if (obj_priv->tiling_mode == I915_TILING_Y)
2193 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2194 val |= I915_FENCE_SIZE_BITS(obj->size);
2195 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2196 val |= I830_FENCE_REG_VALID;
2199 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2201 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2202 I915_WRITE(fence_reg, val);
2205 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2207 struct drm_gem_object *obj = reg->obj;
2208 struct drm_device *dev = obj->dev;
2209 drm_i915_private_t *dev_priv = dev->dev_private;
2210 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2211 int regnum = obj_priv->fence_reg;
2214 uint32_t fence_size_bits;
2216 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2217 (obj_priv->gtt_offset & (obj->size - 1))) {
2218 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2219 __func__, obj_priv->gtt_offset);
2223 pitch_val = obj_priv->stride / 128;
2224 pitch_val = ffs(pitch_val) - 1;
2225 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2227 val = obj_priv->gtt_offset;
2228 if (obj_priv->tiling_mode == I915_TILING_Y)
2229 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2230 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2231 WARN_ON(fence_size_bits & ~0x00000f00);
2232 val |= fence_size_bits;
2233 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2234 val |= I830_FENCE_REG_VALID;
2236 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2239 static int i915_find_fence_reg(struct drm_device *dev,
2242 struct drm_i915_fence_reg *reg = NULL;
2243 struct drm_i915_gem_object *obj_priv = NULL;
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct drm_gem_object *obj = NULL;
2248 /* First try to find a free reg */
2250 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2251 reg = &dev_priv->fence_regs[i];
2255 obj_priv = to_intel_bo(reg->obj);
2256 if (!obj_priv->pin_count)
2263 /* None available, try to steal one or wait for a user to finish */
2264 i = I915_FENCE_REG_NONE;
2265 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2268 obj_priv = to_intel_bo(obj);
2270 if (obj_priv->pin_count)
2274 i = obj_priv->fence_reg;
2278 BUG_ON(i == I915_FENCE_REG_NONE);
2280 /* We only have a reference on obj from the active list. put_fence_reg
2281 * might drop that one, causing a use-after-free in it. So hold a
2282 * private reference to obj like the other callers of put_fence_reg
2283 * (set_tiling ioctl) do. */
2284 drm_gem_object_reference(obj);
2285 ret = i915_gem_object_put_fence_reg(obj, interruptible);
2286 drm_gem_object_unreference(obj);
2294 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2295 * @obj: object to map through a fence reg
2297 * When mapping objects through the GTT, userspace wants to be able to write
2298 * to them without having to worry about swizzling if the object is tiled.
2300 * This function walks the fence regs looking for a free one for @obj,
2301 * stealing one if it can't find any.
2303 * It then sets up the reg based on the object's properties: address, pitch
2304 * and tiling format.
2307 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2310 struct drm_device *dev = obj->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2313 struct drm_i915_fence_reg *reg = NULL;
2316 /* Just update our place in the LRU if our fence is getting used. */
2317 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2318 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2319 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2323 switch (obj_priv->tiling_mode) {
2324 case I915_TILING_NONE:
2325 WARN(1, "allocating a fence for non-tiled object?\n");
2328 if (!obj_priv->stride)
2330 WARN((obj_priv->stride & (512 - 1)),
2331 "object 0x%08x is X tiled but has non-512B pitch\n",
2332 obj_priv->gtt_offset);
2335 if (!obj_priv->stride)
2337 WARN((obj_priv->stride & (128 - 1)),
2338 "object 0x%08x is Y tiled but has non-128B pitch\n",
2339 obj_priv->gtt_offset);
2343 ret = i915_find_fence_reg(dev, interruptible);
2347 obj_priv->fence_reg = ret;
2348 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2349 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2353 switch (INTEL_INFO(dev)->gen) {
2355 sandybridge_write_fence_reg(reg);
2359 i965_write_fence_reg(reg);
2362 i915_write_fence_reg(reg);
2365 i830_write_fence_reg(reg);
2369 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2370 obj_priv->tiling_mode);
2376 * i915_gem_clear_fence_reg - clear out fence register info
2377 * @obj: object to clear
2379 * Zeroes out the fence register itself and clears out the associated
2380 * data structures in dev_priv and obj_priv.
2383 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2385 struct drm_device *dev = obj->dev;
2386 drm_i915_private_t *dev_priv = dev->dev_private;
2387 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2388 struct drm_i915_fence_reg *reg =
2389 &dev_priv->fence_regs[obj_priv->fence_reg];
2392 switch (INTEL_INFO(dev)->gen) {
2394 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2395 (obj_priv->fence_reg * 8), 0);
2399 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2402 if (obj_priv->fence_reg > 8)
2403 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2406 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2408 I915_WRITE(fence_reg, 0);
2413 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2414 list_del_init(®->lru_list);
2418 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2419 * to the buffer to finish, and then resets the fence register.
2420 * @obj: tiled object holding a fence register.
2421 * @bool: whether the wait upon the fence is interruptible
2423 * Zeroes out the fence register itself and clears out the associated
2424 * data structures in dev_priv and obj_priv.
2427 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2430 struct drm_device *dev = obj->dev;
2431 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2433 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2436 /* If we've changed tiling, GTT-mappings of the object
2437 * need to re-fault to ensure that the correct fence register
2438 * setup is in place.
2440 i915_gem_release_mmap(obj);
2442 /* On the i915, GPU access to tiled buffers is via a fence,
2443 * therefore we must wait for any outstanding access to complete
2444 * before clearing the fence.
2446 if (!IS_I965G(dev)) {
2449 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2453 ret = i915_gem_object_wait_rendering(obj, interruptible);
2458 i915_gem_object_flush_gtt_write_domain(obj);
2459 i915_gem_clear_fence_reg(obj);
2465 * Finds free space in the GTT aperture and binds the object there.
2468 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2470 struct drm_device *dev = obj->dev;
2471 drm_i915_private_t *dev_priv = dev->dev_private;
2472 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2473 struct drm_mm_node *free_space;
2474 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2477 if (obj_priv->madv != I915_MADV_WILLNEED) {
2478 DRM_ERROR("Attempting to bind a purgeable object\n");
2483 alignment = i915_gem_get_gtt_alignment(obj);
2484 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2485 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2489 /* If the object is bigger than the entire aperture, reject it early
2490 * before evicting everything in a vain attempt to find space.
2492 if (obj->size > dev->gtt_total) {
2493 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2498 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2499 obj->size, alignment, 0);
2500 if (free_space != NULL) {
2501 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2503 if (obj_priv->gtt_space != NULL)
2504 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2506 if (obj_priv->gtt_space == NULL) {
2507 /* If the gtt is empty and we're still having trouble
2508 * fitting our object in, we're out of memory.
2511 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2513 ret = i915_gem_evict_something(dev, obj->size, alignment);
2521 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2522 obj->size, obj_priv->gtt_offset);
2524 ret = i915_gem_object_get_pages(obj, gfpmask);
2526 drm_mm_put_block(obj_priv->gtt_space);
2527 obj_priv->gtt_space = NULL;
2529 if (ret == -ENOMEM) {
2530 /* first try to clear up some space from the GTT */
2531 ret = i915_gem_evict_something(dev, obj->size,
2534 /* now try to shrink everyone else */
2549 /* Create an AGP memory structure pointing at our pages, and bind it
2552 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2554 obj->size >> PAGE_SHIFT,
2555 obj_priv->gtt_offset,
2556 obj_priv->agp_type);
2557 if (obj_priv->agp_mem == NULL) {
2558 i915_gem_object_put_pages(obj);
2559 drm_mm_put_block(obj_priv->gtt_space);
2560 obj_priv->gtt_space = NULL;
2562 ret = i915_gem_evict_something(dev, obj->size, alignment);
2568 atomic_inc(&dev->gtt_count);
2569 atomic_add(obj->size, &dev->gtt_memory);
2571 /* keep track of bounds object by adding it to the inactive list */
2572 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2574 /* Assert that the object is not currently in any GPU domain. As it
2575 * wasn't in the GTT, there shouldn't be any way it could have been in
2578 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2579 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2581 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2587 i915_gem_clflush_object(struct drm_gem_object *obj)
2589 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2591 /* If we don't have a page list set up, then we're not pinned
2592 * to GPU, and we can ignore the cache flush because it'll happen
2593 * again at bind time.
2595 if (obj_priv->pages == NULL)
2598 trace_i915_gem_object_clflush(obj);
2600 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2603 /** Flushes any GPU write domain for the object if it's dirty. */
2605 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2608 struct drm_device *dev = obj->dev;
2609 uint32_t old_write_domain;
2611 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2614 /* Queue the GPU write cache flushing we need. */
2615 old_write_domain = obj->write_domain;
2616 i915_gem_flush(dev, 0, obj->write_domain);
2617 BUG_ON(obj->write_domain);
2619 trace_i915_gem_object_change_domain(obj,
2626 return i915_gem_object_wait_rendering(obj, true);
2629 /** Flushes the GTT write domain for the object if it's dirty. */
2631 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2633 uint32_t old_write_domain;
2635 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2638 /* No actual flushing is required for the GTT write domain. Writes
2639 * to it immediately go to main memory as far as we know, so there's
2640 * no chipset flush. It also doesn't land in render cache.
2642 old_write_domain = obj->write_domain;
2643 obj->write_domain = 0;
2645 trace_i915_gem_object_change_domain(obj,
2650 /** Flushes the CPU write domain for the object if it's dirty. */
2652 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2654 struct drm_device *dev = obj->dev;
2655 uint32_t old_write_domain;
2657 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2660 i915_gem_clflush_object(obj);
2661 drm_agp_chipset_flush(dev);
2662 old_write_domain = obj->write_domain;
2663 obj->write_domain = 0;
2665 trace_i915_gem_object_change_domain(obj,
2671 * Moves a single object to the GTT read, and possibly write domain.
2673 * This function returns when the move is complete, including waiting on
2677 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2679 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2680 uint32_t old_write_domain, old_read_domains;
2683 /* Not valid to be called on unbound objects. */
2684 if (obj_priv->gtt_space == NULL)
2687 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2691 i915_gem_object_flush_cpu_write_domain(obj);
2694 ret = i915_gem_object_wait_rendering(obj, true);
2699 old_write_domain = obj->write_domain;
2700 old_read_domains = obj->read_domains;
2702 /* It should now be out of any other write domains, and we can update
2703 * the domain values for our changes.
2705 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2706 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2708 obj->read_domains = I915_GEM_DOMAIN_GTT;
2709 obj->write_domain = I915_GEM_DOMAIN_GTT;
2710 obj_priv->dirty = 1;
2713 trace_i915_gem_object_change_domain(obj,
2721 * Prepare buffer for display plane. Use uninterruptible for possible flush
2722 * wait, as in modesetting process we're not supposed to be interrupted.
2725 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2728 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2729 uint32_t old_read_domains;
2732 /* Not valid to be called on unbound objects. */
2733 if (obj_priv->gtt_space == NULL)
2736 ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
2740 i915_gem_object_flush_cpu_write_domain(obj);
2742 old_read_domains = obj->read_domains;
2743 obj->read_domains = I915_GEM_DOMAIN_GTT;
2745 trace_i915_gem_object_change_domain(obj,
2753 * Moves a single object to the CPU read, and possibly write domain.
2755 * This function returns when the move is complete, including waiting on
2759 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2761 uint32_t old_write_domain, old_read_domains;
2764 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2768 i915_gem_object_flush_gtt_write_domain(obj);
2770 /* If we have a partially-valid cache of the object in the CPU,
2771 * finish invalidating it and free the per-page flags.
2773 i915_gem_object_set_to_full_cpu_read_domain(obj);
2776 ret = i915_gem_object_wait_rendering(obj, true);
2781 old_write_domain = obj->write_domain;
2782 old_read_domains = obj->read_domains;
2784 /* Flush the CPU cache if it's still invalid. */
2785 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2786 i915_gem_clflush_object(obj);
2788 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2791 /* It should now be out of any other write domains, and we can update
2792 * the domain values for our changes.
2794 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2796 /* If we're writing through the CPU, then the GPU read domains will
2797 * need to be invalidated at next use.
2800 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2801 obj->write_domain = I915_GEM_DOMAIN_CPU;
2804 trace_i915_gem_object_change_domain(obj,
2812 * Set the next domain for the specified object. This
2813 * may not actually perform the necessary flushing/invaliding though,
2814 * as that may want to be batched with other set_domain operations
2816 * This is (we hope) the only really tricky part of gem. The goal
2817 * is fairly simple -- track which caches hold bits of the object
2818 * and make sure they remain coherent. A few concrete examples may
2819 * help to explain how it works. For shorthand, we use the notation
2820 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2821 * a pair of read and write domain masks.
2823 * Case 1: the batch buffer
2829 * 5. Unmapped from GTT
2832 * Let's take these a step at a time
2835 * Pages allocated from the kernel may still have
2836 * cache contents, so we set them to (CPU, CPU) always.
2837 * 2. Written by CPU (using pwrite)
2838 * The pwrite function calls set_domain (CPU, CPU) and
2839 * this function does nothing (as nothing changes)
2841 * This function asserts that the object is not
2842 * currently in any GPU-based read or write domains
2844 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2845 * As write_domain is zero, this function adds in the
2846 * current read domains (CPU+COMMAND, 0).
2847 * flush_domains is set to CPU.
2848 * invalidate_domains is set to COMMAND
2849 * clflush is run to get data out of the CPU caches
2850 * then i915_dev_set_domain calls i915_gem_flush to
2851 * emit an MI_FLUSH and drm_agp_chipset_flush
2852 * 5. Unmapped from GTT
2853 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2854 * flush_domains and invalidate_domains end up both zero
2855 * so no flushing/invalidating happens
2859 * Case 2: The shared render buffer
2863 * 3. Read/written by GPU
2864 * 4. set_domain to (CPU,CPU)
2865 * 5. Read/written by CPU
2866 * 6. Read/written by GPU
2869 * Same as last example, (CPU, CPU)
2871 * Nothing changes (assertions find that it is not in the GPU)
2872 * 3. Read/written by GPU
2873 * execbuffer calls set_domain (RENDER, RENDER)
2874 * flush_domains gets CPU
2875 * invalidate_domains gets GPU
2877 * MI_FLUSH and drm_agp_chipset_flush
2878 * 4. set_domain (CPU, CPU)
2879 * flush_domains gets GPU
2880 * invalidate_domains gets CPU
2881 * wait_rendering (obj) to make sure all drawing is complete.
2882 * This will include an MI_FLUSH to get the data from GPU
2884 * clflush (obj) to invalidate the CPU cache
2885 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2886 * 5. Read/written by CPU
2887 * cache lines are loaded and dirtied
2888 * 6. Read written by GPU
2889 * Same as last GPU access
2891 * Case 3: The constant buffer
2896 * 4. Updated (written) by CPU again
2905 * flush_domains = CPU
2906 * invalidate_domains = RENDER
2909 * drm_agp_chipset_flush
2910 * 4. Updated (written) by CPU again
2912 * flush_domains = 0 (no previous write domain)
2913 * invalidate_domains = 0 (no new read domains)
2916 * flush_domains = CPU
2917 * invalidate_domains = RENDER
2920 * drm_agp_chipset_flush
2923 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2925 struct drm_device *dev = obj->dev;
2926 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2927 uint32_t invalidate_domains = 0;
2928 uint32_t flush_domains = 0;
2929 uint32_t old_read_domains;
2931 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2932 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2934 intel_mark_busy(dev, obj);
2937 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2939 obj->read_domains, obj->pending_read_domains,
2940 obj->write_domain, obj->pending_write_domain);
2943 * If the object isn't moving to a new write domain,
2944 * let the object stay in multiple read domains
2946 if (obj->pending_write_domain == 0)
2947 obj->pending_read_domains |= obj->read_domains;
2949 obj_priv->dirty = 1;
2952 * Flush the current write domain if
2953 * the new read domains don't match. Invalidate
2954 * any read domains which differ from the old
2957 if (obj->write_domain &&
2958 obj->write_domain != obj->pending_read_domains) {
2959 flush_domains |= obj->write_domain;
2960 invalidate_domains |=
2961 obj->pending_read_domains & ~obj->write_domain;
2964 * Invalidate any read caches which may have
2965 * stale data. That is, any new read domains.
2967 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2968 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2970 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2971 __func__, flush_domains, invalidate_domains);
2973 i915_gem_clflush_object(obj);
2976 old_read_domains = obj->read_domains;
2978 /* The actual obj->write_domain will be updated with
2979 * pending_write_domain after we emit the accumulated flush for all
2980 * of our domain changes in execbuffers (which clears objects'
2981 * write_domains). So if we have a current write domain that we
2982 * aren't changing, set pending_write_domain to that.
2984 if (flush_domains == 0 && obj->pending_write_domain == 0)
2985 obj->pending_write_domain = obj->write_domain;
2986 obj->read_domains = obj->pending_read_domains;
2988 dev->invalidate_domains |= invalidate_domains;
2989 dev->flush_domains |= flush_domains;
2991 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2993 obj->read_domains, obj->write_domain,
2994 dev->invalidate_domains, dev->flush_domains);
2997 trace_i915_gem_object_change_domain(obj,
3003 * Moves the object from a partially CPU read to a full one.
3005 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3006 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3009 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3011 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3013 if (!obj_priv->page_cpu_valid)
3016 /* If we're partially in the CPU read domain, finish moving it in.
3018 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3021 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3022 if (obj_priv->page_cpu_valid[i])
3024 drm_clflush_pages(obj_priv->pages + i, 1);
3028 /* Free the page_cpu_valid mappings which are now stale, whether
3029 * or not we've got I915_GEM_DOMAIN_CPU.
3031 kfree(obj_priv->page_cpu_valid);
3032 obj_priv->page_cpu_valid = NULL;
3036 * Set the CPU read domain on a range of the object.
3038 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3039 * not entirely valid. The page_cpu_valid member of the object flags which
3040 * pages have been flushed, and will be respected by
3041 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3042 * of the whole object.
3044 * This function returns when the move is complete, including waiting on
3048 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3049 uint64_t offset, uint64_t size)
3051 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3052 uint32_t old_read_domains;
3055 if (offset == 0 && size == obj->size)
3056 return i915_gem_object_set_to_cpu_domain(obj, 0);
3058 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3061 i915_gem_object_flush_gtt_write_domain(obj);
3063 /* If we're already fully in the CPU read domain, we're done. */
3064 if (obj_priv->page_cpu_valid == NULL &&
3065 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3068 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3069 * newly adding I915_GEM_DOMAIN_CPU
3071 if (obj_priv->page_cpu_valid == NULL) {
3072 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3074 if (obj_priv->page_cpu_valid == NULL)
3076 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3077 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3079 /* Flush the cache on any pages that are still invalid from the CPU's
3082 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3084 if (obj_priv->page_cpu_valid[i])
3087 drm_clflush_pages(obj_priv->pages + i, 1);
3089 obj_priv->page_cpu_valid[i] = 1;
3092 /* It should now be out of any other write domains, and we can update
3093 * the domain values for our changes.
3095 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3097 old_read_domains = obj->read_domains;
3098 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3100 trace_i915_gem_object_change_domain(obj,
3108 * Pin an object to the GTT and evaluate the relocations landing in it.
3111 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3112 struct drm_file *file_priv,
3113 struct drm_i915_gem_exec_object2 *entry,
3114 struct drm_i915_gem_relocation_entry *relocs)
3116 struct drm_device *dev = obj->dev;
3117 drm_i915_private_t *dev_priv = dev->dev_private;
3118 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3120 void __iomem *reloc_page;
3123 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3124 obj_priv->tiling_mode != I915_TILING_NONE;
3126 /* Check fence reg constraints and rebind if necessary */
3128 !i915_gem_object_fence_offset_ok(obj,
3129 obj_priv->tiling_mode)) {
3130 ret = i915_gem_object_unbind(obj);
3135 /* Choose the GTT offset for our buffer and put it there. */
3136 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3141 * Pre-965 chips need a fence register set up in order to
3142 * properly handle blits to/from tiled surfaces.
3145 ret = i915_gem_object_get_fence_reg(obj, false);
3147 i915_gem_object_unpin(obj);
3152 entry->offset = obj_priv->gtt_offset;
3154 /* Apply the relocations, using the GTT aperture to avoid cache
3155 * flushing requirements.
3157 for (i = 0; i < entry->relocation_count; i++) {
3158 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3159 struct drm_gem_object *target_obj;
3160 struct drm_i915_gem_object *target_obj_priv;
3161 uint32_t reloc_val, reloc_offset;
3162 uint32_t __iomem *reloc_entry;
3164 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3165 reloc->target_handle);
3166 if (target_obj == NULL) {
3167 i915_gem_object_unpin(obj);
3170 target_obj_priv = to_intel_bo(target_obj);
3173 DRM_INFO("%s: obj %p offset %08x target %d "
3174 "read %08x write %08x gtt %08x "
3175 "presumed %08x delta %08x\n",
3178 (int) reloc->offset,
3179 (int) reloc->target_handle,
3180 (int) reloc->read_domains,
3181 (int) reloc->write_domain,
3182 (int) target_obj_priv->gtt_offset,
3183 (int) reloc->presumed_offset,
3187 /* The target buffer should have appeared before us in the
3188 * exec_object list, so it should have a GTT space bound by now.
3190 if (target_obj_priv->gtt_space == NULL) {
3191 DRM_ERROR("No GTT space found for object %d\n",
3192 reloc->target_handle);
3193 drm_gem_object_unreference(target_obj);
3194 i915_gem_object_unpin(obj);
3198 /* Validate that the target is in a valid r/w GPU domain */
3199 if (reloc->write_domain & (reloc->write_domain - 1)) {
3200 DRM_ERROR("reloc with multiple write domains: "
3201 "obj %p target %d offset %d "
3202 "read %08x write %08x",
3203 obj, reloc->target_handle,
3204 (int) reloc->offset,
3205 reloc->read_domains,
3206 reloc->write_domain);
3209 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3210 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3211 DRM_ERROR("reloc with read/write CPU domains: "
3212 "obj %p target %d offset %d "
3213 "read %08x write %08x",
3214 obj, reloc->target_handle,
3215 (int) reloc->offset,
3216 reloc->read_domains,
3217 reloc->write_domain);
3218 drm_gem_object_unreference(target_obj);
3219 i915_gem_object_unpin(obj);
3222 if (reloc->write_domain && target_obj->pending_write_domain &&
3223 reloc->write_domain != target_obj->pending_write_domain) {
3224 DRM_ERROR("Write domain conflict: "
3225 "obj %p target %d offset %d "
3226 "new %08x old %08x\n",
3227 obj, reloc->target_handle,
3228 (int) reloc->offset,
3229 reloc->write_domain,
3230 target_obj->pending_write_domain);
3231 drm_gem_object_unreference(target_obj);
3232 i915_gem_object_unpin(obj);
3236 target_obj->pending_read_domains |= reloc->read_domains;
3237 target_obj->pending_write_domain |= reloc->write_domain;
3239 /* If the relocation already has the right value in it, no
3240 * more work needs to be done.
3242 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3243 drm_gem_object_unreference(target_obj);
3247 /* Check that the relocation address is valid... */
3248 if (reloc->offset > obj->size - 4) {
3249 DRM_ERROR("Relocation beyond object bounds: "
3250 "obj %p target %d offset %d size %d.\n",
3251 obj, reloc->target_handle,
3252 (int) reloc->offset, (int) obj->size);
3253 drm_gem_object_unreference(target_obj);
3254 i915_gem_object_unpin(obj);
3257 if (reloc->offset & 3) {
3258 DRM_ERROR("Relocation not 4-byte aligned: "
3259 "obj %p target %d offset %d.\n",
3260 obj, reloc->target_handle,
3261 (int) reloc->offset);
3262 drm_gem_object_unreference(target_obj);
3263 i915_gem_object_unpin(obj);
3267 /* and points to somewhere within the target object. */
3268 if (reloc->delta >= target_obj->size) {
3269 DRM_ERROR("Relocation beyond target object bounds: "
3270 "obj %p target %d delta %d size %d.\n",
3271 obj, reloc->target_handle,
3272 (int) reloc->delta, (int) target_obj->size);
3273 drm_gem_object_unreference(target_obj);
3274 i915_gem_object_unpin(obj);
3278 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3280 drm_gem_object_unreference(target_obj);
3281 i915_gem_object_unpin(obj);
3285 /* Map the page containing the relocation we're going to
3288 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3289 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3293 reloc_entry = (uint32_t __iomem *)(reloc_page +
3294 (reloc_offset & (PAGE_SIZE - 1)));
3295 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3298 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3299 obj, (unsigned int) reloc->offset,
3300 readl(reloc_entry), reloc_val);
3302 writel(reloc_val, reloc_entry);
3303 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3305 /* The updated presumed offset for this entry will be
3306 * copied back out to the user.
3308 reloc->presumed_offset = target_obj_priv->gtt_offset;
3310 drm_gem_object_unreference(target_obj);
3315 i915_gem_dump_object(obj, 128, __func__, ~0);
3320 /* Throttle our rendering by waiting until the ring has completed our requests
3321 * emitted over 20 msec ago.
3323 * Note that if we were to use the current jiffies each time around the loop,
3324 * we wouldn't escape the function with any frames outstanding if the time to
3325 * render a frame was over 20ms.
3327 * This should get us reasonable parallelism between CPU and GPU but also
3328 * relatively low latency when blocking on a particular request to finish.
3331 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3333 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3335 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3337 mutex_lock(&dev->struct_mutex);
3338 while (!list_empty(&i915_file_priv->mm.request_list)) {
3339 struct drm_i915_gem_request *request;
3341 request = list_first_entry(&i915_file_priv->mm.request_list,
3342 struct drm_i915_gem_request,
3345 if (time_after_eq(request->emitted_jiffies, recent_enough))
3348 ret = i915_wait_request(dev, request->seqno, request->ring);
3352 mutex_unlock(&dev->struct_mutex);
3358 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3359 uint32_t buffer_count,
3360 struct drm_i915_gem_relocation_entry **relocs)
3362 uint32_t reloc_count = 0, reloc_index = 0, i;
3366 for (i = 0; i < buffer_count; i++) {
3367 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3369 reloc_count += exec_list[i].relocation_count;
3372 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3373 if (*relocs == NULL) {
3374 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3378 for (i = 0; i < buffer_count; i++) {
3379 struct drm_i915_gem_relocation_entry __user *user_relocs;
3381 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3383 ret = copy_from_user(&(*relocs)[reloc_index],
3385 exec_list[i].relocation_count *
3388 drm_free_large(*relocs);
3393 reloc_index += exec_list[i].relocation_count;
3400 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3401 uint32_t buffer_count,
3402 struct drm_i915_gem_relocation_entry *relocs)
3404 uint32_t reloc_count = 0, i;
3410 for (i = 0; i < buffer_count; i++) {
3411 struct drm_i915_gem_relocation_entry __user *user_relocs;
3414 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3416 unwritten = copy_to_user(user_relocs,
3417 &relocs[reloc_count],
3418 exec_list[i].relocation_count *
3426 reloc_count += exec_list[i].relocation_count;
3430 drm_free_large(relocs);
3436 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3437 uint64_t exec_offset)
3439 uint32_t exec_start, exec_len;
3441 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3442 exec_len = (uint32_t) exec->batch_len;
3444 if ((exec_start | exec_len) & 0x7)
3454 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3455 struct drm_gem_object **object_list,
3458 drm_i915_private_t *dev_priv = dev->dev_private;
3459 struct drm_i915_gem_object *obj_priv;
3464 prepare_to_wait(&dev_priv->pending_flip_queue,
3465 &wait, TASK_INTERRUPTIBLE);
3466 for (i = 0; i < count; i++) {
3467 obj_priv = to_intel_bo(object_list[i]);
3468 if (atomic_read(&obj_priv->pending_flip) > 0)
3474 if (!signal_pending(current)) {
3475 mutex_unlock(&dev->struct_mutex);
3477 mutex_lock(&dev->struct_mutex);
3483 finish_wait(&dev_priv->pending_flip_queue, &wait);
3489 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3490 struct drm_file *file_priv,
3491 struct drm_i915_gem_execbuffer2 *args,
3492 struct drm_i915_gem_exec_object2 *exec_list)
3494 drm_i915_private_t *dev_priv = dev->dev_private;
3495 struct drm_gem_object **object_list = NULL;
3496 struct drm_gem_object *batch_obj;
3497 struct drm_i915_gem_object *obj_priv;
3498 struct drm_clip_rect *cliprects = NULL;
3499 struct drm_i915_gem_relocation_entry *relocs = NULL;
3500 struct drm_i915_gem_request *request = NULL;
3501 int ret = 0, ret2, i, pinned = 0;
3502 uint64_t exec_offset;
3503 uint32_t seqno, reloc_index;
3504 int pin_tries, flips;
3506 struct intel_ring_buffer *ring = NULL;
3509 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3510 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3512 if (args->flags & I915_EXEC_BSD) {
3513 if (!HAS_BSD(dev)) {
3514 DRM_ERROR("execbuf with wrong flag\n");
3517 ring = &dev_priv->bsd_ring;
3519 ring = &dev_priv->render_ring;
3522 if (args->buffer_count < 1) {
3523 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3526 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3527 if (object_list == NULL) {
3528 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3529 args->buffer_count);
3534 if (args->num_cliprects != 0) {
3535 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3537 if (cliprects == NULL) {
3542 ret = copy_from_user(cliprects,
3543 (struct drm_clip_rect __user *)
3544 (uintptr_t) args->cliprects_ptr,
3545 sizeof(*cliprects) * args->num_cliprects);
3547 DRM_ERROR("copy %d cliprects failed: %d\n",
3548 args->num_cliprects, ret);
3554 request = kzalloc(sizeof(*request), GFP_KERNEL);
3555 if (request == NULL) {
3560 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3565 mutex_lock(&dev->struct_mutex);
3567 i915_verify_inactive(dev, __FILE__, __LINE__);
3569 if (atomic_read(&dev_priv->mm.wedged)) {
3570 mutex_unlock(&dev->struct_mutex);
3575 if (dev_priv->mm.suspended) {
3576 mutex_unlock(&dev->struct_mutex);
3581 /* Look up object handles */
3583 for (i = 0; i < args->buffer_count; i++) {
3584 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3585 exec_list[i].handle);
3586 if (object_list[i] == NULL) {
3587 DRM_ERROR("Invalid object handle %d at index %d\n",
3588 exec_list[i].handle, i);
3589 /* prevent error path from reading uninitialized data */
3590 args->buffer_count = i + 1;
3595 obj_priv = to_intel_bo(object_list[i]);
3596 if (obj_priv->in_execbuffer) {
3597 DRM_ERROR("Object %p appears more than once in object list\n",
3599 /* prevent error path from reading uninitialized data */
3600 args->buffer_count = i + 1;
3604 obj_priv->in_execbuffer = true;
3605 flips += atomic_read(&obj_priv->pending_flip);
3609 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3610 args->buffer_count);
3615 /* Pin and relocate */
3616 for (pin_tries = 0; ; pin_tries++) {
3620 for (i = 0; i < args->buffer_count; i++) {
3621 object_list[i]->pending_read_domains = 0;
3622 object_list[i]->pending_write_domain = 0;
3623 ret = i915_gem_object_pin_and_relocate(object_list[i],
3626 &relocs[reloc_index]);
3630 reloc_index += exec_list[i].relocation_count;
3636 /* error other than GTT full, or we've already tried again */
3637 if (ret != -ENOSPC || pin_tries >= 1) {
3638 if (ret != -ERESTARTSYS) {
3639 unsigned long long total_size = 0;
3641 for (i = 0; i < args->buffer_count; i++) {
3642 obj_priv = to_intel_bo(object_list[i]);
3644 total_size += object_list[i]->size;
3646 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3647 obj_priv->tiling_mode != I915_TILING_NONE;
3649 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3650 pinned+1, args->buffer_count,
3651 total_size, num_fences,
3653 DRM_ERROR("%d objects [%d pinned], "
3654 "%d object bytes [%d pinned], "
3655 "%d/%d gtt bytes\n",
3656 atomic_read(&dev->object_count),
3657 atomic_read(&dev->pin_count),
3658 atomic_read(&dev->object_memory),
3659 atomic_read(&dev->pin_memory),
3660 atomic_read(&dev->gtt_memory),
3666 /* unpin all of our buffers */
3667 for (i = 0; i < pinned; i++)
3668 i915_gem_object_unpin(object_list[i]);
3671 /* evict everyone we can from the aperture */
3672 ret = i915_gem_evict_everything(dev);
3673 if (ret && ret != -ENOSPC)
3677 /* Set the pending read domains for the batch buffer to COMMAND */
3678 batch_obj = object_list[args->buffer_count-1];
3679 if (batch_obj->pending_write_domain) {
3680 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3684 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3686 /* Sanity check the batch buffer, prior to moving objects */
3687 exec_offset = exec_list[args->buffer_count - 1].offset;
3688 ret = i915_gem_check_execbuffer (args, exec_offset);
3690 DRM_ERROR("execbuf with invalid offset/length\n");
3694 i915_verify_inactive(dev, __FILE__, __LINE__);
3696 /* Zero the global flush/invalidate flags. These
3697 * will be modified as new domains are computed
3700 dev->invalidate_domains = 0;
3701 dev->flush_domains = 0;
3703 for (i = 0; i < args->buffer_count; i++) {
3704 struct drm_gem_object *obj = object_list[i];
3706 /* Compute new gpu domains and update invalidate/flush */
3707 i915_gem_object_set_to_gpu_domain(obj);
3710 i915_verify_inactive(dev, __FILE__, __LINE__);
3712 if (dev->invalidate_domains | dev->flush_domains) {
3714 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3716 dev->invalidate_domains,
3717 dev->flush_domains);
3720 dev->invalidate_domains,
3721 dev->flush_domains);
3724 if (dev_priv->render_ring.outstanding_lazy_request) {
3725 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring);
3726 dev_priv->render_ring.outstanding_lazy_request = false;
3728 if (dev_priv->bsd_ring.outstanding_lazy_request) {
3729 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring);
3730 dev_priv->bsd_ring.outstanding_lazy_request = false;
3733 for (i = 0; i < args->buffer_count; i++) {
3734 struct drm_gem_object *obj = object_list[i];
3735 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3736 uint32_t old_write_domain = obj->write_domain;
3738 obj->write_domain = obj->pending_write_domain;
3739 if (obj->write_domain)
3740 list_move_tail(&obj_priv->gpu_write_list,
3741 &dev_priv->mm.gpu_write_list);
3743 list_del_init(&obj_priv->gpu_write_list);
3745 trace_i915_gem_object_change_domain(obj,
3750 i915_verify_inactive(dev, __FILE__, __LINE__);
3753 for (i = 0; i < args->buffer_count; i++) {
3754 i915_gem_object_check_coherency(object_list[i],
3755 exec_list[i].handle);
3760 i915_gem_dump_object(batch_obj,
3766 /* Exec the batchbuffer */
3767 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3768 cliprects, exec_offset);
3770 DRM_ERROR("dispatch failed %d\n", ret);
3775 * Ensure that the commands in the batch buffer are
3776 * finished before the interrupt fires
3778 i915_retire_commands(dev, ring);
3780 i915_verify_inactive(dev, __FILE__, __LINE__);
3782 for (i = 0; i < args->buffer_count; i++) {
3783 struct drm_gem_object *obj = object_list[i];
3784 obj_priv = to_intel_bo(obj);
3786 i915_gem_object_move_to_active(obj, ring);
3788 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3793 * Get a seqno representing the execution of the current buffer,
3794 * which we can wait on. We would like to mitigate these interrupts,
3795 * likely by only creating seqnos occasionally (so that we have
3796 * *some* interrupts representing completion of buffers that we can
3797 * wait on when trying to clear up gtt space).
3799 seqno = i915_add_request(dev, file_priv, request, ring);
3803 i915_dump_lru(dev, __func__);
3806 i915_verify_inactive(dev, __FILE__, __LINE__);
3809 for (i = 0; i < pinned; i++)
3810 i915_gem_object_unpin(object_list[i]);
3812 for (i = 0; i < args->buffer_count; i++) {
3813 if (object_list[i]) {
3814 obj_priv = to_intel_bo(object_list[i]);
3815 obj_priv->in_execbuffer = false;
3817 drm_gem_object_unreference(object_list[i]);
3820 mutex_unlock(&dev->struct_mutex);
3823 /* Copy the updated relocations out regardless of current error
3824 * state. Failure to update the relocs would mean that the next
3825 * time userland calls execbuf, it would do so with presumed offset
3826 * state that didn't match the actual object state.
3828 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3831 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3837 drm_free_large(object_list);
3845 * Legacy execbuffer just creates an exec2 list from the original exec object
3846 * list array and passes it to the real function.
3849 i915_gem_execbuffer(struct drm_device *dev, void *data,
3850 struct drm_file *file_priv)
3852 struct drm_i915_gem_execbuffer *args = data;
3853 struct drm_i915_gem_execbuffer2 exec2;
3854 struct drm_i915_gem_exec_object *exec_list = NULL;
3855 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3859 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3860 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3863 if (args->buffer_count < 1) {
3864 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3868 /* Copy in the exec list from userland */
3869 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3870 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3871 if (exec_list == NULL || exec2_list == NULL) {
3872 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3873 args->buffer_count);
3874 drm_free_large(exec_list);
3875 drm_free_large(exec2_list);
3878 ret = copy_from_user(exec_list,
3879 (struct drm_i915_relocation_entry __user *)
3880 (uintptr_t) args->buffers_ptr,
3881 sizeof(*exec_list) * args->buffer_count);
3883 DRM_ERROR("copy %d exec entries failed %d\n",
3884 args->buffer_count, ret);
3885 drm_free_large(exec_list);
3886 drm_free_large(exec2_list);
3890 for (i = 0; i < args->buffer_count; i++) {
3891 exec2_list[i].handle = exec_list[i].handle;
3892 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3893 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3894 exec2_list[i].alignment = exec_list[i].alignment;
3895 exec2_list[i].offset = exec_list[i].offset;
3897 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3899 exec2_list[i].flags = 0;
3902 exec2.buffers_ptr = args->buffers_ptr;
3903 exec2.buffer_count = args->buffer_count;
3904 exec2.batch_start_offset = args->batch_start_offset;
3905 exec2.batch_len = args->batch_len;
3906 exec2.DR1 = args->DR1;
3907 exec2.DR4 = args->DR4;
3908 exec2.num_cliprects = args->num_cliprects;
3909 exec2.cliprects_ptr = args->cliprects_ptr;
3910 exec2.flags = I915_EXEC_RENDER;
3912 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3914 /* Copy the new buffer offsets back to the user's exec list. */
3915 for (i = 0; i < args->buffer_count; i++)
3916 exec_list[i].offset = exec2_list[i].offset;
3917 /* ... and back out to userspace */
3918 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3919 (uintptr_t) args->buffers_ptr,
3921 sizeof(*exec_list) * args->buffer_count);
3924 DRM_ERROR("failed to copy %d exec entries "
3925 "back to user (%d)\n",
3926 args->buffer_count, ret);
3930 drm_free_large(exec_list);
3931 drm_free_large(exec2_list);
3936 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3937 struct drm_file *file_priv)
3939 struct drm_i915_gem_execbuffer2 *args = data;
3940 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3944 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3945 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3948 if (args->buffer_count < 1) {
3949 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3953 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3954 if (exec2_list == NULL) {
3955 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3956 args->buffer_count);
3959 ret = copy_from_user(exec2_list,
3960 (struct drm_i915_relocation_entry __user *)
3961 (uintptr_t) args->buffers_ptr,
3962 sizeof(*exec2_list) * args->buffer_count);
3964 DRM_ERROR("copy %d exec entries failed %d\n",
3965 args->buffer_count, ret);
3966 drm_free_large(exec2_list);
3970 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3972 /* Copy the new buffer offsets back to the user's exec list. */
3973 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3974 (uintptr_t) args->buffers_ptr,
3976 sizeof(*exec2_list) * args->buffer_count);
3979 DRM_ERROR("failed to copy %d exec entries "
3980 "back to user (%d)\n",
3981 args->buffer_count, ret);
3985 drm_free_large(exec2_list);
3990 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3992 struct drm_device *dev = obj->dev;
3993 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3996 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3998 i915_verify_inactive(dev, __FILE__, __LINE__);
4000 if (obj_priv->gtt_space != NULL) {
4002 alignment = i915_gem_get_gtt_alignment(obj);
4003 if (obj_priv->gtt_offset & (alignment - 1)) {
4004 WARN(obj_priv->pin_count,
4005 "bo is already pinned with incorrect alignment:"
4006 " offset=%x, req.alignment=%x\n",
4007 obj_priv->gtt_offset, alignment);
4008 ret = i915_gem_object_unbind(obj);
4014 if (obj_priv->gtt_space == NULL) {
4015 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4020 obj_priv->pin_count++;
4022 /* If the object is not active and not pending a flush,
4023 * remove it from the inactive list
4025 if (obj_priv->pin_count == 1) {
4026 atomic_inc(&dev->pin_count);
4027 atomic_add(obj->size, &dev->pin_memory);
4028 if (!obj_priv->active &&
4029 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4030 list_del_init(&obj_priv->list);
4032 i915_verify_inactive(dev, __FILE__, __LINE__);
4038 i915_gem_object_unpin(struct drm_gem_object *obj)
4040 struct drm_device *dev = obj->dev;
4041 drm_i915_private_t *dev_priv = dev->dev_private;
4042 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4044 i915_verify_inactive(dev, __FILE__, __LINE__);
4045 obj_priv->pin_count--;
4046 BUG_ON(obj_priv->pin_count < 0);
4047 BUG_ON(obj_priv->gtt_space == NULL);
4049 /* If the object is no longer pinned, and is
4050 * neither active nor being flushed, then stick it on
4053 if (obj_priv->pin_count == 0) {
4054 if (!obj_priv->active &&
4055 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4056 list_move_tail(&obj_priv->list,
4057 &dev_priv->mm.inactive_list);
4058 atomic_dec(&dev->pin_count);
4059 atomic_sub(obj->size, &dev->pin_memory);
4061 i915_verify_inactive(dev, __FILE__, __LINE__);
4065 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4066 struct drm_file *file_priv)
4068 struct drm_i915_gem_pin *args = data;
4069 struct drm_gem_object *obj;
4070 struct drm_i915_gem_object *obj_priv;
4073 mutex_lock(&dev->struct_mutex);
4075 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4077 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4079 mutex_unlock(&dev->struct_mutex);
4082 obj_priv = to_intel_bo(obj);
4084 if (obj_priv->madv != I915_MADV_WILLNEED) {
4085 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4086 drm_gem_object_unreference(obj);
4087 mutex_unlock(&dev->struct_mutex);
4091 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4092 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4094 drm_gem_object_unreference(obj);
4095 mutex_unlock(&dev->struct_mutex);
4099 obj_priv->user_pin_count++;
4100 obj_priv->pin_filp = file_priv;
4101 if (obj_priv->user_pin_count == 1) {
4102 ret = i915_gem_object_pin(obj, args->alignment);
4104 drm_gem_object_unreference(obj);
4105 mutex_unlock(&dev->struct_mutex);
4110 /* XXX - flush the CPU caches for pinned objects
4111 * as the X server doesn't manage domains yet
4113 i915_gem_object_flush_cpu_write_domain(obj);
4114 args->offset = obj_priv->gtt_offset;
4115 drm_gem_object_unreference(obj);
4116 mutex_unlock(&dev->struct_mutex);
4122 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4123 struct drm_file *file_priv)
4125 struct drm_i915_gem_pin *args = data;
4126 struct drm_gem_object *obj;
4127 struct drm_i915_gem_object *obj_priv;
4129 mutex_lock(&dev->struct_mutex);
4131 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4133 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4135 mutex_unlock(&dev->struct_mutex);
4139 obj_priv = to_intel_bo(obj);
4140 if (obj_priv->pin_filp != file_priv) {
4141 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4143 drm_gem_object_unreference(obj);
4144 mutex_unlock(&dev->struct_mutex);
4147 obj_priv->user_pin_count--;
4148 if (obj_priv->user_pin_count == 0) {
4149 obj_priv->pin_filp = NULL;
4150 i915_gem_object_unpin(obj);
4153 drm_gem_object_unreference(obj);
4154 mutex_unlock(&dev->struct_mutex);
4159 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4160 struct drm_file *file_priv)
4162 struct drm_i915_gem_busy *args = data;
4163 struct drm_gem_object *obj;
4164 struct drm_i915_gem_object *obj_priv;
4166 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4168 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4173 mutex_lock(&dev->struct_mutex);
4175 /* Count all active objects as busy, even if they are currently not used
4176 * by the gpu. Users of this interface expect objects to eventually
4177 * become non-busy without any further actions, therefore emit any
4178 * necessary flushes here.
4180 obj_priv = to_intel_bo(obj);
4181 args->busy = obj_priv->active;
4183 /* Unconditionally flush objects, even when the gpu still uses this
4184 * object. Userspace calling this function indicates that it wants to
4185 * use this buffer rather sooner than later, so issuing the required
4186 * flush earlier is beneficial.
4188 if (obj->write_domain) {
4189 i915_gem_flush(dev, 0, obj->write_domain);
4190 (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring);
4193 /* Update the active list for the hardware's current position.
4194 * Otherwise this only updates on a delayed timer or when irqs
4195 * are actually unmasked, and our working set ends up being
4196 * larger than required.
4198 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4200 args->busy = obj_priv->active;
4203 drm_gem_object_unreference(obj);
4204 mutex_unlock(&dev->struct_mutex);
4209 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4210 struct drm_file *file_priv)
4212 return i915_gem_ring_throttle(dev, file_priv);
4216 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4217 struct drm_file *file_priv)
4219 struct drm_i915_gem_madvise *args = data;
4220 struct drm_gem_object *obj;
4221 struct drm_i915_gem_object *obj_priv;
4223 switch (args->madv) {
4224 case I915_MADV_DONTNEED:
4225 case I915_MADV_WILLNEED:
4231 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4233 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4238 mutex_lock(&dev->struct_mutex);
4239 obj_priv = to_intel_bo(obj);
4241 if (obj_priv->pin_count) {
4242 drm_gem_object_unreference(obj);
4243 mutex_unlock(&dev->struct_mutex);
4245 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4249 if (obj_priv->madv != __I915_MADV_PURGED)
4250 obj_priv->madv = args->madv;
4252 /* if the object is no longer bound, discard its backing storage */
4253 if (i915_gem_object_is_purgeable(obj_priv) &&
4254 obj_priv->gtt_space == NULL)
4255 i915_gem_object_truncate(obj);
4257 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4259 drm_gem_object_unreference(obj);
4260 mutex_unlock(&dev->struct_mutex);
4265 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4268 struct drm_i915_gem_object *obj;
4270 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4274 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4279 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4280 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4282 obj->agp_type = AGP_USER_MEMORY;
4283 obj->base.driver_private = NULL;
4284 obj->fence_reg = I915_FENCE_REG_NONE;
4285 INIT_LIST_HEAD(&obj->list);
4286 INIT_LIST_HEAD(&obj->gpu_write_list);
4287 obj->madv = I915_MADV_WILLNEED;
4289 trace_i915_gem_object_create(&obj->base);
4294 int i915_gem_init_object(struct drm_gem_object *obj)
4301 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4303 struct drm_device *dev = obj->dev;
4304 drm_i915_private_t *dev_priv = dev->dev_private;
4305 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4308 ret = i915_gem_object_unbind(obj);
4309 if (ret == -ERESTARTSYS) {
4310 list_move(&obj_priv->list,
4311 &dev_priv->mm.deferred_free_list);
4315 if (obj_priv->mmap_offset)
4316 i915_gem_free_mmap_offset(obj);
4318 drm_gem_object_release(obj);
4320 kfree(obj_priv->page_cpu_valid);
4321 kfree(obj_priv->bit_17);
4325 void i915_gem_free_object(struct drm_gem_object *obj)
4327 struct drm_device *dev = obj->dev;
4328 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4330 trace_i915_gem_object_destroy(obj);
4332 while (obj_priv->pin_count > 0)
4333 i915_gem_object_unpin(obj);
4335 if (obj_priv->phys_obj)
4336 i915_gem_detach_phys_object(dev, obj);
4338 i915_gem_free_object_tail(obj);
4342 i915_gem_idle(struct drm_device *dev)
4344 drm_i915_private_t *dev_priv = dev->dev_private;
4347 mutex_lock(&dev->struct_mutex);
4349 if (dev_priv->mm.suspended ||
4350 (dev_priv->render_ring.gem_object == NULL) ||
4352 dev_priv->bsd_ring.gem_object == NULL)) {
4353 mutex_unlock(&dev->struct_mutex);
4357 ret = i915_gpu_idle(dev);
4359 mutex_unlock(&dev->struct_mutex);
4363 /* Under UMS, be paranoid and evict. */
4364 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4365 ret = i915_gem_evict_inactive(dev);
4367 mutex_unlock(&dev->struct_mutex);
4372 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4373 * We need to replace this with a semaphore, or something.
4374 * And not confound mm.suspended!
4376 dev_priv->mm.suspended = 1;
4377 del_timer_sync(&dev_priv->hangcheck_timer);
4379 i915_kernel_lost_context(dev);
4380 i915_gem_cleanup_ringbuffer(dev);
4382 mutex_unlock(&dev->struct_mutex);
4384 /* Cancel the retire work handler, which should be idle now. */
4385 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4391 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4392 * over cache flushing.
4395 i915_gem_init_pipe_control(struct drm_device *dev)
4397 drm_i915_private_t *dev_priv = dev->dev_private;
4398 struct drm_gem_object *obj;
4399 struct drm_i915_gem_object *obj_priv;
4402 obj = i915_gem_alloc_object(dev, 4096);
4404 DRM_ERROR("Failed to allocate seqno page\n");
4408 obj_priv = to_intel_bo(obj);
4409 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4411 ret = i915_gem_object_pin(obj, 4096);
4415 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4416 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4417 if (dev_priv->seqno_page == NULL)
4420 dev_priv->seqno_obj = obj;
4421 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4426 i915_gem_object_unpin(obj);
4428 drm_gem_object_unreference(obj);
4435 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4437 drm_i915_private_t *dev_priv = dev->dev_private;
4438 struct drm_gem_object *obj;
4439 struct drm_i915_gem_object *obj_priv;
4441 obj = dev_priv->seqno_obj;
4442 obj_priv = to_intel_bo(obj);
4443 kunmap(obj_priv->pages[0]);
4444 i915_gem_object_unpin(obj);
4445 drm_gem_object_unreference(obj);
4446 dev_priv->seqno_obj = NULL;
4448 dev_priv->seqno_page = NULL;
4452 i915_gem_init_ringbuffer(struct drm_device *dev)
4454 drm_i915_private_t *dev_priv = dev->dev_private;
4457 dev_priv->render_ring = render_ring;
4459 if (!I915_NEED_GFX_HWS(dev)) {
4460 dev_priv->render_ring.status_page.page_addr
4461 = dev_priv->status_page_dmah->vaddr;
4462 memset(dev_priv->render_ring.status_page.page_addr,
4466 if (HAS_PIPE_CONTROL(dev)) {
4467 ret = i915_gem_init_pipe_control(dev);
4472 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4474 goto cleanup_pipe_control;
4477 dev_priv->bsd_ring = bsd_ring;
4478 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4480 goto cleanup_render_ring;
4483 dev_priv->next_seqno = 1;
4487 cleanup_render_ring:
4488 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4489 cleanup_pipe_control:
4490 if (HAS_PIPE_CONTROL(dev))
4491 i915_gem_cleanup_pipe_control(dev);
4496 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4498 drm_i915_private_t *dev_priv = dev->dev_private;
4500 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4502 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4503 if (HAS_PIPE_CONTROL(dev))
4504 i915_gem_cleanup_pipe_control(dev);
4508 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4509 struct drm_file *file_priv)
4511 drm_i915_private_t *dev_priv = dev->dev_private;
4514 if (drm_core_check_feature(dev, DRIVER_MODESET))
4517 if (atomic_read(&dev_priv->mm.wedged)) {
4518 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4519 atomic_set(&dev_priv->mm.wedged, 0);
4522 mutex_lock(&dev->struct_mutex);
4523 dev_priv->mm.suspended = 0;
4525 ret = i915_gem_init_ringbuffer(dev);
4527 mutex_unlock(&dev->struct_mutex);
4531 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4532 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4533 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4534 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4535 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4536 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4537 mutex_unlock(&dev->struct_mutex);
4539 ret = drm_irq_install(dev);
4541 goto cleanup_ringbuffer;
4546 mutex_lock(&dev->struct_mutex);
4547 i915_gem_cleanup_ringbuffer(dev);
4548 dev_priv->mm.suspended = 1;
4549 mutex_unlock(&dev->struct_mutex);
4555 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4556 struct drm_file *file_priv)
4558 if (drm_core_check_feature(dev, DRIVER_MODESET))
4561 drm_irq_uninstall(dev);
4562 return i915_gem_idle(dev);
4566 i915_gem_lastclose(struct drm_device *dev)
4570 if (drm_core_check_feature(dev, DRIVER_MODESET))
4573 ret = i915_gem_idle(dev);
4575 DRM_ERROR("failed to idle hardware: %d\n", ret);
4579 i915_gem_load(struct drm_device *dev)
4582 drm_i915_private_t *dev_priv = dev->dev_private;
4584 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4585 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4586 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4587 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4588 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4589 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4590 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4592 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4593 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4595 for (i = 0; i < 16; i++)
4596 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4597 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4598 i915_gem_retire_work_handler);
4599 spin_lock(&shrink_list_lock);
4600 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4601 spin_unlock(&shrink_list_lock);
4603 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4605 u32 tmp = I915_READ(MI_ARB_STATE);
4606 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4607 /* arb state is a masked write, so set bit + bit in mask */
4608 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4609 I915_WRITE(MI_ARB_STATE, tmp);
4613 /* Old X drivers will take 0-2 for front, back, depth buffers */
4614 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4615 dev_priv->fence_reg_start = 3;
4617 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4618 dev_priv->num_fence_regs = 16;
4620 dev_priv->num_fence_regs = 8;
4622 /* Initialize fence registers to zero */
4623 if (IS_I965G(dev)) {
4624 for (i = 0; i < 16; i++)
4625 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4627 for (i = 0; i < 8; i++)
4628 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4629 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4630 for (i = 0; i < 8; i++)
4631 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4633 i915_gem_detect_bit_6_swizzle(dev);
4634 init_waitqueue_head(&dev_priv->pending_flip_queue);
4638 * Create a physically contiguous memory object for this object
4639 * e.g. for cursor + overlay regs
4641 static int i915_gem_init_phys_object(struct drm_device *dev,
4642 int id, int size, int align)
4644 drm_i915_private_t *dev_priv = dev->dev_private;
4645 struct drm_i915_gem_phys_object *phys_obj;
4648 if (dev_priv->mm.phys_objs[id - 1] || !size)
4651 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4657 phys_obj->handle = drm_pci_alloc(dev, size, align);
4658 if (!phys_obj->handle) {
4663 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4666 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4674 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4676 drm_i915_private_t *dev_priv = dev->dev_private;
4677 struct drm_i915_gem_phys_object *phys_obj;
4679 if (!dev_priv->mm.phys_objs[id - 1])
4682 phys_obj = dev_priv->mm.phys_objs[id - 1];
4683 if (phys_obj->cur_obj) {
4684 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4688 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4690 drm_pci_free(dev, phys_obj->handle);
4692 dev_priv->mm.phys_objs[id - 1] = NULL;
4695 void i915_gem_free_all_phys_object(struct drm_device *dev)
4699 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4700 i915_gem_free_phys_object(dev, i);
4703 void i915_gem_detach_phys_object(struct drm_device *dev,
4704 struct drm_gem_object *obj)
4706 struct drm_i915_gem_object *obj_priv;
4711 obj_priv = to_intel_bo(obj);
4712 if (!obj_priv->phys_obj)
4715 ret = i915_gem_object_get_pages(obj, 0);
4719 page_count = obj->size / PAGE_SIZE;
4721 for (i = 0; i < page_count; i++) {
4722 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4723 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4725 memcpy(dst, src, PAGE_SIZE);
4726 kunmap_atomic(dst, KM_USER0);
4728 drm_clflush_pages(obj_priv->pages, page_count);
4729 drm_agp_chipset_flush(dev);
4731 i915_gem_object_put_pages(obj);
4733 obj_priv->phys_obj->cur_obj = NULL;
4734 obj_priv->phys_obj = NULL;
4738 i915_gem_attach_phys_object(struct drm_device *dev,
4739 struct drm_gem_object *obj,
4743 drm_i915_private_t *dev_priv = dev->dev_private;
4744 struct drm_i915_gem_object *obj_priv;
4749 if (id > I915_MAX_PHYS_OBJECT)
4752 obj_priv = to_intel_bo(obj);
4754 if (obj_priv->phys_obj) {
4755 if (obj_priv->phys_obj->id == id)
4757 i915_gem_detach_phys_object(dev, obj);
4760 /* create a new object */
4761 if (!dev_priv->mm.phys_objs[id - 1]) {
4762 ret = i915_gem_init_phys_object(dev, id,
4765 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4770 /* bind to the object */
4771 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4772 obj_priv->phys_obj->cur_obj = obj;
4774 ret = i915_gem_object_get_pages(obj, 0);
4776 DRM_ERROR("failed to get page list\n");
4780 page_count = obj->size / PAGE_SIZE;
4782 for (i = 0; i < page_count; i++) {
4783 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4784 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4786 memcpy(dst, src, PAGE_SIZE);
4787 kunmap_atomic(src, KM_USER0);
4790 i915_gem_object_put_pages(obj);
4798 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4799 struct drm_i915_gem_pwrite *args,
4800 struct drm_file *file_priv)
4802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4805 char __user *user_data;
4807 user_data = (char __user *) (uintptr_t) args->data_ptr;
4808 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4810 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4811 ret = copy_from_user(obj_addr, user_data, args->size);
4815 drm_agp_chipset_flush(dev);
4819 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4821 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4823 /* Clean up our request list when the client is going away, so that
4824 * later retire_requests won't dereference our soon-to-be-gone
4827 mutex_lock(&dev->struct_mutex);
4828 while (!list_empty(&i915_file_priv->mm.request_list))
4829 list_del_init(i915_file_priv->mm.request_list.next);
4830 mutex_unlock(&dev->struct_mutex);
4834 i915_gpu_is_active(struct drm_device *dev)
4836 drm_i915_private_t *dev_priv = dev->dev_private;
4839 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4840 list_empty(&dev_priv->render_ring.active_list);
4842 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4844 return !lists_empty;
4848 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4850 drm_i915_private_t *dev_priv, *next_dev;
4851 struct drm_i915_gem_object *obj_priv, *next_obj;
4853 int would_deadlock = 1;
4855 /* "fast-path" to count number of available objects */
4856 if (nr_to_scan == 0) {
4857 spin_lock(&shrink_list_lock);
4858 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4859 struct drm_device *dev = dev_priv->dev;
4861 if (mutex_trylock(&dev->struct_mutex)) {
4862 list_for_each_entry(obj_priv,
4863 &dev_priv->mm.inactive_list,
4866 mutex_unlock(&dev->struct_mutex);
4869 spin_unlock(&shrink_list_lock);
4871 return (cnt / 100) * sysctl_vfs_cache_pressure;
4874 spin_lock(&shrink_list_lock);
4877 /* first scan for clean buffers */
4878 list_for_each_entry_safe(dev_priv, next_dev,
4879 &shrink_list, mm.shrink_list) {
4880 struct drm_device *dev = dev_priv->dev;
4882 if (! mutex_trylock(&dev->struct_mutex))
4885 spin_unlock(&shrink_list_lock);
4886 i915_gem_retire_requests(dev);
4888 list_for_each_entry_safe(obj_priv, next_obj,
4889 &dev_priv->mm.inactive_list,
4891 if (i915_gem_object_is_purgeable(obj_priv)) {
4892 i915_gem_object_unbind(&obj_priv->base);
4893 if (--nr_to_scan <= 0)
4898 spin_lock(&shrink_list_lock);
4899 mutex_unlock(&dev->struct_mutex);
4903 if (nr_to_scan <= 0)
4907 /* second pass, evict/count anything still on the inactive list */
4908 list_for_each_entry_safe(dev_priv, next_dev,
4909 &shrink_list, mm.shrink_list) {
4910 struct drm_device *dev = dev_priv->dev;
4912 if (! mutex_trylock(&dev->struct_mutex))
4915 spin_unlock(&shrink_list_lock);
4917 list_for_each_entry_safe(obj_priv, next_obj,
4918 &dev_priv->mm.inactive_list,
4920 if (nr_to_scan > 0) {
4921 i915_gem_object_unbind(&obj_priv->base);
4927 spin_lock(&shrink_list_lock);
4928 mutex_unlock(&dev->struct_mutex);
4937 * We are desperate for pages, so as a last resort, wait
4938 * for the GPU to finish and discard whatever we can.
4939 * This has a dramatic impact to reduce the number of
4940 * OOM-killer events whilst running the GPU aggressively.
4942 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4943 struct drm_device *dev = dev_priv->dev;
4945 if (!mutex_trylock(&dev->struct_mutex))
4948 spin_unlock(&shrink_list_lock);
4950 if (i915_gpu_is_active(dev)) {
4955 spin_lock(&shrink_list_lock);
4956 mutex_unlock(&dev->struct_mutex);
4963 spin_unlock(&shrink_list_lock);
4968 return (cnt / 100) * sysctl_vfs_cache_pressure;
4973 static struct shrinker shrinker = {
4974 .shrink = i915_gem_shrink,
4975 .seeks = DEFAULT_SEEKS,
4979 i915_gem_shrinker_init(void)
4981 register_shrinker(&shrinker);
4985 i915_gem_shrinker_exit(void)
4987 unregister_shrinker(&shrinker);