drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static LIST_HEAD(shrink_list);
  62 static DEFINE_SPINLOCK(shrink_list_lock);
  63
  64 static inline bool
  65 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
  66 {
  67         return obj_priv->gtt_space &&
  68                 !obj_priv->active &&
  69                 obj_priv->pin_count == 0;
  70 }
  71
  72 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  73                      unsigned long end)
  74 {
  75         drm_i915_private_t *dev_priv = dev->dev_private;
  76
  77         if (start >= end ||
  78             (start & (PAGE_SIZE - 1)) != 0 ||
  79             (end & (PAGE_SIZE - 1)) != 0) {
  80                 return -EINVAL;
  81         }
  82
  83         drm_mm_init(&dev_priv->mm.gtt_space, start,
  84                     end - start);
  85
  86         dev->gtt_total = (uint32_t) (end - start);
  87
  88         return 0;
  89 }
  90
  91 int
  92 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  93                     struct drm_file *file_priv)
  94 {
  95         struct drm_i915_gem_init *args = data;
  96         int ret;
  97
  98         mutex_lock(&dev->struct_mutex);
  99         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 100         mutex_unlock(&dev->struct_mutex);
 101
 102         return ret;
 103 }
 104
 105 int
 106 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 107                             struct drm_file *file_priv)
 108 {
 109         struct drm_i915_gem_get_aperture *args = data;
 110
 111         if (!(dev->driver->driver_features & DRIVER_GEM))
 112                 return -ENODEV;
 113
 114         args->aper_size = dev->gtt_total;
 115         args->aper_available_size = (args->aper_size -
 116                                      atomic_read(&dev->pin_memory));
 117
 118         return 0;
 119 }
 120
 121
 122 /**
 123  * Creates a new mm object and returns a handle to it.
 124  */
 125 int
 126 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 127                       struct drm_file *file_priv)
 128 {
 129         struct drm_i915_gem_create *args = data;
 130         struct drm_gem_object *obj;
 131         int ret;
 132         u32 handle;
 133
 134         args->size = roundup(args->size, PAGE_SIZE);
 135
 136         /* Allocate the new object */
 137         obj = i915_gem_alloc_object(dev, args->size);
 138         if (obj == NULL)
 139                 return -ENOMEM;
 140
 141         ret = drm_gem_handle_create(file_priv, obj, &handle);
 142         if (ret) {
 143                 drm_gem_object_unreference_unlocked(obj);
 144                 return ret;
 145         }
 146
 147         /* Sink the floating reference from kref_init(handlecount) */
 148         drm_gem_object_handle_unreference_unlocked(obj);
 149
 150         args->handle = handle;
 151         return 0;
 152 }
 153
 154 static inline int
 155 fast_shmem_read(struct page **pages,
 156                 loff_t page_base, int page_offset,
 157                 char __user *data,
 158                 int length)
 159 {
 160         char __iomem *vaddr;
 161         int unwritten;
 162
 163         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 164         if (vaddr == NULL)
 165                 return -ENOMEM;
 166         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 167         kunmap_atomic(vaddr, KM_USER0);
 168
 169         if (unwritten)
 170                 return -EFAULT;
 171
 172         return 0;
 173 }
 174
 175 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 176 {
 177         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 178         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 179
 180         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 181                 obj_priv->tiling_mode != I915_TILING_NONE;
 182 }
 183
 184 static inline void
 185 slow_shmem_copy(struct page *dst_page,
 186                 int dst_offset,
 187                 struct page *src_page,
 188                 int src_offset,
 189                 int length)
 190 {
 191         char *dst_vaddr, *src_vaddr;
 192
 193         dst_vaddr = kmap(dst_page);
 194         src_vaddr = kmap(src_page);
 195
 196         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 197
 198         kunmap(src_page);
 199         kunmap(dst_page);
 200 }
 201
 202 static inline void
 203 slow_shmem_bit17_copy(struct page *gpu_page,
 204                       int gpu_offset,
 205                       struct page *cpu_page,
 206                       int cpu_offset,
 207                       int length,
 208                       int is_read)
 209 {
 210         char *gpu_vaddr, *cpu_vaddr;
 211
 212         /* Use the unswizzled path if this page isn't affected. */
 213         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 214                 if (is_read)
 215                         return slow_shmem_copy(cpu_page, cpu_offset,
 216                                                gpu_page, gpu_offset, length);
 217                 else
 218                         return slow_shmem_copy(gpu_page, gpu_offset,
 219                                                cpu_page, cpu_offset, length);
 220         }
 221
 222         gpu_vaddr = kmap(gpu_page);
 223         cpu_vaddr = kmap(cpu_page);
 224
 225         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 226          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 227          */
 228         while (length > 0) {
 229                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 230                 int this_length = min(cacheline_end - gpu_offset, length);
 231                 int swizzled_gpu_offset = gpu_offset ^ 64;
 232
 233                 if (is_read) {
 234                         memcpy(cpu_vaddr + cpu_offset,
 235                                gpu_vaddr + swizzled_gpu_offset,
 236                                this_length);
 237                 } else {
 238                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 239                                cpu_vaddr + cpu_offset,
 240                                this_length);
 241                 }
 242                 cpu_offset += this_length;
 243                 gpu_offset += this_length;
 244                 length -= this_length;
 245         }
 246
 247         kunmap(cpu_page);
 248         kunmap(gpu_page);
 249 }
 250
 251 /**
 252  * This is the fast shmem pread path, which attempts to copy_from_user directly
 253  * from the backing pages of the object to the user's address space.  On a
 254  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 255  */
 256 static int
 257 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 258                           struct drm_i915_gem_pread *args,
 259                           struct drm_file *file_priv)
 260 {
 261         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 262         ssize_t remain;
 263         loff_t offset, page_base;
 264         char __user *user_data;
 265         int page_offset, page_length;
 266         int ret;
 267
 268         user_data = (char __user *) (uintptr_t) args->data_ptr;
 269         remain = args->size;
 270
 271         mutex_lock(&dev->struct_mutex);
 272
 273         ret = i915_gem_object_get_pages(obj, 0);
 274         if (ret != 0)
 275                 goto fail_unlock;
 276
 277         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 278                                                         args->size);
 279         if (ret != 0)
 280                 goto fail_put_pages;
 281
 282         obj_priv = to_intel_bo(obj);
 283         offset = args->offset;
 284
 285         while (remain > 0) {
 286                 /* Operation in this page
 287                  *
 288                  * page_base = page offset within aperture
 289                  * page_offset = offset within page
 290                  * page_length = bytes to copy for this page
 291                  */
 292                 page_base = (offset & ~(PAGE_SIZE-1));
 293                 page_offset = offset & (PAGE_SIZE-1);
 294                 page_length = remain;
 295                 if ((page_offset + remain) > PAGE_SIZE)
 296                         page_length = PAGE_SIZE - page_offset;
 297
 298                 ret = fast_shmem_read(obj_priv->pages,
 299                                       page_base, page_offset,
 300                                       user_data, page_length);
 301                 if (ret)
 302                         goto fail_put_pages;
 303
 304                 remain -= page_length;
 305                 user_data += page_length;
 306                 offset += page_length;
 307         }
 308
 309 fail_put_pages:
 310         i915_gem_object_put_pages(obj);
 311 fail_unlock:
 312         mutex_unlock(&dev->struct_mutex);
 313
 314         return ret;
 315 }
 316
 317 static int
 318 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 319 {
 320         int ret;
 321
 322         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 323
 324         /* If we've insufficient memory to map in the pages, attempt
 325          * to make some space by throwing out some old buffers.
 326          */
 327         if (ret == -ENOMEM) {
 328                 struct drm_device *dev = obj->dev;
 329
 330                 ret = i915_gem_evict_something(dev, obj->size,
 331                                                i915_gem_get_gtt_alignment(obj));
 332                 if (ret)
 333                         return ret;
 334
 335                 ret = i915_gem_object_get_pages(obj, 0);
 336         }
 337
 338         return ret;
 339 }
 340
 341 /**
 342  * This is the fallback shmem pread path, which allocates temporary storage
 343  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 344  * can copy out of the object's backing pages while holding the struct mutex
 345  * and not take page faults.
 346  */
 347 static int
 348 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 349                           struct drm_i915_gem_pread *args,
 350                           struct drm_file *file_priv)
 351 {
 352         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 353         struct mm_struct *mm = current->mm;
 354         struct page **user_pages;
 355         ssize_t remain;
 356         loff_t offset, pinned_pages, i;
 357         loff_t first_data_page, last_data_page, num_pages;
 358         int shmem_page_index, shmem_page_offset;
 359         int data_page_index,  data_page_offset;
 360         int page_length;
 361         int ret;
 362         uint64_t data_ptr = args->data_ptr;
 363         int do_bit17_swizzling;
 364
 365         remain = args->size;
 366
 367         /* Pin the user pages containing the data.  We can't fault while
 368          * holding the struct mutex, yet we want to hold it while
 369          * dereferencing the user data.
 370          */
 371         first_data_page = data_ptr / PAGE_SIZE;
 372         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 373         num_pages = last_data_page - first_data_page + 1;
 374
 375         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 376         if (user_pages == NULL)
 377                 return -ENOMEM;
 378
 379         down_read(&mm->mmap_sem);
 380         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 381                                       num_pages, 1, 0, user_pages, NULL);
 382         up_read(&mm->mmap_sem);
 383         if (pinned_pages < num_pages) {
 384                 ret = -EFAULT;
 385                 goto fail_put_user_pages;
 386         }
 387
 388         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 389
 390         mutex_lock(&dev->struct_mutex);
 391
 392         ret = i915_gem_object_get_pages_or_evict(obj);
 393         if (ret)
 394                 goto fail_unlock;
 395
 396         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 397                                                         args->size);
 398         if (ret != 0)
 399                 goto fail_put_pages;
 400
 401         obj_priv = to_intel_bo(obj);
 402         offset = args->offset;
 403
 404         while (remain > 0) {
 405                 /* Operation in this page
 406                  *
 407                  * shmem_page_index = page number within shmem file
 408                  * shmem_page_offset = offset within page in shmem file
 409                  * data_page_index = page number in get_user_pages return
 410                  * data_page_offset = offset with data_page_index page.
 411                  * page_length = bytes to copy for this page
 412                  */
 413                 shmem_page_index = offset / PAGE_SIZE;
 414                 shmem_page_offset = offset & ~PAGE_MASK;
 415                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 416                 data_page_offset = data_ptr & ~PAGE_MASK;
 417
 418                 page_length = remain;
 419                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 420                         page_length = PAGE_SIZE - shmem_page_offset;
 421                 if ((data_page_offset + page_length) > PAGE_SIZE)
 422                         page_length = PAGE_SIZE - data_page_offset;
 423
 424                 if (do_bit17_swizzling) {
 425                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 426                                               shmem_page_offset,
 427                                               user_pages[data_page_index],
 428                                               data_page_offset,
 429                                               page_length,
 430                                               1);
 431                 } else {
 432                         slow_shmem_copy(user_pages[data_page_index],
 433                                         data_page_offset,
 434                                         obj_priv->pages[shmem_page_index],
 435                                         shmem_page_offset,
 436                                         page_length);
 437                 }
 438
 439                 remain -= page_length;
 440                 data_ptr += page_length;
 441                 offset += page_length;
 442         }
 443
 444 fail_put_pages:
 445         i915_gem_object_put_pages(obj);
 446 fail_unlock:
 447         mutex_unlock(&dev->struct_mutex);
 448 fail_put_user_pages:
 449         for (i = 0; i < pinned_pages; i++) {
 450                 SetPageDirty(user_pages[i]);
 451                 page_cache_release(user_pages[i]);
 452         }
 453         drm_free_large(user_pages);
 454
 455         return ret;
 456 }
 457
 458 /**
 459  * Reads data from the object referenced by handle.
 460  *
 461  * On error, the contents of *data are undefined.
 462  */
 463 int
 464 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 465                      struct drm_file *file_priv)
 466 {
 467         struct drm_i915_gem_pread *args = data;
 468         struct drm_gem_object *obj;
 469         struct drm_i915_gem_object *obj_priv;
 470         int ret;
 471
 472         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 473         if (obj == NULL)
 474                 return -ENOENT;
 475         obj_priv = to_intel_bo(obj);
 476
 477         /* Bounds check source.
 478          *
 479          * XXX: This could use review for overflow issues...
 480          */
 481         if (args->offset > obj->size || args->size > obj->size ||
 482             args->offset + args->size > obj->size) {
 483                 drm_gem_object_unreference_unlocked(obj);
 484                 return -EINVAL;
 485         }
 486
 487         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 488                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 489         } else {
 490                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 491                 if (ret != 0)
 492                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 493                                                         file_priv);
 494         }
 495
 496         drm_gem_object_unreference_unlocked(obj);
 497
 498         return ret;
 499 }
 500
 501 /* This is the fast write path which cannot handle
 502  * page faults in the source data
 503  */
 504
 505 static inline int
 506 fast_user_write(struct io_mapping *mapping,
 507                 loff_t page_base, int page_offset,
 508                 char __user *user_data,
 509                 int length)
 510 {
 511         char *vaddr_atomic;
 512         unsigned long unwritten;
 513
 514         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 515         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 516                                                       user_data, length);
 517         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 518         if (unwritten)
 519                 return -EFAULT;
 520         return 0;
 521 }
 522
 523 /* Here's the write path which can sleep for
 524  * page faults
 525  */
 526
 527 static inline void
 528 slow_kernel_write(struct io_mapping *mapping,
 529                   loff_t gtt_base, int gtt_offset,
 530                   struct page *user_page, int user_offset,
 531                   int length)
 532 {
 533         char __iomem *dst_vaddr;
 534         char *src_vaddr;
 535
 536         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 537         src_vaddr = kmap(user_page);
 538
 539         memcpy_toio(dst_vaddr + gtt_offset,
 540                     src_vaddr + user_offset,
 541                     length);
 542
 543         kunmap(user_page);
 544         io_mapping_unmap(dst_vaddr);
 545 }
 546
 547 static inline int
 548 fast_shmem_write(struct page **pages,
 549                  loff_t page_base, int page_offset,
 550                  char __user *data,
 551                  int length)
 552 {
 553         char __iomem *vaddr;
 554         unsigned long unwritten;
 555
 556         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 557         if (vaddr == NULL)
 558                 return -ENOMEM;
 559         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 560         kunmap_atomic(vaddr, KM_USER0);
 561
 562         if (unwritten)
 563                 return -EFAULT;
 564         return 0;
 565 }
 566
 567 /**
 568  * This is the fast pwrite path, where we copy the data directly from the
 569  * user into the GTT, uncached.
 570  */
 571 static int
 572 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 573                          struct drm_i915_gem_pwrite *args,
 574                          struct drm_file *file_priv)
 575 {
 576         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 577         drm_i915_private_t *dev_priv = dev->dev_private;
 578         ssize_t remain;
 579         loff_t offset, page_base;
 580         char __user *user_data;
 581         int page_offset, page_length;
 582         int ret;
 583
 584         user_data = (char __user *) (uintptr_t) args->data_ptr;
 585         remain = args->size;
 586         if (!access_ok(VERIFY_READ, user_data, remain))
 587                 return -EFAULT;
 588
 589
 590         mutex_lock(&dev->struct_mutex);
 591         ret = i915_gem_object_pin(obj, 0);
 592         if (ret) {
 593                 mutex_unlock(&dev->struct_mutex);
 594                 return ret;
 595         }
 596         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 597         if (ret)
 598                 goto fail;
 599
 600         obj_priv = to_intel_bo(obj);
 601         offset = obj_priv->gtt_offset + args->offset;
 602
 603         while (remain > 0) {
 604                 /* Operation in this page
 605                  *
 606                  * page_base = page offset within aperture
 607                  * page_offset = offset within page
 608                  * page_length = bytes to copy for this page
 609                  */
 610                 page_base = (offset & ~(PAGE_SIZE-1));
 611                 page_offset = offset & (PAGE_SIZE-1);
 612                 page_length = remain;
 613                 if ((page_offset + remain) > PAGE_SIZE)
 614                         page_length = PAGE_SIZE - page_offset;
 615
 616                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 617                                        page_offset, user_data, page_length);
 618
 619                 /* If we get a fault while copying data, then (presumably) our
 620                  * source page isn't available.  Return the error and we'll
 621                  * retry in the slow path.
 622                  */
 623                 if (ret)
 624                         goto fail;
 625
 626                 remain -= page_length;
 627                 user_data += page_length;
 628                 offset += page_length;
 629         }
 630
 631 fail:
 632         i915_gem_object_unpin(obj);
 633         mutex_unlock(&dev->struct_mutex);
 634
 635         return ret;
 636 }
 637
 638 /**
 639  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 640  * the memory and maps it using kmap_atomic for copying.
 641  *
 642  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 643  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 644  */
 645 static int
 646 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 647                          struct drm_i915_gem_pwrite *args,
 648                          struct drm_file *file_priv)
 649 {
 650         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 651         drm_i915_private_t *dev_priv = dev->dev_private;
 652         ssize_t remain;
 653         loff_t gtt_page_base, offset;
 654         loff_t first_data_page, last_data_page, num_pages;
 655         loff_t pinned_pages, i;
 656         struct page **user_pages;
 657         struct mm_struct *mm = current->mm;
 658         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 659         int ret;
 660         uint64_t data_ptr = args->data_ptr;
 661
 662         remain = args->size;
 663
 664         /* Pin the user pages containing the data.  We can't fault while
 665          * holding the struct mutex, and all of the pwrite implementations
 666          * want to hold it while dereferencing the user data.
 667          */
 668         first_data_page = data_ptr / PAGE_SIZE;
 669         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 670         num_pages = last_data_page - first_data_page + 1;
 671
 672         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 673         if (user_pages == NULL)
 674                 return -ENOMEM;
 675
 676         down_read(&mm->mmap_sem);
 677         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 678                                       num_pages, 0, 0, user_pages, NULL);
 679         up_read(&mm->mmap_sem);
 680         if (pinned_pages < num_pages) {
 681                 ret = -EFAULT;
 682                 goto out_unpin_pages;
 683         }
 684
 685         mutex_lock(&dev->struct_mutex);
 686         ret = i915_gem_object_pin(obj, 0);
 687         if (ret)
 688                 goto out_unlock;
 689
 690         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 691         if (ret)
 692                 goto out_unpin_object;
 693
 694         obj_priv = to_intel_bo(obj);
 695         offset = obj_priv->gtt_offset + args->offset;
 696
 697         while (remain > 0) {
 698                 /* Operation in this page
 699                  *
 700                  * gtt_page_base = page offset within aperture
 701                  * gtt_page_offset = offset within page in aperture
 702                  * data_page_index = page number in get_user_pages return
 703                  * data_page_offset = offset with data_page_index page.
 704                  * page_length = bytes to copy for this page
 705                  */
 706                 gtt_page_base = offset & PAGE_MASK;
 707                 gtt_page_offset = offset & ~PAGE_MASK;
 708                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 709                 data_page_offset = data_ptr & ~PAGE_MASK;
 710
 711                 page_length = remain;
 712                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 713                         page_length = PAGE_SIZE - gtt_page_offset;
 714                 if ((data_page_offset + page_length) > PAGE_SIZE)
 715                         page_length = PAGE_SIZE - data_page_offset;
 716
 717                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 718                                   gtt_page_base, gtt_page_offset,
 719                                   user_pages[data_page_index],
 720                                   data_page_offset,
 721                                   page_length);
 722
 723                 remain -= page_length;
 724                 offset += page_length;
 725                 data_ptr += page_length;
 726         }
 727
 728 out_unpin_object:
 729         i915_gem_object_unpin(obj);
 730 out_unlock:
 731         mutex_unlock(&dev->struct_mutex);
 732 out_unpin_pages:
 733         for (i = 0; i < pinned_pages; i++)
 734                 page_cache_release(user_pages[i]);
 735         drm_free_large(user_pages);
 736
 737         return ret;
 738 }
 739
 740 /**
 741  * This is the fast shmem pwrite path, which attempts to directly
 742  * copy_from_user into the kmapped pages backing the object.
 743  */
 744 static int
 745 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 746                            struct drm_i915_gem_pwrite *args,
 747                            struct drm_file *file_priv)
 748 {
 749         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 750         ssize_t remain;
 751         loff_t offset, page_base;
 752         char __user *user_data;
 753         int page_offset, page_length;
 754         int ret;
 755
 756         user_data = (char __user *) (uintptr_t) args->data_ptr;
 757         remain = args->size;
 758
 759         mutex_lock(&dev->struct_mutex);
 760
 761         ret = i915_gem_object_get_pages(obj, 0);
 762         if (ret != 0)
 763                 goto fail_unlock;
 764
 765         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 766         if (ret != 0)
 767                 goto fail_put_pages;
 768
 769         obj_priv = to_intel_bo(obj);
 770         offset = args->offset;
 771         obj_priv->dirty = 1;
 772
 773         while (remain > 0) {
 774                 /* Operation in this page
 775                  *
 776                  * page_base = page offset within aperture
 777                  * page_offset = offset within page
 778                  * page_length = bytes to copy for this page
 779                  */
 780                 page_base = (offset & ~(PAGE_SIZE-1));
 781                 page_offset = offset & (PAGE_SIZE-1);
 782                 page_length = remain;
 783                 if ((page_offset + remain) > PAGE_SIZE)
 784                         page_length = PAGE_SIZE - page_offset;
 785
 786                 ret = fast_shmem_write(obj_priv->pages,
 787                                        page_base, page_offset,
 788                                        user_data, page_length);
 789                 if (ret)
 790                         goto fail_put_pages;
 791
 792                 remain -= page_length;
 793                 user_data += page_length;
 794                 offset += page_length;
 795         }
 796
 797 fail_put_pages:
 798         i915_gem_object_put_pages(obj);
 799 fail_unlock:
 800         mutex_unlock(&dev->struct_mutex);
 801
 802         return ret;
 803 }
 804
 805 /**
 806  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 807  * the memory and maps it using kmap_atomic for copying.
 808  *
 809  * This avoids taking mmap_sem for faulting on the user's address while the
 810  * struct_mutex is held.
 811  */
 812 static int
 813 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 814                            struct drm_i915_gem_pwrite *args,
 815                            struct drm_file *file_priv)
 816 {
 817         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 818         struct mm_struct *mm = current->mm;
 819         struct page **user_pages;
 820         ssize_t remain;
 821         loff_t offset, pinned_pages, i;
 822         loff_t first_data_page, last_data_page, num_pages;
 823         int shmem_page_index, shmem_page_offset;
 824         int data_page_index,  data_page_offset;
 825         int page_length;
 826         int ret;
 827         uint64_t data_ptr = args->data_ptr;
 828         int do_bit17_swizzling;
 829
 830         remain = args->size;
 831
 832         /* Pin the user pages containing the data.  We can't fault while
 833          * holding the struct mutex, and all of the pwrite implementations
 834          * want to hold it while dereferencing the user data.
 835          */
 836         first_data_page = data_ptr / PAGE_SIZE;
 837         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 838         num_pages = last_data_page - first_data_page + 1;
 839
 840         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 841         if (user_pages == NULL)
 842                 return -ENOMEM;
 843
 844         down_read(&mm->mmap_sem);
 845         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 846                                       num_pages, 0, 0, user_pages, NULL);
 847         up_read(&mm->mmap_sem);
 848         if (pinned_pages < num_pages) {
 849                 ret = -EFAULT;
 850                 goto fail_put_user_pages;
 851         }
 852
 853         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 854
 855         mutex_lock(&dev->struct_mutex);
 856
 857         ret = i915_gem_object_get_pages_or_evict(obj);
 858         if (ret)
 859                 goto fail_unlock;
 860
 861         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 862         if (ret != 0)
 863                 goto fail_put_pages;
 864
 865         obj_priv = to_intel_bo(obj);
 866         offset = args->offset;
 867         obj_priv->dirty = 1;
 868
 869         while (remain > 0) {
 870                 /* Operation in this page
 871                  *
 872                  * shmem_page_index = page number within shmem file
 873                  * shmem_page_offset = offset within page in shmem file
 874                  * data_page_index = page number in get_user_pages return
 875                  * data_page_offset = offset with data_page_index page.
 876                  * page_length = bytes to copy for this page
 877                  */
 878                 shmem_page_index = offset / PAGE_SIZE;
 879                 shmem_page_offset = offset & ~PAGE_MASK;
 880                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 881                 data_page_offset = data_ptr & ~PAGE_MASK;
 882
 883                 page_length = remain;
 884                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 885                         page_length = PAGE_SIZE - shmem_page_offset;
 886                 if ((data_page_offset + page_length) > PAGE_SIZE)
 887                         page_length = PAGE_SIZE - data_page_offset;
 888
 889                 if (do_bit17_swizzling) {
 890                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 891                                               shmem_page_offset,
 892                                               user_pages[data_page_index],
 893                                               data_page_offset,
 894                                               page_length,
 895                                               0);
 896                 } else {
 897                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 898                                         shmem_page_offset,
 899                                         user_pages[data_page_index],
 900                                         data_page_offset,
 901                                         page_length);
 902                 }
 903
 904                 remain -= page_length;
 905                 data_ptr += page_length;
 906                 offset += page_length;
 907         }
 908
 909 fail_put_pages:
 910         i915_gem_object_put_pages(obj);
 911 fail_unlock:
 912         mutex_unlock(&dev->struct_mutex);
 913 fail_put_user_pages:
 914         for (i = 0; i < pinned_pages; i++)
 915                 page_cache_release(user_pages[i]);
 916         drm_free_large(user_pages);
 917
 918         return ret;
 919 }
 920
 921 /**
 922  * Writes data to the object referenced by handle.
 923  *
 924  * On error, the contents of the buffer that were to be modified are undefined.
 925  */
 926 int
 927 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 928                       struct drm_file *file_priv)
 929 {
 930         struct drm_i915_gem_pwrite *args = data;
 931         struct drm_gem_object *obj;
 932         struct drm_i915_gem_object *obj_priv;
 933         int ret = 0;
 934
 935         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 936         if (obj == NULL)
 937                 return -ENOENT;
 938         obj_priv = to_intel_bo(obj);
 939
 940         /* Bounds check destination.
 941          *
 942          * XXX: This could use review for overflow issues...
 943          */
 944         if (args->offset > obj->size || args->size > obj->size ||
 945             args->offset + args->size > obj->size) {
 946                 drm_gem_object_unreference_unlocked(obj);
 947                 return -EINVAL;
 948         }
 949
 950         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 951          * it would end up going through the fenced access, and we'll get
 952          * different detiling behavior between reading and writing.
 953          * pread/pwrite currently are reading and writing from the CPU
 954          * perspective, requiring manual detiling by the client.
 955          */
 956         if (obj_priv->phys_obj)
 957                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 958         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 959                  dev->gtt_total != 0 &&
 960                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
 961                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 962                 if (ret == -EFAULT) {
 963                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 964                                                        file_priv);
 965                 }
 966         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 967                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 968         } else {
 969                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 970                 if (ret == -EFAULT) {
 971                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 972                                                          file_priv);
 973                 }
 974         }
 975
 976 #if WATCH_PWRITE
 977         if (ret)
 978                 DRM_INFO("pwrite failed %d\n", ret);
 979 #endif
 980
 981         drm_gem_object_unreference_unlocked(obj);
 982
 983         return ret;
 984 }
 985
 986 /**
 987  * Called when user space prepares to use an object with the CPU, either
 988  * through the mmap ioctl's mapping or a GTT mapping.
 989  */
 990 int
 991 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 992                           struct drm_file *file_priv)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         struct drm_i915_gem_set_domain *args = data;
 996         struct drm_gem_object *obj;
 997         struct drm_i915_gem_object *obj_priv;
 998         uint32_t read_domains = args->read_domains;
 999         uint32_t write_domain = args->write_domain;
1000         int ret;
1001
1002         if (!(dev->driver->driver_features & DRIVER_GEM))
1003                 return -ENODEV;
1004
1005         /* Only handle setting domains to types used by the CPU. */
1006         if (write_domain & I915_GEM_GPU_DOMAINS)
1007                 return -EINVAL;
1008
1009         if (read_domains & I915_GEM_GPU_DOMAINS)
1010                 return -EINVAL;
1011
1012         /* Having something in the write domain implies it's in the read
1013          * domain, and only that read domain.  Enforce that in the request.
1014          */
1015         if (write_domain != 0 && read_domains != write_domain)
1016                 return -EINVAL;
1017
1018         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1019         if (obj == NULL)
1020                 return -ENOENT;
1021         obj_priv = to_intel_bo(obj);
1022
1023         mutex_lock(&dev->struct_mutex);
1024
1025         intel_mark_busy(dev, obj);
1026
1027 #if WATCH_BUF
1028         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1029                  obj, obj->size, read_domains, write_domain);
1030 #endif
1031         if (read_domains & I915_GEM_DOMAIN_GTT) {
1032                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1033
1034                 /* Update the LRU on the fence for the CPU access that's
1035                  * about to occur.
1036                  */
1037                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1038                         struct drm_i915_fence_reg *reg =
1039                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1040                         list_move_tail(&reg->lru_list,
1041                                        &dev_priv->mm.fence_list);
1042                 }
1043
1044                 /* Silently promote "you're not bound, there was nothing to do"
1045                  * to success, since the client was just asking us to
1046                  * make sure everything was done.
1047                  */
1048                 if (ret == -EINVAL)
1049                         ret = 0;
1050         } else {
1051                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1052         }
1053
1054
1055         /* Maintain LRU order of "inactive" objects */
1056         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1057                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1058
1059         drm_gem_object_unreference(obj);
1060         mutex_unlock(&dev->struct_mutex);
1061         return ret;
1062 }
1063
1064 /**
1065  * Called when user space has done writes to this buffer
1066  */
1067 int
1068 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1069                       struct drm_file *file_priv)
1070 {
1071         struct drm_i915_gem_sw_finish *args = data;
1072         struct drm_gem_object *obj;
1073         struct drm_i915_gem_object *obj_priv;
1074         int ret = 0;
1075
1076         if (!(dev->driver->driver_features & DRIVER_GEM))
1077                 return -ENODEV;
1078
1079         mutex_lock(&dev->struct_mutex);
1080         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1081         if (obj == NULL) {
1082                 mutex_unlock(&dev->struct_mutex);
1083                 return -ENOENT;
1084         }
1085
1086 #if WATCH_BUF
1087         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1088                  __func__, args->handle, obj, obj->size);
1089 #endif
1090         obj_priv = to_intel_bo(obj);
1091
1092         /* Pinned buffers may be scanout, so flush the cache */
1093         if (obj_priv->pin_count)
1094                 i915_gem_object_flush_cpu_write_domain(obj);
1095
1096         drm_gem_object_unreference(obj);
1097         mutex_unlock(&dev->struct_mutex);
1098         return ret;
1099 }
1100
1101 /**
1102  * Maps the contents of an object, returning the address it is mapped
1103  * into.
1104  *
1105  * While the mapping holds a reference on the contents of the object, it doesn't
1106  * imply a ref on the object itself.
1107  */
1108 int
1109 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110                    struct drm_file *file_priv)
1111 {
1112         struct drm_i915_gem_mmap *args = data;
1113         struct drm_gem_object *obj;
1114         loff_t offset;
1115         unsigned long addr;
1116
1117         if (!(dev->driver->driver_features & DRIVER_GEM))
1118                 return -ENODEV;
1119
1120         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1121         if (obj == NULL)
1122                 return -ENOENT;
1123
1124         offset = args->offset;
1125
1126         down_write(&current->mm->mmap_sem);
1127         addr = do_mmap(obj->filp, 0, args->size,
1128                        PROT_READ | PROT_WRITE, MAP_SHARED,
1129                        args->offset);
1130         up_write(&current->mm->mmap_sem);
1131         drm_gem_object_unreference_unlocked(obj);
1132         if (IS_ERR((void *)addr))
1133                 return addr;
1134
1135         args->addr_ptr = (uint64_t) addr;
1136
1137         return 0;
1138 }
1139
1140 /**
1141  * i915_gem_fault - fault a page into the GTT
1142  * vma: VMA in question
1143  * vmf: fault info
1144  *
1145  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146  * from userspace.  The fault handler takes care of binding the object to
1147  * the GTT (if needed), allocating and programming a fence register (again,
1148  * only if needed based on whether the old reg is still valid or the object
1149  * is tiled) and inserting a new PTE into the faulting process.
1150  *
1151  * Note that the faulting process may involve evicting existing objects
1152  * from the GTT and/or fence registers to make room.  So performance may
1153  * suffer if the GTT working set is large or there are few fence registers
1154  * left.
1155  */
1156 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1157 {
1158         struct drm_gem_object *obj = vma->vm_private_data;
1159         struct drm_device *dev = obj->dev;
1160         drm_i915_private_t *dev_priv = dev->dev_private;
1161         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1162         pgoff_t page_offset;
1163         unsigned long pfn;
1164         int ret = 0;
1165         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1166
1167         /* We don't use vmf->pgoff since that has the fake offset */
1168         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1169                 PAGE_SHIFT;
1170
1171         /* Now bind it into the GTT if needed */
1172         mutex_lock(&dev->struct_mutex);
1173         if (!obj_priv->gtt_space) {
1174                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1175                 if (ret)
1176                         goto unlock;
1177
1178                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1179                 if (ret)
1180                         goto unlock;
1181         }
1182
1183         /* Need a new fence register? */
1184         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1185                 ret = i915_gem_object_get_fence_reg(obj, true);
1186                 if (ret)
1187                         goto unlock;
1188         }
1189
1190         if (i915_gem_object_is_inactive(obj_priv))
1191                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192
1193         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1194                 page_offset;
1195
1196         /* Finally, remap it using the new GTT offset */
1197         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1198 unlock:
1199         mutex_unlock(&dev->struct_mutex);
1200
1201         switch (ret) {
1202         case 0:
1203         case -ERESTARTSYS:
1204                 return VM_FAULT_NOPAGE;
1205         case -ENOMEM:
1206         case -EAGAIN:
1207                 return VM_FAULT_OOM;
1208         default:
1209                 return VM_FAULT_SIGBUS;
1210         }
1211 }
1212
1213 /**
1214  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215  * @obj: obj in question
1216  *
1217  * GEM memory mapping works by handing back to userspace a fake mmap offset
1218  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1219  * up the object based on the offset and sets up the various memory mapping
1220  * structures.
1221  *
1222  * This routine allocates and attaches a fake offset for @obj.
1223  */
1224 static int
1225 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1226 {
1227         struct drm_device *dev = obj->dev;
1228         struct drm_gem_mm *mm = dev->mm_private;
1229         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1230         struct drm_map_list *list;
1231         struct drm_local_map *map;
1232         int ret = 0;
1233
1234         /* Set the object up for mmap'ing */
1235         list = &obj->map_list;
1236         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1237         if (!list->map)
1238                 return -ENOMEM;
1239
1240         map = list->map;
1241         map->type = _DRM_GEM;
1242         map->size = obj->size;
1243         map->handle = obj;
1244
1245         /* Get a DRM GEM mmap offset allocated... */
1246         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1247                                                     obj->size / PAGE_SIZE, 0, 0);
1248         if (!list->file_offset_node) {
1249                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1250                 ret = -ENOMEM;
1251                 goto out_free_list;
1252         }
1253
1254         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1255                                                   obj->size / PAGE_SIZE, 0);
1256         if (!list->file_offset_node) {
1257                 ret = -ENOMEM;
1258                 goto out_free_list;
1259         }
1260
1261         list->hash.key = list->file_offset_node->start;
1262         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1263                 DRM_ERROR("failed to add to map hash\n");
1264                 ret = -ENOMEM;
1265                 goto out_free_mm;
1266         }
1267
1268         /* By now we should be all set, any drm_mmap request on the offset
1269          * below will get to our mmap & fault handler */
1270         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1271
1272         return 0;
1273
1274 out_free_mm:
1275         drm_mm_put_block(list->file_offset_node);
1276 out_free_list:
1277         kfree(list->map);
1278
1279         return ret;
1280 }
1281
1282 /**
1283  * i915_gem_release_mmap - remove physical page mappings
1284  * @obj: obj in question
1285  *
1286  * Preserve the reservation of the mmapping with the DRM core code, but
1287  * relinquish ownership of the pages back to the system.
1288  *
1289  * It is vital that we remove the page mapping if we have mapped a tiled
1290  * object through the GTT and then lose the fence register due to
1291  * resource pressure. Similarly if the object has been moved out of the
1292  * aperture, than pages mapped into userspace must be revoked. Removing the
1293  * mapping will then trigger a page fault on the next user access, allowing
1294  * fixup by i915_gem_fault().
1295  */
1296 void
1297 i915_gem_release_mmap(struct drm_gem_object *obj)
1298 {
1299         struct drm_device *dev = obj->dev;
1300         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1301
1302         if (dev->dev_mapping)
1303                 unmap_mapping_range(dev->dev_mapping,
1304                                     obj_priv->mmap_offset, obj->size, 1);
1305 }
1306
1307 static void
1308 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1312         struct drm_gem_mm *mm = dev->mm_private;
1313         struct drm_map_list *list;
1314
1315         list = &obj->map_list;
1316         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1317
1318         if (list->file_offset_node) {
1319                 drm_mm_put_block(list->file_offset_node);
1320                 list->file_offset_node = NULL;
1321         }
1322
1323         if (list->map) {
1324                 kfree(list->map);
1325                 list->map = NULL;
1326         }
1327
1328         obj_priv->mmap_offset = 0;
1329 }
1330
1331 /**
1332  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333  * @obj: object to check
1334  *
1335  * Return the required GTT alignment for an object, taking into account
1336  * potential fence register mapping if needed.
1337  */
1338 static uint32_t
1339 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1340 {
1341         struct drm_device *dev = obj->dev;
1342         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1343         int start, i;
1344
1345         /*
1346          * Minimum alignment is 4k (GTT page size), but might be greater
1347          * if a fence register is needed for the object.
1348          */
1349         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1350                 return 4096;
1351
1352         /*
1353          * Previous chips need to be aligned to the size of the smallest
1354          * fence register that can contain the object.
1355          */
1356         if (IS_I9XX(dev))
1357                 start = 1024*1024;
1358         else
1359                 start = 512*1024;
1360
1361         for (i = start; i < obj->size; i <<= 1)
1362                 ;
1363
1364         return i;
1365 }
1366
1367 /**
1368  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1369  * @dev: DRM device
1370  * @data: GTT mapping ioctl data
1371  * @file_priv: GEM object info
1372  *
1373  * Simply returns the fake offset to userspace so it can mmap it.
1374  * The mmap call will end up in drm_gem_mmap(), which will set things
1375  * up so we can get faults in the handler above.
1376  *
1377  * The fault handler will take care of binding the object into the GTT
1378  * (since it may have been evicted to make room for something), allocating
1379  * a fence register, and mapping the appropriate aperture address into
1380  * userspace.
1381  */
1382 int
1383 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1384                         struct drm_file *file_priv)
1385 {
1386         struct drm_i915_gem_mmap_gtt *args = data;
1387         struct drm_gem_object *obj;
1388         struct drm_i915_gem_object *obj_priv;
1389         int ret;
1390
1391         if (!(dev->driver->driver_features & DRIVER_GEM))
1392                 return -ENODEV;
1393
1394         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1395         if (obj == NULL)
1396                 return -ENOENT;
1397
1398         mutex_lock(&dev->struct_mutex);
1399
1400         obj_priv = to_intel_bo(obj);
1401
1402         if (obj_priv->madv != I915_MADV_WILLNEED) {
1403                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404                 drm_gem_object_unreference(obj);
1405                 mutex_unlock(&dev->struct_mutex);
1406                 return -EINVAL;
1407         }
1408
1409
1410         if (!obj_priv->mmap_offset) {
1411                 ret = i915_gem_create_mmap_offset(obj);
1412                 if (ret) {
1413                         drm_gem_object_unreference(obj);
1414                         mutex_unlock(&dev->struct_mutex);
1415                         return ret;
1416                 }
1417         }
1418
1419         args->offset = obj_priv->mmap_offset;
1420
1421         /*
1422          * Pull it into the GTT so that we have a page list (makes the
1423          * initial fault faster and any subsequent flushing possible).
1424          */
1425         if (!obj_priv->agp_mem) {
1426                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1427                 if (ret) {
1428                         drm_gem_object_unreference(obj);
1429                         mutex_unlock(&dev->struct_mutex);
1430                         return ret;
1431                 }
1432         }
1433
1434         drm_gem_object_unreference(obj);
1435         mutex_unlock(&dev->struct_mutex);
1436
1437         return 0;
1438 }
1439
1440 void
1441 i915_gem_object_put_pages(struct drm_gem_object *obj)
1442 {
1443         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1444         int page_count = obj->size / PAGE_SIZE;
1445         int i;
1446
1447         BUG_ON(obj_priv->pages_refcount == 0);
1448         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1449
1450         if (--obj_priv->pages_refcount != 0)
1451                 return;
1452
1453         if (obj_priv->tiling_mode != I915_TILING_NONE)
1454                 i915_gem_object_save_bit_17_swizzle(obj);
1455
1456         if (obj_priv->madv == I915_MADV_DONTNEED)
1457                 obj_priv->dirty = 0;
1458
1459         for (i = 0; i < page_count; i++) {
1460                 if (obj_priv->dirty)
1461                         set_page_dirty(obj_priv->pages[i]);
1462
1463                 if (obj_priv->madv == I915_MADV_WILLNEED)
1464                         mark_page_accessed(obj_priv->pages[i]);
1465
1466                 page_cache_release(obj_priv->pages[i]);
1467         }
1468         obj_priv->dirty = 0;
1469
1470         drm_free_large(obj_priv->pages);
1471         obj_priv->pages = NULL;
1472 }
1473
1474 static uint32_t
1475 i915_gem_next_request_seqno(struct drm_device *dev,
1476                             struct intel_ring_buffer *ring)
1477 {
1478         drm_i915_private_t *dev_priv = dev->dev_private;
1479
1480         ring->outstanding_lazy_request = true;
1481
1482         return dev_priv->next_seqno;
1483 }
1484
1485 static void
1486 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1487                                struct intel_ring_buffer *ring)
1488 {
1489         struct drm_device *dev = obj->dev;
1490         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1492
1493         BUG_ON(ring == NULL);
1494         obj_priv->ring = ring;
1495
1496         /* Add a reference if we're newly entering the active list. */
1497         if (!obj_priv->active) {
1498                 drm_gem_object_reference(obj);
1499                 obj_priv->active = 1;
1500         }
1501
1502         /* Move from whatever list we were on to the tail of execution. */
1503         list_move_tail(&obj_priv->list, &ring->active_list);
1504         obj_priv->last_rendering_seqno = seqno;
1505 }
1506
1507 static void
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1509 {
1510         struct drm_device *dev = obj->dev;
1511         drm_i915_private_t *dev_priv = dev->dev_private;
1512         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1513
1514         BUG_ON(!obj_priv->active);
1515         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516         obj_priv->last_rendering_seqno = 0;
1517 }
1518
1519 /* Immediately discard the backing storage */
1520 static void
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1522 {
1523         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1524         struct inode *inode;
1525
1526         /* Our goal here is to return as much of the memory as
1527          * is possible back to the system as we are called from OOM.
1528          * To do this we must instruct the shmfs to drop all of its
1529          * backing pages, *now*. Here we mirror the actions taken
1530          * when by shmem_delete_inode() to release the backing store.
1531          */
1532         inode = obj->filp->f_path.dentry->d_inode;
1533         truncate_inode_pages(inode->i_mapping, 0);
1534         if (inode->i_op->truncate_range)
1535                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1536
1537         obj_priv->madv = __I915_MADV_PURGED;
1538 }
1539
1540 static inline int
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1542 {
1543         return obj_priv->madv == I915_MADV_DONTNEED;
1544 }
1545
1546 static void
1547 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1548 {
1549         struct drm_device *dev = obj->dev;
1550         drm_i915_private_t *dev_priv = dev->dev_private;
1551         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1552
1553         i915_verify_inactive(dev, __FILE__, __LINE__);
1554         if (obj_priv->pin_count != 0)
1555                 list_del_init(&obj_priv->list);
1556         else
1557                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1558
1559         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1560
1561         obj_priv->last_rendering_seqno = 0;
1562         obj_priv->ring = NULL;
1563         if (obj_priv->active) {
1564                 obj_priv->active = 0;
1565                 drm_gem_object_unreference(obj);
1566         }
1567         i915_verify_inactive(dev, __FILE__, __LINE__);
1568 }
1569
1570 void
1571 i915_gem_process_flushing_list(struct drm_device *dev,
1572                                uint32_t flush_domains,
1573                                struct intel_ring_buffer *ring)
1574 {
1575         drm_i915_private_t *dev_priv = dev->dev_private;
1576         struct drm_i915_gem_object *obj_priv, *next;
1577
1578         list_for_each_entry_safe(obj_priv, next,
1579                                  &dev_priv->mm.gpu_write_list,
1580                                  gpu_write_list) {
1581                 struct drm_gem_object *obj = &obj_priv->base;
1582
1583                 if (obj->write_domain & flush_domains &&
1584                     obj_priv->ring == ring) {
1585                         uint32_t old_write_domain = obj->write_domain;
1586
1587                         obj->write_domain = 0;
1588                         list_del_init(&obj_priv->gpu_write_list);
1589                         i915_gem_object_move_to_active(obj, ring);
1590
1591                         /* update the fence lru list */
1592                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1593                                 struct drm_i915_fence_reg *reg =
1594                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1595                                 list_move_tail(&reg->lru_list,
1596                                                 &dev_priv->mm.fence_list);
1597                         }
1598
1599                         trace_i915_gem_object_change_domain(obj,
1600                                                             obj->read_domains,
1601                                                             old_write_domain);
1602                 }
1603         }
1604 }
1605
1606 uint32_t
1607 i915_add_request(struct drm_device *dev,
1608                  struct drm_file *file_priv,
1609                  struct drm_i915_gem_request *request,
1610                  struct intel_ring_buffer *ring)
1611 {
1612         drm_i915_private_t *dev_priv = dev->dev_private;
1613         struct drm_i915_file_private *i915_file_priv = NULL;
1614         uint32_t seqno;
1615         int was_empty;
1616
1617         if (file_priv != NULL)
1618                 i915_file_priv = file_priv->driver_priv;
1619
1620         if (request == NULL) {
1621                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1622                 if (request == NULL)
1623                         return 0;
1624         }
1625
1626         seqno = ring->add_request(dev, ring, file_priv, 0);
1627
1628         request->seqno = seqno;
1629         request->ring = ring;
1630         request->emitted_jiffies = jiffies;
1631         was_empty = list_empty(&ring->request_list);
1632         list_add_tail(&request->list, &ring->request_list);
1633
1634         if (i915_file_priv) {
1635                 list_add_tail(&request->client_list,
1636                               &i915_file_priv->mm.request_list);
1637         } else {
1638                 INIT_LIST_HEAD(&request->client_list);
1639         }
1640
1641         if (!dev_priv->mm.suspended) {
1642                 mod_timer(&dev_priv->hangcheck_timer,
1643                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1644                 if (was_empty)
1645                         queue_delayed_work(dev_priv->wq,
1646                                            &dev_priv->mm.retire_work, HZ);
1647         }
1648         return seqno;
1649 }
1650
1651 /**
1652  * Command execution barrier
1653  *
1654  * Ensures that all commands in the ring are finished
1655  * before signalling the CPU
1656  */
1657 static void
1658 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1659 {
1660         uint32_t flush_domains = 0;
1661
1662         /* The sampler always gets flushed on i965 (sigh) */
1663         if (IS_I965G(dev))
1664                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1665
1666         ring->flush(dev, ring,
1667                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1668 }
1669
1670 /**
1671  * Moves buffers associated only with the given active seqno from the active
1672  * to inactive list, potentially freeing them.
1673  */
1674 static void
1675 i915_gem_retire_request(struct drm_device *dev,
1676                         struct drm_i915_gem_request *request)
1677 {
1678         trace_i915_gem_request_retire(dev, request->seqno);
1679
1680         /* Move any buffers on the active list that are no longer referenced
1681          * by the ringbuffer to the flushing/inactive lists as appropriate.
1682          */
1683         while (!list_empty(&request->ring->active_list)) {
1684                 struct drm_gem_object *obj;
1685                 struct drm_i915_gem_object *obj_priv;
1686
1687                 obj_priv = list_first_entry(&request->ring->active_list,
1688                                             struct drm_i915_gem_object,
1689                                             list);
1690                 obj = &obj_priv->base;
1691
1692                 /* If the seqno being retired doesn't match the oldest in the
1693                  * list, then the oldest in the list must still be newer than
1694                  * this seqno.
1695                  */
1696                 if (obj_priv->last_rendering_seqno != request->seqno)
1697                         return;
1698
1699 #if WATCH_LRU
1700                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1701                          __func__, request->seqno, obj);
1702 #endif
1703
1704                 if (obj->write_domain != 0)
1705                         i915_gem_object_move_to_flushing(obj);
1706                 else
1707                         i915_gem_object_move_to_inactive(obj);
1708         }
1709 }
1710
1711 /**
1712  * Returns true if seq1 is later than seq2.
1713  */
1714 bool
1715 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1716 {
1717         return (int32_t)(seq1 - seq2) >= 0;
1718 }
1719
1720 uint32_t
1721 i915_get_gem_seqno(struct drm_device *dev,
1722                    struct intel_ring_buffer *ring)
1723 {
1724         return ring->get_gem_seqno(dev, ring);
1725 }
1726
1727 /**
1728  * This function clears the request list as sequence numbers are passed.
1729  */
1730 static void
1731 i915_gem_retire_requests_ring(struct drm_device *dev,
1732                               struct intel_ring_buffer *ring)
1733 {
1734         drm_i915_private_t *dev_priv = dev->dev_private;
1735         uint32_t seqno;
1736
1737         if (!ring->status_page.page_addr
1738                         || list_empty(&ring->request_list))
1739                 return;
1740
1741         seqno = i915_get_gem_seqno(dev, ring);
1742
1743         while (!list_empty(&ring->request_list)) {
1744                 struct drm_i915_gem_request *request;
1745                 uint32_t retiring_seqno;
1746
1747                 request = list_first_entry(&ring->request_list,
1748                                            struct drm_i915_gem_request,
1749                                            list);
1750                 retiring_seqno = request->seqno;
1751
1752                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1753                     atomic_read(&dev_priv->mm.wedged)) {
1754                         i915_gem_retire_request(dev, request);
1755
1756                         list_del(&request->list);
1757                         list_del(&request->client_list);
1758                         kfree(request);
1759                 } else
1760                         break;
1761         }
1762
1763         if (unlikely (dev_priv->trace_irq_seqno &&
1764                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1765
1766                 ring->user_irq_put(dev, ring);
1767                 dev_priv->trace_irq_seqno = 0;
1768         }
1769 }
1770
1771 void
1772 i915_gem_retire_requests(struct drm_device *dev)
1773 {
1774         drm_i915_private_t *dev_priv = dev->dev_private;
1775
1776         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1777             struct drm_i915_gem_object *obj_priv, *tmp;
1778
1779             /* We must be careful that during unbind() we do not
1780              * accidentally infinitely recurse into retire requests.
1781              * Currently:
1782              *   retire -> free -> unbind -> wait -> retire_ring
1783              */
1784             list_for_each_entry_safe(obj_priv, tmp,
1785                                      &dev_priv->mm.deferred_free_list,
1786                                      list)
1787                     i915_gem_free_object_tail(&obj_priv->base);
1788         }
1789
1790         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1791         if (HAS_BSD(dev))
1792                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1793 }
1794
1795 static void
1796 i915_gem_retire_work_handler(struct work_struct *work)
1797 {
1798         drm_i915_private_t *dev_priv;
1799         struct drm_device *dev;
1800
1801         dev_priv = container_of(work, drm_i915_private_t,
1802                                 mm.retire_work.work);
1803         dev = dev_priv->dev;
1804
1805         mutex_lock(&dev->struct_mutex);
1806         i915_gem_retire_requests(dev);
1807
1808         if (!dev_priv->mm.suspended &&
1809                 (!list_empty(&dev_priv->render_ring.request_list) ||
1810                         (HAS_BSD(dev) &&
1811                          !list_empty(&dev_priv->bsd_ring.request_list))))
1812                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1813         mutex_unlock(&dev->struct_mutex);
1814 }
1815
1816 int
1817 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1818                      bool interruptible, struct intel_ring_buffer *ring)
1819 {
1820         drm_i915_private_t *dev_priv = dev->dev_private;
1821         u32 ier;
1822         int ret = 0;
1823
1824         BUG_ON(seqno == 0);
1825
1826         if (seqno == dev_priv->next_seqno) {
1827                 seqno = i915_add_request(dev, NULL, NULL, ring);
1828                 if (seqno == 0)
1829                         return -ENOMEM;
1830         }
1831
1832         if (atomic_read(&dev_priv->mm.wedged))
1833                 return -EIO;
1834
1835         if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1836                 if (HAS_PCH_SPLIT(dev))
1837                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1838                 else
1839                         ier = I915_READ(IER);
1840                 if (!ier) {
1841                         DRM_ERROR("something (likely vbetool) disabled "
1842                                   "interrupts, re-enabling\n");
1843                         i915_driver_irq_preinstall(dev);
1844                         i915_driver_irq_postinstall(dev);
1845                 }
1846
1847                 trace_i915_gem_request_wait_begin(dev, seqno);
1848
1849                 ring->waiting_gem_seqno = seqno;
1850                 ring->user_irq_get(dev, ring);
1851                 if (interruptible)
1852                         ret = wait_event_interruptible(ring->irq_queue,
1853                                 i915_seqno_passed(
1854                                         ring->get_gem_seqno(dev, ring), seqno)
1855                                 || atomic_read(&dev_priv->mm.wedged));
1856                 else
1857                         wait_event(ring->irq_queue,
1858                                 i915_seqno_passed(
1859                                         ring->get_gem_seqno(dev, ring), seqno)
1860                                 || atomic_read(&dev_priv->mm.wedged));
1861
1862                 ring->user_irq_put(dev, ring);
1863                 ring->waiting_gem_seqno = 0;
1864
1865                 trace_i915_gem_request_wait_end(dev, seqno);
1866         }
1867         if (atomic_read(&dev_priv->mm.wedged))
1868                 ret = -EIO;
1869
1870         if (ret && ret != -ERESTARTSYS)
1871                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1872                           __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1873                           dev_priv->next_seqno);
1874
1875         /* Directly dispatch request retiring.  While we have the work queue
1876          * to handle this, the waiter on a request often wants an associated
1877          * buffer to have made it to the inactive list, and we would need
1878          * a separate wait queue to handle that.
1879          */
1880         if (ret == 0)
1881                 i915_gem_retire_requests_ring(dev, ring);
1882
1883         return ret;
1884 }
1885
1886 /**
1887  * Waits for a sequence number to be signaled, and cleans up the
1888  * request and object lists appropriately for that event.
1889  */
1890 static int
1891 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1892                 struct intel_ring_buffer *ring)
1893 {
1894         return i915_do_wait_request(dev, seqno, 1, ring);
1895 }
1896
1897 static void
1898 i915_gem_flush(struct drm_device *dev,
1899                uint32_t invalidate_domains,
1900                uint32_t flush_domains)
1901 {
1902         drm_i915_private_t *dev_priv = dev->dev_private;
1903
1904         if (flush_domains & I915_GEM_DOMAIN_CPU)
1905                 drm_agp_chipset_flush(dev);
1906
1907         dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1908                         invalidate_domains,
1909                         flush_domains);
1910
1911         if (HAS_BSD(dev))
1912                 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1913                                 invalidate_domains,
1914                                 flush_domains);
1915 }
1916
1917 /**
1918  * Ensures that all rendering to the object has completed and the object is
1919  * safe to unbind from the GTT or access from the CPU.
1920  */
1921 static int
1922 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1923                                bool interruptible)
1924 {
1925         struct drm_device *dev = obj->dev;
1926         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1927         int ret;
1928
1929         /* This function only exists to support waiting for existing rendering,
1930          * not for emitting required flushes.
1931          */
1932         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1933
1934         /* If there is rendering queued on the buffer being evicted, wait for
1935          * it.
1936          */
1937         if (obj_priv->active) {
1938 #if WATCH_BUF
1939                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1940                           __func__, obj, obj_priv->last_rendering_seqno);
1941 #endif
1942                 ret = i915_do_wait_request(dev,
1943                                            obj_priv->last_rendering_seqno,
1944                                            interruptible,
1945                                            obj_priv->ring);
1946                 if (ret)
1947                         return ret;
1948         }
1949
1950         return 0;
1951 }
1952
1953 /**
1954  * Unbinds an object from the GTT aperture.
1955  */
1956 int
1957 i915_gem_object_unbind(struct drm_gem_object *obj)
1958 {
1959         struct drm_device *dev = obj->dev;
1960         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1961         int ret = 0;
1962
1963 #if WATCH_BUF
1964         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1965         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1966 #endif
1967         if (obj_priv->gtt_space == NULL)
1968                 return 0;
1969
1970         if (obj_priv->pin_count != 0) {
1971                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1972                 return -EINVAL;
1973         }
1974
1975         /* blow away mappings if mapped through GTT */
1976         i915_gem_release_mmap(obj);
1977
1978         /* Move the object to the CPU domain to ensure that
1979          * any possible CPU writes while it's not in the GTT
1980          * are flushed when we go to remap it. This will
1981          * also ensure that all pending GPU writes are finished
1982          * before we unbind.
1983          */
1984         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1985         if (ret == -ERESTARTSYS)
1986                 return ret;
1987         /* Continue on if we fail due to EIO, the GPU is hung so we
1988          * should be safe and we need to cleanup or else we might
1989          * cause memory corruption through use-after-free.
1990          */
1991
1992         /* release the fence reg _after_ flushing */
1993         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1994                 i915_gem_clear_fence_reg(obj);
1995
1996         if (obj_priv->agp_mem != NULL) {
1997                 drm_unbind_agp(obj_priv->agp_mem);
1998                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1999                 obj_priv->agp_mem = NULL;
2000         }
2001
2002         i915_gem_object_put_pages(obj);
2003         BUG_ON(obj_priv->pages_refcount);
2004
2005         if (obj_priv->gtt_space) {
2006                 atomic_dec(&dev->gtt_count);
2007                 atomic_sub(obj->size, &dev->gtt_memory);
2008
2009                 drm_mm_put_block(obj_priv->gtt_space);
2010                 obj_priv->gtt_space = NULL;
2011         }
2012
2013         /* Remove ourselves from the LRU list if present. */
2014         if (!list_empty(&obj_priv->list))
2015                 list_del_init(&obj_priv->list);
2016
2017         if (i915_gem_object_is_purgeable(obj_priv))
2018                 i915_gem_object_truncate(obj);
2019
2020         trace_i915_gem_object_unbind(obj);
2021
2022         return ret;
2023 }
2024
2025 int
2026 i915_gpu_idle(struct drm_device *dev)
2027 {
2028         drm_i915_private_t *dev_priv = dev->dev_private;
2029         bool lists_empty;
2030         int ret;
2031
2032         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2033                        list_empty(&dev_priv->render_ring.active_list) &&
2034                        (!HAS_BSD(dev) ||
2035                         list_empty(&dev_priv->bsd_ring.active_list)));
2036         if (lists_empty)
2037                 return 0;
2038
2039         /* Flush everything onto the inactive list. */
2040         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2041
2042         ret = i915_wait_request(dev,
2043                                 i915_gem_next_request_seqno(dev, &dev_priv->render_ring),
2044                                 &dev_priv->render_ring);
2045         if (ret)
2046                 return ret;
2047
2048         if (HAS_BSD(dev)) {
2049                 ret = i915_wait_request(dev,
2050                                         i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring),
2051                                         &dev_priv->bsd_ring);
2052                 if (ret)
2053                         return ret;
2054         }
2055
2056         return 0;
2057 }
2058
2059 int
2060 i915_gem_object_get_pages(struct drm_gem_object *obj,
2061                           gfp_t gfpmask)
2062 {
2063         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2064         int page_count, i;
2065         struct address_space *mapping;
2066         struct inode *inode;
2067         struct page *page;
2068
2069         BUG_ON(obj_priv->pages_refcount
2070                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2071
2072         if (obj_priv->pages_refcount++ != 0)
2073                 return 0;
2074
2075         /* Get the list of pages out of our struct file.  They'll be pinned
2076          * at this point until we release them.
2077          */
2078         page_count = obj->size / PAGE_SIZE;
2079         BUG_ON(obj_priv->pages != NULL);
2080         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2081         if (obj_priv->pages == NULL) {
2082                 obj_priv->pages_refcount--;
2083                 return -ENOMEM;
2084         }
2085
2086         inode = obj->filp->f_path.dentry->d_inode;
2087         mapping = inode->i_mapping;
2088         for (i = 0; i < page_count; i++) {
2089                 page = read_cache_page_gfp(mapping, i,
2090                                            GFP_HIGHUSER |
2091                                            __GFP_COLD |
2092                                            __GFP_RECLAIMABLE |
2093                                            gfpmask);
2094                 if (IS_ERR(page))
2095                         goto err_pages;
2096
2097                 obj_priv->pages[i] = page;
2098         }
2099
2100         if (obj_priv->tiling_mode != I915_TILING_NONE)
2101                 i915_gem_object_do_bit_17_swizzle(obj);
2102
2103         return 0;
2104
2105 err_pages:
2106         while (i--)
2107                 page_cache_release(obj_priv->pages[i]);
2108
2109         drm_free_large(obj_priv->pages);
2110         obj_priv->pages = NULL;
2111         obj_priv->pages_refcount--;
2112         return PTR_ERR(page);
2113 }
2114
2115 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2116 {
2117         struct drm_gem_object *obj = reg->obj;
2118         struct drm_device *dev = obj->dev;
2119         drm_i915_private_t *dev_priv = dev->dev_private;
2120         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2121         int regnum = obj_priv->fence_reg;
2122         uint64_t val;
2123
2124         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2125                     0xfffff000) << 32;
2126         val |= obj_priv->gtt_offset & 0xfffff000;
2127         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2128                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2129
2130         if (obj_priv->tiling_mode == I915_TILING_Y)
2131                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2132         val |= I965_FENCE_REG_VALID;
2133
2134         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2135 }
2136
2137 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2138 {
2139         struct drm_gem_object *obj = reg->obj;
2140         struct drm_device *dev = obj->dev;
2141         drm_i915_private_t *dev_priv = dev->dev_private;
2142         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2143         int regnum = obj_priv->fence_reg;
2144         uint64_t val;
2145
2146         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2147                     0xfffff000) << 32;
2148         val |= obj_priv->gtt_offset & 0xfffff000;
2149         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2150         if (obj_priv->tiling_mode == I915_TILING_Y)
2151                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2152         val |= I965_FENCE_REG_VALID;
2153
2154         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2155 }
2156
2157 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2158 {
2159         struct drm_gem_object *obj = reg->obj;
2160         struct drm_device *dev = obj->dev;
2161         drm_i915_private_t *dev_priv = dev->dev_private;
2162         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2163         int regnum = obj_priv->fence_reg;
2164         int tile_width;
2165         uint32_t fence_reg, val;
2166         uint32_t pitch_val;
2167
2168         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2169             (obj_priv->gtt_offset & (obj->size - 1))) {
2170                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2171                      __func__, obj_priv->gtt_offset, obj->size);
2172                 return;
2173         }
2174
2175         if (obj_priv->tiling_mode == I915_TILING_Y &&
2176             HAS_128_BYTE_Y_TILING(dev))
2177                 tile_width = 128;
2178         else
2179                 tile_width = 512;
2180
2181         /* Note: pitch better be a power of two tile widths */
2182         pitch_val = obj_priv->stride / tile_width;
2183         pitch_val = ffs(pitch_val) - 1;
2184
2185         if (obj_priv->tiling_mode == I915_TILING_Y &&
2186             HAS_128_BYTE_Y_TILING(dev))
2187                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2188         else
2189                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2190
2191         val = obj_priv->gtt_offset;
2192         if (obj_priv->tiling_mode == I915_TILING_Y)
2193                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2194         val |= I915_FENCE_SIZE_BITS(obj->size);
2195         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2196         val |= I830_FENCE_REG_VALID;
2197
2198         if (regnum < 8)
2199                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2200         else
2201                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2202         I915_WRITE(fence_reg, val);
2203 }
2204
2205 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2206 {
2207         struct drm_gem_object *obj = reg->obj;
2208         struct drm_device *dev = obj->dev;
2209         drm_i915_private_t *dev_priv = dev->dev_private;
2210         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2211         int regnum = obj_priv->fence_reg;
2212         uint32_t val;
2213         uint32_t pitch_val;
2214         uint32_t fence_size_bits;
2215
2216         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2217             (obj_priv->gtt_offset & (obj->size - 1))) {
2218                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2219                      __func__, obj_priv->gtt_offset);
2220                 return;
2221         }
2222
2223         pitch_val = obj_priv->stride / 128;
2224         pitch_val = ffs(pitch_val) - 1;
2225         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2226
2227         val = obj_priv->gtt_offset;
2228         if (obj_priv->tiling_mode == I915_TILING_Y)
2229                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2230         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2231         WARN_ON(fence_size_bits & ~0x00000f00);
2232         val |= fence_size_bits;
2233         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2234         val |= I830_FENCE_REG_VALID;
2235
2236         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2237 }
2238
2239 static int i915_find_fence_reg(struct drm_device *dev,
2240                                bool interruptible)
2241 {
2242         struct drm_i915_fence_reg *reg = NULL;
2243         struct drm_i915_gem_object *obj_priv = NULL;
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct drm_gem_object *obj = NULL;
2246         int i, avail, ret;
2247
2248         /* First try to find a free reg */
2249         avail = 0;
2250         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2251                 reg = &dev_priv->fence_regs[i];
2252                 if (!reg->obj)
2253                         return i;
2254
2255                 obj_priv = to_intel_bo(reg->obj);
2256                 if (!obj_priv->pin_count)
2257                     avail++;
2258         }
2259
2260         if (avail == 0)
2261                 return -ENOSPC;
2262
2263         /* None available, try to steal one or wait for a user to finish */
2264         i = I915_FENCE_REG_NONE;
2265         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2266                             lru_list) {
2267                 obj = reg->obj;
2268                 obj_priv = to_intel_bo(obj);
2269
2270                 if (obj_priv->pin_count)
2271                         continue;
2272
2273                 /* found one! */
2274                 i = obj_priv->fence_reg;
2275                 break;
2276         }
2277
2278         BUG_ON(i == I915_FENCE_REG_NONE);
2279
2280         /* We only have a reference on obj from the active list. put_fence_reg
2281          * might drop that one, causing a use-after-free in it. So hold a
2282          * private reference to obj like the other callers of put_fence_reg
2283          * (set_tiling ioctl) do. */
2284         drm_gem_object_reference(obj);
2285         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2286         drm_gem_object_unreference(obj);
2287         if (ret != 0)
2288                 return ret;
2289
2290         return i;
2291 }
2292
2293 /**
2294  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2295  * @obj: object to map through a fence reg
2296  *
2297  * When mapping objects through the GTT, userspace wants to be able to write
2298  * to them without having to worry about swizzling if the object is tiled.
2299  *
2300  * This function walks the fence regs looking for a free one for @obj,
2301  * stealing one if it can't find any.
2302  *
2303  * It then sets up the reg based on the object's properties: address, pitch
2304  * and tiling format.
2305  */
2306 int
2307 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2308                               bool interruptible)
2309 {
2310         struct drm_device *dev = obj->dev;
2311         struct drm_i915_private *dev_priv = dev->dev_private;
2312         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2313         struct drm_i915_fence_reg *reg = NULL;
2314         int ret;
2315
2316         /* Just update our place in the LRU if our fence is getting used. */
2317         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2318                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2319                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2320                 return 0;
2321         }
2322
2323         switch (obj_priv->tiling_mode) {
2324         case I915_TILING_NONE:
2325                 WARN(1, "allocating a fence for non-tiled object?\n");
2326                 break;
2327         case I915_TILING_X:
2328                 if (!obj_priv->stride)
2329                         return -EINVAL;
2330                 WARN((obj_priv->stride & (512 - 1)),
2331                      "object 0x%08x is X tiled but has non-512B pitch\n",
2332                      obj_priv->gtt_offset);
2333                 break;
2334         case I915_TILING_Y:
2335                 if (!obj_priv->stride)
2336                         return -EINVAL;
2337                 WARN((obj_priv->stride & (128 - 1)),
2338                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2339                      obj_priv->gtt_offset);
2340                 break;
2341         }
2342
2343         ret = i915_find_fence_reg(dev, interruptible);
2344         if (ret < 0)
2345                 return ret;
2346
2347         obj_priv->fence_reg = ret;
2348         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2349         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2350
2351         reg->obj = obj;
2352
2353         switch (INTEL_INFO(dev)->gen) {
2354         case 6:
2355                 sandybridge_write_fence_reg(reg);
2356                 break;
2357         case 5:
2358         case 4:
2359                 i965_write_fence_reg(reg);
2360                 break;
2361         case 3:
2362                 i915_write_fence_reg(reg);
2363                 break;
2364         case 2:
2365                 i830_write_fence_reg(reg);
2366                 break;
2367         }
2368
2369         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2370                         obj_priv->tiling_mode);
2371
2372         return 0;
2373 }
2374
2375 /**
2376  * i915_gem_clear_fence_reg - clear out fence register info
2377  * @obj: object to clear
2378  *
2379  * Zeroes out the fence register itself and clears out the associated
2380  * data structures in dev_priv and obj_priv.
2381  */
2382 static void
2383 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2384 {
2385         struct drm_device *dev = obj->dev;
2386         drm_i915_private_t *dev_priv = dev->dev_private;
2387         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2388         struct drm_i915_fence_reg *reg =
2389                 &dev_priv->fence_regs[obj_priv->fence_reg];
2390         uint32_t fence_reg;
2391
2392         switch (INTEL_INFO(dev)->gen) {
2393         case 6:
2394                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2395                              (obj_priv->fence_reg * 8), 0);
2396                 break;
2397         case 5:
2398         case 4:
2399                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2400                 break;
2401         case 3:
2402                 if (obj_priv->fence_reg > 8)
2403                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2404                 else
2405         case 2:
2406                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2407
2408                 I915_WRITE(fence_reg, 0);
2409                 break;
2410         }
2411
2412         reg->obj = NULL;
2413         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2414         list_del_init(&reg->lru_list);
2415 }
2416
2417 /**
2418  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2419  * to the buffer to finish, and then resets the fence register.
2420  * @obj: tiled object holding a fence register.
2421  * @bool: whether the wait upon the fence is interruptible
2422  *
2423  * Zeroes out the fence register itself and clears out the associated
2424  * data structures in dev_priv and obj_priv.
2425  */
2426 int
2427 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2428                               bool interruptible)
2429 {
2430         struct drm_device *dev = obj->dev;
2431         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2432
2433         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2434                 return 0;
2435
2436         /* If we've changed tiling, GTT-mappings of the object
2437          * need to re-fault to ensure that the correct fence register
2438          * setup is in place.
2439          */
2440         i915_gem_release_mmap(obj);
2441
2442         /* On the i915, GPU access to tiled buffers is via a fence,
2443          * therefore we must wait for any outstanding access to complete
2444          * before clearing the fence.
2445          */
2446         if (!IS_I965G(dev)) {
2447                 int ret;
2448
2449                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2450                 if (ret)
2451                         return ret;
2452
2453                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2454                 if (ret)
2455                         return ret;
2456         }
2457
2458         i915_gem_object_flush_gtt_write_domain(obj);
2459         i915_gem_clear_fence_reg(obj);
2460
2461         return 0;
2462 }
2463
2464 /**
2465  * Finds free space in the GTT aperture and binds the object there.
2466  */
2467 static int
2468 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2469 {
2470         struct drm_device *dev = obj->dev;
2471         drm_i915_private_t *dev_priv = dev->dev_private;
2472         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2473         struct drm_mm_node *free_space;
2474         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2475         int ret;
2476
2477         if (obj_priv->madv != I915_MADV_WILLNEED) {
2478                 DRM_ERROR("Attempting to bind a purgeable object\n");
2479                 return -EINVAL;
2480         }
2481
2482         if (alignment == 0)
2483                 alignment = i915_gem_get_gtt_alignment(obj);
2484         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2485                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2486                 return -EINVAL;
2487         }
2488
2489         /* If the object is bigger than the entire aperture, reject it early
2490          * before evicting everything in a vain attempt to find space.
2491          */
2492         if (obj->size > dev->gtt_total) {
2493                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2494                 return -E2BIG;
2495         }
2496
2497  search_free:
2498         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2499                                         obj->size, alignment, 0);
2500         if (free_space != NULL) {
2501                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2502                                                        alignment);
2503                 if (obj_priv->gtt_space != NULL)
2504                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2505         }
2506         if (obj_priv->gtt_space == NULL) {
2507                 /* If the gtt is empty and we're still having trouble
2508                  * fitting our object in, we're out of memory.
2509                  */
2510 #if WATCH_LRU
2511                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2512 #endif
2513                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2514                 if (ret)
2515                         return ret;
2516
2517                 goto search_free;
2518         }
2519
2520 #if WATCH_BUF
2521         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2522                  obj->size, obj_priv->gtt_offset);
2523 #endif
2524         ret = i915_gem_object_get_pages(obj, gfpmask);
2525         if (ret) {
2526                 drm_mm_put_block(obj_priv->gtt_space);
2527                 obj_priv->gtt_space = NULL;
2528
2529                 if (ret == -ENOMEM) {
2530                         /* first try to clear up some space from the GTT */
2531                         ret = i915_gem_evict_something(dev, obj->size,
2532                                                        alignment);
2533                         if (ret) {
2534                                 /* now try to shrink everyone else */
2535                                 if (gfpmask) {
2536                                         gfpmask = 0;
2537                                         goto search_free;
2538                                 }
2539
2540                                 return ret;
2541                         }
2542
2543                         goto search_free;
2544                 }
2545
2546                 return ret;
2547         }
2548
2549         /* Create an AGP memory structure pointing at our pages, and bind it
2550          * into the GTT.
2551          */
2552         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2553                                                obj_priv->pages,
2554                                                obj->size >> PAGE_SHIFT,
2555                                                obj_priv->gtt_offset,
2556                                                obj_priv->agp_type);
2557         if (obj_priv->agp_mem == NULL) {
2558                 i915_gem_object_put_pages(obj);
2559                 drm_mm_put_block(obj_priv->gtt_space);
2560                 obj_priv->gtt_space = NULL;
2561
2562                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2563                 if (ret)
2564                         return ret;
2565
2566                 goto search_free;
2567         }
2568         atomic_inc(&dev->gtt_count);
2569         atomic_add(obj->size, &dev->gtt_memory);
2570
2571         /* keep track of bounds object by adding it to the inactive list */
2572         list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2573
2574         /* Assert that the object is not currently in any GPU domain. As it
2575          * wasn't in the GTT, there shouldn't be any way it could have been in
2576          * a GPU cache
2577          */
2578         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2579         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2580
2581         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2582
2583         return 0;
2584 }
2585
2586 void
2587 i915_gem_clflush_object(struct drm_gem_object *obj)
2588 {
2589         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2590
2591         /* If we don't have a page list set up, then we're not pinned
2592          * to GPU, and we can ignore the cache flush because it'll happen
2593          * again at bind time.
2594          */
2595         if (obj_priv->pages == NULL)
2596                 return;
2597
2598         trace_i915_gem_object_clflush(obj);
2599
2600         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2601 }
2602
2603 /** Flushes any GPU write domain for the object if it's dirty. */
2604 static int
2605 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2606                                        bool pipelined)
2607 {
2608         struct drm_device *dev = obj->dev;
2609         uint32_t old_write_domain;
2610
2611         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2612                 return 0;
2613
2614         /* Queue the GPU write cache flushing we need. */
2615         old_write_domain = obj->write_domain;
2616         i915_gem_flush(dev, 0, obj->write_domain);
2617         BUG_ON(obj->write_domain);
2618
2619         trace_i915_gem_object_change_domain(obj,
2620                                             obj->read_domains,
2621                                             old_write_domain);
2622
2623         if (pipelined)
2624                 return 0;
2625
2626         return i915_gem_object_wait_rendering(obj, true);
2627 }
2628
2629 /** Flushes the GTT write domain for the object if it's dirty. */
2630 static void
2631 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2632 {
2633         uint32_t old_write_domain;
2634
2635         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2636                 return;
2637
2638         /* No actual flushing is required for the GTT write domain.   Writes
2639          * to it immediately go to main memory as far as we know, so there's
2640          * no chipset flush.  It also doesn't land in render cache.
2641          */
2642         old_write_domain = obj->write_domain;
2643         obj->write_domain = 0;
2644
2645         trace_i915_gem_object_change_domain(obj,
2646                                             obj->read_domains,
2647                                             old_write_domain);
2648 }
2649
2650 /** Flushes the CPU write domain for the object if it's dirty. */
2651 static void
2652 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2653 {
2654         struct drm_device *dev = obj->dev;
2655         uint32_t old_write_domain;
2656
2657         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2658                 return;
2659
2660         i915_gem_clflush_object(obj);
2661         drm_agp_chipset_flush(dev);
2662         old_write_domain = obj->write_domain;
2663         obj->write_domain = 0;
2664
2665         trace_i915_gem_object_change_domain(obj,
2666                                             obj->read_domains,
2667                                             old_write_domain);
2668 }
2669
2670 /**
2671  * Moves a single object to the GTT read, and possibly write domain.
2672  *
2673  * This function returns when the move is complete, including waiting on
2674  * flushes to occur.
2675  */
2676 int
2677 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2678 {
2679         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2680         uint32_t old_write_domain, old_read_domains;
2681         int ret;
2682
2683         /* Not valid to be called on unbound objects. */
2684         if (obj_priv->gtt_space == NULL)
2685                 return -EINVAL;
2686
2687         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2688         if (ret != 0)
2689                 return ret;
2690
2691         i915_gem_object_flush_cpu_write_domain(obj);
2692
2693         if (write) {
2694                 ret = i915_gem_object_wait_rendering(obj, true);
2695                 if (ret)
2696                         return ret;
2697         }
2698
2699         old_write_domain = obj->write_domain;
2700         old_read_domains = obj->read_domains;
2701
2702         /* It should now be out of any other write domains, and we can update
2703          * the domain values for our changes.
2704          */
2705         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2706         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2707         if (write) {
2708                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2709                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2710                 obj_priv->dirty = 1;
2711         }
2712
2713         trace_i915_gem_object_change_domain(obj,
2714                                             old_read_domains,
2715                                             old_write_domain);
2716
2717         return 0;
2718 }
2719
2720 /*
2721  * Prepare buffer for display plane. Use uninterruptible for possible flush
2722  * wait, as in modesetting process we're not supposed to be interrupted.
2723  */
2724 int
2725 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2726                                      bool pipelined)
2727 {
2728         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2729         uint32_t old_read_domains;
2730         int ret;
2731
2732         /* Not valid to be called on unbound objects. */
2733         if (obj_priv->gtt_space == NULL)
2734                 return -EINVAL;
2735
2736         ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
2737         if (ret)
2738                 return ret;
2739
2740         i915_gem_object_flush_cpu_write_domain(obj);
2741
2742         old_read_domains = obj->read_domains;
2743         obj->read_domains = I915_GEM_DOMAIN_GTT;
2744
2745         trace_i915_gem_object_change_domain(obj,
2746                                             old_read_domains,
2747                                             obj->write_domain);
2748
2749         return 0;
2750 }
2751
2752 /**
2753  * Moves a single object to the CPU read, and possibly write domain.
2754  *
2755  * This function returns when the move is complete, including waiting on
2756  * flushes to occur.
2757  */
2758 static int
2759 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2760 {
2761         uint32_t old_write_domain, old_read_domains;
2762         int ret;
2763
2764         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2765         if (ret != 0)
2766                 return ret;
2767
2768         i915_gem_object_flush_gtt_write_domain(obj);
2769
2770         /* If we have a partially-valid cache of the object in the CPU,
2771          * finish invalidating it and free the per-page flags.
2772          */
2773         i915_gem_object_set_to_full_cpu_read_domain(obj);
2774
2775         if (write) {
2776                 ret = i915_gem_object_wait_rendering(obj, true);
2777                 if (ret)
2778                         return ret;
2779         }
2780
2781         old_write_domain = obj->write_domain;
2782         old_read_domains = obj->read_domains;
2783
2784         /* Flush the CPU cache if it's still invalid. */
2785         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2786                 i915_gem_clflush_object(obj);
2787
2788                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2789         }
2790
2791         /* It should now be out of any other write domains, and we can update
2792          * the domain values for our changes.
2793          */
2794         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2795
2796         /* If we're writing through the CPU, then the GPU read domains will
2797          * need to be invalidated at next use.
2798          */
2799         if (write) {
2800                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2801                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2802         }
2803
2804         trace_i915_gem_object_change_domain(obj,
2805                                             old_read_domains,
2806                                             old_write_domain);
2807
2808         return 0;
2809 }
2810
2811 /*
2812  * Set the next domain for the specified object. This
2813  * may not actually perform the necessary flushing/invaliding though,
2814  * as that may want to be batched with other set_domain operations
2815  *
2816  * This is (we hope) the only really tricky part of gem. The goal
2817  * is fairly simple -- track which caches hold bits of the object
2818  * and make sure they remain coherent. A few concrete examples may
2819  * help to explain how it works. For shorthand, we use the notation
2820  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2821  * a pair of read and write domain masks.
2822  *
2823  * Case 1: the batch buffer
2824  *
2825  *      1. Allocated
2826  *      2. Written by CPU
2827  *      3. Mapped to GTT
2828  *      4. Read by GPU
2829  *      5. Unmapped from GTT
2830  *      6. Freed
2831  *
2832  *      Let's take these a step at a time
2833  *
2834  *      1. Allocated
2835  *              Pages allocated from the kernel may still have
2836  *              cache contents, so we set them to (CPU, CPU) always.
2837  *      2. Written by CPU (using pwrite)
2838  *              The pwrite function calls set_domain (CPU, CPU) and
2839  *              this function does nothing (as nothing changes)
2840  *      3. Mapped by GTT
2841  *              This function asserts that the object is not
2842  *              currently in any GPU-based read or write domains
2843  *      4. Read by GPU
2844  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2845  *              As write_domain is zero, this function adds in the
2846  *              current read domains (CPU+COMMAND, 0).
2847  *              flush_domains is set to CPU.
2848  *              invalidate_domains is set to COMMAND
2849  *              clflush is run to get data out of the CPU caches
2850  *              then i915_dev_set_domain calls i915_gem_flush to
2851  *              emit an MI_FLUSH and drm_agp_chipset_flush
2852  *      5. Unmapped from GTT
2853  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2854  *              flush_domains and invalidate_domains end up both zero
2855  *              so no flushing/invalidating happens
2856  *      6. Freed
2857  *              yay, done
2858  *
2859  * Case 2: The shared render buffer
2860  *
2861  *      1. Allocated
2862  *      2. Mapped to GTT
2863  *      3. Read/written by GPU
2864  *      4. set_domain to (CPU,CPU)
2865  *      5. Read/written by CPU
2866  *      6. Read/written by GPU
2867  *
2868  *      1. Allocated
2869  *              Same as last example, (CPU, CPU)
2870  *      2. Mapped to GTT
2871  *              Nothing changes (assertions find that it is not in the GPU)
2872  *      3. Read/written by GPU
2873  *              execbuffer calls set_domain (RENDER, RENDER)
2874  *              flush_domains gets CPU
2875  *              invalidate_domains gets GPU
2876  *              clflush (obj)
2877  *              MI_FLUSH and drm_agp_chipset_flush
2878  *      4. set_domain (CPU, CPU)
2879  *              flush_domains gets GPU
2880  *              invalidate_domains gets CPU
2881  *              wait_rendering (obj) to make sure all drawing is complete.
2882  *              This will include an MI_FLUSH to get the data from GPU
2883  *              to memory
2884  *              clflush (obj) to invalidate the CPU cache
2885  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2886  *      5. Read/written by CPU
2887  *              cache lines are loaded and dirtied
2888  *      6. Read written by GPU
2889  *              Same as last GPU access
2890  *
2891  * Case 3: The constant buffer
2892  *
2893  *      1. Allocated
2894  *      2. Written by CPU
2895  *      3. Read by GPU
2896  *      4. Updated (written) by CPU again
2897  *      5. Read by GPU
2898  *
2899  *      1. Allocated
2900  *              (CPU, CPU)
2901  *      2. Written by CPU
2902  *              (CPU, CPU)
2903  *      3. Read by GPU
2904  *              (CPU+RENDER, 0)
2905  *              flush_domains = CPU
2906  *              invalidate_domains = RENDER
2907  *              clflush (obj)
2908  *              MI_FLUSH
2909  *              drm_agp_chipset_flush
2910  *      4. Updated (written) by CPU again
2911  *              (CPU, CPU)
2912  *              flush_domains = 0 (no previous write domain)
2913  *              invalidate_domains = 0 (no new read domains)
2914  *      5. Read by GPU
2915  *              (CPU+RENDER, 0)
2916  *              flush_domains = CPU
2917  *              invalidate_domains = RENDER
2918  *              clflush (obj)
2919  *              MI_FLUSH
2920  *              drm_agp_chipset_flush
2921  */
2922 static void
2923 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2924 {
2925         struct drm_device               *dev = obj->dev;
2926         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2927         uint32_t                        invalidate_domains = 0;
2928         uint32_t                        flush_domains = 0;
2929         uint32_t                        old_read_domains;
2930
2931         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2932         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2933
2934         intel_mark_busy(dev, obj);
2935
2936 #if WATCH_BUF
2937         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2938                  __func__, obj,
2939                  obj->read_domains, obj->pending_read_domains,
2940                  obj->write_domain, obj->pending_write_domain);
2941 #endif
2942         /*
2943          * If the object isn't moving to a new write domain,
2944          * let the object stay in multiple read domains
2945          */
2946         if (obj->pending_write_domain == 0)
2947                 obj->pending_read_domains |= obj->read_domains;
2948         else
2949                 obj_priv->dirty = 1;
2950
2951         /*
2952          * Flush the current write domain if
2953          * the new read domains don't match. Invalidate
2954          * any read domains which differ from the old
2955          * write domain
2956          */
2957         if (obj->write_domain &&
2958             obj->write_domain != obj->pending_read_domains) {
2959                 flush_domains |= obj->write_domain;
2960                 invalidate_domains |=
2961                         obj->pending_read_domains & ~obj->write_domain;
2962         }
2963         /*
2964          * Invalidate any read caches which may have
2965          * stale data. That is, any new read domains.
2966          */
2967         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2968         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2969 #if WATCH_BUF
2970                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2971                          __func__, flush_domains, invalidate_domains);
2972 #endif
2973                 i915_gem_clflush_object(obj);
2974         }
2975
2976         old_read_domains = obj->read_domains;
2977
2978         /* The actual obj->write_domain will be updated with
2979          * pending_write_domain after we emit the accumulated flush for all
2980          * of our domain changes in execbuffers (which clears objects'
2981          * write_domains).  So if we have a current write domain that we
2982          * aren't changing, set pending_write_domain to that.
2983          */
2984         if (flush_domains == 0 && obj->pending_write_domain == 0)
2985                 obj->pending_write_domain = obj->write_domain;
2986         obj->read_domains = obj->pending_read_domains;
2987
2988         dev->invalidate_domains |= invalidate_domains;
2989         dev->flush_domains |= flush_domains;
2990 #if WATCH_BUF
2991         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2992                  __func__,
2993                  obj->read_domains, obj->write_domain,
2994                  dev->invalidate_domains, dev->flush_domains);
2995 #endif
2996
2997         trace_i915_gem_object_change_domain(obj,
2998                                             old_read_domains,
2999                                             obj->write_domain);
3000 }
3001
3002 /**
3003  * Moves the object from a partially CPU read to a full one.
3004  *
3005  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3006  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3007  */
3008 static void
3009 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3010 {
3011         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3012
3013         if (!obj_priv->page_cpu_valid)
3014                 return;
3015
3016         /* If we're partially in the CPU read domain, finish moving it in.
3017          */
3018         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3019                 int i;
3020
3021                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3022                         if (obj_priv->page_cpu_valid[i])
3023                                 continue;
3024                         drm_clflush_pages(obj_priv->pages + i, 1);
3025                 }
3026         }
3027
3028         /* Free the page_cpu_valid mappings which are now stale, whether
3029          * or not we've got I915_GEM_DOMAIN_CPU.
3030          */
3031         kfree(obj_priv->page_cpu_valid);
3032         obj_priv->page_cpu_valid = NULL;
3033 }
3034
3035 /**
3036  * Set the CPU read domain on a range of the object.
3037  *
3038  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3039  * not entirely valid.  The page_cpu_valid member of the object flags which
3040  * pages have been flushed, and will be respected by
3041  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3042  * of the whole object.
3043  *
3044  * This function returns when the move is complete, including waiting on
3045  * flushes to occur.
3046  */
3047 static int
3048 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3049                                           uint64_t offset, uint64_t size)
3050 {
3051         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3052         uint32_t old_read_domains;
3053         int i, ret;
3054
3055         if (offset == 0 && size == obj->size)
3056                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3057
3058         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3059         if (ret != 0)
3060                 return ret;
3061         i915_gem_object_flush_gtt_write_domain(obj);
3062
3063         /* If we're already fully in the CPU read domain, we're done. */
3064         if (obj_priv->page_cpu_valid == NULL &&
3065             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3066                 return 0;
3067
3068         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3069          * newly adding I915_GEM_DOMAIN_CPU
3070          */
3071         if (obj_priv->page_cpu_valid == NULL) {
3072                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3073                                                    GFP_KERNEL);
3074                 if (obj_priv->page_cpu_valid == NULL)
3075                         return -ENOMEM;
3076         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3077                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3078
3079         /* Flush the cache on any pages that are still invalid from the CPU's
3080          * perspective.
3081          */
3082         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3083              i++) {
3084                 if (obj_priv->page_cpu_valid[i])
3085                         continue;
3086
3087                 drm_clflush_pages(obj_priv->pages + i, 1);
3088
3089                 obj_priv->page_cpu_valid[i] = 1;
3090         }
3091
3092         /* It should now be out of any other write domains, and we can update
3093          * the domain values for our changes.
3094          */
3095         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3096
3097         old_read_domains = obj->read_domains;
3098         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3099
3100         trace_i915_gem_object_change_domain(obj,
3101                                             old_read_domains,
3102                                             obj->write_domain);
3103
3104         return 0;
3105 }
3106
3107 /**
3108  * Pin an object to the GTT and evaluate the relocations landing in it.
3109  */
3110 static int
3111 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3112                                  struct drm_file *file_priv,
3113                                  struct drm_i915_gem_exec_object2 *entry,
3114                                  struct drm_i915_gem_relocation_entry *relocs)
3115 {
3116         struct drm_device *dev = obj->dev;
3117         drm_i915_private_t *dev_priv = dev->dev_private;
3118         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3119         int i, ret;
3120         void __iomem *reloc_page;
3121         bool need_fence;
3122
3123         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3124                      obj_priv->tiling_mode != I915_TILING_NONE;
3125
3126         /* Check fence reg constraints and rebind if necessary */
3127         if (need_fence &&
3128             !i915_gem_object_fence_offset_ok(obj,
3129                                              obj_priv->tiling_mode)) {
3130                 ret = i915_gem_object_unbind(obj);
3131                 if (ret)
3132                         return ret;
3133         }
3134
3135         /* Choose the GTT offset for our buffer and put it there. */
3136         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3137         if (ret)
3138                 return ret;
3139
3140         /*
3141          * Pre-965 chips need a fence register set up in order to
3142          * properly handle blits to/from tiled surfaces.
3143          */
3144         if (need_fence) {
3145                 ret = i915_gem_object_get_fence_reg(obj, false);
3146                 if (ret != 0) {
3147                         i915_gem_object_unpin(obj);
3148                         return ret;
3149                 }
3150         }
3151
3152         entry->offset = obj_priv->gtt_offset;
3153
3154         /* Apply the relocations, using the GTT aperture to avoid cache
3155          * flushing requirements.
3156          */
3157         for (i = 0; i < entry->relocation_count; i++) {
3158                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3159                 struct drm_gem_object *target_obj;
3160                 struct drm_i915_gem_object *target_obj_priv;
3161                 uint32_t reloc_val, reloc_offset;
3162                 uint32_t __iomem *reloc_entry;
3163
3164                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3165                                                    reloc->target_handle);
3166                 if (target_obj == NULL) {
3167                         i915_gem_object_unpin(obj);
3168                         return -ENOENT;
3169                 }
3170                 target_obj_priv = to_intel_bo(target_obj);
3171
3172 #if WATCH_RELOC
3173                 DRM_INFO("%s: obj %p offset %08x target %d "
3174                          "read %08x write %08x gtt %08x "
3175                          "presumed %08x delta %08x\n",
3176                          __func__,
3177                          obj,
3178                          (int) reloc->offset,
3179                          (int) reloc->target_handle,
3180                          (int) reloc->read_domains,
3181                          (int) reloc->write_domain,
3182                          (int) target_obj_priv->gtt_offset,
3183                          (int) reloc->presumed_offset,
3184                          reloc->delta);
3185 #endif
3186
3187                 /* The target buffer should have appeared before us in the
3188                  * exec_object list, so it should have a GTT space bound by now.
3189                  */
3190                 if (target_obj_priv->gtt_space == NULL) {
3191                         DRM_ERROR("No GTT space found for object %d\n",
3192                                   reloc->target_handle);
3193                         drm_gem_object_unreference(target_obj);
3194                         i915_gem_object_unpin(obj);
3195                         return -EINVAL;
3196                 }
3197
3198                 /* Validate that the target is in a valid r/w GPU domain */
3199                 if (reloc->write_domain & (reloc->write_domain - 1)) {
3200                         DRM_ERROR("reloc with multiple write domains: "
3201                                   "obj %p target %d offset %d "
3202                                   "read %08x write %08x",
3203                                   obj, reloc->target_handle,
3204                                   (int) reloc->offset,
3205                                   reloc->read_domains,
3206                                   reloc->write_domain);
3207                         return -EINVAL;
3208                 }
3209                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3210                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3211                         DRM_ERROR("reloc with read/write CPU domains: "
3212                                   "obj %p target %d offset %d "
3213                                   "read %08x write %08x",
3214                                   obj, reloc->target_handle,
3215                                   (int) reloc->offset,
3216                                   reloc->read_domains,
3217                                   reloc->write_domain);
3218                         drm_gem_object_unreference(target_obj);
3219                         i915_gem_object_unpin(obj);
3220                         return -EINVAL;
3221                 }
3222                 if (reloc->write_domain && target_obj->pending_write_domain &&
3223                     reloc->write_domain != target_obj->pending_write_domain) {
3224                         DRM_ERROR("Write domain conflict: "
3225                                   "obj %p target %d offset %d "
3226                                   "new %08x old %08x\n",
3227                                   obj, reloc->target_handle,
3228                                   (int) reloc->offset,
3229                                   reloc->write_domain,
3230                                   target_obj->pending_write_domain);
3231                         drm_gem_object_unreference(target_obj);
3232                         i915_gem_object_unpin(obj);
3233                         return -EINVAL;
3234                 }
3235
3236                 target_obj->pending_read_domains |= reloc->read_domains;
3237                 target_obj->pending_write_domain |= reloc->write_domain;
3238
3239                 /* If the relocation already has the right value in it, no
3240                  * more work needs to be done.
3241                  */
3242                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3243                         drm_gem_object_unreference(target_obj);
3244                         continue;
3245                 }
3246
3247                 /* Check that the relocation address is valid... */
3248                 if (reloc->offset > obj->size - 4) {
3249                         DRM_ERROR("Relocation beyond object bounds: "
3250                                   "obj %p target %d offset %d size %d.\n",
3251                                   obj, reloc->target_handle,
3252                                   (int) reloc->offset, (int) obj->size);
3253                         drm_gem_object_unreference(target_obj);
3254                         i915_gem_object_unpin(obj);
3255                         return -EINVAL;
3256                 }
3257                 if (reloc->offset & 3) {
3258                         DRM_ERROR("Relocation not 4-byte aligned: "
3259                                   "obj %p target %d offset %d.\n",
3260                                   obj, reloc->target_handle,
3261                                   (int) reloc->offset);
3262                         drm_gem_object_unreference(target_obj);
3263                         i915_gem_object_unpin(obj);
3264                         return -EINVAL;
3265                 }
3266
3267                 /* and points to somewhere within the target object. */
3268                 if (reloc->delta >= target_obj->size) {
3269                         DRM_ERROR("Relocation beyond target object bounds: "
3270                                   "obj %p target %d delta %d size %d.\n",
3271                                   obj, reloc->target_handle,
3272                                   (int) reloc->delta, (int) target_obj->size);
3273                         drm_gem_object_unreference(target_obj);
3274                         i915_gem_object_unpin(obj);
3275                         return -EINVAL;
3276                 }
3277
3278                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3279                 if (ret != 0) {
3280                         drm_gem_object_unreference(target_obj);
3281                         i915_gem_object_unpin(obj);
3282                         return -EINVAL;
3283                 }
3284
3285                 /* Map the page containing the relocation we're going to
3286                  * perform.
3287                  */
3288                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3289                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3290                                                       (reloc_offset &
3291                                                        ~(PAGE_SIZE - 1)),
3292                                                       KM_USER0);
3293                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3294                                                    (reloc_offset & (PAGE_SIZE - 1)));
3295                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3296
3297 #if WATCH_BUF
3298                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3299                           obj, (unsigned int) reloc->offset,
3300                           readl(reloc_entry), reloc_val);
3301 #endif
3302                 writel(reloc_val, reloc_entry);
3303                 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3304
3305                 /* The updated presumed offset for this entry will be
3306                  * copied back out to the user.
3307                  */
3308                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3309
3310                 drm_gem_object_unreference(target_obj);
3311         }
3312
3313 #if WATCH_BUF
3314         if (0)
3315                 i915_gem_dump_object(obj, 128, __func__, ~0);
3316 #endif
3317         return 0;
3318 }
3319
3320 /* Throttle our rendering by waiting until the ring has completed our requests
3321  * emitted over 20 msec ago.
3322  *
3323  * Note that if we were to use the current jiffies each time around the loop,
3324  * we wouldn't escape the function with any frames outstanding if the time to
3325  * render a frame was over 20ms.
3326  *
3327  * This should get us reasonable parallelism between CPU and GPU but also
3328  * relatively low latency when blocking on a particular request to finish.
3329  */
3330 static int
3331 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3332 {
3333         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3334         int ret = 0;
3335         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         while (!list_empty(&i915_file_priv->mm.request_list)) {
3339                 struct drm_i915_gem_request *request;
3340
3341                 request = list_first_entry(&i915_file_priv->mm.request_list,
3342                                            struct drm_i915_gem_request,
3343                                            client_list);
3344
3345                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3346                         break;
3347
3348                 ret = i915_wait_request(dev, request->seqno, request->ring);
3349                 if (ret != 0)
3350                         break;
3351         }
3352         mutex_unlock(&dev->struct_mutex);
3353
3354         return ret;
3355 }
3356
3357 static int
3358 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3359                               uint32_t buffer_count,
3360                               struct drm_i915_gem_relocation_entry **relocs)
3361 {
3362         uint32_t reloc_count = 0, reloc_index = 0, i;
3363         int ret;
3364
3365         *relocs = NULL;
3366         for (i = 0; i < buffer_count; i++) {
3367                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3368                         return -EINVAL;
3369                 reloc_count += exec_list[i].relocation_count;
3370         }
3371
3372         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3373         if (*relocs == NULL) {
3374                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3375                 return -ENOMEM;
3376         }
3377
3378         for (i = 0; i < buffer_count; i++) {
3379                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3380
3381                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3382
3383                 ret = copy_from_user(&(*relocs)[reloc_index],
3384                                      user_relocs,
3385                                      exec_list[i].relocation_count *
3386                                      sizeof(**relocs));
3387                 if (ret != 0) {
3388                         drm_free_large(*relocs);
3389                         *relocs = NULL;
3390                         return -EFAULT;
3391                 }
3392
3393                 reloc_index += exec_list[i].relocation_count;
3394         }
3395
3396         return 0;
3397 }
3398
3399 static int
3400 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3401                             uint32_t buffer_count,
3402                             struct drm_i915_gem_relocation_entry *relocs)
3403 {
3404         uint32_t reloc_count = 0, i;
3405         int ret = 0;
3406
3407         if (relocs == NULL)
3408             return 0;
3409
3410         for (i = 0; i < buffer_count; i++) {
3411                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3412                 int unwritten;
3413
3414                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3415
3416                 unwritten = copy_to_user(user_relocs,
3417                                          &relocs[reloc_count],
3418                                          exec_list[i].relocation_count *
3419                                          sizeof(*relocs));
3420
3421                 if (unwritten) {
3422                         ret = -EFAULT;
3423                         goto err;
3424                 }
3425
3426                 reloc_count += exec_list[i].relocation_count;
3427         }
3428
3429 err:
3430         drm_free_large(relocs);
3431
3432         return ret;
3433 }
3434
3435 static int
3436 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3437                            uint64_t exec_offset)
3438 {
3439         uint32_t exec_start, exec_len;
3440
3441         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3442         exec_len = (uint32_t) exec->batch_len;
3443
3444         if ((exec_start | exec_len) & 0x7)
3445                 return -EINVAL;
3446
3447         if (!exec_start)
3448                 return -EINVAL;
3449
3450         return 0;
3451 }
3452
3453 static int
3454 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3455                                struct drm_gem_object **object_list,
3456                                int count)
3457 {
3458         drm_i915_private_t *dev_priv = dev->dev_private;
3459         struct drm_i915_gem_object *obj_priv;
3460         DEFINE_WAIT(wait);
3461         int i, ret = 0;
3462
3463         for (;;) {
3464                 prepare_to_wait(&dev_priv->pending_flip_queue,
3465                                 &wait, TASK_INTERRUPTIBLE);
3466                 for (i = 0; i < count; i++) {
3467                         obj_priv = to_intel_bo(object_list[i]);
3468                         if (atomic_read(&obj_priv->pending_flip) > 0)
3469                                 break;
3470                 }
3471                 if (i == count)
3472                         break;
3473
3474                 if (!signal_pending(current)) {
3475                         mutex_unlock(&dev->struct_mutex);
3476                         schedule();
3477                         mutex_lock(&dev->struct_mutex);
3478                         continue;
3479                 }
3480                 ret = -ERESTARTSYS;
3481                 break;
3482         }
3483         finish_wait(&dev_priv->pending_flip_queue, &wait);
3484
3485         return ret;
3486 }
3487
3488 static int
3489 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3490                        struct drm_file *file_priv,
3491                        struct drm_i915_gem_execbuffer2 *args,
3492                        struct drm_i915_gem_exec_object2 *exec_list)
3493 {
3494         drm_i915_private_t *dev_priv = dev->dev_private;
3495         struct drm_gem_object **object_list = NULL;
3496         struct drm_gem_object *batch_obj;
3497         struct drm_i915_gem_object *obj_priv;
3498         struct drm_clip_rect *cliprects = NULL;
3499         struct drm_i915_gem_relocation_entry *relocs = NULL;
3500         struct drm_i915_gem_request *request = NULL;
3501         int ret = 0, ret2, i, pinned = 0;
3502         uint64_t exec_offset;
3503         uint32_t seqno, reloc_index;
3504         int pin_tries, flips;
3505
3506         struct intel_ring_buffer *ring = NULL;
3507
3508 #if WATCH_EXEC
3509         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3510                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3511 #endif
3512         if (args->flags & I915_EXEC_BSD) {
3513                 if (!HAS_BSD(dev)) {
3514                         DRM_ERROR("execbuf with wrong flag\n");
3515                         return -EINVAL;
3516                 }
3517                 ring = &dev_priv->bsd_ring;
3518         } else {
3519                 ring = &dev_priv->render_ring;
3520         }
3521
3522         if (args->buffer_count < 1) {
3523                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3524                 return -EINVAL;
3525         }
3526         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3527         if (object_list == NULL) {
3528                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3529                           args->buffer_count);
3530                 ret = -ENOMEM;
3531                 goto pre_mutex_err;
3532         }
3533
3534         if (args->num_cliprects != 0) {
3535                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3536                                     GFP_KERNEL);
3537                 if (cliprects == NULL) {
3538                         ret = -ENOMEM;
3539                         goto pre_mutex_err;
3540                 }
3541
3542                 ret = copy_from_user(cliprects,
3543                                      (struct drm_clip_rect __user *)
3544                                      (uintptr_t) args->cliprects_ptr,
3545                                      sizeof(*cliprects) * args->num_cliprects);
3546                 if (ret != 0) {
3547                         DRM_ERROR("copy %d cliprects failed: %d\n",
3548                                   args->num_cliprects, ret);
3549                         ret = -EFAULT;
3550                         goto pre_mutex_err;
3551                 }
3552         }
3553
3554         request = kzalloc(sizeof(*request), GFP_KERNEL);
3555         if (request == NULL) {
3556                 ret = -ENOMEM;
3557                 goto pre_mutex_err;
3558         }
3559
3560         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3561                                             &relocs);
3562         if (ret != 0)
3563                 goto pre_mutex_err;
3564
3565         mutex_lock(&dev->struct_mutex);
3566
3567         i915_verify_inactive(dev, __FILE__, __LINE__);
3568
3569         if (atomic_read(&dev_priv->mm.wedged)) {
3570                 mutex_unlock(&dev->struct_mutex);
3571                 ret = -EIO;
3572                 goto pre_mutex_err;
3573         }
3574
3575         if (dev_priv->mm.suspended) {
3576                 mutex_unlock(&dev->struct_mutex);
3577                 ret = -EBUSY;
3578                 goto pre_mutex_err;
3579         }
3580
3581         /* Look up object handles */
3582         flips = 0;
3583         for (i = 0; i < args->buffer_count; i++) {
3584                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3585                                                        exec_list[i].handle);
3586                 if (object_list[i] == NULL) {
3587                         DRM_ERROR("Invalid object handle %d at index %d\n",
3588                                    exec_list[i].handle, i);
3589                         /* prevent error path from reading uninitialized data */
3590                         args->buffer_count = i + 1;
3591                         ret = -ENOENT;
3592                         goto err;
3593                 }
3594
3595                 obj_priv = to_intel_bo(object_list[i]);
3596                 if (obj_priv->in_execbuffer) {
3597                         DRM_ERROR("Object %p appears more than once in object list\n",
3598                                    object_list[i]);
3599                         /* prevent error path from reading uninitialized data */
3600                         args->buffer_count = i + 1;
3601                         ret = -EINVAL;
3602                         goto err;
3603                 }
3604                 obj_priv->in_execbuffer = true;
3605                 flips += atomic_read(&obj_priv->pending_flip);
3606         }
3607
3608         if (flips > 0) {
3609                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3610                                                      args->buffer_count);
3611                 if (ret)
3612                         goto err;
3613         }
3614
3615         /* Pin and relocate */
3616         for (pin_tries = 0; ; pin_tries++) {
3617                 ret = 0;
3618                 reloc_index = 0;
3619
3620                 for (i = 0; i < args->buffer_count; i++) {
3621                         object_list[i]->pending_read_domains = 0;
3622                         object_list[i]->pending_write_domain = 0;
3623                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3624                                                                file_priv,
3625                                                                &exec_list[i],
3626                                                                &relocs[reloc_index]);
3627                         if (ret)
3628                                 break;
3629                         pinned = i + 1;
3630                         reloc_index += exec_list[i].relocation_count;
3631                 }
3632                 /* success */
3633                 if (ret == 0)
3634                         break;
3635
3636                 /* error other than GTT full, or we've already tried again */
3637                 if (ret != -ENOSPC || pin_tries >= 1) {
3638                         if (ret != -ERESTARTSYS) {
3639                                 unsigned long long total_size = 0;
3640                                 int num_fences = 0;
3641                                 for (i = 0; i < args->buffer_count; i++) {
3642                                         obj_priv = to_intel_bo(object_list[i]);
3643
3644                                         total_size += object_list[i]->size;
3645                                         num_fences +=
3646                                                 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3647                                                 obj_priv->tiling_mode != I915_TILING_NONE;
3648                                 }
3649                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3650                                           pinned+1, args->buffer_count,
3651                                           total_size, num_fences,
3652                                           ret);
3653                                 DRM_ERROR("%d objects [%d pinned], "
3654                                           "%d object bytes [%d pinned], "
3655                                           "%d/%d gtt bytes\n",
3656                                           atomic_read(&dev->object_count),
3657                                           atomic_read(&dev->pin_count),
3658                                           atomic_read(&dev->object_memory),
3659                                           atomic_read(&dev->pin_memory),
3660                                           atomic_read(&dev->gtt_memory),
3661                                           dev->gtt_total);
3662                         }
3663                         goto err;
3664                 }
3665
3666                 /* unpin all of our buffers */
3667                 for (i = 0; i < pinned; i++)
3668                         i915_gem_object_unpin(object_list[i]);
3669                 pinned = 0;
3670
3671                 /* evict everyone we can from the aperture */
3672                 ret = i915_gem_evict_everything(dev);
3673                 if (ret && ret != -ENOSPC)
3674                         goto err;
3675         }
3676
3677         /* Set the pending read domains for the batch buffer to COMMAND */
3678         batch_obj = object_list[args->buffer_count-1];
3679         if (batch_obj->pending_write_domain) {
3680                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3681                 ret = -EINVAL;
3682                 goto err;
3683         }
3684         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3685
3686         /* Sanity check the batch buffer, prior to moving objects */
3687         exec_offset = exec_list[args->buffer_count - 1].offset;
3688         ret = i915_gem_check_execbuffer (args, exec_offset);
3689         if (ret != 0) {
3690                 DRM_ERROR("execbuf with invalid offset/length\n");
3691                 goto err;
3692         }
3693
3694         i915_verify_inactive(dev, __FILE__, __LINE__);
3695
3696         /* Zero the global flush/invalidate flags. These
3697          * will be modified as new domains are computed
3698          * for each object
3699          */
3700         dev->invalidate_domains = 0;
3701         dev->flush_domains = 0;
3702
3703         for (i = 0; i < args->buffer_count; i++) {
3704                 struct drm_gem_object *obj = object_list[i];
3705
3706                 /* Compute new gpu domains and update invalidate/flush */
3707                 i915_gem_object_set_to_gpu_domain(obj);
3708         }
3709
3710         i915_verify_inactive(dev, __FILE__, __LINE__);
3711
3712         if (dev->invalidate_domains | dev->flush_domains) {
3713 #if WATCH_EXEC
3714                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3715                           __func__,
3716                          dev->invalidate_domains,
3717                          dev->flush_domains);
3718 #endif
3719                 i915_gem_flush(dev,
3720                                dev->invalidate_domains,
3721                                dev->flush_domains);
3722         }
3723
3724         if (dev_priv->render_ring.outstanding_lazy_request) {
3725                 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring);
3726                 dev_priv->render_ring.outstanding_lazy_request = false;
3727         }
3728         if (dev_priv->bsd_ring.outstanding_lazy_request) {
3729                 (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring);
3730                 dev_priv->bsd_ring.outstanding_lazy_request = false;
3731         }
3732
3733         for (i = 0; i < args->buffer_count; i++) {
3734                 struct drm_gem_object *obj = object_list[i];
3735                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3736                 uint32_t old_write_domain = obj->write_domain;
3737
3738                 obj->write_domain = obj->pending_write_domain;
3739                 if (obj->write_domain)
3740                         list_move_tail(&obj_priv->gpu_write_list,
3741                                        &dev_priv->mm.gpu_write_list);
3742                 else
3743                         list_del_init(&obj_priv->gpu_write_list);
3744
3745                 trace_i915_gem_object_change_domain(obj,
3746                                                     obj->read_domains,
3747                                                     old_write_domain);
3748         }
3749
3750         i915_verify_inactive(dev, __FILE__, __LINE__);
3751
3752 #if WATCH_COHERENCY
3753         for (i = 0; i < args->buffer_count; i++) {
3754                 i915_gem_object_check_coherency(object_list[i],
3755                                                 exec_list[i].handle);
3756         }
3757 #endif
3758
3759 #if WATCH_EXEC
3760         i915_gem_dump_object(batch_obj,
3761                               args->batch_len,
3762                               __func__,
3763                               ~0);
3764 #endif
3765
3766         /* Exec the batchbuffer */
3767         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3768                         cliprects, exec_offset);
3769         if (ret) {
3770                 DRM_ERROR("dispatch failed %d\n", ret);
3771                 goto err;
3772         }
3773
3774         /*
3775          * Ensure that the commands in the batch buffer are
3776          * finished before the interrupt fires
3777          */
3778         i915_retire_commands(dev, ring);
3779
3780         i915_verify_inactive(dev, __FILE__, __LINE__);
3781
3782         for (i = 0; i < args->buffer_count; i++) {
3783                 struct drm_gem_object *obj = object_list[i];
3784                 obj_priv = to_intel_bo(obj);
3785
3786                 i915_gem_object_move_to_active(obj, ring);
3787 #if WATCH_LRU
3788                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3789 #endif
3790         }
3791
3792         /*
3793          * Get a seqno representing the execution of the current buffer,
3794          * which we can wait on.  We would like to mitigate these interrupts,
3795          * likely by only creating seqnos occasionally (so that we have
3796          * *some* interrupts representing completion of buffers that we can
3797          * wait on when trying to clear up gtt space).
3798          */
3799         seqno = i915_add_request(dev, file_priv, request, ring);
3800         request = NULL;
3801
3802 #if WATCH_LRU
3803         i915_dump_lru(dev, __func__);
3804 #endif
3805
3806         i915_verify_inactive(dev, __FILE__, __LINE__);
3807
3808 err:
3809         for (i = 0; i < pinned; i++)
3810                 i915_gem_object_unpin(object_list[i]);
3811
3812         for (i = 0; i < args->buffer_count; i++) {
3813                 if (object_list[i]) {
3814                         obj_priv = to_intel_bo(object_list[i]);
3815                         obj_priv->in_execbuffer = false;
3816                 }
3817                 drm_gem_object_unreference(object_list[i]);
3818         }
3819
3820         mutex_unlock(&dev->struct_mutex);
3821
3822 pre_mutex_err:
3823         /* Copy the updated relocations out regardless of current error
3824          * state.  Failure to update the relocs would mean that the next
3825          * time userland calls execbuf, it would do so with presumed offset
3826          * state that didn't match the actual object state.
3827          */
3828         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3829                                            relocs);
3830         if (ret2 != 0) {
3831                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3832
3833                 if (ret == 0)
3834                         ret = ret2;
3835         }
3836
3837         drm_free_large(object_list);
3838         kfree(cliprects);
3839         kfree(request);
3840
3841         return ret;
3842 }
3843
3844 /*
3845  * Legacy execbuffer just creates an exec2 list from the original exec object
3846  * list array and passes it to the real function.
3847  */
3848 int
3849 i915_gem_execbuffer(struct drm_device *dev, void *data,
3850                     struct drm_file *file_priv)
3851 {
3852         struct drm_i915_gem_execbuffer *args = data;
3853         struct drm_i915_gem_execbuffer2 exec2;
3854         struct drm_i915_gem_exec_object *exec_list = NULL;
3855         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3856         int ret, i;
3857
3858 #if WATCH_EXEC
3859         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3860                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3861 #endif
3862
3863         if (args->buffer_count < 1) {
3864                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3865                 return -EINVAL;
3866         }
3867
3868         /* Copy in the exec list from userland */
3869         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3870         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3871         if (exec_list == NULL || exec2_list == NULL) {
3872                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3873                           args->buffer_count);
3874                 drm_free_large(exec_list);
3875                 drm_free_large(exec2_list);
3876                 return -ENOMEM;
3877         }
3878         ret = copy_from_user(exec_list,
3879                              (struct drm_i915_relocation_entry __user *)
3880                              (uintptr_t) args->buffers_ptr,
3881                              sizeof(*exec_list) * args->buffer_count);
3882         if (ret != 0) {
3883                 DRM_ERROR("copy %d exec entries failed %d\n",
3884                           args->buffer_count, ret);
3885                 drm_free_large(exec_list);
3886                 drm_free_large(exec2_list);
3887                 return -EFAULT;
3888         }
3889
3890         for (i = 0; i < args->buffer_count; i++) {
3891                 exec2_list[i].handle = exec_list[i].handle;
3892                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3893                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3894                 exec2_list[i].alignment = exec_list[i].alignment;
3895                 exec2_list[i].offset = exec_list[i].offset;
3896                 if (!IS_I965G(dev))
3897                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3898                 else
3899                         exec2_list[i].flags = 0;
3900         }
3901
3902         exec2.buffers_ptr = args->buffers_ptr;
3903         exec2.buffer_count = args->buffer_count;
3904         exec2.batch_start_offset = args->batch_start_offset;
3905         exec2.batch_len = args->batch_len;
3906         exec2.DR1 = args->DR1;
3907         exec2.DR4 = args->DR4;
3908         exec2.num_cliprects = args->num_cliprects;
3909         exec2.cliprects_ptr = args->cliprects_ptr;
3910         exec2.flags = I915_EXEC_RENDER;
3911
3912         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3913         if (!ret) {
3914                 /* Copy the new buffer offsets back to the user's exec list. */
3915                 for (i = 0; i < args->buffer_count; i++)
3916                         exec_list[i].offset = exec2_list[i].offset;
3917                 /* ... and back out to userspace */
3918                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3919                                    (uintptr_t) args->buffers_ptr,
3920                                    exec_list,
3921                                    sizeof(*exec_list) * args->buffer_count);
3922                 if (ret) {
3923                         ret = -EFAULT;
3924                         DRM_ERROR("failed to copy %d exec entries "
3925                                   "back to user (%d)\n",
3926                                   args->buffer_count, ret);
3927                 }
3928         }
3929
3930         drm_free_large(exec_list);
3931         drm_free_large(exec2_list);
3932         return ret;
3933 }
3934
3935 int
3936 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3937                      struct drm_file *file_priv)
3938 {
3939         struct drm_i915_gem_execbuffer2 *args = data;
3940         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3941         int ret;
3942
3943 #if WATCH_EXEC
3944         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3945                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3946 #endif
3947
3948         if (args->buffer_count < 1) {
3949                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3950                 return -EINVAL;
3951         }
3952
3953         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3954         if (exec2_list == NULL) {
3955                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3956                           args->buffer_count);
3957                 return -ENOMEM;
3958         }
3959         ret = copy_from_user(exec2_list,
3960                              (struct drm_i915_relocation_entry __user *)
3961                              (uintptr_t) args->buffers_ptr,
3962                              sizeof(*exec2_list) * args->buffer_count);
3963         if (ret != 0) {
3964                 DRM_ERROR("copy %d exec entries failed %d\n",
3965                           args->buffer_count, ret);
3966                 drm_free_large(exec2_list);
3967                 return -EFAULT;
3968         }
3969
3970         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
3971         if (!ret) {
3972                 /* Copy the new buffer offsets back to the user's exec list. */
3973                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3974                                    (uintptr_t) args->buffers_ptr,
3975                                    exec2_list,
3976                                    sizeof(*exec2_list) * args->buffer_count);
3977                 if (ret) {
3978                         ret = -EFAULT;
3979                         DRM_ERROR("failed to copy %d exec entries "
3980                                   "back to user (%d)\n",
3981                                   args->buffer_count, ret);
3982                 }
3983         }
3984
3985         drm_free_large(exec2_list);
3986         return ret;
3987 }
3988
3989 int
3990 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3991 {
3992         struct drm_device *dev = obj->dev;
3993         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3994         int ret;
3995
3996         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3997
3998         i915_verify_inactive(dev, __FILE__, __LINE__);
3999
4000         if (obj_priv->gtt_space != NULL) {
4001                 if (alignment == 0)
4002                         alignment = i915_gem_get_gtt_alignment(obj);
4003                 if (obj_priv->gtt_offset & (alignment - 1)) {
4004                         WARN(obj_priv->pin_count,
4005                              "bo is already pinned with incorrect alignment:"
4006                              " offset=%x, req.alignment=%x\n",
4007                              obj_priv->gtt_offset, alignment);
4008                         ret = i915_gem_object_unbind(obj);
4009                         if (ret)
4010                                 return ret;
4011                 }
4012         }
4013
4014         if (obj_priv->gtt_space == NULL) {
4015                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4016                 if (ret)
4017                         return ret;
4018         }
4019
4020         obj_priv->pin_count++;
4021
4022         /* If the object is not active and not pending a flush,
4023          * remove it from the inactive list
4024          */
4025         if (obj_priv->pin_count == 1) {
4026                 atomic_inc(&dev->pin_count);
4027                 atomic_add(obj->size, &dev->pin_memory);
4028                 if (!obj_priv->active &&
4029                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4030                         list_del_init(&obj_priv->list);
4031         }
4032         i915_verify_inactive(dev, __FILE__, __LINE__);
4033
4034         return 0;
4035 }
4036
4037 void
4038 i915_gem_object_unpin(struct drm_gem_object *obj)
4039 {
4040         struct drm_device *dev = obj->dev;
4041         drm_i915_private_t *dev_priv = dev->dev_private;
4042         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4043
4044         i915_verify_inactive(dev, __FILE__, __LINE__);
4045         obj_priv->pin_count--;
4046         BUG_ON(obj_priv->pin_count < 0);
4047         BUG_ON(obj_priv->gtt_space == NULL);
4048
4049         /* If the object is no longer pinned, and is
4050          * neither active nor being flushed, then stick it on
4051          * the inactive list
4052          */
4053         if (obj_priv->pin_count == 0) {
4054                 if (!obj_priv->active &&
4055                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4056                         list_move_tail(&obj_priv->list,
4057                                        &dev_priv->mm.inactive_list);
4058                 atomic_dec(&dev->pin_count);
4059                 atomic_sub(obj->size, &dev->pin_memory);
4060         }
4061         i915_verify_inactive(dev, __FILE__, __LINE__);
4062 }
4063
4064 int
4065 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4066                    struct drm_file *file_priv)
4067 {
4068         struct drm_i915_gem_pin *args = data;
4069         struct drm_gem_object *obj;
4070         struct drm_i915_gem_object *obj_priv;
4071         int ret;
4072
4073         mutex_lock(&dev->struct_mutex);
4074
4075         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4076         if (obj == NULL) {
4077                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4078                           args->handle);
4079                 mutex_unlock(&dev->struct_mutex);
4080                 return -ENOENT;
4081         }
4082         obj_priv = to_intel_bo(obj);
4083
4084         if (obj_priv->madv != I915_MADV_WILLNEED) {
4085                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4086                 drm_gem_object_unreference(obj);
4087                 mutex_unlock(&dev->struct_mutex);
4088                 return -EINVAL;
4089         }
4090
4091         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4092                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4093                           args->handle);
4094                 drm_gem_object_unreference(obj);
4095                 mutex_unlock(&dev->struct_mutex);
4096                 return -EINVAL;
4097         }
4098
4099         obj_priv->user_pin_count++;
4100         obj_priv->pin_filp = file_priv;
4101         if (obj_priv->user_pin_count == 1) {
4102                 ret = i915_gem_object_pin(obj, args->alignment);
4103                 if (ret != 0) {
4104                         drm_gem_object_unreference(obj);
4105                         mutex_unlock(&dev->struct_mutex);
4106                         return ret;
4107                 }
4108         }
4109
4110         /* XXX - flush the CPU caches for pinned objects
4111          * as the X server doesn't manage domains yet
4112          */
4113         i915_gem_object_flush_cpu_write_domain(obj);
4114         args->offset = obj_priv->gtt_offset;
4115         drm_gem_object_unreference(obj);
4116         mutex_unlock(&dev->struct_mutex);
4117
4118         return 0;
4119 }
4120
4121 int
4122 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4123                      struct drm_file *file_priv)
4124 {
4125         struct drm_i915_gem_pin *args = data;
4126         struct drm_gem_object *obj;
4127         struct drm_i915_gem_object *obj_priv;
4128
4129         mutex_lock(&dev->struct_mutex);
4130
4131         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4132         if (obj == NULL) {
4133                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4134                           args->handle);
4135                 mutex_unlock(&dev->struct_mutex);
4136                 return -ENOENT;
4137         }
4138
4139         obj_priv = to_intel_bo(obj);
4140         if (obj_priv->pin_filp != file_priv) {
4141                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4142                           args->handle);
4143                 drm_gem_object_unreference(obj);
4144                 mutex_unlock(&dev->struct_mutex);
4145                 return -EINVAL;
4146         }
4147         obj_priv->user_pin_count--;
4148         if (obj_priv->user_pin_count == 0) {
4149                 obj_priv->pin_filp = NULL;
4150                 i915_gem_object_unpin(obj);
4151         }
4152
4153         drm_gem_object_unreference(obj);
4154         mutex_unlock(&dev->struct_mutex);
4155         return 0;
4156 }
4157
4158 int
4159 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4160                     struct drm_file *file_priv)
4161 {
4162         struct drm_i915_gem_busy *args = data;
4163         struct drm_gem_object *obj;
4164         struct drm_i915_gem_object *obj_priv;
4165
4166         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4167         if (obj == NULL) {
4168                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4169                           args->handle);
4170                 return -ENOENT;
4171         }
4172
4173         mutex_lock(&dev->struct_mutex);
4174
4175         /* Count all active objects as busy, even if they are currently not used
4176          * by the gpu. Users of this interface expect objects to eventually
4177          * become non-busy without any further actions, therefore emit any
4178          * necessary flushes here.
4179          */
4180         obj_priv = to_intel_bo(obj);
4181         args->busy = obj_priv->active;
4182         if (args->busy) {
4183                 /* Unconditionally flush objects, even when the gpu still uses this
4184                  * object. Userspace calling this function indicates that it wants to
4185                  * use this buffer rather sooner than later, so issuing the required
4186                  * flush earlier is beneficial.
4187                  */
4188                 if (obj->write_domain) {
4189                         i915_gem_flush(dev, 0, obj->write_domain);
4190                         (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring);
4191                 }
4192
4193                 /* Update the active list for the hardware's current position.
4194                  * Otherwise this only updates on a delayed timer or when irqs
4195                  * are actually unmasked, and our working set ends up being
4196                  * larger than required.
4197                  */
4198                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4199
4200                 args->busy = obj_priv->active;
4201         }
4202
4203         drm_gem_object_unreference(obj);
4204         mutex_unlock(&dev->struct_mutex);
4205         return 0;
4206 }
4207
4208 int
4209 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4210                         struct drm_file *file_priv)
4211 {
4212     return i915_gem_ring_throttle(dev, file_priv);
4213 }
4214
4215 int
4216 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4217                        struct drm_file *file_priv)
4218 {
4219         struct drm_i915_gem_madvise *args = data;
4220         struct drm_gem_object *obj;
4221         struct drm_i915_gem_object *obj_priv;
4222
4223         switch (args->madv) {
4224         case I915_MADV_DONTNEED:
4225         case I915_MADV_WILLNEED:
4226             break;
4227         default:
4228             return -EINVAL;
4229         }
4230
4231         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4232         if (obj == NULL) {
4233                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4234                           args->handle);
4235                 return -ENOENT;
4236         }
4237
4238         mutex_lock(&dev->struct_mutex);
4239         obj_priv = to_intel_bo(obj);
4240
4241         if (obj_priv->pin_count) {
4242                 drm_gem_object_unreference(obj);
4243                 mutex_unlock(&dev->struct_mutex);
4244
4245                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4246                 return -EINVAL;
4247         }
4248
4249         if (obj_priv->madv != __I915_MADV_PURGED)
4250                 obj_priv->madv = args->madv;
4251
4252         /* if the object is no longer bound, discard its backing storage */
4253         if (i915_gem_object_is_purgeable(obj_priv) &&
4254             obj_priv->gtt_space == NULL)
4255                 i915_gem_object_truncate(obj);
4256
4257         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4258
4259         drm_gem_object_unreference(obj);
4260         mutex_unlock(&dev->struct_mutex);
4261
4262         return 0;
4263 }
4264
4265 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4266                                               size_t size)
4267 {
4268         struct drm_i915_gem_object *obj;
4269
4270         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4271         if (obj == NULL)
4272                 return NULL;
4273
4274         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4275                 kfree(obj);
4276                 return NULL;
4277         }
4278
4279         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4280         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4281
4282         obj->agp_type = AGP_USER_MEMORY;
4283         obj->base.driver_private = NULL;
4284         obj->fence_reg = I915_FENCE_REG_NONE;
4285         INIT_LIST_HEAD(&obj->list);
4286         INIT_LIST_HEAD(&obj->gpu_write_list);
4287         obj->madv = I915_MADV_WILLNEED;
4288
4289         trace_i915_gem_object_create(&obj->base);
4290
4291         return &obj->base;
4292 }
4293
4294 int i915_gem_init_object(struct drm_gem_object *obj)
4295 {
4296         BUG();
4297
4298         return 0;
4299 }
4300
4301 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4302 {
4303         struct drm_device *dev = obj->dev;
4304         drm_i915_private_t *dev_priv = dev->dev_private;
4305         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4306         int ret;
4307
4308         ret = i915_gem_object_unbind(obj);
4309         if (ret == -ERESTARTSYS) {
4310                 list_move(&obj_priv->list,
4311                           &dev_priv->mm.deferred_free_list);
4312                 return;
4313         }
4314
4315         if (obj_priv->mmap_offset)
4316                 i915_gem_free_mmap_offset(obj);
4317
4318         drm_gem_object_release(obj);
4319
4320         kfree(obj_priv->page_cpu_valid);
4321         kfree(obj_priv->bit_17);
4322         kfree(obj_priv);
4323 }
4324
4325 void i915_gem_free_object(struct drm_gem_object *obj)
4326 {
4327         struct drm_device *dev = obj->dev;
4328         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4329
4330         trace_i915_gem_object_destroy(obj);
4331
4332         while (obj_priv->pin_count > 0)
4333                 i915_gem_object_unpin(obj);
4334
4335         if (obj_priv->phys_obj)
4336                 i915_gem_detach_phys_object(dev, obj);
4337
4338         i915_gem_free_object_tail(obj);
4339 }
4340
4341 int
4342 i915_gem_idle(struct drm_device *dev)
4343 {
4344         drm_i915_private_t *dev_priv = dev->dev_private;
4345         int ret;
4346
4347         mutex_lock(&dev->struct_mutex);
4348
4349         if (dev_priv->mm.suspended ||
4350                         (dev_priv->render_ring.gem_object == NULL) ||
4351                         (HAS_BSD(dev) &&
4352                          dev_priv->bsd_ring.gem_object == NULL)) {
4353                 mutex_unlock(&dev->struct_mutex);
4354                 return 0;
4355         }
4356
4357         ret = i915_gpu_idle(dev);
4358         if (ret) {
4359                 mutex_unlock(&dev->struct_mutex);
4360                 return ret;
4361         }
4362
4363         /* Under UMS, be paranoid and evict. */
4364         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4365                 ret = i915_gem_evict_inactive(dev);
4366                 if (ret) {
4367                         mutex_unlock(&dev->struct_mutex);
4368                         return ret;
4369                 }
4370         }
4371
4372         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4373          * We need to replace this with a semaphore, or something.
4374          * And not confound mm.suspended!
4375          */
4376         dev_priv->mm.suspended = 1;
4377         del_timer_sync(&dev_priv->hangcheck_timer);
4378
4379         i915_kernel_lost_context(dev);
4380         i915_gem_cleanup_ringbuffer(dev);
4381
4382         mutex_unlock(&dev->struct_mutex);
4383
4384         /* Cancel the retire work handler, which should be idle now. */
4385         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4386
4387         return 0;
4388 }
4389
4390 /*
4391  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4392  * over cache flushing.
4393  */
4394 static int
4395 i915_gem_init_pipe_control(struct drm_device *dev)
4396 {
4397         drm_i915_private_t *dev_priv = dev->dev_private;
4398         struct drm_gem_object *obj;
4399         struct drm_i915_gem_object *obj_priv;
4400         int ret;
4401
4402         obj = i915_gem_alloc_object(dev, 4096);
4403         if (obj == NULL) {
4404                 DRM_ERROR("Failed to allocate seqno page\n");
4405                 ret = -ENOMEM;
4406                 goto err;
4407         }
4408         obj_priv = to_intel_bo(obj);
4409         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4410
4411         ret = i915_gem_object_pin(obj, 4096);
4412         if (ret)
4413                 goto err_unref;
4414
4415         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4416         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4417         if (dev_priv->seqno_page == NULL)
4418                 goto err_unpin;
4419
4420         dev_priv->seqno_obj = obj;
4421         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4422
4423         return 0;
4424
4425 err_unpin:
4426         i915_gem_object_unpin(obj);
4427 err_unref:
4428         drm_gem_object_unreference(obj);
4429 err:
4430         return ret;
4431 }
4432
4433
4434 static void
4435 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4436 {
4437         drm_i915_private_t *dev_priv = dev->dev_private;
4438         struct drm_gem_object *obj;
4439         struct drm_i915_gem_object *obj_priv;
4440
4441         obj = dev_priv->seqno_obj;
4442         obj_priv = to_intel_bo(obj);
4443         kunmap(obj_priv->pages[0]);
4444         i915_gem_object_unpin(obj);
4445         drm_gem_object_unreference(obj);
4446         dev_priv->seqno_obj = NULL;
4447
4448         dev_priv->seqno_page = NULL;
4449 }
4450
4451 int
4452 i915_gem_init_ringbuffer(struct drm_device *dev)
4453 {
4454         drm_i915_private_t *dev_priv = dev->dev_private;
4455         int ret;
4456
4457         dev_priv->render_ring = render_ring;
4458
4459         if (!I915_NEED_GFX_HWS(dev)) {
4460                 dev_priv->render_ring.status_page.page_addr
4461                         = dev_priv->status_page_dmah->vaddr;
4462                 memset(dev_priv->render_ring.status_page.page_addr,
4463                                 0, PAGE_SIZE);
4464         }
4465
4466         if (HAS_PIPE_CONTROL(dev)) {
4467                 ret = i915_gem_init_pipe_control(dev);
4468                 if (ret)
4469                         return ret;
4470         }
4471
4472         ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4473         if (ret)
4474                 goto cleanup_pipe_control;
4475
4476         if (HAS_BSD(dev)) {
4477                 dev_priv->bsd_ring = bsd_ring;
4478                 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4479                 if (ret)
4480                         goto cleanup_render_ring;
4481         }
4482
4483         dev_priv->next_seqno = 1;
4484
4485         return 0;
4486
4487 cleanup_render_ring:
4488         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4489 cleanup_pipe_control:
4490         if (HAS_PIPE_CONTROL(dev))
4491                 i915_gem_cleanup_pipe_control(dev);
4492         return ret;
4493 }
4494
4495 void
4496 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4497 {
4498         drm_i915_private_t *dev_priv = dev->dev_private;
4499
4500         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4501         if (HAS_BSD(dev))
4502                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4503         if (HAS_PIPE_CONTROL(dev))
4504                 i915_gem_cleanup_pipe_control(dev);
4505 }
4506
4507 int
4508 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4509                        struct drm_file *file_priv)
4510 {
4511         drm_i915_private_t *dev_priv = dev->dev_private;
4512         int ret;
4513
4514         if (drm_core_check_feature(dev, DRIVER_MODESET))
4515                 return 0;
4516
4517         if (atomic_read(&dev_priv->mm.wedged)) {
4518                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4519                 atomic_set(&dev_priv->mm.wedged, 0);
4520         }
4521
4522         mutex_lock(&dev->struct_mutex);
4523         dev_priv->mm.suspended = 0;
4524
4525         ret = i915_gem_init_ringbuffer(dev);
4526         if (ret != 0) {
4527                 mutex_unlock(&dev->struct_mutex);
4528                 return ret;
4529         }
4530
4531         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4532         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4533         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4534         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4535         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4536         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4537         mutex_unlock(&dev->struct_mutex);
4538
4539         ret = drm_irq_install(dev);
4540         if (ret)
4541                 goto cleanup_ringbuffer;
4542
4543         return 0;
4544
4545 cleanup_ringbuffer:
4546         mutex_lock(&dev->struct_mutex);
4547         i915_gem_cleanup_ringbuffer(dev);
4548         dev_priv->mm.suspended = 1;
4549         mutex_unlock(&dev->struct_mutex);
4550
4551         return ret;
4552 }
4553
4554 int
4555 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4556                        struct drm_file *file_priv)
4557 {
4558         if (drm_core_check_feature(dev, DRIVER_MODESET))
4559                 return 0;
4560
4561         drm_irq_uninstall(dev);
4562         return i915_gem_idle(dev);
4563 }
4564
4565 void
4566 i915_gem_lastclose(struct drm_device *dev)
4567 {
4568         int ret;
4569
4570         if (drm_core_check_feature(dev, DRIVER_MODESET))
4571                 return;
4572
4573         ret = i915_gem_idle(dev);
4574         if (ret)
4575                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4576 }
4577
4578 void
4579 i915_gem_load(struct drm_device *dev)
4580 {
4581         int i;
4582         drm_i915_private_t *dev_priv = dev->dev_private;
4583
4584         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4585         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4586         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4587         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4588         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4589         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4590         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4591         if (HAS_BSD(dev)) {
4592                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4593                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4594         }
4595         for (i = 0; i < 16; i++)
4596                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4597         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4598                           i915_gem_retire_work_handler);
4599         spin_lock(&shrink_list_lock);
4600         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4601         spin_unlock(&shrink_list_lock);
4602
4603         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4604         if (IS_GEN3(dev)) {
4605                 u32 tmp = I915_READ(MI_ARB_STATE);
4606                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4607                         /* arb state is a masked write, so set bit + bit in mask */
4608                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4609                         I915_WRITE(MI_ARB_STATE, tmp);
4610                 }
4611         }
4612
4613         /* Old X drivers will take 0-2 for front, back, depth buffers */
4614         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4615                 dev_priv->fence_reg_start = 3;
4616
4617         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4618                 dev_priv->num_fence_regs = 16;
4619         else
4620                 dev_priv->num_fence_regs = 8;
4621
4622         /* Initialize fence registers to zero */
4623         if (IS_I965G(dev)) {
4624                 for (i = 0; i < 16; i++)
4625                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4626         } else {
4627                 for (i = 0; i < 8; i++)
4628                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4629                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4630                         for (i = 0; i < 8; i++)
4631                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4632         }
4633         i915_gem_detect_bit_6_swizzle(dev);
4634         init_waitqueue_head(&dev_priv->pending_flip_queue);
4635 }
4636
4637 /*
4638  * Create a physically contiguous memory object for this object
4639  * e.g. for cursor + overlay regs
4640  */
4641 static int i915_gem_init_phys_object(struct drm_device *dev,
4642                                      int id, int size, int align)
4643 {
4644         drm_i915_private_t *dev_priv = dev->dev_private;
4645         struct drm_i915_gem_phys_object *phys_obj;
4646         int ret;
4647
4648         if (dev_priv->mm.phys_objs[id - 1] || !size)
4649                 return 0;
4650
4651         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4652         if (!phys_obj)
4653                 return -ENOMEM;
4654
4655         phys_obj->id = id;
4656
4657         phys_obj->handle = drm_pci_alloc(dev, size, align);
4658         if (!phys_obj->handle) {
4659                 ret = -ENOMEM;
4660                 goto kfree_obj;
4661         }
4662 #ifdef CONFIG_X86
4663         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4664 #endif
4665
4666         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4667
4668         return 0;
4669 kfree_obj:
4670         kfree(phys_obj);
4671         return ret;
4672 }
4673
4674 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4675 {
4676         drm_i915_private_t *dev_priv = dev->dev_private;
4677         struct drm_i915_gem_phys_object *phys_obj;
4678
4679         if (!dev_priv->mm.phys_objs[id - 1])
4680                 return;
4681
4682         phys_obj = dev_priv->mm.phys_objs[id - 1];
4683         if (phys_obj->cur_obj) {
4684                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4685         }
4686
4687 #ifdef CONFIG_X86
4688         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4689 #endif
4690         drm_pci_free(dev, phys_obj->handle);
4691         kfree(phys_obj);
4692         dev_priv->mm.phys_objs[id - 1] = NULL;
4693 }
4694
4695 void i915_gem_free_all_phys_object(struct drm_device *dev)
4696 {
4697         int i;
4698
4699         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4700                 i915_gem_free_phys_object(dev, i);
4701 }
4702
4703 void i915_gem_detach_phys_object(struct drm_device *dev,
4704                                  struct drm_gem_object *obj)
4705 {
4706         struct drm_i915_gem_object *obj_priv;
4707         int i;
4708         int ret;
4709         int page_count;
4710
4711         obj_priv = to_intel_bo(obj);
4712         if (!obj_priv->phys_obj)
4713                 return;
4714
4715         ret = i915_gem_object_get_pages(obj, 0);
4716         if (ret)
4717                 goto out;
4718
4719         page_count = obj->size / PAGE_SIZE;
4720
4721         for (i = 0; i < page_count; i++) {
4722                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4723                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4724
4725                 memcpy(dst, src, PAGE_SIZE);
4726                 kunmap_atomic(dst, KM_USER0);
4727         }
4728         drm_clflush_pages(obj_priv->pages, page_count);
4729         drm_agp_chipset_flush(dev);
4730
4731         i915_gem_object_put_pages(obj);
4732 out:
4733         obj_priv->phys_obj->cur_obj = NULL;
4734         obj_priv->phys_obj = NULL;
4735 }
4736
4737 int
4738 i915_gem_attach_phys_object(struct drm_device *dev,
4739                             struct drm_gem_object *obj,
4740                             int id,
4741                             int align)
4742 {
4743         drm_i915_private_t *dev_priv = dev->dev_private;
4744         struct drm_i915_gem_object *obj_priv;
4745         int ret = 0;
4746         int page_count;
4747         int i;
4748
4749         if (id > I915_MAX_PHYS_OBJECT)
4750                 return -EINVAL;
4751
4752         obj_priv = to_intel_bo(obj);
4753
4754         if (obj_priv->phys_obj) {
4755                 if (obj_priv->phys_obj->id == id)
4756                         return 0;
4757                 i915_gem_detach_phys_object(dev, obj);
4758         }
4759
4760         /* create a new object */
4761         if (!dev_priv->mm.phys_objs[id - 1]) {
4762                 ret = i915_gem_init_phys_object(dev, id,
4763                                                 obj->size, align);
4764                 if (ret) {
4765                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4766                         goto out;
4767                 }
4768         }
4769
4770         /* bind to the object */
4771         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4772         obj_priv->phys_obj->cur_obj = obj;
4773
4774         ret = i915_gem_object_get_pages(obj, 0);
4775         if (ret) {
4776                 DRM_ERROR("failed to get page list\n");
4777                 goto out;
4778         }
4779
4780         page_count = obj->size / PAGE_SIZE;
4781
4782         for (i = 0; i < page_count; i++) {
4783                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4784                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4785
4786                 memcpy(dst, src, PAGE_SIZE);
4787                 kunmap_atomic(src, KM_USER0);
4788         }
4789
4790         i915_gem_object_put_pages(obj);
4791
4792         return 0;
4793 out:
4794         return ret;
4795 }
4796
4797 static int
4798 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4799                      struct drm_i915_gem_pwrite *args,
4800                      struct drm_file *file_priv)
4801 {
4802         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4803         void *obj_addr;
4804         int ret;
4805         char __user *user_data;
4806
4807         user_data = (char __user *) (uintptr_t) args->data_ptr;
4808         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4809
4810         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4811         ret = copy_from_user(obj_addr, user_data, args->size);
4812         if (ret)
4813                 return -EFAULT;
4814
4815         drm_agp_chipset_flush(dev);
4816         return 0;
4817 }
4818
4819 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4820 {
4821         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4822
4823         /* Clean up our request list when the client is going away, so that
4824          * later retire_requests won't dereference our soon-to-be-gone
4825          * file_priv.
4826          */
4827         mutex_lock(&dev->struct_mutex);
4828         while (!list_empty(&i915_file_priv->mm.request_list))
4829                 list_del_init(i915_file_priv->mm.request_list.next);
4830         mutex_unlock(&dev->struct_mutex);
4831 }
4832
4833 static int
4834 i915_gpu_is_active(struct drm_device *dev)
4835 {
4836         drm_i915_private_t *dev_priv = dev->dev_private;
4837         int lists_empty;
4838
4839         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4840                       list_empty(&dev_priv->render_ring.active_list);
4841         if (HAS_BSD(dev))
4842                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4843
4844         return !lists_empty;
4845 }
4846
4847 static int
4848 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4849 {
4850         drm_i915_private_t *dev_priv, *next_dev;
4851         struct drm_i915_gem_object *obj_priv, *next_obj;
4852         int cnt = 0;
4853         int would_deadlock = 1;
4854
4855         /* "fast-path" to count number of available objects */
4856         if (nr_to_scan == 0) {
4857                 spin_lock(&shrink_list_lock);
4858                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4859                         struct drm_device *dev = dev_priv->dev;
4860
4861                         if (mutex_trylock(&dev->struct_mutex)) {
4862                                 list_for_each_entry(obj_priv,
4863                                                     &dev_priv->mm.inactive_list,
4864                                                     list)
4865                                         cnt++;
4866                                 mutex_unlock(&dev->struct_mutex);
4867                         }
4868                 }
4869                 spin_unlock(&shrink_list_lock);
4870
4871                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4872         }
4873
4874         spin_lock(&shrink_list_lock);
4875
4876 rescan:
4877         /* first scan for clean buffers */
4878         list_for_each_entry_safe(dev_priv, next_dev,
4879                                  &shrink_list, mm.shrink_list) {
4880                 struct drm_device *dev = dev_priv->dev;
4881
4882                 if (! mutex_trylock(&dev->struct_mutex))
4883                         continue;
4884
4885                 spin_unlock(&shrink_list_lock);
4886                 i915_gem_retire_requests(dev);
4887
4888                 list_for_each_entry_safe(obj_priv, next_obj,
4889                                          &dev_priv->mm.inactive_list,
4890                                          list) {
4891                         if (i915_gem_object_is_purgeable(obj_priv)) {
4892                                 i915_gem_object_unbind(&obj_priv->base);
4893                                 if (--nr_to_scan <= 0)
4894                                         break;
4895                         }
4896                 }
4897
4898                 spin_lock(&shrink_list_lock);
4899                 mutex_unlock(&dev->struct_mutex);
4900
4901                 would_deadlock = 0;
4902
4903                 if (nr_to_scan <= 0)
4904                         break;
4905         }
4906
4907         /* second pass, evict/count anything still on the inactive list */
4908         list_for_each_entry_safe(dev_priv, next_dev,
4909                                  &shrink_list, mm.shrink_list) {
4910                 struct drm_device *dev = dev_priv->dev;
4911
4912                 if (! mutex_trylock(&dev->struct_mutex))
4913                         continue;
4914
4915                 spin_unlock(&shrink_list_lock);
4916
4917                 list_for_each_entry_safe(obj_priv, next_obj,
4918                                          &dev_priv->mm.inactive_list,
4919                                          list) {
4920                         if (nr_to_scan > 0) {
4921                                 i915_gem_object_unbind(&obj_priv->base);
4922                                 nr_to_scan--;
4923                         } else
4924                                 cnt++;
4925                 }
4926
4927                 spin_lock(&shrink_list_lock);
4928                 mutex_unlock(&dev->struct_mutex);
4929
4930                 would_deadlock = 0;
4931         }
4932
4933         if (nr_to_scan) {
4934                 int active = 0;
4935
4936                 /*
4937                  * We are desperate for pages, so as a last resort, wait
4938                  * for the GPU to finish and discard whatever we can.
4939                  * This has a dramatic impact to reduce the number of
4940                  * OOM-killer events whilst running the GPU aggressively.
4941                  */
4942                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4943                         struct drm_device *dev = dev_priv->dev;
4944
4945                         if (!mutex_trylock(&dev->struct_mutex))
4946                                 continue;
4947
4948                         spin_unlock(&shrink_list_lock);
4949
4950                         if (i915_gpu_is_active(dev)) {
4951                                 i915_gpu_idle(dev);
4952                                 active++;
4953                         }
4954
4955                         spin_lock(&shrink_list_lock);
4956                         mutex_unlock(&dev->struct_mutex);
4957                 }
4958
4959                 if (active)
4960                         goto rescan;
4961         }
4962
4963         spin_unlock(&shrink_list_lock);
4964
4965         if (would_deadlock)
4966                 return -1;
4967         else if (cnt > 0)
4968                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4969         else
4970                 return 0;
4971 }
4972
4973 static struct shrinker shrinker = {
4974         .shrink = i915_gem_shrink,
4975         .seeks = DEFAULT_SEEKS,
4976 };
4977
4978 __init void
4979 i915_gem_shrinker_init(void)
4980 {
4981     register_shrinker(&shrinker);
4982 }
4983
4984 __exit void
4985 i915_gem_shrinker_exit(void)
4986 {
4987     unregister_shrinker(&shrinker);
4988 }