1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
59 #define I915_NUM_PIPE 2
61 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 * 1.2: Add Power Management
67 * 1.3: Add vblank support
68 * 1.4: Fix cmdbuffer path, add heap destroy
69 * 1.5: Add vblank pipe configuration
70 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
71 * - Support vertical blank on secondary display pipe
73 #define DRIVER_MAJOR 1
74 #define DRIVER_MINOR 6
75 #define DRIVER_PATCHLEVEL 0
77 #define WATCH_COHERENCY 0
82 #define WATCH_INACTIVE 0
83 #define WATCH_PWRITE 0
85 #define I915_GEM_PHYS_CURSOR_0 1
86 #define I915_GEM_PHYS_CURSOR_1 2
87 #define I915_GEM_PHYS_OVERLAY_REGS 3
88 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90 struct drm_i915_gem_phys_object {
92 struct page **page_list;
93 drm_dma_handle_t *handle;
94 struct drm_gem_object *cur_obj;
98 struct mem_block *next;
99 struct mem_block *prev;
102 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
105 struct opregion_header;
106 struct opregion_acpi;
107 struct opregion_swsci;
108 struct opregion_asle;
110 struct intel_opregion {
111 struct opregion_header *header;
112 struct opregion_acpi *acpi;
113 struct opregion_swsci *swsci;
114 struct opregion_asle *asle;
117 #define OPREGION_SIZE (8*1024)
119 struct intel_overlay;
120 struct intel_overlay_error_state;
122 struct drm_i915_master_private {
123 drm_local_map_t *sarea;
124 struct _drm_i915_sarea *sarea_priv;
126 #define I915_FENCE_REG_NONE -1
128 struct drm_i915_fence_reg {
129 struct drm_gem_object *obj;
130 struct list_head lru_list;
133 struct sdvo_device_mapping {
141 struct drm_i915_error_state {
156 struct drm_i915_error_object {
160 } *ringbuffer, *batchbuffer[2];
161 struct drm_i915_error_buffer {
175 struct intel_overlay_error_state *overlay;
178 struct drm_i915_display_funcs {
179 void (*dpms)(struct drm_crtc *crtc, int mode);
180 bool (*fbc_enabled)(struct drm_device *dev);
181 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
182 void (*disable_fbc)(struct drm_device *dev);
183 int (*get_display_clock_speed)(struct drm_device *dev);
184 int (*get_fifo_size)(struct drm_device *dev, int plane);
185 void (*update_wm)(struct drm_device *dev, int planea_clock,
186 int planeb_clock, int sr_hdisplay, int sr_htotal,
188 /* clock updates for mode set */
190 /* render clock increase/decrease */
191 /* display clock increase/decrease */
192 /* pll clock increase/decrease */
193 /* clock gating init */
196 struct intel_device_info {
210 u8 is_broadwater : 1;
215 u8 has_pipe_cxsr : 1;
217 u8 cursor_needs_physical : 1;
219 u8 overlay_needs_physical : 1;
223 FBC_NO_OUTPUT, /* no outputs enabled to compress */
224 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
225 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
226 FBC_MODE_TOO_LARGE, /* mode too large for compression */
227 FBC_BAD_PLANE, /* fbc not supported on plane */
228 FBC_NOT_TILED, /* buffer not tiled */
229 FBC_MULTIPLE_PIPES, /* more than one pipe active */
233 PCH_IBX, /* Ibexpeak PCH */
234 PCH_CPT, /* Cougarpoint PCH */
237 #define QUIRK_PIPEA_FORCE (1<<0)
241 typedef struct drm_i915_private {
242 struct drm_device *dev;
244 const struct intel_device_info *info;
251 struct i2c_adapter adapter;
252 struct i2c_adapter *force_bitbanging;
256 struct pci_dev *bridge_dev;
257 struct intel_ring_buffer render_ring;
258 struct intel_ring_buffer bsd_ring;
261 drm_dma_handle_t *status_page_dmah;
263 dma_addr_t dma_status_page;
265 unsigned int seqno_gfx_addr;
266 drm_local_map_t hws_map;
267 struct drm_gem_object *seqno_obj;
268 struct drm_gem_object *pwrctx;
269 struct drm_gem_object *renderctx;
271 struct resource mch_res;
278 #define I915_DEBUG_READ (1<<0)
279 #define I915_DEBUG_WRITE (1<<1)
280 unsigned long debug_flags;
282 wait_queue_head_t irq_queue;
283 atomic_t irq_received;
284 /** Protects user_irq_refcount and irq_mask_reg */
285 spinlock_t user_irq_lock;
287 /** Cached value of IMR to avoid reads in updating the bitfield */
290 /** splitted irq regs for graphics and display engine on Ironlake,
291 irq_mask_reg is still used for display irq. */
293 u32 gt_irq_enable_reg;
294 u32 de_irq_enable_reg;
295 u32 pch_irq_mask_reg;
296 u32 pch_irq_enable_reg;
298 u32 hotplug_supported_mask;
299 struct work_struct hotplug_work;
301 int tex_lru_log_granularity;
302 int allow_batchbuffer;
303 struct mem_block *agp_heap;
304 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
308 /* For hangcheck timer */
309 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
310 struct timer_list hangcheck_timer;
313 uint32_t last_instdone;
314 uint32_t last_instdone1;
316 unsigned long cfb_size;
317 unsigned long cfb_pitch;
318 unsigned long cfb_offset;
325 struct intel_opregion opregion;
328 struct intel_overlay *overlay;
331 int backlight_level; /* restore backlight to this value */
332 bool panel_wants_dither;
333 struct drm_display_mode *panel_fixed_mode;
334 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
335 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
337 /* Feature bits from the VBIOS */
338 unsigned int int_tv_support:1;
339 unsigned int lvds_dither:1;
340 unsigned int lvds_vbt:1;
341 unsigned int int_crt_support:1;
342 unsigned int lvds_use_ssc:1;
343 unsigned int edp_support:1;
347 struct notifier_block lid_notifier;
350 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
351 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
352 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
354 unsigned int fsb_freq, mem_freq, is_ddr3;
356 spinlock_t error_lock;
357 struct drm_i915_error_state *first_error;
358 struct work_struct error_work;
359 struct workqueue_struct *wq;
361 /* Display functions */
362 struct drm_i915_display_funcs display;
364 /* PCH chipset type */
365 enum intel_pch pch_type;
367 unsigned long quirks;
392 u32 saveTRANS_HTOTAL_A;
393 u32 saveTRANS_HBLANK_A;
394 u32 saveTRANS_HSYNC_A;
395 u32 saveTRANS_VTOTAL_A;
396 u32 saveTRANS_VBLANK_A;
397 u32 saveTRANS_VSYNC_A;
405 u32 savePFIT_PGM_RATIOS;
406 u32 saveBLC_HIST_CTL;
408 u32 saveBLC_PWM_CTL2;
409 u32 saveBLC_CPU_PWM_CTL;
410 u32 saveBLC_CPU_PWM_CTL2;
423 u32 saveTRANS_HTOTAL_B;
424 u32 saveTRANS_HBLANK_B;
425 u32 saveTRANS_HSYNC_B;
426 u32 saveTRANS_VTOTAL_B;
427 u32 saveTRANS_VBLANK_B;
428 u32 saveTRANS_VSYNC_B;
442 u32 savePP_ON_DELAYS;
443 u32 savePP_OFF_DELAYS;
451 u32 savePFIT_CONTROL;
452 u32 save_palette_a[256];
453 u32 save_palette_b[256];
454 u32 saveDPFC_CB_BASE;
455 u32 saveFBC_CFB_BASE;
458 u32 saveFBC_CONTROL2;
468 u32 saveCACHE_MODE_0;
469 u32 saveMI_ARB_STATE;
480 uint64_t saveFENCE[16];
491 u32 savePIPEA_GMCH_DATA_M;
492 u32 savePIPEB_GMCH_DATA_M;
493 u32 savePIPEA_GMCH_DATA_N;
494 u32 savePIPEB_GMCH_DATA_N;
495 u32 savePIPEA_DP_LINK_M;
496 u32 savePIPEB_DP_LINK_M;
497 u32 savePIPEA_DP_LINK_N;
498 u32 savePIPEB_DP_LINK_N;
509 u32 savePCH_DREF_CONTROL;
510 u32 saveDISP_ARB_CTL;
511 u32 savePIPEA_DATA_M1;
512 u32 savePIPEA_DATA_N1;
513 u32 savePIPEA_LINK_M1;
514 u32 savePIPEA_LINK_N1;
515 u32 savePIPEB_DATA_M1;
516 u32 savePIPEB_DATA_N1;
517 u32 savePIPEB_LINK_M1;
518 u32 savePIPEB_LINK_N1;
519 u32 saveMCHBAR_RENDER_STANDBY;
522 /** Bridge to intel-gtt-ko */
523 struct intel_gtt *gtt;
524 /** Memory allocator for GTT stolen memory */
526 /** Memory allocator for GTT */
527 struct drm_mm gtt_space;
529 struct io_mapping *gtt_mapping;
533 * Membership on list of all loaded devices, used to evict
534 * inactive buffers under memory pressure.
536 * Modifications should only be done whilst holding the
537 * shrink_list_lock spinlock.
539 struct list_head shrink_list;
542 * List of objects which are not in the ringbuffer but which
543 * still have a write_domain which needs to be flushed before
546 * last_rendering_seqno is 0 while an object is in this list.
548 * A reference is held on the buffer while on this list.
550 struct list_head flushing_list;
553 * List of objects currently pending a GPU write flush.
555 * All elements on this list will belong to either the
556 * active_list or flushing_list, last_rendering_seqno can
557 * be used to differentiate between the two elements.
559 struct list_head gpu_write_list;
562 * LRU list of objects which are not in the ringbuffer and
563 * are ready to unbind, but are still in the GTT.
565 * last_rendering_seqno is 0 while an object is in this list.
567 * A reference is not held on the buffer while on this list,
568 * as merely being GTT-bound shouldn't prevent its being
569 * freed, and we'll pull it off the list in the free path.
571 struct list_head inactive_list;
573 /** LRU list of objects with fence regs on them. */
574 struct list_head fence_list;
577 * List of objects currently pending being freed.
579 * These objects are no longer in use, but due to a signal
580 * we were prevented from freeing them at the appointed time.
582 struct list_head deferred_free_list;
585 * We leave the user IRQ off as much as possible,
586 * but this means that requests will finish and never
587 * be retired once the system goes idle. Set a timer to
588 * fire periodically while the ring is running. When it
589 * fires, go retire requests.
591 struct delayed_work retire_work;
594 * Waiting sequence number, if any
596 uint32_t waiting_gem_seqno;
599 * Last seq seen at irq time
601 uint32_t irq_gem_seqno;
604 * Flag if the X Server, and thus DRM, is not currently in
605 * control of the device.
607 * This is set between LeaveVT and EnterVT. It needs to be
608 * replaced with a semaphore. It also needs to be
609 * transitioned away from for kernel modesetting.
614 * Flag if the hardware appears to be wedged.
616 * This is set when attempts to idle the device timeout.
617 * It prevents command submission from occuring and makes
618 * every pending request fail
622 /** Bit 6 swizzling required for X tiling */
623 uint32_t bit_6_swizzle_x;
624 /** Bit 6 swizzling required for Y tiling */
625 uint32_t bit_6_swizzle_y;
627 /* storage for physical objects */
628 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
630 struct sdvo_device_mapping sdvo_mappings[2];
631 /* indicate whether the LVDS_BORDER should be enabled or not */
632 unsigned int lvds_border_bits;
633 /* Panel fitter placement and size for Ironlake+ */
634 u32 pch_pf_pos, pch_pf_size;
636 struct drm_crtc *plane_to_crtc_mapping[2];
637 struct drm_crtc *pipe_to_crtc_mapping[2];
638 wait_queue_head_t pending_flip_queue;
639 bool flip_pending_is_done;
641 /* Reclocking support */
642 bool render_reclock_avail;
643 bool lvds_downclock_avail;
644 /* indicates the reduced downclock for LVDS*/
646 struct work_struct idle_work;
647 struct timer_list idle_timer;
651 struct child_device_config *child_dev;
652 struct drm_connector *int_lvds_connector;
654 bool mchbar_need_disable;
663 unsigned long last_time1;
665 struct timespec last_time2;
666 unsigned long gfx_power;
670 spinlock_t *mchdev_lock;
672 enum no_fbc_reason no_fbc_reason;
674 struct drm_mm_node *compressed_fb;
675 struct drm_mm_node *compressed_llb;
677 /* list of fbdev register on this device */
678 struct intel_fbdev *fbdev;
679 } drm_i915_private_t;
681 /** driver private structure attached to each drm_gem_object */
682 struct drm_i915_gem_object {
683 struct drm_gem_object base;
685 /** Current space allocated to this object in the GTT, if any. */
686 struct drm_mm_node *gtt_space;
688 /** This object's place on the active/flushing/inactive lists */
689 struct list_head list;
690 /** This object's place on GPU write list */
691 struct list_head gpu_write_list;
692 /** This object's place on eviction list */
693 struct list_head evict_list;
696 * This is set if the object is on the active or flushing lists
697 * (has pending rendering), and is not set if it's on inactive (ready
700 unsigned int active : 1;
703 * This is set if the object has been written to since last bound
706 unsigned int dirty : 1;
709 * Fence register bits (if any) for this object. Will be set
710 * as needed when mapped into the GTT.
711 * Protected by dev->struct_mutex.
713 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
715 signed int fence_reg : 5;
718 * Used for checking the object doesn't appear more than once
719 * in an execbuffer object list.
721 unsigned int in_execbuffer : 1;
724 * Advice: are the backing pages purgeable?
726 unsigned int madv : 2;
729 * Refcount for the pages array. With the current locking scheme, there
730 * are at most two concurrent users: Binding a bo to the gtt and
731 * pwrite/pread using physical addresses. So two bits for a maximum
732 * of two users are enough.
734 unsigned int pages_refcount : 2;
735 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
738 * Current tiling mode for the object.
740 unsigned int tiling_mode : 2;
742 /** How many users have pinned this object in GTT space. The following
743 * users can each hold at most one reference: pwrite/pread, pin_ioctl
744 * (via user_pin_count), execbuffer (objects are not allowed multiple
745 * times for the same batchbuffer), and the framebuffer code. When
746 * switching/pageflipping, the framebuffer code has at most two buffers
749 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
750 * bits with absolutely no headroom. So use 4 bits. */
751 unsigned int pin_count : 4;
752 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
754 /** AGP memory structure for our GTT binding. */
755 DRM_AGP_MEM *agp_mem;
760 * Current offset of the object in GTT space.
762 * This is the same as gtt_space->start
766 /* Which ring is refering to is this object */
767 struct intel_ring_buffer *ring;
770 * Fake offset for use by mmap(2)
772 uint64_t mmap_offset;
774 /** Breadcrumb of last rendering to the buffer. */
775 uint32_t last_rendering_seqno;
777 /** Current tiling stride for the object, if it's tiled. */
780 /** Record of address bit 17 of each page at last unbind. */
781 unsigned long *bit_17;
783 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
787 * If present, while GEM_DOMAIN_CPU is in the read domain this array
788 * flags which individual pages are valid.
790 uint8_t *page_cpu_valid;
792 /** User space pin count and filp owning the pin */
793 uint32_t user_pin_count;
794 struct drm_file *pin_filp;
796 /** for phy allocated objects */
797 struct drm_i915_gem_phys_object *phys_obj;
800 * Number of crtcs where this object is currently the fb, but
801 * will be page flipped away on the next vblank. When it
802 * reaches 0, dev_priv->pending_flip_queue will be woken up.
804 atomic_t pending_flip;
807 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
810 * Request queue structure.
812 * The request queue allows us to note sequence numbers that have been emitted
813 * and may be associated with active buffers to be retired.
815 * By keeping this list, we can avoid having to do questionable
816 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
817 * an emission time with seqnos for tracking how far ahead of the GPU we are.
819 struct drm_i915_gem_request {
820 /** On Which ring this request was generated */
821 struct intel_ring_buffer *ring;
823 /** GEM sequence number associated with this request. */
826 /** Time at which this request was emitted, in jiffies. */
827 unsigned long emitted_jiffies;
829 /** global list entry for this request */
830 struct list_head list;
832 /** file_priv list entry for this request */
833 struct list_head client_list;
836 struct drm_i915_file_private {
838 struct list_head request_list;
842 enum intel_chip_family {
849 extern struct drm_ioctl_desc i915_ioctls[];
850 extern int i915_max_ioctl;
851 extern unsigned int i915_fbpercrtc;
852 extern unsigned int i915_powersave;
853 extern unsigned int i915_lvds_downclock;
855 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
856 extern int i915_resume(struct drm_device *dev);
857 extern void i915_save_display(struct drm_device *dev);
858 extern void i915_restore_display(struct drm_device *dev);
859 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
860 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
863 extern void i915_kernel_lost_context(struct drm_device * dev);
864 extern int i915_driver_load(struct drm_device *, unsigned long flags);
865 extern int i915_driver_unload(struct drm_device *);
866 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
867 extern void i915_driver_lastclose(struct drm_device * dev);
868 extern void i915_driver_preclose(struct drm_device *dev,
869 struct drm_file *file_priv);
870 extern void i915_driver_postclose(struct drm_device *dev,
871 struct drm_file *file_priv);
872 extern int i915_driver_device_is_agp(struct drm_device * dev);
873 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
875 extern int i915_emit_box(struct drm_device *dev,
876 struct drm_clip_rect *boxes,
877 int i, int DR1, int DR4);
878 extern int i965_reset(struct drm_device *dev, u8 flags);
879 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
880 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
881 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
882 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
886 void i915_hangcheck_elapsed(unsigned long data);
887 extern int i915_irq_emit(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 extern int i915_irq_wait(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
892 extern void i915_enable_interrupt (struct drm_device *dev);
894 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
895 extern void i915_driver_irq_preinstall(struct drm_device * dev);
896 extern int i915_driver_irq_postinstall(struct drm_device *dev);
897 extern void i915_driver_irq_uninstall(struct drm_device * dev);
898 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
899 struct drm_file *file_priv);
900 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
901 struct drm_file *file_priv);
902 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
903 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
904 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
905 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
906 extern int i915_vblank_swap(struct drm_device *dev, void *data,
907 struct drm_file *file_priv);
908 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
909 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
910 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
912 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
916 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
919 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
921 void intel_enable_asle (struct drm_device *dev);
923 #ifdef CONFIG_DEBUG_FS
924 extern void i915_destroy_error_state(struct drm_device *dev);
926 #define i915_destroy_error_state(x)
931 extern int i915_mem_alloc(struct drm_device *dev, void *data,
932 struct drm_file *file_priv);
933 extern int i915_mem_free(struct drm_device *dev, void *data,
934 struct drm_file *file_priv);
935 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
936 struct drm_file *file_priv);
937 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
938 struct drm_file *file_priv);
939 extern void i915_mem_takedown(struct mem_block **heap);
940 extern void i915_mem_release(struct drm_device * dev,
941 struct drm_file *file_priv, struct mem_block *heap);
943 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
944 struct drm_file *file_priv);
945 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv);
947 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
948 struct drm_file *file_priv);
949 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
950 struct drm_file *file_priv);
951 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
952 struct drm_file *file_priv);
953 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
954 struct drm_file *file_priv);
955 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
956 struct drm_file *file_priv);
957 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
958 struct drm_file *file_priv);
959 int i915_gem_execbuffer(struct drm_device *dev, void *data,
960 struct drm_file *file_priv);
961 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
962 struct drm_file *file_priv);
963 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
964 struct drm_file *file_priv);
965 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
966 struct drm_file *file_priv);
967 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
968 struct drm_file *file_priv);
969 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
970 struct drm_file *file_priv);
971 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
972 struct drm_file *file_priv);
973 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
974 struct drm_file *file_priv);
975 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
976 struct drm_file *file_priv);
977 int i915_gem_set_tiling(struct drm_device *dev, void *data,
978 struct drm_file *file_priv);
979 int i915_gem_get_tiling(struct drm_device *dev, void *data,
980 struct drm_file *file_priv);
981 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
982 struct drm_file *file_priv);
983 void i915_gem_load(struct drm_device *dev);
984 int i915_gem_init_object(struct drm_gem_object *obj);
985 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
987 void i915_gem_free_object(struct drm_gem_object *obj);
988 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
989 void i915_gem_object_unpin(struct drm_gem_object *obj);
990 int i915_gem_object_unbind(struct drm_gem_object *obj);
991 void i915_gem_release_mmap(struct drm_gem_object *obj);
992 void i915_gem_lastclose(struct drm_device *dev);
993 uint32_t i915_get_gem_seqno(struct drm_device *dev,
994 struct intel_ring_buffer *ring);
995 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
996 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
998 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
1000 void i915_gem_retire_requests(struct drm_device *dev);
1001 void i915_gem_clflush_object(struct drm_gem_object *obj);
1002 int i915_gem_object_set_domain(struct drm_gem_object *obj,
1003 uint32_t read_domains,
1004 uint32_t write_domain);
1005 int i915_gem_init_ringbuffer(struct drm_device *dev);
1006 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1007 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1009 int i915_gpu_idle(struct drm_device *dev);
1010 int i915_gem_idle(struct drm_device *dev);
1011 uint32_t i915_add_request(struct drm_device *dev,
1012 struct drm_file *file_priv,
1013 struct drm_i915_gem_request *request,
1014 struct intel_ring_buffer *ring);
1015 int i915_do_wait_request(struct drm_device *dev,
1018 struct intel_ring_buffer *ring);
1019 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1020 void i915_gem_process_flushing_list(struct drm_device *dev,
1021 uint32_t flush_domains,
1022 struct intel_ring_buffer *ring);
1023 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
1025 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
1027 int i915_gem_attach_phys_object(struct drm_device *dev,
1028 struct drm_gem_object *obj,
1031 void i915_gem_detach_phys_object(struct drm_device *dev,
1032 struct drm_gem_object *obj);
1033 void i915_gem_free_all_phys_object(struct drm_device *dev);
1034 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
1035 void i915_gem_object_put_pages(struct drm_gem_object *obj);
1036 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
1038 void i915_gem_shrinker_init(void);
1039 void i915_gem_shrinker_exit(void);
1041 /* i915_gem_evict.c */
1042 int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment);
1043 int i915_gem_evict_everything(struct drm_device *dev);
1044 int i915_gem_evict_inactive(struct drm_device *dev);
1046 /* i915_gem_tiling.c */
1047 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1048 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
1049 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
1050 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
1052 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
1055 /* i915_gem_debug.c */
1056 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1057 const char *where, uint32_t mark);
1059 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
1061 #define i915_verify_inactive(dev, file, line)
1063 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1064 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1065 const char *where, uint32_t mark);
1066 void i915_dump_lru(struct drm_device *dev, const char *where);
1068 /* i915_debugfs.c */
1069 int i915_debugfs_init(struct drm_minor *minor);
1070 void i915_debugfs_cleanup(struct drm_minor *minor);
1072 /* i915_suspend.c */
1073 extern int i915_save_state(struct drm_device *dev);
1074 extern int i915_restore_state(struct drm_device *dev);
1076 /* i915_suspend.c */
1077 extern int i915_save_state(struct drm_device *dev);
1078 extern int i915_restore_state(struct drm_device *dev);
1081 extern int intel_setup_gmbus(struct drm_device *dev);
1082 extern void intel_teardown_gmbus(struct drm_device *dev);
1083 extern void intel_i2c_reset(struct drm_device *dev);
1085 /* intel_opregion.c */
1086 extern int intel_opregion_setup(struct drm_device *dev);
1088 extern void intel_opregion_init(struct drm_device *dev);
1089 extern void intel_opregion_fini(struct drm_device *dev);
1090 extern void intel_opregion_asle_intr(struct drm_device *dev);
1091 extern void intel_opregion_gse_intr(struct drm_device *dev);
1092 extern void intel_opregion_enable_asle(struct drm_device *dev);
1094 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1095 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1096 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1097 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1098 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1102 extern void intel_modeset_init(struct drm_device *dev);
1103 extern void intel_modeset_cleanup(struct drm_device *dev);
1104 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1105 extern void i8xx_disable_fbc(struct drm_device *dev);
1106 extern void g4x_disable_fbc(struct drm_device *dev);
1107 extern void ironlake_disable_fbc(struct drm_device *dev);
1108 extern void intel_disable_fbc(struct drm_device *dev);
1109 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1110 extern bool intel_fbc_enabled(struct drm_device *dev);
1111 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1112 extern void intel_detect_pch (struct drm_device *dev);
1113 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1116 #ifdef CONFIG_DEBUG_FS
1117 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1118 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1122 * Lock test for when it's just for synchronization of ring access.
1124 * In that case, we don't need to do it when GEM is initialized as nobody else
1125 * has access to the ring.
1127 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1128 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1130 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1133 static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
1137 val = readl(dev_priv->regs + reg);
1138 if (dev_priv->debug_flags & I915_DEBUG_READ)
1139 printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
1143 static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
1146 writel(val, dev_priv->regs + reg);
1147 if (dev_priv->debug_flags & I915_DEBUG_WRITE)
1148 printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
1151 #define I915_READ(reg) i915_read(dev_priv, (reg))
1152 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1153 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1154 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1155 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1156 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1157 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1158 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1159 #define POSTING_READ(reg) (void)I915_READ(reg)
1160 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1162 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1164 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1167 #define I915_VERBOSE 0
1169 #define BEGIN_LP_RING(n) do { \
1170 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1172 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1173 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1177 #define OUT_RING(x) do { \
1178 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1180 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1181 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1184 #define ADVANCE_LP_RING() do { \
1185 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1187 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1188 dev_priv__->render_ring.tail); \
1189 intel_ring_advance(dev, &dev_priv__->render_ring); \
1193 * Reads a dword out of the status page, which is written to from the command
1194 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1195 * MI_STORE_DATA_IMM.
1197 * The following dwords have a reserved meaning:
1198 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1199 * 0x04: ring 0 head pointer
1200 * 0x05: ring 1 head pointer (915-class)
1201 * 0x06: ring 2 head pointer (915-class)
1202 * 0x10-0x1b: Context status DWords (GM45)
1203 * 0x1f: Last written status offset. (GM45)
1205 * The area from dword 0x20 to 0x3ff is available for driver usage.
1207 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1208 (dev_priv->render_ring.status_page.page_addr))[reg])
1209 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1210 #define I915_GEM_HWS_INDEX 0x20
1211 #define I915_BREADCRUMB_INDEX 0x21
1213 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1215 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1216 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1217 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1218 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1219 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1220 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1221 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1222 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1223 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1224 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1225 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1226 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1227 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1228 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1229 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1230 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1231 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1232 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1233 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1234 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1235 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1236 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1237 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1239 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1240 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1241 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1242 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1243 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1245 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1246 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1248 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1249 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1251 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1252 * rows, which changed the alignment requirements and fence programming.
1254 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1256 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1257 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1258 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1259 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1260 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1261 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1263 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1264 /* dsparb controlled by hw only */
1265 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1267 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1268 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1269 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1270 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1272 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1274 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1276 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1277 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1279 #define PRIMARY_RINGBUFFER_SIZE (128*1024)