drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset __read_mostly = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42 MODULE_PARM_DESC(modeset,
  43                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  44                 "1=on, -1=force vga console preference [default])");
  45
  46 unsigned int i915_fbpercrtc __always_unused = 0;
  47 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  48
  49 int i915_panel_ignore_lid __read_mostly = 0;
  50 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  51 MODULE_PARM_DESC(panel_ignore_lid,
  52                 "Override lid status (0=autodetect [default], 1=lid open, "
  53                 "-1=lid closed)");
  54
  55 unsigned int i915_powersave __read_mostly = 1;
  56 module_param_named(powersave, i915_powersave, int, 0600);
  57 MODULE_PARM_DESC(powersave,
  58                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  59
  60 unsigned int i915_semaphores __read_mostly = 0;
  61 module_param_named(semaphores, i915_semaphores, int, 0600);
  62 MODULE_PARM_DESC(semaphores,
  63                 "Use semaphores for inter-ring sync (default: false)");
  64
  65 unsigned int i915_enable_rc6 __read_mostly = 0;
  66 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  67 MODULE_PARM_DESC(i915_enable_rc6,
  68                 "Enable power-saving render C-state 6 (default: true)");
  69
  70 unsigned int i915_enable_fbc __read_mostly = -1;
  71 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  72 MODULE_PARM_DESC(i915_enable_fbc,
  73                 "Enable frame buffer compression for power savings "
  74                 "(default: -1 (use per-chip default))");
  75
  76 unsigned int i915_lvds_downclock __read_mostly = 0;
  77 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  78 MODULE_PARM_DESC(lvds_downclock,
  79                 "Use panel (LVDS/eDP) downclocking for power savings "
  80                 "(default: false)");
  81
  82 unsigned int i915_panel_use_ssc __read_mostly = -1;
  83 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  84 MODULE_PARM_DESC(lvds_use_ssc,
  85                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  86                 "(default: auto from VBT)");
  87
  88 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  89 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  90 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  91                 "Override selection of SDVO panel mode in the VBT "
  92                 "(default: auto)");
  93
  94 static bool i915_try_reset __read_mostly = true;
  95 module_param_named(reset, i915_try_reset, bool, 0600);
  96 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  97
  98 bool i915_enable_hangcheck __read_mostly = true;
  99 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 100 MODULE_PARM_DESC(enable_hangcheck,
 101                 "Periodically check GPU activity for detecting hangs. "
 102                 "WARNING: Disabling this can cause system wide hangs. "
 103                 "(default: true)");
 104
 105 static struct drm_driver driver;
 106 extern int intel_agp_enabled;
 107
 108 #define INTEL_VGA_DEVICE(id, info) {            \
 109         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
 110         .class_mask = 0xff0000,                 \
 111         .vendor = 0x8086,                       \
 112         .device = id,                           \
 113         .subvendor = PCI_ANY_ID,                \
 114         .subdevice = PCI_ANY_ID,                \
 115         .driver_data = (unsigned long) info }
 116
 117 static const struct intel_device_info intel_i830_info = {
 118         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120 };
 121
 122 static const struct intel_device_info intel_845g_info = {
 123         .gen = 2,
 124         .has_overlay = 1, .overlay_needs_physical = 1,
 125 };
 126
 127 static const struct intel_device_info intel_i85x_info = {
 128         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 129         .cursor_needs_physical = 1,
 130         .has_overlay = 1, .overlay_needs_physical = 1,
 131 };
 132
 133 static const struct intel_device_info intel_i865g_info = {
 134         .gen = 2,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136 };
 137
 138 static const struct intel_device_info intel_i915g_info = {
 139         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142 static const struct intel_device_info intel_i915gm_info = {
 143         .gen = 3, .is_mobile = 1,
 144         .cursor_needs_physical = 1,
 145         .has_overlay = 1, .overlay_needs_physical = 1,
 146         .supports_tv = 1,
 147 };
 148 static const struct intel_device_info intel_i945g_info = {
 149         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 150         .has_overlay = 1, .overlay_needs_physical = 1,
 151 };
 152 static const struct intel_device_info intel_i945gm_info = {
 153         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 154         .has_hotplug = 1, .cursor_needs_physical = 1,
 155         .has_overlay = 1, .overlay_needs_physical = 1,
 156         .supports_tv = 1,
 157 };
 158
 159 static const struct intel_device_info intel_i965g_info = {
 160         .gen = 4, .is_broadwater = 1,
 161         .has_hotplug = 1,
 162         .has_overlay = 1,
 163 };
 164
 165 static const struct intel_device_info intel_i965gm_info = {
 166         .gen = 4, .is_crestline = 1,
 167         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 168         .has_overlay = 1,
 169         .supports_tv = 1,
 170 };
 171
 172 static const struct intel_device_info intel_g33_info = {
 173         .gen = 3, .is_g33 = 1,
 174         .need_gfx_hws = 1, .has_hotplug = 1,
 175         .has_overlay = 1,
 176 };
 177
 178 static const struct intel_device_info intel_g45_info = {
 179         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 180         .has_pipe_cxsr = 1, .has_hotplug = 1,
 181         .has_bsd_ring = 1,
 182 };
 183
 184 static const struct intel_device_info intel_gm45_info = {
 185         .gen = 4, .is_g4x = 1,
 186         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 187         .has_pipe_cxsr = 1, .has_hotplug = 1,
 188         .supports_tv = 1,
 189         .has_bsd_ring = 1,
 190 };
 191
 192 static const struct intel_device_info intel_pineview_info = {
 193         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 194         .need_gfx_hws = 1, .has_hotplug = 1,
 195         .has_overlay = 1,
 196 };
 197
 198 static const struct intel_device_info intel_ironlake_d_info = {
 199         .gen = 5,
 200         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 201         .has_bsd_ring = 1,
 202 };
 203
 204 static const struct intel_device_info intel_ironlake_m_info = {
 205         .gen = 5, .is_mobile = 1,
 206         .need_gfx_hws = 1, .has_hotplug = 1,
 207         .has_fbc = 1,
 208         .has_bsd_ring = 1,
 209 };
 210
 211 static const struct intel_device_info intel_sandybridge_d_info = {
 212         .gen = 6,
 213         .need_gfx_hws = 1, .has_hotplug = 1,
 214         .has_bsd_ring = 1,
 215         .has_blt_ring = 1,
 216 };
 217
 218 static const struct intel_device_info intel_sandybridge_m_info = {
 219         .gen = 6, .is_mobile = 1,
 220         .need_gfx_hws = 1, .has_hotplug = 1,
 221         .has_fbc = 1,
 222         .has_bsd_ring = 1,
 223         .has_blt_ring = 1,
 224 };
 225
 226 static const struct intel_device_info intel_ivybridge_d_info = {
 227         .is_ivybridge = 1, .gen = 7,
 228         .need_gfx_hws = 1, .has_hotplug = 1,
 229         .has_bsd_ring = 1,
 230         .has_blt_ring = 1,
 231 };
 232
 233 static const struct intel_device_info intel_ivybridge_m_info = {
 234         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 235         .need_gfx_hws = 1, .has_hotplug = 1,
 236         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 237         .has_bsd_ring = 1,
 238         .has_blt_ring = 1,
 239 };
 240
 241 static const struct pci_device_id pciidlist[] = {               /* aka */
 242         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 243         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 244         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 245         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 246         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 247         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 248         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 249         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 250         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 251         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 252         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 253         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 254         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 255         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 256         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 257         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 258         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 259         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 260         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 261         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 262         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 263         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 264         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 265         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 266         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 267         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 268         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 269         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 270         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 271         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 272         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 273         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 274         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 275         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 276         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 277         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 278         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 279         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 280         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 281         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 282         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 283         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 284         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 285         {0, 0, 0}
 286 };
 287
 288 #if defined(CONFIG_DRM_I915_KMS)
 289 MODULE_DEVICE_TABLE(pci, pciidlist);
 290 #endif
 291
 292 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 293 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 294 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 295 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 296
 297 void intel_detect_pch(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         struct pci_dev *pch;
 301
 302         /*
 303          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 304          * make graphics device passthrough work easy for VMM, that only
 305          * need to expose ISA bridge to let driver know the real hardware
 306          * underneath. This is a requirement from virtualization team.
 307          */
 308         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 309         if (pch) {
 310                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 311                         int id;
 312                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 313
 314                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 315                                 dev_priv->pch_type = PCH_IBX;
 316                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 317                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 318                                 dev_priv->pch_type = PCH_CPT;
 319                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 320                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 321                                 /* PantherPoint is CPT compatible */
 322                                 dev_priv->pch_type = PCH_CPT;
 323                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 324                         }
 325                 }
 326                 pci_dev_put(pch);
 327         }
 328 }
 329
 330 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 331 {
 332         int count;
 333
 334         count = 0;
 335         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 336                 udelay(10);
 337
 338         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 339         POSTING_READ(FORCEWAKE);
 340
 341         count = 0;
 342         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 343                 udelay(10);
 344 }
 345
 346 /*
 347  * Generally this is called implicitly by the register read function. However,
 348  * if some sequence requires the GT to not power down then this function should
 349  * be called at the beginning of the sequence followed by a call to
 350  * gen6_gt_force_wake_put() at the end of the sequence.
 351  */
 352 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 353 {
 354         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 355
 356         /* Forcewake is atomic in case we get in here without the lock */
 357         if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
 358                 __gen6_gt_force_wake_get(dev_priv);
 359 }
 360
 361 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 362 {
 363         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 364         POSTING_READ(FORCEWAKE);
 365 }
 366
 367 /*
 368  * see gen6_gt_force_wake_get()
 369  */
 370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 371 {
 372         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 373
 374         if (atomic_dec_and_test(&dev_priv->forcewake_count))
 375                 __gen6_gt_force_wake_put(dev_priv);
 376 }
 377
 378 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 379 {
 380         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 381                 int loop = 500;
 382                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 383                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 384                         udelay(10);
 385                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 386                 }
 387                 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
 388                 dev_priv->gt_fifo_count = fifo;
 389         }
 390         dev_priv->gt_fifo_count--;
 391 }
 392
 393 static int i915_drm_freeze(struct drm_device *dev)
 394 {
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396
 397         drm_kms_helper_poll_disable(dev);
 398
 399         pci_save_state(dev->pdev);
 400
 401         /* If KMS is active, we do the leavevt stuff here */
 402         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 403                 int error = i915_gem_idle(dev);
 404                 if (error) {
 405                         dev_err(&dev->pdev->dev,
 406                                 "GEM idle failed, resume might fail\n");
 407                         return error;
 408                 }
 409                 drm_irq_uninstall(dev);
 410         }
 411
 412         i915_save_state(dev);
 413
 414         intel_opregion_fini(dev);
 415
 416         /* Modeset on resume, not lid events */
 417         dev_priv->modeset_on_lid = 0;
 418
 419         return 0;
 420 }
 421
 422 int i915_suspend(struct drm_device *dev, pm_message_t state)
 423 {
 424         int error;
 425
 426         if (!dev || !dev->dev_private) {
 427                 DRM_ERROR("dev: %p\n", dev);
 428                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 429                 return -ENODEV;
 430         }
 431
 432         if (state.event == PM_EVENT_PRETHAW)
 433                 return 0;
 434
 435
 436         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 437                 return 0;
 438
 439         error = i915_drm_freeze(dev);
 440         if (error)
 441                 return error;
 442
 443         if (state.event == PM_EVENT_SUSPEND) {
 444                 /* Shut down the device */
 445                 pci_disable_device(dev->pdev);
 446                 pci_set_power_state(dev->pdev, PCI_D3hot);
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int i915_drm_thaw(struct drm_device *dev)
 453 {
 454         struct drm_i915_private *dev_priv = dev->dev_private;
 455         int error = 0;
 456
 457         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 458                 mutex_lock(&dev->struct_mutex);
 459                 i915_gem_restore_gtt_mappings(dev);
 460                 mutex_unlock(&dev->struct_mutex);
 461         }
 462
 463         i915_restore_state(dev);
 464         intel_opregion_setup(dev);
 465
 466         /* KMS EnterVT equivalent */
 467         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 468                 mutex_lock(&dev->struct_mutex);
 469                 dev_priv->mm.suspended = 0;
 470
 471                 error = i915_gem_init_ringbuffer(dev);
 472                 mutex_unlock(&dev->struct_mutex);
 473
 474                 if (HAS_PCH_SPLIT(dev))
 475                         ironlake_init_pch_refclk(dev);
 476
 477                 drm_mode_config_reset(dev);
 478                 drm_irq_install(dev);
 479
 480                 /* Resume the modeset for every activated CRTC */
 481                 drm_helper_resume_force_mode(dev);
 482
 483                 if (IS_IRONLAKE_M(dev))
 484                         ironlake_enable_rc6(dev);
 485         }
 486
 487         intel_opregion_init(dev);
 488
 489         dev_priv->modeset_on_lid = 0;
 490
 491         return error;
 492 }
 493
 494 int i915_resume(struct drm_device *dev)
 495 {
 496         int ret;
 497
 498         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 499                 return 0;
 500
 501         if (pci_enable_device(dev->pdev))
 502                 return -EIO;
 503
 504         pci_set_master(dev->pdev);
 505
 506         ret = i915_drm_thaw(dev);
 507         if (ret)
 508                 return ret;
 509
 510         drm_kms_helper_poll_enable(dev);
 511         return 0;
 512 }
 513
 514 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 515 {
 516         struct drm_i915_private *dev_priv = dev->dev_private;
 517
 518         if (IS_I85X(dev))
 519                 return -ENODEV;
 520
 521         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 522         POSTING_READ(D_STATE);
 523
 524         if (IS_I830(dev) || IS_845G(dev)) {
 525                 I915_WRITE(DEBUG_RESET_I830,
 526                            DEBUG_RESET_DISPLAY |
 527                            DEBUG_RESET_RENDER |
 528                            DEBUG_RESET_FULL);
 529                 POSTING_READ(DEBUG_RESET_I830);
 530                 msleep(1);
 531
 532                 I915_WRITE(DEBUG_RESET_I830, 0);
 533                 POSTING_READ(DEBUG_RESET_I830);
 534         }
 535
 536         msleep(1);
 537
 538         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 539         POSTING_READ(D_STATE);
 540
 541         return 0;
 542 }
 543
 544 static int i965_reset_complete(struct drm_device *dev)
 545 {
 546         u8 gdrst;
 547         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 548         return gdrst & 0x1;
 549 }
 550
 551 static int i965_do_reset(struct drm_device *dev, u8 flags)
 552 {
 553         u8 gdrst;
 554
 555         /*
 556          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 557          * well as the reset bit (GR/bit 0).  Setting the GR bit
 558          * triggers the reset; when done, the hardware will clear it.
 559          */
 560         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 561         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 562
 563         return wait_for(i965_reset_complete(dev), 500);
 564 }
 565
 566 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 567 {
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 570         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 571         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 572 }
 573
 574 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 575 {
 576         struct drm_i915_private *dev_priv = dev->dev_private;
 577
 578         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 579         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 580 }
 581
 582 /**
 583  * i965_reset - reset chip after a hang
 584  * @dev: drm device to reset
 585  * @flags: reset domains
 586  *
 587  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 588  * reset or otherwise an error code.
 589  *
 590  * Procedure is fairly simple:
 591  *   - reset the chip using the reset reg
 592  *   - re-init context state
 593  *   - re-init hardware status page
 594  *   - re-init ring buffer
 595  *   - re-init interrupt state
 596  *   - re-init display
 597  */
 598 int i915_reset(struct drm_device *dev, u8 flags)
 599 {
 600         drm_i915_private_t *dev_priv = dev->dev_private;
 601         /*
 602          * We really should only reset the display subsystem if we actually
 603          * need to
 604          */
 605         bool need_display = true;
 606         int ret;
 607
 608         if (!i915_try_reset)
 609                 return 0;
 610
 611         if (!mutex_trylock(&dev->struct_mutex))
 612                 return -EBUSY;
 613
 614         i915_gem_reset(dev);
 615
 616         ret = -ENODEV;
 617         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 618                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 619         } else switch (INTEL_INFO(dev)->gen) {
 620         case 7:
 621         case 6:
 622                 ret = gen6_do_reset(dev, flags);
 623                 /* If reset with a user forcewake, try to restore */
 624                 if (atomic_read(&dev_priv->forcewake_count))
 625                         __gen6_gt_force_wake_get(dev_priv);
 626                 break;
 627         case 5:
 628                 ret = ironlake_do_reset(dev, flags);
 629                 break;
 630         case 4:
 631                 ret = i965_do_reset(dev, flags);
 632                 break;
 633         case 2:
 634                 ret = i8xx_do_reset(dev, flags);
 635                 break;
 636         }
 637         dev_priv->last_gpu_reset = get_seconds();
 638         if (ret) {
 639                 DRM_ERROR("Failed to reset chip.\n");
 640                 mutex_unlock(&dev->struct_mutex);
 641                 return ret;
 642         }
 643
 644         /* Ok, now get things going again... */
 645
 646         /*
 647          * Everything depends on having the GTT running, so we need to start
 648          * there.  Fortunately we don't need to do this unless we reset the
 649          * chip at a PCI level.
 650          *
 651          * Next we need to restore the context, but we don't use those
 652          * yet either...
 653          *
 654          * Ring buffer needs to be re-initialized in the KMS case, or if X
 655          * was running at the time of the reset (i.e. we weren't VT
 656          * switched away).
 657          */
 658         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 659                         !dev_priv->mm.suspended) {
 660                 dev_priv->mm.suspended = 0;
 661
 662                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 663                 if (HAS_BSD(dev))
 664                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 665                 if (HAS_BLT(dev))
 666                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 667
 668                 mutex_unlock(&dev->struct_mutex);
 669                 drm_irq_uninstall(dev);
 670                 drm_mode_config_reset(dev);
 671                 drm_irq_install(dev);
 672                 mutex_lock(&dev->struct_mutex);
 673         }
 674
 675         mutex_unlock(&dev->struct_mutex);
 676
 677         /*
 678          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 679          * need to retrain the display link and cannot just restore the register
 680          * values.
 681          */
 682         if (need_display) {
 683                 mutex_lock(&dev->mode_config.mutex);
 684                 drm_helper_resume_force_mode(dev);
 685                 mutex_unlock(&dev->mode_config.mutex);
 686         }
 687
 688         return 0;
 689 }
 690
 691
 692 static int __devinit
 693 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 694 {
 695         /* Only bind to function 0 of the device. Early generations
 696          * used function 1 as a placeholder for multi-head. This causes
 697          * us confusion instead, especially on the systems where both
 698          * functions have the same PCI-ID!
 699          */
 700         if (PCI_FUNC(pdev->devfn))
 701                 return -ENODEV;
 702
 703         return drm_get_pci_dev(pdev, ent, &driver);
 704 }
 705
 706 static void
 707 i915_pci_remove(struct pci_dev *pdev)
 708 {
 709         struct drm_device *dev = pci_get_drvdata(pdev);
 710
 711         drm_put_dev(dev);
 712 }
 713
 714 static int i915_pm_suspend(struct device *dev)
 715 {
 716         struct pci_dev *pdev = to_pci_dev(dev);
 717         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 718         int error;
 719
 720         if (!drm_dev || !drm_dev->dev_private) {
 721                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 722                 return -ENODEV;
 723         }
 724
 725         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 726                 return 0;
 727
 728         error = i915_drm_freeze(drm_dev);
 729         if (error)
 730                 return error;
 731
 732         pci_disable_device(pdev);
 733         pci_set_power_state(pdev, PCI_D3hot);
 734
 735         return 0;
 736 }
 737
 738 static int i915_pm_resume(struct device *dev)
 739 {
 740         struct pci_dev *pdev = to_pci_dev(dev);
 741         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 742
 743         return i915_resume(drm_dev);
 744 }
 745
 746 static int i915_pm_freeze(struct device *dev)
 747 {
 748         struct pci_dev *pdev = to_pci_dev(dev);
 749         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 750
 751         if (!drm_dev || !drm_dev->dev_private) {
 752                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 753                 return -ENODEV;
 754         }
 755
 756         return i915_drm_freeze(drm_dev);
 757 }
 758
 759 static int i915_pm_thaw(struct device *dev)
 760 {
 761         struct pci_dev *pdev = to_pci_dev(dev);
 762         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 763
 764         return i915_drm_thaw(drm_dev);
 765 }
 766
 767 static int i915_pm_poweroff(struct device *dev)
 768 {
 769         struct pci_dev *pdev = to_pci_dev(dev);
 770         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 771
 772         return i915_drm_freeze(drm_dev);
 773 }
 774
 775 static const struct dev_pm_ops i915_pm_ops = {
 776         .suspend = i915_pm_suspend,
 777         .resume = i915_pm_resume,
 778         .freeze = i915_pm_freeze,
 779         .thaw = i915_pm_thaw,
 780         .poweroff = i915_pm_poweroff,
 781         .restore = i915_pm_resume,
 782 };
 783
 784 static struct vm_operations_struct i915_gem_vm_ops = {
 785         .fault = i915_gem_fault,
 786         .open = drm_gem_vm_open,
 787         .close = drm_gem_vm_close,
 788 };
 789
 790 static struct drm_driver driver = {
 791         /* don't use mtrr's here, the Xserver or user space app should
 792          * deal with them for intel hardware.
 793          */
 794         .driver_features =
 795             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 796             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 797         .load = i915_driver_load,
 798         .unload = i915_driver_unload,
 799         .open = i915_driver_open,
 800         .lastclose = i915_driver_lastclose,
 801         .preclose = i915_driver_preclose,
 802         .postclose = i915_driver_postclose,
 803
 804         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 805         .suspend = i915_suspend,
 806         .resume = i915_resume,
 807
 808         .device_is_agp = i915_driver_device_is_agp,
 809         .reclaim_buffers = drm_core_reclaim_buffers,
 810         .master_create = i915_master_create,
 811         .master_destroy = i915_master_destroy,
 812 #if defined(CONFIG_DEBUG_FS)
 813         .debugfs_init = i915_debugfs_init,
 814         .debugfs_cleanup = i915_debugfs_cleanup,
 815 #endif
 816         .gem_init_object = i915_gem_init_object,
 817         .gem_free_object = i915_gem_free_object,
 818         .gem_vm_ops = &i915_gem_vm_ops,
 819         .dumb_create = i915_gem_dumb_create,
 820         .dumb_map_offset = i915_gem_mmap_gtt,
 821         .dumb_destroy = i915_gem_dumb_destroy,
 822         .ioctls = i915_ioctls,
 823         .fops = {
 824                  .owner = THIS_MODULE,
 825                  .open = drm_open,
 826                  .release = drm_release,
 827                  .unlocked_ioctl = drm_ioctl,
 828                  .mmap = drm_gem_mmap,
 829                  .poll = drm_poll,
 830                  .fasync = drm_fasync,
 831                  .read = drm_read,
 832 #ifdef CONFIG_COMPAT
 833                  .compat_ioctl = i915_compat_ioctl,
 834 #endif
 835                  .llseek = noop_llseek,
 836         },
 837
 838         .name = DRIVER_NAME,
 839         .desc = DRIVER_DESC,
 840         .date = DRIVER_DATE,
 841         .major = DRIVER_MAJOR,
 842         .minor = DRIVER_MINOR,
 843         .patchlevel = DRIVER_PATCHLEVEL,
 844 };
 845
 846 static struct pci_driver i915_pci_driver = {
 847         .name = DRIVER_NAME,
 848         .id_table = pciidlist,
 849         .probe = i915_pci_probe,
 850         .remove = i915_pci_remove,
 851         .driver.pm = &i915_pm_ops,
 852 };
 853
 854 static int __init i915_init(void)
 855 {
 856         if (!intel_agp_enabled) {
 857                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 858                 return -ENODEV;
 859         }
 860
 861         driver.num_ioctls = i915_max_ioctl;
 862
 863         /*
 864          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 865          * explicitly disabled with the module pararmeter.
 866          *
 867          * Otherwise, just follow the parameter (defaulting to off).
 868          *
 869          * Allow optional vga_text_mode_force boot option to override
 870          * the default behavior.
 871          */
 872 #if defined(CONFIG_DRM_I915_KMS)
 873         if (i915_modeset != 0)
 874                 driver.driver_features |= DRIVER_MODESET;
 875 #endif
 876         if (i915_modeset == 1)
 877                 driver.driver_features |= DRIVER_MODESET;
 878
 879 #ifdef CONFIG_VGA_CONSOLE
 880         if (vgacon_text_force() && i915_modeset == -1)
 881                 driver.driver_features &= ~DRIVER_MODESET;
 882 #endif
 883
 884         if (!(driver.driver_features & DRIVER_MODESET))
 885                 driver.get_vblank_timestamp = NULL;
 886
 887         return drm_pci_init(&driver, &i915_pci_driver);
 888 }
 889
 890 static void __exit i915_exit(void)
 891 {
 892         drm_pci_exit(&driver, &i915_pci_driver);
 893 }
 894
 895 module_init(i915_init);
 896 module_exit(i915_exit);
 897
 898 MODULE_AUTHOR(DRIVER_AUTHOR);
 899 MODULE_DESCRIPTION(DRIVER_DESC);
 900 MODULE_LICENSE("GPL and additional rights");
 901
 902 /* We give fast paths for the really cool registers */
 903 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 904         (((dev_priv)->info->gen >= 6) && \
 905         ((reg) < 0x40000) && \
 906         ((reg) != FORCEWAKE))
 907
 908 #define __i915_read(x, y) \
 909 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 910         u##x val = 0; \
 911         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 912                 gen6_gt_force_wake_get(dev_priv); \
 913                 val = read##y(dev_priv->regs + reg); \
 914                 gen6_gt_force_wake_put(dev_priv); \
 915         } else { \
 916                 val = read##y(dev_priv->regs + reg); \
 917         } \
 918         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 919         return val; \
 920 }
 921
 922 __i915_read(8, b)
 923 __i915_read(16, w)
 924 __i915_read(32, l)
 925 __i915_read(64, q)
 926 #undef __i915_read
 927
 928 #define __i915_write(x, y) \
 929 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 930         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 931         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 932                 __gen6_gt_wait_for_fifo(dev_priv); \
 933         } \
 934         write##y(val, dev_priv->regs + reg); \
 935 }
 936 __i915_write(8, b)
 937 __i915_write(16, w)
 938 __i915_write(32, l)
 939 __i915_write(64, q)
 940 #undef __i915_write