drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include "drm_crtc_helper.h"
  39
  40 static int i915_modeset = -1;
  41 module_param_named(modeset, i915_modeset, int, 0400);
  42
  43 unsigned int i915_fbpercrtc = 0;
  44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45
  46 int i915_panel_ignore_lid = 0;
  47 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  48
  49 unsigned int i915_powersave = 1;
  50 module_param_named(powersave, i915_powersave, int, 0600);
  51
  52 unsigned int i915_semaphores = 0;
  53 module_param_named(semaphores, i915_semaphores, int, 0600);
  54
  55 unsigned int i915_enable_rc6 = 1;
  56 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  57
  58 unsigned int i915_enable_fbc = 0;
  59 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  60
  61 unsigned int i915_lvds_downclock = 0;
  62 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  63
  64 unsigned int i915_panel_use_ssc = 1;
  65 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  66
  67 int i915_vbt_sdvo_panel_type = -1;
  68 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  69
  70 static bool i915_try_reset = true;
  71 module_param_named(reset, i915_try_reset, bool, 0600);
  72
  73 static struct drm_driver driver;
  74 extern int intel_agp_enabled;
  75
  76 #define INTEL_VGA_DEVICE(id, info) {            \
  77         .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  78         .class_mask = 0xff0000,                 \
  79         .vendor = 0x8086,                       \
  80         .device = id,                           \
  81         .subvendor = PCI_ANY_ID,                \
  82         .subdevice = PCI_ANY_ID,                \
  83         .driver_data = (unsigned long) info }
  84
  85 static const struct intel_device_info intel_i830_info = {
  86         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88 };
  89
  90 static const struct intel_device_info intel_845g_info = {
  91         .gen = 2,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93 };
  94
  95 static const struct intel_device_info intel_i85x_info = {
  96         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  97         .cursor_needs_physical = 1,
  98         .has_overlay = 1, .overlay_needs_physical = 1,
  99 };
 100
 101 static const struct intel_device_info intel_i865g_info = {
 102         .gen = 2,
 103         .has_overlay = 1, .overlay_needs_physical = 1,
 104 };
 105
 106 static const struct intel_device_info intel_i915g_info = {
 107         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 108         .has_overlay = 1, .overlay_needs_physical = 1,
 109 };
 110 static const struct intel_device_info intel_i915gm_info = {
 111         .gen = 3, .is_mobile = 1,
 112         .cursor_needs_physical = 1,
 113         .has_overlay = 1, .overlay_needs_physical = 1,
 114         .supports_tv = 1,
 115 };
 116 static const struct intel_device_info intel_i945g_info = {
 117         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 118         .has_overlay = 1, .overlay_needs_physical = 1,
 119 };
 120 static const struct intel_device_info intel_i945gm_info = {
 121         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 122         .has_hotplug = 1, .cursor_needs_physical = 1,
 123         .has_overlay = 1, .overlay_needs_physical = 1,
 124         .supports_tv = 1,
 125 };
 126
 127 static const struct intel_device_info intel_i965g_info = {
 128         .gen = 4, .is_broadwater = 1,
 129         .has_hotplug = 1,
 130         .has_overlay = 1,
 131 };
 132
 133 static const struct intel_device_info intel_i965gm_info = {
 134         .gen = 4, .is_crestline = 1,
 135         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 136         .has_overlay = 1,
 137         .supports_tv = 1,
 138 };
 139
 140 static const struct intel_device_info intel_g33_info = {
 141         .gen = 3, .is_g33 = 1,
 142         .need_gfx_hws = 1, .has_hotplug = 1,
 143         .has_overlay = 1,
 144 };
 145
 146 static const struct intel_device_info intel_g45_info = {
 147         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 148         .has_pipe_cxsr = 1, .has_hotplug = 1,
 149         .has_bsd_ring = 1,
 150 };
 151
 152 static const struct intel_device_info intel_gm45_info = {
 153         .gen = 4, .is_g4x = 1,
 154         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 155         .has_pipe_cxsr = 1, .has_hotplug = 1,
 156         .supports_tv = 1,
 157         .has_bsd_ring = 1,
 158 };
 159
 160 static const struct intel_device_info intel_pineview_info = {
 161         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 162         .need_gfx_hws = 1, .has_hotplug = 1,
 163         .has_overlay = 1,
 164 };
 165
 166 static const struct intel_device_info intel_ironlake_d_info = {
 167         .gen = 5,
 168         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 169         .has_bsd_ring = 1,
 170 };
 171
 172 static const struct intel_device_info intel_ironlake_m_info = {
 173         .gen = 5, .is_mobile = 1,
 174         .need_gfx_hws = 1, .has_hotplug = 1,
 175         .has_fbc = 1,
 176         .has_bsd_ring = 1,
 177 };
 178
 179 static const struct intel_device_info intel_sandybridge_d_info = {
 180         .gen = 6,
 181         .need_gfx_hws = 1, .has_hotplug = 1,
 182         .has_bsd_ring = 1,
 183         .has_blt_ring = 1,
 184 };
 185
 186 static const struct intel_device_info intel_sandybridge_m_info = {
 187         .gen = 6, .is_mobile = 1,
 188         .need_gfx_hws = 1, .has_hotplug = 1,
 189         .has_fbc = 1,
 190         .has_bsd_ring = 1,
 191         .has_blt_ring = 1,
 192 };
 193
 194 static const struct intel_device_info intel_ivybridge_d_info = {
 195         .is_ivybridge = 1, .gen = 7,
 196         .need_gfx_hws = 1, .has_hotplug = 1,
 197         .has_bsd_ring = 1,
 198         .has_blt_ring = 1,
 199 };
 200
 201 static const struct intel_device_info intel_ivybridge_m_info = {
 202         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 203         .need_gfx_hws = 1, .has_hotplug = 1,
 204         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 205         .has_bsd_ring = 1,
 206         .has_blt_ring = 1,
 207 };
 208
 209 static const struct pci_device_id pciidlist[] = {               /* aka */
 210         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 211         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 212         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 213         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 214         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 215         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 216         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 217         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 218         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 219         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 220         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 221         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 222         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 223         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 224         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 225         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 226         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 227         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 228         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 229         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 230         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 231         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 232         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 233         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 234         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 235         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 236         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 237         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 238         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 239         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 240         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 241         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 242         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 243         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 244         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 245         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 246         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 247         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 248         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 249         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 250         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 251         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 252         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 253         {0, 0, 0}
 254 };
 255
 256 #if defined(CONFIG_DRM_I915_KMS)
 257 MODULE_DEVICE_TABLE(pci, pciidlist);
 258 #endif
 259
 260 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 261 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 262 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 263 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 264
 265 void intel_detect_pch (struct drm_device *dev)
 266 {
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct pci_dev *pch;
 269
 270         /*
 271          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 272          * make graphics device passthrough work easy for VMM, that only
 273          * need to expose ISA bridge to let driver know the real hardware
 274          * underneath. This is a requirement from virtualization team.
 275          */
 276         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 277         if (pch) {
 278                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 279                         int id;
 280                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 281
 282                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 283                                 dev_priv->pch_type = PCH_IBX;
 284                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 285                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 286                                 dev_priv->pch_type = PCH_CPT;
 287                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 288                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 289                                 /* PantherPoint is CPT compatible */
 290                                 dev_priv->pch_type = PCH_CPT;
 291                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 292                         }
 293                 }
 294                 pci_dev_put(pch);
 295         }
 296 }
 297
 298 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 299 {
 300         int count;
 301
 302         count = 0;
 303         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 304                 udelay(10);
 305
 306         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 307         POSTING_READ(FORCEWAKE);
 308
 309         count = 0;
 310         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 311                 udelay(10);
 312 }
 313
 314 /*
 315  * Generally this is called implicitly by the register read function. However,
 316  * if some sequence requires the GT to not power down then this function should
 317  * be called at the beginning of the sequence followed by a call to
 318  * gen6_gt_force_wake_put() at the end of the sequence.
 319  */
 320 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 321 {
 322         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 323
 324         /* Forcewake is atomic in case we get in here without the lock */
 325         if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
 326                 __gen6_gt_force_wake_get(dev_priv);
 327 }
 328
 329 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 330 {
 331         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 332         POSTING_READ(FORCEWAKE);
 333 }
 334
 335 /*
 336  * see gen6_gt_force_wake_get()
 337  */
 338 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 339 {
 340         WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
 341
 342         if (atomic_dec_and_test(&dev_priv->forcewake_count))
 343                 __gen6_gt_force_wake_put(dev_priv);
 344 }
 345
 346 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 347 {
 348         int loop = 500;
 349         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 350         while (fifo < 20 && loop--) {
 351                 udelay(10);
 352                 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 353         }
 354 }
 355
 356 static int i915_drm_freeze(struct drm_device *dev)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359
 360         drm_kms_helper_poll_disable(dev);
 361
 362         pci_save_state(dev->pdev);
 363
 364         /* If KMS is active, we do the leavevt stuff here */
 365         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 366                 int error = i915_gem_idle(dev);
 367                 if (error) {
 368                         dev_err(&dev->pdev->dev,
 369                                 "GEM idle failed, resume might fail\n");
 370                         return error;
 371                 }
 372                 drm_irq_uninstall(dev);
 373         }
 374
 375         i915_save_state(dev);
 376
 377         intel_opregion_fini(dev);
 378
 379         /* Modeset on resume, not lid events */
 380         dev_priv->modeset_on_lid = 0;
 381
 382         return 0;
 383 }
 384
 385 int i915_suspend(struct drm_device *dev, pm_message_t state)
 386 {
 387         int error;
 388
 389         if (!dev || !dev->dev_private) {
 390                 DRM_ERROR("dev: %p\n", dev);
 391                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 392                 return -ENODEV;
 393         }
 394
 395         if (state.event == PM_EVENT_PRETHAW)
 396                 return 0;
 397
 398
 399         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 400                 return 0;
 401
 402         error = i915_drm_freeze(dev);
 403         if (error)
 404                 return error;
 405
 406         if (state.event == PM_EVENT_SUSPEND) {
 407                 /* Shut down the device */
 408                 pci_disable_device(dev->pdev);
 409                 pci_set_power_state(dev->pdev, PCI_D3hot);
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int i915_drm_thaw(struct drm_device *dev)
 416 {
 417         struct drm_i915_private *dev_priv = dev->dev_private;
 418         int error = 0;
 419
 420         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 421                 mutex_lock(&dev->struct_mutex);
 422                 i915_gem_restore_gtt_mappings(dev);
 423                 mutex_unlock(&dev->struct_mutex);
 424         }
 425
 426         i915_restore_state(dev);
 427         intel_opregion_setup(dev);
 428
 429         /* KMS EnterVT equivalent */
 430         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 431                 mutex_lock(&dev->struct_mutex);
 432                 dev_priv->mm.suspended = 0;
 433
 434                 error = i915_gem_init_ringbuffer(dev);
 435                 mutex_unlock(&dev->struct_mutex);
 436
 437                 drm_mode_config_reset(dev);
 438                 drm_irq_install(dev);
 439
 440                 /* Resume the modeset for every activated CRTC */
 441                 drm_helper_resume_force_mode(dev);
 442
 443                 if (IS_IRONLAKE_M(dev))
 444                         ironlake_enable_rc6(dev);
 445         }
 446
 447         intel_opregion_init(dev);
 448
 449         dev_priv->modeset_on_lid = 0;
 450
 451         return error;
 452 }
 453
 454 int i915_resume(struct drm_device *dev)
 455 {
 456         int ret;
 457
 458         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 459                 return 0;
 460
 461         if (pci_enable_device(dev->pdev))
 462                 return -EIO;
 463
 464         pci_set_master(dev->pdev);
 465
 466         ret = i915_drm_thaw(dev);
 467         if (ret)
 468                 return ret;
 469
 470         drm_kms_helper_poll_enable(dev);
 471         return 0;
 472 }
 473
 474 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 475 {
 476         struct drm_i915_private *dev_priv = dev->dev_private;
 477
 478         if (IS_I85X(dev))
 479                 return -ENODEV;
 480
 481         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 482         POSTING_READ(D_STATE);
 483
 484         if (IS_I830(dev) || IS_845G(dev)) {
 485                 I915_WRITE(DEBUG_RESET_I830,
 486                            DEBUG_RESET_DISPLAY |
 487                            DEBUG_RESET_RENDER |
 488                            DEBUG_RESET_FULL);
 489                 POSTING_READ(DEBUG_RESET_I830);
 490                 msleep(1);
 491
 492                 I915_WRITE(DEBUG_RESET_I830, 0);
 493                 POSTING_READ(DEBUG_RESET_I830);
 494         }
 495
 496         msleep(1);
 497
 498         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 499         POSTING_READ(D_STATE);
 500
 501         return 0;
 502 }
 503
 504 static int i965_reset_complete(struct drm_device *dev)
 505 {
 506         u8 gdrst;
 507         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 508         return gdrst & 0x1;
 509 }
 510
 511 static int i965_do_reset(struct drm_device *dev, u8 flags)
 512 {
 513         u8 gdrst;
 514
 515         /*
 516          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 517          * well as the reset bit (GR/bit 0).  Setting the GR bit
 518          * triggers the reset; when done, the hardware will clear it.
 519          */
 520         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 521         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 522
 523         return wait_for(i965_reset_complete(dev), 500);
 524 }
 525
 526 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 527 {
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 530         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 531         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 532 }
 533
 534 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 535 {
 536         struct drm_i915_private *dev_priv = dev->dev_private;
 537
 538         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 539         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 540 }
 541
 542 /**
 543  * i965_reset - reset chip after a hang
 544  * @dev: drm device to reset
 545  * @flags: reset domains
 546  *
 547  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 548  * reset or otherwise an error code.
 549  *
 550  * Procedure is fairly simple:
 551  *   - reset the chip using the reset reg
 552  *   - re-init context state
 553  *   - re-init hardware status page
 554  *   - re-init ring buffer
 555  *   - re-init interrupt state
 556  *   - re-init display
 557  */
 558 int i915_reset(struct drm_device *dev, u8 flags)
 559 {
 560         drm_i915_private_t *dev_priv = dev->dev_private;
 561         /*
 562          * We really should only reset the display subsystem if we actually
 563          * need to
 564          */
 565         bool need_display = true;
 566         int ret;
 567
 568         if (!i915_try_reset)
 569                 return 0;
 570
 571         if (!mutex_trylock(&dev->struct_mutex))
 572                 return -EBUSY;
 573
 574         i915_gem_reset(dev);
 575
 576         ret = -ENODEV;
 577         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 578                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 579         } else switch (INTEL_INFO(dev)->gen) {
 580         case 6:
 581                 ret = gen6_do_reset(dev, flags);
 582                 /* If reset with a user forcewake, try to restore */
 583                 if (atomic_read(&dev_priv->forcewake_count))
 584                         __gen6_gt_force_wake_get(dev_priv);
 585                 break;
 586         case 5:
 587                 ret = ironlake_do_reset(dev, flags);
 588                 break;
 589         case 4:
 590                 ret = i965_do_reset(dev, flags);
 591                 break;
 592         case 2:
 593                 ret = i8xx_do_reset(dev, flags);
 594                 break;
 595         }
 596         dev_priv->last_gpu_reset = get_seconds();
 597         if (ret) {
 598                 DRM_ERROR("Failed to reset chip.\n");
 599                 mutex_unlock(&dev->struct_mutex);
 600                 return ret;
 601         }
 602
 603         /* Ok, now get things going again... */
 604
 605         /*
 606          * Everything depends on having the GTT running, so we need to start
 607          * there.  Fortunately we don't need to do this unless we reset the
 608          * chip at a PCI level.
 609          *
 610          * Next we need to restore the context, but we don't use those
 611          * yet either...
 612          *
 613          * Ring buffer needs to be re-initialized in the KMS case, or if X
 614          * was running at the time of the reset (i.e. we weren't VT
 615          * switched away).
 616          */
 617         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 618                         !dev_priv->mm.suspended) {
 619                 dev_priv->mm.suspended = 0;
 620
 621                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 622                 if (HAS_BSD(dev))
 623                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 624                 if (HAS_BLT(dev))
 625                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 626
 627                 mutex_unlock(&dev->struct_mutex);
 628                 drm_irq_uninstall(dev);
 629                 drm_mode_config_reset(dev);
 630                 drm_irq_install(dev);
 631                 mutex_lock(&dev->struct_mutex);
 632         }
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         /*
 637          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 638          * need to retrain the display link and cannot just restore the register
 639          * values.
 640          */
 641         if (need_display) {
 642                 mutex_lock(&dev->mode_config.mutex);
 643                 drm_helper_resume_force_mode(dev);
 644                 mutex_unlock(&dev->mode_config.mutex);
 645         }
 646
 647         return 0;
 648 }
 649
 650
 651 static int __devinit
 652 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 653 {
 654         /* Only bind to function 0 of the device. Early generations
 655          * used function 1 as a placeholder for multi-head. This causes
 656          * us confusion instead, especially on the systems where both
 657          * functions have the same PCI-ID!
 658          */
 659         if (PCI_FUNC(pdev->devfn))
 660                 return -ENODEV;
 661
 662         return drm_get_pci_dev(pdev, ent, &driver);
 663 }
 664
 665 static void
 666 i915_pci_remove(struct pci_dev *pdev)
 667 {
 668         struct drm_device *dev = pci_get_drvdata(pdev);
 669
 670         drm_put_dev(dev);
 671 }
 672
 673 static int i915_pm_suspend(struct device *dev)
 674 {
 675         struct pci_dev *pdev = to_pci_dev(dev);
 676         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 677         int error;
 678
 679         if (!drm_dev || !drm_dev->dev_private) {
 680                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 681                 return -ENODEV;
 682         }
 683
 684         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 685                 return 0;
 686
 687         error = i915_drm_freeze(drm_dev);
 688         if (error)
 689                 return error;
 690
 691         pci_disable_device(pdev);
 692         pci_set_power_state(pdev, PCI_D3hot);
 693
 694         return 0;
 695 }
 696
 697 static int i915_pm_resume(struct device *dev)
 698 {
 699         struct pci_dev *pdev = to_pci_dev(dev);
 700         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 701
 702         return i915_resume(drm_dev);
 703 }
 704
 705 static int i915_pm_freeze(struct device *dev)
 706 {
 707         struct pci_dev *pdev = to_pci_dev(dev);
 708         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 709
 710         if (!drm_dev || !drm_dev->dev_private) {
 711                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 712                 return -ENODEV;
 713         }
 714
 715         return i915_drm_freeze(drm_dev);
 716 }
 717
 718 static int i915_pm_thaw(struct device *dev)
 719 {
 720         struct pci_dev *pdev = to_pci_dev(dev);
 721         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 722
 723         return i915_drm_thaw(drm_dev);
 724 }
 725
 726 static int i915_pm_poweroff(struct device *dev)
 727 {
 728         struct pci_dev *pdev = to_pci_dev(dev);
 729         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 730
 731         return i915_drm_freeze(drm_dev);
 732 }
 733
 734 static const struct dev_pm_ops i915_pm_ops = {
 735      .suspend = i915_pm_suspend,
 736      .resume = i915_pm_resume,
 737      .freeze = i915_pm_freeze,
 738      .thaw = i915_pm_thaw,
 739      .poweroff = i915_pm_poweroff,
 740      .restore = i915_pm_resume,
 741 };
 742
 743 static struct vm_operations_struct i915_gem_vm_ops = {
 744         .fault = i915_gem_fault,
 745         .open = drm_gem_vm_open,
 746         .close = drm_gem_vm_close,
 747 };
 748
 749 static struct drm_driver driver = {
 750         /* don't use mtrr's here, the Xserver or user space app should
 751          * deal with them for intel hardware.
 752          */
 753         .driver_features =
 754             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 755             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 756         .load = i915_driver_load,
 757         .unload = i915_driver_unload,
 758         .open = i915_driver_open,
 759         .lastclose = i915_driver_lastclose,
 760         .preclose = i915_driver_preclose,
 761         .postclose = i915_driver_postclose,
 762
 763         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 764         .suspend = i915_suspend,
 765         .resume = i915_resume,
 766
 767         .device_is_agp = i915_driver_device_is_agp,
 768         .enable_vblank = i915_enable_vblank,
 769         .disable_vblank = i915_disable_vblank,
 770         .get_vblank_timestamp = i915_get_vblank_timestamp,
 771         .get_scanout_position = i915_get_crtc_scanoutpos,
 772         .irq_preinstall = i915_driver_irq_preinstall,
 773         .irq_postinstall = i915_driver_irq_postinstall,
 774         .irq_uninstall = i915_driver_irq_uninstall,
 775         .irq_handler = i915_driver_irq_handler,
 776         .reclaim_buffers = drm_core_reclaim_buffers,
 777         .master_create = i915_master_create,
 778         .master_destroy = i915_master_destroy,
 779 #if defined(CONFIG_DEBUG_FS)
 780         .debugfs_init = i915_debugfs_init,
 781         .debugfs_cleanup = i915_debugfs_cleanup,
 782 #endif
 783         .gem_init_object = i915_gem_init_object,
 784         .gem_free_object = i915_gem_free_object,
 785         .gem_vm_ops = &i915_gem_vm_ops,
 786         .dumb_create = i915_gem_dumb_create,
 787         .dumb_map_offset = i915_gem_mmap_gtt,
 788         .dumb_destroy = i915_gem_dumb_destroy,
 789         .ioctls = i915_ioctls,
 790         .fops = {
 791                  .owner = THIS_MODULE,
 792                  .open = drm_open,
 793                  .release = drm_release,
 794                  .unlocked_ioctl = drm_ioctl,
 795                  .mmap = drm_gem_mmap,
 796                  .poll = drm_poll,
 797                  .fasync = drm_fasync,
 798                  .read = drm_read,
 799 #ifdef CONFIG_COMPAT
 800                  .compat_ioctl = i915_compat_ioctl,
 801 #endif
 802                  .llseek = noop_llseek,
 803         },
 804
 805         .name = DRIVER_NAME,
 806         .desc = DRIVER_DESC,
 807         .date = DRIVER_DATE,
 808         .major = DRIVER_MAJOR,
 809         .minor = DRIVER_MINOR,
 810         .patchlevel = DRIVER_PATCHLEVEL,
 811 };
 812
 813 static struct pci_driver i915_pci_driver = {
 814         .name = DRIVER_NAME,
 815         .id_table = pciidlist,
 816         .probe = i915_pci_probe,
 817         .remove = i915_pci_remove,
 818         .driver.pm = &i915_pm_ops,
 819 };
 820
 821 static int __init i915_init(void)
 822 {
 823         if (!intel_agp_enabled) {
 824                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 825                 return -ENODEV;
 826         }
 827
 828         driver.num_ioctls = i915_max_ioctl;
 829
 830         /*
 831          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 832          * explicitly disabled with the module pararmeter.
 833          *
 834          * Otherwise, just follow the parameter (defaulting to off).
 835          *
 836          * Allow optional vga_text_mode_force boot option to override
 837          * the default behavior.
 838          */
 839 #if defined(CONFIG_DRM_I915_KMS)
 840         if (i915_modeset != 0)
 841                 driver.driver_features |= DRIVER_MODESET;
 842 #endif
 843         if (i915_modeset == 1)
 844                 driver.driver_features |= DRIVER_MODESET;
 845
 846 #ifdef CONFIG_VGA_CONSOLE
 847         if (vgacon_text_force() && i915_modeset == -1)
 848                 driver.driver_features &= ~DRIVER_MODESET;
 849 #endif
 850
 851         if (!(driver.driver_features & DRIVER_MODESET))
 852                 driver.get_vblank_timestamp = NULL;
 853
 854         return drm_pci_init(&driver, &i915_pci_driver);
 855 }
 856
 857 static void __exit i915_exit(void)
 858 {
 859         drm_pci_exit(&driver, &i915_pci_driver);
 860 }
 861
 862 module_init(i915_init);
 863 module_exit(i915_exit);
 864
 865 MODULE_AUTHOR(DRIVER_AUTHOR);
 866 MODULE_DESCRIPTION(DRIVER_DESC);
 867 MODULE_LICENSE("GPL and additional rights");