drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43 #include <acpi/video.h>
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         /* Program Hardware Status Page */
  53         dev_priv->status_page_dmah =
  54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  55
  56         if (!dev_priv->status_page_dmah) {
  57                 DRM_ERROR("Can not allocate hardware status page\n");
  58                 return -ENOMEM;
  59         }
  60         dev_priv->render_ring.status_page.page_addr
  61                 = dev_priv->status_page_dmah->vaddr;
  62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  63
  64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  65
  66         if (INTEL_INFO(dev)->gen >= 4)
  67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  68                                              0xf0;
  69
  70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  72         return 0;
  73 }
  74
  75 /**
  76  * Frees the hardware status page, whether it's a physical address or a virtual
  77  * address set up by the X Server.
  78  */
  79 static void i915_free_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         if (dev_priv->status_page_dmah) {
  83                 drm_pci_free(dev, dev_priv->status_page_dmah);
  84                 dev_priv->status_page_dmah = NULL;
  85         }
  86
  87         if (dev_priv->render_ring.status_page.gfx_addr) {
  88                 dev_priv->render_ring.status_page.gfx_addr = 0;
  89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  90         }
  91
  92         /* Need to rewrite hardware status page */
  93         I915_WRITE(HWS_PGA, 0x1ffff000);
  94 }
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         struct drm_i915_master_private *master_priv;
 100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 101
 102         /*
 103          * We should never lose context on the ring with modesetting
 104          * as we don't expose it to userspace
 105          */
 106         if (drm_core_check_feature(dev, DRIVER_MODESET))
 107                 return;
 108
 109         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 110         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 111         ring->space = ring->head - (ring->tail + 8);
 112         if (ring->space < 0)
 113                 ring->space += ring->size;
 114
 115         if (!dev->primary->master)
 116                 return;
 117
 118         master_priv = dev->primary->master->driver_priv;
 119         if (ring->head == ring->tail && master_priv->sarea_priv)
 120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 121 }
 122
 123 static int i915_dma_cleanup(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         /* Make sure interrupts are disabled here because the uninstall ioctl
 127          * may not have been called from userspace and after dev_private
 128          * is freed, it's too late.
 129          */
 130         if (dev->irq_enabled)
 131                 drm_irq_uninstall(dev);
 132
 133         mutex_lock(&dev->struct_mutex);
 134         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 135         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 136         intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring);
 137         mutex_unlock(&dev->struct_mutex);
 138
 139         /* Clear the HWS virtual address at teardown */
 140         if (I915_NEED_GFX_HWS(dev))
 141                 i915_free_hws(dev);
 142
 143         return 0;
 144 }
 145
 146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 147 {
 148         drm_i915_private_t *dev_priv = dev->dev_private;
 149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 150
 151         master_priv->sarea = drm_getsarea(dev);
 152         if (master_priv->sarea) {
 153                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 154                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 155         } else {
 156                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 157         }
 158
 159         if (init->ring_size != 0) {
 160                 if (dev_priv->render_ring.gem_object != NULL) {
 161                         i915_dma_cleanup(dev);
 162                         DRM_ERROR("Client tried to initialize ringbuffer in "
 163                                   "GEM mode\n");
 164                         return -EINVAL;
 165                 }
 166
 167                 dev_priv->render_ring.size = init->ring_size;
 168
 169                 dev_priv->render_ring.map.offset = init->ring_start;
 170                 dev_priv->render_ring.map.size = init->ring_size;
 171                 dev_priv->render_ring.map.type = 0;
 172                 dev_priv->render_ring.map.flags = 0;
 173                 dev_priv->render_ring.map.mtrr = 0;
 174
 175                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 176
 177                 if (dev_priv->render_ring.map.handle == NULL) {
 178                         i915_dma_cleanup(dev);
 179                         DRM_ERROR("can not ioremap virtual address for"
 180                                   " ring buffer\n");
 181                         return -ENOMEM;
 182                 }
 183         }
 184
 185         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 186
 187         dev_priv->cpp = init->cpp;
 188         dev_priv->back_offset = init->back_offset;
 189         dev_priv->front_offset = init->front_offset;
 190         dev_priv->current_page = 0;
 191         if (master_priv->sarea_priv)
 192                 master_priv->sarea_priv->pf_current_page = 0;
 193
 194         /* Allow hardware batchbuffers unless told otherwise.
 195          */
 196         dev_priv->allow_batchbuffer = 1;
 197
 198         return 0;
 199 }
 200
 201 static int i915_dma_resume(struct drm_device * dev)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204
 205         struct intel_ring_buffer *ring;
 206         DRM_DEBUG_DRIVER("%s\n", __func__);
 207
 208         ring = &dev_priv->render_ring;
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 intel_ring_setup_status_page(dev, ring);
 225         else
 226                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int do_validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int validate_cmd(int cmd)
 325 {
 326         int ret = do_validate_cmd(cmd);
 327
 328 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 329
 330         return ret;
 331 }
 332
 333 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 334 {
 335         drm_i915_private_t *dev_priv = dev->dev_private;
 336         int i;
 337
 338         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 339                 return -EINVAL;
 340
 341         BEGIN_LP_RING((dwords+1)&~1);
 342
 343         for (i = 0; i < dwords;) {
 344                 int cmd, sz;
 345
 346                 cmd = buffer[i];
 347
 348                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 349                         return -EINVAL;
 350
 351                 OUT_RING(cmd);
 352
 353                 while (++i, --sz) {
 354                         OUT_RING(buffer[i]);
 355                 }
 356         }
 357
 358         if (dwords & 1)
 359                 OUT_RING(0);
 360
 361         ADVANCE_LP_RING();
 362
 363         return 0;
 364 }
 365
 366 int
 367 i915_emit_box(struct drm_device *dev,
 368               struct drm_clip_rect *boxes,
 369               int i, int DR1, int DR4)
 370 {
 371         struct drm_clip_rect box = boxes[i];
 372
 373         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 374                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 375                           box.x1, box.y1, box.x2, box.y2);
 376                 return -EINVAL;
 377         }
 378
 379         if (INTEL_INFO(dev)->gen >= 4) {
 380                 BEGIN_LP_RING(4);
 381                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 382                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 383                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 384                 OUT_RING(DR4);
 385                 ADVANCE_LP_RING();
 386         } else {
 387                 BEGIN_LP_RING(6);
 388                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 389                 OUT_RING(DR1);
 390                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 391                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 392                 OUT_RING(DR4);
 393                 OUT_RING(0);
 394                 ADVANCE_LP_RING();
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* XXX: Emitting the counter should really be moved to part of the IRQ
 401  * emit. For now, do it in both places:
 402  */
 403
 404 static void i915_emit_breadcrumb(struct drm_device *dev)
 405 {
 406         drm_i915_private_t *dev_priv = dev->dev_private;
 407         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 408
 409         dev_priv->counter++;
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->counter = 0;
 412         if (master_priv->sarea_priv)
 413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 414
 415         BEGIN_LP_RING(4);
 416         OUT_RING(MI_STORE_DWORD_INDEX);
 417         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 418         OUT_RING(dev_priv->counter);
 419         OUT_RING(0);
 420         ADVANCE_LP_RING();
 421 }
 422
 423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 424                                    drm_i915_cmdbuffer_t *cmd,
 425                                    struct drm_clip_rect *cliprects,
 426                                    void *cmdbuf)
 427 {
 428         int nbox = cmd->num_cliprects;
 429         int i = 0, count, ret;
 430
 431         if (cmd->sz & 0x3) {
 432                 DRM_ERROR("alignment");
 433                 return -EINVAL;
 434         }
 435
 436         i915_kernel_lost_context(dev);
 437
 438         count = nbox ? nbox : 1;
 439
 440         for (i = 0; i < count; i++) {
 441                 if (i < nbox) {
 442                         ret = i915_emit_box(dev, cliprects, i,
 443                                             cmd->DR1, cmd->DR4);
 444                         if (ret)
 445                                 return ret;
 446                 }
 447
 448                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         i915_emit_breadcrumb(dev);
 454         return 0;
 455 }
 456
 457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 458                                      drm_i915_batchbuffer_t * batch,
 459                                      struct drm_clip_rect *cliprects)
 460 {
 461         int nbox = batch->num_cliprects;
 462         int i = 0, count;
 463
 464         if ((batch->start | batch->used) & 0x7) {
 465                 DRM_ERROR("alignment");
 466                 return -EINVAL;
 467         }
 468
 469         i915_kernel_lost_context(dev);
 470
 471         count = nbox ? nbox : 1;
 472
 473         for (i = 0; i < count; i++) {
 474                 if (i < nbox) {
 475                         int ret = i915_emit_box(dev, cliprects, i,
 476                                                 batch->DR1, batch->DR4);
 477                         if (ret)
 478                                 return ret;
 479                 }
 480
 481                 if (!IS_I830(dev) && !IS_845G(dev)) {
 482                         BEGIN_LP_RING(2);
 483                         if (INTEL_INFO(dev)->gen >= 4) {
 484                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 485                                 OUT_RING(batch->start);
 486                         } else {
 487                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 488                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 489                         }
 490                         ADVANCE_LP_RING();
 491                 } else {
 492                         BEGIN_LP_RING(4);
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                         ADVANCE_LP_RING();
 498                 }
 499         }
 500
 501
 502         if (IS_G4X(dev) || IS_GEN5(dev)) {
 503                 BEGIN_LP_RING(2);
 504                 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 505                 OUT_RING(MI_NOOP);
 506                 ADVANCE_LP_RING();
 507         }
 508         i915_emit_breadcrumb(dev);
 509
 510         return 0;
 511 }
 512
 513 static int i915_dispatch_flip(struct drm_device * dev)
 514 {
 515         drm_i915_private_t *dev_priv = dev->dev_private;
 516         struct drm_i915_master_private *master_priv =
 517                 dev->primary->master->driver_priv;
 518
 519         if (!master_priv->sarea_priv)
 520                 return -EINVAL;
 521
 522         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 523                           __func__,
 524                          dev_priv->current_page,
 525                          master_priv->sarea_priv->pf_current_page);
 526
 527         i915_kernel_lost_context(dev);
 528
 529         BEGIN_LP_RING(2);
 530         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 531         OUT_RING(0);
 532         ADVANCE_LP_RING();
 533
 534         BEGIN_LP_RING(6);
 535         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 536         OUT_RING(0);
 537         if (dev_priv->current_page == 0) {
 538                 OUT_RING(dev_priv->back_offset);
 539                 dev_priv->current_page = 1;
 540         } else {
 541                 OUT_RING(dev_priv->front_offset);
 542                 dev_priv->current_page = 0;
 543         }
 544         OUT_RING(0);
 545         ADVANCE_LP_RING();
 546
 547         BEGIN_LP_RING(2);
 548         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 549         OUT_RING(0);
 550         ADVANCE_LP_RING();
 551
 552         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 553
 554         BEGIN_LP_RING(4);
 555         OUT_RING(MI_STORE_DWORD_INDEX);
 556         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 557         OUT_RING(dev_priv->counter);
 558         OUT_RING(0);
 559         ADVANCE_LP_RING();
 560
 561         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 562         return 0;
 563 }
 564
 565 static int i915_quiescent(struct drm_device * dev)
 566 {
 567         drm_i915_private_t *dev_priv = dev->dev_private;
 568
 569         i915_kernel_lost_context(dev);
 570         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 571                                       dev_priv->render_ring.size - 8);
 572 }
 573
 574 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 575                             struct drm_file *file_priv)
 576 {
 577         int ret;
 578
 579         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 580
 581         mutex_lock(&dev->struct_mutex);
 582         ret = i915_quiescent(dev);
 583         mutex_unlock(&dev->struct_mutex);
 584
 585         return ret;
 586 }
 587
 588 static int i915_batchbuffer(struct drm_device *dev, void *data,
 589                             struct drm_file *file_priv)
 590 {
 591         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 592         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 593         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 594             master_priv->sarea_priv;
 595         drm_i915_batchbuffer_t *batch = data;
 596         int ret;
 597         struct drm_clip_rect *cliprects = NULL;
 598
 599         if (!dev_priv->allow_batchbuffer) {
 600                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 601                 return -EINVAL;
 602         }
 603
 604         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 605                         batch->start, batch->used, batch->num_cliprects);
 606
 607         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 608
 609         if (batch->num_cliprects < 0)
 610                 return -EINVAL;
 611
 612         if (batch->num_cliprects) {
 613                 cliprects = kcalloc(batch->num_cliprects,
 614                                     sizeof(struct drm_clip_rect),
 615                                     GFP_KERNEL);
 616                 if (cliprects == NULL)
 617                         return -ENOMEM;
 618
 619                 ret = copy_from_user(cliprects, batch->cliprects,
 620                                      batch->num_cliprects *
 621                                      sizeof(struct drm_clip_rect));
 622                 if (ret != 0) {
 623                         ret = -EFAULT;
 624                         goto fail_free;
 625                 }
 626         }
 627
 628         mutex_lock(&dev->struct_mutex);
 629         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 630         mutex_unlock(&dev->struct_mutex);
 631
 632         if (sarea_priv)
 633                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 634
 635 fail_free:
 636         kfree(cliprects);
 637
 638         return ret;
 639 }
 640
 641 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 642                           struct drm_file *file_priv)
 643 {
 644         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 645         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 646         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 647             master_priv->sarea_priv;
 648         drm_i915_cmdbuffer_t *cmdbuf = data;
 649         struct drm_clip_rect *cliprects = NULL;
 650         void *batch_data;
 651         int ret;
 652
 653         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 654                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 655
 656         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 657
 658         if (cmdbuf->num_cliprects < 0)
 659                 return -EINVAL;
 660
 661         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 662         if (batch_data == NULL)
 663                 return -ENOMEM;
 664
 665         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 666         if (ret != 0) {
 667                 ret = -EFAULT;
 668                 goto fail_batch_free;
 669         }
 670
 671         if (cmdbuf->num_cliprects) {
 672                 cliprects = kcalloc(cmdbuf->num_cliprects,
 673                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 674                 if (cliprects == NULL) {
 675                         ret = -ENOMEM;
 676                         goto fail_batch_free;
 677                 }
 678
 679                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 680                                      cmdbuf->num_cliprects *
 681                                      sizeof(struct drm_clip_rect));
 682                 if (ret != 0) {
 683                         ret = -EFAULT;
 684                         goto fail_clip_free;
 685                 }
 686         }
 687
 688         mutex_lock(&dev->struct_mutex);
 689         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 690         mutex_unlock(&dev->struct_mutex);
 691         if (ret) {
 692                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 693                 goto fail_clip_free;
 694         }
 695
 696         if (sarea_priv)
 697                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 698
 699 fail_clip_free:
 700         kfree(cliprects);
 701 fail_batch_free:
 702         kfree(batch_data);
 703
 704         return ret;
 705 }
 706
 707 static int i915_flip_bufs(struct drm_device *dev, void *data,
 708                           struct drm_file *file_priv)
 709 {
 710         int ret;
 711
 712         DRM_DEBUG_DRIVER("%s\n", __func__);
 713
 714         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 715
 716         mutex_lock(&dev->struct_mutex);
 717         ret = i915_dispatch_flip(dev);
 718         mutex_unlock(&dev->struct_mutex);
 719
 720         return ret;
 721 }
 722
 723 static int i915_getparam(struct drm_device *dev, void *data,
 724                          struct drm_file *file_priv)
 725 {
 726         drm_i915_private_t *dev_priv = dev->dev_private;
 727         drm_i915_getparam_t *param = data;
 728         int value;
 729
 730         if (!dev_priv) {
 731                 DRM_ERROR("called with no initialization\n");
 732                 return -EINVAL;
 733         }
 734
 735         switch (param->param) {
 736         case I915_PARAM_IRQ_ACTIVE:
 737                 value = dev->pdev->irq ? 1 : 0;
 738                 break;
 739         case I915_PARAM_ALLOW_BATCHBUFFER:
 740                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 741                 break;
 742         case I915_PARAM_LAST_DISPATCH:
 743                 value = READ_BREADCRUMB(dev_priv);
 744                 break;
 745         case I915_PARAM_CHIPSET_ID:
 746                 value = dev->pci_device;
 747                 break;
 748         case I915_PARAM_HAS_GEM:
 749                 value = dev_priv->has_gem;
 750                 break;
 751         case I915_PARAM_NUM_FENCES_AVAIL:
 752                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 753                 break;
 754         case I915_PARAM_HAS_OVERLAY:
 755                 value = dev_priv->overlay ? 1 : 0;
 756                 break;
 757         case I915_PARAM_HAS_PAGEFLIPPING:
 758                 value = 1;
 759                 break;
 760         case I915_PARAM_HAS_EXECBUF2:
 761                 /* depends on GEM */
 762                 value = dev_priv->has_gem;
 763                 break;
 764         case I915_PARAM_HAS_BSD:
 765                 value = HAS_BSD(dev);
 766                 break;
 767         case I915_PARAM_HAS_BLT:
 768                 value = HAS_BLT(dev);
 769                 break;
 770         default:
 771                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 772                                  param->param);
 773                 return -EINVAL;
 774         }
 775
 776         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 777                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 778                 return -EFAULT;
 779         }
 780
 781         return 0;
 782 }
 783
 784 static int i915_setparam(struct drm_device *dev, void *data,
 785                          struct drm_file *file_priv)
 786 {
 787         drm_i915_private_t *dev_priv = dev->dev_private;
 788         drm_i915_setparam_t *param = data;
 789
 790         if (!dev_priv) {
 791                 DRM_ERROR("called with no initialization\n");
 792                 return -EINVAL;
 793         }
 794
 795         switch (param->param) {
 796         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 797                 break;
 798         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 799                 dev_priv->tex_lru_log_granularity = param->value;
 800                 break;
 801         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 802                 dev_priv->allow_batchbuffer = param->value;
 803                 break;
 804         case I915_SETPARAM_NUM_USED_FENCES:
 805                 if (param->value > dev_priv->num_fence_regs ||
 806                     param->value < 0)
 807                         return -EINVAL;
 808                 /* Userspace can use first N regs */
 809                 dev_priv->fence_reg_start = param->value;
 810                 break;
 811         default:
 812                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 813                                         param->param);
 814                 return -EINVAL;
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int i915_set_status_page(struct drm_device *dev, void *data,
 821                                 struct drm_file *file_priv)
 822 {
 823         drm_i915_private_t *dev_priv = dev->dev_private;
 824         drm_i915_hws_addr_t *hws = data;
 825         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 826
 827         if (!I915_NEED_GFX_HWS(dev))
 828                 return -EINVAL;
 829
 830         if (!dev_priv) {
 831                 DRM_ERROR("called with no initialization\n");
 832                 return -EINVAL;
 833         }
 834
 835         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 836                 WARN(1, "tried to set status page when mode setting active\n");
 837                 return 0;
 838         }
 839
 840         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 841
 842         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 843
 844         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 845         dev_priv->hws_map.size = 4*1024;
 846         dev_priv->hws_map.type = 0;
 847         dev_priv->hws_map.flags = 0;
 848         dev_priv->hws_map.mtrr = 0;
 849
 850         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 851         if (dev_priv->hws_map.handle == NULL) {
 852                 i915_dma_cleanup(dev);
 853                 ring->status_page.gfx_addr = 0;
 854                 DRM_ERROR("can not ioremap virtual address for"
 855                                 " G33 hw status page\n");
 856                 return -ENOMEM;
 857         }
 858         ring->status_page.page_addr = dev_priv->hws_map.handle;
 859         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 860         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 861
 862         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 863                          ring->status_page.gfx_addr);
 864         DRM_DEBUG_DRIVER("load hws at %p\n",
 865                          ring->status_page.page_addr);
 866         return 0;
 867 }
 868
 869 static int i915_get_bridge_dev(struct drm_device *dev)
 870 {
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872
 873         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 874         if (!dev_priv->bridge_dev) {
 875                 DRM_ERROR("bridge device not found\n");
 876                 return -1;
 877         }
 878         return 0;
 879 }
 880
 881 #define MCHBAR_I915 0x44
 882 #define MCHBAR_I965 0x48
 883 #define MCHBAR_SIZE (4*4096)
 884
 885 #define DEVEN_REG 0x54
 886 #define   DEVEN_MCHBAR_EN (1 << 28)
 887
 888 /* Allocate space for the MCH regs if needed, return nonzero on error */
 889 static int
 890 intel_alloc_mchbar_resource(struct drm_device *dev)
 891 {
 892         drm_i915_private_t *dev_priv = dev->dev_private;
 893         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 894         u32 temp_lo, temp_hi = 0;
 895         u64 mchbar_addr;
 896         int ret;
 897
 898         if (INTEL_INFO(dev)->gen >= 4)
 899                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 900         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 901         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 902
 903         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 904 #ifdef CONFIG_PNP
 905         if (mchbar_addr &&
 906             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 907                 return 0;
 908 #endif
 909
 910         /* Get some space for it */
 911         dev_priv->mch_res.name = "i915 MCHBAR";
 912         dev_priv->mch_res.flags = IORESOURCE_MEM;
 913         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 914                                      &dev_priv->mch_res,
 915                                      MCHBAR_SIZE, MCHBAR_SIZE,
 916                                      PCIBIOS_MIN_MEM,
 917                                      0, pcibios_align_resource,
 918                                      dev_priv->bridge_dev);
 919         if (ret) {
 920                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 921                 dev_priv->mch_res.start = 0;
 922                 return ret;
 923         }
 924
 925         if (INTEL_INFO(dev)->gen >= 4)
 926                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 927                                        upper_32_bits(dev_priv->mch_res.start));
 928
 929         pci_write_config_dword(dev_priv->bridge_dev, reg,
 930                                lower_32_bits(dev_priv->mch_res.start));
 931         return 0;
 932 }
 933
 934 /* Setup MCHBAR if possible, return true if we should disable it again */
 935 static void
 936 intel_setup_mchbar(struct drm_device *dev)
 937 {
 938         drm_i915_private_t *dev_priv = dev->dev_private;
 939         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 940         u32 temp;
 941         bool enabled;
 942
 943         dev_priv->mchbar_need_disable = false;
 944
 945         if (IS_I915G(dev) || IS_I915GM(dev)) {
 946                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 947                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 948         } else {
 949                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 950                 enabled = temp & 1;
 951         }
 952
 953         /* If it's already enabled, don't have to do anything */
 954         if (enabled)
 955                 return;
 956
 957         if (intel_alloc_mchbar_resource(dev))
 958                 return;
 959
 960         dev_priv->mchbar_need_disable = true;
 961
 962         /* Space is allocated or reserved, so enable it. */
 963         if (IS_I915G(dev) || IS_I915GM(dev)) {
 964                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 965                                        temp | DEVEN_MCHBAR_EN);
 966         } else {
 967                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 968                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 969         }
 970 }
 971
 972 static void
 973 intel_teardown_mchbar(struct drm_device *dev)
 974 {
 975         drm_i915_private_t *dev_priv = dev->dev_private;
 976         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 977         u32 temp;
 978
 979         if (dev_priv->mchbar_need_disable) {
 980                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 981                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 982                         temp &= ~DEVEN_MCHBAR_EN;
 983                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 984                 } else {
 985                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 986                         temp &= ~1;
 987                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 988                 }
 989         }
 990
 991         if (dev_priv->mch_res.start)
 992                 release_resource(&dev_priv->mch_res);
 993 }
 994
 995 #define PTE_ADDRESS_MASK                0xfffff000
 996 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
 997 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
 998 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
 999 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1000 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1001 #define PTE_VALID                       (1 << 0)
1002
1003 /**
1004  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1005  * @dev: drm device
1006  * @gtt_addr: address to translate
1007  *
1008  * Some chip functions require allocations from stolen space but need the
1009  * physical address of the memory in question.  We use this routine
1010  * to get a physical address suitable for register programming from a given
1011  * GTT address.
1012  */
1013 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1014                                       unsigned long gtt_addr)
1015 {
1016         unsigned long *gtt;
1017         unsigned long entry, phys;
1018         int gtt_bar = IS_GEN2(dev) ? 1 : 0;
1019         int gtt_offset, gtt_size;
1020
1021         if (INTEL_INFO(dev)->gen >= 4) {
1022                 if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {
1023                         gtt_offset = 2*1024*1024;
1024                         gtt_size = 2*1024*1024;
1025                 } else {
1026                         gtt_offset = 512*1024;
1027                         gtt_size = 512*1024;
1028                 }
1029         } else {
1030                 gtt_bar = 3;
1031                 gtt_offset = 0;
1032                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1033         }
1034
1035         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1036                          gtt_size);
1037         if (!gtt) {
1038                 DRM_ERROR("ioremap of GTT failed\n");
1039                 return 0;
1040         }
1041
1042         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1043
1044         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1045
1046         /* Mask out these reserved bits on this hardware. */
1047         if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))
1048                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1049
1050         /* If it's not a mapping type we know, then bail. */
1051         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1052             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1053                 iounmap(gtt);
1054                 return 0;
1055         }
1056
1057         if (!(entry & PTE_VALID)) {
1058                 DRM_ERROR("bad GTT entry in stolen space\n");
1059                 iounmap(gtt);
1060                 return 0;
1061         }
1062
1063         iounmap(gtt);
1064
1065         phys =(entry & PTE_ADDRESS_MASK) |
1066                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1067
1068         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1069
1070         return phys;
1071 }
1072
1073 static void i915_warn_stolen(struct drm_device *dev)
1074 {
1075         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1076         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1077 }
1078
1079 static void i915_setup_compression(struct drm_device *dev, int size)
1080 {
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1083         unsigned long cfb_base;
1084         unsigned long ll_base = 0;
1085
1086         /* Leave 1M for line length buffer & misc. */
1087         compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0);
1088         if (!compressed_fb) {
1089                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1090                 i915_warn_stolen(dev);
1091                 return;
1092         }
1093
1094         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1095         if (!compressed_fb) {
1096                 i915_warn_stolen(dev);
1097                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1098                 return;
1099         }
1100
1101         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1102         if (!cfb_base) {
1103                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1104                 drm_mm_put_block(compressed_fb);
1105         }
1106
1107         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1108                 compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096,
1109                                                     4096, 0);
1110                 if (!compressed_llb) {
1111                         i915_warn_stolen(dev);
1112                         return;
1113                 }
1114
1115                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1116                 if (!compressed_llb) {
1117                         i915_warn_stolen(dev);
1118                         return;
1119                 }
1120
1121                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1122                 if (!ll_base) {
1123                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1124                         drm_mm_put_block(compressed_fb);
1125                         drm_mm_put_block(compressed_llb);
1126                 }
1127         }
1128
1129         dev_priv->cfb_size = size;
1130
1131         intel_disable_fbc(dev);
1132         dev_priv->compressed_fb = compressed_fb;
1133         if (IS_IRONLAKE_M(dev))
1134                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1135         else if (IS_GM45(dev)) {
1136                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1137         } else {
1138                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1139                 I915_WRITE(FBC_LL_BASE, ll_base);
1140                 dev_priv->compressed_llb = compressed_llb;
1141         }
1142
1143         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1144                   ll_base, size >> 20);
1145 }
1146
1147 static void i915_cleanup_compression(struct drm_device *dev)
1148 {
1149         struct drm_i915_private *dev_priv = dev->dev_private;
1150
1151         drm_mm_put_block(dev_priv->compressed_fb);
1152         if (dev_priv->compressed_llb)
1153                 drm_mm_put_block(dev_priv->compressed_llb);
1154 }
1155
1156 /* true = enable decode, false = disable decoder */
1157 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1158 {
1159         struct drm_device *dev = cookie;
1160
1161         intel_modeset_vga_set_state(dev, state);
1162         if (state)
1163                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1164                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1165         else
1166                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1167 }
1168
1169 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1170 {
1171         struct drm_device *dev = pci_get_drvdata(pdev);
1172         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1173         if (state == VGA_SWITCHEROO_ON) {
1174                 printk(KERN_INFO "i915: switched on\n");
1175                 /* i915 resume handler doesn't set to D0 */
1176                 pci_set_power_state(dev->pdev, PCI_D0);
1177                 i915_resume(dev);
1178         } else {
1179                 printk(KERN_ERR "i915: switched off\n");
1180                 i915_suspend(dev, pmm);
1181         }
1182 }
1183
1184 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1185 {
1186         struct drm_device *dev = pci_get_drvdata(pdev);
1187         bool can_switch;
1188
1189         spin_lock(&dev->count_lock);
1190         can_switch = (dev->open_count == 0);
1191         spin_unlock(&dev->count_lock);
1192         return can_switch;
1193 }
1194
1195 static int i915_load_modeset_init(struct drm_device *dev,
1196                                   unsigned long prealloc_size,
1197                                   unsigned long agp_size)
1198 {
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         int ret = 0;
1201
1202         /* Basic memrange allocator for stolen space (aka mm.vram) */
1203         drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size);
1204
1205         /* Let GEM Manage from end of prealloc space to end of aperture.
1206          *
1207          * However, leave one page at the end still bound to the scratch page.
1208          * There are a number of places where the hardware apparently
1209          * prefetches past the end of the object, and we've seen multiple
1210          * hangs with the GPU head pointer stuck in a batchbuffer bound
1211          * at the last page of the aperture.  One page should be enough to
1212          * keep any prefetching inside of the aperture.
1213          */
1214         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1215
1216         mutex_lock(&dev->struct_mutex);
1217         ret = i915_gem_init_ringbuffer(dev);
1218         mutex_unlock(&dev->struct_mutex);
1219         if (ret)
1220                 goto out;
1221
1222         /* Try to set up FBC with a reasonable compressed buffer size */
1223         if (I915_HAS_FBC(dev) && i915_powersave) {
1224                 int cfb_size;
1225
1226                 /* Try to get an 8M buffer... */
1227                 if (prealloc_size > (9*1024*1024))
1228                         cfb_size = 8*1024*1024;
1229                 else /* fall back to 7/8 of the stolen space */
1230                         cfb_size = prealloc_size * 7 / 8;
1231                 i915_setup_compression(dev, cfb_size);
1232         }
1233
1234         /* Allow hardware batchbuffers unless told otherwise.
1235          */
1236         dev_priv->allow_batchbuffer = 1;
1237
1238         ret = intel_parse_bios(dev);
1239         if (ret)
1240                 DRM_INFO("failed to find VBIOS tables\n");
1241
1242         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1243         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1244         if (ret)
1245                 goto cleanup_ringbuffer;
1246
1247         intel_register_dsm_handler();
1248
1249         ret = vga_switcheroo_register_client(dev->pdev,
1250                                              i915_switcheroo_set_state,
1251                                              i915_switcheroo_can_switch);
1252         if (ret)
1253                 goto cleanup_vga_client;
1254
1255         /* IIR "flip pending" bit means done if this bit is set */
1256         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1257                 dev_priv->flip_pending_is_done = true;
1258
1259         intel_modeset_init(dev);
1260
1261         ret = drm_irq_install(dev);
1262         if (ret)
1263                 goto cleanup_vga_switcheroo;
1264
1265         /* Always safe in the mode setting case. */
1266         /* FIXME: do pre/post-mode set stuff in core KMS code */
1267         dev->vblank_disable_allowed = 1;
1268
1269         ret = intel_fbdev_init(dev);
1270         if (ret)
1271                 goto cleanup_irq;
1272
1273         drm_kms_helper_poll_init(dev);
1274
1275         /* We're off and running w/KMS */
1276         dev_priv->mm.suspended = 0;
1277
1278         return 0;
1279
1280 cleanup_irq:
1281         drm_irq_uninstall(dev);
1282 cleanup_vga_switcheroo:
1283         vga_switcheroo_unregister_client(dev->pdev);
1284 cleanup_vga_client:
1285         vga_client_register(dev->pdev, NULL, NULL, NULL);
1286 cleanup_ringbuffer:
1287         mutex_lock(&dev->struct_mutex);
1288         i915_gem_cleanup_ringbuffer(dev);
1289         mutex_unlock(&dev->struct_mutex);
1290 out:
1291         return ret;
1292 }
1293
1294 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1295 {
1296         struct drm_i915_master_private *master_priv;
1297
1298         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1299         if (!master_priv)
1300                 return -ENOMEM;
1301
1302         master->driver_priv = master_priv;
1303         return 0;
1304 }
1305
1306 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1307 {
1308         struct drm_i915_master_private *master_priv = master->driver_priv;
1309
1310         if (!master_priv)
1311                 return;
1312
1313         kfree(master_priv);
1314
1315         master->driver_priv = NULL;
1316 }
1317
1318 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1319 {
1320         drm_i915_private_t *dev_priv = dev->dev_private;
1321         u32 tmp;
1322
1323         tmp = I915_READ(CLKCFG);
1324
1325         switch (tmp & CLKCFG_FSB_MASK) {
1326         case CLKCFG_FSB_533:
1327                 dev_priv->fsb_freq = 533; /* 133*4 */
1328                 break;
1329         case CLKCFG_FSB_800:
1330                 dev_priv->fsb_freq = 800; /* 200*4 */
1331                 break;
1332         case CLKCFG_FSB_667:
1333                 dev_priv->fsb_freq =  667; /* 167*4 */
1334                 break;
1335         case CLKCFG_FSB_400:
1336                 dev_priv->fsb_freq = 400; /* 100*4 */
1337                 break;
1338         }
1339
1340         switch (tmp & CLKCFG_MEM_MASK) {
1341         case CLKCFG_MEM_533:
1342                 dev_priv->mem_freq = 533;
1343                 break;
1344         case CLKCFG_MEM_667:
1345                 dev_priv->mem_freq = 667;
1346                 break;
1347         case CLKCFG_MEM_800:
1348                 dev_priv->mem_freq = 800;
1349                 break;
1350         }
1351
1352         /* detect pineview DDR3 setting */
1353         tmp = I915_READ(CSHRDDR3CTL);
1354         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1355 }
1356
1357 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1358 {
1359         drm_i915_private_t *dev_priv = dev->dev_private;
1360         u16 ddrpll, csipll;
1361
1362         ddrpll = I915_READ16(DDRMPLL1);
1363         csipll = I915_READ16(CSIPLL0);
1364
1365         switch (ddrpll & 0xff) {
1366         case 0xc:
1367                 dev_priv->mem_freq = 800;
1368                 break;
1369         case 0x10:
1370                 dev_priv->mem_freq = 1066;
1371                 break;
1372         case 0x14:
1373                 dev_priv->mem_freq = 1333;
1374                 break;
1375         case 0x18:
1376                 dev_priv->mem_freq = 1600;
1377                 break;
1378         default:
1379                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1380                                  ddrpll & 0xff);
1381                 dev_priv->mem_freq = 0;
1382                 break;
1383         }
1384
1385         dev_priv->r_t = dev_priv->mem_freq;
1386
1387         switch (csipll & 0x3ff) {
1388         case 0x00c:
1389                 dev_priv->fsb_freq = 3200;
1390                 break;
1391         case 0x00e:
1392                 dev_priv->fsb_freq = 3733;
1393                 break;
1394         case 0x010:
1395                 dev_priv->fsb_freq = 4266;
1396                 break;
1397         case 0x012:
1398                 dev_priv->fsb_freq = 4800;
1399                 break;
1400         case 0x014:
1401                 dev_priv->fsb_freq = 5333;
1402                 break;
1403         case 0x016:
1404                 dev_priv->fsb_freq = 5866;
1405                 break;
1406         case 0x018:
1407                 dev_priv->fsb_freq = 6400;
1408                 break;
1409         default:
1410                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1411                                  csipll & 0x3ff);
1412                 dev_priv->fsb_freq = 0;
1413                 break;
1414         }
1415
1416         if (dev_priv->fsb_freq == 3200) {
1417                 dev_priv->c_m = 0;
1418         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1419                 dev_priv->c_m = 1;
1420         } else {
1421                 dev_priv->c_m = 2;
1422         }
1423 }
1424
1425 struct v_table {
1426         u8 vid;
1427         unsigned long vd; /* in .1 mil */
1428         unsigned long vm; /* in .1 mil */
1429         u8 pvid;
1430 };
1431
1432 static struct v_table v_table[] = {
1433         { 0, 16125, 15000, 0x7f, },
1434         { 1, 16000, 14875, 0x7e, },
1435         { 2, 15875, 14750, 0x7d, },
1436         { 3, 15750, 14625, 0x7c, },
1437         { 4, 15625, 14500, 0x7b, },
1438         { 5, 15500, 14375, 0x7a, },
1439         { 6, 15375, 14250, 0x79, },
1440         { 7, 15250, 14125, 0x78, },
1441         { 8, 15125, 14000, 0x77, },
1442         { 9, 15000, 13875, 0x76, },
1443         { 10, 14875, 13750, 0x75, },
1444         { 11, 14750, 13625, 0x74, },
1445         { 12, 14625, 13500, 0x73, },
1446         { 13, 14500, 13375, 0x72, },
1447         { 14, 14375, 13250, 0x71, },
1448         { 15, 14250, 13125, 0x70, },
1449         { 16, 14125, 13000, 0x6f, },
1450         { 17, 14000, 12875, 0x6e, },
1451         { 18, 13875, 12750, 0x6d, },
1452         { 19, 13750, 12625, 0x6c, },
1453         { 20, 13625, 12500, 0x6b, },
1454         { 21, 13500, 12375, 0x6a, },
1455         { 22, 13375, 12250, 0x69, },
1456         { 23, 13250, 12125, 0x68, },
1457         { 24, 13125, 12000, 0x67, },
1458         { 25, 13000, 11875, 0x66, },
1459         { 26, 12875, 11750, 0x65, },
1460         { 27, 12750, 11625, 0x64, },
1461         { 28, 12625, 11500, 0x63, },
1462         { 29, 12500, 11375, 0x62, },
1463         { 30, 12375, 11250, 0x61, },
1464         { 31, 12250, 11125, 0x60, },
1465         { 32, 12125, 11000, 0x5f, },
1466         { 33, 12000, 10875, 0x5e, },
1467         { 34, 11875, 10750, 0x5d, },
1468         { 35, 11750, 10625, 0x5c, },
1469         { 36, 11625, 10500, 0x5b, },
1470         { 37, 11500, 10375, 0x5a, },
1471         { 38, 11375, 10250, 0x59, },
1472         { 39, 11250, 10125, 0x58, },
1473         { 40, 11125, 10000, 0x57, },
1474         { 41, 11000, 9875, 0x56, },
1475         { 42, 10875, 9750, 0x55, },
1476         { 43, 10750, 9625, 0x54, },
1477         { 44, 10625, 9500, 0x53, },
1478         { 45, 10500, 9375, 0x52, },
1479         { 46, 10375, 9250, 0x51, },
1480         { 47, 10250, 9125, 0x50, },
1481         { 48, 10125, 9000, 0x4f, },
1482         { 49, 10000, 8875, 0x4e, },
1483         { 50, 9875, 8750, 0x4d, },
1484         { 51, 9750, 8625, 0x4c, },
1485         { 52, 9625, 8500, 0x4b, },
1486         { 53, 9500, 8375, 0x4a, },
1487         { 54, 9375, 8250, 0x49, },
1488         { 55, 9250, 8125, 0x48, },
1489         { 56, 9125, 8000, 0x47, },
1490         { 57, 9000, 7875, 0x46, },
1491         { 58, 8875, 7750, 0x45, },
1492         { 59, 8750, 7625, 0x44, },
1493         { 60, 8625, 7500, 0x43, },
1494         { 61, 8500, 7375, 0x42, },
1495         { 62, 8375, 7250, 0x41, },
1496         { 63, 8250, 7125, 0x40, },
1497         { 64, 8125, 7000, 0x3f, },
1498         { 65, 8000, 6875, 0x3e, },
1499         { 66, 7875, 6750, 0x3d, },
1500         { 67, 7750, 6625, 0x3c, },
1501         { 68, 7625, 6500, 0x3b, },
1502         { 69, 7500, 6375, 0x3a, },
1503         { 70, 7375, 6250, 0x39, },
1504         { 71, 7250, 6125, 0x38, },
1505         { 72, 7125, 6000, 0x37, },
1506         { 73, 7000, 5875, 0x36, },
1507         { 74, 6875, 5750, 0x35, },
1508         { 75, 6750, 5625, 0x34, },
1509         { 76, 6625, 5500, 0x33, },
1510         { 77, 6500, 5375, 0x32, },
1511         { 78, 6375, 5250, 0x31, },
1512         { 79, 6250, 5125, 0x30, },
1513         { 80, 6125, 5000, 0x2f, },
1514         { 81, 6000, 4875, 0x2e, },
1515         { 82, 5875, 4750, 0x2d, },
1516         { 83, 5750, 4625, 0x2c, },
1517         { 84, 5625, 4500, 0x2b, },
1518         { 85, 5500, 4375, 0x2a, },
1519         { 86, 5375, 4250, 0x29, },
1520         { 87, 5250, 4125, 0x28, },
1521         { 88, 5125, 4000, 0x27, },
1522         { 89, 5000, 3875, 0x26, },
1523         { 90, 4875, 3750, 0x25, },
1524         { 91, 4750, 3625, 0x24, },
1525         { 92, 4625, 3500, 0x23, },
1526         { 93, 4500, 3375, 0x22, },
1527         { 94, 4375, 3250, 0x21, },
1528         { 95, 4250, 3125, 0x20, },
1529         { 96, 4125, 3000, 0x1f, },
1530         { 97, 4125, 3000, 0x1e, },
1531         { 98, 4125, 3000, 0x1d, },
1532         { 99, 4125, 3000, 0x1c, },
1533         { 100, 4125, 3000, 0x1b, },
1534         { 101, 4125, 3000, 0x1a, },
1535         { 102, 4125, 3000, 0x19, },
1536         { 103, 4125, 3000, 0x18, },
1537         { 104, 4125, 3000, 0x17, },
1538         { 105, 4125, 3000, 0x16, },
1539         { 106, 4125, 3000, 0x15, },
1540         { 107, 4125, 3000, 0x14, },
1541         { 108, 4125, 3000, 0x13, },
1542         { 109, 4125, 3000, 0x12, },
1543         { 110, 4125, 3000, 0x11, },
1544         { 111, 4125, 3000, 0x10, },
1545         { 112, 4125, 3000, 0x0f, },
1546         { 113, 4125, 3000, 0x0e, },
1547         { 114, 4125, 3000, 0x0d, },
1548         { 115, 4125, 3000, 0x0c, },
1549         { 116, 4125, 3000, 0x0b, },
1550         { 117, 4125, 3000, 0x0a, },
1551         { 118, 4125, 3000, 0x09, },
1552         { 119, 4125, 3000, 0x08, },
1553         { 120, 1125, 0, 0x07, },
1554         { 121, 1000, 0, 0x06, },
1555         { 122, 875, 0, 0x05, },
1556         { 123, 750, 0, 0x04, },
1557         { 124, 625, 0, 0x03, },
1558         { 125, 500, 0, 0x02, },
1559         { 126, 375, 0, 0x01, },
1560         { 127, 0, 0, 0x00, },
1561 };
1562
1563 struct cparams {
1564         int i;
1565         int t;
1566         int m;
1567         int c;
1568 };
1569
1570 static struct cparams cparams[] = {
1571         { 1, 1333, 301, 28664 },
1572         { 1, 1066, 294, 24460 },
1573         { 1, 800, 294, 25192 },
1574         { 0, 1333, 276, 27605 },
1575         { 0, 1066, 276, 27605 },
1576         { 0, 800, 231, 23784 },
1577 };
1578
1579 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1580 {
1581         u64 total_count, diff, ret;
1582         u32 count1, count2, count3, m = 0, c = 0;
1583         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1584         int i;
1585
1586         diff1 = now - dev_priv->last_time1;
1587
1588         count1 = I915_READ(DMIEC);
1589         count2 = I915_READ(DDREC);
1590         count3 = I915_READ(CSIEC);
1591
1592         total_count = count1 + count2 + count3;
1593
1594         /* FIXME: handle per-counter overflow */
1595         if (total_count < dev_priv->last_count1) {
1596                 diff = ~0UL - dev_priv->last_count1;
1597                 diff += total_count;
1598         } else {
1599                 diff = total_count - dev_priv->last_count1;
1600         }
1601
1602         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1603                 if (cparams[i].i == dev_priv->c_m &&
1604                     cparams[i].t == dev_priv->r_t) {
1605                         m = cparams[i].m;
1606                         c = cparams[i].c;
1607                         break;
1608                 }
1609         }
1610
1611         diff = div_u64(diff, diff1);
1612         ret = ((m * diff) + c);
1613         ret = div_u64(ret, 10);
1614
1615         dev_priv->last_count1 = total_count;
1616         dev_priv->last_time1 = now;
1617
1618         return ret;
1619 }
1620
1621 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1622 {
1623         unsigned long m, x, b;
1624         u32 tsfs;
1625
1626         tsfs = I915_READ(TSFS);
1627
1628         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1629         x = I915_READ8(TR1);
1630
1631         b = tsfs & TSFS_INTR_MASK;
1632
1633         return ((m * x) / 127) - b;
1634 }
1635
1636 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1637 {
1638         unsigned long val = 0;
1639         int i;
1640
1641         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1642                 if (v_table[i].pvid == pxvid) {
1643                         if (IS_MOBILE(dev_priv->dev))
1644                                 val = v_table[i].vm;
1645                         else
1646                                 val = v_table[i].vd;
1647                 }
1648         }
1649
1650         return val;
1651 }
1652
1653 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1654 {
1655         struct timespec now, diff1;
1656         u64 diff;
1657         unsigned long diffms;
1658         u32 count;
1659
1660         getrawmonotonic(&now);
1661         diff1 = timespec_sub(now, dev_priv->last_time2);
1662
1663         /* Don't divide by 0 */
1664         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1665         if (!diffms)
1666                 return;
1667
1668         count = I915_READ(GFXEC);
1669
1670         if (count < dev_priv->last_count2) {
1671                 diff = ~0UL - dev_priv->last_count2;
1672                 diff += count;
1673         } else {
1674                 diff = count - dev_priv->last_count2;
1675         }
1676
1677         dev_priv->last_count2 = count;
1678         dev_priv->last_time2 = now;
1679
1680         /* More magic constants... */
1681         diff = diff * 1181;
1682         diff = div_u64(diff, diffms * 10);
1683         dev_priv->gfx_power = diff;
1684 }
1685
1686 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1687 {
1688         unsigned long t, corr, state1, corr2, state2;
1689         u32 pxvid, ext_v;
1690
1691         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1692         pxvid = (pxvid >> 24) & 0x7f;
1693         ext_v = pvid_to_extvid(dev_priv, pxvid);
1694
1695         state1 = ext_v;
1696
1697         t = i915_mch_val(dev_priv);
1698
1699         /* Revel in the empirically derived constants */
1700
1701         /* Correction factor in 1/100000 units */
1702         if (t > 80)
1703                 corr = ((t * 2349) + 135940);
1704         else if (t >= 50)
1705                 corr = ((t * 964) + 29317);
1706         else /* < 50 */
1707                 corr = ((t * 301) + 1004);
1708
1709         corr = corr * ((150142 * state1) / 10000 - 78642);
1710         corr /= 100000;
1711         corr2 = (corr * dev_priv->corr);
1712
1713         state2 = (corr2 * state1) / 10000;
1714         state2 /= 100; /* convert to mW */
1715
1716         i915_update_gfx_val(dev_priv);
1717
1718         return dev_priv->gfx_power + state2;
1719 }
1720
1721 /* Global for IPS driver to get at the current i915 device */
1722 static struct drm_i915_private *i915_mch_dev;
1723 /*
1724  * Lock protecting IPS related data structures
1725  *   - i915_mch_dev
1726  *   - dev_priv->max_delay
1727  *   - dev_priv->min_delay
1728  *   - dev_priv->fmax
1729  *   - dev_priv->gpu_busy
1730  */
1731 static DEFINE_SPINLOCK(mchdev_lock);
1732
1733 /**
1734  * i915_read_mch_val - return value for IPS use
1735  *
1736  * Calculate and return a value for the IPS driver to use when deciding whether
1737  * we have thermal and power headroom to increase CPU or GPU power budget.
1738  */
1739 unsigned long i915_read_mch_val(void)
1740 {
1741         struct drm_i915_private *dev_priv;
1742         unsigned long chipset_val, graphics_val, ret = 0;
1743
1744         spin_lock(&mchdev_lock);
1745         if (!i915_mch_dev)
1746                 goto out_unlock;
1747         dev_priv = i915_mch_dev;
1748
1749         chipset_val = i915_chipset_val(dev_priv);
1750         graphics_val = i915_gfx_val(dev_priv);
1751
1752         ret = chipset_val + graphics_val;
1753
1754 out_unlock:
1755         spin_unlock(&mchdev_lock);
1756
1757         return ret;
1758 }
1759 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1760
1761 /**
1762  * i915_gpu_raise - raise GPU frequency limit
1763  *
1764  * Raise the limit; IPS indicates we have thermal headroom.
1765  */
1766 bool i915_gpu_raise(void)
1767 {
1768         struct drm_i915_private *dev_priv;
1769         bool ret = true;
1770
1771         spin_lock(&mchdev_lock);
1772         if (!i915_mch_dev) {
1773                 ret = false;
1774                 goto out_unlock;
1775         }
1776         dev_priv = i915_mch_dev;
1777
1778         if (dev_priv->max_delay > dev_priv->fmax)
1779                 dev_priv->max_delay--;
1780
1781 out_unlock:
1782         spin_unlock(&mchdev_lock);
1783
1784         return ret;
1785 }
1786 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1787
1788 /**
1789  * i915_gpu_lower - lower GPU frequency limit
1790  *
1791  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1792  * frequency maximum.
1793  */
1794 bool i915_gpu_lower(void)
1795 {
1796         struct drm_i915_private *dev_priv;
1797         bool ret = true;
1798
1799         spin_lock(&mchdev_lock);
1800         if (!i915_mch_dev) {
1801                 ret = false;
1802                 goto out_unlock;
1803         }
1804         dev_priv = i915_mch_dev;
1805
1806         if (dev_priv->max_delay < dev_priv->min_delay)
1807                 dev_priv->max_delay++;
1808
1809 out_unlock:
1810         spin_unlock(&mchdev_lock);
1811
1812         return ret;
1813 }
1814 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1815
1816 /**
1817  * i915_gpu_busy - indicate GPU business to IPS
1818  *
1819  * Tell the IPS driver whether or not the GPU is busy.
1820  */
1821 bool i915_gpu_busy(void)
1822 {
1823         struct drm_i915_private *dev_priv;
1824         bool ret = false;
1825
1826         spin_lock(&mchdev_lock);
1827         if (!i915_mch_dev)
1828                 goto out_unlock;
1829         dev_priv = i915_mch_dev;
1830
1831         ret = dev_priv->busy;
1832
1833 out_unlock:
1834         spin_unlock(&mchdev_lock);
1835
1836         return ret;
1837 }
1838 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1839
1840 /**
1841  * i915_gpu_turbo_disable - disable graphics turbo
1842  *
1843  * Disable graphics turbo by resetting the max frequency and setting the
1844  * current frequency to the default.
1845  */
1846 bool i915_gpu_turbo_disable(void)
1847 {
1848         struct drm_i915_private *dev_priv;
1849         bool ret = true;
1850
1851         spin_lock(&mchdev_lock);
1852         if (!i915_mch_dev) {
1853                 ret = false;
1854                 goto out_unlock;
1855         }
1856         dev_priv = i915_mch_dev;
1857
1858         dev_priv->max_delay = dev_priv->fstart;
1859
1860         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1861                 ret = false;
1862
1863 out_unlock:
1864         spin_unlock(&mchdev_lock);
1865
1866         return ret;
1867 }
1868 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1869
1870 /**
1871  * i915_driver_load - setup chip and create an initial config
1872  * @dev: DRM device
1873  * @flags: startup flags
1874  *
1875  * The driver load routine has to do several things:
1876  *   - drive output discovery via intel_modeset_init()
1877  *   - initialize the memory manager
1878  *   - allocate initial config memory
1879  *   - setup the DRM framebuffer with the allocated memory
1880  */
1881 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1882 {
1883         struct drm_i915_private *dev_priv;
1884         resource_size_t base, size;
1885         int ret = 0, mmio_bar;
1886         uint32_t agp_size, prealloc_size;
1887         /* i915 has 4 more counters */
1888         dev->counters += 4;
1889         dev->types[6] = _DRM_STAT_IRQ;
1890         dev->types[7] = _DRM_STAT_PRIMARY;
1891         dev->types[8] = _DRM_STAT_SECONDARY;
1892         dev->types[9] = _DRM_STAT_DMA;
1893
1894         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1895         if (dev_priv == NULL)
1896                 return -ENOMEM;
1897
1898         dev->dev_private = (void *)dev_priv;
1899         dev_priv->dev = dev;
1900         dev_priv->info = (struct intel_device_info *) flags;
1901
1902         /* Add register map (needed for suspend/resume) */
1903         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1904         base = pci_resource_start(dev->pdev, mmio_bar);
1905         size = pci_resource_len(dev->pdev, mmio_bar);
1906
1907         if (i915_get_bridge_dev(dev)) {
1908                 ret = -EIO;
1909                 goto free_priv;
1910         }
1911
1912         /* overlay on gen2 is broken and can't address above 1G */
1913         if (IS_GEN2(dev))
1914                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1915
1916         dev_priv->regs = ioremap(base, size);
1917         if (!dev_priv->regs) {
1918                 DRM_ERROR("failed to map registers\n");
1919                 ret = -EIO;
1920                 goto put_bridge;
1921         }
1922
1923         dev_priv->mm.gtt_mapping =
1924                 io_mapping_create_wc(dev->agp->base,
1925                                      dev->agp->agp_info.aper_size * 1024*1024);
1926         if (dev_priv->mm.gtt_mapping == NULL) {
1927                 ret = -EIO;
1928                 goto out_rmmap;
1929         }
1930
1931         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1932          * one would think, because the kernel disables PAT on first
1933          * generation Core chips because WC PAT gets overridden by a UC
1934          * MTRR if present.  Even if a UC MTRR isn't present.
1935          */
1936         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1937                                          dev->agp->agp_info.aper_size *
1938                                          1024 * 1024,
1939                                          MTRR_TYPE_WRCOMB, 1);
1940         if (dev_priv->mm.gtt_mtrr < 0) {
1941                 DRM_INFO("MTRR allocation failed.  Graphics "
1942                          "performance may suffer.\n");
1943         }
1944
1945         dev_priv->mm.gtt = intel_gtt_get();
1946         if (!dev_priv->mm.gtt) {
1947                 DRM_ERROR("Failed to initialize GTT\n");
1948                 ret = -ENODEV;
1949                 goto out_iomapfree;
1950         }
1951
1952         prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
1953         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1954
1955         /* The i915 workqueue is primarily used for batched retirement of
1956          * requests (and thus managing bo) once the task has been completed
1957          * by the GPU. i915_gem_retire_requests() is called directly when we
1958          * need high-priority retirement, such as waiting for an explicit
1959          * bo.
1960          *
1961          * It is also used for periodic low-priority events, such as
1962          * idle-timers and hangcheck.
1963          *
1964          * All tasks on the workqueue are expected to acquire the dev mutex
1965          * so there is no point in running more than one instance of the
1966          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1967          */
1968         dev_priv->wq = alloc_workqueue("i915",
1969                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1970                                        1);
1971         if (dev_priv->wq == NULL) {
1972                 DRM_ERROR("Failed to create our workqueue.\n");
1973                 ret = -ENOMEM;
1974                 goto out_iomapfree;
1975         }
1976
1977         /* enable GEM by default */
1978         dev_priv->has_gem = 1;
1979
1980         if (prealloc_size > agp_size * 3 / 4) {
1981                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1982                           "memory stolen.\n",
1983                           prealloc_size / 1024, agp_size / 1024);
1984                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1985                           "updating the BIOS to fix).\n");
1986                 dev_priv->has_gem = 0;
1987         }
1988
1989         if (dev_priv->has_gem == 0 &&
1990             drm_core_check_feature(dev, DRIVER_MODESET)) {
1991                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1992                 ret = -ENODEV;
1993                 goto out_iomapfree;
1994         }
1995
1996         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1997         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1998         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1999                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2000                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2001         }
2002
2003         /* Try to make sure MCHBAR is enabled before poking at it */
2004         intel_setup_mchbar(dev);
2005         intel_setup_gmbus(dev);
2006         intel_opregion_setup(dev);
2007
2008         /* Make sure the bios did its job and set up vital registers */
2009         intel_setup_bios(dev);
2010
2011         i915_gem_load(dev);
2012
2013         /* Init HWS */
2014         if (!I915_NEED_GFX_HWS(dev)) {
2015                 ret = i915_init_phys_hws(dev);
2016                 if (ret != 0)
2017                         goto out_workqueue_free;
2018         }
2019
2020         if (IS_PINEVIEW(dev))
2021                 i915_pineview_get_mem_freq(dev);
2022         else if (IS_GEN5(dev))
2023                 i915_ironlake_get_mem_freq(dev);
2024
2025         /* On the 945G/GM, the chipset reports the MSI capability on the
2026          * integrated graphics even though the support isn't actually there
2027          * according to the published specs.  It doesn't appear to function
2028          * correctly in testing on 945G.
2029          * This may be a side effect of MSI having been made available for PEG
2030          * and the registers being closely associated.
2031          *
2032          * According to chipset errata, on the 965GM, MSI interrupts may
2033          * be lost or delayed, but we use them anyways to avoid
2034          * stuck interrupts on some machines.
2035          */
2036         if (!IS_I945G(dev) && !IS_I945GM(dev))
2037                 pci_enable_msi(dev->pdev);
2038
2039         spin_lock_init(&dev_priv->user_irq_lock);
2040         spin_lock_init(&dev_priv->error_lock);
2041         dev_priv->trace_irq_seqno = 0;
2042
2043         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2044
2045         if (ret) {
2046                 (void) i915_driver_unload(dev);
2047                 return ret;
2048         }
2049
2050         /* Start out suspended */
2051         dev_priv->mm.suspended = 1;
2052
2053         intel_detect_pch(dev);
2054
2055         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2056                 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
2057                 if (ret < 0) {
2058                         DRM_ERROR("failed to init modeset\n");
2059                         goto out_workqueue_free;
2060                 }
2061         }
2062
2063         /* Must be done after probing outputs */
2064         intel_opregion_init(dev);
2065         acpi_video_register();
2066
2067         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2068                     (unsigned long) dev);
2069
2070         spin_lock(&mchdev_lock);
2071         i915_mch_dev = dev_priv;
2072         dev_priv->mchdev_lock = &mchdev_lock;
2073         spin_unlock(&mchdev_lock);
2074
2075         return 0;
2076
2077 out_workqueue_free:
2078         destroy_workqueue(dev_priv->wq);
2079 out_iomapfree:
2080         io_mapping_free(dev_priv->mm.gtt_mapping);
2081 out_rmmap:
2082         iounmap(dev_priv->regs);
2083 put_bridge:
2084         pci_dev_put(dev_priv->bridge_dev);
2085 free_priv:
2086         kfree(dev_priv);
2087         return ret;
2088 }
2089
2090 int i915_driver_unload(struct drm_device *dev)
2091 {
2092         struct drm_i915_private *dev_priv = dev->dev_private;
2093         int ret;
2094
2095         spin_lock(&mchdev_lock);
2096         i915_mch_dev = NULL;
2097         spin_unlock(&mchdev_lock);
2098
2099         mutex_lock(&dev->struct_mutex);
2100         ret = i915_gpu_idle(dev);
2101         if (ret)
2102                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2103         mutex_unlock(&dev->struct_mutex);
2104
2105         /* Cancel the retire work handler, which should be idle now. */
2106         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2107
2108         io_mapping_free(dev_priv->mm.gtt_mapping);
2109         if (dev_priv->mm.gtt_mtrr >= 0) {
2110                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2111                          dev->agp->agp_info.aper_size * 1024 * 1024);
2112                 dev_priv->mm.gtt_mtrr = -1;
2113         }
2114
2115         acpi_video_unregister();
2116
2117         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2118                 intel_fbdev_fini(dev);
2119                 intel_modeset_cleanup(dev);
2120
2121                 /*
2122                  * free the memory space allocated for the child device
2123                  * config parsed from VBT
2124                  */
2125                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2126                         kfree(dev_priv->child_dev);
2127                         dev_priv->child_dev = NULL;
2128                         dev_priv->child_dev_num = 0;
2129                 }
2130
2131                 vga_switcheroo_unregister_client(dev->pdev);
2132                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2133         }
2134
2135         /* Free error state after interrupts are fully disabled. */
2136         del_timer_sync(&dev_priv->hangcheck_timer);
2137         cancel_work_sync(&dev_priv->error_work);
2138         i915_destroy_error_state(dev);
2139
2140         if (dev->pdev->msi_enabled)
2141                 pci_disable_msi(dev->pdev);
2142
2143         intel_opregion_fini(dev);
2144
2145         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2146                 /* Flush any outstanding unpin_work. */
2147                 flush_workqueue(dev_priv->wq);
2148
2149                 i915_gem_free_all_phys_object(dev);
2150
2151                 mutex_lock(&dev->struct_mutex);
2152                 i915_gem_cleanup_ringbuffer(dev);
2153                 mutex_unlock(&dev->struct_mutex);
2154                 if (I915_HAS_FBC(dev) && i915_powersave)
2155                         i915_cleanup_compression(dev);
2156                 drm_mm_takedown(&dev_priv->mm.vram);
2157
2158                 intel_cleanup_overlay(dev);
2159
2160                 if (!I915_NEED_GFX_HWS(dev))
2161                         i915_free_hws(dev);
2162         }
2163
2164         if (dev_priv->regs != NULL)
2165                 iounmap(dev_priv->regs);
2166
2167         intel_teardown_gmbus(dev);
2168         intel_teardown_mchbar(dev);
2169
2170         destroy_workqueue(dev_priv->wq);
2171
2172         pci_dev_put(dev_priv->bridge_dev);
2173         kfree(dev->dev_private);
2174
2175         return 0;
2176 }
2177
2178 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2179 {
2180         struct drm_i915_file_private *file_priv;
2181
2182         DRM_DEBUG_DRIVER("\n");
2183         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2184         if (!file_priv)
2185                 return -ENOMEM;
2186
2187         file->driver_priv = file_priv;
2188
2189         spin_lock_init(&file_priv->mm.lock);
2190         INIT_LIST_HEAD(&file_priv->mm.request_list);
2191
2192         return 0;
2193 }
2194
2195 /**
2196  * i915_driver_lastclose - clean up after all DRM clients have exited
2197  * @dev: DRM device
2198  *
2199  * Take care of cleaning up after all DRM clients have exited.  In the
2200  * mode setting case, we want to restore the kernel's initial mode (just
2201  * in case the last client left us in a bad state).
2202  *
2203  * Additionally, in the non-mode setting case, we'll tear down the AGP
2204  * and DMA structures, since the kernel won't be using them, and clea
2205  * up any GEM state.
2206  */
2207 void i915_driver_lastclose(struct drm_device * dev)
2208 {
2209         drm_i915_private_t *dev_priv = dev->dev_private;
2210
2211         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2212                 drm_fb_helper_restore();
2213                 vga_switcheroo_process_delayed_switch();
2214                 return;
2215         }
2216
2217         i915_gem_lastclose(dev);
2218
2219         if (dev_priv->agp_heap)
2220                 i915_mem_takedown(&(dev_priv->agp_heap));
2221
2222         i915_dma_cleanup(dev);
2223 }
2224
2225 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2226 {
2227         drm_i915_private_t *dev_priv = dev->dev_private;
2228         i915_gem_release(dev, file_priv);
2229         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2230                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2231 }
2232
2233 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2234 {
2235         struct drm_i915_file_private *file_priv = file->driver_priv;
2236
2237         kfree(file_priv);
2238 }
2239
2240 struct drm_ioctl_desc i915_ioctls[] = {
2241         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2242         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2243         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2244         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2245         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2246         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2247         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2248         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2249         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2250         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2251         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2252         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2253         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2254         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2255         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2256         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2257         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2258         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2259         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2260         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2261         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2262         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2263         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2264         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2265         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2266         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2267         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2268         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2269         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2270         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2271         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2272         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2273         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2274         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2275         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2276         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2277         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2278         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2279         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2280         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2281 };
2282
2283 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2284
2285 /**
2286  * Determine if the device really is AGP or not.
2287  *
2288  * All Intel graphics chipsets are treated as AGP, even if they are really
2289  * PCI-e.
2290  *
2291  * \param dev   The device to be tested.
2292  *
2293  * \returns
2294  * A value of 1 is always retured to indictate every i9x5 is AGP.
2295  */
2296 int i915_driver_device_is_agp(struct drm_device * dev)
2297 {
2298         return 1;
2299 }