2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
47 #include <asm/byteorder.h>
49 #include <asm/system.h>
51 #ifdef CONFIG_PPC_PMAC
52 #include <asm/pmac_feature.h>
58 #define DESCRIPTOR_OUTPUT_MORE 0
59 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
60 #define DESCRIPTOR_INPUT_MORE (2 << 12)
61 #define DESCRIPTOR_INPUT_LAST (3 << 12)
62 #define DESCRIPTOR_STATUS (1 << 11)
63 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
64 #define DESCRIPTOR_PING (1 << 7)
65 #define DESCRIPTOR_YY (1 << 6)
66 #define DESCRIPTOR_NO_IRQ (0 << 4)
67 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
68 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
69 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
70 #define DESCRIPTOR_WAIT (3 << 0)
76 __le32 branch_address;
78 __le16 transfer_status;
79 } __attribute__((aligned(16)));
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
86 #define AR_BUFFER_SIZE (32*1024)
87 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
88 /* we need at least two pages for proper list management */
89 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
91 #define MAX_ASYNC_PAYLOAD 4096
92 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
93 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
97 struct page *pages[AR_BUFFERS];
99 struct descriptor *descriptors;
100 dma_addr_t descriptors_bus;
102 unsigned int last_buffer_index;
104 struct tasklet_struct tasklet;
109 typedef int (*descriptor_callback_t)(struct context *ctx,
110 struct descriptor *d,
111 struct descriptor *last);
114 * A buffer that contains a block of DMA-able coherent memory used for
115 * storing a portion of a DMA descriptor program.
117 struct descriptor_buffer {
118 struct list_head list;
119 dma_addr_t buffer_bus;
122 struct descriptor buffer[0];
126 struct fw_ohci *ohci;
128 int total_allocation;
133 * List of page-sized buffers for storing DMA descriptors.
134 * Head of list contains buffers in use and tail of list contains
137 struct list_head buffer_list;
140 * Pointer to a buffer inside buffer_list that contains the tail
141 * end of the current DMA program.
143 struct descriptor_buffer *buffer_tail;
146 * The descriptor containing the branch address of the first
147 * descriptor that has not yet been filled by the device.
149 struct descriptor *last;
152 * The last descriptor in the DMA program. It contains the branch
153 * address that must be updated upon appending a new descriptor.
155 struct descriptor *prev;
157 descriptor_callback_t callback;
159 struct tasklet_struct tasklet;
162 #define IT_HEADER_SY(v) ((v) << 0)
163 #define IT_HEADER_TCODE(v) ((v) << 4)
164 #define IT_HEADER_CHANNEL(v) ((v) << 8)
165 #define IT_HEADER_TAG(v) ((v) << 14)
166 #define IT_HEADER_SPEED(v) ((v) << 16)
167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
170 struct fw_iso_context base;
171 struct context context;
174 size_t header_length;
180 #define CONFIG_ROM_SIZE 1024
185 __iomem char *registers;
188 int request_generation; /* for timestamping incoming requests */
190 unsigned int pri_req_max;
193 bool csr_state_setclear_abdicate;
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
202 struct mutex phy_reg_mutex;
205 dma_addr_t misc_buffer_bus;
207 struct ar_context ar_request_ctx;
208 struct ar_context ar_response_ctx;
209 struct context at_request_ctx;
210 struct context at_response_ctx;
212 u32 it_context_support;
213 u32 it_context_mask; /* unoccupied IT contexts */
214 struct iso_context *it_context_list;
215 u64 ir_context_channels; /* unoccupied channels */
216 u32 ir_context_support;
217 u32 ir_context_mask; /* unoccupied IR contexts */
218 struct iso_context *ir_context_list;
219 u64 mc_channels; /* channels in use by the multichannel IR context */
223 dma_addr_t config_rom_bus;
224 __be32 *next_config_rom;
225 dma_addr_t next_config_rom_bus;
229 dma_addr_t self_id_bus;
230 struct work_struct bus_reset_work;
232 u32 self_id_buffer[512];
235 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
237 return container_of(card, struct fw_ohci, card);
240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
241 #define IR_CONTEXT_BUFFER_FILL 0x80000000
242 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
244 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
245 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
247 #define CONTEXT_RUN 0x8000
248 #define CONTEXT_WAKE 0x1000
249 #define CONTEXT_DEAD 0x0800
250 #define CONTEXT_ACTIVE 0x0400
252 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
253 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
254 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
256 #define OHCI1394_REGISTER_SIZE 0x800
257 #define OHCI1394_PCI_HCI_Control 0x40
258 #define SELF_ID_BUF_SIZE 0x800
259 #define OHCI_TCODE_PHY_PACKET 0x0e
260 #define OHCI_VERSION_1_1 0x010010
262 static char ohci_driver_name[] = KBUILD_MODNAME;
264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
266 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
267 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
268 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
269 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
271 #define QUIRK_CYCLE_TIMER 1
272 #define QUIRK_RESET_PACKET 2
273 #define QUIRK_BE_HEADERS 4
274 #define QUIRK_NO_1394A 8
275 #define QUIRK_NO_MSI 16
276 #define QUIRK_TI_SLLZ059 32
278 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
279 static const struct {
280 unsigned short vendor, device, revision, flags;
282 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
285 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
288 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
291 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
294 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
297 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
300 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
303 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
304 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
306 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
307 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
309 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
310 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
312 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
315 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
316 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
319 /* This overrides anything that was found in ohci_quirks[]. */
320 static int param_quirks;
321 module_param_named(quirks, param_quirks, int, 0644);
322 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
323 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
324 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
325 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
326 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
327 ", disable MSI = " __stringify(QUIRK_NO_MSI)
328 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
331 #define OHCI_PARAM_DEBUG_AT_AR 1
332 #define OHCI_PARAM_DEBUG_SELFIDS 2
333 #define OHCI_PARAM_DEBUG_IRQS 4
334 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
336 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
338 static int param_debug;
339 module_param_named(debug, param_debug, int, 0644);
340 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
341 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
342 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
343 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
344 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
345 ", or a combination, or all = -1)");
347 static void log_irqs(u32 evt)
349 if (likely(!(param_debug &
350 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
353 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
354 !(evt & OHCI1394_busReset))
357 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
358 evt & OHCI1394_selfIDComplete ? " selfID" : "",
359 evt & OHCI1394_RQPkt ? " AR_req" : "",
360 evt & OHCI1394_RSPkt ? " AR_resp" : "",
361 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
362 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
363 evt & OHCI1394_isochRx ? " IR" : "",
364 evt & OHCI1394_isochTx ? " IT" : "",
365 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
366 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
367 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
368 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
369 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
370 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
371 evt & OHCI1394_busReset ? " busReset" : "",
372 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
373 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
374 OHCI1394_respTxComplete | OHCI1394_isochRx |
375 OHCI1394_isochTx | OHCI1394_postedWriteErr |
376 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
377 OHCI1394_cycleInconsistent |
378 OHCI1394_regAccessFail | OHCI1394_busReset)
382 static const char *speed[] = {
383 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
385 static const char *power[] = {
386 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
387 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
389 static const char port[] = { '.', '-', 'p', 'c', };
391 static char _p(u32 *s, int shift)
393 return port[*s >> shift & 3];
396 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
398 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
401 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
402 self_id_count, generation, node_id);
404 for (; self_id_count--; ++s)
405 if ((*s & 1 << 23) == 0)
406 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
407 "%s gc=%d %s %s%s%s\n",
408 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
409 speed[*s >> 14 & 3], *s >> 16 & 63,
410 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
411 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
413 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
415 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
416 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
419 static const char *evts[] = {
420 [0x00] = "evt_no_status", [0x01] = "-reserved-",
421 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
422 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
423 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
424 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
425 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
426 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
427 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
428 [0x10] = "-reserved-", [0x11] = "ack_complete",
429 [0x12] = "ack_pending ", [0x13] = "-reserved-",
430 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
431 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
432 [0x18] = "-reserved-", [0x19] = "-reserved-",
433 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
434 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
435 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
436 [0x20] = "pending/cancelled",
438 static const char *tcodes[] = {
439 [0x0] = "QW req", [0x1] = "BW req",
440 [0x2] = "W resp", [0x3] = "-reserved-",
441 [0x4] = "QR req", [0x5] = "BR req",
442 [0x6] = "QR resp", [0x7] = "BR resp",
443 [0x8] = "cycle start", [0x9] = "Lk req",
444 [0xa] = "async stream packet", [0xb] = "Lk resp",
445 [0xc] = "-reserved-", [0xd] = "-reserved-",
446 [0xe] = "link internal", [0xf] = "-reserved-",
449 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
451 int tcode = header[0] >> 4 & 0xf;
454 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
457 if (unlikely(evt >= ARRAY_SIZE(evts)))
460 if (evt == OHCI1394_evt_bus_reset) {
461 fw_notify("A%c evt_bus_reset, generation %d\n",
462 dir, (header[2] >> 16) & 0xff);
467 case 0x0: case 0x6: case 0x8:
468 snprintf(specific, sizeof(specific), " = %08x",
469 be32_to_cpu((__force __be32)header[3]));
471 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
472 snprintf(specific, sizeof(specific), " %x,%x",
473 header[3] >> 16, header[3] & 0xffff);
481 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
484 fw_notify("A%c %s, PHY %08x %08x\n",
485 dir, evts[evt], header[1], header[2]);
487 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
488 fw_notify("A%c spd %x tl %02x, "
491 dir, speed, header[0] >> 10 & 0x3f,
492 header[1] >> 16, header[0] >> 16, evts[evt],
493 tcodes[tcode], header[1] & 0xffff, header[2], specific);
496 fw_notify("A%c spd %x tl %02x, "
499 dir, speed, header[0] >> 10 & 0x3f,
500 header[1] >> 16, header[0] >> 16, evts[evt],
501 tcodes[tcode], specific);
507 #define param_debug 0
508 static inline void log_irqs(u32 evt) {}
509 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
510 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
512 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
514 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
516 writel(data, ohci->registers + offset);
519 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
521 return readl(ohci->registers + offset);
524 static inline void flush_writes(const struct fw_ohci *ohci)
526 /* Do a dummy read to flush writes. */
527 reg_read(ohci, OHCI1394_Version);
531 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
532 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
533 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
534 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
536 static int read_phy_reg(struct fw_ohci *ohci, int addr)
541 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
542 for (i = 0; i < 3 + 100; i++) {
543 val = reg_read(ohci, OHCI1394_PhyControl);
545 return -ENODEV; /* Card was ejected. */
547 if (val & OHCI1394_PhyControl_ReadDone)
548 return OHCI1394_PhyControl_ReadData(val);
551 * Try a few times without waiting. Sleeping is necessary
552 * only when the link/PHY interface is busy.
557 fw_error("failed to read phy reg\n");
562 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
566 reg_write(ohci, OHCI1394_PhyControl,
567 OHCI1394_PhyControl_Write(addr, val));
568 for (i = 0; i < 3 + 100; i++) {
569 val = reg_read(ohci, OHCI1394_PhyControl);
571 return -ENODEV; /* Card was ejected. */
573 if (!(val & OHCI1394_PhyControl_WritePending))
579 fw_error("failed to write phy reg\n");
584 static int update_phy_reg(struct fw_ohci *ohci, int addr,
585 int clear_bits, int set_bits)
587 int ret = read_phy_reg(ohci, addr);
592 * The interrupt status bits are cleared by writing a one bit.
593 * Avoid clearing them unless explicitly requested in set_bits.
596 clear_bits |= PHY_INT_STATUS_BITS;
598 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
601 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
605 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
609 return read_phy_reg(ohci, addr);
612 static int ohci_read_phy_reg(struct fw_card *card, int addr)
614 struct fw_ohci *ohci = fw_ohci(card);
617 mutex_lock(&ohci->phy_reg_mutex);
618 ret = read_phy_reg(ohci, addr);
619 mutex_unlock(&ohci->phy_reg_mutex);
624 static int ohci_update_phy_reg(struct fw_card *card, int addr,
625 int clear_bits, int set_bits)
627 struct fw_ohci *ohci = fw_ohci(card);
630 mutex_lock(&ohci->phy_reg_mutex);
631 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
632 mutex_unlock(&ohci->phy_reg_mutex);
637 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
639 return page_private(ctx->pages[i]);
642 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
644 struct descriptor *d;
646 d = &ctx->descriptors[index];
647 d->branch_address &= cpu_to_le32(~0xf);
648 d->res_count = cpu_to_le16(PAGE_SIZE);
649 d->transfer_status = 0;
651 wmb(); /* finish init of new descriptors before branch_address update */
652 d = &ctx->descriptors[ctx->last_buffer_index];
653 d->branch_address |= cpu_to_le32(1);
655 ctx->last_buffer_index = index;
657 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
660 static void ar_context_release(struct ar_context *ctx)
665 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
667 for (i = 0; i < AR_BUFFERS; i++)
669 dma_unmap_page(ctx->ohci->card.device,
670 ar_buffer_bus(ctx, i),
671 PAGE_SIZE, DMA_FROM_DEVICE);
672 __free_page(ctx->pages[i]);
676 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
678 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
679 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
680 flush_writes(ctx->ohci);
682 fw_error("AR error: %s; DMA stopped\n", error_msg);
684 /* FIXME: restart? */
687 static inline unsigned int ar_next_buffer_index(unsigned int index)
689 return (index + 1) % AR_BUFFERS;
692 static inline unsigned int ar_prev_buffer_index(unsigned int index)
694 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
697 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
699 return ar_next_buffer_index(ctx->last_buffer_index);
703 * We search for the buffer that contains the last AR packet DMA data written
706 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
707 unsigned int *buffer_offset)
709 unsigned int i, next_i, last = ctx->last_buffer_index;
710 __le16 res_count, next_res_count;
712 i = ar_first_buffer_index(ctx);
713 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
715 /* A buffer that is not yet completely filled must be the last one. */
716 while (i != last && res_count == 0) {
718 /* Peek at the next descriptor. */
719 next_i = ar_next_buffer_index(i);
720 rmb(); /* read descriptors in order */
721 next_res_count = ACCESS_ONCE(
722 ctx->descriptors[next_i].res_count);
724 * If the next descriptor is still empty, we must stop at this
727 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
729 * The exception is when the DMA data for one packet is
730 * split over three buffers; in this case, the middle
731 * buffer's descriptor might be never updated by the
732 * controller and look still empty, and we have to peek
735 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
736 next_i = ar_next_buffer_index(next_i);
738 next_res_count = ACCESS_ONCE(
739 ctx->descriptors[next_i].res_count);
740 if (next_res_count != cpu_to_le16(PAGE_SIZE))
741 goto next_buffer_is_active;
747 next_buffer_is_active:
749 res_count = next_res_count;
752 rmb(); /* read res_count before the DMA data */
754 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
755 if (*buffer_offset > PAGE_SIZE) {
757 ar_context_abort(ctx, "corrupted descriptor");
763 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
764 unsigned int end_buffer_index,
765 unsigned int end_buffer_offset)
769 i = ar_first_buffer_index(ctx);
770 while (i != end_buffer_index) {
771 dma_sync_single_for_cpu(ctx->ohci->card.device,
772 ar_buffer_bus(ctx, i),
773 PAGE_SIZE, DMA_FROM_DEVICE);
774 i = ar_next_buffer_index(i);
776 if (end_buffer_offset > 0)
777 dma_sync_single_for_cpu(ctx->ohci->card.device,
778 ar_buffer_bus(ctx, i),
779 end_buffer_offset, DMA_FROM_DEVICE);
782 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
783 #define cond_le32_to_cpu(v) \
784 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
786 #define cond_le32_to_cpu(v) le32_to_cpu(v)
789 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
791 struct fw_ohci *ohci = ctx->ohci;
793 u32 status, length, tcode;
796 p.header[0] = cond_le32_to_cpu(buffer[0]);
797 p.header[1] = cond_le32_to_cpu(buffer[1]);
798 p.header[2] = cond_le32_to_cpu(buffer[2]);
800 tcode = (p.header[0] >> 4) & 0x0f;
802 case TCODE_WRITE_QUADLET_REQUEST:
803 case TCODE_READ_QUADLET_RESPONSE:
804 p.header[3] = (__force __u32) buffer[3];
805 p.header_length = 16;
806 p.payload_length = 0;
809 case TCODE_READ_BLOCK_REQUEST :
810 p.header[3] = cond_le32_to_cpu(buffer[3]);
811 p.header_length = 16;
812 p.payload_length = 0;
815 case TCODE_WRITE_BLOCK_REQUEST:
816 case TCODE_READ_BLOCK_RESPONSE:
817 case TCODE_LOCK_REQUEST:
818 case TCODE_LOCK_RESPONSE:
819 p.header[3] = cond_le32_to_cpu(buffer[3]);
820 p.header_length = 16;
821 p.payload_length = p.header[3] >> 16;
822 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
823 ar_context_abort(ctx, "invalid packet length");
828 case TCODE_WRITE_RESPONSE:
829 case TCODE_READ_QUADLET_REQUEST:
830 case OHCI_TCODE_PHY_PACKET:
831 p.header_length = 12;
832 p.payload_length = 0;
836 ar_context_abort(ctx, "invalid tcode");
840 p.payload = (void *) buffer + p.header_length;
842 /* FIXME: What to do about evt_* errors? */
843 length = (p.header_length + p.payload_length + 3) / 4;
844 status = cond_le32_to_cpu(buffer[length]);
845 evt = (status >> 16) & 0x1f;
848 p.speed = (status >> 21) & 0x7;
849 p.timestamp = status & 0xffff;
850 p.generation = ohci->request_generation;
852 log_ar_at_event('R', p.speed, p.header, evt);
855 * Several controllers, notably from NEC and VIA, forget to
856 * write ack_complete status at PHY packet reception.
858 if (evt == OHCI1394_evt_no_status &&
859 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
860 p.ack = ACK_COMPLETE;
863 * The OHCI bus reset handler synthesizes a PHY packet with
864 * the new generation number when a bus reset happens (see
865 * section 8.4.2.3). This helps us determine when a request
866 * was received and make sure we send the response in the same
867 * generation. We only need this for requests; for responses
868 * we use the unique tlabel for finding the matching
871 * Alas some chips sometimes emit bus reset packets with a
872 * wrong generation. We set the correct generation for these
873 * at a slightly incorrect time (in bus_reset_work).
875 if (evt == OHCI1394_evt_bus_reset) {
876 if (!(ohci->quirks & QUIRK_RESET_PACKET))
877 ohci->request_generation = (p.header[2] >> 16) & 0xff;
878 } else if (ctx == &ohci->ar_request_ctx) {
879 fw_core_handle_request(&ohci->card, &p);
881 fw_core_handle_response(&ohci->card, &p);
884 return buffer + length + 1;
887 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
892 next = handle_ar_packet(ctx, p);
901 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
905 i = ar_first_buffer_index(ctx);
906 while (i != end_buffer) {
907 dma_sync_single_for_device(ctx->ohci->card.device,
908 ar_buffer_bus(ctx, i),
909 PAGE_SIZE, DMA_FROM_DEVICE);
910 ar_context_link_page(ctx, i);
911 i = ar_next_buffer_index(i);
915 static void ar_context_tasklet(unsigned long data)
917 struct ar_context *ctx = (struct ar_context *)data;
918 unsigned int end_buffer_index, end_buffer_offset;
925 end_buffer_index = ar_search_last_active_buffer(ctx,
927 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
928 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
930 if (end_buffer_index < ar_first_buffer_index(ctx)) {
932 * The filled part of the overall buffer wraps around; handle
933 * all packets up to the buffer end here. If the last packet
934 * wraps around, its tail will be visible after the buffer end
935 * because the buffer start pages are mapped there again.
937 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
938 p = handle_ar_packets(ctx, p, buffer_end);
941 /* adjust p to point back into the actual buffer */
942 p -= AR_BUFFERS * PAGE_SIZE;
945 p = handle_ar_packets(ctx, p, end);
948 ar_context_abort(ctx, "inconsistent descriptor");
953 ar_recycle_buffers(ctx, end_buffer_index);
961 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
962 unsigned int descriptors_offset, u32 regs)
966 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
967 struct descriptor *d;
971 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
973 for (i = 0; i < AR_BUFFERS; i++) {
974 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
977 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
978 0, PAGE_SIZE, DMA_FROM_DEVICE);
979 if (dma_mapping_error(ohci->card.device, dma_addr)) {
980 __free_page(ctx->pages[i]);
981 ctx->pages[i] = NULL;
984 set_page_private(ctx->pages[i], dma_addr);
987 for (i = 0; i < AR_BUFFERS; i++)
988 pages[i] = ctx->pages[i];
989 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
990 pages[AR_BUFFERS + i] = ctx->pages[i];
991 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
996 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
997 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
999 for (i = 0; i < AR_BUFFERS; i++) {
1000 d = &ctx->descriptors[i];
1001 d->req_count = cpu_to_le16(PAGE_SIZE);
1002 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1004 DESCRIPTOR_BRANCH_ALWAYS);
1005 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1006 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1007 ar_next_buffer_index(i) * sizeof(struct descriptor));
1013 ar_context_release(ctx);
1018 static void ar_context_run(struct ar_context *ctx)
1022 for (i = 0; i < AR_BUFFERS; i++)
1023 ar_context_link_page(ctx, i);
1025 ctx->pointer = ctx->buffer;
1027 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1028 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1031 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1035 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1037 /* figure out which descriptor the branch address goes in */
1038 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1044 static void context_tasklet(unsigned long data)
1046 struct context *ctx = (struct context *) data;
1047 struct descriptor *d, *last;
1050 struct descriptor_buffer *desc;
1052 desc = list_entry(ctx->buffer_list.next,
1053 struct descriptor_buffer, list);
1055 while (last->branch_address != 0) {
1056 struct descriptor_buffer *old_desc = desc;
1057 address = le32_to_cpu(last->branch_address);
1061 /* If the branch address points to a buffer outside of the
1062 * current buffer, advance to the next buffer. */
1063 if (address < desc->buffer_bus ||
1064 address >= desc->buffer_bus + desc->used)
1065 desc = list_entry(desc->list.next,
1066 struct descriptor_buffer, list);
1067 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1068 last = find_branch_descriptor(d, z);
1070 if (!ctx->callback(ctx, d, last))
1073 if (old_desc != desc) {
1074 /* If we've advanced to the next buffer, move the
1075 * previous buffer to the free list. */
1076 unsigned long flags;
1078 spin_lock_irqsave(&ctx->ohci->lock, flags);
1079 list_move_tail(&old_desc->list, &ctx->buffer_list);
1080 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1087 * Allocate a new buffer and add it to the list of free buffers for this
1088 * context. Must be called with ohci->lock held.
1090 static int context_add_buffer(struct context *ctx)
1092 struct descriptor_buffer *desc;
1093 dma_addr_t uninitialized_var(bus_addr);
1097 * 16MB of descriptors should be far more than enough for any DMA
1098 * program. This will catch run-away userspace or DoS attacks.
1100 if (ctx->total_allocation >= 16*1024*1024)
1103 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1104 &bus_addr, GFP_ATOMIC);
1108 offset = (void *)&desc->buffer - (void *)desc;
1109 desc->buffer_size = PAGE_SIZE - offset;
1110 desc->buffer_bus = bus_addr + offset;
1113 list_add_tail(&desc->list, &ctx->buffer_list);
1114 ctx->total_allocation += PAGE_SIZE;
1119 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1120 u32 regs, descriptor_callback_t callback)
1124 ctx->total_allocation = 0;
1126 INIT_LIST_HEAD(&ctx->buffer_list);
1127 if (context_add_buffer(ctx) < 0)
1130 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1131 struct descriptor_buffer, list);
1133 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1134 ctx->callback = callback;
1137 * We put a dummy descriptor in the buffer that has a NULL
1138 * branch address and looks like it's been sent. That way we
1139 * have a descriptor to append DMA programs to.
1141 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1142 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1143 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1144 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1145 ctx->last = ctx->buffer_tail->buffer;
1146 ctx->prev = ctx->buffer_tail->buffer;
1151 static void context_release(struct context *ctx)
1153 struct fw_card *card = &ctx->ohci->card;
1154 struct descriptor_buffer *desc, *tmp;
1156 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1157 dma_free_coherent(card->device, PAGE_SIZE, desc,
1159 ((void *)&desc->buffer - (void *)desc));
1162 /* Must be called with ohci->lock held */
1163 static struct descriptor *context_get_descriptors(struct context *ctx,
1164 int z, dma_addr_t *d_bus)
1166 struct descriptor *d = NULL;
1167 struct descriptor_buffer *desc = ctx->buffer_tail;
1169 if (z * sizeof(*d) > desc->buffer_size)
1172 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1173 /* No room for the descriptor in this buffer, so advance to the
1176 if (desc->list.next == &ctx->buffer_list) {
1177 /* If there is no free buffer next in the list,
1179 if (context_add_buffer(ctx) < 0)
1182 desc = list_entry(desc->list.next,
1183 struct descriptor_buffer, list);
1184 ctx->buffer_tail = desc;
1187 d = desc->buffer + desc->used / sizeof(*d);
1188 memset(d, 0, z * sizeof(*d));
1189 *d_bus = desc->buffer_bus + desc->used;
1194 static void context_run(struct context *ctx, u32 extra)
1196 struct fw_ohci *ohci = ctx->ohci;
1198 reg_write(ohci, COMMAND_PTR(ctx->regs),
1199 le32_to_cpu(ctx->last->branch_address));
1200 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1201 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1202 ctx->running = true;
1206 static void context_append(struct context *ctx,
1207 struct descriptor *d, int z, int extra)
1210 struct descriptor_buffer *desc = ctx->buffer_tail;
1212 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1214 desc->used += (z + extra) * sizeof(*d);
1216 wmb(); /* finish init of new descriptors before branch_address update */
1217 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1218 ctx->prev = find_branch_descriptor(d, z);
1221 static void context_stop(struct context *ctx)
1226 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1227 ctx->running = false;
1229 for (i = 0; i < 1000; i++) {
1230 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1231 if ((reg & CONTEXT_ACTIVE) == 0)
1237 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1240 struct driver_data {
1242 struct fw_packet *packet;
1246 * This function apppends a packet to the DMA queue for transmission.
1247 * Must always be called with the ochi->lock held to ensure proper
1248 * generation handling and locking around packet queue manipulation.
1250 static int at_context_queue_packet(struct context *ctx,
1251 struct fw_packet *packet)
1253 struct fw_ohci *ohci = ctx->ohci;
1254 dma_addr_t d_bus, uninitialized_var(payload_bus);
1255 struct driver_data *driver_data;
1256 struct descriptor *d, *last;
1260 d = context_get_descriptors(ctx, 4, &d_bus);
1262 packet->ack = RCODE_SEND_ERROR;
1266 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1267 d[0].res_count = cpu_to_le16(packet->timestamp);
1270 * The DMA format for asyncronous link packets is different
1271 * from the IEEE1394 layout, so shift the fields around
1275 tcode = (packet->header[0] >> 4) & 0x0f;
1276 header = (__le32 *) &d[1];
1278 case TCODE_WRITE_QUADLET_REQUEST:
1279 case TCODE_WRITE_BLOCK_REQUEST:
1280 case TCODE_WRITE_RESPONSE:
1281 case TCODE_READ_QUADLET_REQUEST:
1282 case TCODE_READ_BLOCK_REQUEST:
1283 case TCODE_READ_QUADLET_RESPONSE:
1284 case TCODE_READ_BLOCK_RESPONSE:
1285 case TCODE_LOCK_REQUEST:
1286 case TCODE_LOCK_RESPONSE:
1287 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1288 (packet->speed << 16));
1289 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1290 (packet->header[0] & 0xffff0000));
1291 header[2] = cpu_to_le32(packet->header[2]);
1293 if (TCODE_IS_BLOCK_PACKET(tcode))
1294 header[3] = cpu_to_le32(packet->header[3]);
1296 header[3] = (__force __le32) packet->header[3];
1298 d[0].req_count = cpu_to_le16(packet->header_length);
1301 case TCODE_LINK_INTERNAL:
1302 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1303 (packet->speed << 16));
1304 header[1] = cpu_to_le32(packet->header[1]);
1305 header[2] = cpu_to_le32(packet->header[2]);
1306 d[0].req_count = cpu_to_le16(12);
1308 if (is_ping_packet(&packet->header[1]))
1309 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1312 case TCODE_STREAM_DATA:
1313 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1314 (packet->speed << 16));
1315 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1316 d[0].req_count = cpu_to_le16(8);
1321 packet->ack = RCODE_SEND_ERROR;
1325 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1326 driver_data = (struct driver_data *) &d[3];
1327 driver_data->packet = packet;
1328 packet->driver_data = driver_data;
1330 if (packet->payload_length > 0) {
1331 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1332 payload_bus = dma_map_single(ohci->card.device,
1334 packet->payload_length,
1336 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1337 packet->ack = RCODE_SEND_ERROR;
1340 packet->payload_bus = payload_bus;
1341 packet->payload_mapped = true;
1343 memcpy(driver_data->inline_data, packet->payload,
1344 packet->payload_length);
1345 payload_bus = d_bus + 3 * sizeof(*d);
1348 d[2].req_count = cpu_to_le16(packet->payload_length);
1349 d[2].data_address = cpu_to_le32(payload_bus);
1357 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1358 DESCRIPTOR_IRQ_ALWAYS |
1359 DESCRIPTOR_BRANCH_ALWAYS);
1361 /* FIXME: Document how the locking works. */
1362 if (ohci->generation != packet->generation) {
1363 if (packet->payload_mapped)
1364 dma_unmap_single(ohci->card.device, payload_bus,
1365 packet->payload_length, DMA_TO_DEVICE);
1366 packet->ack = RCODE_GENERATION;
1370 context_append(ctx, d, z, 4 - z);
1373 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1375 context_run(ctx, 0);
1380 static void at_context_flush(struct context *ctx)
1382 tasklet_disable(&ctx->tasklet);
1384 ctx->flushing = true;
1385 context_tasklet((unsigned long)ctx);
1386 ctx->flushing = false;
1388 tasklet_enable(&ctx->tasklet);
1391 static int handle_at_packet(struct context *context,
1392 struct descriptor *d,
1393 struct descriptor *last)
1395 struct driver_data *driver_data;
1396 struct fw_packet *packet;
1397 struct fw_ohci *ohci = context->ohci;
1400 if (last->transfer_status == 0 && !context->flushing)
1401 /* This descriptor isn't done yet, stop iteration. */
1404 driver_data = (struct driver_data *) &d[3];
1405 packet = driver_data->packet;
1407 /* This packet was cancelled, just continue. */
1410 if (packet->payload_mapped)
1411 dma_unmap_single(ohci->card.device, packet->payload_bus,
1412 packet->payload_length, DMA_TO_DEVICE);
1414 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1415 packet->timestamp = le16_to_cpu(last->res_count);
1417 log_ar_at_event('T', packet->speed, packet->header, evt);
1420 case OHCI1394_evt_timeout:
1421 /* Async response transmit timed out. */
1422 packet->ack = RCODE_CANCELLED;
1425 case OHCI1394_evt_flushed:
1427 * The packet was flushed should give same error as
1428 * when we try to use a stale generation count.
1430 packet->ack = RCODE_GENERATION;
1433 case OHCI1394_evt_missing_ack:
1434 if (context->flushing)
1435 packet->ack = RCODE_GENERATION;
1438 * Using a valid (current) generation count, but the
1439 * node is not on the bus or not sending acks.
1441 packet->ack = RCODE_NO_ACK;
1445 case ACK_COMPLETE + 0x10:
1446 case ACK_PENDING + 0x10:
1447 case ACK_BUSY_X + 0x10:
1448 case ACK_BUSY_A + 0x10:
1449 case ACK_BUSY_B + 0x10:
1450 case ACK_DATA_ERROR + 0x10:
1451 case ACK_TYPE_ERROR + 0x10:
1452 packet->ack = evt - 0x10;
1455 case OHCI1394_evt_no_status:
1456 if (context->flushing) {
1457 packet->ack = RCODE_GENERATION;
1463 packet->ack = RCODE_SEND_ERROR;
1467 packet->callback(packet, &ohci->card, packet->ack);
1472 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1473 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1474 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1475 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1476 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1478 static void handle_local_rom(struct fw_ohci *ohci,
1479 struct fw_packet *packet, u32 csr)
1481 struct fw_packet response;
1482 int tcode, length, i;
1484 tcode = HEADER_GET_TCODE(packet->header[0]);
1485 if (TCODE_IS_BLOCK_PACKET(tcode))
1486 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1490 i = csr - CSR_CONFIG_ROM;
1491 if (i + length > CONFIG_ROM_SIZE) {
1492 fw_fill_response(&response, packet->header,
1493 RCODE_ADDRESS_ERROR, NULL, 0);
1494 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1495 fw_fill_response(&response, packet->header,
1496 RCODE_TYPE_ERROR, NULL, 0);
1498 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1499 (void *) ohci->config_rom + i, length);
1502 fw_core_handle_response(&ohci->card, &response);
1505 static void handle_local_lock(struct fw_ohci *ohci,
1506 struct fw_packet *packet, u32 csr)
1508 struct fw_packet response;
1509 int tcode, length, ext_tcode, sel, try;
1510 __be32 *payload, lock_old;
1511 u32 lock_arg, lock_data;
1513 tcode = HEADER_GET_TCODE(packet->header[0]);
1514 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1515 payload = packet->payload;
1516 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1518 if (tcode == TCODE_LOCK_REQUEST &&
1519 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1520 lock_arg = be32_to_cpu(payload[0]);
1521 lock_data = be32_to_cpu(payload[1]);
1522 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1526 fw_fill_response(&response, packet->header,
1527 RCODE_TYPE_ERROR, NULL, 0);
1531 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1532 reg_write(ohci, OHCI1394_CSRData, lock_data);
1533 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1534 reg_write(ohci, OHCI1394_CSRControl, sel);
1536 for (try = 0; try < 20; try++)
1537 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1538 lock_old = cpu_to_be32(reg_read(ohci,
1540 fw_fill_response(&response, packet->header,
1542 &lock_old, sizeof(lock_old));
1546 fw_error("swap not done (CSR lock timeout)\n");
1547 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1550 fw_core_handle_response(&ohci->card, &response);
1553 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1557 if (ctx == &ctx->ohci->at_request_ctx) {
1558 packet->ack = ACK_PENDING;
1559 packet->callback(packet, &ctx->ohci->card, packet->ack);
1563 ((unsigned long long)
1564 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1566 csr = offset - CSR_REGISTER_BASE;
1568 /* Handle config rom reads. */
1569 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1570 handle_local_rom(ctx->ohci, packet, csr);
1572 case CSR_BUS_MANAGER_ID:
1573 case CSR_BANDWIDTH_AVAILABLE:
1574 case CSR_CHANNELS_AVAILABLE_HI:
1575 case CSR_CHANNELS_AVAILABLE_LO:
1576 handle_local_lock(ctx->ohci, packet, csr);
1579 if (ctx == &ctx->ohci->at_request_ctx)
1580 fw_core_handle_request(&ctx->ohci->card, packet);
1582 fw_core_handle_response(&ctx->ohci->card, packet);
1586 if (ctx == &ctx->ohci->at_response_ctx) {
1587 packet->ack = ACK_COMPLETE;
1588 packet->callback(packet, &ctx->ohci->card, packet->ack);
1592 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1594 unsigned long flags;
1597 spin_lock_irqsave(&ctx->ohci->lock, flags);
1599 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1600 ctx->ohci->generation == packet->generation) {
1601 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1602 handle_local_request(ctx, packet);
1606 ret = at_context_queue_packet(ctx, packet);
1607 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1610 packet->callback(packet, &ctx->ohci->card, packet->ack);
1614 static void detect_dead_context(struct fw_ohci *ohci,
1615 const char *name, unsigned int regs)
1619 ctl = reg_read(ohci, CONTROL_SET(regs));
1620 if (ctl & CONTEXT_DEAD) {
1621 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1622 fw_error("DMA context %s has stopped, error code: %s\n",
1623 name, evts[ctl & 0x1f]);
1625 fw_error("DMA context %s has stopped, error code: %#x\n",
1631 static void handle_dead_contexts(struct fw_ohci *ohci)
1636 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1637 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1638 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1639 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1640 for (i = 0; i < 32; ++i) {
1641 if (!(ohci->it_context_support & (1 << i)))
1643 sprintf(name, "IT%u", i);
1644 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1646 for (i = 0; i < 32; ++i) {
1647 if (!(ohci->ir_context_support & (1 << i)))
1649 sprintf(name, "IR%u", i);
1650 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1652 /* TODO: maybe try to flush and restart the dead contexts */
1655 static u32 cycle_timer_ticks(u32 cycle_timer)
1659 ticks = cycle_timer & 0xfff;
1660 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1661 ticks += (3072 * 8000) * (cycle_timer >> 25);
1667 * Some controllers exhibit one or more of the following bugs when updating the
1668 * iso cycle timer register:
1669 * - When the lowest six bits are wrapping around to zero, a read that happens
1670 * at the same time will return garbage in the lowest ten bits.
1671 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1672 * not incremented for about 60 ns.
1673 * - Occasionally, the entire register reads zero.
1675 * To catch these, we read the register three times and ensure that the
1676 * difference between each two consecutive reads is approximately the same, i.e.
1677 * less than twice the other. Furthermore, any negative difference indicates an
1678 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1679 * execute, so we have enough precision to compute the ratio of the differences.)
1681 static u32 get_cycle_time(struct fw_ohci *ohci)
1688 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1690 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1693 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1697 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698 t0 = cycle_timer_ticks(c0);
1699 t1 = cycle_timer_ticks(c1);
1700 t2 = cycle_timer_ticks(c2);
1703 } while ((diff01 <= 0 || diff12 <= 0 ||
1704 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1712 * This function has to be called at least every 64 seconds. The bus_time
1713 * field stores not only the upper 25 bits of the BUS_TIME register but also
1714 * the most significant bit of the cycle timer in bit 6 so that we can detect
1715 * changes in this bit.
1717 static u32 update_bus_time(struct fw_ohci *ohci)
1719 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1721 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1722 ohci->bus_time += 0x40;
1724 return ohci->bus_time | cycle_time_seconds;
1727 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1731 mutex_lock(&ohci->phy_reg_mutex);
1732 reg = write_phy_reg(ohci, 7, port_index);
1734 reg = read_phy_reg(ohci, 8);
1735 mutex_unlock(&ohci->phy_reg_mutex);
1739 switch (reg & 0x0f) {
1741 return 2; /* is child node (connected to parent node) */
1743 return 3; /* is parent node (connected to child node) */
1745 return 1; /* not connected */
1748 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1754 for (i = 0; i < self_id_count; i++) {
1755 entry = ohci->self_id_buffer[i];
1756 if ((self_id & 0xff000000) == (entry & 0xff000000))
1758 if ((self_id & 0xff000000) < (entry & 0xff000000))
1765 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1766 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1767 * Construct the selfID from phy register contents.
1768 * FIXME: How to determine the selfID.i flag?
1770 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1772 int reg, i, pos, status;
1773 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1774 u32 self_id = 0x8040c800;
1776 reg = reg_read(ohci, OHCI1394_NodeID);
1777 if (!(reg & OHCI1394_NodeID_idValid)) {
1778 fw_notify("node ID not valid, new bus reset in progress\n");
1781 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1783 reg = ohci_read_phy_reg(&ohci->card, 4);
1786 self_id |= ((reg & 0x07) << 8); /* power class */
1788 reg = ohci_read_phy_reg(&ohci->card, 1);
1791 self_id |= ((reg & 0x3f) << 16); /* gap count */
1793 for (i = 0; i < 3; i++) {
1794 status = get_status_for_port(ohci, i);
1797 self_id |= ((status & 0x3) << (6 - (i * 2)));
1800 pos = get_self_id_pos(ohci, self_id, self_id_count);
1802 memmove(&(ohci->self_id_buffer[pos+1]),
1803 &(ohci->self_id_buffer[pos]),
1804 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1805 ohci->self_id_buffer[pos] = self_id;
1808 return self_id_count;
1811 static void bus_reset_work(struct work_struct *work)
1813 struct fw_ohci *ohci =
1814 container_of(work, struct fw_ohci, bus_reset_work);
1815 int self_id_count, i, j, reg;
1816 int generation, new_generation;
1817 unsigned long flags;
1818 void *free_rom = NULL;
1819 dma_addr_t free_rom_bus = 0;
1822 reg = reg_read(ohci, OHCI1394_NodeID);
1823 if (!(reg & OHCI1394_NodeID_idValid)) {
1824 fw_notify("node ID not valid, new bus reset in progress\n");
1827 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1828 fw_notify("malconfigured bus\n");
1831 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1832 OHCI1394_NodeID_nodeNumber);
1834 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1835 if (!(ohci->is_root && is_new_root))
1836 reg_write(ohci, OHCI1394_LinkControlSet,
1837 OHCI1394_LinkControl_cycleMaster);
1838 ohci->is_root = is_new_root;
1840 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1841 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1842 fw_notify("inconsistent self IDs\n");
1846 * The count in the SelfIDCount register is the number of
1847 * bytes in the self ID receive buffer. Since we also receive
1848 * the inverted quadlets and a header quadlet, we shift one
1849 * bit extra to get the actual number of self IDs.
1851 self_id_count = (reg >> 3) & 0xff;
1853 if (self_id_count > 252) {
1854 fw_notify("inconsistent self IDs\n");
1858 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1861 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1862 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1863 fw_notify("inconsistent self IDs\n");
1866 ohci->self_id_buffer[j] =
1867 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1870 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1871 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1872 if (self_id_count < 0) {
1873 fw_notify("could not construct local self ID\n");
1878 if (self_id_count == 0) {
1879 fw_notify("inconsistent self IDs\n");
1885 * Check the consistency of the self IDs we just read. The
1886 * problem we face is that a new bus reset can start while we
1887 * read out the self IDs from the DMA buffer. If this happens,
1888 * the DMA buffer will be overwritten with new self IDs and we
1889 * will read out inconsistent data. The OHCI specification
1890 * (section 11.2) recommends a technique similar to
1891 * linux/seqlock.h, where we remember the generation of the
1892 * self IDs in the buffer before reading them out and compare
1893 * it to the current generation after reading them out. If
1894 * the two generations match we know we have a consistent set
1898 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1899 if (new_generation != generation) {
1900 fw_notify("recursive bus reset detected, "
1901 "discarding self ids\n");
1905 /* FIXME: Document how the locking works. */
1906 spin_lock_irqsave(&ohci->lock, flags);
1908 ohci->generation = -1; /* prevent AT packet queueing */
1909 context_stop(&ohci->at_request_ctx);
1910 context_stop(&ohci->at_response_ctx);
1912 spin_unlock_irqrestore(&ohci->lock, flags);
1915 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1916 * packets in the AT queues and software needs to drain them.
1917 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1919 at_context_flush(&ohci->at_request_ctx);
1920 at_context_flush(&ohci->at_response_ctx);
1922 spin_lock_irqsave(&ohci->lock, flags);
1924 ohci->generation = generation;
1925 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1927 if (ohci->quirks & QUIRK_RESET_PACKET)
1928 ohci->request_generation = generation;
1931 * This next bit is unrelated to the AT context stuff but we
1932 * have to do it under the spinlock also. If a new config rom
1933 * was set up before this reset, the old one is now no longer
1934 * in use and we can free it. Update the config rom pointers
1935 * to point to the current config rom and clear the
1936 * next_config_rom pointer so a new update can take place.
1939 if (ohci->next_config_rom != NULL) {
1940 if (ohci->next_config_rom != ohci->config_rom) {
1941 free_rom = ohci->config_rom;
1942 free_rom_bus = ohci->config_rom_bus;
1944 ohci->config_rom = ohci->next_config_rom;
1945 ohci->config_rom_bus = ohci->next_config_rom_bus;
1946 ohci->next_config_rom = NULL;
1949 * Restore config_rom image and manually update
1950 * config_rom registers. Writing the header quadlet
1951 * will indicate that the config rom is ready, so we
1954 reg_write(ohci, OHCI1394_BusOptions,
1955 be32_to_cpu(ohci->config_rom[2]));
1956 ohci->config_rom[0] = ohci->next_header;
1957 reg_write(ohci, OHCI1394_ConfigROMhdr,
1958 be32_to_cpu(ohci->next_header));
1961 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1962 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1963 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1966 spin_unlock_irqrestore(&ohci->lock, flags);
1969 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1970 free_rom, free_rom_bus);
1972 log_selfids(ohci->node_id, generation,
1973 self_id_count, ohci->self_id_buffer);
1975 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1976 self_id_count, ohci->self_id_buffer,
1977 ohci->csr_state_setclear_abdicate);
1978 ohci->csr_state_setclear_abdicate = false;
1981 static irqreturn_t irq_handler(int irq, void *data)
1983 struct fw_ohci *ohci = data;
1984 u32 event, iso_event;
1987 event = reg_read(ohci, OHCI1394_IntEventClear);
1989 if (!event || !~event)
1993 * busReset and postedWriteErr must not be cleared yet
1994 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1996 reg_write(ohci, OHCI1394_IntEventClear,
1997 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2000 if (event & OHCI1394_selfIDComplete)
2001 queue_work(fw_workqueue, &ohci->bus_reset_work);
2003 if (event & OHCI1394_RQPkt)
2004 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2006 if (event & OHCI1394_RSPkt)
2007 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2009 if (event & OHCI1394_reqTxComplete)
2010 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2012 if (event & OHCI1394_respTxComplete)
2013 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2015 if (event & OHCI1394_isochRx) {
2016 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2017 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2020 i = ffs(iso_event) - 1;
2022 &ohci->ir_context_list[i].context.tasklet);
2023 iso_event &= ~(1 << i);
2027 if (event & OHCI1394_isochTx) {
2028 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2029 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2032 i = ffs(iso_event) - 1;
2034 &ohci->it_context_list[i].context.tasklet);
2035 iso_event &= ~(1 << i);
2039 if (unlikely(event & OHCI1394_regAccessFail))
2040 fw_error("Register access failure - "
2041 "please notify linux1394-devel@lists.sf.net\n");
2043 if (unlikely(event & OHCI1394_postedWriteErr)) {
2044 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2045 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2046 reg_write(ohci, OHCI1394_IntEventClear,
2047 OHCI1394_postedWriteErr);
2048 fw_error("PCI posted write error\n");
2051 if (unlikely(event & OHCI1394_cycleTooLong)) {
2052 if (printk_ratelimit())
2053 fw_notify("isochronous cycle too long\n");
2054 reg_write(ohci, OHCI1394_LinkControlSet,
2055 OHCI1394_LinkControl_cycleMaster);
2058 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2060 * We need to clear this event bit in order to make
2061 * cycleMatch isochronous I/O work. In theory we should
2062 * stop active cycleMatch iso contexts now and restart
2063 * them at least two cycles later. (FIXME?)
2065 if (printk_ratelimit())
2066 fw_notify("isochronous cycle inconsistent\n");
2069 if (unlikely(event & OHCI1394_unrecoverableError))
2070 handle_dead_contexts(ohci);
2072 if (event & OHCI1394_cycle64Seconds) {
2073 spin_lock(&ohci->lock);
2074 update_bus_time(ohci);
2075 spin_unlock(&ohci->lock);
2082 static int software_reset(struct fw_ohci *ohci)
2087 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2088 for (i = 0; i < 500; i++) {
2089 val = reg_read(ohci, OHCI1394_HCControlSet);
2091 return -ENODEV; /* Card was ejected. */
2093 if (!(val & OHCI1394_HCControl_softReset))
2102 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2104 size_t size = length * 4;
2106 memcpy(dest, src, size);
2107 if (size < CONFIG_ROM_SIZE)
2108 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2111 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2114 int ret, clear, set, offset;
2116 /* Check if the driver should configure link and PHY. */
2117 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2118 OHCI1394_HCControl_programPhyEnable))
2121 /* Paranoia: check whether the PHY supports 1394a, too. */
2122 enable_1394a = false;
2123 ret = read_phy_reg(ohci, 2);
2126 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2127 ret = read_paged_phy_reg(ohci, 1, 8);
2131 enable_1394a = true;
2134 if (ohci->quirks & QUIRK_NO_1394A)
2135 enable_1394a = false;
2137 /* Configure PHY and link consistently. */
2140 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2142 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2145 ret = update_phy_reg(ohci, 5, clear, set);
2150 offset = OHCI1394_HCControlSet;
2152 offset = OHCI1394_HCControlClear;
2153 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2155 /* Clean up: configuration has been taken care of. */
2156 reg_write(ohci, OHCI1394_HCControlClear,
2157 OHCI1394_HCControl_programPhyEnable);
2162 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2164 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2165 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2168 reg = read_phy_reg(ohci, 2);
2171 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2174 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2175 reg = read_paged_phy_reg(ohci, 1, i + 10);
2184 static int ohci_enable(struct fw_card *card,
2185 const __be32 *config_rom, size_t length)
2187 struct fw_ohci *ohci = fw_ohci(card);
2188 struct pci_dev *dev = to_pci_dev(card->device);
2189 u32 lps, seconds, version, irqs;
2192 if (software_reset(ohci)) {
2193 fw_error("Failed to reset ohci card.\n");
2198 * Now enable LPS, which we need in order to start accessing
2199 * most of the registers. In fact, on some cards (ALI M5251),
2200 * accessing registers in the SClk domain without LPS enabled
2201 * will lock up the machine. Wait 50msec to make sure we have
2202 * full link enabled. However, with some cards (well, at least
2203 * a JMicron PCIe card), we have to try again sometimes.
2205 reg_write(ohci, OHCI1394_HCControlSet,
2206 OHCI1394_HCControl_LPS |
2207 OHCI1394_HCControl_postedWriteEnable);
2210 for (lps = 0, i = 0; !lps && i < 3; i++) {
2212 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2213 OHCI1394_HCControl_LPS;
2217 fw_error("Failed to set Link Power Status\n");
2221 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2222 ret = probe_tsb41ba3d(ohci);
2226 fw_notify("local TSB41BA3D phy\n");
2228 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2231 reg_write(ohci, OHCI1394_HCControlClear,
2232 OHCI1394_HCControl_noByteSwapData);
2234 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2235 reg_write(ohci, OHCI1394_LinkControlSet,
2236 OHCI1394_LinkControl_cycleTimerEnable |
2237 OHCI1394_LinkControl_cycleMaster);
2239 reg_write(ohci, OHCI1394_ATRetries,
2240 OHCI1394_MAX_AT_REQ_RETRIES |
2241 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2242 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2245 seconds = lower_32_bits(get_seconds());
2246 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2247 ohci->bus_time = seconds & ~0x3f;
2249 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2250 if (version >= OHCI_VERSION_1_1) {
2251 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2253 card->broadcast_channel_auto_allocated = true;
2256 /* Get implemented bits of the priority arbitration request counter. */
2257 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2258 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2259 reg_write(ohci, OHCI1394_FairnessControl, 0);
2260 card->priority_budget_implemented = ohci->pri_req_max != 0;
2262 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2263 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2264 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2266 ret = configure_1394a_enhancements(ohci);
2270 /* Activate link_on bit and contender bit in our self ID packets.*/
2271 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2276 * When the link is not yet enabled, the atomic config rom
2277 * update mechanism described below in ohci_set_config_rom()
2278 * is not active. We have to update ConfigRomHeader and
2279 * BusOptions manually, and the write to ConfigROMmap takes
2280 * effect immediately. We tie this to the enabling of the
2281 * link, so we have a valid config rom before enabling - the
2282 * OHCI requires that ConfigROMhdr and BusOptions have valid
2283 * values before enabling.
2285 * However, when the ConfigROMmap is written, some controllers
2286 * always read back quadlets 0 and 2 from the config rom to
2287 * the ConfigRomHeader and BusOptions registers on bus reset.
2288 * They shouldn't do that in this initial case where the link
2289 * isn't enabled. This means we have to use the same
2290 * workaround here, setting the bus header to 0 and then write
2291 * the right values in the bus reset tasklet.
2295 ohci->next_config_rom =
2296 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2297 &ohci->next_config_rom_bus,
2299 if (ohci->next_config_rom == NULL)
2302 copy_config_rom(ohci->next_config_rom, config_rom, length);
2305 * In the suspend case, config_rom is NULL, which
2306 * means that we just reuse the old config rom.
2308 ohci->next_config_rom = ohci->config_rom;
2309 ohci->next_config_rom_bus = ohci->config_rom_bus;
2312 ohci->next_header = ohci->next_config_rom[0];
2313 ohci->next_config_rom[0] = 0;
2314 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2315 reg_write(ohci, OHCI1394_BusOptions,
2316 be32_to_cpu(ohci->next_config_rom[2]));
2317 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2319 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2321 if (!(ohci->quirks & QUIRK_NO_MSI))
2322 pci_enable_msi(dev);
2323 if (request_irq(dev->irq, irq_handler,
2324 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2325 ohci_driver_name, ohci)) {
2326 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2327 pci_disable_msi(dev);
2330 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2331 ohci->next_config_rom,
2332 ohci->next_config_rom_bus);
2333 ohci->next_config_rom = NULL;
2338 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2339 OHCI1394_RQPkt | OHCI1394_RSPkt |
2340 OHCI1394_isochTx | OHCI1394_isochRx |
2341 OHCI1394_postedWriteErr |
2342 OHCI1394_selfIDComplete |
2343 OHCI1394_regAccessFail |
2344 OHCI1394_cycle64Seconds |
2345 OHCI1394_cycleInconsistent |
2346 OHCI1394_unrecoverableError |
2347 OHCI1394_cycleTooLong |
2348 OHCI1394_masterIntEnable;
2349 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2350 irqs |= OHCI1394_busReset;
2351 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2353 reg_write(ohci, OHCI1394_HCControlSet,
2354 OHCI1394_HCControl_linkEnable |
2355 OHCI1394_HCControl_BIBimageValid);
2357 reg_write(ohci, OHCI1394_LinkControlSet,
2358 OHCI1394_LinkControl_rcvSelfID |
2359 OHCI1394_LinkControl_rcvPhyPkt);
2361 ar_context_run(&ohci->ar_request_ctx);
2362 ar_context_run(&ohci->ar_response_ctx);
2366 /* We are ready to go, reset bus to finish initialization. */
2367 fw_schedule_bus_reset(&ohci->card, false, true);
2372 static int ohci_set_config_rom(struct fw_card *card,
2373 const __be32 *config_rom, size_t length)
2375 struct fw_ohci *ohci;
2376 unsigned long flags;
2377 __be32 *next_config_rom;
2378 dma_addr_t uninitialized_var(next_config_rom_bus);
2380 ohci = fw_ohci(card);
2383 * When the OHCI controller is enabled, the config rom update
2384 * mechanism is a bit tricky, but easy enough to use. See
2385 * section 5.5.6 in the OHCI specification.
2387 * The OHCI controller caches the new config rom address in a
2388 * shadow register (ConfigROMmapNext) and needs a bus reset
2389 * for the changes to take place. When the bus reset is
2390 * detected, the controller loads the new values for the
2391 * ConfigRomHeader and BusOptions registers from the specified
2392 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2393 * shadow register. All automatically and atomically.
2395 * Now, there's a twist to this story. The automatic load of
2396 * ConfigRomHeader and BusOptions doesn't honor the
2397 * noByteSwapData bit, so with a be32 config rom, the
2398 * controller will load be32 values in to these registers
2399 * during the atomic update, even on litte endian
2400 * architectures. The workaround we use is to put a 0 in the
2401 * header quadlet; 0 is endian agnostic and means that the
2402 * config rom isn't ready yet. In the bus reset tasklet we
2403 * then set up the real values for the two registers.
2405 * We use ohci->lock to avoid racing with the code that sets
2406 * ohci->next_config_rom to NULL (see bus_reset_work).
2410 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2411 &next_config_rom_bus, GFP_KERNEL);
2412 if (next_config_rom == NULL)
2415 spin_lock_irqsave(&ohci->lock, flags);
2418 * If there is not an already pending config_rom update,
2419 * push our new allocation into the ohci->next_config_rom
2420 * and then mark the local variable as null so that we
2421 * won't deallocate the new buffer.
2423 * OTOH, if there is a pending config_rom update, just
2424 * use that buffer with the new config_rom data, and
2425 * let this routine free the unused DMA allocation.
2428 if (ohci->next_config_rom == NULL) {
2429 ohci->next_config_rom = next_config_rom;
2430 ohci->next_config_rom_bus = next_config_rom_bus;
2431 next_config_rom = NULL;
2434 copy_config_rom(ohci->next_config_rom, config_rom, length);
2436 ohci->next_header = config_rom[0];
2437 ohci->next_config_rom[0] = 0;
2439 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2441 spin_unlock_irqrestore(&ohci->lock, flags);
2443 /* If we didn't use the DMA allocation, delete it. */
2444 if (next_config_rom != NULL)
2445 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2446 next_config_rom, next_config_rom_bus);
2449 * Now initiate a bus reset to have the changes take
2450 * effect. We clean up the old config rom memory and DMA
2451 * mappings in the bus reset tasklet, since the OHCI
2452 * controller could need to access it before the bus reset
2456 fw_schedule_bus_reset(&ohci->card, true, true);
2461 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2463 struct fw_ohci *ohci = fw_ohci(card);
2465 at_context_transmit(&ohci->at_request_ctx, packet);
2468 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2470 struct fw_ohci *ohci = fw_ohci(card);
2472 at_context_transmit(&ohci->at_response_ctx, packet);
2475 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2477 struct fw_ohci *ohci = fw_ohci(card);
2478 struct context *ctx = &ohci->at_request_ctx;
2479 struct driver_data *driver_data = packet->driver_data;
2482 tasklet_disable(&ctx->tasklet);
2484 if (packet->ack != 0)
2487 if (packet->payload_mapped)
2488 dma_unmap_single(ohci->card.device, packet->payload_bus,
2489 packet->payload_length, DMA_TO_DEVICE);
2491 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2492 driver_data->packet = NULL;
2493 packet->ack = RCODE_CANCELLED;
2494 packet->callback(packet, &ohci->card, packet->ack);
2497 tasklet_enable(&ctx->tasklet);
2502 static int ohci_enable_phys_dma(struct fw_card *card,
2503 int node_id, int generation)
2505 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2508 struct fw_ohci *ohci = fw_ohci(card);
2509 unsigned long flags;
2513 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2514 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2517 spin_lock_irqsave(&ohci->lock, flags);
2519 if (ohci->generation != generation) {
2525 * Note, if the node ID contains a non-local bus ID, physical DMA is
2526 * enabled for _all_ nodes on remote buses.
2529 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2531 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2533 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2537 spin_unlock_irqrestore(&ohci->lock, flags);
2540 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2543 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2545 struct fw_ohci *ohci = fw_ohci(card);
2546 unsigned long flags;
2549 switch (csr_offset) {
2550 case CSR_STATE_CLEAR:
2552 if (ohci->is_root &&
2553 (reg_read(ohci, OHCI1394_LinkControlSet) &
2554 OHCI1394_LinkControl_cycleMaster))
2555 value = CSR_STATE_BIT_CMSTR;
2558 if (ohci->csr_state_setclear_abdicate)
2559 value |= CSR_STATE_BIT_ABDICATE;
2564 return reg_read(ohci, OHCI1394_NodeID) << 16;
2566 case CSR_CYCLE_TIME:
2567 return get_cycle_time(ohci);
2571 * We might be called just after the cycle timer has wrapped
2572 * around but just before the cycle64Seconds handler, so we
2573 * better check here, too, if the bus time needs to be updated.
2575 spin_lock_irqsave(&ohci->lock, flags);
2576 value = update_bus_time(ohci);
2577 spin_unlock_irqrestore(&ohci->lock, flags);
2580 case CSR_BUSY_TIMEOUT:
2581 value = reg_read(ohci, OHCI1394_ATRetries);
2582 return (value >> 4) & 0x0ffff00f;
2584 case CSR_PRIORITY_BUDGET:
2585 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2586 (ohci->pri_req_max << 8);
2594 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2596 struct fw_ohci *ohci = fw_ohci(card);
2597 unsigned long flags;
2599 switch (csr_offset) {
2600 case CSR_STATE_CLEAR:
2601 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2602 reg_write(ohci, OHCI1394_LinkControlClear,
2603 OHCI1394_LinkControl_cycleMaster);
2606 if (value & CSR_STATE_BIT_ABDICATE)
2607 ohci->csr_state_setclear_abdicate = false;
2611 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2612 reg_write(ohci, OHCI1394_LinkControlSet,
2613 OHCI1394_LinkControl_cycleMaster);
2616 if (value & CSR_STATE_BIT_ABDICATE)
2617 ohci->csr_state_setclear_abdicate = true;
2621 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2625 case CSR_CYCLE_TIME:
2626 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2627 reg_write(ohci, OHCI1394_IntEventSet,
2628 OHCI1394_cycleInconsistent);
2633 spin_lock_irqsave(&ohci->lock, flags);
2634 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2635 spin_unlock_irqrestore(&ohci->lock, flags);
2638 case CSR_BUSY_TIMEOUT:
2639 value = (value & 0xf) | ((value & 0xf) << 4) |
2640 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2641 reg_write(ohci, OHCI1394_ATRetries, value);
2645 case CSR_PRIORITY_BUDGET:
2646 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2656 static void copy_iso_headers(struct iso_context *ctx, void *p)
2658 int i = ctx->header_length;
2660 if (i + ctx->base.header_size > PAGE_SIZE)
2664 * The iso header is byteswapped to little endian by
2665 * the controller, but the remaining header quadlets
2666 * are big endian. We want to present all the headers
2667 * as big endian, so we have to swap the first quadlet.
2669 if (ctx->base.header_size > 0)
2670 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2671 if (ctx->base.header_size > 4)
2672 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2673 if (ctx->base.header_size > 8)
2674 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2675 ctx->header_length += ctx->base.header_size;
2678 static int handle_ir_packet_per_buffer(struct context *context,
2679 struct descriptor *d,
2680 struct descriptor *last)
2682 struct iso_context *ctx =
2683 container_of(context, struct iso_context, context);
2684 struct descriptor *pd;
2688 for (pd = d; pd <= last; pd++)
2689 if (pd->transfer_status)
2692 /* Descriptor(s) not done yet, stop iteration */
2696 copy_iso_headers(ctx, p);
2698 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2699 ir_header = (__le32 *) p;
2700 ctx->base.callback.sc(&ctx->base,
2701 le32_to_cpu(ir_header[0]) & 0xffff,
2702 ctx->header_length, ctx->header,
2703 ctx->base.callback_data);
2704 ctx->header_length = 0;
2710 /* d == last because each descriptor block is only a single descriptor. */
2711 static int handle_ir_buffer_fill(struct context *context,
2712 struct descriptor *d,
2713 struct descriptor *last)
2715 struct iso_context *ctx =
2716 container_of(context, struct iso_context, context);
2718 if (!last->transfer_status)
2719 /* Descriptor(s) not done yet, stop iteration */
2722 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2723 ctx->base.callback.mc(&ctx->base,
2724 le32_to_cpu(last->data_address) +
2725 le16_to_cpu(last->req_count) -
2726 le16_to_cpu(last->res_count),
2727 ctx->base.callback_data);
2732 static int handle_it_packet(struct context *context,
2733 struct descriptor *d,
2734 struct descriptor *last)
2736 struct iso_context *ctx =
2737 container_of(context, struct iso_context, context);
2739 struct descriptor *pd;
2741 for (pd = d; pd <= last; pd++)
2742 if (pd->transfer_status)
2745 /* Descriptor(s) not done yet, stop iteration */
2748 i = ctx->header_length;
2749 if (i + 4 < PAGE_SIZE) {
2750 /* Present this value as big-endian to match the receive code */
2751 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2752 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2753 le16_to_cpu(pd->res_count));
2754 ctx->header_length += 4;
2756 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2757 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2758 ctx->header_length, ctx->header,
2759 ctx->base.callback_data);
2760 ctx->header_length = 0;
2765 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2767 u32 hi = channels >> 32, lo = channels;
2769 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2770 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2771 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2772 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2774 ohci->mc_channels = channels;
2777 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2778 int type, int channel, size_t header_size)
2780 struct fw_ohci *ohci = fw_ohci(card);
2781 struct iso_context *uninitialized_var(ctx);
2782 descriptor_callback_t uninitialized_var(callback);
2783 u64 *uninitialized_var(channels);
2784 u32 *uninitialized_var(mask), uninitialized_var(regs);
2785 unsigned long flags;
2786 int index, ret = -EBUSY;
2788 spin_lock_irqsave(&ohci->lock, flags);
2791 case FW_ISO_CONTEXT_TRANSMIT:
2792 mask = &ohci->it_context_mask;
2793 callback = handle_it_packet;
2794 index = ffs(*mask) - 1;
2796 *mask &= ~(1 << index);
2797 regs = OHCI1394_IsoXmitContextBase(index);
2798 ctx = &ohci->it_context_list[index];
2802 case FW_ISO_CONTEXT_RECEIVE:
2803 channels = &ohci->ir_context_channels;
2804 mask = &ohci->ir_context_mask;
2805 callback = handle_ir_packet_per_buffer;
2806 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2808 *channels &= ~(1ULL << channel);
2809 *mask &= ~(1 << index);
2810 regs = OHCI1394_IsoRcvContextBase(index);
2811 ctx = &ohci->ir_context_list[index];
2815 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2816 mask = &ohci->ir_context_mask;
2817 callback = handle_ir_buffer_fill;
2818 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2820 ohci->mc_allocated = true;
2821 *mask &= ~(1 << index);
2822 regs = OHCI1394_IsoRcvContextBase(index);
2823 ctx = &ohci->ir_context_list[index];
2832 spin_unlock_irqrestore(&ohci->lock, flags);
2835 return ERR_PTR(ret);
2837 memset(ctx, 0, sizeof(*ctx));
2838 ctx->header_length = 0;
2839 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2840 if (ctx->header == NULL) {
2844 ret = context_init(&ctx->context, ohci, regs, callback);
2846 goto out_with_header;
2848 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2849 set_multichannel_mask(ohci, 0);
2854 free_page((unsigned long)ctx->header);
2856 spin_lock_irqsave(&ohci->lock, flags);
2859 case FW_ISO_CONTEXT_RECEIVE:
2860 *channels |= 1ULL << channel;
2863 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2864 ohci->mc_allocated = false;
2867 *mask |= 1 << index;
2869 spin_unlock_irqrestore(&ohci->lock, flags);
2871 return ERR_PTR(ret);
2874 static int ohci_start_iso(struct fw_iso_context *base,
2875 s32 cycle, u32 sync, u32 tags)
2877 struct iso_context *ctx = container_of(base, struct iso_context, base);
2878 struct fw_ohci *ohci = ctx->context.ohci;
2879 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2882 /* the controller cannot start without any queued packets */
2883 if (ctx->context.last->branch_address == 0)
2886 switch (ctx->base.type) {
2887 case FW_ISO_CONTEXT_TRANSMIT:
2888 index = ctx - ohci->it_context_list;
2891 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2892 (cycle & 0x7fff) << 16;
2894 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2895 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2896 context_run(&ctx->context, match);
2899 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2900 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2902 case FW_ISO_CONTEXT_RECEIVE:
2903 index = ctx - ohci->ir_context_list;
2904 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2906 match |= (cycle & 0x07fff) << 12;
2907 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2910 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2911 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2912 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2913 context_run(&ctx->context, control);
2924 static int ohci_stop_iso(struct fw_iso_context *base)
2926 struct fw_ohci *ohci = fw_ohci(base->card);
2927 struct iso_context *ctx = container_of(base, struct iso_context, base);
2930 switch (ctx->base.type) {
2931 case FW_ISO_CONTEXT_TRANSMIT:
2932 index = ctx - ohci->it_context_list;
2933 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2936 case FW_ISO_CONTEXT_RECEIVE:
2937 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2938 index = ctx - ohci->ir_context_list;
2939 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2943 context_stop(&ctx->context);
2944 tasklet_kill(&ctx->context.tasklet);
2949 static void ohci_free_iso_context(struct fw_iso_context *base)
2951 struct fw_ohci *ohci = fw_ohci(base->card);
2952 struct iso_context *ctx = container_of(base, struct iso_context, base);
2953 unsigned long flags;
2956 ohci_stop_iso(base);
2957 context_release(&ctx->context);
2958 free_page((unsigned long)ctx->header);
2960 spin_lock_irqsave(&ohci->lock, flags);
2962 switch (base->type) {
2963 case FW_ISO_CONTEXT_TRANSMIT:
2964 index = ctx - ohci->it_context_list;
2965 ohci->it_context_mask |= 1 << index;
2968 case FW_ISO_CONTEXT_RECEIVE:
2969 index = ctx - ohci->ir_context_list;
2970 ohci->ir_context_mask |= 1 << index;
2971 ohci->ir_context_channels |= 1ULL << base->channel;
2974 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2975 index = ctx - ohci->ir_context_list;
2976 ohci->ir_context_mask |= 1 << index;
2977 ohci->ir_context_channels |= ohci->mc_channels;
2978 ohci->mc_channels = 0;
2979 ohci->mc_allocated = false;
2983 spin_unlock_irqrestore(&ohci->lock, flags);
2986 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2988 struct fw_ohci *ohci = fw_ohci(base->card);
2989 unsigned long flags;
2992 switch (base->type) {
2993 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2995 spin_lock_irqsave(&ohci->lock, flags);
2997 /* Don't allow multichannel to grab other contexts' channels. */
2998 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2999 *channels = ohci->ir_context_channels;
3002 set_multichannel_mask(ohci, *channels);
3006 spin_unlock_irqrestore(&ohci->lock, flags);
3017 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3020 struct iso_context *ctx;
3022 for (i = 0 ; i < ohci->n_ir ; i++) {
3023 ctx = &ohci->ir_context_list[i];
3024 if (ctx->context.running)
3025 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3028 for (i = 0 ; i < ohci->n_it ; i++) {
3029 ctx = &ohci->it_context_list[i];
3030 if (ctx->context.running)
3031 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3036 static int queue_iso_transmit(struct iso_context *ctx,
3037 struct fw_iso_packet *packet,
3038 struct fw_iso_buffer *buffer,
3039 unsigned long payload)
3041 struct descriptor *d, *last, *pd;
3042 struct fw_iso_packet *p;
3044 dma_addr_t d_bus, page_bus;
3045 u32 z, header_z, payload_z, irq;
3046 u32 payload_index, payload_end_index, next_page_index;
3047 int page, end_page, i, length, offset;
3050 payload_index = payload;
3056 if (p->header_length > 0)
3059 /* Determine the first page the payload isn't contained in. */
3060 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3061 if (p->payload_length > 0)
3062 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3068 /* Get header size in number of descriptors. */
3069 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3071 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3076 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3077 d[0].req_count = cpu_to_le16(8);
3079 * Link the skip address to this descriptor itself. This causes
3080 * a context to skip a cycle whenever lost cycles or FIFO
3081 * overruns occur, without dropping the data. The application
3082 * should then decide whether this is an error condition or not.
3083 * FIXME: Make the context's cycle-lost behaviour configurable?
3085 d[0].branch_address = cpu_to_le32(d_bus | z);
3087 header = (__le32 *) &d[1];
3088 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3089 IT_HEADER_TAG(p->tag) |
3090 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3091 IT_HEADER_CHANNEL(ctx->base.channel) |
3092 IT_HEADER_SPEED(ctx->base.speed));
3094 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3095 p->payload_length));
3098 if (p->header_length > 0) {
3099 d[2].req_count = cpu_to_le16(p->header_length);
3100 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3101 memcpy(&d[z], p->header, p->header_length);
3104 pd = d + z - payload_z;
3105 payload_end_index = payload_index + p->payload_length;
3106 for (i = 0; i < payload_z; i++) {
3107 page = payload_index >> PAGE_SHIFT;
3108 offset = payload_index & ~PAGE_MASK;
3109 next_page_index = (page + 1) << PAGE_SHIFT;
3111 min(next_page_index, payload_end_index) - payload_index;
3112 pd[i].req_count = cpu_to_le16(length);
3114 page_bus = page_private(buffer->pages[page]);
3115 pd[i].data_address = cpu_to_le32(page_bus + offset);
3117 payload_index += length;
3121 irq = DESCRIPTOR_IRQ_ALWAYS;
3123 irq = DESCRIPTOR_NO_IRQ;
3125 last = z == 2 ? d : d + z - 1;
3126 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3128 DESCRIPTOR_BRANCH_ALWAYS |
3131 context_append(&ctx->context, d, z, header_z);
3136 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3137 struct fw_iso_packet *packet,
3138 struct fw_iso_buffer *buffer,
3139 unsigned long payload)
3141 struct descriptor *d, *pd;
3142 dma_addr_t d_bus, page_bus;
3143 u32 z, header_z, rest;
3145 int page, offset, packet_count, header_size, payload_per_buffer;
3148 * The OHCI controller puts the isochronous header and trailer in the
3149 * buffer, so we need at least 8 bytes.
3151 packet_count = packet->header_length / ctx->base.header_size;
3152 header_size = max(ctx->base.header_size, (size_t)8);
3154 /* Get header size in number of descriptors. */
3155 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3156 page = payload >> PAGE_SHIFT;
3157 offset = payload & ~PAGE_MASK;
3158 payload_per_buffer = packet->payload_length / packet_count;
3160 for (i = 0; i < packet_count; i++) {
3161 /* d points to the header descriptor */
3162 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3163 d = context_get_descriptors(&ctx->context,
3164 z + header_z, &d_bus);
3168 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3169 DESCRIPTOR_INPUT_MORE);
3170 if (packet->skip && i == 0)
3171 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3172 d->req_count = cpu_to_le16(header_size);
3173 d->res_count = d->req_count;
3174 d->transfer_status = 0;
3175 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3177 rest = payload_per_buffer;
3179 for (j = 1; j < z; j++) {
3181 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3182 DESCRIPTOR_INPUT_MORE);
3184 if (offset + rest < PAGE_SIZE)
3187 length = PAGE_SIZE - offset;
3188 pd->req_count = cpu_to_le16(length);
3189 pd->res_count = pd->req_count;
3190 pd->transfer_status = 0;
3192 page_bus = page_private(buffer->pages[page]);
3193 pd->data_address = cpu_to_le32(page_bus + offset);
3195 offset = (offset + length) & ~PAGE_MASK;
3200 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3201 DESCRIPTOR_INPUT_LAST |
3202 DESCRIPTOR_BRANCH_ALWAYS);
3203 if (packet->interrupt && i == packet_count - 1)
3204 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3206 context_append(&ctx->context, d, z, header_z);
3212 static int queue_iso_buffer_fill(struct iso_context *ctx,
3213 struct fw_iso_packet *packet,
3214 struct fw_iso_buffer *buffer,
3215 unsigned long payload)
3217 struct descriptor *d;
3218 dma_addr_t d_bus, page_bus;
3219 int page, offset, rest, z, i, length;
3221 page = payload >> PAGE_SHIFT;
3222 offset = payload & ~PAGE_MASK;
3223 rest = packet->payload_length;
3225 /* We need one descriptor for each page in the buffer. */
3226 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3228 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3231 for (i = 0; i < z; i++) {
3232 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3236 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3237 DESCRIPTOR_BRANCH_ALWAYS);
3238 if (packet->skip && i == 0)
3239 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3240 if (packet->interrupt && i == z - 1)
3241 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3243 if (offset + rest < PAGE_SIZE)
3246 length = PAGE_SIZE - offset;
3247 d->req_count = cpu_to_le16(length);
3248 d->res_count = d->req_count;
3249 d->transfer_status = 0;
3251 page_bus = page_private(buffer->pages[page]);
3252 d->data_address = cpu_to_le32(page_bus + offset);
3258 context_append(&ctx->context, d, 1, 0);
3264 static int ohci_queue_iso(struct fw_iso_context *base,
3265 struct fw_iso_packet *packet,
3266 struct fw_iso_buffer *buffer,
3267 unsigned long payload)
3269 struct iso_context *ctx = container_of(base, struct iso_context, base);
3270 unsigned long flags;
3273 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3274 switch (base->type) {
3275 case FW_ISO_CONTEXT_TRANSMIT:
3276 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3278 case FW_ISO_CONTEXT_RECEIVE:
3279 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3281 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3282 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3285 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3290 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3292 struct context *ctx =
3293 &container_of(base, struct iso_context, base)->context;
3295 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3298 static const struct fw_card_driver ohci_driver = {
3299 .enable = ohci_enable,
3300 .read_phy_reg = ohci_read_phy_reg,
3301 .update_phy_reg = ohci_update_phy_reg,
3302 .set_config_rom = ohci_set_config_rom,
3303 .send_request = ohci_send_request,
3304 .send_response = ohci_send_response,
3305 .cancel_packet = ohci_cancel_packet,
3306 .enable_phys_dma = ohci_enable_phys_dma,
3307 .read_csr = ohci_read_csr,
3308 .write_csr = ohci_write_csr,
3310 .allocate_iso_context = ohci_allocate_iso_context,
3311 .free_iso_context = ohci_free_iso_context,
3312 .set_iso_channels = ohci_set_iso_channels,
3313 .queue_iso = ohci_queue_iso,
3314 .flush_queue_iso = ohci_flush_queue_iso,
3315 .start_iso = ohci_start_iso,
3316 .stop_iso = ohci_stop_iso,
3319 #ifdef CONFIG_PPC_PMAC
3320 static void pmac_ohci_on(struct pci_dev *dev)
3322 if (machine_is(powermac)) {
3323 struct device_node *ofn = pci_device_to_OF_node(dev);
3326 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3327 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3332 static void pmac_ohci_off(struct pci_dev *dev)
3334 if (machine_is(powermac)) {
3335 struct device_node *ofn = pci_device_to_OF_node(dev);
3338 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3339 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3344 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3345 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3346 #endif /* CONFIG_PPC_PMAC */
3348 static int __devinit pci_probe(struct pci_dev *dev,
3349 const struct pci_device_id *ent)
3351 struct fw_ohci *ohci;
3352 u32 bus_options, max_receive, link_speed, version;
3357 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3358 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3362 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3368 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3372 err = pci_enable_device(dev);
3374 fw_error("Failed to enable OHCI hardware\n");
3378 pci_set_master(dev);
3379 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3380 pci_set_drvdata(dev, ohci);
3382 spin_lock_init(&ohci->lock);
3383 mutex_init(&ohci->phy_reg_mutex);
3385 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3387 err = pci_request_region(dev, 0, ohci_driver_name);
3389 fw_error("MMIO resource unavailable\n");
3393 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3394 if (ohci->registers == NULL) {
3395 fw_error("Failed to remap registers\n");
3400 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3401 if ((ohci_quirks[i].vendor == dev->vendor) &&
3402 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3403 ohci_quirks[i].device == dev->device) &&
3404 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3405 ohci_quirks[i].revision >= dev->revision)) {
3406 ohci->quirks = ohci_quirks[i].flags;
3410 ohci->quirks = param_quirks;
3413 * Because dma_alloc_coherent() allocates at least one page,
3414 * we save space by using a common buffer for the AR request/
3415 * response descriptors and the self IDs buffer.
3417 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3418 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3419 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3421 &ohci->misc_buffer_bus,
3423 if (!ohci->misc_buffer) {
3428 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3429 OHCI1394_AsReqRcvContextControlSet);
3433 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3434 OHCI1394_AsRspRcvContextControlSet);
3436 goto fail_arreq_ctx;
3438 err = context_init(&ohci->at_request_ctx, ohci,
3439 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3441 goto fail_arrsp_ctx;
3443 err = context_init(&ohci->at_response_ctx, ohci,
3444 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3446 goto fail_atreq_ctx;
3448 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3449 ohci->ir_context_channels = ~0ULL;
3450 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3451 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3452 ohci->ir_context_mask = ohci->ir_context_support;
3453 ohci->n_ir = hweight32(ohci->ir_context_mask);
3454 size = sizeof(struct iso_context) * ohci->n_ir;
3455 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3457 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3458 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3459 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3460 ohci->it_context_mask = ohci->it_context_support;
3461 ohci->n_it = hweight32(ohci->it_context_mask);
3462 size = sizeof(struct iso_context) * ohci->n_it;
3463 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3465 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3470 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3471 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3473 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3474 max_receive = (bus_options >> 12) & 0xf;
3475 link_speed = bus_options & 0x7;
3476 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3477 reg_read(ohci, OHCI1394_GUIDLo);
3479 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3483 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3484 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3485 "%d IR + %d IT contexts, quirks 0x%x\n",
3486 dev_name(&dev->dev), version >> 16, version & 0xff,
3487 ohci->n_ir, ohci->n_it, ohci->quirks);
3492 kfree(ohci->ir_context_list);
3493 kfree(ohci->it_context_list);
3494 context_release(&ohci->at_response_ctx);
3496 context_release(&ohci->at_request_ctx);
3498 ar_context_release(&ohci->ar_response_ctx);
3500 ar_context_release(&ohci->ar_request_ctx);
3502 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3503 ohci->misc_buffer, ohci->misc_buffer_bus);
3505 pci_iounmap(dev, ohci->registers);
3507 pci_release_region(dev, 0);
3509 pci_disable_device(dev);
3515 fw_error("Out of memory\n");
3520 static void pci_remove(struct pci_dev *dev)
3522 struct fw_ohci *ohci;
3524 ohci = pci_get_drvdata(dev);
3525 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3527 cancel_work_sync(&ohci->bus_reset_work);
3528 fw_core_remove_card(&ohci->card);
3531 * FIXME: Fail all pending packets here, now that the upper
3532 * layers can't queue any more.
3535 software_reset(ohci);
3536 free_irq(dev->irq, ohci);
3538 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3539 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3540 ohci->next_config_rom, ohci->next_config_rom_bus);
3541 if (ohci->config_rom)
3542 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3543 ohci->config_rom, ohci->config_rom_bus);
3544 ar_context_release(&ohci->ar_request_ctx);
3545 ar_context_release(&ohci->ar_response_ctx);
3546 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3547 ohci->misc_buffer, ohci->misc_buffer_bus);
3548 context_release(&ohci->at_request_ctx);
3549 context_release(&ohci->at_response_ctx);
3550 kfree(ohci->it_context_list);
3551 kfree(ohci->ir_context_list);
3552 pci_disable_msi(dev);
3553 pci_iounmap(dev, ohci->registers);
3554 pci_release_region(dev, 0);
3555 pci_disable_device(dev);
3559 fw_notify("Removed fw-ohci device.\n");
3563 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3565 struct fw_ohci *ohci = pci_get_drvdata(dev);
3568 software_reset(ohci);
3569 free_irq(dev->irq, ohci);
3570 pci_disable_msi(dev);
3571 err = pci_save_state(dev);
3573 fw_error("pci_save_state failed\n");
3576 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3578 fw_error("pci_set_power_state failed with %d\n", err);
3584 static int pci_resume(struct pci_dev *dev)
3586 struct fw_ohci *ohci = pci_get_drvdata(dev);
3590 pci_set_power_state(dev, PCI_D0);
3591 pci_restore_state(dev);
3592 err = pci_enable_device(dev);
3594 fw_error("pci_enable_device failed\n");
3598 /* Some systems don't setup GUID register on resume from ram */
3599 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3600 !reg_read(ohci, OHCI1394_GUIDHi)) {
3601 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3602 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3605 err = ohci_enable(&ohci->card, NULL, 0);
3609 ohci_resume_iso_dma(ohci);
3615 static const struct pci_device_id pci_table[] = {
3616 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3620 MODULE_DEVICE_TABLE(pci, pci_table);
3622 static struct pci_driver fw_ohci_pci_driver = {
3623 .name = ohci_driver_name,
3624 .id_table = pci_table,
3626 .remove = pci_remove,
3628 .resume = pci_resume,
3629 .suspend = pci_suspend,
3633 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3634 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3635 MODULE_LICENSE("GPL");
3637 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3638 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3639 MODULE_ALIAS("ohci1394");
3642 static int __init fw_ohci_init(void)
3644 return pci_register_driver(&fw_ohci_pci_driver);
3647 static void __exit fw_ohci_cleanup(void)
3649 pci_unregister_driver(&fw_ohci_pci_driver);
3652 module_init(fw_ohci_init);
3653 module_exit(fw_ohci_cleanup);