drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bug.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/firewire.h>
  27 #include <linux/firewire-constants.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/slab.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/string.h>
  42 #include <linux/time.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/page.h>
  46 #include <asm/system.h>
  47
  48 #ifdef CONFIG_PPC_PMAC
  49 #include <asm/pmac_feature.h>
  50 #endif
  51
  52 #include "core.h"
  53 #include "ohci.h"
  54
  55 #define DESCRIPTOR_OUTPUT_MORE          0
  56 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  57 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  58 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  59 #define DESCRIPTOR_STATUS               (1 << 11)
  60 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  61 #define DESCRIPTOR_PING                 (1 << 7)
  62 #define DESCRIPTOR_YY                   (1 << 6)
  63 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  64 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  65 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  66 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  67 #define DESCRIPTOR_WAIT                 (3 << 0)
  68
  69 struct descriptor {
  70         __le16 req_count;
  71         __le16 control;
  72         __le32 data_address;
  73         __le32 branch_address;
  74         __le16 res_count;
  75         __le16 transfer_status;
  76 } __attribute__((aligned(16)));
  77
  78 #define CONTROL_SET(regs)       (regs)
  79 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  80 #define COMMAND_PTR(regs)       ((regs) + 12)
  81 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  82
  83 struct ar_buffer {
  84         struct descriptor descriptor;
  85         struct ar_buffer *next;
  86         __le32 data[0];
  87 };
  88
  89 struct ar_context {
  90         struct fw_ohci *ohci;
  91         struct ar_buffer *current_buffer;
  92         struct ar_buffer *last_buffer;
  93         void *pointer;
  94         u32 regs;
  95         struct tasklet_struct tasklet;
  96 };
  97
  98 struct context;
  99
 100 typedef int (*descriptor_callback_t)(struct context *ctx,
 101                                      struct descriptor *d,
 102                                      struct descriptor *last);
 103
 104 /*
 105  * A buffer that contains a block of DMA-able coherent memory used for
 106  * storing a portion of a DMA descriptor program.
 107  */
 108 struct descriptor_buffer {
 109         struct list_head list;
 110         dma_addr_t buffer_bus;
 111         size_t buffer_size;
 112         size_t used;
 113         struct descriptor buffer[0];
 114 };
 115
 116 struct context {
 117         struct fw_ohci *ohci;
 118         u32 regs;
 119         int total_allocation;
 120
 121         /*
 122          * List of page-sized buffers for storing DMA descriptors.
 123          * Head of list contains buffers in use and tail of list contains
 124          * free buffers.
 125          */
 126         struct list_head buffer_list;
 127
 128         /*
 129          * Pointer to a buffer inside buffer_list that contains the tail
 130          * end of the current DMA program.
 131          */
 132         struct descriptor_buffer *buffer_tail;
 133
 134         /*
 135          * The descriptor containing the branch address of the first
 136          * descriptor that has not yet been filled by the device.
 137          */
 138         struct descriptor *last;
 139
 140         /*
 141          * The last descriptor in the DMA program.  It contains the branch
 142          * address that must be updated upon appending a new descriptor.
 143          */
 144         struct descriptor *prev;
 145
 146         descriptor_callback_t callback;
 147
 148         struct tasklet_struct tasklet;
 149 };
 150
 151 #define IT_HEADER_SY(v)          ((v) <<  0)
 152 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 153 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 154 #define IT_HEADER_TAG(v)         ((v) << 14)
 155 #define IT_HEADER_SPEED(v)       ((v) << 16)
 156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 157
 158 struct iso_context {
 159         struct fw_iso_context base;
 160         struct context context;
 161         int excess_bytes;
 162         void *header;
 163         size_t header_length;
 164 };
 165
 166 #define CONFIG_ROM_SIZE 1024
 167
 168 struct fw_ohci {
 169         struct fw_card card;
 170
 171         __iomem char *registers;
 172         int node_id;
 173         int generation;
 174         int request_generation; /* for timestamping incoming requests */
 175         unsigned quirks;
 176         unsigned int pri_req_max;
 177         u32 bus_time;
 178         bool is_root;
 179         bool csr_state_setclear_abdicate;
 180
 181         /*
 182          * Spinlock for accessing fw_ohci data.  Never call out of
 183          * this driver with this lock held.
 184          */
 185         spinlock_t lock;
 186
 187         struct mutex phy_reg_mutex;
 188
 189         struct ar_context ar_request_ctx;
 190         struct ar_context ar_response_ctx;
 191         struct context at_request_ctx;
 192         struct context at_response_ctx;
 193
 194         u32 it_context_mask;     /* unoccupied IT contexts */
 195         struct iso_context *it_context_list;
 196         u64 ir_context_channels; /* unoccupied channels */
 197         u32 ir_context_mask;     /* unoccupied IR contexts */
 198         struct iso_context *ir_context_list;
 199         u64 mc_channels; /* channels in use by the multichannel IR context */
 200         bool mc_allocated;
 201
 202         __be32    *config_rom;
 203         dma_addr_t config_rom_bus;
 204         __be32    *next_config_rom;
 205         dma_addr_t next_config_rom_bus;
 206         __be32     next_header;
 207
 208         __le32    *self_id_cpu;
 209         dma_addr_t self_id_bus;
 210         struct tasklet_struct bus_reset_tasklet;
 211
 212         u32 self_id_buffer[512];
 213 };
 214
 215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 216 {
 217         return container_of(card, struct fw_ohci, card);
 218 }
 219
 220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 221 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 222 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 224 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 225 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 226
 227 #define CONTEXT_RUN     0x8000
 228 #define CONTEXT_WAKE    0x1000
 229 #define CONTEXT_DEAD    0x0800
 230 #define CONTEXT_ACTIVE  0x0400
 231
 232 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 233 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 234 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 235
 236 #define OHCI1394_REGISTER_SIZE          0x800
 237 #define OHCI_LOOP_COUNT                 500
 238 #define OHCI1394_PCI_HCI_Control        0x40
 239 #define SELF_ID_BUF_SIZE                0x800
 240 #define OHCI_TCODE_PHY_PACKET           0x0e
 241 #define OHCI_VERSION_1_1                0x010010
 242
 243 static char ohci_driver_name[] = KBUILD_MODNAME;
 244
 245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 246 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 247
 248 #define QUIRK_CYCLE_TIMER               1
 249 #define QUIRK_RESET_PACKET              2
 250 #define QUIRK_BE_HEADERS                4
 251 #define QUIRK_NO_1394A                  8
 252 #define QUIRK_NO_MSI                    16
 253
 254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 255 static const struct {
 256         unsigned short vendor, device, flags;
 257 } ohci_quirks[] = {
 258         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
 259                                                             QUIRK_RESET_PACKET |
 260                                                             QUIRK_NO_1394A},
 261         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
 262         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 263         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
 264         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 265         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER |
 266                                                 QUIRK_NO_MSI},
 267         {PCI_VENDOR_ID_RICOH,   PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 268         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
 269 };
 270
 271 /* This overrides anything that was found in ohci_quirks[]. */
 272 static int param_quirks;
 273 module_param_named(quirks, param_quirks, int, 0644);
 274 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 275         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 276         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 277         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 278         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 279         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 280         ")");
 281
 282 #define OHCI_PARAM_DEBUG_AT_AR          1
 283 #define OHCI_PARAM_DEBUG_SELFIDS        2
 284 #define OHCI_PARAM_DEBUG_IRQS           4
 285 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 286
 287 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 288
 289 static int param_debug;
 290 module_param_named(debug, param_debug, int, 0644);
 291 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 292         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 293         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 294         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 295         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 296         ", or a combination, or all = -1)");
 297
 298 static void log_irqs(u32 evt)
 299 {
 300         if (likely(!(param_debug &
 301                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 302                 return;
 303
 304         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 305             !(evt & OHCI1394_busReset))
 306                 return;
 307
 308         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 309             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 310             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 311             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 312             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 313             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 314             evt & OHCI1394_isochRx              ? " IR"                 : "",
 315             evt & OHCI1394_isochTx              ? " IT"                 : "",
 316             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 317             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 318             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 319             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 320             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 321             evt & OHCI1394_busReset             ? " busReset"           : "",
 322             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 323                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 324                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 325                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 326                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 327                     OHCI1394_cycleInconsistent |
 328                     OHCI1394_regAccessFail | OHCI1394_busReset)
 329                                                 ? " ?"                  : "");
 330 }
 331
 332 static const char *speed[] = {
 333         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 334 };
 335 static const char *power[] = {
 336         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 337         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 338 };
 339 static const char port[] = { '.', '-', 'p', 'c', };
 340
 341 static char _p(u32 *s, int shift)
 342 {
 343         return port[*s >> shift & 3];
 344 }
 345
 346 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 347 {
 348         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 349                 return;
 350
 351         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 352                   self_id_count, generation, node_id);
 353
 354         for (; self_id_count--; ++s)
 355                 if ((*s & 1 << 23) == 0)
 356                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 357                             "%s gc=%d %s %s%s%s\n",
 358                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 359                             speed[*s >> 14 & 3], *s >> 16 & 63,
 360                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 361                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 362                 else
 363                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 364                             *s, *s >> 24 & 63,
 365                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 366                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 367 }
 368
 369 static const char *evts[] = {
 370         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 371         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 372         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 373         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 374         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 375         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 376         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 377         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 378         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 379         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 380         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 381         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 382         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 383         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 384         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 385         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 386         [0x20] = "pending/cancelled",
 387 };
 388 static const char *tcodes[] = {
 389         [0x0] = "QW req",               [0x1] = "BW req",
 390         [0x2] = "W resp",               [0x3] = "-reserved-",
 391         [0x4] = "QR req",               [0x5] = "BR req",
 392         [0x6] = "QR resp",              [0x7] = "BR resp",
 393         [0x8] = "cycle start",          [0x9] = "Lk req",
 394         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 395         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 396         [0xe] = "link internal",        [0xf] = "-reserved-",
 397 };
 398 static const char *phys[] = {
 399         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 400         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 401 };
 402
 403 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 404 {
 405         int tcode = header[0] >> 4 & 0xf;
 406         char specific[12];
 407
 408         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 409                 return;
 410
 411         if (unlikely(evt >= ARRAY_SIZE(evts)))
 412                         evt = 0x1f;
 413
 414         if (evt == OHCI1394_evt_bus_reset) {
 415                 fw_notify("A%c evt_bus_reset, generation %d\n",
 416                     dir, (header[2] >> 16) & 0xff);
 417                 return;
 418         }
 419
 420         if (header[0] == ~header[1]) {
 421                 fw_notify("A%c %s, %s, %08x\n",
 422                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 423                 return;
 424         }
 425
 426         switch (tcode) {
 427         case 0x0: case 0x6: case 0x8:
 428                 snprintf(specific, sizeof(specific), " = %08x",
 429                          be32_to_cpu((__force __be32)header[3]));
 430                 break;
 431         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 432                 snprintf(specific, sizeof(specific), " %x,%x",
 433                          header[3] >> 16, header[3] & 0xffff);
 434                 break;
 435         default:
 436                 specific[0] = '\0';
 437         }
 438
 439         switch (tcode) {
 440         case 0xe: case 0xa:
 441                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 442                 break;
 443         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 444                 fw_notify("A%c spd %x tl %02x, "
 445                     "%04x -> %04x, %s, "
 446                     "%s, %04x%08x%s\n",
 447                     dir, speed, header[0] >> 10 & 0x3f,
 448                     header[1] >> 16, header[0] >> 16, evts[evt],
 449                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 450                 break;
 451         default:
 452                 fw_notify("A%c spd %x tl %02x, "
 453                     "%04x -> %04x, %s, "
 454                     "%s%s\n",
 455                     dir, speed, header[0] >> 10 & 0x3f,
 456                     header[1] >> 16, header[0] >> 16, evts[evt],
 457                     tcodes[tcode], specific);
 458         }
 459 }
 460
 461 #else
 462
 463 #define param_debug 0
 464 static inline void log_irqs(u32 evt) {}
 465 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 466 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 467
 468 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 469
 470 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 471 {
 472         writel(data, ohci->registers + offset);
 473 }
 474
 475 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 476 {
 477         return readl(ohci->registers + offset);
 478 }
 479
 480 static inline void flush_writes(const struct fw_ohci *ohci)
 481 {
 482         /* Do a dummy read to flush writes. */
 483         reg_read(ohci, OHCI1394_Version);
 484 }
 485
 486 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 487 {
 488         u32 val;
 489         int i;
 490
 491         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 492         for (i = 0; i < 3 + 100; i++) {
 493                 val = reg_read(ohci, OHCI1394_PhyControl);
 494                 if (val & OHCI1394_PhyControl_ReadDone)
 495                         return OHCI1394_PhyControl_ReadData(val);
 496
 497                 /*
 498                  * Try a few times without waiting.  Sleeping is necessary
 499                  * only when the link/PHY interface is busy.
 500                  */
 501                 if (i >= 3)
 502                         msleep(1);
 503         }
 504         fw_error("failed to read phy reg\n");
 505
 506         return -EBUSY;
 507 }
 508
 509 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 510 {
 511         int i;
 512
 513         reg_write(ohci, OHCI1394_PhyControl,
 514                   OHCI1394_PhyControl_Write(addr, val));
 515         for (i = 0; i < 3 + 100; i++) {
 516                 val = reg_read(ohci, OHCI1394_PhyControl);
 517                 if (!(val & OHCI1394_PhyControl_WritePending))
 518                         return 0;
 519
 520                 if (i >= 3)
 521                         msleep(1);
 522         }
 523         fw_error("failed to write phy reg\n");
 524
 525         return -EBUSY;
 526 }
 527
 528 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 529                           int clear_bits, int set_bits)
 530 {
 531         int ret = read_phy_reg(ohci, addr);
 532         if (ret < 0)
 533                 return ret;
 534
 535         /*
 536          * The interrupt status bits are cleared by writing a one bit.
 537          * Avoid clearing them unless explicitly requested in set_bits.
 538          */
 539         if (addr == 5)
 540                 clear_bits |= PHY_INT_STATUS_BITS;
 541
 542         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 543 }
 544
 545 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 546 {
 547         int ret;
 548
 549         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 550         if (ret < 0)
 551                 return ret;
 552
 553         return read_phy_reg(ohci, addr);
 554 }
 555
 556 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 557 {
 558         struct fw_ohci *ohci = fw_ohci(card);
 559         int ret;
 560
 561         mutex_lock(&ohci->phy_reg_mutex);
 562         ret = read_phy_reg(ohci, addr);
 563         mutex_unlock(&ohci->phy_reg_mutex);
 564
 565         return ret;
 566 }
 567
 568 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 569                                int clear_bits, int set_bits)
 570 {
 571         struct fw_ohci *ohci = fw_ohci(card);
 572         int ret;
 573
 574         mutex_lock(&ohci->phy_reg_mutex);
 575         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 576         mutex_unlock(&ohci->phy_reg_mutex);
 577
 578         return ret;
 579 }
 580
 581 static void ar_context_link_page(struct ar_context *ctx,
 582                                  struct ar_buffer *ab, dma_addr_t ab_bus)
 583 {
 584         size_t offset;
 585
 586         ab->next = NULL;
 587         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 588         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 589                                                     DESCRIPTOR_STATUS |
 590                                                     DESCRIPTOR_BRANCH_ALWAYS);
 591         offset = offsetof(struct ar_buffer, data);
 592         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 593         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 594         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 595         ab->descriptor.branch_address = 0;
 596
 597         wmb(); /* finish init of new descriptors before branch_address update */
 598         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 599         ctx->last_buffer->next = ab;
 600         ctx->last_buffer = ab;
 601
 602         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 603         flush_writes(ctx->ohci);
 604 }
 605
 606 static int ar_context_add_page(struct ar_context *ctx)
 607 {
 608         struct device *dev = ctx->ohci->card.device;
 609         struct ar_buffer *ab;
 610         dma_addr_t uninitialized_var(ab_bus);
 611
 612         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 613         if (ab == NULL)
 614                 return -ENOMEM;
 615
 616         ar_context_link_page(ctx, ab, ab_bus);
 617
 618         return 0;
 619 }
 620
 621 static void ar_context_release(struct ar_context *ctx)
 622 {
 623         struct ar_buffer *ab, *ab_next;
 624         size_t offset;
 625         dma_addr_t ab_bus;
 626
 627         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 628                 ab_next = ab->next;
 629                 offset = offsetof(struct ar_buffer, data);
 630                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 631                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 632                                   ab, ab_bus);
 633         }
 634 }
 635
 636 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 637 #define cond_le32_to_cpu(v) \
 638         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 639 #else
 640 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 641 #endif
 642
 643 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 644 {
 645         struct fw_ohci *ohci = ctx->ohci;
 646         struct fw_packet p;
 647         u32 status, length, tcode;
 648         int evt;
 649
 650         p.header[0] = cond_le32_to_cpu(buffer[0]);
 651         p.header[1] = cond_le32_to_cpu(buffer[1]);
 652         p.header[2] = cond_le32_to_cpu(buffer[2]);
 653
 654         tcode = (p.header[0] >> 4) & 0x0f;
 655         switch (tcode) {
 656         case TCODE_WRITE_QUADLET_REQUEST:
 657         case TCODE_READ_QUADLET_RESPONSE:
 658                 p.header[3] = (__force __u32) buffer[3];
 659                 p.header_length = 16;
 660                 p.payload_length = 0;
 661                 break;
 662
 663         case TCODE_READ_BLOCK_REQUEST :
 664                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 665                 p.header_length = 16;
 666                 p.payload_length = 0;
 667                 break;
 668
 669         case TCODE_WRITE_BLOCK_REQUEST:
 670         case TCODE_READ_BLOCK_RESPONSE:
 671         case TCODE_LOCK_REQUEST:
 672         case TCODE_LOCK_RESPONSE:
 673                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 674                 p.header_length = 16;
 675                 p.payload_length = p.header[3] >> 16;
 676                 break;
 677
 678         case TCODE_WRITE_RESPONSE:
 679         case TCODE_READ_QUADLET_REQUEST:
 680         case OHCI_TCODE_PHY_PACKET:
 681                 p.header_length = 12;
 682                 p.payload_length = 0;
 683                 break;
 684
 685         default:
 686                 /* FIXME: Stop context, discard everything, and restart? */
 687                 p.header_length = 0;
 688                 p.payload_length = 0;
 689         }
 690
 691         p.payload = (void *) buffer + p.header_length;
 692
 693         /* FIXME: What to do about evt_* errors? */
 694         length = (p.header_length + p.payload_length + 3) / 4;
 695         status = cond_le32_to_cpu(buffer[length]);
 696         evt    = (status >> 16) & 0x1f;
 697
 698         p.ack        = evt - 16;
 699         p.speed      = (status >> 21) & 0x7;
 700         p.timestamp  = status & 0xffff;
 701         p.generation = ohci->request_generation;
 702
 703         log_ar_at_event('R', p.speed, p.header, evt);
 704
 705         /*
 706          * Several controllers, notably from NEC and VIA, forget to
 707          * write ack_complete status at PHY packet reception.
 708          */
 709         if (evt == OHCI1394_evt_no_status &&
 710             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 711                 p.ack = ACK_COMPLETE;
 712
 713         /*
 714          * The OHCI bus reset handler synthesizes a PHY packet with
 715          * the new generation number when a bus reset happens (see
 716          * section 8.4.2.3).  This helps us determine when a request
 717          * was received and make sure we send the response in the same
 718          * generation.  We only need this for requests; for responses
 719          * we use the unique tlabel for finding the matching
 720          * request.
 721          *
 722          * Alas some chips sometimes emit bus reset packets with a
 723          * wrong generation.  We set the correct generation for these
 724          * at a slightly incorrect time (in bus_reset_tasklet).
 725          */
 726         if (evt == OHCI1394_evt_bus_reset) {
 727                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 728                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 729         } else if (ctx == &ohci->ar_request_ctx) {
 730                 fw_core_handle_request(&ohci->card, &p);
 731         } else {
 732                 fw_core_handle_response(&ohci->card, &p);
 733         }
 734
 735         return buffer + length + 1;
 736 }
 737
 738 static void ar_context_tasklet(unsigned long data)
 739 {
 740         struct ar_context *ctx = (struct ar_context *)data;
 741         struct ar_buffer *ab;
 742         struct descriptor *d;
 743         void *buffer, *end;
 744         __le16 res_count;
 745
 746         ab = ctx->current_buffer;
 747         d = &ab->descriptor;
 748
 749         res_count = ACCESS_ONCE(d->res_count);
 750         if (res_count == 0) {
 751                 size_t size, size2, rest, pktsize, size3, offset;
 752                 dma_addr_t start_bus;
 753                 void *start;
 754
 755                 /*
 756                  * This descriptor is finished and we may have a
 757                  * packet split across this and the next buffer. We
 758                  * reuse the page for reassembling the split packet.
 759                  */
 760
 761                 offset = offsetof(struct ar_buffer, data);
 762                 start = ab;
 763                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 764                 buffer = ab->data;
 765
 766                 ab = ab->next;
 767                 d = &ab->descriptor;
 768                 size = start + PAGE_SIZE - ctx->pointer;
 769                 /* valid buffer data in the next page */
 770                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 771                 /* what actually fits in this page */
 772                 size2 = min(rest, (size_t)PAGE_SIZE - offset - size);
 773                 memmove(buffer, ctx->pointer, size);
 774                 memcpy(buffer + size, ab->data, size2);
 775
 776                 while (size > 0) {
 777                         void *next = handle_ar_packet(ctx, buffer);
 778                         pktsize = next - buffer;
 779                         if (pktsize >= size) {
 780                                 /*
 781                                  * We have handled all the data that was
 782                                  * originally in this page, so we can now
 783                                  * continue in the next page.
 784                                  */
 785                                 buffer = next;
 786                                 break;
 787                         }
 788                         /* move the next packet to the start of the buffer */
 789                         memmove(buffer, next, size + size2 - pktsize);
 790                         size -= pktsize;
 791                         /* fill up this page again */
 792                         size3 = min(rest - size2,
 793                                     (size_t)PAGE_SIZE - offset - size - size2);
 794                         memcpy(buffer + size + size2,
 795                                (void *) ab->data + size2, size3);
 796                         size2 += size3;
 797                 }
 798
 799                 if (rest > 0) {
 800                         /* handle the packets that are fully in the next page */
 801                         buffer = (void *) ab->data +
 802                                         (buffer - (start + offset + size));
 803                         end = (void *) ab->data + rest;
 804
 805                         while (buffer < end)
 806                                 buffer = handle_ar_packet(ctx, buffer);
 807
 808                         ctx->current_buffer = ab;
 809                         ctx->pointer = end;
 810
 811                         ar_context_link_page(ctx, start, start_bus);
 812                 } else {
 813                         ctx->pointer = start + PAGE_SIZE;
 814                 }
 815         } else {
 816                 buffer = ctx->pointer;
 817                 ctx->pointer = end =
 818                         (void *) ab + PAGE_SIZE - le16_to_cpu(res_count);
 819
 820                 while (buffer < end)
 821                         buffer = handle_ar_packet(ctx, buffer);
 822         }
 823 }
 824
 825 static int ar_context_init(struct ar_context *ctx,
 826                            struct fw_ohci *ohci, u32 regs)
 827 {
 828         struct ar_buffer ab;
 829
 830         ctx->regs        = regs;
 831         ctx->ohci        = ohci;
 832         ctx->last_buffer = &ab;
 833         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 834
 835         ar_context_add_page(ctx);
 836         ar_context_add_page(ctx);
 837         ctx->current_buffer = ab.next;
 838         ctx->pointer = ctx->current_buffer->data;
 839
 840         return 0;
 841 }
 842
 843 static void ar_context_run(struct ar_context *ctx)
 844 {
 845         struct ar_buffer *ab = ctx->current_buffer;
 846         dma_addr_t ab_bus;
 847         size_t offset;
 848
 849         offset = offsetof(struct ar_buffer, data);
 850         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 851
 852         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 853         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 854         flush_writes(ctx->ohci);
 855 }
 856
 857 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 858 {
 859         int b, key;
 860
 861         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 862         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 863
 864         /* figure out which descriptor the branch address goes in */
 865         if (z == 2 && (b == 3 || key == 2))
 866                 return d;
 867         else
 868                 return d + z - 1;
 869 }
 870
 871 static void context_tasklet(unsigned long data)
 872 {
 873         struct context *ctx = (struct context *) data;
 874         struct descriptor *d, *last;
 875         u32 address;
 876         int z;
 877         struct descriptor_buffer *desc;
 878
 879         desc = list_entry(ctx->buffer_list.next,
 880                         struct descriptor_buffer, list);
 881         last = ctx->last;
 882         while (last->branch_address != 0) {
 883                 struct descriptor_buffer *old_desc = desc;
 884                 address = le32_to_cpu(last->branch_address);
 885                 z = address & 0xf;
 886                 address &= ~0xf;
 887
 888                 /* If the branch address points to a buffer outside of the
 889                  * current buffer, advance to the next buffer. */
 890                 if (address < desc->buffer_bus ||
 891                                 address >= desc->buffer_bus + desc->used)
 892                         desc = list_entry(desc->list.next,
 893                                         struct descriptor_buffer, list);
 894                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 895                 last = find_branch_descriptor(d, z);
 896
 897                 if (!ctx->callback(ctx, d, last))
 898                         break;
 899
 900                 if (old_desc != desc) {
 901                         /* If we've advanced to the next buffer, move the
 902                          * previous buffer to the free list. */
 903                         unsigned long flags;
 904                         old_desc->used = 0;
 905                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 906                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 907                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 908                 }
 909                 ctx->last = last;
 910         }
 911 }
 912
 913 /*
 914  * Allocate a new buffer and add it to the list of free buffers for this
 915  * context.  Must be called with ohci->lock held.
 916  */
 917 static int context_add_buffer(struct context *ctx)
 918 {
 919         struct descriptor_buffer *desc;
 920         dma_addr_t uninitialized_var(bus_addr);
 921         int offset;
 922
 923         /*
 924          * 16MB of descriptors should be far more than enough for any DMA
 925          * program.  This will catch run-away userspace or DoS attacks.
 926          */
 927         if (ctx->total_allocation >= 16*1024*1024)
 928                 return -ENOMEM;
 929
 930         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 931                         &bus_addr, GFP_ATOMIC);
 932         if (!desc)
 933                 return -ENOMEM;
 934
 935         offset = (void *)&desc->buffer - (void *)desc;
 936         desc->buffer_size = PAGE_SIZE - offset;
 937         desc->buffer_bus = bus_addr + offset;
 938         desc->used = 0;
 939
 940         list_add_tail(&desc->list, &ctx->buffer_list);
 941         ctx->total_allocation += PAGE_SIZE;
 942
 943         return 0;
 944 }
 945
 946 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 947                         u32 regs, descriptor_callback_t callback)
 948 {
 949         ctx->ohci = ohci;
 950         ctx->regs = regs;
 951         ctx->total_allocation = 0;
 952
 953         INIT_LIST_HEAD(&ctx->buffer_list);
 954         if (context_add_buffer(ctx) < 0)
 955                 return -ENOMEM;
 956
 957         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 958                         struct descriptor_buffer, list);
 959
 960         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 961         ctx->callback = callback;
 962
 963         /*
 964          * We put a dummy descriptor in the buffer that has a NULL
 965          * branch address and looks like it's been sent.  That way we
 966          * have a descriptor to append DMA programs to.
 967          */
 968         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 969         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 970         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 971         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 972         ctx->last = ctx->buffer_tail->buffer;
 973         ctx->prev = ctx->buffer_tail->buffer;
 974
 975         return 0;
 976 }
 977
 978 static void context_release(struct context *ctx)
 979 {
 980         struct fw_card *card = &ctx->ohci->card;
 981         struct descriptor_buffer *desc, *tmp;
 982
 983         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 984                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 985                         desc->buffer_bus -
 986                         ((void *)&desc->buffer - (void *)desc));
 987 }
 988
 989 /* Must be called with ohci->lock held */
 990 static struct descriptor *context_get_descriptors(struct context *ctx,
 991                                                   int z, dma_addr_t *d_bus)
 992 {
 993         struct descriptor *d = NULL;
 994         struct descriptor_buffer *desc = ctx->buffer_tail;
 995
 996         if (z * sizeof(*d) > desc->buffer_size)
 997                 return NULL;
 998
 999         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1000                 /* No room for the descriptor in this buffer, so advance to the
1001                  * next one. */
1002
1003                 if (desc->list.next == &ctx->buffer_list) {
1004                         /* If there is no free buffer next in the list,
1005                          * allocate one. */
1006                         if (context_add_buffer(ctx) < 0)
1007                                 return NULL;
1008                 }
1009                 desc = list_entry(desc->list.next,
1010                                 struct descriptor_buffer, list);
1011                 ctx->buffer_tail = desc;
1012         }
1013
1014         d = desc->buffer + desc->used / sizeof(*d);
1015         memset(d, 0, z * sizeof(*d));
1016         *d_bus = desc->buffer_bus + desc->used;
1017
1018         return d;
1019 }
1020
1021 static void context_run(struct context *ctx, u32 extra)
1022 {
1023         struct fw_ohci *ohci = ctx->ohci;
1024
1025         reg_write(ohci, COMMAND_PTR(ctx->regs),
1026                   le32_to_cpu(ctx->last->branch_address));
1027         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1028         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1029         flush_writes(ohci);
1030 }
1031
1032 static void context_append(struct context *ctx,
1033                            struct descriptor *d, int z, int extra)
1034 {
1035         dma_addr_t d_bus;
1036         struct descriptor_buffer *desc = ctx->buffer_tail;
1037
1038         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1039
1040         desc->used += (z + extra) * sizeof(*d);
1041
1042         wmb(); /* finish init of new descriptors before branch_address update */
1043         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1044         ctx->prev = find_branch_descriptor(d, z);
1045
1046         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1047         flush_writes(ctx->ohci);
1048 }
1049
1050 static void context_stop(struct context *ctx)
1051 {
1052         u32 reg;
1053         int i;
1054
1055         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1056         flush_writes(ctx->ohci);
1057
1058         for (i = 0; i < 10; i++) {
1059                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1060                 if ((reg & CONTEXT_ACTIVE) == 0)
1061                         return;
1062
1063                 mdelay(1);
1064         }
1065         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1066 }
1067
1068 struct driver_data {
1069         struct fw_packet *packet;
1070 };
1071
1072 /*
1073  * This function apppends a packet to the DMA queue for transmission.
1074  * Must always be called with the ochi->lock held to ensure proper
1075  * generation handling and locking around packet queue manipulation.
1076  */
1077 static int at_context_queue_packet(struct context *ctx,
1078                                    struct fw_packet *packet)
1079 {
1080         struct fw_ohci *ohci = ctx->ohci;
1081         dma_addr_t d_bus, uninitialized_var(payload_bus);
1082         struct driver_data *driver_data;
1083         struct descriptor *d, *last;
1084         __le32 *header;
1085         int z, tcode;
1086         u32 reg;
1087
1088         d = context_get_descriptors(ctx, 4, &d_bus);
1089         if (d == NULL) {
1090                 packet->ack = RCODE_SEND_ERROR;
1091                 return -1;
1092         }
1093
1094         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1095         d[0].res_count = cpu_to_le16(packet->timestamp);
1096
1097         /*
1098          * The DMA format for asyncronous link packets is different
1099          * from the IEEE1394 layout, so shift the fields around
1100          * accordingly.  If header_length is 8, it's a PHY packet, to
1101          * which we need to prepend an extra quadlet.
1102          */
1103
1104         header = (__le32 *) &d[1];
1105         switch (packet->header_length) {
1106         case 16:
1107         case 12:
1108                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1109                                         (packet->speed << 16));
1110                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1111                                         (packet->header[0] & 0xffff0000));
1112                 header[2] = cpu_to_le32(packet->header[2]);
1113
1114                 tcode = (packet->header[0] >> 4) & 0x0f;
1115                 if (TCODE_IS_BLOCK_PACKET(tcode))
1116                         header[3] = cpu_to_le32(packet->header[3]);
1117                 else
1118                         header[3] = (__force __le32) packet->header[3];
1119
1120                 d[0].req_count = cpu_to_le16(packet->header_length);
1121                 break;
1122
1123         case 8:
1124                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1125                                         (packet->speed << 16));
1126                 header[1] = cpu_to_le32(packet->header[0]);
1127                 header[2] = cpu_to_le32(packet->header[1]);
1128                 d[0].req_count = cpu_to_le16(12);
1129
1130                 if (is_ping_packet(packet->header))
1131                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1132                 break;
1133
1134         case 4:
1135                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1136                                         (packet->speed << 16));
1137                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1138                 d[0].req_count = cpu_to_le16(8);
1139                 break;
1140
1141         default:
1142                 /* BUG(); */
1143                 packet->ack = RCODE_SEND_ERROR;
1144                 return -1;
1145         }
1146
1147         driver_data = (struct driver_data *) &d[3];
1148         driver_data->packet = packet;
1149         packet->driver_data = driver_data;
1150
1151         if (packet->payload_length > 0) {
1152                 payload_bus =
1153                         dma_map_single(ohci->card.device, packet->payload,
1154                                        packet->payload_length, DMA_TO_DEVICE);
1155                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1156                         packet->ack = RCODE_SEND_ERROR;
1157                         return -1;
1158                 }
1159                 packet->payload_bus     = payload_bus;
1160                 packet->payload_mapped  = true;
1161
1162                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1163                 d[2].data_address = cpu_to_le32(payload_bus);
1164                 last = &d[2];
1165                 z = 3;
1166         } else {
1167                 last = &d[0];
1168                 z = 2;
1169         }
1170
1171         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1172                                      DESCRIPTOR_IRQ_ALWAYS |
1173                                      DESCRIPTOR_BRANCH_ALWAYS);
1174
1175         /*
1176          * If the controller and packet generations don't match, we need to
1177          * bail out and try again.  If IntEvent.busReset is set, the AT context
1178          * is halted, so appending to the context and trying to run it is
1179          * futile.  Most controllers do the right thing and just flush the AT
1180          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1181          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1182          * up stalling out.  So we just bail out in software and try again
1183          * later, and everyone is happy.
1184          * FIXME: Document how the locking works.
1185          */
1186         if (ohci->generation != packet->generation ||
1187             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1188                 if (packet->payload_mapped)
1189                         dma_unmap_single(ohci->card.device, payload_bus,
1190                                          packet->payload_length, DMA_TO_DEVICE);
1191                 packet->ack = RCODE_GENERATION;
1192                 return -1;
1193         }
1194
1195         context_append(ctx, d, z, 4 - z);
1196
1197         /* If the context isn't already running, start it up. */
1198         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1199         if ((reg & CONTEXT_RUN) == 0)
1200                 context_run(ctx, 0);
1201
1202         return 0;
1203 }
1204
1205 static int handle_at_packet(struct context *context,
1206                             struct descriptor *d,
1207                             struct descriptor *last)
1208 {
1209         struct driver_data *driver_data;
1210         struct fw_packet *packet;
1211         struct fw_ohci *ohci = context->ohci;
1212         int evt;
1213
1214         if (last->transfer_status == 0)
1215                 /* This descriptor isn't done yet, stop iteration. */
1216                 return 0;
1217
1218         driver_data = (struct driver_data *) &d[3];
1219         packet = driver_data->packet;
1220         if (packet == NULL)
1221                 /* This packet was cancelled, just continue. */
1222                 return 1;
1223
1224         if (packet->payload_mapped)
1225                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1226                                  packet->payload_length, DMA_TO_DEVICE);
1227
1228         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1229         packet->timestamp = le16_to_cpu(last->res_count);
1230
1231         log_ar_at_event('T', packet->speed, packet->header, evt);
1232
1233         switch (evt) {
1234         case OHCI1394_evt_timeout:
1235                 /* Async response transmit timed out. */
1236                 packet->ack = RCODE_CANCELLED;
1237                 break;
1238
1239         case OHCI1394_evt_flushed:
1240                 /*
1241                  * The packet was flushed should give same error as
1242                  * when we try to use a stale generation count.
1243                  */
1244                 packet->ack = RCODE_GENERATION;
1245                 break;
1246
1247         case OHCI1394_evt_missing_ack:
1248                 /*
1249                  * Using a valid (current) generation count, but the
1250                  * node is not on the bus or not sending acks.
1251                  */
1252                 packet->ack = RCODE_NO_ACK;
1253                 break;
1254
1255         case ACK_COMPLETE + 0x10:
1256         case ACK_PENDING + 0x10:
1257         case ACK_BUSY_X + 0x10:
1258         case ACK_BUSY_A + 0x10:
1259         case ACK_BUSY_B + 0x10:
1260         case ACK_DATA_ERROR + 0x10:
1261         case ACK_TYPE_ERROR + 0x10:
1262                 packet->ack = evt - 0x10;
1263                 break;
1264
1265         default:
1266                 packet->ack = RCODE_SEND_ERROR;
1267                 break;
1268         }
1269
1270         packet->callback(packet, &ohci->card, packet->ack);
1271
1272         return 1;
1273 }
1274
1275 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1276 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1277 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1278 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1279 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1280
1281 static void handle_local_rom(struct fw_ohci *ohci,
1282                              struct fw_packet *packet, u32 csr)
1283 {
1284         struct fw_packet response;
1285         int tcode, length, i;
1286
1287         tcode = HEADER_GET_TCODE(packet->header[0]);
1288         if (TCODE_IS_BLOCK_PACKET(tcode))
1289                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1290         else
1291                 length = 4;
1292
1293         i = csr - CSR_CONFIG_ROM;
1294         if (i + length > CONFIG_ROM_SIZE) {
1295                 fw_fill_response(&response, packet->header,
1296                                  RCODE_ADDRESS_ERROR, NULL, 0);
1297         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1298                 fw_fill_response(&response, packet->header,
1299                                  RCODE_TYPE_ERROR, NULL, 0);
1300         } else {
1301                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1302                                  (void *) ohci->config_rom + i, length);
1303         }
1304
1305         fw_core_handle_response(&ohci->card, &response);
1306 }
1307
1308 static void handle_local_lock(struct fw_ohci *ohci,
1309                               struct fw_packet *packet, u32 csr)
1310 {
1311         struct fw_packet response;
1312         int tcode, length, ext_tcode, sel, try;
1313         __be32 *payload, lock_old;
1314         u32 lock_arg, lock_data;
1315
1316         tcode = HEADER_GET_TCODE(packet->header[0]);
1317         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1318         payload = packet->payload;
1319         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1320
1321         if (tcode == TCODE_LOCK_REQUEST &&
1322             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1323                 lock_arg = be32_to_cpu(payload[0]);
1324                 lock_data = be32_to_cpu(payload[1]);
1325         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1326                 lock_arg = 0;
1327                 lock_data = 0;
1328         } else {
1329                 fw_fill_response(&response, packet->header,
1330                                  RCODE_TYPE_ERROR, NULL, 0);
1331                 goto out;
1332         }
1333
1334         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1335         reg_write(ohci, OHCI1394_CSRData, lock_data);
1336         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1337         reg_write(ohci, OHCI1394_CSRControl, sel);
1338
1339         for (try = 0; try < 20; try++)
1340                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1341                         lock_old = cpu_to_be32(reg_read(ohci,
1342                                                         OHCI1394_CSRData));
1343                         fw_fill_response(&response, packet->header,
1344                                          RCODE_COMPLETE,
1345                                          &lock_old, sizeof(lock_old));
1346                         goto out;
1347                 }
1348
1349         fw_error("swap not done (CSR lock timeout)\n");
1350         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1351
1352  out:
1353         fw_core_handle_response(&ohci->card, &response);
1354 }
1355
1356 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1357 {
1358         u64 offset, csr;
1359
1360         if (ctx == &ctx->ohci->at_request_ctx) {
1361                 packet->ack = ACK_PENDING;
1362                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1363         }
1364
1365         offset =
1366                 ((unsigned long long)
1367                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1368                 packet->header[2];
1369         csr = offset - CSR_REGISTER_BASE;
1370
1371         /* Handle config rom reads. */
1372         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1373                 handle_local_rom(ctx->ohci, packet, csr);
1374         else switch (csr) {
1375         case CSR_BUS_MANAGER_ID:
1376         case CSR_BANDWIDTH_AVAILABLE:
1377         case CSR_CHANNELS_AVAILABLE_HI:
1378         case CSR_CHANNELS_AVAILABLE_LO:
1379                 handle_local_lock(ctx->ohci, packet, csr);
1380                 break;
1381         default:
1382                 if (ctx == &ctx->ohci->at_request_ctx)
1383                         fw_core_handle_request(&ctx->ohci->card, packet);
1384                 else
1385                         fw_core_handle_response(&ctx->ohci->card, packet);
1386                 break;
1387         }
1388
1389         if (ctx == &ctx->ohci->at_response_ctx) {
1390                 packet->ack = ACK_COMPLETE;
1391                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1392         }
1393 }
1394
1395 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1396 {
1397         unsigned long flags;
1398         int ret;
1399
1400         spin_lock_irqsave(&ctx->ohci->lock, flags);
1401
1402         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1403             ctx->ohci->generation == packet->generation) {
1404                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1405                 handle_local_request(ctx, packet);
1406                 return;
1407         }
1408
1409         ret = at_context_queue_packet(ctx, packet);
1410         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1411
1412         if (ret < 0)
1413                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1414
1415 }
1416
1417 static u32 cycle_timer_ticks(u32 cycle_timer)
1418 {
1419         u32 ticks;
1420
1421         ticks = cycle_timer & 0xfff;
1422         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1423         ticks += (3072 * 8000) * (cycle_timer >> 25);
1424
1425         return ticks;
1426 }
1427
1428 /*
1429  * Some controllers exhibit one or more of the following bugs when updating the
1430  * iso cycle timer register:
1431  *  - When the lowest six bits are wrapping around to zero, a read that happens
1432  *    at the same time will return garbage in the lowest ten bits.
1433  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1434  *    not incremented for about 60 ns.
1435  *  - Occasionally, the entire register reads zero.
1436  *
1437  * To catch these, we read the register three times and ensure that the
1438  * difference between each two consecutive reads is approximately the same, i.e.
1439  * less than twice the other.  Furthermore, any negative difference indicates an
1440  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1441  * execute, so we have enough precision to compute the ratio of the differences.)
1442  */
1443 static u32 get_cycle_time(struct fw_ohci *ohci)
1444 {
1445         u32 c0, c1, c2;
1446         u32 t0, t1, t2;
1447         s32 diff01, diff12;
1448         int i;
1449
1450         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1451
1452         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1453                 i = 0;
1454                 c1 = c2;
1455                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1456                 do {
1457                         c0 = c1;
1458                         c1 = c2;
1459                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1460                         t0 = cycle_timer_ticks(c0);
1461                         t1 = cycle_timer_ticks(c1);
1462                         t2 = cycle_timer_ticks(c2);
1463                         diff01 = t1 - t0;
1464                         diff12 = t2 - t1;
1465                 } while ((diff01 <= 0 || diff12 <= 0 ||
1466                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1467                          && i++ < 20);
1468         }
1469
1470         return c2;
1471 }
1472
1473 /*
1474  * This function has to be called at least every 64 seconds.  The bus_time
1475  * field stores not only the upper 25 bits of the BUS_TIME register but also
1476  * the most significant bit of the cycle timer in bit 6 so that we can detect
1477  * changes in this bit.
1478  */
1479 static u32 update_bus_time(struct fw_ohci *ohci)
1480 {
1481         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1482
1483         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1484                 ohci->bus_time += 0x40;
1485
1486         return ohci->bus_time | cycle_time_seconds;
1487 }
1488
1489 static void bus_reset_tasklet(unsigned long data)
1490 {
1491         struct fw_ohci *ohci = (struct fw_ohci *)data;
1492         int self_id_count, i, j, reg;
1493         int generation, new_generation;
1494         unsigned long flags;
1495         void *free_rom = NULL;
1496         dma_addr_t free_rom_bus = 0;
1497         bool is_new_root;
1498
1499         reg = reg_read(ohci, OHCI1394_NodeID);
1500         if (!(reg & OHCI1394_NodeID_idValid)) {
1501                 fw_notify("node ID not valid, new bus reset in progress\n");
1502                 return;
1503         }
1504         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1505                 fw_notify("malconfigured bus\n");
1506                 return;
1507         }
1508         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1509                                OHCI1394_NodeID_nodeNumber);
1510
1511         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1512         if (!(ohci->is_root && is_new_root))
1513                 reg_write(ohci, OHCI1394_LinkControlSet,
1514                           OHCI1394_LinkControl_cycleMaster);
1515         ohci->is_root = is_new_root;
1516
1517         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1518         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1519                 fw_notify("inconsistent self IDs\n");
1520                 return;
1521         }
1522         /*
1523          * The count in the SelfIDCount register is the number of
1524          * bytes in the self ID receive buffer.  Since we also receive
1525          * the inverted quadlets and a header quadlet, we shift one
1526          * bit extra to get the actual number of self IDs.
1527          */
1528         self_id_count = (reg >> 3) & 0xff;
1529         if (self_id_count == 0 || self_id_count > 252) {
1530                 fw_notify("inconsistent self IDs\n");
1531                 return;
1532         }
1533         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1534         rmb();
1535
1536         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1537                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1538                         fw_notify("inconsistent self IDs\n");
1539                         return;
1540                 }
1541                 ohci->self_id_buffer[j] =
1542                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1543         }
1544         rmb();
1545
1546         /*
1547          * Check the consistency of the self IDs we just read.  The
1548          * problem we face is that a new bus reset can start while we
1549          * read out the self IDs from the DMA buffer. If this happens,
1550          * the DMA buffer will be overwritten with new self IDs and we
1551          * will read out inconsistent data.  The OHCI specification
1552          * (section 11.2) recommends a technique similar to
1553          * linux/seqlock.h, where we remember the generation of the
1554          * self IDs in the buffer before reading them out and compare
1555          * it to the current generation after reading them out.  If
1556          * the two generations match we know we have a consistent set
1557          * of self IDs.
1558          */
1559
1560         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1561         if (new_generation != generation) {
1562                 fw_notify("recursive bus reset detected, "
1563                           "discarding self ids\n");
1564                 return;
1565         }
1566
1567         /* FIXME: Document how the locking works. */
1568         spin_lock_irqsave(&ohci->lock, flags);
1569
1570         ohci->generation = generation;
1571         context_stop(&ohci->at_request_ctx);
1572         context_stop(&ohci->at_response_ctx);
1573         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1574
1575         if (ohci->quirks & QUIRK_RESET_PACKET)
1576                 ohci->request_generation = generation;
1577
1578         /*
1579          * This next bit is unrelated to the AT context stuff but we
1580          * have to do it under the spinlock also.  If a new config rom
1581          * was set up before this reset, the old one is now no longer
1582          * in use and we can free it. Update the config rom pointers
1583          * to point to the current config rom and clear the
1584          * next_config_rom pointer so a new update can take place.
1585          */
1586
1587         if (ohci->next_config_rom != NULL) {
1588                 if (ohci->next_config_rom != ohci->config_rom) {
1589                         free_rom      = ohci->config_rom;
1590                         free_rom_bus  = ohci->config_rom_bus;
1591                 }
1592                 ohci->config_rom      = ohci->next_config_rom;
1593                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1594                 ohci->next_config_rom = NULL;
1595
1596                 /*
1597                  * Restore config_rom image and manually update
1598                  * config_rom registers.  Writing the header quadlet
1599                  * will indicate that the config rom is ready, so we
1600                  * do that last.
1601                  */
1602                 reg_write(ohci, OHCI1394_BusOptions,
1603                           be32_to_cpu(ohci->config_rom[2]));
1604                 ohci->config_rom[0] = ohci->next_header;
1605                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1606                           be32_to_cpu(ohci->next_header));
1607         }
1608
1609 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1610         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1611         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1612 #endif
1613
1614         spin_unlock_irqrestore(&ohci->lock, flags);
1615
1616         if (free_rom)
1617                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1618                                   free_rom, free_rom_bus);
1619
1620         log_selfids(ohci->node_id, generation,
1621                     self_id_count, ohci->self_id_buffer);
1622
1623         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1624                                  self_id_count, ohci->self_id_buffer,
1625                                  ohci->csr_state_setclear_abdicate);
1626         ohci->csr_state_setclear_abdicate = false;
1627 }
1628
1629 static irqreturn_t irq_handler(int irq, void *data)
1630 {
1631         struct fw_ohci *ohci = data;
1632         u32 event, iso_event;
1633         int i;
1634
1635         event = reg_read(ohci, OHCI1394_IntEventClear);
1636
1637         if (!event || !~event)
1638                 return IRQ_NONE;
1639
1640         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1641         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1642         log_irqs(event);
1643
1644         if (event & OHCI1394_selfIDComplete)
1645                 tasklet_schedule(&ohci->bus_reset_tasklet);
1646
1647         if (event & OHCI1394_RQPkt)
1648                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1649
1650         if (event & OHCI1394_RSPkt)
1651                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1652
1653         if (event & OHCI1394_reqTxComplete)
1654                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1655
1656         if (event & OHCI1394_respTxComplete)
1657                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1658
1659         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1660         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1661
1662         while (iso_event) {
1663                 i = ffs(iso_event) - 1;
1664                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1665                 iso_event &= ~(1 << i);
1666         }
1667
1668         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1669         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1670
1671         while (iso_event) {
1672                 i = ffs(iso_event) - 1;
1673                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1674                 iso_event &= ~(1 << i);
1675         }
1676
1677         if (unlikely(event & OHCI1394_regAccessFail))
1678                 fw_error("Register access failure - "
1679                          "please notify linux1394-devel@lists.sf.net\n");
1680
1681         if (unlikely(event & OHCI1394_postedWriteErr))
1682                 fw_error("PCI posted write error\n");
1683
1684         if (unlikely(event & OHCI1394_cycleTooLong)) {
1685                 if (printk_ratelimit())
1686                         fw_notify("isochronous cycle too long\n");
1687                 reg_write(ohci, OHCI1394_LinkControlSet,
1688                           OHCI1394_LinkControl_cycleMaster);
1689         }
1690
1691         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1692                 /*
1693                  * We need to clear this event bit in order to make
1694                  * cycleMatch isochronous I/O work.  In theory we should
1695                  * stop active cycleMatch iso contexts now and restart
1696                  * them at least two cycles later.  (FIXME?)
1697                  */
1698                 if (printk_ratelimit())
1699                         fw_notify("isochronous cycle inconsistent\n");
1700         }
1701
1702         if (event & OHCI1394_cycle64Seconds) {
1703                 spin_lock(&ohci->lock);
1704                 update_bus_time(ohci);
1705                 spin_unlock(&ohci->lock);
1706         }
1707
1708         return IRQ_HANDLED;
1709 }
1710
1711 static int software_reset(struct fw_ohci *ohci)
1712 {
1713         int i;
1714
1715         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1716
1717         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1718                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1719                      OHCI1394_HCControl_softReset) == 0)
1720                         return 0;
1721                 msleep(1);
1722         }
1723
1724         return -EBUSY;
1725 }
1726
1727 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1728 {
1729         size_t size = length * 4;
1730
1731         memcpy(dest, src, size);
1732         if (size < CONFIG_ROM_SIZE)
1733                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1734 }
1735
1736 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1737 {
1738         bool enable_1394a;
1739         int ret, clear, set, offset;
1740
1741         /* Check if the driver should configure link and PHY. */
1742         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1743               OHCI1394_HCControl_programPhyEnable))
1744                 return 0;
1745
1746         /* Paranoia: check whether the PHY supports 1394a, too. */
1747         enable_1394a = false;
1748         ret = read_phy_reg(ohci, 2);
1749         if (ret < 0)
1750                 return ret;
1751         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1752                 ret = read_paged_phy_reg(ohci, 1, 8);
1753                 if (ret < 0)
1754                         return ret;
1755                 if (ret >= 1)
1756                         enable_1394a = true;
1757         }
1758
1759         if (ohci->quirks & QUIRK_NO_1394A)
1760                 enable_1394a = false;
1761
1762         /* Configure PHY and link consistently. */
1763         if (enable_1394a) {
1764                 clear = 0;
1765                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1766         } else {
1767                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1768                 set = 0;
1769         }
1770         ret = update_phy_reg(ohci, 5, clear, set);
1771         if (ret < 0)
1772                 return ret;
1773
1774         if (enable_1394a)
1775                 offset = OHCI1394_HCControlSet;
1776         else
1777                 offset = OHCI1394_HCControlClear;
1778         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1779
1780         /* Clean up: configuration has been taken care of. */
1781         reg_write(ohci, OHCI1394_HCControlClear,
1782                   OHCI1394_HCControl_programPhyEnable);
1783
1784         return 0;
1785 }
1786
1787 static int ohci_enable(struct fw_card *card,
1788                        const __be32 *config_rom, size_t length)
1789 {
1790         struct fw_ohci *ohci = fw_ohci(card);
1791         struct pci_dev *dev = to_pci_dev(card->device);
1792         u32 lps, seconds, version, irqs;
1793         int i, ret;
1794
1795         if (software_reset(ohci)) {
1796                 fw_error("Failed to reset ohci card.\n");
1797                 return -EBUSY;
1798         }
1799
1800         /*
1801          * Now enable LPS, which we need in order to start accessing
1802          * most of the registers.  In fact, on some cards (ALI M5251),
1803          * accessing registers in the SClk domain without LPS enabled
1804          * will lock up the machine.  Wait 50msec to make sure we have
1805          * full link enabled.  However, with some cards (well, at least
1806          * a JMicron PCIe card), we have to try again sometimes.
1807          */
1808         reg_write(ohci, OHCI1394_HCControlSet,
1809                   OHCI1394_HCControl_LPS |
1810                   OHCI1394_HCControl_postedWriteEnable);
1811         flush_writes(ohci);
1812
1813         for (lps = 0, i = 0; !lps && i < 3; i++) {
1814                 msleep(50);
1815                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1816                       OHCI1394_HCControl_LPS;
1817         }
1818
1819         if (!lps) {
1820                 fw_error("Failed to set Link Power Status\n");
1821                 return -EIO;
1822         }
1823
1824         reg_write(ohci, OHCI1394_HCControlClear,
1825                   OHCI1394_HCControl_noByteSwapData);
1826
1827         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1828         reg_write(ohci, OHCI1394_LinkControlSet,
1829                   OHCI1394_LinkControl_rcvSelfID |
1830                   OHCI1394_LinkControl_rcvPhyPkt |
1831                   OHCI1394_LinkControl_cycleTimerEnable |
1832                   OHCI1394_LinkControl_cycleMaster);
1833
1834         reg_write(ohci, OHCI1394_ATRetries,
1835                   OHCI1394_MAX_AT_REQ_RETRIES |
1836                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1837                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1838                   (200 << 16));
1839
1840         seconds = lower_32_bits(get_seconds());
1841         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1842         ohci->bus_time = seconds & ~0x3f;
1843
1844         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1845         if (version >= OHCI_VERSION_1_1) {
1846                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1847                           0xfffffffe);
1848                 card->broadcast_channel_auto_allocated = true;
1849         }
1850
1851         /* Get implemented bits of the priority arbitration request counter. */
1852         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1853         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1854         reg_write(ohci, OHCI1394_FairnessControl, 0);
1855         card->priority_budget_implemented = ohci->pri_req_max != 0;
1856
1857         ar_context_run(&ohci->ar_request_ctx);
1858         ar_context_run(&ohci->ar_response_ctx);
1859
1860         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1861         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1862         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1863
1864         ret = configure_1394a_enhancements(ohci);
1865         if (ret < 0)
1866                 return ret;
1867
1868         /* Activate link_on bit and contender bit in our self ID packets.*/
1869         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1870         if (ret < 0)
1871                 return ret;
1872
1873         /*
1874          * When the link is not yet enabled, the atomic config rom
1875          * update mechanism described below in ohci_set_config_rom()
1876          * is not active.  We have to update ConfigRomHeader and
1877          * BusOptions manually, and the write to ConfigROMmap takes
1878          * effect immediately.  We tie this to the enabling of the
1879          * link, so we have a valid config rom before enabling - the
1880          * OHCI requires that ConfigROMhdr and BusOptions have valid
1881          * values before enabling.
1882          *
1883          * However, when the ConfigROMmap is written, some controllers
1884          * always read back quadlets 0 and 2 from the config rom to
1885          * the ConfigRomHeader and BusOptions registers on bus reset.
1886          * They shouldn't do that in this initial case where the link
1887          * isn't enabled.  This means we have to use the same
1888          * workaround here, setting the bus header to 0 and then write
1889          * the right values in the bus reset tasklet.
1890          */
1891
1892         if (config_rom) {
1893                 ohci->next_config_rom =
1894                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1895                                            &ohci->next_config_rom_bus,
1896                                            GFP_KERNEL);
1897                 if (ohci->next_config_rom == NULL)
1898                         return -ENOMEM;
1899
1900                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1901         } else {
1902                 /*
1903                  * In the suspend case, config_rom is NULL, which
1904                  * means that we just reuse the old config rom.
1905                  */
1906                 ohci->next_config_rom = ohci->config_rom;
1907                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1908         }
1909
1910         ohci->next_header = ohci->next_config_rom[0];
1911         ohci->next_config_rom[0] = 0;
1912         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1913         reg_write(ohci, OHCI1394_BusOptions,
1914                   be32_to_cpu(ohci->next_config_rom[2]));
1915         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1916
1917         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1918
1919         if (!(ohci->quirks & QUIRK_NO_MSI))
1920                 pci_enable_msi(dev);
1921         if (request_irq(dev->irq, irq_handler,
1922                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1923                         ohci_driver_name, ohci)) {
1924                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1925                 pci_disable_msi(dev);
1926                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1927                                   ohci->config_rom, ohci->config_rom_bus);
1928                 return -EIO;
1929         }
1930
1931         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1932                 OHCI1394_RQPkt | OHCI1394_RSPkt |
1933                 OHCI1394_isochTx | OHCI1394_isochRx |
1934                 OHCI1394_postedWriteErr |
1935                 OHCI1394_selfIDComplete |
1936                 OHCI1394_regAccessFail |
1937                 OHCI1394_cycle64Seconds |
1938                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1939                 OHCI1394_masterIntEnable;
1940         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1941                 irqs |= OHCI1394_busReset;
1942         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1943
1944         reg_write(ohci, OHCI1394_HCControlSet,
1945                   OHCI1394_HCControl_linkEnable |
1946                   OHCI1394_HCControl_BIBimageValid);
1947         flush_writes(ohci);
1948
1949         /* We are ready to go, reset bus to finish initialization. */
1950         fw_schedule_bus_reset(&ohci->card, false, true);
1951
1952         return 0;
1953 }
1954
1955 static int ohci_set_config_rom(struct fw_card *card,
1956                                const __be32 *config_rom, size_t length)
1957 {
1958         struct fw_ohci *ohci;
1959         unsigned long flags;
1960         int ret = -EBUSY;
1961         __be32 *next_config_rom;
1962         dma_addr_t uninitialized_var(next_config_rom_bus);
1963
1964         ohci = fw_ohci(card);
1965
1966         /*
1967          * When the OHCI controller is enabled, the config rom update
1968          * mechanism is a bit tricky, but easy enough to use.  See
1969          * section 5.5.6 in the OHCI specification.
1970          *
1971          * The OHCI controller caches the new config rom address in a
1972          * shadow register (ConfigROMmapNext) and needs a bus reset
1973          * for the changes to take place.  When the bus reset is
1974          * detected, the controller loads the new values for the
1975          * ConfigRomHeader and BusOptions registers from the specified
1976          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1977          * shadow register. All automatically and atomically.
1978          *
1979          * Now, there's a twist to this story.  The automatic load of
1980          * ConfigRomHeader and BusOptions doesn't honor the
1981          * noByteSwapData bit, so with a be32 config rom, the
1982          * controller will load be32 values in to these registers
1983          * during the atomic update, even on litte endian
1984          * architectures.  The workaround we use is to put a 0 in the
1985          * header quadlet; 0 is endian agnostic and means that the
1986          * config rom isn't ready yet.  In the bus reset tasklet we
1987          * then set up the real values for the two registers.
1988          *
1989          * We use ohci->lock to avoid racing with the code that sets
1990          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1991          */
1992
1993         next_config_rom =
1994                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1995                                    &next_config_rom_bus, GFP_KERNEL);
1996         if (next_config_rom == NULL)
1997                 return -ENOMEM;
1998
1999         spin_lock_irqsave(&ohci->lock, flags);
2000
2001         if (ohci->next_config_rom == NULL) {
2002                 ohci->next_config_rom = next_config_rom;
2003                 ohci->next_config_rom_bus = next_config_rom_bus;
2004
2005                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2006
2007                 ohci->next_header = config_rom[0];
2008                 ohci->next_config_rom[0] = 0;
2009
2010                 reg_write(ohci, OHCI1394_ConfigROMmap,
2011                           ohci->next_config_rom_bus);
2012                 ret = 0;
2013         }
2014
2015         spin_unlock_irqrestore(&ohci->lock, flags);
2016
2017         /*
2018          * Now initiate a bus reset to have the changes take
2019          * effect. We clean up the old config rom memory and DMA
2020          * mappings in the bus reset tasklet, since the OHCI
2021          * controller could need to access it before the bus reset
2022          * takes effect.
2023          */
2024         if (ret == 0)
2025                 fw_schedule_bus_reset(&ohci->card, true, true);
2026         else
2027                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2028                                   next_config_rom, next_config_rom_bus);
2029
2030         return ret;
2031 }
2032
2033 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2034 {
2035         struct fw_ohci *ohci = fw_ohci(card);
2036
2037         at_context_transmit(&ohci->at_request_ctx, packet);
2038 }
2039
2040 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2041 {
2042         struct fw_ohci *ohci = fw_ohci(card);
2043
2044         at_context_transmit(&ohci->at_response_ctx, packet);
2045 }
2046
2047 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2048 {
2049         struct fw_ohci *ohci = fw_ohci(card);
2050         struct context *ctx = &ohci->at_request_ctx;
2051         struct driver_data *driver_data = packet->driver_data;
2052         int ret = -ENOENT;
2053
2054         tasklet_disable(&ctx->tasklet);
2055
2056         if (packet->ack != 0)
2057                 goto out;
2058
2059         if (packet->payload_mapped)
2060                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2061                                  packet->payload_length, DMA_TO_DEVICE);
2062
2063         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2064         driver_data->packet = NULL;
2065         packet->ack = RCODE_CANCELLED;
2066         packet->callback(packet, &ohci->card, packet->ack);
2067         ret = 0;
2068  out:
2069         tasklet_enable(&ctx->tasklet);
2070
2071         return ret;
2072 }
2073
2074 static int ohci_enable_phys_dma(struct fw_card *card,
2075                                 int node_id, int generation)
2076 {
2077 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2078         return 0;
2079 #else
2080         struct fw_ohci *ohci = fw_ohci(card);
2081         unsigned long flags;
2082         int n, ret = 0;
2083
2084         /*
2085          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2086          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2087          */
2088
2089         spin_lock_irqsave(&ohci->lock, flags);
2090
2091         if (ohci->generation != generation) {
2092                 ret = -ESTALE;
2093                 goto out;
2094         }
2095
2096         /*
2097          * Note, if the node ID contains a non-local bus ID, physical DMA is
2098          * enabled for _all_ nodes on remote buses.
2099          */
2100
2101         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2102         if (n < 32)
2103                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2104         else
2105                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2106
2107         flush_writes(ohci);
2108  out:
2109         spin_unlock_irqrestore(&ohci->lock, flags);
2110
2111         return ret;
2112 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2113 }
2114
2115 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2116 {
2117         struct fw_ohci *ohci = fw_ohci(card);
2118         unsigned long flags;
2119         u32 value;
2120
2121         switch (csr_offset) {
2122         case CSR_STATE_CLEAR:
2123         case CSR_STATE_SET:
2124                 if (ohci->is_root &&
2125                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2126                      OHCI1394_LinkControl_cycleMaster))
2127                         value = CSR_STATE_BIT_CMSTR;
2128                 else
2129                         value = 0;
2130                 if (ohci->csr_state_setclear_abdicate)
2131                         value |= CSR_STATE_BIT_ABDICATE;
2132
2133                 return value;
2134
2135         case CSR_NODE_IDS:
2136                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2137
2138         case CSR_CYCLE_TIME:
2139                 return get_cycle_time(ohci);
2140
2141         case CSR_BUS_TIME:
2142                 /*
2143                  * We might be called just after the cycle timer has wrapped
2144                  * around but just before the cycle64Seconds handler, so we
2145                  * better check here, too, if the bus time needs to be updated.
2146                  */
2147                 spin_lock_irqsave(&ohci->lock, flags);
2148                 value = update_bus_time(ohci);
2149                 spin_unlock_irqrestore(&ohci->lock, flags);
2150                 return value;
2151
2152         case CSR_BUSY_TIMEOUT:
2153                 value = reg_read(ohci, OHCI1394_ATRetries);
2154                 return (value >> 4) & 0x0ffff00f;
2155
2156         case CSR_PRIORITY_BUDGET:
2157                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2158                         (ohci->pri_req_max << 8);
2159
2160         default:
2161                 WARN_ON(1);
2162                 return 0;
2163         }
2164 }
2165
2166 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2167 {
2168         struct fw_ohci *ohci = fw_ohci(card);
2169         unsigned long flags;
2170
2171         switch (csr_offset) {
2172         case CSR_STATE_CLEAR:
2173                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2174                         reg_write(ohci, OHCI1394_LinkControlClear,
2175                                   OHCI1394_LinkControl_cycleMaster);
2176                         flush_writes(ohci);
2177                 }
2178                 if (value & CSR_STATE_BIT_ABDICATE)
2179                         ohci->csr_state_setclear_abdicate = false;
2180                 break;
2181
2182         case CSR_STATE_SET:
2183                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2184                         reg_write(ohci, OHCI1394_LinkControlSet,
2185                                   OHCI1394_LinkControl_cycleMaster);
2186                         flush_writes(ohci);
2187                 }
2188                 if (value & CSR_STATE_BIT_ABDICATE)
2189                         ohci->csr_state_setclear_abdicate = true;
2190                 break;
2191
2192         case CSR_NODE_IDS:
2193                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2194                 flush_writes(ohci);
2195                 break;
2196
2197         case CSR_CYCLE_TIME:
2198                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2199                 reg_write(ohci, OHCI1394_IntEventSet,
2200                           OHCI1394_cycleInconsistent);
2201                 flush_writes(ohci);
2202                 break;
2203
2204         case CSR_BUS_TIME:
2205                 spin_lock_irqsave(&ohci->lock, flags);
2206                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2207                 spin_unlock_irqrestore(&ohci->lock, flags);
2208                 break;
2209
2210         case CSR_BUSY_TIMEOUT:
2211                 value = (value & 0xf) | ((value & 0xf) << 4) |
2212                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2213                 reg_write(ohci, OHCI1394_ATRetries, value);
2214                 flush_writes(ohci);
2215                 break;
2216
2217         case CSR_PRIORITY_BUDGET:
2218                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2219                 flush_writes(ohci);
2220                 break;
2221
2222         default:
2223                 WARN_ON(1);
2224                 break;
2225         }
2226 }
2227
2228 static void copy_iso_headers(struct iso_context *ctx, void *p)
2229 {
2230         int i = ctx->header_length;
2231
2232         if (i + ctx->base.header_size > PAGE_SIZE)
2233                 return;
2234
2235         /*
2236          * The iso header is byteswapped to little endian by
2237          * the controller, but the remaining header quadlets
2238          * are big endian.  We want to present all the headers
2239          * as big endian, so we have to swap the first quadlet.
2240          */
2241         if (ctx->base.header_size > 0)
2242                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2243         if (ctx->base.header_size > 4)
2244                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2245         if (ctx->base.header_size > 8)
2246                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2247         ctx->header_length += ctx->base.header_size;
2248 }
2249
2250 static int handle_ir_packet_per_buffer(struct context *context,
2251                                        struct descriptor *d,
2252                                        struct descriptor *last)
2253 {
2254         struct iso_context *ctx =
2255                 container_of(context, struct iso_context, context);
2256         struct descriptor *pd;
2257         __le32 *ir_header;
2258         void *p;
2259
2260         for (pd = d; pd <= last; pd++)
2261                 if (pd->transfer_status)
2262                         break;
2263         if (pd > last)
2264                 /* Descriptor(s) not done yet, stop iteration */
2265                 return 0;
2266
2267         p = last + 1;
2268         copy_iso_headers(ctx, p);
2269
2270         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2271                 ir_header = (__le32 *) p;
2272                 ctx->base.callback.sc(&ctx->base,
2273                                       le32_to_cpu(ir_header[0]) & 0xffff,
2274                                       ctx->header_length, ctx->header,
2275                                       ctx->base.callback_data);
2276                 ctx->header_length = 0;
2277         }
2278
2279         return 1;
2280 }
2281
2282 /* d == last because each descriptor block is only a single descriptor. */
2283 static int handle_ir_buffer_fill(struct context *context,
2284                                  struct descriptor *d,
2285                                  struct descriptor *last)
2286 {
2287         struct iso_context *ctx =
2288                 container_of(context, struct iso_context, context);
2289
2290         if (!last->transfer_status)
2291                 /* Descriptor(s) not done yet, stop iteration */
2292                 return 0;
2293
2294         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2295                 ctx->base.callback.mc(&ctx->base,
2296                                       le32_to_cpu(last->data_address) +
2297                                       le16_to_cpu(last->req_count) -
2298                                       le16_to_cpu(last->res_count),
2299                                       ctx->base.callback_data);
2300
2301         return 1;
2302 }
2303
2304 static int handle_it_packet(struct context *context,
2305                             struct descriptor *d,
2306                             struct descriptor *last)
2307 {
2308         struct iso_context *ctx =
2309                 container_of(context, struct iso_context, context);
2310         int i;
2311         struct descriptor *pd;
2312
2313         for (pd = d; pd <= last; pd++)
2314                 if (pd->transfer_status)
2315                         break;
2316         if (pd > last)
2317                 /* Descriptor(s) not done yet, stop iteration */
2318                 return 0;
2319
2320         i = ctx->header_length;
2321         if (i + 4 < PAGE_SIZE) {
2322                 /* Present this value as big-endian to match the receive code */
2323                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2324                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2325                                 le16_to_cpu(pd->res_count));
2326                 ctx->header_length += 4;
2327         }
2328         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2329                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2330                                       ctx->header_length, ctx->header,
2331                                       ctx->base.callback_data);
2332                 ctx->header_length = 0;
2333         }
2334         return 1;
2335 }
2336
2337 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2338 {
2339         u32 hi = channels >> 32, lo = channels;
2340
2341         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2342         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2343         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2344         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2345         mmiowb();
2346         ohci->mc_channels = channels;
2347 }
2348
2349 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2350                                 int type, int channel, size_t header_size)
2351 {
2352         struct fw_ohci *ohci = fw_ohci(card);
2353         struct iso_context *uninitialized_var(ctx);
2354         descriptor_callback_t uninitialized_var(callback);
2355         u64 *uninitialized_var(channels);
2356         u32 *uninitialized_var(mask), uninitialized_var(regs);
2357         unsigned long flags;
2358         int index, ret = -EBUSY;
2359
2360         spin_lock_irqsave(&ohci->lock, flags);
2361
2362         switch (type) {
2363         case FW_ISO_CONTEXT_TRANSMIT:
2364                 mask     = &ohci->it_context_mask;
2365                 callback = handle_it_packet;
2366                 index    = ffs(*mask) - 1;
2367                 if (index >= 0) {
2368                         *mask &= ~(1 << index);
2369                         regs = OHCI1394_IsoXmitContextBase(index);
2370                         ctx  = &ohci->it_context_list[index];
2371                 }
2372                 break;
2373
2374         case FW_ISO_CONTEXT_RECEIVE:
2375                 channels = &ohci->ir_context_channels;
2376                 mask     = &ohci->ir_context_mask;
2377                 callback = handle_ir_packet_per_buffer;
2378                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2379                 if (index >= 0) {
2380                         *channels &= ~(1ULL << channel);
2381                         *mask     &= ~(1 << index);
2382                         regs = OHCI1394_IsoRcvContextBase(index);
2383                         ctx  = &ohci->ir_context_list[index];
2384                 }
2385                 break;
2386
2387         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2388                 mask     = &ohci->ir_context_mask;
2389                 callback = handle_ir_buffer_fill;
2390                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2391                 if (index >= 0) {
2392                         ohci->mc_allocated = true;
2393                         *mask &= ~(1 << index);
2394                         regs = OHCI1394_IsoRcvContextBase(index);
2395                         ctx  = &ohci->ir_context_list[index];
2396                 }
2397                 break;
2398
2399         default:
2400                 index = -1;
2401                 ret = -ENOSYS;
2402         }
2403
2404         spin_unlock_irqrestore(&ohci->lock, flags);
2405
2406         if (index < 0)
2407                 return ERR_PTR(ret);
2408
2409         memset(ctx, 0, sizeof(*ctx));
2410         ctx->header_length = 0;
2411         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2412         if (ctx->header == NULL) {
2413                 ret = -ENOMEM;
2414                 goto out;
2415         }
2416         ret = context_init(&ctx->context, ohci, regs, callback);
2417         if (ret < 0)
2418                 goto out_with_header;
2419
2420         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2421                 set_multichannel_mask(ohci, 0);
2422
2423         return &ctx->base;
2424
2425  out_with_header:
2426         free_page((unsigned long)ctx->header);
2427  out:
2428         spin_lock_irqsave(&ohci->lock, flags);
2429
2430         switch (type) {
2431         case FW_ISO_CONTEXT_RECEIVE:
2432                 *channels |= 1ULL << channel;
2433                 break;
2434
2435         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2436                 ohci->mc_allocated = false;
2437                 break;
2438         }
2439         *mask |= 1 << index;
2440
2441         spin_unlock_irqrestore(&ohci->lock, flags);
2442
2443         return ERR_PTR(ret);
2444 }
2445
2446 static int ohci_start_iso(struct fw_iso_context *base,
2447                           s32 cycle, u32 sync, u32 tags)
2448 {
2449         struct iso_context *ctx = container_of(base, struct iso_context, base);
2450         struct fw_ohci *ohci = ctx->context.ohci;
2451         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2452         int index;
2453
2454         switch (ctx->base.type) {
2455         case FW_ISO_CONTEXT_TRANSMIT:
2456                 index = ctx - ohci->it_context_list;
2457                 match = 0;
2458                 if (cycle >= 0)
2459                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2460                                 (cycle & 0x7fff) << 16;
2461
2462                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2463                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2464                 context_run(&ctx->context, match);
2465                 break;
2466
2467         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2468                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2469                 /* fall through */
2470         case FW_ISO_CONTEXT_RECEIVE:
2471                 index = ctx - ohci->ir_context_list;
2472                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2473                 if (cycle >= 0) {
2474                         match |= (cycle & 0x07fff) << 12;
2475                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2476                 }
2477
2478                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2479                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2480                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2481                 context_run(&ctx->context, control);
2482                 break;
2483         }
2484
2485         return 0;
2486 }
2487
2488 static int ohci_stop_iso(struct fw_iso_context *base)
2489 {
2490         struct fw_ohci *ohci = fw_ohci(base->card);
2491         struct iso_context *ctx = container_of(base, struct iso_context, base);
2492         int index;
2493
2494         switch (ctx->base.type) {
2495         case FW_ISO_CONTEXT_TRANSMIT:
2496                 index = ctx - ohci->it_context_list;
2497                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2498                 break;
2499
2500         case FW_ISO_CONTEXT_RECEIVE:
2501         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2502                 index = ctx - ohci->ir_context_list;
2503                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2504                 break;
2505         }
2506         flush_writes(ohci);
2507         context_stop(&ctx->context);
2508
2509         return 0;
2510 }
2511
2512 static void ohci_free_iso_context(struct fw_iso_context *base)
2513 {
2514         struct fw_ohci *ohci = fw_ohci(base->card);
2515         struct iso_context *ctx = container_of(base, struct iso_context, base);
2516         unsigned long flags;
2517         int index;
2518
2519         ohci_stop_iso(base);
2520         context_release(&ctx->context);
2521         free_page((unsigned long)ctx->header);
2522
2523         spin_lock_irqsave(&ohci->lock, flags);
2524
2525         switch (base->type) {
2526         case FW_ISO_CONTEXT_TRANSMIT:
2527                 index = ctx - ohci->it_context_list;
2528                 ohci->it_context_mask |= 1 << index;
2529                 break;
2530
2531         case FW_ISO_CONTEXT_RECEIVE:
2532                 index = ctx - ohci->ir_context_list;
2533                 ohci->ir_context_mask |= 1 << index;
2534                 ohci->ir_context_channels |= 1ULL << base->channel;
2535                 break;
2536
2537         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2538                 index = ctx - ohci->ir_context_list;
2539                 ohci->ir_context_mask |= 1 << index;
2540                 ohci->ir_context_channels |= ohci->mc_channels;
2541                 ohci->mc_channels = 0;
2542                 ohci->mc_allocated = false;
2543                 break;
2544         }
2545
2546         spin_unlock_irqrestore(&ohci->lock, flags);
2547 }
2548
2549 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2550 {
2551         struct fw_ohci *ohci = fw_ohci(base->card);
2552         unsigned long flags;
2553         int ret;
2554
2555         switch (base->type) {
2556         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2557
2558                 spin_lock_irqsave(&ohci->lock, flags);
2559
2560                 /* Don't allow multichannel to grab other contexts' channels. */
2561                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2562                         *channels = ohci->ir_context_channels;
2563                         ret = -EBUSY;
2564                 } else {
2565                         set_multichannel_mask(ohci, *channels);
2566                         ret = 0;
2567                 }
2568
2569                 spin_unlock_irqrestore(&ohci->lock, flags);
2570
2571                 break;
2572         default:
2573                 ret = -EINVAL;
2574         }
2575
2576         return ret;
2577 }
2578
2579 static int queue_iso_transmit(struct iso_context *ctx,
2580                               struct fw_iso_packet *packet,
2581                               struct fw_iso_buffer *buffer,
2582                               unsigned long payload)
2583 {
2584         struct descriptor *d, *last, *pd;
2585         struct fw_iso_packet *p;
2586         __le32 *header;
2587         dma_addr_t d_bus, page_bus;
2588         u32 z, header_z, payload_z, irq;
2589         u32 payload_index, payload_end_index, next_page_index;
2590         int page, end_page, i, length, offset;
2591
2592         p = packet;
2593         payload_index = payload;
2594
2595         if (p->skip)
2596                 z = 1;
2597         else
2598                 z = 2;
2599         if (p->header_length > 0)
2600                 z++;
2601
2602         /* Determine the first page the payload isn't contained in. */
2603         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2604         if (p->payload_length > 0)
2605                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2606         else
2607                 payload_z = 0;
2608
2609         z += payload_z;
2610
2611         /* Get header size in number of descriptors. */
2612         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2613
2614         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2615         if (d == NULL)
2616                 return -ENOMEM;
2617
2618         if (!p->skip) {
2619                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2620                 d[0].req_count = cpu_to_le16(8);
2621                 /*
2622                  * Link the skip address to this descriptor itself.  This causes
2623                  * a context to skip a cycle whenever lost cycles or FIFO
2624                  * overruns occur, without dropping the data.  The application
2625                  * should then decide whether this is an error condition or not.
2626                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2627                  */
2628                 d[0].branch_address = cpu_to_le32(d_bus | z);
2629
2630                 header = (__le32 *) &d[1];
2631                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2632                                         IT_HEADER_TAG(p->tag) |
2633                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2634                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2635                                         IT_HEADER_SPEED(ctx->base.speed));
2636                 header[1] =
2637                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2638                                                           p->payload_length));
2639         }
2640
2641         if (p->header_length > 0) {
2642                 d[2].req_count    = cpu_to_le16(p->header_length);
2643                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2644                 memcpy(&d[z], p->header, p->header_length);
2645         }
2646
2647         pd = d + z - payload_z;
2648         payload_end_index = payload_index + p->payload_length;
2649         for (i = 0; i < payload_z; i++) {
2650                 page               = payload_index >> PAGE_SHIFT;
2651                 offset             = payload_index & ~PAGE_MASK;
2652                 next_page_index    = (page + 1) << PAGE_SHIFT;
2653                 length             =
2654                         min(next_page_index, payload_end_index) - payload_index;
2655                 pd[i].req_count    = cpu_to_le16(length);
2656
2657                 page_bus = page_private(buffer->pages[page]);
2658                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2659
2660                 payload_index += length;
2661         }
2662
2663         if (p->interrupt)
2664                 irq = DESCRIPTOR_IRQ_ALWAYS;
2665         else
2666                 irq = DESCRIPTOR_NO_IRQ;
2667
2668         last = z == 2 ? d : d + z - 1;
2669         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2670                                      DESCRIPTOR_STATUS |
2671                                      DESCRIPTOR_BRANCH_ALWAYS |
2672                                      irq);
2673
2674         context_append(&ctx->context, d, z, header_z);
2675
2676         return 0;
2677 }
2678
2679 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2680                                        struct fw_iso_packet *packet,
2681                                        struct fw_iso_buffer *buffer,
2682                                        unsigned long payload)
2683 {
2684         struct descriptor *d, *pd;
2685         dma_addr_t d_bus, page_bus;
2686         u32 z, header_z, rest;
2687         int i, j, length;
2688         int page, offset, packet_count, header_size, payload_per_buffer;
2689
2690         /*
2691          * The OHCI controller puts the isochronous header and trailer in the
2692          * buffer, so we need at least 8 bytes.
2693          */
2694         packet_count = packet->header_length / ctx->base.header_size;
2695         header_size  = max(ctx->base.header_size, (size_t)8);
2696
2697         /* Get header size in number of descriptors. */
2698         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2699         page     = payload >> PAGE_SHIFT;
2700         offset   = payload & ~PAGE_MASK;
2701         payload_per_buffer = packet->payload_length / packet_count;
2702
2703         for (i = 0; i < packet_count; i++) {
2704                 /* d points to the header descriptor */
2705                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2706                 d = context_get_descriptors(&ctx->context,
2707                                 z + header_z, &d_bus);
2708                 if (d == NULL)
2709                         return -ENOMEM;
2710
2711                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2712                                               DESCRIPTOR_INPUT_MORE);
2713                 if (packet->skip && i == 0)
2714                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2715                 d->req_count    = cpu_to_le16(header_size);
2716                 d->res_count    = d->req_count;
2717                 d->transfer_status = 0;
2718                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2719
2720                 rest = payload_per_buffer;
2721                 pd = d;
2722                 for (j = 1; j < z; j++) {
2723                         pd++;
2724                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2725                                                   DESCRIPTOR_INPUT_MORE);
2726
2727                         if (offset + rest < PAGE_SIZE)
2728                                 length = rest;
2729                         else
2730                                 length = PAGE_SIZE - offset;
2731                         pd->req_count = cpu_to_le16(length);
2732                         pd->res_count = pd->req_count;
2733                         pd->transfer_status = 0;
2734
2735                         page_bus = page_private(buffer->pages[page]);
2736                         pd->data_address = cpu_to_le32(page_bus + offset);
2737
2738                         offset = (offset + length) & ~PAGE_MASK;
2739                         rest -= length;
2740                         if (offset == 0)
2741                                 page++;
2742                 }
2743                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2744                                           DESCRIPTOR_INPUT_LAST |
2745                                           DESCRIPTOR_BRANCH_ALWAYS);
2746                 if (packet->interrupt && i == packet_count - 1)
2747                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2748
2749                 context_append(&ctx->context, d, z, header_z);
2750         }
2751
2752         return 0;
2753 }
2754
2755 static int queue_iso_buffer_fill(struct iso_context *ctx,
2756                                  struct fw_iso_packet *packet,
2757                                  struct fw_iso_buffer *buffer,
2758                                  unsigned long payload)
2759 {
2760         struct descriptor *d;
2761         dma_addr_t d_bus, page_bus;
2762         int page, offset, rest, z, i, length;
2763
2764         page   = payload >> PAGE_SHIFT;
2765         offset = payload & ~PAGE_MASK;
2766         rest   = packet->payload_length;
2767
2768         /* We need one descriptor for each page in the buffer. */
2769         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2770
2771         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2772                 return -EFAULT;
2773
2774         for (i = 0; i < z; i++) {
2775                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2776                 if (d == NULL)
2777                         return -ENOMEM;
2778
2779                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2780                                          DESCRIPTOR_BRANCH_ALWAYS);
2781                 if (packet->skip && i == 0)
2782                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2783                 if (packet->interrupt && i == z - 1)
2784                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2785
2786                 if (offset + rest < PAGE_SIZE)
2787                         length = rest;
2788                 else
2789                         length = PAGE_SIZE - offset;
2790                 d->req_count = cpu_to_le16(length);
2791                 d->res_count = d->req_count;
2792                 d->transfer_status = 0;
2793
2794                 page_bus = page_private(buffer->pages[page]);
2795                 d->data_address = cpu_to_le32(page_bus + offset);
2796
2797                 rest -= length;
2798                 offset = 0;
2799                 page++;
2800
2801                 context_append(&ctx->context, d, 1, 0);
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int ohci_queue_iso(struct fw_iso_context *base,
2808                           struct fw_iso_packet *packet,
2809                           struct fw_iso_buffer *buffer,
2810                           unsigned long payload)
2811 {
2812         struct iso_context *ctx = container_of(base, struct iso_context, base);
2813         unsigned long flags;
2814         int ret = -ENOSYS;
2815
2816         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2817         switch (base->type) {
2818         case FW_ISO_CONTEXT_TRANSMIT:
2819                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2820                 break;
2821         case FW_ISO_CONTEXT_RECEIVE:
2822                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2823                 break;
2824         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2825                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2826                 break;
2827         }
2828         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2829
2830         return ret;
2831 }
2832
2833 static const struct fw_card_driver ohci_driver = {
2834         .enable                 = ohci_enable,
2835         .read_phy_reg           = ohci_read_phy_reg,
2836         .update_phy_reg         = ohci_update_phy_reg,
2837         .set_config_rom         = ohci_set_config_rom,
2838         .send_request           = ohci_send_request,
2839         .send_response          = ohci_send_response,
2840         .cancel_packet          = ohci_cancel_packet,
2841         .enable_phys_dma        = ohci_enable_phys_dma,
2842         .read_csr               = ohci_read_csr,
2843         .write_csr              = ohci_write_csr,
2844
2845         .allocate_iso_context   = ohci_allocate_iso_context,
2846         .free_iso_context       = ohci_free_iso_context,
2847         .set_iso_channels       = ohci_set_iso_channels,
2848         .queue_iso              = ohci_queue_iso,
2849         .start_iso              = ohci_start_iso,
2850         .stop_iso               = ohci_stop_iso,
2851 };
2852
2853 #ifdef CONFIG_PPC_PMAC
2854 static void pmac_ohci_on(struct pci_dev *dev)
2855 {
2856         if (machine_is(powermac)) {
2857                 struct device_node *ofn = pci_device_to_OF_node(dev);
2858
2859                 if (ofn) {
2860                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2861                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2862                 }
2863         }
2864 }
2865
2866 static void pmac_ohci_off(struct pci_dev *dev)
2867 {
2868         if (machine_is(powermac)) {
2869                 struct device_node *ofn = pci_device_to_OF_node(dev);
2870
2871                 if (ofn) {
2872                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2873                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2874                 }
2875         }
2876 }
2877 #else
2878 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2879 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2880 #endif /* CONFIG_PPC_PMAC */
2881
2882 static int __devinit pci_probe(struct pci_dev *dev,
2883                                const struct pci_device_id *ent)
2884 {
2885         struct fw_ohci *ohci;
2886         u32 bus_options, max_receive, link_speed, version;
2887         u64 guid;
2888         int i, err, n_ir, n_it;
2889         size_t size;
2890
2891         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2892         if (ohci == NULL) {
2893                 err = -ENOMEM;
2894                 goto fail;
2895         }
2896
2897         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2898
2899         pmac_ohci_on(dev);
2900
2901         err = pci_enable_device(dev);
2902         if (err) {
2903                 fw_error("Failed to enable OHCI hardware\n");
2904                 goto fail_free;
2905         }
2906
2907         pci_set_master(dev);
2908         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2909         pci_set_drvdata(dev, ohci);
2910
2911         spin_lock_init(&ohci->lock);
2912         mutex_init(&ohci->phy_reg_mutex);
2913
2914         tasklet_init(&ohci->bus_reset_tasklet,
2915                      bus_reset_tasklet, (unsigned long)ohci);
2916
2917         err = pci_request_region(dev, 0, ohci_driver_name);
2918         if (err) {
2919                 fw_error("MMIO resource unavailable\n");
2920                 goto fail_disable;
2921         }
2922
2923         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2924         if (ohci->registers == NULL) {
2925                 fw_error("Failed to remap registers\n");
2926                 err = -ENXIO;
2927                 goto fail_iomem;
2928         }
2929
2930         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2931                 if (ohci_quirks[i].vendor == dev->vendor &&
2932                     (ohci_quirks[i].device == dev->device ||
2933                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2934                         ohci->quirks = ohci_quirks[i].flags;
2935                         break;
2936                 }
2937         if (param_quirks)
2938                 ohci->quirks = param_quirks;
2939
2940         ar_context_init(&ohci->ar_request_ctx, ohci,
2941                         OHCI1394_AsReqRcvContextControlSet);
2942
2943         ar_context_init(&ohci->ar_response_ctx, ohci,
2944                         OHCI1394_AsRspRcvContextControlSet);
2945
2946         context_init(&ohci->at_request_ctx, ohci,
2947                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2948
2949         context_init(&ohci->at_response_ctx, ohci,
2950                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2951
2952         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2953         ohci->ir_context_channels = ~0ULL;
2954         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2955         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2956         n_ir = hweight32(ohci->ir_context_mask);
2957         size = sizeof(struct iso_context) * n_ir;
2958         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2959
2960         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2961         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2962         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2963         n_it = hweight32(ohci->it_context_mask);
2964         size = sizeof(struct iso_context) * n_it;
2965         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2966
2967         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2968                 err = -ENOMEM;
2969                 goto fail_contexts;
2970         }
2971
2972         /* self-id dma buffer allocation */
2973         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2974                                                SELF_ID_BUF_SIZE,
2975                                                &ohci->self_id_bus,
2976                                                GFP_KERNEL);
2977         if (ohci->self_id_cpu == NULL) {
2978                 err = -ENOMEM;
2979                 goto fail_contexts;
2980         }
2981
2982         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2983         max_receive = (bus_options >> 12) & 0xf;
2984         link_speed = bus_options & 0x7;
2985         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2986                 reg_read(ohci, OHCI1394_GUIDLo);
2987
2988         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2989         if (err)
2990                 goto fail_self_id;
2991
2992         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2993         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2994                   "%d IR + %d IT contexts, quirks 0x%x\n",
2995                   dev_name(&dev->dev), version >> 16, version & 0xff,
2996                   n_ir, n_it, ohci->quirks);
2997
2998         return 0;
2999
3000  fail_self_id:
3001         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3002                           ohci->self_id_cpu, ohci->self_id_bus);
3003  fail_contexts:
3004         kfree(ohci->ir_context_list);
3005         kfree(ohci->it_context_list);
3006         context_release(&ohci->at_response_ctx);
3007         context_release(&ohci->at_request_ctx);
3008         ar_context_release(&ohci->ar_response_ctx);
3009         ar_context_release(&ohci->ar_request_ctx);
3010         pci_iounmap(dev, ohci->registers);
3011  fail_iomem:
3012         pci_release_region(dev, 0);
3013  fail_disable:
3014         pci_disable_device(dev);
3015  fail_free:
3016         kfree(&ohci->card);
3017         pmac_ohci_off(dev);
3018  fail:
3019         if (err == -ENOMEM)
3020                 fw_error("Out of memory\n");
3021
3022         return err;
3023 }
3024
3025 static void pci_remove(struct pci_dev *dev)
3026 {
3027         struct fw_ohci *ohci;
3028
3029         ohci = pci_get_drvdata(dev);
3030         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3031         flush_writes(ohci);
3032         fw_core_remove_card(&ohci->card);
3033
3034         /*
3035          * FIXME: Fail all pending packets here, now that the upper
3036          * layers can't queue any more.
3037          */
3038
3039         software_reset(ohci);
3040         free_irq(dev->irq, ohci);
3041
3042         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3043                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3044                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3045         if (ohci->config_rom)
3046                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3047                                   ohci->config_rom, ohci->config_rom_bus);
3048         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3049                           ohci->self_id_cpu, ohci->self_id_bus);
3050         ar_context_release(&ohci->ar_request_ctx);
3051         ar_context_release(&ohci->ar_response_ctx);
3052         context_release(&ohci->at_request_ctx);
3053         context_release(&ohci->at_response_ctx);
3054         kfree(ohci->it_context_list);
3055         kfree(ohci->ir_context_list);
3056         pci_disable_msi(dev);
3057         pci_iounmap(dev, ohci->registers);
3058         pci_release_region(dev, 0);
3059         pci_disable_device(dev);
3060         kfree(&ohci->card);
3061         pmac_ohci_off(dev);
3062
3063         fw_notify("Removed fw-ohci device.\n");
3064 }
3065
3066 #ifdef CONFIG_PM
3067 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3068 {
3069         struct fw_ohci *ohci = pci_get_drvdata(dev);
3070         int err;
3071
3072         software_reset(ohci);
3073         free_irq(dev->irq, ohci);
3074         pci_disable_msi(dev);
3075         err = pci_save_state(dev);
3076         if (err) {
3077                 fw_error("pci_save_state failed\n");
3078                 return err;
3079         }
3080         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3081         if (err)
3082                 fw_error("pci_set_power_state failed with %d\n", err);
3083         pmac_ohci_off(dev);
3084
3085         return 0;
3086 }
3087
3088 static int pci_resume(struct pci_dev *dev)
3089 {
3090         struct fw_ohci *ohci = pci_get_drvdata(dev);
3091         int err;
3092
3093         pmac_ohci_on(dev);
3094         pci_set_power_state(dev, PCI_D0);
3095         pci_restore_state(dev);
3096         err = pci_enable_device(dev);
3097         if (err) {
3098                 fw_error("pci_enable_device failed\n");
3099                 return err;
3100         }
3101
3102         return ohci_enable(&ohci->card, NULL, 0);
3103 }
3104 #endif
3105
3106 static const struct pci_device_id pci_table[] = {
3107         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3108         { }
3109 };
3110
3111 MODULE_DEVICE_TABLE(pci, pci_table);
3112
3113 static struct pci_driver fw_ohci_pci_driver = {
3114         .name           = ohci_driver_name,
3115         .id_table       = pci_table,
3116         .probe          = pci_probe,
3117         .remove         = pci_remove,
3118 #ifdef CONFIG_PM
3119         .resume         = pci_resume,
3120         .suspend        = pci_suspend,
3121 #endif
3122 };
3123
3124 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3125 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3126 MODULE_LICENSE("GPL");
3127
3128 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3129 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3130 MODULE_ALIAS("ohci1394");
3131 #endif
3132
3133 static int __init fw_ohci_init(void)
3134 {
3135         return pci_register_driver(&fw_ohci_pci_driver);
3136 }
3137
3138 static void __exit fw_ohci_cleanup(void)
3139 {
3140         pci_unregister_driver(&fw_ohci_pci_driver);
3141 }
3142
3143 module_init(fw_ohci_init);
3144 module_exit(fw_ohci_cleanup);