drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bug.h>
  22 #include <linux/compiler.h>
  23 #include <linux/delay.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/firewire.h>
  27 #include <linux/firewire-constants.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/mm.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/mutex.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/slab.h>
  40 #include <linux/spinlock.h>
  41 #include <linux/string.h>
  42 #include <linux/time.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/page.h>
  46 #include <asm/system.h>
  47
  48 #ifdef CONFIG_PPC_PMAC
  49 #include <asm/pmac_feature.h>
  50 #endif
  51
  52 #include "core.h"
  53 #include "ohci.h"
  54
  55 #define DESCRIPTOR_OUTPUT_MORE          0
  56 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  57 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  58 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  59 #define DESCRIPTOR_STATUS               (1 << 11)
  60 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  61 #define DESCRIPTOR_PING                 (1 << 7)
  62 #define DESCRIPTOR_YY                   (1 << 6)
  63 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  64 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  65 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  66 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  67 #define DESCRIPTOR_WAIT                 (3 << 0)
  68
  69 struct descriptor {
  70         __le16 req_count;
  71         __le16 control;
  72         __le32 data_address;
  73         __le32 branch_address;
  74         __le16 res_count;
  75         __le16 transfer_status;
  76 } __attribute__((aligned(16)));
  77
  78 #define CONTROL_SET(regs)       (regs)
  79 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  80 #define COMMAND_PTR(regs)       ((regs) + 12)
  81 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  82
  83 struct ar_buffer {
  84         struct descriptor descriptor;
  85         struct ar_buffer *next;
  86         __le32 data[0];
  87 };
  88
  89 struct ar_context {
  90         struct fw_ohci *ohci;
  91         struct ar_buffer *current_buffer;
  92         struct ar_buffer *last_buffer;
  93         void *pointer;
  94         u32 regs;
  95         struct tasklet_struct tasklet;
  96 };
  97
  98 struct context;
  99
 100 typedef int (*descriptor_callback_t)(struct context *ctx,
 101                                      struct descriptor *d,
 102                                      struct descriptor *last);
 103
 104 /*
 105  * A buffer that contains a block of DMA-able coherent memory used for
 106  * storing a portion of a DMA descriptor program.
 107  */
 108 struct descriptor_buffer {
 109         struct list_head list;
 110         dma_addr_t buffer_bus;
 111         size_t buffer_size;
 112         size_t used;
 113         struct descriptor buffer[0];
 114 };
 115
 116 struct context {
 117         struct fw_ohci *ohci;
 118         u32 regs;
 119         int total_allocation;
 120
 121         /*
 122          * List of page-sized buffers for storing DMA descriptors.
 123          * Head of list contains buffers in use and tail of list contains
 124          * free buffers.
 125          */
 126         struct list_head buffer_list;
 127
 128         /*
 129          * Pointer to a buffer inside buffer_list that contains the tail
 130          * end of the current DMA program.
 131          */
 132         struct descriptor_buffer *buffer_tail;
 133
 134         /*
 135          * The descriptor containing the branch address of the first
 136          * descriptor that has not yet been filled by the device.
 137          */
 138         struct descriptor *last;
 139
 140         /*
 141          * The last descriptor in the DMA program.  It contains the branch
 142          * address that must be updated upon appending a new descriptor.
 143          */
 144         struct descriptor *prev;
 145
 146         descriptor_callback_t callback;
 147
 148         struct tasklet_struct tasklet;
 149 };
 150
 151 #define IT_HEADER_SY(v)          ((v) <<  0)
 152 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 153 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 154 #define IT_HEADER_TAG(v)         ((v) << 14)
 155 #define IT_HEADER_SPEED(v)       ((v) << 16)
 156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 157
 158 struct iso_context {
 159         struct fw_iso_context base;
 160         struct context context;
 161         int excess_bytes;
 162         void *header;
 163         size_t header_length;
 164 };
 165
 166 #define CONFIG_ROM_SIZE 1024
 167
 168 struct fw_ohci {
 169         struct fw_card card;
 170
 171         __iomem char *registers;
 172         int node_id;
 173         int generation;
 174         int request_generation; /* for timestamping incoming requests */
 175         unsigned quirks;
 176         unsigned int pri_req_max;
 177         u32 bus_time;
 178         bool is_root;
 179         bool csr_state_setclear_abdicate;
 180
 181         /*
 182          * Spinlock for accessing fw_ohci data.  Never call out of
 183          * this driver with this lock held.
 184          */
 185         spinlock_t lock;
 186
 187         struct mutex phy_reg_mutex;
 188
 189         struct ar_context ar_request_ctx;
 190         struct ar_context ar_response_ctx;
 191         struct context at_request_ctx;
 192         struct context at_response_ctx;
 193
 194         u32 it_context_mask;     /* unoccupied IT contexts */
 195         struct iso_context *it_context_list;
 196         u64 ir_context_channels; /* unoccupied channels */
 197         u32 ir_context_mask;     /* unoccupied IR contexts */
 198         struct iso_context *ir_context_list;
 199         u64 mc_channels; /* channels in use by the multichannel IR context */
 200         bool mc_allocated;
 201
 202         __be32    *config_rom;
 203         dma_addr_t config_rom_bus;
 204         __be32    *next_config_rom;
 205         dma_addr_t next_config_rom_bus;
 206         __be32     next_header;
 207
 208         __le32    *self_id_cpu;
 209         dma_addr_t self_id_bus;
 210         struct tasklet_struct bus_reset_tasklet;
 211
 212         u32 self_id_buffer[512];
 213 };
 214
 215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 216 {
 217         return container_of(card, struct fw_ohci, card);
 218 }
 219
 220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 221 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 222 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 224 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 225 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 226
 227 #define CONTEXT_RUN     0x8000
 228 #define CONTEXT_WAKE    0x1000
 229 #define CONTEXT_DEAD    0x0800
 230 #define CONTEXT_ACTIVE  0x0400
 231
 232 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 233 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 234 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 235
 236 #define OHCI1394_REGISTER_SIZE          0x800
 237 #define OHCI_LOOP_COUNT                 500
 238 #define OHCI1394_PCI_HCI_Control        0x40
 239 #define SELF_ID_BUF_SIZE                0x800
 240 #define OHCI_TCODE_PHY_PACKET           0x0e
 241 #define OHCI_VERSION_1_1                0x010010
 242
 243 static char ohci_driver_name[] = KBUILD_MODNAME;
 244
 245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 246 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 247
 248 #define QUIRK_CYCLE_TIMER               1
 249 #define QUIRK_RESET_PACKET              2
 250 #define QUIRK_BE_HEADERS                4
 251 #define QUIRK_NO_1394A                  8
 252 #define QUIRK_NO_MSI                    16
 253
 254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 255 static const struct {
 256         unsigned short vendor, device, flags;
 257 } ohci_quirks[] = {
 258         {PCI_VENDOR_ID_TI,      PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
 259                                                             QUIRK_RESET_PACKET |
 260                                                             QUIRK_NO_1394A},
 261         {PCI_VENDOR_ID_TI,      PCI_ANY_ID,     QUIRK_RESET_PACKET},
 262         {PCI_VENDOR_ID_AL,      PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 263         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
 264         {PCI_VENDOR_ID_NEC,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 265         {PCI_VENDOR_ID_VIA,     PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 266         {PCI_VENDOR_ID_RICOH,   PCI_ANY_ID,     QUIRK_CYCLE_TIMER},
 267         {PCI_VENDOR_ID_APPLE,   PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
 268 };
 269
 270 /* This overrides anything that was found in ohci_quirks[]. */
 271 static int param_quirks;
 272 module_param_named(quirks, param_quirks, int, 0644);
 273 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 274         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 275         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 276         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 277         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 278         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 279         ")");
 280
 281 #define OHCI_PARAM_DEBUG_AT_AR          1
 282 #define OHCI_PARAM_DEBUG_SELFIDS        2
 283 #define OHCI_PARAM_DEBUG_IRQS           4
 284 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 285
 286 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 287
 288 static int param_debug;
 289 module_param_named(debug, param_debug, int, 0644);
 290 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 291         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 292         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 293         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 294         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 295         ", or a combination, or all = -1)");
 296
 297 static void log_irqs(u32 evt)
 298 {
 299         if (likely(!(param_debug &
 300                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 301                 return;
 302
 303         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 304             !(evt & OHCI1394_busReset))
 305                 return;
 306
 307         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 308             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 309             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 310             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 311             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 312             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 313             evt & OHCI1394_isochRx              ? " IR"                 : "",
 314             evt & OHCI1394_isochTx              ? " IT"                 : "",
 315             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 316             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 317             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 318             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 319             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 320             evt & OHCI1394_busReset             ? " busReset"           : "",
 321             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 322                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 323                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 324                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 325                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 326                     OHCI1394_cycleInconsistent |
 327                     OHCI1394_regAccessFail | OHCI1394_busReset)
 328                                                 ? " ?"                  : "");
 329 }
 330
 331 static const char *speed[] = {
 332         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 333 };
 334 static const char *power[] = {
 335         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 336         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 337 };
 338 static const char port[] = { '.', '-', 'p', 'c', };
 339
 340 static char _p(u32 *s, int shift)
 341 {
 342         return port[*s >> shift & 3];
 343 }
 344
 345 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 346 {
 347         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 348                 return;
 349
 350         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 351                   self_id_count, generation, node_id);
 352
 353         for (; self_id_count--; ++s)
 354                 if ((*s & 1 << 23) == 0)
 355                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 356                             "%s gc=%d %s %s%s%s\n",
 357                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 358                             speed[*s >> 14 & 3], *s >> 16 & 63,
 359                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 360                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 361                 else
 362                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 363                             *s, *s >> 24 & 63,
 364                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 365                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 366 }
 367
 368 static const char *evts[] = {
 369         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 370         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 371         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 372         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 373         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 374         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 375         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 376         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 377         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 378         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 379         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 380         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 381         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 382         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 383         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 384         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 385         [0x20] = "pending/cancelled",
 386 };
 387 static const char *tcodes[] = {
 388         [0x0] = "QW req",               [0x1] = "BW req",
 389         [0x2] = "W resp",               [0x3] = "-reserved-",
 390         [0x4] = "QR req",               [0x5] = "BR req",
 391         [0x6] = "QR resp",              [0x7] = "BR resp",
 392         [0x8] = "cycle start",          [0x9] = "Lk req",
 393         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 394         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 395         [0xe] = "link internal",        [0xf] = "-reserved-",
 396 };
 397 static const char *phys[] = {
 398         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 399         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 400 };
 401
 402 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 403 {
 404         int tcode = header[0] >> 4 & 0xf;
 405         char specific[12];
 406
 407         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 408                 return;
 409
 410         if (unlikely(evt >= ARRAY_SIZE(evts)))
 411                         evt = 0x1f;
 412
 413         if (evt == OHCI1394_evt_bus_reset) {
 414                 fw_notify("A%c evt_bus_reset, generation %d\n",
 415                     dir, (header[2] >> 16) & 0xff);
 416                 return;
 417         }
 418
 419         if (header[0] == ~header[1]) {
 420                 fw_notify("A%c %s, %s, %08x\n",
 421                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 422                 return;
 423         }
 424
 425         switch (tcode) {
 426         case 0x0: case 0x6: case 0x8:
 427                 snprintf(specific, sizeof(specific), " = %08x",
 428                          be32_to_cpu((__force __be32)header[3]));
 429                 break;
 430         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 431                 snprintf(specific, sizeof(specific), " %x,%x",
 432                          header[3] >> 16, header[3] & 0xffff);
 433                 break;
 434         default:
 435                 specific[0] = '\0';
 436         }
 437
 438         switch (tcode) {
 439         case 0xe: case 0xa:
 440                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 441                 break;
 442         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 443                 fw_notify("A%c spd %x tl %02x, "
 444                     "%04x -> %04x, %s, "
 445                     "%s, %04x%08x%s\n",
 446                     dir, speed, header[0] >> 10 & 0x3f,
 447                     header[1] >> 16, header[0] >> 16, evts[evt],
 448                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 449                 break;
 450         default:
 451                 fw_notify("A%c spd %x tl %02x, "
 452                     "%04x -> %04x, %s, "
 453                     "%s%s\n",
 454                     dir, speed, header[0] >> 10 & 0x3f,
 455                     header[1] >> 16, header[0] >> 16, evts[evt],
 456                     tcodes[tcode], specific);
 457         }
 458 }
 459
 460 #else
 461
 462 #define param_debug 0
 463 static inline void log_irqs(u32 evt) {}
 464 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
 465 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
 466
 467 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 468
 469 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 470 {
 471         writel(data, ohci->registers + offset);
 472 }
 473
 474 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 475 {
 476         return readl(ohci->registers + offset);
 477 }
 478
 479 static inline void flush_writes(const struct fw_ohci *ohci)
 480 {
 481         /* Do a dummy read to flush writes. */
 482         reg_read(ohci, OHCI1394_Version);
 483 }
 484
 485 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 486 {
 487         u32 val;
 488         int i;
 489
 490         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 491         for (i = 0; i < 3 + 100; i++) {
 492                 val = reg_read(ohci, OHCI1394_PhyControl);
 493                 if (val & OHCI1394_PhyControl_ReadDone)
 494                         return OHCI1394_PhyControl_ReadData(val);
 495
 496                 /*
 497                  * Try a few times without waiting.  Sleeping is necessary
 498                  * only when the link/PHY interface is busy.
 499                  */
 500                 if (i >= 3)
 501                         msleep(1);
 502         }
 503         fw_error("failed to read phy reg\n");
 504
 505         return -EBUSY;
 506 }
 507
 508 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 509 {
 510         int i;
 511
 512         reg_write(ohci, OHCI1394_PhyControl,
 513                   OHCI1394_PhyControl_Write(addr, val));
 514         for (i = 0; i < 3 + 100; i++) {
 515                 val = reg_read(ohci, OHCI1394_PhyControl);
 516                 if (!(val & OHCI1394_PhyControl_WritePending))
 517                         return 0;
 518
 519                 if (i >= 3)
 520                         msleep(1);
 521         }
 522         fw_error("failed to write phy reg\n");
 523
 524         return -EBUSY;
 525 }
 526
 527 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 528                           int clear_bits, int set_bits)
 529 {
 530         int ret = read_phy_reg(ohci, addr);
 531         if (ret < 0)
 532                 return ret;
 533
 534         /*
 535          * The interrupt status bits are cleared by writing a one bit.
 536          * Avoid clearing them unless explicitly requested in set_bits.
 537          */
 538         if (addr == 5)
 539                 clear_bits |= PHY_INT_STATUS_BITS;
 540
 541         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 542 }
 543
 544 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 545 {
 546         int ret;
 547
 548         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 549         if (ret < 0)
 550                 return ret;
 551
 552         return read_phy_reg(ohci, addr);
 553 }
 554
 555 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 556 {
 557         struct fw_ohci *ohci = fw_ohci(card);
 558         int ret;
 559
 560         mutex_lock(&ohci->phy_reg_mutex);
 561         ret = read_phy_reg(ohci, addr);
 562         mutex_unlock(&ohci->phy_reg_mutex);
 563
 564         return ret;
 565 }
 566
 567 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 568                                int clear_bits, int set_bits)
 569 {
 570         struct fw_ohci *ohci = fw_ohci(card);
 571         int ret;
 572
 573         mutex_lock(&ohci->phy_reg_mutex);
 574         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 575         mutex_unlock(&ohci->phy_reg_mutex);
 576
 577         return ret;
 578 }
 579
 580 static void ar_context_link_page(struct ar_context *ctx,
 581                                  struct ar_buffer *ab, dma_addr_t ab_bus)
 582 {
 583         size_t offset;
 584
 585         ab->next = NULL;
 586         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 587         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 588                                                     DESCRIPTOR_STATUS |
 589                                                     DESCRIPTOR_BRANCH_ALWAYS);
 590         offset = offsetof(struct ar_buffer, data);
 591         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 592         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 593         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 594         ab->descriptor.branch_address = 0;
 595
 596         wmb(); /* finish init of new descriptors before branch_address update */
 597         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 598         ctx->last_buffer->next = ab;
 599         ctx->last_buffer = ab;
 600
 601         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 602         flush_writes(ctx->ohci);
 603 }
 604
 605 static int ar_context_add_page(struct ar_context *ctx)
 606 {
 607         struct device *dev = ctx->ohci->card.device;
 608         struct ar_buffer *ab;
 609         dma_addr_t uninitialized_var(ab_bus);
 610
 611         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 612         if (ab == NULL)
 613                 return -ENOMEM;
 614
 615         ar_context_link_page(ctx, ab, ab_bus);
 616
 617         return 0;
 618 }
 619
 620 static void ar_context_release(struct ar_context *ctx)
 621 {
 622         struct ar_buffer *ab, *ab_next;
 623         size_t offset;
 624         dma_addr_t ab_bus;
 625
 626         for (ab = ctx->current_buffer; ab; ab = ab_next) {
 627                 ab_next = ab->next;
 628                 offset = offsetof(struct ar_buffer, data);
 629                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 630                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
 631                                   ab, ab_bus);
 632         }
 633 }
 634
 635 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 636 #define cond_le32_to_cpu(v) \
 637         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 638 #else
 639 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 640 #endif
 641
 642 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 643 {
 644         struct fw_ohci *ohci = ctx->ohci;
 645         struct fw_packet p;
 646         u32 status, length, tcode;
 647         int evt;
 648
 649         p.header[0] = cond_le32_to_cpu(buffer[0]);
 650         p.header[1] = cond_le32_to_cpu(buffer[1]);
 651         p.header[2] = cond_le32_to_cpu(buffer[2]);
 652
 653         tcode = (p.header[0] >> 4) & 0x0f;
 654         switch (tcode) {
 655         case TCODE_WRITE_QUADLET_REQUEST:
 656         case TCODE_READ_QUADLET_RESPONSE:
 657                 p.header[3] = (__force __u32) buffer[3];
 658                 p.header_length = 16;
 659                 p.payload_length = 0;
 660                 break;
 661
 662         case TCODE_READ_BLOCK_REQUEST :
 663                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 664                 p.header_length = 16;
 665                 p.payload_length = 0;
 666                 break;
 667
 668         case TCODE_WRITE_BLOCK_REQUEST:
 669         case TCODE_READ_BLOCK_RESPONSE:
 670         case TCODE_LOCK_REQUEST:
 671         case TCODE_LOCK_RESPONSE:
 672                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 673                 p.header_length = 16;
 674                 p.payload_length = p.header[3] >> 16;
 675                 break;
 676
 677         case TCODE_WRITE_RESPONSE:
 678         case TCODE_READ_QUADLET_REQUEST:
 679         case OHCI_TCODE_PHY_PACKET:
 680                 p.header_length = 12;
 681                 p.payload_length = 0;
 682                 break;
 683
 684         default:
 685                 /* FIXME: Stop context, discard everything, and restart? */
 686                 p.header_length = 0;
 687                 p.payload_length = 0;
 688         }
 689
 690         p.payload = (void *) buffer + p.header_length;
 691
 692         /* FIXME: What to do about evt_* errors? */
 693         length = (p.header_length + p.payload_length + 3) / 4;
 694         status = cond_le32_to_cpu(buffer[length]);
 695         evt    = (status >> 16) & 0x1f;
 696
 697         p.ack        = evt - 16;
 698         p.speed      = (status >> 21) & 0x7;
 699         p.timestamp  = status & 0xffff;
 700         p.generation = ohci->request_generation;
 701
 702         log_ar_at_event('R', p.speed, p.header, evt);
 703
 704         /*
 705          * Several controllers, notably from NEC and VIA, forget to
 706          * write ack_complete status at PHY packet reception.
 707          */
 708         if (evt == OHCI1394_evt_no_status &&
 709             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 710                 p.ack = ACK_COMPLETE;
 711
 712         /*
 713          * The OHCI bus reset handler synthesizes a PHY packet with
 714          * the new generation number when a bus reset happens (see
 715          * section 8.4.2.3).  This helps us determine when a request
 716          * was received and make sure we send the response in the same
 717          * generation.  We only need this for requests; for responses
 718          * we use the unique tlabel for finding the matching
 719          * request.
 720          *
 721          * Alas some chips sometimes emit bus reset packets with a
 722          * wrong generation.  We set the correct generation for these
 723          * at a slightly incorrect time (in bus_reset_tasklet).
 724          */
 725         if (evt == OHCI1394_evt_bus_reset) {
 726                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 727                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 728         } else if (ctx == &ohci->ar_request_ctx) {
 729                 fw_core_handle_request(&ohci->card, &p);
 730         } else {
 731                 fw_core_handle_response(&ohci->card, &p);
 732         }
 733
 734         return buffer + length + 1;
 735 }
 736
 737 static void ar_context_tasklet(unsigned long data)
 738 {
 739         struct ar_context *ctx = (struct ar_context *)data;
 740         struct ar_buffer *ab;
 741         struct descriptor *d;
 742         void *buffer, *end;
 743         __le16 res_count;
 744
 745         ab = ctx->current_buffer;
 746         d = &ab->descriptor;
 747
 748         res_count = ACCESS_ONCE(d->res_count);
 749         if (res_count == 0) {
 750                 size_t size, size2, rest, pktsize, size3, offset;
 751                 dma_addr_t start_bus;
 752                 void *start;
 753
 754                 /*
 755                  * This descriptor is finished and we may have a
 756                  * packet split across this and the next buffer. We
 757                  * reuse the page for reassembling the split packet.
 758                  */
 759
 760                 offset = offsetof(struct ar_buffer, data);
 761                 start = ab;
 762                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 763                 buffer = ab->data;
 764
 765                 ab = ab->next;
 766                 d = &ab->descriptor;
 767                 size = start + PAGE_SIZE - ctx->pointer;
 768                 /* valid buffer data in the next page */
 769                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 770                 /* what actually fits in this page */
 771                 size2 = min(rest, (size_t)PAGE_SIZE - offset - size);
 772                 memmove(buffer, ctx->pointer, size);
 773                 memcpy(buffer + size, ab->data, size2);
 774
 775                 while (size > 0) {
 776                         void *next = handle_ar_packet(ctx, buffer);
 777                         pktsize = next - buffer;
 778                         if (pktsize >= size) {
 779                                 /*
 780                                  * We have handled all the data that was
 781                                  * originally in this page, so we can now
 782                                  * continue in the next page.
 783                                  */
 784                                 buffer = next;
 785                                 break;
 786                         }
 787                         /* move the next packet to the start of the buffer */
 788                         memmove(buffer, next, size + size2 - pktsize);
 789                         size -= pktsize;
 790                         /* fill up this page again */
 791                         size3 = min(rest - size2,
 792                                     (size_t)PAGE_SIZE - offset - size - size2);
 793                         memcpy(buffer + size + size2,
 794                                (void *) ab->data + size2, size3);
 795                         size2 += size3;
 796                 }
 797
 798                 if (rest > 0) {
 799                         /* handle the packets that are fully in the next page */
 800                         buffer = (void *) ab->data +
 801                                         (buffer - (start + offset + size));
 802                         end = (void *) ab->data + rest;
 803
 804                         while (buffer < end)
 805                                 buffer = handle_ar_packet(ctx, buffer);
 806
 807                         ctx->current_buffer = ab;
 808                         ctx->pointer = end;
 809
 810                         ar_context_link_page(ctx, start, start_bus);
 811                 } else {
 812                         ctx->pointer = start + PAGE_SIZE;
 813                 }
 814         } else {
 815                 buffer = ctx->pointer;
 816                 ctx->pointer = end =
 817                         (void *) ab + PAGE_SIZE - le16_to_cpu(res_count);
 818
 819                 while (buffer < end)
 820                         buffer = handle_ar_packet(ctx, buffer);
 821         }
 822 }
 823
 824 static int ar_context_init(struct ar_context *ctx,
 825                            struct fw_ohci *ohci, u32 regs)
 826 {
 827         struct ar_buffer ab;
 828
 829         ctx->regs        = regs;
 830         ctx->ohci        = ohci;
 831         ctx->last_buffer = &ab;
 832         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 833
 834         ar_context_add_page(ctx);
 835         ar_context_add_page(ctx);
 836         ctx->current_buffer = ab.next;
 837         ctx->pointer = ctx->current_buffer->data;
 838
 839         return 0;
 840 }
 841
 842 static void ar_context_run(struct ar_context *ctx)
 843 {
 844         struct ar_buffer *ab = ctx->current_buffer;
 845         dma_addr_t ab_bus;
 846         size_t offset;
 847
 848         offset = offsetof(struct ar_buffer, data);
 849         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 850
 851         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 852         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 853         flush_writes(ctx->ohci);
 854 }
 855
 856 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
 857 {
 858         int b, key;
 859
 860         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 861         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 862
 863         /* figure out which descriptor the branch address goes in */
 864         if (z == 2 && (b == 3 || key == 2))
 865                 return d;
 866         else
 867                 return d + z - 1;
 868 }
 869
 870 static void context_tasklet(unsigned long data)
 871 {
 872         struct context *ctx = (struct context *) data;
 873         struct descriptor *d, *last;
 874         u32 address;
 875         int z;
 876         struct descriptor_buffer *desc;
 877
 878         desc = list_entry(ctx->buffer_list.next,
 879                         struct descriptor_buffer, list);
 880         last = ctx->last;
 881         while (last->branch_address != 0) {
 882                 struct descriptor_buffer *old_desc = desc;
 883                 address = le32_to_cpu(last->branch_address);
 884                 z = address & 0xf;
 885                 address &= ~0xf;
 886
 887                 /* If the branch address points to a buffer outside of the
 888                  * current buffer, advance to the next buffer. */
 889                 if (address < desc->buffer_bus ||
 890                                 address >= desc->buffer_bus + desc->used)
 891                         desc = list_entry(desc->list.next,
 892                                         struct descriptor_buffer, list);
 893                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 894                 last = find_branch_descriptor(d, z);
 895
 896                 if (!ctx->callback(ctx, d, last))
 897                         break;
 898
 899                 if (old_desc != desc) {
 900                         /* If we've advanced to the next buffer, move the
 901                          * previous buffer to the free list. */
 902                         unsigned long flags;
 903                         old_desc->used = 0;
 904                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 905                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 906                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 907                 }
 908                 ctx->last = last;
 909         }
 910 }
 911
 912 /*
 913  * Allocate a new buffer and add it to the list of free buffers for this
 914  * context.  Must be called with ohci->lock held.
 915  */
 916 static int context_add_buffer(struct context *ctx)
 917 {
 918         struct descriptor_buffer *desc;
 919         dma_addr_t uninitialized_var(bus_addr);
 920         int offset;
 921
 922         /*
 923          * 16MB of descriptors should be far more than enough for any DMA
 924          * program.  This will catch run-away userspace or DoS attacks.
 925          */
 926         if (ctx->total_allocation >= 16*1024*1024)
 927                 return -ENOMEM;
 928
 929         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 930                         &bus_addr, GFP_ATOMIC);
 931         if (!desc)
 932                 return -ENOMEM;
 933
 934         offset = (void *)&desc->buffer - (void *)desc;
 935         desc->buffer_size = PAGE_SIZE - offset;
 936         desc->buffer_bus = bus_addr + offset;
 937         desc->used = 0;
 938
 939         list_add_tail(&desc->list, &ctx->buffer_list);
 940         ctx->total_allocation += PAGE_SIZE;
 941
 942         return 0;
 943 }
 944
 945 static int context_init(struct context *ctx, struct fw_ohci *ohci,
 946                         u32 regs, descriptor_callback_t callback)
 947 {
 948         ctx->ohci = ohci;
 949         ctx->regs = regs;
 950         ctx->total_allocation = 0;
 951
 952         INIT_LIST_HEAD(&ctx->buffer_list);
 953         if (context_add_buffer(ctx) < 0)
 954                 return -ENOMEM;
 955
 956         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 957                         struct descriptor_buffer, list);
 958
 959         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 960         ctx->callback = callback;
 961
 962         /*
 963          * We put a dummy descriptor in the buffer that has a NULL
 964          * branch address and looks like it's been sent.  That way we
 965          * have a descriptor to append DMA programs to.
 966          */
 967         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 968         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 969         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 970         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 971         ctx->last = ctx->buffer_tail->buffer;
 972         ctx->prev = ctx->buffer_tail->buffer;
 973
 974         return 0;
 975 }
 976
 977 static void context_release(struct context *ctx)
 978 {
 979         struct fw_card *card = &ctx->ohci->card;
 980         struct descriptor_buffer *desc, *tmp;
 981
 982         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 983                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 984                         desc->buffer_bus -
 985                         ((void *)&desc->buffer - (void *)desc));
 986 }
 987
 988 /* Must be called with ohci->lock held */
 989 static struct descriptor *context_get_descriptors(struct context *ctx,
 990                                                   int z, dma_addr_t *d_bus)
 991 {
 992         struct descriptor *d = NULL;
 993         struct descriptor_buffer *desc = ctx->buffer_tail;
 994
 995         if (z * sizeof(*d) > desc->buffer_size)
 996                 return NULL;
 997
 998         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 999                 /* No room for the descriptor in this buffer, so advance to the
1000                  * next one. */
1001
1002                 if (desc->list.next == &ctx->buffer_list) {
1003                         /* If there is no free buffer next in the list,
1004                          * allocate one. */
1005                         if (context_add_buffer(ctx) < 0)
1006                                 return NULL;
1007                 }
1008                 desc = list_entry(desc->list.next,
1009                                 struct descriptor_buffer, list);
1010                 ctx->buffer_tail = desc;
1011         }
1012
1013         d = desc->buffer + desc->used / sizeof(*d);
1014         memset(d, 0, z * sizeof(*d));
1015         *d_bus = desc->buffer_bus + desc->used;
1016
1017         return d;
1018 }
1019
1020 static void context_run(struct context *ctx, u32 extra)
1021 {
1022         struct fw_ohci *ohci = ctx->ohci;
1023
1024         reg_write(ohci, COMMAND_PTR(ctx->regs),
1025                   le32_to_cpu(ctx->last->branch_address));
1026         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1027         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1028         flush_writes(ohci);
1029 }
1030
1031 static void context_append(struct context *ctx,
1032                            struct descriptor *d, int z, int extra)
1033 {
1034         dma_addr_t d_bus;
1035         struct descriptor_buffer *desc = ctx->buffer_tail;
1036
1037         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1038
1039         desc->used += (z + extra) * sizeof(*d);
1040
1041         wmb(); /* finish init of new descriptors before branch_address update */
1042         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1043         ctx->prev = find_branch_descriptor(d, z);
1044
1045         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1046         flush_writes(ctx->ohci);
1047 }
1048
1049 static void context_stop(struct context *ctx)
1050 {
1051         u32 reg;
1052         int i;
1053
1054         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1055         flush_writes(ctx->ohci);
1056
1057         for (i = 0; i < 10; i++) {
1058                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1059                 if ((reg & CONTEXT_ACTIVE) == 0)
1060                         return;
1061
1062                 mdelay(1);
1063         }
1064         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1065 }
1066
1067 struct driver_data {
1068         struct fw_packet *packet;
1069 };
1070
1071 /*
1072  * This function apppends a packet to the DMA queue for transmission.
1073  * Must always be called with the ochi->lock held to ensure proper
1074  * generation handling and locking around packet queue manipulation.
1075  */
1076 static int at_context_queue_packet(struct context *ctx,
1077                                    struct fw_packet *packet)
1078 {
1079         struct fw_ohci *ohci = ctx->ohci;
1080         dma_addr_t d_bus, uninitialized_var(payload_bus);
1081         struct driver_data *driver_data;
1082         struct descriptor *d, *last;
1083         __le32 *header;
1084         int z, tcode;
1085         u32 reg;
1086
1087         d = context_get_descriptors(ctx, 4, &d_bus);
1088         if (d == NULL) {
1089                 packet->ack = RCODE_SEND_ERROR;
1090                 return -1;
1091         }
1092
1093         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1094         d[0].res_count = cpu_to_le16(packet->timestamp);
1095
1096         /*
1097          * The DMA format for asyncronous link packets is different
1098          * from the IEEE1394 layout, so shift the fields around
1099          * accordingly.  If header_length is 8, it's a PHY packet, to
1100          * which we need to prepend an extra quadlet.
1101          */
1102
1103         header = (__le32 *) &d[1];
1104         switch (packet->header_length) {
1105         case 16:
1106         case 12:
1107                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1108                                         (packet->speed << 16));
1109                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1110                                         (packet->header[0] & 0xffff0000));
1111                 header[2] = cpu_to_le32(packet->header[2]);
1112
1113                 tcode = (packet->header[0] >> 4) & 0x0f;
1114                 if (TCODE_IS_BLOCK_PACKET(tcode))
1115                         header[3] = cpu_to_le32(packet->header[3]);
1116                 else
1117                         header[3] = (__force __le32) packet->header[3];
1118
1119                 d[0].req_count = cpu_to_le16(packet->header_length);
1120                 break;
1121
1122         case 8:
1123                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1124                                         (packet->speed << 16));
1125                 header[1] = cpu_to_le32(packet->header[0]);
1126                 header[2] = cpu_to_le32(packet->header[1]);
1127                 d[0].req_count = cpu_to_le16(12);
1128
1129                 if (is_ping_packet(packet->header))
1130                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1131                 break;
1132
1133         case 4:
1134                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1135                                         (packet->speed << 16));
1136                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1137                 d[0].req_count = cpu_to_le16(8);
1138                 break;
1139
1140         default:
1141                 /* BUG(); */
1142                 packet->ack = RCODE_SEND_ERROR;
1143                 return -1;
1144         }
1145
1146         driver_data = (struct driver_data *) &d[3];
1147         driver_data->packet = packet;
1148         packet->driver_data = driver_data;
1149
1150         if (packet->payload_length > 0) {
1151                 payload_bus =
1152                         dma_map_single(ohci->card.device, packet->payload,
1153                                        packet->payload_length, DMA_TO_DEVICE);
1154                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1155                         packet->ack = RCODE_SEND_ERROR;
1156                         return -1;
1157                 }
1158                 packet->payload_bus     = payload_bus;
1159                 packet->payload_mapped  = true;
1160
1161                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1162                 d[2].data_address = cpu_to_le32(payload_bus);
1163                 last = &d[2];
1164                 z = 3;
1165         } else {
1166                 last = &d[0];
1167                 z = 2;
1168         }
1169
1170         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1171                                      DESCRIPTOR_IRQ_ALWAYS |
1172                                      DESCRIPTOR_BRANCH_ALWAYS);
1173
1174         /*
1175          * If the controller and packet generations don't match, we need to
1176          * bail out and try again.  If IntEvent.busReset is set, the AT context
1177          * is halted, so appending to the context and trying to run it is
1178          * futile.  Most controllers do the right thing and just flush the AT
1179          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1180          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1181          * up stalling out.  So we just bail out in software and try again
1182          * later, and everyone is happy.
1183          * FIXME: Document how the locking works.
1184          */
1185         if (ohci->generation != packet->generation ||
1186             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1187                 if (packet->payload_mapped)
1188                         dma_unmap_single(ohci->card.device, payload_bus,
1189                                          packet->payload_length, DMA_TO_DEVICE);
1190                 packet->ack = RCODE_GENERATION;
1191                 return -1;
1192         }
1193
1194         context_append(ctx, d, z, 4 - z);
1195
1196         /* If the context isn't already running, start it up. */
1197         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1198         if ((reg & CONTEXT_RUN) == 0)
1199                 context_run(ctx, 0);
1200
1201         return 0;
1202 }
1203
1204 static int handle_at_packet(struct context *context,
1205                             struct descriptor *d,
1206                             struct descriptor *last)
1207 {
1208         struct driver_data *driver_data;
1209         struct fw_packet *packet;
1210         struct fw_ohci *ohci = context->ohci;
1211         int evt;
1212
1213         if (last->transfer_status == 0)
1214                 /* This descriptor isn't done yet, stop iteration. */
1215                 return 0;
1216
1217         driver_data = (struct driver_data *) &d[3];
1218         packet = driver_data->packet;
1219         if (packet == NULL)
1220                 /* This packet was cancelled, just continue. */
1221                 return 1;
1222
1223         if (packet->payload_mapped)
1224                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1225                                  packet->payload_length, DMA_TO_DEVICE);
1226
1227         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1228         packet->timestamp = le16_to_cpu(last->res_count);
1229
1230         log_ar_at_event('T', packet->speed, packet->header, evt);
1231
1232         switch (evt) {
1233         case OHCI1394_evt_timeout:
1234                 /* Async response transmit timed out. */
1235                 packet->ack = RCODE_CANCELLED;
1236                 break;
1237
1238         case OHCI1394_evt_flushed:
1239                 /*
1240                  * The packet was flushed should give same error as
1241                  * when we try to use a stale generation count.
1242                  */
1243                 packet->ack = RCODE_GENERATION;
1244                 break;
1245
1246         case OHCI1394_evt_missing_ack:
1247                 /*
1248                  * Using a valid (current) generation count, but the
1249                  * node is not on the bus or not sending acks.
1250                  */
1251                 packet->ack = RCODE_NO_ACK;
1252                 break;
1253
1254         case ACK_COMPLETE + 0x10:
1255         case ACK_PENDING + 0x10:
1256         case ACK_BUSY_X + 0x10:
1257         case ACK_BUSY_A + 0x10:
1258         case ACK_BUSY_B + 0x10:
1259         case ACK_DATA_ERROR + 0x10:
1260         case ACK_TYPE_ERROR + 0x10:
1261                 packet->ack = evt - 0x10;
1262                 break;
1263
1264         default:
1265                 packet->ack = RCODE_SEND_ERROR;
1266                 break;
1267         }
1268
1269         packet->callback(packet, &ohci->card, packet->ack);
1270
1271         return 1;
1272 }
1273
1274 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1275 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1276 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1277 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1278 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1279
1280 static void handle_local_rom(struct fw_ohci *ohci,
1281                              struct fw_packet *packet, u32 csr)
1282 {
1283         struct fw_packet response;
1284         int tcode, length, i;
1285
1286         tcode = HEADER_GET_TCODE(packet->header[0]);
1287         if (TCODE_IS_BLOCK_PACKET(tcode))
1288                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1289         else
1290                 length = 4;
1291
1292         i = csr - CSR_CONFIG_ROM;
1293         if (i + length > CONFIG_ROM_SIZE) {
1294                 fw_fill_response(&response, packet->header,
1295                                  RCODE_ADDRESS_ERROR, NULL, 0);
1296         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1297                 fw_fill_response(&response, packet->header,
1298                                  RCODE_TYPE_ERROR, NULL, 0);
1299         } else {
1300                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1301                                  (void *) ohci->config_rom + i, length);
1302         }
1303
1304         fw_core_handle_response(&ohci->card, &response);
1305 }
1306
1307 static void handle_local_lock(struct fw_ohci *ohci,
1308                               struct fw_packet *packet, u32 csr)
1309 {
1310         struct fw_packet response;
1311         int tcode, length, ext_tcode, sel, try;
1312         __be32 *payload, lock_old;
1313         u32 lock_arg, lock_data;
1314
1315         tcode = HEADER_GET_TCODE(packet->header[0]);
1316         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1317         payload = packet->payload;
1318         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1319
1320         if (tcode == TCODE_LOCK_REQUEST &&
1321             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1322                 lock_arg = be32_to_cpu(payload[0]);
1323                 lock_data = be32_to_cpu(payload[1]);
1324         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1325                 lock_arg = 0;
1326                 lock_data = 0;
1327         } else {
1328                 fw_fill_response(&response, packet->header,
1329                                  RCODE_TYPE_ERROR, NULL, 0);
1330                 goto out;
1331         }
1332
1333         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1334         reg_write(ohci, OHCI1394_CSRData, lock_data);
1335         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1336         reg_write(ohci, OHCI1394_CSRControl, sel);
1337
1338         for (try = 0; try < 20; try++)
1339                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1340                         lock_old = cpu_to_be32(reg_read(ohci,
1341                                                         OHCI1394_CSRData));
1342                         fw_fill_response(&response, packet->header,
1343                                          RCODE_COMPLETE,
1344                                          &lock_old, sizeof(lock_old));
1345                         goto out;
1346                 }
1347
1348         fw_error("swap not done (CSR lock timeout)\n");
1349         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1350
1351  out:
1352         fw_core_handle_response(&ohci->card, &response);
1353 }
1354
1355 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1356 {
1357         u64 offset, csr;
1358
1359         if (ctx == &ctx->ohci->at_request_ctx) {
1360                 packet->ack = ACK_PENDING;
1361                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1362         }
1363
1364         offset =
1365                 ((unsigned long long)
1366                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1367                 packet->header[2];
1368         csr = offset - CSR_REGISTER_BASE;
1369
1370         /* Handle config rom reads. */
1371         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1372                 handle_local_rom(ctx->ohci, packet, csr);
1373         else switch (csr) {
1374         case CSR_BUS_MANAGER_ID:
1375         case CSR_BANDWIDTH_AVAILABLE:
1376         case CSR_CHANNELS_AVAILABLE_HI:
1377         case CSR_CHANNELS_AVAILABLE_LO:
1378                 handle_local_lock(ctx->ohci, packet, csr);
1379                 break;
1380         default:
1381                 if (ctx == &ctx->ohci->at_request_ctx)
1382                         fw_core_handle_request(&ctx->ohci->card, packet);
1383                 else
1384                         fw_core_handle_response(&ctx->ohci->card, packet);
1385                 break;
1386         }
1387
1388         if (ctx == &ctx->ohci->at_response_ctx) {
1389                 packet->ack = ACK_COMPLETE;
1390                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1391         }
1392 }
1393
1394 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1395 {
1396         unsigned long flags;
1397         int ret;
1398
1399         spin_lock_irqsave(&ctx->ohci->lock, flags);
1400
1401         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1402             ctx->ohci->generation == packet->generation) {
1403                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1404                 handle_local_request(ctx, packet);
1405                 return;
1406         }
1407
1408         ret = at_context_queue_packet(ctx, packet);
1409         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1410
1411         if (ret < 0)
1412                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1413
1414 }
1415
1416 static u32 cycle_timer_ticks(u32 cycle_timer)
1417 {
1418         u32 ticks;
1419
1420         ticks = cycle_timer & 0xfff;
1421         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1422         ticks += (3072 * 8000) * (cycle_timer >> 25);
1423
1424         return ticks;
1425 }
1426
1427 /*
1428  * Some controllers exhibit one or more of the following bugs when updating the
1429  * iso cycle timer register:
1430  *  - When the lowest six bits are wrapping around to zero, a read that happens
1431  *    at the same time will return garbage in the lowest ten bits.
1432  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1433  *    not incremented for about 60 ns.
1434  *  - Occasionally, the entire register reads zero.
1435  *
1436  * To catch these, we read the register three times and ensure that the
1437  * difference between each two consecutive reads is approximately the same, i.e.
1438  * less than twice the other.  Furthermore, any negative difference indicates an
1439  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1440  * execute, so we have enough precision to compute the ratio of the differences.)
1441  */
1442 static u32 get_cycle_time(struct fw_ohci *ohci)
1443 {
1444         u32 c0, c1, c2;
1445         u32 t0, t1, t2;
1446         s32 diff01, diff12;
1447         int i;
1448
1449         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1450
1451         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1452                 i = 0;
1453                 c1 = c2;
1454                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1455                 do {
1456                         c0 = c1;
1457                         c1 = c2;
1458                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1459                         t0 = cycle_timer_ticks(c0);
1460                         t1 = cycle_timer_ticks(c1);
1461                         t2 = cycle_timer_ticks(c2);
1462                         diff01 = t1 - t0;
1463                         diff12 = t2 - t1;
1464                 } while ((diff01 <= 0 || diff12 <= 0 ||
1465                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1466                          && i++ < 20);
1467         }
1468
1469         return c2;
1470 }
1471
1472 /*
1473  * This function has to be called at least every 64 seconds.  The bus_time
1474  * field stores not only the upper 25 bits of the BUS_TIME register but also
1475  * the most significant bit of the cycle timer in bit 6 so that we can detect
1476  * changes in this bit.
1477  */
1478 static u32 update_bus_time(struct fw_ohci *ohci)
1479 {
1480         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1481
1482         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1483                 ohci->bus_time += 0x40;
1484
1485         return ohci->bus_time | cycle_time_seconds;
1486 }
1487
1488 static void bus_reset_tasklet(unsigned long data)
1489 {
1490         struct fw_ohci *ohci = (struct fw_ohci *)data;
1491         int self_id_count, i, j, reg;
1492         int generation, new_generation;
1493         unsigned long flags;
1494         void *free_rom = NULL;
1495         dma_addr_t free_rom_bus = 0;
1496         bool is_new_root;
1497
1498         reg = reg_read(ohci, OHCI1394_NodeID);
1499         if (!(reg & OHCI1394_NodeID_idValid)) {
1500                 fw_notify("node ID not valid, new bus reset in progress\n");
1501                 return;
1502         }
1503         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1504                 fw_notify("malconfigured bus\n");
1505                 return;
1506         }
1507         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1508                                OHCI1394_NodeID_nodeNumber);
1509
1510         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1511         if (!(ohci->is_root && is_new_root))
1512                 reg_write(ohci, OHCI1394_LinkControlSet,
1513                           OHCI1394_LinkControl_cycleMaster);
1514         ohci->is_root = is_new_root;
1515
1516         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1517         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1518                 fw_notify("inconsistent self IDs\n");
1519                 return;
1520         }
1521         /*
1522          * The count in the SelfIDCount register is the number of
1523          * bytes in the self ID receive buffer.  Since we also receive
1524          * the inverted quadlets and a header quadlet, we shift one
1525          * bit extra to get the actual number of self IDs.
1526          */
1527         self_id_count = (reg >> 3) & 0xff;
1528         if (self_id_count == 0 || self_id_count > 252) {
1529                 fw_notify("inconsistent self IDs\n");
1530                 return;
1531         }
1532         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1533         rmb();
1534
1535         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1536                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1537                         fw_notify("inconsistent self IDs\n");
1538                         return;
1539                 }
1540                 ohci->self_id_buffer[j] =
1541                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1542         }
1543         rmb();
1544
1545         /*
1546          * Check the consistency of the self IDs we just read.  The
1547          * problem we face is that a new bus reset can start while we
1548          * read out the self IDs from the DMA buffer. If this happens,
1549          * the DMA buffer will be overwritten with new self IDs and we
1550          * will read out inconsistent data.  The OHCI specification
1551          * (section 11.2) recommends a technique similar to
1552          * linux/seqlock.h, where we remember the generation of the
1553          * self IDs in the buffer before reading them out and compare
1554          * it to the current generation after reading them out.  If
1555          * the two generations match we know we have a consistent set
1556          * of self IDs.
1557          */
1558
1559         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1560         if (new_generation != generation) {
1561                 fw_notify("recursive bus reset detected, "
1562                           "discarding self ids\n");
1563                 return;
1564         }
1565
1566         /* FIXME: Document how the locking works. */
1567         spin_lock_irqsave(&ohci->lock, flags);
1568
1569         ohci->generation = generation;
1570         context_stop(&ohci->at_request_ctx);
1571         context_stop(&ohci->at_response_ctx);
1572         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1573
1574         if (ohci->quirks & QUIRK_RESET_PACKET)
1575                 ohci->request_generation = generation;
1576
1577         /*
1578          * This next bit is unrelated to the AT context stuff but we
1579          * have to do it under the spinlock also.  If a new config rom
1580          * was set up before this reset, the old one is now no longer
1581          * in use and we can free it. Update the config rom pointers
1582          * to point to the current config rom and clear the
1583          * next_config_rom pointer so a new update can take place.
1584          */
1585
1586         if (ohci->next_config_rom != NULL) {
1587                 if (ohci->next_config_rom != ohci->config_rom) {
1588                         free_rom      = ohci->config_rom;
1589                         free_rom_bus  = ohci->config_rom_bus;
1590                 }
1591                 ohci->config_rom      = ohci->next_config_rom;
1592                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1593                 ohci->next_config_rom = NULL;
1594
1595                 /*
1596                  * Restore config_rom image and manually update
1597                  * config_rom registers.  Writing the header quadlet
1598                  * will indicate that the config rom is ready, so we
1599                  * do that last.
1600                  */
1601                 reg_write(ohci, OHCI1394_BusOptions,
1602                           be32_to_cpu(ohci->config_rom[2]));
1603                 ohci->config_rom[0] = ohci->next_header;
1604                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1605                           be32_to_cpu(ohci->next_header));
1606         }
1607
1608 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1609         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1610         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1611 #endif
1612
1613         spin_unlock_irqrestore(&ohci->lock, flags);
1614
1615         if (free_rom)
1616                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1617                                   free_rom, free_rom_bus);
1618
1619         log_selfids(ohci->node_id, generation,
1620                     self_id_count, ohci->self_id_buffer);
1621
1622         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1623                                  self_id_count, ohci->self_id_buffer,
1624                                  ohci->csr_state_setclear_abdicate);
1625         ohci->csr_state_setclear_abdicate = false;
1626 }
1627
1628 static irqreturn_t irq_handler(int irq, void *data)
1629 {
1630         struct fw_ohci *ohci = data;
1631         u32 event, iso_event;
1632         int i;
1633
1634         event = reg_read(ohci, OHCI1394_IntEventClear);
1635
1636         if (!event || !~event)
1637                 return IRQ_NONE;
1638
1639         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1640         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1641         log_irqs(event);
1642
1643         if (event & OHCI1394_selfIDComplete)
1644                 tasklet_schedule(&ohci->bus_reset_tasklet);
1645
1646         if (event & OHCI1394_RQPkt)
1647                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1648
1649         if (event & OHCI1394_RSPkt)
1650                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1651
1652         if (event & OHCI1394_reqTxComplete)
1653                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1654
1655         if (event & OHCI1394_respTxComplete)
1656                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1657
1658         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1659         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1660
1661         while (iso_event) {
1662                 i = ffs(iso_event) - 1;
1663                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1664                 iso_event &= ~(1 << i);
1665         }
1666
1667         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1668         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1669
1670         while (iso_event) {
1671                 i = ffs(iso_event) - 1;
1672                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1673                 iso_event &= ~(1 << i);
1674         }
1675
1676         if (unlikely(event & OHCI1394_regAccessFail))
1677                 fw_error("Register access failure - "
1678                          "please notify linux1394-devel@lists.sf.net\n");
1679
1680         if (unlikely(event & OHCI1394_postedWriteErr))
1681                 fw_error("PCI posted write error\n");
1682
1683         if (unlikely(event & OHCI1394_cycleTooLong)) {
1684                 if (printk_ratelimit())
1685                         fw_notify("isochronous cycle too long\n");
1686                 reg_write(ohci, OHCI1394_LinkControlSet,
1687                           OHCI1394_LinkControl_cycleMaster);
1688         }
1689
1690         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1691                 /*
1692                  * We need to clear this event bit in order to make
1693                  * cycleMatch isochronous I/O work.  In theory we should
1694                  * stop active cycleMatch iso contexts now and restart
1695                  * them at least two cycles later.  (FIXME?)
1696                  */
1697                 if (printk_ratelimit())
1698                         fw_notify("isochronous cycle inconsistent\n");
1699         }
1700
1701         if (event & OHCI1394_cycle64Seconds) {
1702                 spin_lock(&ohci->lock);
1703                 update_bus_time(ohci);
1704                 spin_unlock(&ohci->lock);
1705         }
1706
1707         return IRQ_HANDLED;
1708 }
1709
1710 static int software_reset(struct fw_ohci *ohci)
1711 {
1712         int i;
1713
1714         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1715
1716         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1717                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1718                      OHCI1394_HCControl_softReset) == 0)
1719                         return 0;
1720                 msleep(1);
1721         }
1722
1723         return -EBUSY;
1724 }
1725
1726 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1727 {
1728         size_t size = length * 4;
1729
1730         memcpy(dest, src, size);
1731         if (size < CONFIG_ROM_SIZE)
1732                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1733 }
1734
1735 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1736 {
1737         bool enable_1394a;
1738         int ret, clear, set, offset;
1739
1740         /* Check if the driver should configure link and PHY. */
1741         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1742               OHCI1394_HCControl_programPhyEnable))
1743                 return 0;
1744
1745         /* Paranoia: check whether the PHY supports 1394a, too. */
1746         enable_1394a = false;
1747         ret = read_phy_reg(ohci, 2);
1748         if (ret < 0)
1749                 return ret;
1750         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1751                 ret = read_paged_phy_reg(ohci, 1, 8);
1752                 if (ret < 0)
1753                         return ret;
1754                 if (ret >= 1)
1755                         enable_1394a = true;
1756         }
1757
1758         if (ohci->quirks & QUIRK_NO_1394A)
1759                 enable_1394a = false;
1760
1761         /* Configure PHY and link consistently. */
1762         if (enable_1394a) {
1763                 clear = 0;
1764                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1765         } else {
1766                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1767                 set = 0;
1768         }
1769         ret = update_phy_reg(ohci, 5, clear, set);
1770         if (ret < 0)
1771                 return ret;
1772
1773         if (enable_1394a)
1774                 offset = OHCI1394_HCControlSet;
1775         else
1776                 offset = OHCI1394_HCControlClear;
1777         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1778
1779         /* Clean up: configuration has been taken care of. */
1780         reg_write(ohci, OHCI1394_HCControlClear,
1781                   OHCI1394_HCControl_programPhyEnable);
1782
1783         return 0;
1784 }
1785
1786 static int ohci_enable(struct fw_card *card,
1787                        const __be32 *config_rom, size_t length)
1788 {
1789         struct fw_ohci *ohci = fw_ohci(card);
1790         struct pci_dev *dev = to_pci_dev(card->device);
1791         u32 lps, seconds, version, irqs;
1792         int i, ret;
1793
1794         if (software_reset(ohci)) {
1795                 fw_error("Failed to reset ohci card.\n");
1796                 return -EBUSY;
1797         }
1798
1799         /*
1800          * Now enable LPS, which we need in order to start accessing
1801          * most of the registers.  In fact, on some cards (ALI M5251),
1802          * accessing registers in the SClk domain without LPS enabled
1803          * will lock up the machine.  Wait 50msec to make sure we have
1804          * full link enabled.  However, with some cards (well, at least
1805          * a JMicron PCIe card), we have to try again sometimes.
1806          */
1807         reg_write(ohci, OHCI1394_HCControlSet,
1808                   OHCI1394_HCControl_LPS |
1809                   OHCI1394_HCControl_postedWriteEnable);
1810         flush_writes(ohci);
1811
1812         for (lps = 0, i = 0; !lps && i < 3; i++) {
1813                 msleep(50);
1814                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1815                       OHCI1394_HCControl_LPS;
1816         }
1817
1818         if (!lps) {
1819                 fw_error("Failed to set Link Power Status\n");
1820                 return -EIO;
1821         }
1822
1823         reg_write(ohci, OHCI1394_HCControlClear,
1824                   OHCI1394_HCControl_noByteSwapData);
1825
1826         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1827         reg_write(ohci, OHCI1394_LinkControlSet,
1828                   OHCI1394_LinkControl_rcvSelfID |
1829                   OHCI1394_LinkControl_rcvPhyPkt |
1830                   OHCI1394_LinkControl_cycleTimerEnable |
1831                   OHCI1394_LinkControl_cycleMaster);
1832
1833         reg_write(ohci, OHCI1394_ATRetries,
1834                   OHCI1394_MAX_AT_REQ_RETRIES |
1835                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1836                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1837                   (200 << 16));
1838
1839         seconds = lower_32_bits(get_seconds());
1840         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1841         ohci->bus_time = seconds & ~0x3f;
1842
1843         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1844         if (version >= OHCI_VERSION_1_1) {
1845                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1846                           0xfffffffe);
1847                 card->broadcast_channel_auto_allocated = true;
1848         }
1849
1850         /* Get implemented bits of the priority arbitration request counter. */
1851         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1852         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1853         reg_write(ohci, OHCI1394_FairnessControl, 0);
1854         card->priority_budget_implemented = ohci->pri_req_max != 0;
1855
1856         ar_context_run(&ohci->ar_request_ctx);
1857         ar_context_run(&ohci->ar_response_ctx);
1858
1859         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1860         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1861         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1862
1863         ret = configure_1394a_enhancements(ohci);
1864         if (ret < 0)
1865                 return ret;
1866
1867         /* Activate link_on bit and contender bit in our self ID packets.*/
1868         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1869         if (ret < 0)
1870                 return ret;
1871
1872         /*
1873          * When the link is not yet enabled, the atomic config rom
1874          * update mechanism described below in ohci_set_config_rom()
1875          * is not active.  We have to update ConfigRomHeader and
1876          * BusOptions manually, and the write to ConfigROMmap takes
1877          * effect immediately.  We tie this to the enabling of the
1878          * link, so we have a valid config rom before enabling - the
1879          * OHCI requires that ConfigROMhdr and BusOptions have valid
1880          * values before enabling.
1881          *
1882          * However, when the ConfigROMmap is written, some controllers
1883          * always read back quadlets 0 and 2 from the config rom to
1884          * the ConfigRomHeader and BusOptions registers on bus reset.
1885          * They shouldn't do that in this initial case where the link
1886          * isn't enabled.  This means we have to use the same
1887          * workaround here, setting the bus header to 0 and then write
1888          * the right values in the bus reset tasklet.
1889          */
1890
1891         if (config_rom) {
1892                 ohci->next_config_rom =
1893                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1894                                            &ohci->next_config_rom_bus,
1895                                            GFP_KERNEL);
1896                 if (ohci->next_config_rom == NULL)
1897                         return -ENOMEM;
1898
1899                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1900         } else {
1901                 /*
1902                  * In the suspend case, config_rom is NULL, which
1903                  * means that we just reuse the old config rom.
1904                  */
1905                 ohci->next_config_rom = ohci->config_rom;
1906                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1907         }
1908
1909         ohci->next_header = ohci->next_config_rom[0];
1910         ohci->next_config_rom[0] = 0;
1911         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1912         reg_write(ohci, OHCI1394_BusOptions,
1913                   be32_to_cpu(ohci->next_config_rom[2]));
1914         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1915
1916         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1917
1918         if (!(ohci->quirks & QUIRK_NO_MSI))
1919                 pci_enable_msi(dev);
1920         if (request_irq(dev->irq, irq_handler,
1921                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1922                         ohci_driver_name, ohci)) {
1923                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1924                 pci_disable_msi(dev);
1925                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1926                                   ohci->config_rom, ohci->config_rom_bus);
1927                 return -EIO;
1928         }
1929
1930         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1931                 OHCI1394_RQPkt | OHCI1394_RSPkt |
1932                 OHCI1394_isochTx | OHCI1394_isochRx |
1933                 OHCI1394_postedWriteErr |
1934                 OHCI1394_selfIDComplete |
1935                 OHCI1394_regAccessFail |
1936                 OHCI1394_cycle64Seconds |
1937                 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1938                 OHCI1394_masterIntEnable;
1939         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1940                 irqs |= OHCI1394_busReset;
1941         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1942
1943         reg_write(ohci, OHCI1394_HCControlSet,
1944                   OHCI1394_HCControl_linkEnable |
1945                   OHCI1394_HCControl_BIBimageValid);
1946         flush_writes(ohci);
1947
1948         /* We are ready to go, reset bus to finish initialization. */
1949         fw_schedule_bus_reset(&ohci->card, false, true);
1950
1951         return 0;
1952 }
1953
1954 static int ohci_set_config_rom(struct fw_card *card,
1955                                const __be32 *config_rom, size_t length)
1956 {
1957         struct fw_ohci *ohci;
1958         unsigned long flags;
1959         int ret = -EBUSY;
1960         __be32 *next_config_rom;
1961         dma_addr_t uninitialized_var(next_config_rom_bus);
1962
1963         ohci = fw_ohci(card);
1964
1965         /*
1966          * When the OHCI controller is enabled, the config rom update
1967          * mechanism is a bit tricky, but easy enough to use.  See
1968          * section 5.5.6 in the OHCI specification.
1969          *
1970          * The OHCI controller caches the new config rom address in a
1971          * shadow register (ConfigROMmapNext) and needs a bus reset
1972          * for the changes to take place.  When the bus reset is
1973          * detected, the controller loads the new values for the
1974          * ConfigRomHeader and BusOptions registers from the specified
1975          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1976          * shadow register. All automatically and atomically.
1977          *
1978          * Now, there's a twist to this story.  The automatic load of
1979          * ConfigRomHeader and BusOptions doesn't honor the
1980          * noByteSwapData bit, so with a be32 config rom, the
1981          * controller will load be32 values in to these registers
1982          * during the atomic update, even on litte endian
1983          * architectures.  The workaround we use is to put a 0 in the
1984          * header quadlet; 0 is endian agnostic and means that the
1985          * config rom isn't ready yet.  In the bus reset tasklet we
1986          * then set up the real values for the two registers.
1987          *
1988          * We use ohci->lock to avoid racing with the code that sets
1989          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1990          */
1991
1992         next_config_rom =
1993                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1994                                    &next_config_rom_bus, GFP_KERNEL);
1995         if (next_config_rom == NULL)
1996                 return -ENOMEM;
1997
1998         spin_lock_irqsave(&ohci->lock, flags);
1999
2000         if (ohci->next_config_rom == NULL) {
2001                 ohci->next_config_rom = next_config_rom;
2002                 ohci->next_config_rom_bus = next_config_rom_bus;
2003
2004                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2005
2006                 ohci->next_header = config_rom[0];
2007                 ohci->next_config_rom[0] = 0;
2008
2009                 reg_write(ohci, OHCI1394_ConfigROMmap,
2010                           ohci->next_config_rom_bus);
2011                 ret = 0;
2012         }
2013
2014         spin_unlock_irqrestore(&ohci->lock, flags);
2015
2016         /*
2017          * Now initiate a bus reset to have the changes take
2018          * effect. We clean up the old config rom memory and DMA
2019          * mappings in the bus reset tasklet, since the OHCI
2020          * controller could need to access it before the bus reset
2021          * takes effect.
2022          */
2023         if (ret == 0)
2024                 fw_schedule_bus_reset(&ohci->card, true, true);
2025         else
2026                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2027                                   next_config_rom, next_config_rom_bus);
2028
2029         return ret;
2030 }
2031
2032 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2033 {
2034         struct fw_ohci *ohci = fw_ohci(card);
2035
2036         at_context_transmit(&ohci->at_request_ctx, packet);
2037 }
2038
2039 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2040 {
2041         struct fw_ohci *ohci = fw_ohci(card);
2042
2043         at_context_transmit(&ohci->at_response_ctx, packet);
2044 }
2045
2046 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2047 {
2048         struct fw_ohci *ohci = fw_ohci(card);
2049         struct context *ctx = &ohci->at_request_ctx;
2050         struct driver_data *driver_data = packet->driver_data;
2051         int ret = -ENOENT;
2052
2053         tasklet_disable(&ctx->tasklet);
2054
2055         if (packet->ack != 0)
2056                 goto out;
2057
2058         if (packet->payload_mapped)
2059                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2060                                  packet->payload_length, DMA_TO_DEVICE);
2061
2062         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2063         driver_data->packet = NULL;
2064         packet->ack = RCODE_CANCELLED;
2065         packet->callback(packet, &ohci->card, packet->ack);
2066         ret = 0;
2067  out:
2068         tasklet_enable(&ctx->tasklet);
2069
2070         return ret;
2071 }
2072
2073 static int ohci_enable_phys_dma(struct fw_card *card,
2074                                 int node_id, int generation)
2075 {
2076 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2077         return 0;
2078 #else
2079         struct fw_ohci *ohci = fw_ohci(card);
2080         unsigned long flags;
2081         int n, ret = 0;
2082
2083         /*
2084          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2085          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2086          */
2087
2088         spin_lock_irqsave(&ohci->lock, flags);
2089
2090         if (ohci->generation != generation) {
2091                 ret = -ESTALE;
2092                 goto out;
2093         }
2094
2095         /*
2096          * Note, if the node ID contains a non-local bus ID, physical DMA is
2097          * enabled for _all_ nodes on remote buses.
2098          */
2099
2100         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2101         if (n < 32)
2102                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2103         else
2104                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2105
2106         flush_writes(ohci);
2107  out:
2108         spin_unlock_irqrestore(&ohci->lock, flags);
2109
2110         return ret;
2111 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2112 }
2113
2114 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2115 {
2116         struct fw_ohci *ohci = fw_ohci(card);
2117         unsigned long flags;
2118         u32 value;
2119
2120         switch (csr_offset) {
2121         case CSR_STATE_CLEAR:
2122         case CSR_STATE_SET:
2123                 if (ohci->is_root &&
2124                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2125                      OHCI1394_LinkControl_cycleMaster))
2126                         value = CSR_STATE_BIT_CMSTR;
2127                 else
2128                         value = 0;
2129                 if (ohci->csr_state_setclear_abdicate)
2130                         value |= CSR_STATE_BIT_ABDICATE;
2131
2132                 return value;
2133
2134         case CSR_NODE_IDS:
2135                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2136
2137         case CSR_CYCLE_TIME:
2138                 return get_cycle_time(ohci);
2139
2140         case CSR_BUS_TIME:
2141                 /*
2142                  * We might be called just after the cycle timer has wrapped
2143                  * around but just before the cycle64Seconds handler, so we
2144                  * better check here, too, if the bus time needs to be updated.
2145                  */
2146                 spin_lock_irqsave(&ohci->lock, flags);
2147                 value = update_bus_time(ohci);
2148                 spin_unlock_irqrestore(&ohci->lock, flags);
2149                 return value;
2150
2151         case CSR_BUSY_TIMEOUT:
2152                 value = reg_read(ohci, OHCI1394_ATRetries);
2153                 return (value >> 4) & 0x0ffff00f;
2154
2155         case CSR_PRIORITY_BUDGET:
2156                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2157                         (ohci->pri_req_max << 8);
2158
2159         default:
2160                 WARN_ON(1);
2161                 return 0;
2162         }
2163 }
2164
2165 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2166 {
2167         struct fw_ohci *ohci = fw_ohci(card);
2168         unsigned long flags;
2169
2170         switch (csr_offset) {
2171         case CSR_STATE_CLEAR:
2172                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2173                         reg_write(ohci, OHCI1394_LinkControlClear,
2174                                   OHCI1394_LinkControl_cycleMaster);
2175                         flush_writes(ohci);
2176                 }
2177                 if (value & CSR_STATE_BIT_ABDICATE)
2178                         ohci->csr_state_setclear_abdicate = false;
2179                 break;
2180
2181         case CSR_STATE_SET:
2182                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2183                         reg_write(ohci, OHCI1394_LinkControlSet,
2184                                   OHCI1394_LinkControl_cycleMaster);
2185                         flush_writes(ohci);
2186                 }
2187                 if (value & CSR_STATE_BIT_ABDICATE)
2188                         ohci->csr_state_setclear_abdicate = true;
2189                 break;
2190
2191         case CSR_NODE_IDS:
2192                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2193                 flush_writes(ohci);
2194                 break;
2195
2196         case CSR_CYCLE_TIME:
2197                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2198                 reg_write(ohci, OHCI1394_IntEventSet,
2199                           OHCI1394_cycleInconsistent);
2200                 flush_writes(ohci);
2201                 break;
2202
2203         case CSR_BUS_TIME:
2204                 spin_lock_irqsave(&ohci->lock, flags);
2205                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2206                 spin_unlock_irqrestore(&ohci->lock, flags);
2207                 break;
2208
2209         case CSR_BUSY_TIMEOUT:
2210                 value = (value & 0xf) | ((value & 0xf) << 4) |
2211                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2212                 reg_write(ohci, OHCI1394_ATRetries, value);
2213                 flush_writes(ohci);
2214                 break;
2215
2216         case CSR_PRIORITY_BUDGET:
2217                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2218                 flush_writes(ohci);
2219                 break;
2220
2221         default:
2222                 WARN_ON(1);
2223                 break;
2224         }
2225 }
2226
2227 static void copy_iso_headers(struct iso_context *ctx, void *p)
2228 {
2229         int i = ctx->header_length;
2230
2231         if (i + ctx->base.header_size > PAGE_SIZE)
2232                 return;
2233
2234         /*
2235          * The iso header is byteswapped to little endian by
2236          * the controller, but the remaining header quadlets
2237          * are big endian.  We want to present all the headers
2238          * as big endian, so we have to swap the first quadlet.
2239          */
2240         if (ctx->base.header_size > 0)
2241                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2242         if (ctx->base.header_size > 4)
2243                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2244         if (ctx->base.header_size > 8)
2245                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2246         ctx->header_length += ctx->base.header_size;
2247 }
2248
2249 static int handle_ir_packet_per_buffer(struct context *context,
2250                                        struct descriptor *d,
2251                                        struct descriptor *last)
2252 {
2253         struct iso_context *ctx =
2254                 container_of(context, struct iso_context, context);
2255         struct descriptor *pd;
2256         __le32 *ir_header;
2257         void *p;
2258
2259         for (pd = d; pd <= last; pd++)
2260                 if (pd->transfer_status)
2261                         break;
2262         if (pd > last)
2263                 /* Descriptor(s) not done yet, stop iteration */
2264                 return 0;
2265
2266         p = last + 1;
2267         copy_iso_headers(ctx, p);
2268
2269         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2270                 ir_header = (__le32 *) p;
2271                 ctx->base.callback.sc(&ctx->base,
2272                                       le32_to_cpu(ir_header[0]) & 0xffff,
2273                                       ctx->header_length, ctx->header,
2274                                       ctx->base.callback_data);
2275                 ctx->header_length = 0;
2276         }
2277
2278         return 1;
2279 }
2280
2281 /* d == last because each descriptor block is only a single descriptor. */
2282 static int handle_ir_buffer_fill(struct context *context,
2283                                  struct descriptor *d,
2284                                  struct descriptor *last)
2285 {
2286         struct iso_context *ctx =
2287                 container_of(context, struct iso_context, context);
2288
2289         if (!last->transfer_status)
2290                 /* Descriptor(s) not done yet, stop iteration */
2291                 return 0;
2292
2293         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2294                 ctx->base.callback.mc(&ctx->base,
2295                                       le32_to_cpu(last->data_address) +
2296                                       le16_to_cpu(last->req_count) -
2297                                       le16_to_cpu(last->res_count),
2298                                       ctx->base.callback_data);
2299
2300         return 1;
2301 }
2302
2303 static int handle_it_packet(struct context *context,
2304                             struct descriptor *d,
2305                             struct descriptor *last)
2306 {
2307         struct iso_context *ctx =
2308                 container_of(context, struct iso_context, context);
2309         int i;
2310         struct descriptor *pd;
2311
2312         for (pd = d; pd <= last; pd++)
2313                 if (pd->transfer_status)
2314                         break;
2315         if (pd > last)
2316                 /* Descriptor(s) not done yet, stop iteration */
2317                 return 0;
2318
2319         i = ctx->header_length;
2320         if (i + 4 < PAGE_SIZE) {
2321                 /* Present this value as big-endian to match the receive code */
2322                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2323                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2324                                 le16_to_cpu(pd->res_count));
2325                 ctx->header_length += 4;
2326         }
2327         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2328                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2329                                       ctx->header_length, ctx->header,
2330                                       ctx->base.callback_data);
2331                 ctx->header_length = 0;
2332         }
2333         return 1;
2334 }
2335
2336 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2337 {
2338         u32 hi = channels >> 32, lo = channels;
2339
2340         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2341         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2342         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2343         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2344         mmiowb();
2345         ohci->mc_channels = channels;
2346 }
2347
2348 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2349                                 int type, int channel, size_t header_size)
2350 {
2351         struct fw_ohci *ohci = fw_ohci(card);
2352         struct iso_context *uninitialized_var(ctx);
2353         descriptor_callback_t uninitialized_var(callback);
2354         u64 *uninitialized_var(channels);
2355         u32 *uninitialized_var(mask), uninitialized_var(regs);
2356         unsigned long flags;
2357         int index, ret = -EBUSY;
2358
2359         spin_lock_irqsave(&ohci->lock, flags);
2360
2361         switch (type) {
2362         case FW_ISO_CONTEXT_TRANSMIT:
2363                 mask     = &ohci->it_context_mask;
2364                 callback = handle_it_packet;
2365                 index    = ffs(*mask) - 1;
2366                 if (index >= 0) {
2367                         *mask &= ~(1 << index);
2368                         regs = OHCI1394_IsoXmitContextBase(index);
2369                         ctx  = &ohci->it_context_list[index];
2370                 }
2371                 break;
2372
2373         case FW_ISO_CONTEXT_RECEIVE:
2374                 channels = &ohci->ir_context_channels;
2375                 mask     = &ohci->ir_context_mask;
2376                 callback = handle_ir_packet_per_buffer;
2377                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2378                 if (index >= 0) {
2379                         *channels &= ~(1ULL << channel);
2380                         *mask     &= ~(1 << index);
2381                         regs = OHCI1394_IsoRcvContextBase(index);
2382                         ctx  = &ohci->ir_context_list[index];
2383                 }
2384                 break;
2385
2386         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2387                 mask     = &ohci->ir_context_mask;
2388                 callback = handle_ir_buffer_fill;
2389                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2390                 if (index >= 0) {
2391                         ohci->mc_allocated = true;
2392                         *mask &= ~(1 << index);
2393                         regs = OHCI1394_IsoRcvContextBase(index);
2394                         ctx  = &ohci->ir_context_list[index];
2395                 }
2396                 break;
2397
2398         default:
2399                 index = -1;
2400                 ret = -ENOSYS;
2401         }
2402
2403         spin_unlock_irqrestore(&ohci->lock, flags);
2404
2405         if (index < 0)
2406                 return ERR_PTR(ret);
2407
2408         memset(ctx, 0, sizeof(*ctx));
2409         ctx->header_length = 0;
2410         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2411         if (ctx->header == NULL) {
2412                 ret = -ENOMEM;
2413                 goto out;
2414         }
2415         ret = context_init(&ctx->context, ohci, regs, callback);
2416         if (ret < 0)
2417                 goto out_with_header;
2418
2419         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2420                 set_multichannel_mask(ohci, 0);
2421
2422         return &ctx->base;
2423
2424  out_with_header:
2425         free_page((unsigned long)ctx->header);
2426  out:
2427         spin_lock_irqsave(&ohci->lock, flags);
2428
2429         switch (type) {
2430         case FW_ISO_CONTEXT_RECEIVE:
2431                 *channels |= 1ULL << channel;
2432                 break;
2433
2434         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2435                 ohci->mc_allocated = false;
2436                 break;
2437         }
2438         *mask |= 1 << index;
2439
2440         spin_unlock_irqrestore(&ohci->lock, flags);
2441
2442         return ERR_PTR(ret);
2443 }
2444
2445 static int ohci_start_iso(struct fw_iso_context *base,
2446                           s32 cycle, u32 sync, u32 tags)
2447 {
2448         struct iso_context *ctx = container_of(base, struct iso_context, base);
2449         struct fw_ohci *ohci = ctx->context.ohci;
2450         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2451         int index;
2452
2453         switch (ctx->base.type) {
2454         case FW_ISO_CONTEXT_TRANSMIT:
2455                 index = ctx - ohci->it_context_list;
2456                 match = 0;
2457                 if (cycle >= 0)
2458                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2459                                 (cycle & 0x7fff) << 16;
2460
2461                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2462                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2463                 context_run(&ctx->context, match);
2464                 break;
2465
2466         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2467                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2468                 /* fall through */
2469         case FW_ISO_CONTEXT_RECEIVE:
2470                 index = ctx - ohci->ir_context_list;
2471                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2472                 if (cycle >= 0) {
2473                         match |= (cycle & 0x07fff) << 12;
2474                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2475                 }
2476
2477                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2478                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2479                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2480                 context_run(&ctx->context, control);
2481                 break;
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int ohci_stop_iso(struct fw_iso_context *base)
2488 {
2489         struct fw_ohci *ohci = fw_ohci(base->card);
2490         struct iso_context *ctx = container_of(base, struct iso_context, base);
2491         int index;
2492
2493         switch (ctx->base.type) {
2494         case FW_ISO_CONTEXT_TRANSMIT:
2495                 index = ctx - ohci->it_context_list;
2496                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2497                 break;
2498
2499         case FW_ISO_CONTEXT_RECEIVE:
2500         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2501                 index = ctx - ohci->ir_context_list;
2502                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2503                 break;
2504         }
2505         flush_writes(ohci);
2506         context_stop(&ctx->context);
2507
2508         return 0;
2509 }
2510
2511 static void ohci_free_iso_context(struct fw_iso_context *base)
2512 {
2513         struct fw_ohci *ohci = fw_ohci(base->card);
2514         struct iso_context *ctx = container_of(base, struct iso_context, base);
2515         unsigned long flags;
2516         int index;
2517
2518         ohci_stop_iso(base);
2519         context_release(&ctx->context);
2520         free_page((unsigned long)ctx->header);
2521
2522         spin_lock_irqsave(&ohci->lock, flags);
2523
2524         switch (base->type) {
2525         case FW_ISO_CONTEXT_TRANSMIT:
2526                 index = ctx - ohci->it_context_list;
2527                 ohci->it_context_mask |= 1 << index;
2528                 break;
2529
2530         case FW_ISO_CONTEXT_RECEIVE:
2531                 index = ctx - ohci->ir_context_list;
2532                 ohci->ir_context_mask |= 1 << index;
2533                 ohci->ir_context_channels |= 1ULL << base->channel;
2534                 break;
2535
2536         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2537                 index = ctx - ohci->ir_context_list;
2538                 ohci->ir_context_mask |= 1 << index;
2539                 ohci->ir_context_channels |= ohci->mc_channels;
2540                 ohci->mc_channels = 0;
2541                 ohci->mc_allocated = false;
2542                 break;
2543         }
2544
2545         spin_unlock_irqrestore(&ohci->lock, flags);
2546 }
2547
2548 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2549 {
2550         struct fw_ohci *ohci = fw_ohci(base->card);
2551         unsigned long flags;
2552         int ret;
2553
2554         switch (base->type) {
2555         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2556
2557                 spin_lock_irqsave(&ohci->lock, flags);
2558
2559                 /* Don't allow multichannel to grab other contexts' channels. */
2560                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2561                         *channels = ohci->ir_context_channels;
2562                         ret = -EBUSY;
2563                 } else {
2564                         set_multichannel_mask(ohci, *channels);
2565                         ret = 0;
2566                 }
2567
2568                 spin_unlock_irqrestore(&ohci->lock, flags);
2569
2570                 break;
2571         default:
2572                 ret = -EINVAL;
2573         }
2574
2575         return ret;
2576 }
2577
2578 static int queue_iso_transmit(struct iso_context *ctx,
2579                               struct fw_iso_packet *packet,
2580                               struct fw_iso_buffer *buffer,
2581                               unsigned long payload)
2582 {
2583         struct descriptor *d, *last, *pd;
2584         struct fw_iso_packet *p;
2585         __le32 *header;
2586         dma_addr_t d_bus, page_bus;
2587         u32 z, header_z, payload_z, irq;
2588         u32 payload_index, payload_end_index, next_page_index;
2589         int page, end_page, i, length, offset;
2590
2591         p = packet;
2592         payload_index = payload;
2593
2594         if (p->skip)
2595                 z = 1;
2596         else
2597                 z = 2;
2598         if (p->header_length > 0)
2599                 z++;
2600
2601         /* Determine the first page the payload isn't contained in. */
2602         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2603         if (p->payload_length > 0)
2604                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2605         else
2606                 payload_z = 0;
2607
2608         z += payload_z;
2609
2610         /* Get header size in number of descriptors. */
2611         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2612
2613         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2614         if (d == NULL)
2615                 return -ENOMEM;
2616
2617         if (!p->skip) {
2618                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2619                 d[0].req_count = cpu_to_le16(8);
2620                 /*
2621                  * Link the skip address to this descriptor itself.  This causes
2622                  * a context to skip a cycle whenever lost cycles or FIFO
2623                  * overruns occur, without dropping the data.  The application
2624                  * should then decide whether this is an error condition or not.
2625                  * FIXME:  Make the context's cycle-lost behaviour configurable?
2626                  */
2627                 d[0].branch_address = cpu_to_le32(d_bus | z);
2628
2629                 header = (__le32 *) &d[1];
2630                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2631                                         IT_HEADER_TAG(p->tag) |
2632                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2633                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2634                                         IT_HEADER_SPEED(ctx->base.speed));
2635                 header[1] =
2636                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2637                                                           p->payload_length));
2638         }
2639
2640         if (p->header_length > 0) {
2641                 d[2].req_count    = cpu_to_le16(p->header_length);
2642                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2643                 memcpy(&d[z], p->header, p->header_length);
2644         }
2645
2646         pd = d + z - payload_z;
2647         payload_end_index = payload_index + p->payload_length;
2648         for (i = 0; i < payload_z; i++) {
2649                 page               = payload_index >> PAGE_SHIFT;
2650                 offset             = payload_index & ~PAGE_MASK;
2651                 next_page_index    = (page + 1) << PAGE_SHIFT;
2652                 length             =
2653                         min(next_page_index, payload_end_index) - payload_index;
2654                 pd[i].req_count    = cpu_to_le16(length);
2655
2656                 page_bus = page_private(buffer->pages[page]);
2657                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2658
2659                 payload_index += length;
2660         }
2661
2662         if (p->interrupt)
2663                 irq = DESCRIPTOR_IRQ_ALWAYS;
2664         else
2665                 irq = DESCRIPTOR_NO_IRQ;
2666
2667         last = z == 2 ? d : d + z - 1;
2668         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2669                                      DESCRIPTOR_STATUS |
2670                                      DESCRIPTOR_BRANCH_ALWAYS |
2671                                      irq);
2672
2673         context_append(&ctx->context, d, z, header_z);
2674
2675         return 0;
2676 }
2677
2678 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2679                                        struct fw_iso_packet *packet,
2680                                        struct fw_iso_buffer *buffer,
2681                                        unsigned long payload)
2682 {
2683         struct descriptor *d, *pd;
2684         dma_addr_t d_bus, page_bus;
2685         u32 z, header_z, rest;
2686         int i, j, length;
2687         int page, offset, packet_count, header_size, payload_per_buffer;
2688
2689         /*
2690          * The OHCI controller puts the isochronous header and trailer in the
2691          * buffer, so we need at least 8 bytes.
2692          */
2693         packet_count = packet->header_length / ctx->base.header_size;
2694         header_size  = max(ctx->base.header_size, (size_t)8);
2695
2696         /* Get header size in number of descriptors. */
2697         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2698         page     = payload >> PAGE_SHIFT;
2699         offset   = payload & ~PAGE_MASK;
2700         payload_per_buffer = packet->payload_length / packet_count;
2701
2702         for (i = 0; i < packet_count; i++) {
2703                 /* d points to the header descriptor */
2704                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2705                 d = context_get_descriptors(&ctx->context,
2706                                 z + header_z, &d_bus);
2707                 if (d == NULL)
2708                         return -ENOMEM;
2709
2710                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2711                                               DESCRIPTOR_INPUT_MORE);
2712                 if (packet->skip && i == 0)
2713                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2714                 d->req_count    = cpu_to_le16(header_size);
2715                 d->res_count    = d->req_count;
2716                 d->transfer_status = 0;
2717                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2718
2719                 rest = payload_per_buffer;
2720                 pd = d;
2721                 for (j = 1; j < z; j++) {
2722                         pd++;
2723                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2724                                                   DESCRIPTOR_INPUT_MORE);
2725
2726                         if (offset + rest < PAGE_SIZE)
2727                                 length = rest;
2728                         else
2729                                 length = PAGE_SIZE - offset;
2730                         pd->req_count = cpu_to_le16(length);
2731                         pd->res_count = pd->req_count;
2732                         pd->transfer_status = 0;
2733
2734                         page_bus = page_private(buffer->pages[page]);
2735                         pd->data_address = cpu_to_le32(page_bus + offset);
2736
2737                         offset = (offset + length) & ~PAGE_MASK;
2738                         rest -= length;
2739                         if (offset == 0)
2740                                 page++;
2741                 }
2742                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2743                                           DESCRIPTOR_INPUT_LAST |
2744                                           DESCRIPTOR_BRANCH_ALWAYS);
2745                 if (packet->interrupt && i == packet_count - 1)
2746                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2747
2748                 context_append(&ctx->context, d, z, header_z);
2749         }
2750
2751         return 0;
2752 }
2753
2754 static int queue_iso_buffer_fill(struct iso_context *ctx,
2755                                  struct fw_iso_packet *packet,
2756                                  struct fw_iso_buffer *buffer,
2757                                  unsigned long payload)
2758 {
2759         struct descriptor *d;
2760         dma_addr_t d_bus, page_bus;
2761         int page, offset, rest, z, i, length;
2762
2763         page   = payload >> PAGE_SHIFT;
2764         offset = payload & ~PAGE_MASK;
2765         rest   = packet->payload_length;
2766
2767         /* We need one descriptor for each page in the buffer. */
2768         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2769
2770         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2771                 return -EFAULT;
2772
2773         for (i = 0; i < z; i++) {
2774                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2775                 if (d == NULL)
2776                         return -ENOMEM;
2777
2778                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2779                                          DESCRIPTOR_BRANCH_ALWAYS);
2780                 if (packet->skip && i == 0)
2781                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2782                 if (packet->interrupt && i == z - 1)
2783                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2784
2785                 if (offset + rest < PAGE_SIZE)
2786                         length = rest;
2787                 else
2788                         length = PAGE_SIZE - offset;
2789                 d->req_count = cpu_to_le16(length);
2790                 d->res_count = d->req_count;
2791                 d->transfer_status = 0;
2792
2793                 page_bus = page_private(buffer->pages[page]);
2794                 d->data_address = cpu_to_le32(page_bus + offset);
2795
2796                 rest -= length;
2797                 offset = 0;
2798                 page++;
2799
2800                 context_append(&ctx->context, d, 1, 0);
2801         }
2802
2803         return 0;
2804 }
2805
2806 static int ohci_queue_iso(struct fw_iso_context *base,
2807                           struct fw_iso_packet *packet,
2808                           struct fw_iso_buffer *buffer,
2809                           unsigned long payload)
2810 {
2811         struct iso_context *ctx = container_of(base, struct iso_context, base);
2812         unsigned long flags;
2813         int ret = -ENOSYS;
2814
2815         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2816         switch (base->type) {
2817         case FW_ISO_CONTEXT_TRANSMIT:
2818                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2819                 break;
2820         case FW_ISO_CONTEXT_RECEIVE:
2821                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2822                 break;
2823         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2824                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2825                 break;
2826         }
2827         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2828
2829         return ret;
2830 }
2831
2832 static const struct fw_card_driver ohci_driver = {
2833         .enable                 = ohci_enable,
2834         .read_phy_reg           = ohci_read_phy_reg,
2835         .update_phy_reg         = ohci_update_phy_reg,
2836         .set_config_rom         = ohci_set_config_rom,
2837         .send_request           = ohci_send_request,
2838         .send_response          = ohci_send_response,
2839         .cancel_packet          = ohci_cancel_packet,
2840         .enable_phys_dma        = ohci_enable_phys_dma,
2841         .read_csr               = ohci_read_csr,
2842         .write_csr              = ohci_write_csr,
2843
2844         .allocate_iso_context   = ohci_allocate_iso_context,
2845         .free_iso_context       = ohci_free_iso_context,
2846         .set_iso_channels       = ohci_set_iso_channels,
2847         .queue_iso              = ohci_queue_iso,
2848         .start_iso              = ohci_start_iso,
2849         .stop_iso               = ohci_stop_iso,
2850 };
2851
2852 #ifdef CONFIG_PPC_PMAC
2853 static void pmac_ohci_on(struct pci_dev *dev)
2854 {
2855         if (machine_is(powermac)) {
2856                 struct device_node *ofn = pci_device_to_OF_node(dev);
2857
2858                 if (ofn) {
2859                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2860                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2861                 }
2862         }
2863 }
2864
2865 static void pmac_ohci_off(struct pci_dev *dev)
2866 {
2867         if (machine_is(powermac)) {
2868                 struct device_node *ofn = pci_device_to_OF_node(dev);
2869
2870                 if (ofn) {
2871                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2872                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2873                 }
2874         }
2875 }
2876 #else
2877 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2878 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2879 #endif /* CONFIG_PPC_PMAC */
2880
2881 static int __devinit pci_probe(struct pci_dev *dev,
2882                                const struct pci_device_id *ent)
2883 {
2884         struct fw_ohci *ohci;
2885         u32 bus_options, max_receive, link_speed, version;
2886         u64 guid;
2887         int i, err, n_ir, n_it;
2888         size_t size;
2889
2890         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2891         if (ohci == NULL) {
2892                 err = -ENOMEM;
2893                 goto fail;
2894         }
2895
2896         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2897
2898         pmac_ohci_on(dev);
2899
2900         err = pci_enable_device(dev);
2901         if (err) {
2902                 fw_error("Failed to enable OHCI hardware\n");
2903                 goto fail_free;
2904         }
2905
2906         pci_set_master(dev);
2907         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2908         pci_set_drvdata(dev, ohci);
2909
2910         spin_lock_init(&ohci->lock);
2911         mutex_init(&ohci->phy_reg_mutex);
2912
2913         tasklet_init(&ohci->bus_reset_tasklet,
2914                      bus_reset_tasklet, (unsigned long)ohci);
2915
2916         err = pci_request_region(dev, 0, ohci_driver_name);
2917         if (err) {
2918                 fw_error("MMIO resource unavailable\n");
2919                 goto fail_disable;
2920         }
2921
2922         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2923         if (ohci->registers == NULL) {
2924                 fw_error("Failed to remap registers\n");
2925                 err = -ENXIO;
2926                 goto fail_iomem;
2927         }
2928
2929         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2930                 if (ohci_quirks[i].vendor == dev->vendor &&
2931                     (ohci_quirks[i].device == dev->device ||
2932                      ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2933                         ohci->quirks = ohci_quirks[i].flags;
2934                         break;
2935                 }
2936         if (param_quirks)
2937                 ohci->quirks = param_quirks;
2938
2939         ar_context_init(&ohci->ar_request_ctx, ohci,
2940                         OHCI1394_AsReqRcvContextControlSet);
2941
2942         ar_context_init(&ohci->ar_response_ctx, ohci,
2943                         OHCI1394_AsRspRcvContextControlSet);
2944
2945         context_init(&ohci->at_request_ctx, ohci,
2946                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2947
2948         context_init(&ohci->at_response_ctx, ohci,
2949                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2950
2951         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2952         ohci->ir_context_channels = ~0ULL;
2953         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2954         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2955         n_ir = hweight32(ohci->ir_context_mask);
2956         size = sizeof(struct iso_context) * n_ir;
2957         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2958
2959         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2960         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2961         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2962         n_it = hweight32(ohci->it_context_mask);
2963         size = sizeof(struct iso_context) * n_it;
2964         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2965
2966         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2967                 err = -ENOMEM;
2968                 goto fail_contexts;
2969         }
2970
2971         /* self-id dma buffer allocation */
2972         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2973                                                SELF_ID_BUF_SIZE,
2974                                                &ohci->self_id_bus,
2975                                                GFP_KERNEL);
2976         if (ohci->self_id_cpu == NULL) {
2977                 err = -ENOMEM;
2978                 goto fail_contexts;
2979         }
2980
2981         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2982         max_receive = (bus_options >> 12) & 0xf;
2983         link_speed = bus_options & 0x7;
2984         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2985                 reg_read(ohci, OHCI1394_GUIDLo);
2986
2987         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2988         if (err)
2989                 goto fail_self_id;
2990
2991         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2992         fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2993                   "%d IR + %d IT contexts, quirks 0x%x\n",
2994                   dev_name(&dev->dev), version >> 16, version & 0xff,
2995                   n_ir, n_it, ohci->quirks);
2996
2997         return 0;
2998
2999  fail_self_id:
3000         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3001                           ohci->self_id_cpu, ohci->self_id_bus);
3002  fail_contexts:
3003         kfree(ohci->ir_context_list);
3004         kfree(ohci->it_context_list);
3005         context_release(&ohci->at_response_ctx);
3006         context_release(&ohci->at_request_ctx);
3007         ar_context_release(&ohci->ar_response_ctx);
3008         ar_context_release(&ohci->ar_request_ctx);
3009         pci_iounmap(dev, ohci->registers);
3010  fail_iomem:
3011         pci_release_region(dev, 0);
3012  fail_disable:
3013         pci_disable_device(dev);
3014  fail_free:
3015         kfree(&ohci->card);
3016         pmac_ohci_off(dev);
3017  fail:
3018         if (err == -ENOMEM)
3019                 fw_error("Out of memory\n");
3020
3021         return err;
3022 }
3023
3024 static void pci_remove(struct pci_dev *dev)
3025 {
3026         struct fw_ohci *ohci;
3027
3028         ohci = pci_get_drvdata(dev);
3029         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3030         flush_writes(ohci);
3031         fw_core_remove_card(&ohci->card);
3032
3033         /*
3034          * FIXME: Fail all pending packets here, now that the upper
3035          * layers can't queue any more.
3036          */
3037
3038         software_reset(ohci);
3039         free_irq(dev->irq, ohci);
3040
3041         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3042                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3043                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3044         if (ohci->config_rom)
3045                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3046                                   ohci->config_rom, ohci->config_rom_bus);
3047         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3048                           ohci->self_id_cpu, ohci->self_id_bus);
3049         ar_context_release(&ohci->ar_request_ctx);
3050         ar_context_release(&ohci->ar_response_ctx);
3051         context_release(&ohci->at_request_ctx);
3052         context_release(&ohci->at_response_ctx);
3053         kfree(ohci->it_context_list);
3054         kfree(ohci->ir_context_list);
3055         pci_disable_msi(dev);
3056         pci_iounmap(dev, ohci->registers);
3057         pci_release_region(dev, 0);
3058         pci_disable_device(dev);
3059         kfree(&ohci->card);
3060         pmac_ohci_off(dev);
3061
3062         fw_notify("Removed fw-ohci device.\n");
3063 }
3064
3065 #ifdef CONFIG_PM
3066 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3067 {
3068         struct fw_ohci *ohci = pci_get_drvdata(dev);
3069         int err;
3070
3071         software_reset(ohci);
3072         free_irq(dev->irq, ohci);
3073         pci_disable_msi(dev);
3074         err = pci_save_state(dev);
3075         if (err) {
3076                 fw_error("pci_save_state failed\n");
3077                 return err;
3078         }
3079         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3080         if (err)
3081                 fw_error("pci_set_power_state failed with %d\n", err);
3082         pmac_ohci_off(dev);
3083
3084         return 0;
3085 }
3086
3087 static int pci_resume(struct pci_dev *dev)
3088 {
3089         struct fw_ohci *ohci = pci_get_drvdata(dev);
3090         int err;
3091
3092         pmac_ohci_on(dev);
3093         pci_set_power_state(dev, PCI_D0);
3094         pci_restore_state(dev);
3095         err = pci_enable_device(dev);
3096         if (err) {
3097                 fw_error("pci_enable_device failed\n");
3098                 return err;
3099         }
3100
3101         return ohci_enable(&ohci->card, NULL, 0);
3102 }
3103 #endif
3104
3105 static const struct pci_device_id pci_table[] = {
3106         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3107         { }
3108 };
3109
3110 MODULE_DEVICE_TABLE(pci, pci_table);
3111
3112 static struct pci_driver fw_ohci_pci_driver = {
3113         .name           = ohci_driver_name,
3114         .id_table       = pci_table,
3115         .probe          = pci_probe,
3116         .remove         = pci_remove,
3117 #ifdef CONFIG_PM
3118         .resume         = pci_resume,
3119         .suspend        = pci_suspend,
3120 #endif
3121 };
3122
3123 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3124 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3125 MODULE_LICENSE("GPL");
3126
3127 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3128 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3129 MODULE_ALIAS("ohci1394");
3130 #endif
3131
3132 static int __init fw_ohci_init(void)
3133 {
3134         return pci_register_driver(&fw_ohci_pci_driver);
3135 }
3136
3137 static void __exit fw_ohci_cleanup(void)
3138 {
3139         pci_unregister_driver(&fw_ohci_pci_driver);
3140 }
3141
3142 module_init(fw_ohci_init);
3143 module_exit(fw_ohci_cleanup);