firewire: ohci: work around selfID junk due to wrong gap count
[pandora-kernel.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/page.h>
49 #include <asm/system.h>
50
51 #ifdef CONFIG_PPC_PMAC
52 #include <asm/pmac_feature.h>
53 #endif
54
55 #include "core.h"
56 #include "ohci.h"
57
58 #define DESCRIPTOR_OUTPUT_MORE          0
59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
62 #define DESCRIPTOR_STATUS               (1 << 11)
63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
64 #define DESCRIPTOR_PING                 (1 << 7)
65 #define DESCRIPTOR_YY                   (1 << 6)
66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
70 #define DESCRIPTOR_WAIT                 (3 << 0)
71
72 struct descriptor {
73         __le16 req_count;
74         __le16 control;
75         __le32 data_address;
76         __le32 branch_address;
77         __le16 res_count;
78         __le16 transfer_status;
79 } __attribute__((aligned(16)));
80
81 #define CONTROL_SET(regs)       (regs)
82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
83 #define COMMAND_PTR(regs)       ((regs) + 12)
84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
85
86 #define AR_BUFFER_SIZE  (32*1024)
87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
88 /* we need at least two pages for proper list management */
89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
90
91 #define MAX_ASYNC_PAYLOAD       4096
92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
94
95 struct ar_context {
96         struct fw_ohci *ohci;
97         struct page *pages[AR_BUFFERS];
98         void *buffer;
99         struct descriptor *descriptors;
100         dma_addr_t descriptors_bus;
101         void *pointer;
102         unsigned int last_buffer_index;
103         u32 regs;
104         struct tasklet_struct tasklet;
105 };
106
107 struct context;
108
109 typedef int (*descriptor_callback_t)(struct context *ctx,
110                                      struct descriptor *d,
111                                      struct descriptor *last);
112
113 /*
114  * A buffer that contains a block of DMA-able coherent memory used for
115  * storing a portion of a DMA descriptor program.
116  */
117 struct descriptor_buffer {
118         struct list_head list;
119         dma_addr_t buffer_bus;
120         size_t buffer_size;
121         size_t used;
122         struct descriptor buffer[0];
123 };
124
125 struct context {
126         struct fw_ohci *ohci;
127         u32 regs;
128         int total_allocation;
129         bool running;
130         bool flushing;
131
132         /*
133          * List of page-sized buffers for storing DMA descriptors.
134          * Head of list contains buffers in use and tail of list contains
135          * free buffers.
136          */
137         struct list_head buffer_list;
138
139         /*
140          * Pointer to a buffer inside buffer_list that contains the tail
141          * end of the current DMA program.
142          */
143         struct descriptor_buffer *buffer_tail;
144
145         /*
146          * The descriptor containing the branch address of the first
147          * descriptor that has not yet been filled by the device.
148          */
149         struct descriptor *last;
150
151         /*
152          * The last descriptor in the DMA program.  It contains the branch
153          * address that must be updated upon appending a new descriptor.
154          */
155         struct descriptor *prev;
156
157         descriptor_callback_t callback;
158
159         struct tasklet_struct tasklet;
160 };
161
162 #define IT_HEADER_SY(v)          ((v) <<  0)
163 #define IT_HEADER_TCODE(v)       ((v) <<  4)
164 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
165 #define IT_HEADER_TAG(v)         ((v) << 14)
166 #define IT_HEADER_SPEED(v)       ((v) << 16)
167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
168
169 struct iso_context {
170         struct fw_iso_context base;
171         struct context context;
172         int excess_bytes;
173         void *header;
174         size_t header_length;
175
176         u8 sync;
177         u8 tags;
178 };
179
180 #define CONFIG_ROM_SIZE 1024
181
182 struct fw_ohci {
183         struct fw_card card;
184
185         __iomem char *registers;
186         int node_id;
187         int generation;
188         int request_generation; /* for timestamping incoming requests */
189         unsigned quirks;
190         unsigned int pri_req_max;
191         u32 bus_time;
192         bool is_root;
193         bool csr_state_setclear_abdicate;
194         int n_ir;
195         int n_it;
196         /*
197          * Spinlock for accessing fw_ohci data.  Never call out of
198          * this driver with this lock held.
199          */
200         spinlock_t lock;
201
202         struct mutex phy_reg_mutex;
203
204         void *misc_buffer;
205         dma_addr_t misc_buffer_bus;
206
207         struct ar_context ar_request_ctx;
208         struct ar_context ar_response_ctx;
209         struct context at_request_ctx;
210         struct context at_response_ctx;
211
212         u32 it_context_support;
213         u32 it_context_mask;     /* unoccupied IT contexts */
214         struct iso_context *it_context_list;
215         u64 ir_context_channels; /* unoccupied channels */
216         u32 ir_context_support;
217         u32 ir_context_mask;     /* unoccupied IR contexts */
218         struct iso_context *ir_context_list;
219         u64 mc_channels; /* channels in use by the multichannel IR context */
220         bool mc_allocated;
221
222         __be32    *config_rom;
223         dma_addr_t config_rom_bus;
224         __be32    *next_config_rom;
225         dma_addr_t next_config_rom_bus;
226         __be32     next_header;
227
228         __le32    *self_id_cpu;
229         dma_addr_t self_id_bus;
230         struct work_struct bus_reset_work;
231
232         u32 self_id_buffer[512];
233 };
234
235 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
236 {
237         return container_of(card, struct fw_ohci, card);
238 }
239
240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
241 #define IR_CONTEXT_BUFFER_FILL          0x80000000
242 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
244 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
245 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
246
247 #define CONTEXT_RUN     0x8000
248 #define CONTEXT_WAKE    0x1000
249 #define CONTEXT_DEAD    0x0800
250 #define CONTEXT_ACTIVE  0x0400
251
252 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
253 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
254 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
255
256 #define OHCI1394_REGISTER_SIZE          0x800
257 #define OHCI1394_PCI_HCI_Control        0x40
258 #define SELF_ID_BUF_SIZE                0x800
259 #define OHCI_TCODE_PHY_PACKET           0x0e
260 #define OHCI_VERSION_1_1                0x010010
261
262 static char ohci_driver_name[] = KBUILD_MODNAME;
263
264 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
266 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
267 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
268 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
269 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
270
271 #define QUIRK_CYCLE_TIMER               1
272 #define QUIRK_RESET_PACKET              2
273 #define QUIRK_BE_HEADERS                4
274 #define QUIRK_NO_1394A                  8
275 #define QUIRK_NO_MSI                    16
276 #define QUIRK_TI_SLLZ059                32
277
278 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
279 static const struct {
280         unsigned short vendor, device, revision, flags;
281 } ohci_quirks[] = {
282         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
283                 QUIRK_CYCLE_TIMER},
284
285         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
286                 QUIRK_BE_HEADERS},
287
288         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
289                 QUIRK_NO_MSI},
290
291         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
292                 QUIRK_NO_MSI},
293
294         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
295                 QUIRK_CYCLE_TIMER},
296
297         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
298                 QUIRK_NO_MSI},
299
300         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
301                 QUIRK_CYCLE_TIMER},
302
303         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
304                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
305
306         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
307                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
308
309         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
310                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
311
312         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
313                 QUIRK_RESET_PACKET},
314
315         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
316                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
317 };
318
319 /* This overrides anything that was found in ohci_quirks[]. */
320 static int param_quirks;
321 module_param_named(quirks, param_quirks, int, 0644);
322 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
323         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
324         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
325         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
326         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
327         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
328         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
329         ")");
330
331 #define OHCI_PARAM_DEBUG_AT_AR          1
332 #define OHCI_PARAM_DEBUG_SELFIDS        2
333 #define OHCI_PARAM_DEBUG_IRQS           4
334 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
335
336 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
337
338 static int param_debug;
339 module_param_named(debug, param_debug, int, 0644);
340 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
341         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
342         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
343         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
344         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
345         ", or a combination, or all = -1)");
346
347 static void log_irqs(u32 evt)
348 {
349         if (likely(!(param_debug &
350                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
351                 return;
352
353         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
354             !(evt & OHCI1394_busReset))
355                 return;
356
357         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
358             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
359             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
360             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
361             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
362             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
363             evt & OHCI1394_isochRx              ? " IR"                 : "",
364             evt & OHCI1394_isochTx              ? " IT"                 : "",
365             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
366             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
367             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
368             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
369             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
370             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
371             evt & OHCI1394_busReset             ? " busReset"           : "",
372             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
373                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
374                     OHCI1394_respTxComplete | OHCI1394_isochRx |
375                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
376                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
377                     OHCI1394_cycleInconsistent |
378                     OHCI1394_regAccessFail | OHCI1394_busReset)
379                                                 ? " ?"                  : "");
380 }
381
382 static const char *speed[] = {
383         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
384 };
385 static const char *power[] = {
386         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
387         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
388 };
389 static const char port[] = { '.', '-', 'p', 'c', };
390
391 static char _p(u32 *s, int shift)
392 {
393         return port[*s >> shift & 3];
394 }
395
396 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
397 {
398         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
399                 return;
400
401         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
402                   self_id_count, generation, node_id);
403
404         for (; self_id_count--; ++s)
405                 if ((*s & 1 << 23) == 0)
406                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
407                             "%s gc=%d %s %s%s%s\n",
408                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
409                             speed[*s >> 14 & 3], *s >> 16 & 63,
410                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
411                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
412                 else
413                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
414                             *s, *s >> 24 & 63,
415                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
416                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
417 }
418
419 static const char *evts[] = {
420         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
421         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
422         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
423         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
424         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
425         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
426         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
427         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
428         [0x10] = "-reserved-",          [0x11] = "ack_complete",
429         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
430         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
431         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
432         [0x18] = "-reserved-",          [0x19] = "-reserved-",
433         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
434         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
435         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
436         [0x20] = "pending/cancelled",
437 };
438 static const char *tcodes[] = {
439         [0x0] = "QW req",               [0x1] = "BW req",
440         [0x2] = "W resp",               [0x3] = "-reserved-",
441         [0x4] = "QR req",               [0x5] = "BR req",
442         [0x6] = "QR resp",              [0x7] = "BR resp",
443         [0x8] = "cycle start",          [0x9] = "Lk req",
444         [0xa] = "async stream packet",  [0xb] = "Lk resp",
445         [0xc] = "-reserved-",           [0xd] = "-reserved-",
446         [0xe] = "link internal",        [0xf] = "-reserved-",
447 };
448
449 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
450 {
451         int tcode = header[0] >> 4 & 0xf;
452         char specific[12];
453
454         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
455                 return;
456
457         if (unlikely(evt >= ARRAY_SIZE(evts)))
458                         evt = 0x1f;
459
460         if (evt == OHCI1394_evt_bus_reset) {
461                 fw_notify("A%c evt_bus_reset, generation %d\n",
462                     dir, (header[2] >> 16) & 0xff);
463                 return;
464         }
465
466         switch (tcode) {
467         case 0x0: case 0x6: case 0x8:
468                 snprintf(specific, sizeof(specific), " = %08x",
469                          be32_to_cpu((__force __be32)header[3]));
470                 break;
471         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
472                 snprintf(specific, sizeof(specific), " %x,%x",
473                          header[3] >> 16, header[3] & 0xffff);
474                 break;
475         default:
476                 specific[0] = '\0';
477         }
478
479         switch (tcode) {
480         case 0xa:
481                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
482                 break;
483         case 0xe:
484                 fw_notify("A%c %s, PHY %08x %08x\n",
485                           dir, evts[evt], header[1], header[2]);
486                 break;
487         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
488                 fw_notify("A%c spd %x tl %02x, "
489                     "%04x -> %04x, %s, "
490                     "%s, %04x%08x%s\n",
491                     dir, speed, header[0] >> 10 & 0x3f,
492                     header[1] >> 16, header[0] >> 16, evts[evt],
493                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
494                 break;
495         default:
496                 fw_notify("A%c spd %x tl %02x, "
497                     "%04x -> %04x, %s, "
498                     "%s%s\n",
499                     dir, speed, header[0] >> 10 & 0x3f,
500                     header[1] >> 16, header[0] >> 16, evts[evt],
501                     tcodes[tcode], specific);
502         }
503 }
504
505 #else
506
507 #define param_debug 0
508 static inline void log_irqs(u32 evt) {}
509 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
510 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
511
512 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
513
514 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
515 {
516         writel(data, ohci->registers + offset);
517 }
518
519 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
520 {
521         return readl(ohci->registers + offset);
522 }
523
524 static inline void flush_writes(const struct fw_ohci *ohci)
525 {
526         /* Do a dummy read to flush writes. */
527         reg_read(ohci, OHCI1394_Version);
528 }
529
530 /*
531  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
532  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
533  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
534  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
535  */
536 static int read_phy_reg(struct fw_ohci *ohci, int addr)
537 {
538         u32 val;
539         int i;
540
541         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
542         for (i = 0; i < 3 + 100; i++) {
543                 val = reg_read(ohci, OHCI1394_PhyControl);
544                 if (!~val)
545                         return -ENODEV; /* Card was ejected. */
546
547                 if (val & OHCI1394_PhyControl_ReadDone)
548                         return OHCI1394_PhyControl_ReadData(val);
549
550                 /*
551                  * Try a few times without waiting.  Sleeping is necessary
552                  * only when the link/PHY interface is busy.
553                  */
554                 if (i >= 3)
555                         msleep(1);
556         }
557         fw_error("failed to read phy reg\n");
558
559         return -EBUSY;
560 }
561
562 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
563 {
564         int i;
565
566         reg_write(ohci, OHCI1394_PhyControl,
567                   OHCI1394_PhyControl_Write(addr, val));
568         for (i = 0; i < 3 + 100; i++) {
569                 val = reg_read(ohci, OHCI1394_PhyControl);
570                 if (!~val)
571                         return -ENODEV; /* Card was ejected. */
572
573                 if (!(val & OHCI1394_PhyControl_WritePending))
574                         return 0;
575
576                 if (i >= 3)
577                         msleep(1);
578         }
579         fw_error("failed to write phy reg\n");
580
581         return -EBUSY;
582 }
583
584 static int update_phy_reg(struct fw_ohci *ohci, int addr,
585                           int clear_bits, int set_bits)
586 {
587         int ret = read_phy_reg(ohci, addr);
588         if (ret < 0)
589                 return ret;
590
591         /*
592          * The interrupt status bits are cleared by writing a one bit.
593          * Avoid clearing them unless explicitly requested in set_bits.
594          */
595         if (addr == 5)
596                 clear_bits |= PHY_INT_STATUS_BITS;
597
598         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
599 }
600
601 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
602 {
603         int ret;
604
605         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
606         if (ret < 0)
607                 return ret;
608
609         return read_phy_reg(ohci, addr);
610 }
611
612 static int ohci_read_phy_reg(struct fw_card *card, int addr)
613 {
614         struct fw_ohci *ohci = fw_ohci(card);
615         int ret;
616
617         mutex_lock(&ohci->phy_reg_mutex);
618         ret = read_phy_reg(ohci, addr);
619         mutex_unlock(&ohci->phy_reg_mutex);
620
621         return ret;
622 }
623
624 static int ohci_update_phy_reg(struct fw_card *card, int addr,
625                                int clear_bits, int set_bits)
626 {
627         struct fw_ohci *ohci = fw_ohci(card);
628         int ret;
629
630         mutex_lock(&ohci->phy_reg_mutex);
631         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
632         mutex_unlock(&ohci->phy_reg_mutex);
633
634         return ret;
635 }
636
637 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
638 {
639         return page_private(ctx->pages[i]);
640 }
641
642 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
643 {
644         struct descriptor *d;
645
646         d = &ctx->descriptors[index];
647         d->branch_address  &= cpu_to_le32(~0xf);
648         d->res_count       =  cpu_to_le16(PAGE_SIZE);
649         d->transfer_status =  0;
650
651         wmb(); /* finish init of new descriptors before branch_address update */
652         d = &ctx->descriptors[ctx->last_buffer_index];
653         d->branch_address  |= cpu_to_le32(1);
654
655         ctx->last_buffer_index = index;
656
657         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
658 }
659
660 static void ar_context_release(struct ar_context *ctx)
661 {
662         unsigned int i;
663
664         if (ctx->buffer)
665                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
666
667         for (i = 0; i < AR_BUFFERS; i++)
668                 if (ctx->pages[i]) {
669                         dma_unmap_page(ctx->ohci->card.device,
670                                        ar_buffer_bus(ctx, i),
671                                        PAGE_SIZE, DMA_FROM_DEVICE);
672                         __free_page(ctx->pages[i]);
673                 }
674 }
675
676 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
677 {
678         if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
679                 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
680                 flush_writes(ctx->ohci);
681
682                 fw_error("AR error: %s; DMA stopped\n", error_msg);
683         }
684         /* FIXME: restart? */
685 }
686
687 static inline unsigned int ar_next_buffer_index(unsigned int index)
688 {
689         return (index + 1) % AR_BUFFERS;
690 }
691
692 static inline unsigned int ar_prev_buffer_index(unsigned int index)
693 {
694         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
695 }
696
697 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
698 {
699         return ar_next_buffer_index(ctx->last_buffer_index);
700 }
701
702 /*
703  * We search for the buffer that contains the last AR packet DMA data written
704  * by the controller.
705  */
706 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
707                                                  unsigned int *buffer_offset)
708 {
709         unsigned int i, next_i, last = ctx->last_buffer_index;
710         __le16 res_count, next_res_count;
711
712         i = ar_first_buffer_index(ctx);
713         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
714
715         /* A buffer that is not yet completely filled must be the last one. */
716         while (i != last && res_count == 0) {
717
718                 /* Peek at the next descriptor. */
719                 next_i = ar_next_buffer_index(i);
720                 rmb(); /* read descriptors in order */
721                 next_res_count = ACCESS_ONCE(
722                                 ctx->descriptors[next_i].res_count);
723                 /*
724                  * If the next descriptor is still empty, we must stop at this
725                  * descriptor.
726                  */
727                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
728                         /*
729                          * The exception is when the DMA data for one packet is
730                          * split over three buffers; in this case, the middle
731                          * buffer's descriptor might be never updated by the
732                          * controller and look still empty, and we have to peek
733                          * at the third one.
734                          */
735                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
736                                 next_i = ar_next_buffer_index(next_i);
737                                 rmb();
738                                 next_res_count = ACCESS_ONCE(
739                                         ctx->descriptors[next_i].res_count);
740                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
741                                         goto next_buffer_is_active;
742                         }
743
744                         break;
745                 }
746
747 next_buffer_is_active:
748                 i = next_i;
749                 res_count = next_res_count;
750         }
751
752         rmb(); /* read res_count before the DMA data */
753
754         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
755         if (*buffer_offset > PAGE_SIZE) {
756                 *buffer_offset = 0;
757                 ar_context_abort(ctx, "corrupted descriptor");
758         }
759
760         return i;
761 }
762
763 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
764                                     unsigned int end_buffer_index,
765                                     unsigned int end_buffer_offset)
766 {
767         unsigned int i;
768
769         i = ar_first_buffer_index(ctx);
770         while (i != end_buffer_index) {
771                 dma_sync_single_for_cpu(ctx->ohci->card.device,
772                                         ar_buffer_bus(ctx, i),
773                                         PAGE_SIZE, DMA_FROM_DEVICE);
774                 i = ar_next_buffer_index(i);
775         }
776         if (end_buffer_offset > 0)
777                 dma_sync_single_for_cpu(ctx->ohci->card.device,
778                                         ar_buffer_bus(ctx, i),
779                                         end_buffer_offset, DMA_FROM_DEVICE);
780 }
781
782 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
783 #define cond_le32_to_cpu(v) \
784         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
785 #else
786 #define cond_le32_to_cpu(v) le32_to_cpu(v)
787 #endif
788
789 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
790 {
791         struct fw_ohci *ohci = ctx->ohci;
792         struct fw_packet p;
793         u32 status, length, tcode;
794         int evt;
795
796         p.header[0] = cond_le32_to_cpu(buffer[0]);
797         p.header[1] = cond_le32_to_cpu(buffer[1]);
798         p.header[2] = cond_le32_to_cpu(buffer[2]);
799
800         tcode = (p.header[0] >> 4) & 0x0f;
801         switch (tcode) {
802         case TCODE_WRITE_QUADLET_REQUEST:
803         case TCODE_READ_QUADLET_RESPONSE:
804                 p.header[3] = (__force __u32) buffer[3];
805                 p.header_length = 16;
806                 p.payload_length = 0;
807                 break;
808
809         case TCODE_READ_BLOCK_REQUEST :
810                 p.header[3] = cond_le32_to_cpu(buffer[3]);
811                 p.header_length = 16;
812                 p.payload_length = 0;
813                 break;
814
815         case TCODE_WRITE_BLOCK_REQUEST:
816         case TCODE_READ_BLOCK_RESPONSE:
817         case TCODE_LOCK_REQUEST:
818         case TCODE_LOCK_RESPONSE:
819                 p.header[3] = cond_le32_to_cpu(buffer[3]);
820                 p.header_length = 16;
821                 p.payload_length = p.header[3] >> 16;
822                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
823                         ar_context_abort(ctx, "invalid packet length");
824                         return NULL;
825                 }
826                 break;
827
828         case TCODE_WRITE_RESPONSE:
829         case TCODE_READ_QUADLET_REQUEST:
830         case OHCI_TCODE_PHY_PACKET:
831                 p.header_length = 12;
832                 p.payload_length = 0;
833                 break;
834
835         default:
836                 ar_context_abort(ctx, "invalid tcode");
837                 return NULL;
838         }
839
840         p.payload = (void *) buffer + p.header_length;
841
842         /* FIXME: What to do about evt_* errors? */
843         length = (p.header_length + p.payload_length + 3) / 4;
844         status = cond_le32_to_cpu(buffer[length]);
845         evt    = (status >> 16) & 0x1f;
846
847         p.ack        = evt - 16;
848         p.speed      = (status >> 21) & 0x7;
849         p.timestamp  = status & 0xffff;
850         p.generation = ohci->request_generation;
851
852         log_ar_at_event('R', p.speed, p.header, evt);
853
854         /*
855          * Several controllers, notably from NEC and VIA, forget to
856          * write ack_complete status at PHY packet reception.
857          */
858         if (evt == OHCI1394_evt_no_status &&
859             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
860                 p.ack = ACK_COMPLETE;
861
862         /*
863          * The OHCI bus reset handler synthesizes a PHY packet with
864          * the new generation number when a bus reset happens (see
865          * section 8.4.2.3).  This helps us determine when a request
866          * was received and make sure we send the response in the same
867          * generation.  We only need this for requests; for responses
868          * we use the unique tlabel for finding the matching
869          * request.
870          *
871          * Alas some chips sometimes emit bus reset packets with a
872          * wrong generation.  We set the correct generation for these
873          * at a slightly incorrect time (in bus_reset_work).
874          */
875         if (evt == OHCI1394_evt_bus_reset) {
876                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
877                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
878         } else if (ctx == &ohci->ar_request_ctx) {
879                 fw_core_handle_request(&ohci->card, &p);
880         } else {
881                 fw_core_handle_response(&ohci->card, &p);
882         }
883
884         return buffer + length + 1;
885 }
886
887 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
888 {
889         void *next;
890
891         while (p < end) {
892                 next = handle_ar_packet(ctx, p);
893                 if (!next)
894                         return p;
895                 p = next;
896         }
897
898         return p;
899 }
900
901 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
902 {
903         unsigned int i;
904
905         i = ar_first_buffer_index(ctx);
906         while (i != end_buffer) {
907                 dma_sync_single_for_device(ctx->ohci->card.device,
908                                            ar_buffer_bus(ctx, i),
909                                            PAGE_SIZE, DMA_FROM_DEVICE);
910                 ar_context_link_page(ctx, i);
911                 i = ar_next_buffer_index(i);
912         }
913 }
914
915 static void ar_context_tasklet(unsigned long data)
916 {
917         struct ar_context *ctx = (struct ar_context *)data;
918         unsigned int end_buffer_index, end_buffer_offset;
919         void *p, *end;
920
921         p = ctx->pointer;
922         if (!p)
923                 return;
924
925         end_buffer_index = ar_search_last_active_buffer(ctx,
926                                                         &end_buffer_offset);
927         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
928         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
929
930         if (end_buffer_index < ar_first_buffer_index(ctx)) {
931                 /*
932                  * The filled part of the overall buffer wraps around; handle
933                  * all packets up to the buffer end here.  If the last packet
934                  * wraps around, its tail will be visible after the buffer end
935                  * because the buffer start pages are mapped there again.
936                  */
937                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
938                 p = handle_ar_packets(ctx, p, buffer_end);
939                 if (p < buffer_end)
940                         goto error;
941                 /* adjust p to point back into the actual buffer */
942                 p -= AR_BUFFERS * PAGE_SIZE;
943         }
944
945         p = handle_ar_packets(ctx, p, end);
946         if (p != end) {
947                 if (p > end)
948                         ar_context_abort(ctx, "inconsistent descriptor");
949                 goto error;
950         }
951
952         ctx->pointer = p;
953         ar_recycle_buffers(ctx, end_buffer_index);
954
955         return;
956
957 error:
958         ctx->pointer = NULL;
959 }
960
961 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
962                            unsigned int descriptors_offset, u32 regs)
963 {
964         unsigned int i;
965         dma_addr_t dma_addr;
966         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
967         struct descriptor *d;
968
969         ctx->regs        = regs;
970         ctx->ohci        = ohci;
971         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
972
973         for (i = 0; i < AR_BUFFERS; i++) {
974                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
975                 if (!ctx->pages[i])
976                         goto out_of_memory;
977                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
978                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
979                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
980                         __free_page(ctx->pages[i]);
981                         ctx->pages[i] = NULL;
982                         goto out_of_memory;
983                 }
984                 set_page_private(ctx->pages[i], dma_addr);
985         }
986
987         for (i = 0; i < AR_BUFFERS; i++)
988                 pages[i]              = ctx->pages[i];
989         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
990                 pages[AR_BUFFERS + i] = ctx->pages[i];
991         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
992                                  -1, PAGE_KERNEL);
993         if (!ctx->buffer)
994                 goto out_of_memory;
995
996         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
997         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
998
999         for (i = 0; i < AR_BUFFERS; i++) {
1000                 d = &ctx->descriptors[i];
1001                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1002                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1003                                                 DESCRIPTOR_STATUS |
1004                                                 DESCRIPTOR_BRANCH_ALWAYS);
1005                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1006                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1007                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1008         }
1009
1010         return 0;
1011
1012 out_of_memory:
1013         ar_context_release(ctx);
1014
1015         return -ENOMEM;
1016 }
1017
1018 static void ar_context_run(struct ar_context *ctx)
1019 {
1020         unsigned int i;
1021
1022         for (i = 0; i < AR_BUFFERS; i++)
1023                 ar_context_link_page(ctx, i);
1024
1025         ctx->pointer = ctx->buffer;
1026
1027         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1028         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1029 }
1030
1031 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1032 {
1033         __le16 branch;
1034
1035         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1036
1037         /* figure out which descriptor the branch address goes in */
1038         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1039                 return d;
1040         else
1041                 return d + z - 1;
1042 }
1043
1044 static void context_tasklet(unsigned long data)
1045 {
1046         struct context *ctx = (struct context *) data;
1047         struct descriptor *d, *last;
1048         u32 address;
1049         int z;
1050         struct descriptor_buffer *desc;
1051
1052         desc = list_entry(ctx->buffer_list.next,
1053                         struct descriptor_buffer, list);
1054         last = ctx->last;
1055         while (last->branch_address != 0) {
1056                 struct descriptor_buffer *old_desc = desc;
1057                 address = le32_to_cpu(last->branch_address);
1058                 z = address & 0xf;
1059                 address &= ~0xf;
1060
1061                 /* If the branch address points to a buffer outside of the
1062                  * current buffer, advance to the next buffer. */
1063                 if (address < desc->buffer_bus ||
1064                                 address >= desc->buffer_bus + desc->used)
1065                         desc = list_entry(desc->list.next,
1066                                         struct descriptor_buffer, list);
1067                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1068                 last = find_branch_descriptor(d, z);
1069
1070                 if (!ctx->callback(ctx, d, last))
1071                         break;
1072
1073                 if (old_desc != desc) {
1074                         /* If we've advanced to the next buffer, move the
1075                          * previous buffer to the free list. */
1076                         unsigned long flags;
1077                         old_desc->used = 0;
1078                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1079                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1080                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1081                 }
1082                 ctx->last = last;
1083         }
1084 }
1085
1086 /*
1087  * Allocate a new buffer and add it to the list of free buffers for this
1088  * context.  Must be called with ohci->lock held.
1089  */
1090 static int context_add_buffer(struct context *ctx)
1091 {
1092         struct descriptor_buffer *desc;
1093         dma_addr_t uninitialized_var(bus_addr);
1094         int offset;
1095
1096         /*
1097          * 16MB of descriptors should be far more than enough for any DMA
1098          * program.  This will catch run-away userspace or DoS attacks.
1099          */
1100         if (ctx->total_allocation >= 16*1024*1024)
1101                 return -ENOMEM;
1102
1103         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1104                         &bus_addr, GFP_ATOMIC);
1105         if (!desc)
1106                 return -ENOMEM;
1107
1108         offset = (void *)&desc->buffer - (void *)desc;
1109         desc->buffer_size = PAGE_SIZE - offset;
1110         desc->buffer_bus = bus_addr + offset;
1111         desc->used = 0;
1112
1113         list_add_tail(&desc->list, &ctx->buffer_list);
1114         ctx->total_allocation += PAGE_SIZE;
1115
1116         return 0;
1117 }
1118
1119 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1120                         u32 regs, descriptor_callback_t callback)
1121 {
1122         ctx->ohci = ohci;
1123         ctx->regs = regs;
1124         ctx->total_allocation = 0;
1125
1126         INIT_LIST_HEAD(&ctx->buffer_list);
1127         if (context_add_buffer(ctx) < 0)
1128                 return -ENOMEM;
1129
1130         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1131                         struct descriptor_buffer, list);
1132
1133         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1134         ctx->callback = callback;
1135
1136         /*
1137          * We put a dummy descriptor in the buffer that has a NULL
1138          * branch address and looks like it's been sent.  That way we
1139          * have a descriptor to append DMA programs to.
1140          */
1141         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1142         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1143         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1144         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1145         ctx->last = ctx->buffer_tail->buffer;
1146         ctx->prev = ctx->buffer_tail->buffer;
1147
1148         return 0;
1149 }
1150
1151 static void context_release(struct context *ctx)
1152 {
1153         struct fw_card *card = &ctx->ohci->card;
1154         struct descriptor_buffer *desc, *tmp;
1155
1156         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1157                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1158                         desc->buffer_bus -
1159                         ((void *)&desc->buffer - (void *)desc));
1160 }
1161
1162 /* Must be called with ohci->lock held */
1163 static struct descriptor *context_get_descriptors(struct context *ctx,
1164                                                   int z, dma_addr_t *d_bus)
1165 {
1166         struct descriptor *d = NULL;
1167         struct descriptor_buffer *desc = ctx->buffer_tail;
1168
1169         if (z * sizeof(*d) > desc->buffer_size)
1170                 return NULL;
1171
1172         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1173                 /* No room for the descriptor in this buffer, so advance to the
1174                  * next one. */
1175
1176                 if (desc->list.next == &ctx->buffer_list) {
1177                         /* If there is no free buffer next in the list,
1178                          * allocate one. */
1179                         if (context_add_buffer(ctx) < 0)
1180                                 return NULL;
1181                 }
1182                 desc = list_entry(desc->list.next,
1183                                 struct descriptor_buffer, list);
1184                 ctx->buffer_tail = desc;
1185         }
1186
1187         d = desc->buffer + desc->used / sizeof(*d);
1188         memset(d, 0, z * sizeof(*d));
1189         *d_bus = desc->buffer_bus + desc->used;
1190
1191         return d;
1192 }
1193
1194 static void context_run(struct context *ctx, u32 extra)
1195 {
1196         struct fw_ohci *ohci = ctx->ohci;
1197
1198         reg_write(ohci, COMMAND_PTR(ctx->regs),
1199                   le32_to_cpu(ctx->last->branch_address));
1200         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1201         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1202         ctx->running = true;
1203         flush_writes(ohci);
1204 }
1205
1206 static void context_append(struct context *ctx,
1207                            struct descriptor *d, int z, int extra)
1208 {
1209         dma_addr_t d_bus;
1210         struct descriptor_buffer *desc = ctx->buffer_tail;
1211
1212         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1213
1214         desc->used += (z + extra) * sizeof(*d);
1215
1216         wmb(); /* finish init of new descriptors before branch_address update */
1217         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1218         ctx->prev = find_branch_descriptor(d, z);
1219 }
1220
1221 static void context_stop(struct context *ctx)
1222 {
1223         u32 reg;
1224         int i;
1225
1226         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1227         ctx->running = false;
1228
1229         for (i = 0; i < 1000; i++) {
1230                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1231                 if ((reg & CONTEXT_ACTIVE) == 0)
1232                         return;
1233
1234                 if (i)
1235                         udelay(10);
1236         }
1237         fw_error("Error: DMA context still active (0x%08x)\n", reg);
1238 }
1239
1240 struct driver_data {
1241         u8 inline_data[8];
1242         struct fw_packet *packet;
1243 };
1244
1245 /*
1246  * This function apppends a packet to the DMA queue for transmission.
1247  * Must always be called with the ochi->lock held to ensure proper
1248  * generation handling and locking around packet queue manipulation.
1249  */
1250 static int at_context_queue_packet(struct context *ctx,
1251                                    struct fw_packet *packet)
1252 {
1253         struct fw_ohci *ohci = ctx->ohci;
1254         dma_addr_t d_bus, uninitialized_var(payload_bus);
1255         struct driver_data *driver_data;
1256         struct descriptor *d, *last;
1257         __le32 *header;
1258         int z, tcode;
1259
1260         d = context_get_descriptors(ctx, 4, &d_bus);
1261         if (d == NULL) {
1262                 packet->ack = RCODE_SEND_ERROR;
1263                 return -1;
1264         }
1265
1266         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1267         d[0].res_count = cpu_to_le16(packet->timestamp);
1268
1269         /*
1270          * The DMA format for asyncronous link packets is different
1271          * from the IEEE1394 layout, so shift the fields around
1272          * accordingly.
1273          */
1274
1275         tcode = (packet->header[0] >> 4) & 0x0f;
1276         header = (__le32 *) &d[1];
1277         switch (tcode) {
1278         case TCODE_WRITE_QUADLET_REQUEST:
1279         case TCODE_WRITE_BLOCK_REQUEST:
1280         case TCODE_WRITE_RESPONSE:
1281         case TCODE_READ_QUADLET_REQUEST:
1282         case TCODE_READ_BLOCK_REQUEST:
1283         case TCODE_READ_QUADLET_RESPONSE:
1284         case TCODE_READ_BLOCK_RESPONSE:
1285         case TCODE_LOCK_REQUEST:
1286         case TCODE_LOCK_RESPONSE:
1287                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1288                                         (packet->speed << 16));
1289                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1290                                         (packet->header[0] & 0xffff0000));
1291                 header[2] = cpu_to_le32(packet->header[2]);
1292
1293                 if (TCODE_IS_BLOCK_PACKET(tcode))
1294                         header[3] = cpu_to_le32(packet->header[3]);
1295                 else
1296                         header[3] = (__force __le32) packet->header[3];
1297
1298                 d[0].req_count = cpu_to_le16(packet->header_length);
1299                 break;
1300
1301         case TCODE_LINK_INTERNAL:
1302                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1303                                         (packet->speed << 16));
1304                 header[1] = cpu_to_le32(packet->header[1]);
1305                 header[2] = cpu_to_le32(packet->header[2]);
1306                 d[0].req_count = cpu_to_le16(12);
1307
1308                 if (is_ping_packet(&packet->header[1]))
1309                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1310                 break;
1311
1312         case TCODE_STREAM_DATA:
1313                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1314                                         (packet->speed << 16));
1315                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1316                 d[0].req_count = cpu_to_le16(8);
1317                 break;
1318
1319         default:
1320                 /* BUG(); */
1321                 packet->ack = RCODE_SEND_ERROR;
1322                 return -1;
1323         }
1324
1325         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1326         driver_data = (struct driver_data *) &d[3];
1327         driver_data->packet = packet;
1328         packet->driver_data = driver_data;
1329
1330         if (packet->payload_length > 0) {
1331                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1332                         payload_bus = dma_map_single(ohci->card.device,
1333                                                      packet->payload,
1334                                                      packet->payload_length,
1335                                                      DMA_TO_DEVICE);
1336                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1337                                 packet->ack = RCODE_SEND_ERROR;
1338                                 return -1;
1339                         }
1340                         packet->payload_bus     = payload_bus;
1341                         packet->payload_mapped  = true;
1342                 } else {
1343                         memcpy(driver_data->inline_data, packet->payload,
1344                                packet->payload_length);
1345                         payload_bus = d_bus + 3 * sizeof(*d);
1346                 }
1347
1348                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1349                 d[2].data_address = cpu_to_le32(payload_bus);
1350                 last = &d[2];
1351                 z = 3;
1352         } else {
1353                 last = &d[0];
1354                 z = 2;
1355         }
1356
1357         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1358                                      DESCRIPTOR_IRQ_ALWAYS |
1359                                      DESCRIPTOR_BRANCH_ALWAYS);
1360
1361         /* FIXME: Document how the locking works. */
1362         if (ohci->generation != packet->generation) {
1363                 if (packet->payload_mapped)
1364                         dma_unmap_single(ohci->card.device, payload_bus,
1365                                          packet->payload_length, DMA_TO_DEVICE);
1366                 packet->ack = RCODE_GENERATION;
1367                 return -1;
1368         }
1369
1370         context_append(ctx, d, z, 4 - z);
1371
1372         if (ctx->running)
1373                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1374         else
1375                 context_run(ctx, 0);
1376
1377         return 0;
1378 }
1379
1380 static void at_context_flush(struct context *ctx)
1381 {
1382         tasklet_disable(&ctx->tasklet);
1383
1384         ctx->flushing = true;
1385         context_tasklet((unsigned long)ctx);
1386         ctx->flushing = false;
1387
1388         tasklet_enable(&ctx->tasklet);
1389 }
1390
1391 static int handle_at_packet(struct context *context,
1392                             struct descriptor *d,
1393                             struct descriptor *last)
1394 {
1395         struct driver_data *driver_data;
1396         struct fw_packet *packet;
1397         struct fw_ohci *ohci = context->ohci;
1398         int evt;
1399
1400         if (last->transfer_status == 0 && !context->flushing)
1401                 /* This descriptor isn't done yet, stop iteration. */
1402                 return 0;
1403
1404         driver_data = (struct driver_data *) &d[3];
1405         packet = driver_data->packet;
1406         if (packet == NULL)
1407                 /* This packet was cancelled, just continue. */
1408                 return 1;
1409
1410         if (packet->payload_mapped)
1411                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1412                                  packet->payload_length, DMA_TO_DEVICE);
1413
1414         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1415         packet->timestamp = le16_to_cpu(last->res_count);
1416
1417         log_ar_at_event('T', packet->speed, packet->header, evt);
1418
1419         switch (evt) {
1420         case OHCI1394_evt_timeout:
1421                 /* Async response transmit timed out. */
1422                 packet->ack = RCODE_CANCELLED;
1423                 break;
1424
1425         case OHCI1394_evt_flushed:
1426                 /*
1427                  * The packet was flushed should give same error as
1428                  * when we try to use a stale generation count.
1429                  */
1430                 packet->ack = RCODE_GENERATION;
1431                 break;
1432
1433         case OHCI1394_evt_missing_ack:
1434                 if (context->flushing)
1435                         packet->ack = RCODE_GENERATION;
1436                 else {
1437                         /*
1438                          * Using a valid (current) generation count, but the
1439                          * node is not on the bus or not sending acks.
1440                          */
1441                         packet->ack = RCODE_NO_ACK;
1442                 }
1443                 break;
1444
1445         case ACK_COMPLETE + 0x10:
1446         case ACK_PENDING + 0x10:
1447         case ACK_BUSY_X + 0x10:
1448         case ACK_BUSY_A + 0x10:
1449         case ACK_BUSY_B + 0x10:
1450         case ACK_DATA_ERROR + 0x10:
1451         case ACK_TYPE_ERROR + 0x10:
1452                 packet->ack = evt - 0x10;
1453                 break;
1454
1455         case OHCI1394_evt_no_status:
1456                 if (context->flushing) {
1457                         packet->ack = RCODE_GENERATION;
1458                         break;
1459                 }
1460                 /* fall through */
1461
1462         default:
1463                 packet->ack = RCODE_SEND_ERROR;
1464                 break;
1465         }
1466
1467         packet->callback(packet, &ohci->card, packet->ack);
1468
1469         return 1;
1470 }
1471
1472 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1473 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1474 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1475 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1476 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1477
1478 static void handle_local_rom(struct fw_ohci *ohci,
1479                              struct fw_packet *packet, u32 csr)
1480 {
1481         struct fw_packet response;
1482         int tcode, length, i;
1483
1484         tcode = HEADER_GET_TCODE(packet->header[0]);
1485         if (TCODE_IS_BLOCK_PACKET(tcode))
1486                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1487         else
1488                 length = 4;
1489
1490         i = csr - CSR_CONFIG_ROM;
1491         if (i + length > CONFIG_ROM_SIZE) {
1492                 fw_fill_response(&response, packet->header,
1493                                  RCODE_ADDRESS_ERROR, NULL, 0);
1494         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1495                 fw_fill_response(&response, packet->header,
1496                                  RCODE_TYPE_ERROR, NULL, 0);
1497         } else {
1498                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1499                                  (void *) ohci->config_rom + i, length);
1500         }
1501
1502         fw_core_handle_response(&ohci->card, &response);
1503 }
1504
1505 static void handle_local_lock(struct fw_ohci *ohci,
1506                               struct fw_packet *packet, u32 csr)
1507 {
1508         struct fw_packet response;
1509         int tcode, length, ext_tcode, sel, try;
1510         __be32 *payload, lock_old;
1511         u32 lock_arg, lock_data;
1512
1513         tcode = HEADER_GET_TCODE(packet->header[0]);
1514         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1515         payload = packet->payload;
1516         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1517
1518         if (tcode == TCODE_LOCK_REQUEST &&
1519             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1520                 lock_arg = be32_to_cpu(payload[0]);
1521                 lock_data = be32_to_cpu(payload[1]);
1522         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1523                 lock_arg = 0;
1524                 lock_data = 0;
1525         } else {
1526                 fw_fill_response(&response, packet->header,
1527                                  RCODE_TYPE_ERROR, NULL, 0);
1528                 goto out;
1529         }
1530
1531         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1532         reg_write(ohci, OHCI1394_CSRData, lock_data);
1533         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1534         reg_write(ohci, OHCI1394_CSRControl, sel);
1535
1536         for (try = 0; try < 20; try++)
1537                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1538                         lock_old = cpu_to_be32(reg_read(ohci,
1539                                                         OHCI1394_CSRData));
1540                         fw_fill_response(&response, packet->header,
1541                                          RCODE_COMPLETE,
1542                                          &lock_old, sizeof(lock_old));
1543                         goto out;
1544                 }
1545
1546         fw_error("swap not done (CSR lock timeout)\n");
1547         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1548
1549  out:
1550         fw_core_handle_response(&ohci->card, &response);
1551 }
1552
1553 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1554 {
1555         u64 offset, csr;
1556
1557         if (ctx == &ctx->ohci->at_request_ctx) {
1558                 packet->ack = ACK_PENDING;
1559                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1560         }
1561
1562         offset =
1563                 ((unsigned long long)
1564                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1565                 packet->header[2];
1566         csr = offset - CSR_REGISTER_BASE;
1567
1568         /* Handle config rom reads. */
1569         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1570                 handle_local_rom(ctx->ohci, packet, csr);
1571         else switch (csr) {
1572         case CSR_BUS_MANAGER_ID:
1573         case CSR_BANDWIDTH_AVAILABLE:
1574         case CSR_CHANNELS_AVAILABLE_HI:
1575         case CSR_CHANNELS_AVAILABLE_LO:
1576                 handle_local_lock(ctx->ohci, packet, csr);
1577                 break;
1578         default:
1579                 if (ctx == &ctx->ohci->at_request_ctx)
1580                         fw_core_handle_request(&ctx->ohci->card, packet);
1581                 else
1582                         fw_core_handle_response(&ctx->ohci->card, packet);
1583                 break;
1584         }
1585
1586         if (ctx == &ctx->ohci->at_response_ctx) {
1587                 packet->ack = ACK_COMPLETE;
1588                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1589         }
1590 }
1591
1592 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1593 {
1594         unsigned long flags;
1595         int ret;
1596
1597         spin_lock_irqsave(&ctx->ohci->lock, flags);
1598
1599         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1600             ctx->ohci->generation == packet->generation) {
1601                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1602                 handle_local_request(ctx, packet);
1603                 return;
1604         }
1605
1606         ret = at_context_queue_packet(ctx, packet);
1607         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1608
1609         if (ret < 0)
1610                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1611
1612 }
1613
1614 static void detect_dead_context(struct fw_ohci *ohci,
1615                                 const char *name, unsigned int regs)
1616 {
1617         u32 ctl;
1618
1619         ctl = reg_read(ohci, CONTROL_SET(regs));
1620         if (ctl & CONTEXT_DEAD) {
1621 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1622                 fw_error("DMA context %s has stopped, error code: %s\n",
1623                          name, evts[ctl & 0x1f]);
1624 #else
1625                 fw_error("DMA context %s has stopped, error code: %#x\n",
1626                          name, ctl & 0x1f);
1627 #endif
1628         }
1629 }
1630
1631 static void handle_dead_contexts(struct fw_ohci *ohci)
1632 {
1633         unsigned int i;
1634         char name[8];
1635
1636         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1637         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1638         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1639         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1640         for (i = 0; i < 32; ++i) {
1641                 if (!(ohci->it_context_support & (1 << i)))
1642                         continue;
1643                 sprintf(name, "IT%u", i);
1644                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1645         }
1646         for (i = 0; i < 32; ++i) {
1647                 if (!(ohci->ir_context_support & (1 << i)))
1648                         continue;
1649                 sprintf(name, "IR%u", i);
1650                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1651         }
1652         /* TODO: maybe try to flush and restart the dead contexts */
1653 }
1654
1655 static u32 cycle_timer_ticks(u32 cycle_timer)
1656 {
1657         u32 ticks;
1658
1659         ticks = cycle_timer & 0xfff;
1660         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1661         ticks += (3072 * 8000) * (cycle_timer >> 25);
1662
1663         return ticks;
1664 }
1665
1666 /*
1667  * Some controllers exhibit one or more of the following bugs when updating the
1668  * iso cycle timer register:
1669  *  - When the lowest six bits are wrapping around to zero, a read that happens
1670  *    at the same time will return garbage in the lowest ten bits.
1671  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1672  *    not incremented for about 60 ns.
1673  *  - Occasionally, the entire register reads zero.
1674  *
1675  * To catch these, we read the register three times and ensure that the
1676  * difference between each two consecutive reads is approximately the same, i.e.
1677  * less than twice the other.  Furthermore, any negative difference indicates an
1678  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1679  * execute, so we have enough precision to compute the ratio of the differences.)
1680  */
1681 static u32 get_cycle_time(struct fw_ohci *ohci)
1682 {
1683         u32 c0, c1, c2;
1684         u32 t0, t1, t2;
1685         s32 diff01, diff12;
1686         int i;
1687
1688         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1689
1690         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1691                 i = 0;
1692                 c1 = c2;
1693                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1694                 do {
1695                         c0 = c1;
1696                         c1 = c2;
1697                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698                         t0 = cycle_timer_ticks(c0);
1699                         t1 = cycle_timer_ticks(c1);
1700                         t2 = cycle_timer_ticks(c2);
1701                         diff01 = t1 - t0;
1702                         diff12 = t2 - t1;
1703                 } while ((diff01 <= 0 || diff12 <= 0 ||
1704                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1705                          && i++ < 20);
1706         }
1707
1708         return c2;
1709 }
1710
1711 /*
1712  * This function has to be called at least every 64 seconds.  The bus_time
1713  * field stores not only the upper 25 bits of the BUS_TIME register but also
1714  * the most significant bit of the cycle timer in bit 6 so that we can detect
1715  * changes in this bit.
1716  */
1717 static u32 update_bus_time(struct fw_ohci *ohci)
1718 {
1719         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1720
1721         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1722                 ohci->bus_time += 0x40;
1723
1724         return ohci->bus_time | cycle_time_seconds;
1725 }
1726
1727 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1728 {
1729         int reg;
1730
1731         mutex_lock(&ohci->phy_reg_mutex);
1732         reg = write_phy_reg(ohci, 7, port_index);
1733         if (reg >= 0)
1734                 reg = read_phy_reg(ohci, 8);
1735         mutex_unlock(&ohci->phy_reg_mutex);
1736         if (reg < 0)
1737                 return reg;
1738
1739         switch (reg & 0x0f) {
1740         case 0x06:
1741                 return 2;       /* is child node (connected to parent node) */
1742         case 0x0e:
1743                 return 3;       /* is parent node (connected to child node) */
1744         }
1745         return 1;               /* not connected */
1746 }
1747
1748 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1749         int self_id_count)
1750 {
1751         int i;
1752         u32 entry;
1753
1754         for (i = 0; i < self_id_count; i++) {
1755                 entry = ohci->self_id_buffer[i];
1756                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1757                         return -1;
1758                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1759                         return i;
1760         }
1761         return i;
1762 }
1763
1764 /*
1765  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1766  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1767  * Construct the selfID from phy register contents.
1768  * FIXME:  How to determine the selfID.i flag?
1769  */
1770 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1771 {
1772         int reg, i, pos, status;
1773         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1774         u32 self_id = 0x8040c800;
1775
1776         reg = reg_read(ohci, OHCI1394_NodeID);
1777         if (!(reg & OHCI1394_NodeID_idValid)) {
1778                 fw_notify("node ID not valid, new bus reset in progress\n");
1779                 return -EBUSY;
1780         }
1781         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1782
1783         reg = ohci_read_phy_reg(&ohci->card, 4);
1784         if (reg < 0)
1785                 return reg;
1786         self_id |= ((reg & 0x07) << 8); /* power class */
1787
1788         reg = ohci_read_phy_reg(&ohci->card, 1);
1789         if (reg < 0)
1790                 return reg;
1791         self_id |= ((reg & 0x3f) << 16); /* gap count */
1792
1793         for (i = 0; i < 3; i++) {
1794                 status = get_status_for_port(ohci, i);
1795                 if (status < 0)
1796                         return status;
1797                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1798         }
1799
1800         pos = get_self_id_pos(ohci, self_id, self_id_count);
1801         if (pos >= 0) {
1802                 memmove(&(ohci->self_id_buffer[pos+1]),
1803                         &(ohci->self_id_buffer[pos]),
1804                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1805                 ohci->self_id_buffer[pos] = self_id;
1806                 self_id_count++;
1807         }
1808         return self_id_count;
1809 }
1810
1811 static void bus_reset_work(struct work_struct *work)
1812 {
1813         struct fw_ohci *ohci =
1814                 container_of(work, struct fw_ohci, bus_reset_work);
1815         int self_id_count, i, j, reg;
1816         int generation, new_generation;
1817         unsigned long flags;
1818         void *free_rom = NULL;
1819         dma_addr_t free_rom_bus = 0;
1820         bool is_new_root;
1821
1822         reg = reg_read(ohci, OHCI1394_NodeID);
1823         if (!(reg & OHCI1394_NodeID_idValid)) {
1824                 fw_notify("node ID not valid, new bus reset in progress\n");
1825                 return;
1826         }
1827         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1828                 fw_notify("malconfigured bus\n");
1829                 return;
1830         }
1831         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1832                                OHCI1394_NodeID_nodeNumber);
1833
1834         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1835         if (!(ohci->is_root && is_new_root))
1836                 reg_write(ohci, OHCI1394_LinkControlSet,
1837                           OHCI1394_LinkControl_cycleMaster);
1838         ohci->is_root = is_new_root;
1839
1840         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1841         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1842                 fw_notify("inconsistent self IDs\n");
1843                 return;
1844         }
1845         /*
1846          * The count in the SelfIDCount register is the number of
1847          * bytes in the self ID receive buffer.  Since we also receive
1848          * the inverted quadlets and a header quadlet, we shift one
1849          * bit extra to get the actual number of self IDs.
1850          */
1851         self_id_count = (reg >> 3) & 0xff;
1852
1853         if (self_id_count > 252) {
1854                 fw_notify("inconsistent self IDs\n");
1855                 return;
1856         }
1857
1858         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1859         rmb();
1860
1861         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1862                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1863                         /*
1864                          * If the invalid data looks like a cycle start packet,
1865                          * it's likely to be the result of the cycle master
1866                          * having a wrong gap count.  In this case, the self IDs
1867                          * so far are valid and should be processed so that the
1868                          * bus manager can then correct the gap count.
1869                          */
1870                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1871                                                         == 0xffff008f) {
1872                                 fw_notify("ignoring spurious self IDs\n");
1873                                 self_id_count = j;
1874                                 break;
1875                         } else {
1876                                 fw_notify("inconsistent self IDs\n");
1877                                 return;
1878                         }
1879                 }
1880                 ohci->self_id_buffer[j] =
1881                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1882         }
1883
1884         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1885                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1886                 if (self_id_count < 0) {
1887                         fw_notify("could not construct local self ID\n");
1888                         return;
1889                 }
1890         }
1891
1892         if (self_id_count == 0) {
1893                 fw_notify("inconsistent self IDs\n");
1894                 return;
1895         }
1896         rmb();
1897
1898         /*
1899          * Check the consistency of the self IDs we just read.  The
1900          * problem we face is that a new bus reset can start while we
1901          * read out the self IDs from the DMA buffer. If this happens,
1902          * the DMA buffer will be overwritten with new self IDs and we
1903          * will read out inconsistent data.  The OHCI specification
1904          * (section 11.2) recommends a technique similar to
1905          * linux/seqlock.h, where we remember the generation of the
1906          * self IDs in the buffer before reading them out and compare
1907          * it to the current generation after reading them out.  If
1908          * the two generations match we know we have a consistent set
1909          * of self IDs.
1910          */
1911
1912         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1913         if (new_generation != generation) {
1914                 fw_notify("recursive bus reset detected, "
1915                           "discarding self ids\n");
1916                 return;
1917         }
1918
1919         /* FIXME: Document how the locking works. */
1920         spin_lock_irqsave(&ohci->lock, flags);
1921
1922         ohci->generation = -1; /* prevent AT packet queueing */
1923         context_stop(&ohci->at_request_ctx);
1924         context_stop(&ohci->at_response_ctx);
1925
1926         spin_unlock_irqrestore(&ohci->lock, flags);
1927
1928         /*
1929          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1930          * packets in the AT queues and software needs to drain them.
1931          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1932          */
1933         at_context_flush(&ohci->at_request_ctx);
1934         at_context_flush(&ohci->at_response_ctx);
1935
1936         spin_lock_irqsave(&ohci->lock, flags);
1937
1938         ohci->generation = generation;
1939         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1940
1941         if (ohci->quirks & QUIRK_RESET_PACKET)
1942                 ohci->request_generation = generation;
1943
1944         /*
1945          * This next bit is unrelated to the AT context stuff but we
1946          * have to do it under the spinlock also.  If a new config rom
1947          * was set up before this reset, the old one is now no longer
1948          * in use and we can free it. Update the config rom pointers
1949          * to point to the current config rom and clear the
1950          * next_config_rom pointer so a new update can take place.
1951          */
1952
1953         if (ohci->next_config_rom != NULL) {
1954                 if (ohci->next_config_rom != ohci->config_rom) {
1955                         free_rom      = ohci->config_rom;
1956                         free_rom_bus  = ohci->config_rom_bus;
1957                 }
1958                 ohci->config_rom      = ohci->next_config_rom;
1959                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1960                 ohci->next_config_rom = NULL;
1961
1962                 /*
1963                  * Restore config_rom image and manually update
1964                  * config_rom registers.  Writing the header quadlet
1965                  * will indicate that the config rom is ready, so we
1966                  * do that last.
1967                  */
1968                 reg_write(ohci, OHCI1394_BusOptions,
1969                           be32_to_cpu(ohci->config_rom[2]));
1970                 ohci->config_rom[0] = ohci->next_header;
1971                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1972                           be32_to_cpu(ohci->next_header));
1973         }
1974
1975 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1976         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1977         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1978 #endif
1979
1980         spin_unlock_irqrestore(&ohci->lock, flags);
1981
1982         if (free_rom)
1983                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1984                                   free_rom, free_rom_bus);
1985
1986         log_selfids(ohci->node_id, generation,
1987                     self_id_count, ohci->self_id_buffer);
1988
1989         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1990                                  self_id_count, ohci->self_id_buffer,
1991                                  ohci->csr_state_setclear_abdicate);
1992         ohci->csr_state_setclear_abdicate = false;
1993 }
1994
1995 static irqreturn_t irq_handler(int irq, void *data)
1996 {
1997         struct fw_ohci *ohci = data;
1998         u32 event, iso_event;
1999         int i;
2000
2001         event = reg_read(ohci, OHCI1394_IntEventClear);
2002
2003         if (!event || !~event)
2004                 return IRQ_NONE;
2005
2006         /*
2007          * busReset and postedWriteErr must not be cleared yet
2008          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2009          */
2010         reg_write(ohci, OHCI1394_IntEventClear,
2011                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2012         log_irqs(event);
2013
2014         if (event & OHCI1394_selfIDComplete)
2015                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2016
2017         if (event & OHCI1394_RQPkt)
2018                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2019
2020         if (event & OHCI1394_RSPkt)
2021                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2022
2023         if (event & OHCI1394_reqTxComplete)
2024                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2025
2026         if (event & OHCI1394_respTxComplete)
2027                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2028
2029         if (event & OHCI1394_isochRx) {
2030                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2031                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2032
2033                 while (iso_event) {
2034                         i = ffs(iso_event) - 1;
2035                         tasklet_schedule(
2036                                 &ohci->ir_context_list[i].context.tasklet);
2037                         iso_event &= ~(1 << i);
2038                 }
2039         }
2040
2041         if (event & OHCI1394_isochTx) {
2042                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2043                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2044
2045                 while (iso_event) {
2046                         i = ffs(iso_event) - 1;
2047                         tasklet_schedule(
2048                                 &ohci->it_context_list[i].context.tasklet);
2049                         iso_event &= ~(1 << i);
2050                 }
2051         }
2052
2053         if (unlikely(event & OHCI1394_regAccessFail))
2054                 fw_error("Register access failure - "
2055                          "please notify linux1394-devel@lists.sf.net\n");
2056
2057         if (unlikely(event & OHCI1394_postedWriteErr)) {
2058                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2059                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2060                 reg_write(ohci, OHCI1394_IntEventClear,
2061                           OHCI1394_postedWriteErr);
2062                 if (printk_ratelimit())
2063                         fw_error("PCI posted write error\n");
2064         }
2065
2066         if (unlikely(event & OHCI1394_cycleTooLong)) {
2067                 if (printk_ratelimit())
2068                         fw_notify("isochronous cycle too long\n");
2069                 reg_write(ohci, OHCI1394_LinkControlSet,
2070                           OHCI1394_LinkControl_cycleMaster);
2071         }
2072
2073         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2074                 /*
2075                  * We need to clear this event bit in order to make
2076                  * cycleMatch isochronous I/O work.  In theory we should
2077                  * stop active cycleMatch iso contexts now and restart
2078                  * them at least two cycles later.  (FIXME?)
2079                  */
2080                 if (printk_ratelimit())
2081                         fw_notify("isochronous cycle inconsistent\n");
2082         }
2083
2084         if (unlikely(event & OHCI1394_unrecoverableError))
2085                 handle_dead_contexts(ohci);
2086
2087         if (event & OHCI1394_cycle64Seconds) {
2088                 spin_lock(&ohci->lock);
2089                 update_bus_time(ohci);
2090                 spin_unlock(&ohci->lock);
2091         } else
2092                 flush_writes(ohci);
2093
2094         return IRQ_HANDLED;
2095 }
2096
2097 static int software_reset(struct fw_ohci *ohci)
2098 {
2099         u32 val;
2100         int i;
2101
2102         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2103         for (i = 0; i < 500; i++) {
2104                 val = reg_read(ohci, OHCI1394_HCControlSet);
2105                 if (!~val)
2106                         return -ENODEV; /* Card was ejected. */
2107
2108                 if (!(val & OHCI1394_HCControl_softReset))
2109                         return 0;
2110
2111                 msleep(1);
2112         }
2113
2114         return -EBUSY;
2115 }
2116
2117 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2118 {
2119         size_t size = length * 4;
2120
2121         memcpy(dest, src, size);
2122         if (size < CONFIG_ROM_SIZE)
2123                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2124 }
2125
2126 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2127 {
2128         bool enable_1394a;
2129         int ret, clear, set, offset;
2130
2131         /* Check if the driver should configure link and PHY. */
2132         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2133               OHCI1394_HCControl_programPhyEnable))
2134                 return 0;
2135
2136         /* Paranoia: check whether the PHY supports 1394a, too. */
2137         enable_1394a = false;
2138         ret = read_phy_reg(ohci, 2);
2139         if (ret < 0)
2140                 return ret;
2141         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2142                 ret = read_paged_phy_reg(ohci, 1, 8);
2143                 if (ret < 0)
2144                         return ret;
2145                 if (ret >= 1)
2146                         enable_1394a = true;
2147         }
2148
2149         if (ohci->quirks & QUIRK_NO_1394A)
2150                 enable_1394a = false;
2151
2152         /* Configure PHY and link consistently. */
2153         if (enable_1394a) {
2154                 clear = 0;
2155                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2156         } else {
2157                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2158                 set = 0;
2159         }
2160         ret = update_phy_reg(ohci, 5, clear, set);
2161         if (ret < 0)
2162                 return ret;
2163
2164         if (enable_1394a)
2165                 offset = OHCI1394_HCControlSet;
2166         else
2167                 offset = OHCI1394_HCControlClear;
2168         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2169
2170         /* Clean up: configuration has been taken care of. */
2171         reg_write(ohci, OHCI1394_HCControlClear,
2172                   OHCI1394_HCControl_programPhyEnable);
2173
2174         return 0;
2175 }
2176
2177 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2178 {
2179         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2180         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2181         int reg, i;
2182
2183         reg = read_phy_reg(ohci, 2);
2184         if (reg < 0)
2185                 return reg;
2186         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2187                 return 0;
2188
2189         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2190                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2191                 if (reg < 0)
2192                         return reg;
2193                 if (reg != id[i])
2194                         return 0;
2195         }
2196         return 1;
2197 }
2198
2199 static int ohci_enable(struct fw_card *card,
2200                        const __be32 *config_rom, size_t length)
2201 {
2202         struct fw_ohci *ohci = fw_ohci(card);
2203         struct pci_dev *dev = to_pci_dev(card->device);
2204         u32 lps, seconds, version, irqs;
2205         int i, ret;
2206
2207         if (software_reset(ohci)) {
2208                 fw_error("Failed to reset ohci card.\n");
2209                 return -EBUSY;
2210         }
2211
2212         /*
2213          * Now enable LPS, which we need in order to start accessing
2214          * most of the registers.  In fact, on some cards (ALI M5251),
2215          * accessing registers in the SClk domain without LPS enabled
2216          * will lock up the machine.  Wait 50msec to make sure we have
2217          * full link enabled.  However, with some cards (well, at least
2218          * a JMicron PCIe card), we have to try again sometimes.
2219          */
2220         reg_write(ohci, OHCI1394_HCControlSet,
2221                   OHCI1394_HCControl_LPS |
2222                   OHCI1394_HCControl_postedWriteEnable);
2223         flush_writes(ohci);
2224
2225         for (lps = 0, i = 0; !lps && i < 3; i++) {
2226                 msleep(50);
2227                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2228                       OHCI1394_HCControl_LPS;
2229         }
2230
2231         if (!lps) {
2232                 fw_error("Failed to set Link Power Status\n");
2233                 return -EIO;
2234         }
2235
2236         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2237                 ret = probe_tsb41ba3d(ohci);
2238                 if (ret < 0)
2239                         return ret;
2240                 if (ret)
2241                         fw_notify("local TSB41BA3D phy\n");
2242                 else
2243                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2244         }
2245
2246         reg_write(ohci, OHCI1394_HCControlClear,
2247                   OHCI1394_HCControl_noByteSwapData);
2248
2249         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2250         reg_write(ohci, OHCI1394_LinkControlSet,
2251                   OHCI1394_LinkControl_cycleTimerEnable |
2252                   OHCI1394_LinkControl_cycleMaster);
2253
2254         reg_write(ohci, OHCI1394_ATRetries,
2255                   OHCI1394_MAX_AT_REQ_RETRIES |
2256                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2257                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2258                   (200 << 16));
2259
2260         seconds = lower_32_bits(get_seconds());
2261         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2262         ohci->bus_time = seconds & ~0x3f;
2263
2264         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2265         if (version >= OHCI_VERSION_1_1) {
2266                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2267                           0xfffffffe);
2268                 card->broadcast_channel_auto_allocated = true;
2269         }
2270
2271         /* Get implemented bits of the priority arbitration request counter. */
2272         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2273         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2274         reg_write(ohci, OHCI1394_FairnessControl, 0);
2275         card->priority_budget_implemented = ohci->pri_req_max != 0;
2276
2277         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2278         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2279         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2280
2281         ret = configure_1394a_enhancements(ohci);
2282         if (ret < 0)
2283                 return ret;
2284
2285         /* Activate link_on bit and contender bit in our self ID packets.*/
2286         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2287         if (ret < 0)
2288                 return ret;
2289
2290         /*
2291          * When the link is not yet enabled, the atomic config rom
2292          * update mechanism described below in ohci_set_config_rom()
2293          * is not active.  We have to update ConfigRomHeader and
2294          * BusOptions manually, and the write to ConfigROMmap takes
2295          * effect immediately.  We tie this to the enabling of the
2296          * link, so we have a valid config rom before enabling - the
2297          * OHCI requires that ConfigROMhdr and BusOptions have valid
2298          * values before enabling.
2299          *
2300          * However, when the ConfigROMmap is written, some controllers
2301          * always read back quadlets 0 and 2 from the config rom to
2302          * the ConfigRomHeader and BusOptions registers on bus reset.
2303          * They shouldn't do that in this initial case where the link
2304          * isn't enabled.  This means we have to use the same
2305          * workaround here, setting the bus header to 0 and then write
2306          * the right values in the bus reset tasklet.
2307          */
2308
2309         if (config_rom) {
2310                 ohci->next_config_rom =
2311                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2312                                            &ohci->next_config_rom_bus,
2313                                            GFP_KERNEL);
2314                 if (ohci->next_config_rom == NULL)
2315                         return -ENOMEM;
2316
2317                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2318         } else {
2319                 /*
2320                  * In the suspend case, config_rom is NULL, which
2321                  * means that we just reuse the old config rom.
2322                  */
2323                 ohci->next_config_rom = ohci->config_rom;
2324                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2325         }
2326
2327         ohci->next_header = ohci->next_config_rom[0];
2328         ohci->next_config_rom[0] = 0;
2329         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2330         reg_write(ohci, OHCI1394_BusOptions,
2331                   be32_to_cpu(ohci->next_config_rom[2]));
2332         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2333
2334         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2335
2336         if (!(ohci->quirks & QUIRK_NO_MSI))
2337                 pci_enable_msi(dev);
2338         if (request_irq(dev->irq, irq_handler,
2339                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2340                         ohci_driver_name, ohci)) {
2341                 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2342                 pci_disable_msi(dev);
2343
2344                 if (config_rom) {
2345                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2346                                           ohci->next_config_rom,
2347                                           ohci->next_config_rom_bus);
2348                         ohci->next_config_rom = NULL;
2349                 }
2350                 return -EIO;
2351         }
2352
2353         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2354                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2355                 OHCI1394_isochTx | OHCI1394_isochRx |
2356                 OHCI1394_postedWriteErr |
2357                 OHCI1394_selfIDComplete |
2358                 OHCI1394_regAccessFail |
2359                 OHCI1394_cycle64Seconds |
2360                 OHCI1394_cycleInconsistent |
2361                 OHCI1394_unrecoverableError |
2362                 OHCI1394_cycleTooLong |
2363                 OHCI1394_masterIntEnable;
2364         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2365                 irqs |= OHCI1394_busReset;
2366         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2367
2368         reg_write(ohci, OHCI1394_HCControlSet,
2369                   OHCI1394_HCControl_linkEnable |
2370                   OHCI1394_HCControl_BIBimageValid);
2371
2372         reg_write(ohci, OHCI1394_LinkControlSet,
2373                   OHCI1394_LinkControl_rcvSelfID |
2374                   OHCI1394_LinkControl_rcvPhyPkt);
2375
2376         ar_context_run(&ohci->ar_request_ctx);
2377         ar_context_run(&ohci->ar_response_ctx);
2378
2379         flush_writes(ohci);
2380
2381         /* We are ready to go, reset bus to finish initialization. */
2382         fw_schedule_bus_reset(&ohci->card, false, true);
2383
2384         return 0;
2385 }
2386
2387 static int ohci_set_config_rom(struct fw_card *card,
2388                                const __be32 *config_rom, size_t length)
2389 {
2390         struct fw_ohci *ohci;
2391         unsigned long flags;
2392         __be32 *next_config_rom;
2393         dma_addr_t uninitialized_var(next_config_rom_bus);
2394
2395         ohci = fw_ohci(card);
2396
2397         /*
2398          * When the OHCI controller is enabled, the config rom update
2399          * mechanism is a bit tricky, but easy enough to use.  See
2400          * section 5.5.6 in the OHCI specification.
2401          *
2402          * The OHCI controller caches the new config rom address in a
2403          * shadow register (ConfigROMmapNext) and needs a bus reset
2404          * for the changes to take place.  When the bus reset is
2405          * detected, the controller loads the new values for the
2406          * ConfigRomHeader and BusOptions registers from the specified
2407          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2408          * shadow register. All automatically and atomically.
2409          *
2410          * Now, there's a twist to this story.  The automatic load of
2411          * ConfigRomHeader and BusOptions doesn't honor the
2412          * noByteSwapData bit, so with a be32 config rom, the
2413          * controller will load be32 values in to these registers
2414          * during the atomic update, even on litte endian
2415          * architectures.  The workaround we use is to put a 0 in the
2416          * header quadlet; 0 is endian agnostic and means that the
2417          * config rom isn't ready yet.  In the bus reset tasklet we
2418          * then set up the real values for the two registers.
2419          *
2420          * We use ohci->lock to avoid racing with the code that sets
2421          * ohci->next_config_rom to NULL (see bus_reset_work).
2422          */
2423
2424         next_config_rom =
2425                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2426                                    &next_config_rom_bus, GFP_KERNEL);
2427         if (next_config_rom == NULL)
2428                 return -ENOMEM;
2429
2430         spin_lock_irqsave(&ohci->lock, flags);
2431
2432         /*
2433          * If there is not an already pending config_rom update,
2434          * push our new allocation into the ohci->next_config_rom
2435          * and then mark the local variable as null so that we
2436          * won't deallocate the new buffer.
2437          *
2438          * OTOH, if there is a pending config_rom update, just
2439          * use that buffer with the new config_rom data, and
2440          * let this routine free the unused DMA allocation.
2441          */
2442
2443         if (ohci->next_config_rom == NULL) {
2444                 ohci->next_config_rom = next_config_rom;
2445                 ohci->next_config_rom_bus = next_config_rom_bus;
2446                 next_config_rom = NULL;
2447         }
2448
2449         copy_config_rom(ohci->next_config_rom, config_rom, length);
2450
2451         ohci->next_header = config_rom[0];
2452         ohci->next_config_rom[0] = 0;
2453
2454         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2455
2456         spin_unlock_irqrestore(&ohci->lock, flags);
2457
2458         /* If we didn't use the DMA allocation, delete it. */
2459         if (next_config_rom != NULL)
2460                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2461                                   next_config_rom, next_config_rom_bus);
2462
2463         /*
2464          * Now initiate a bus reset to have the changes take
2465          * effect. We clean up the old config rom memory and DMA
2466          * mappings in the bus reset tasklet, since the OHCI
2467          * controller could need to access it before the bus reset
2468          * takes effect.
2469          */
2470
2471         fw_schedule_bus_reset(&ohci->card, true, true);
2472
2473         return 0;
2474 }
2475
2476 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2477 {
2478         struct fw_ohci *ohci = fw_ohci(card);
2479
2480         at_context_transmit(&ohci->at_request_ctx, packet);
2481 }
2482
2483 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2484 {
2485         struct fw_ohci *ohci = fw_ohci(card);
2486
2487         at_context_transmit(&ohci->at_response_ctx, packet);
2488 }
2489
2490 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2491 {
2492         struct fw_ohci *ohci = fw_ohci(card);
2493         struct context *ctx = &ohci->at_request_ctx;
2494         struct driver_data *driver_data = packet->driver_data;
2495         int ret = -ENOENT;
2496
2497         tasklet_disable(&ctx->tasklet);
2498
2499         if (packet->ack != 0)
2500                 goto out;
2501
2502         if (packet->payload_mapped)
2503                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2504                                  packet->payload_length, DMA_TO_DEVICE);
2505
2506         log_ar_at_event('T', packet->speed, packet->header, 0x20);
2507         driver_data->packet = NULL;
2508         packet->ack = RCODE_CANCELLED;
2509         packet->callback(packet, &ohci->card, packet->ack);
2510         ret = 0;
2511  out:
2512         tasklet_enable(&ctx->tasklet);
2513
2514         return ret;
2515 }
2516
2517 static int ohci_enable_phys_dma(struct fw_card *card,
2518                                 int node_id, int generation)
2519 {
2520 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2521         return 0;
2522 #else
2523         struct fw_ohci *ohci = fw_ohci(card);
2524         unsigned long flags;
2525         int n, ret = 0;
2526
2527         /*
2528          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2529          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2530          */
2531
2532         spin_lock_irqsave(&ohci->lock, flags);
2533
2534         if (ohci->generation != generation) {
2535                 ret = -ESTALE;
2536                 goto out;
2537         }
2538
2539         /*
2540          * Note, if the node ID contains a non-local bus ID, physical DMA is
2541          * enabled for _all_ nodes on remote buses.
2542          */
2543
2544         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2545         if (n < 32)
2546                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2547         else
2548                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2549
2550         flush_writes(ohci);
2551  out:
2552         spin_unlock_irqrestore(&ohci->lock, flags);
2553
2554         return ret;
2555 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2556 }
2557
2558 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2559 {
2560         struct fw_ohci *ohci = fw_ohci(card);
2561         unsigned long flags;
2562         u32 value;
2563
2564         switch (csr_offset) {
2565         case CSR_STATE_CLEAR:
2566         case CSR_STATE_SET:
2567                 if (ohci->is_root &&
2568                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2569                      OHCI1394_LinkControl_cycleMaster))
2570                         value = CSR_STATE_BIT_CMSTR;
2571                 else
2572                         value = 0;
2573                 if (ohci->csr_state_setclear_abdicate)
2574                         value |= CSR_STATE_BIT_ABDICATE;
2575
2576                 return value;
2577
2578         case CSR_NODE_IDS:
2579                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2580
2581         case CSR_CYCLE_TIME:
2582                 return get_cycle_time(ohci);
2583
2584         case CSR_BUS_TIME:
2585                 /*
2586                  * We might be called just after the cycle timer has wrapped
2587                  * around but just before the cycle64Seconds handler, so we
2588                  * better check here, too, if the bus time needs to be updated.
2589                  */
2590                 spin_lock_irqsave(&ohci->lock, flags);
2591                 value = update_bus_time(ohci);
2592                 spin_unlock_irqrestore(&ohci->lock, flags);
2593                 return value;
2594
2595         case CSR_BUSY_TIMEOUT:
2596                 value = reg_read(ohci, OHCI1394_ATRetries);
2597                 return (value >> 4) & 0x0ffff00f;
2598
2599         case CSR_PRIORITY_BUDGET:
2600                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2601                         (ohci->pri_req_max << 8);
2602
2603         default:
2604                 WARN_ON(1);
2605                 return 0;
2606         }
2607 }
2608
2609 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2610 {
2611         struct fw_ohci *ohci = fw_ohci(card);
2612         unsigned long flags;
2613
2614         switch (csr_offset) {
2615         case CSR_STATE_CLEAR:
2616                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2617                         reg_write(ohci, OHCI1394_LinkControlClear,
2618                                   OHCI1394_LinkControl_cycleMaster);
2619                         flush_writes(ohci);
2620                 }
2621                 if (value & CSR_STATE_BIT_ABDICATE)
2622                         ohci->csr_state_setclear_abdicate = false;
2623                 break;
2624
2625         case CSR_STATE_SET:
2626                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2627                         reg_write(ohci, OHCI1394_LinkControlSet,
2628                                   OHCI1394_LinkControl_cycleMaster);
2629                         flush_writes(ohci);
2630                 }
2631                 if (value & CSR_STATE_BIT_ABDICATE)
2632                         ohci->csr_state_setclear_abdicate = true;
2633                 break;
2634
2635         case CSR_NODE_IDS:
2636                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2637                 flush_writes(ohci);
2638                 break;
2639
2640         case CSR_CYCLE_TIME:
2641                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2642                 reg_write(ohci, OHCI1394_IntEventSet,
2643                           OHCI1394_cycleInconsistent);
2644                 flush_writes(ohci);
2645                 break;
2646
2647         case CSR_BUS_TIME:
2648                 spin_lock_irqsave(&ohci->lock, flags);
2649                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2650                 spin_unlock_irqrestore(&ohci->lock, flags);
2651                 break;
2652
2653         case CSR_BUSY_TIMEOUT:
2654                 value = (value & 0xf) | ((value & 0xf) << 4) |
2655                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2656                 reg_write(ohci, OHCI1394_ATRetries, value);
2657                 flush_writes(ohci);
2658                 break;
2659
2660         case CSR_PRIORITY_BUDGET:
2661                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2662                 flush_writes(ohci);
2663                 break;
2664
2665         default:
2666                 WARN_ON(1);
2667                 break;
2668         }
2669 }
2670
2671 static void copy_iso_headers(struct iso_context *ctx, void *p)
2672 {
2673         int i = ctx->header_length;
2674
2675         if (i + ctx->base.header_size > PAGE_SIZE)
2676                 return;
2677
2678         /*
2679          * The iso header is byteswapped to little endian by
2680          * the controller, but the remaining header quadlets
2681          * are big endian.  We want to present all the headers
2682          * as big endian, so we have to swap the first quadlet.
2683          */
2684         if (ctx->base.header_size > 0)
2685                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2686         if (ctx->base.header_size > 4)
2687                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2688         if (ctx->base.header_size > 8)
2689                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2690         ctx->header_length += ctx->base.header_size;
2691 }
2692
2693 static int handle_ir_packet_per_buffer(struct context *context,
2694                                        struct descriptor *d,
2695                                        struct descriptor *last)
2696 {
2697         struct iso_context *ctx =
2698                 container_of(context, struct iso_context, context);
2699         struct descriptor *pd;
2700         __le32 *ir_header;
2701         void *p;
2702
2703         for (pd = d; pd <= last; pd++)
2704                 if (pd->transfer_status)
2705                         break;
2706         if (pd > last)
2707                 /* Descriptor(s) not done yet, stop iteration */
2708                 return 0;
2709
2710         p = last + 1;
2711         copy_iso_headers(ctx, p);
2712
2713         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2714                 ir_header = (__le32 *) p;
2715                 ctx->base.callback.sc(&ctx->base,
2716                                       le32_to_cpu(ir_header[0]) & 0xffff,
2717                                       ctx->header_length, ctx->header,
2718                                       ctx->base.callback_data);
2719                 ctx->header_length = 0;
2720         }
2721
2722         return 1;
2723 }
2724
2725 /* d == last because each descriptor block is only a single descriptor. */
2726 static int handle_ir_buffer_fill(struct context *context,
2727                                  struct descriptor *d,
2728                                  struct descriptor *last)
2729 {
2730         struct iso_context *ctx =
2731                 container_of(context, struct iso_context, context);
2732
2733         if (!last->transfer_status)
2734                 /* Descriptor(s) not done yet, stop iteration */
2735                 return 0;
2736
2737         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2738                 ctx->base.callback.mc(&ctx->base,
2739                                       le32_to_cpu(last->data_address) +
2740                                       le16_to_cpu(last->req_count) -
2741                                       le16_to_cpu(last->res_count),
2742                                       ctx->base.callback_data);
2743
2744         return 1;
2745 }
2746
2747 static int handle_it_packet(struct context *context,
2748                             struct descriptor *d,
2749                             struct descriptor *last)
2750 {
2751         struct iso_context *ctx =
2752                 container_of(context, struct iso_context, context);
2753         int i;
2754         struct descriptor *pd;
2755
2756         for (pd = d; pd <= last; pd++)
2757                 if (pd->transfer_status)
2758                         break;
2759         if (pd > last)
2760                 /* Descriptor(s) not done yet, stop iteration */
2761                 return 0;
2762
2763         i = ctx->header_length;
2764         if (i + 4 < PAGE_SIZE) {
2765                 /* Present this value as big-endian to match the receive code */
2766                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2767                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2768                                 le16_to_cpu(pd->res_count));
2769                 ctx->header_length += 4;
2770         }
2771         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2772                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2773                                       ctx->header_length, ctx->header,
2774                                       ctx->base.callback_data);
2775                 ctx->header_length = 0;
2776         }
2777         return 1;
2778 }
2779
2780 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2781 {
2782         u32 hi = channels >> 32, lo = channels;
2783
2784         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2785         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2786         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2787         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2788         mmiowb();
2789         ohci->mc_channels = channels;
2790 }
2791
2792 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2793                                 int type, int channel, size_t header_size)
2794 {
2795         struct fw_ohci *ohci = fw_ohci(card);
2796         struct iso_context *uninitialized_var(ctx);
2797         descriptor_callback_t uninitialized_var(callback);
2798         u64 *uninitialized_var(channels);
2799         u32 *uninitialized_var(mask), uninitialized_var(regs);
2800         unsigned long flags;
2801         int index, ret = -EBUSY;
2802
2803         spin_lock_irqsave(&ohci->lock, flags);
2804
2805         switch (type) {
2806         case FW_ISO_CONTEXT_TRANSMIT:
2807                 mask     = &ohci->it_context_mask;
2808                 callback = handle_it_packet;
2809                 index    = ffs(*mask) - 1;
2810                 if (index >= 0) {
2811                         *mask &= ~(1 << index);
2812                         regs = OHCI1394_IsoXmitContextBase(index);
2813                         ctx  = &ohci->it_context_list[index];
2814                 }
2815                 break;
2816
2817         case FW_ISO_CONTEXT_RECEIVE:
2818                 channels = &ohci->ir_context_channels;
2819                 mask     = &ohci->ir_context_mask;
2820                 callback = handle_ir_packet_per_buffer;
2821                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2822                 if (index >= 0) {
2823                         *channels &= ~(1ULL << channel);
2824                         *mask     &= ~(1 << index);
2825                         regs = OHCI1394_IsoRcvContextBase(index);
2826                         ctx  = &ohci->ir_context_list[index];
2827                 }
2828                 break;
2829
2830         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2831                 mask     = &ohci->ir_context_mask;
2832                 callback = handle_ir_buffer_fill;
2833                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2834                 if (index >= 0) {
2835                         ohci->mc_allocated = true;
2836                         *mask &= ~(1 << index);
2837                         regs = OHCI1394_IsoRcvContextBase(index);
2838                         ctx  = &ohci->ir_context_list[index];
2839                 }
2840                 break;
2841
2842         default:
2843                 index = -1;
2844                 ret = -ENOSYS;
2845         }
2846
2847         spin_unlock_irqrestore(&ohci->lock, flags);
2848
2849         if (index < 0)
2850                 return ERR_PTR(ret);
2851
2852         memset(ctx, 0, sizeof(*ctx));
2853         ctx->header_length = 0;
2854         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2855         if (ctx->header == NULL) {
2856                 ret = -ENOMEM;
2857                 goto out;
2858         }
2859         ret = context_init(&ctx->context, ohci, regs, callback);
2860         if (ret < 0)
2861                 goto out_with_header;
2862
2863         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2864                 set_multichannel_mask(ohci, 0);
2865
2866         return &ctx->base;
2867
2868  out_with_header:
2869         free_page((unsigned long)ctx->header);
2870  out:
2871         spin_lock_irqsave(&ohci->lock, flags);
2872
2873         switch (type) {
2874         case FW_ISO_CONTEXT_RECEIVE:
2875                 *channels |= 1ULL << channel;
2876                 break;
2877
2878         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2879                 ohci->mc_allocated = false;
2880                 break;
2881         }
2882         *mask |= 1 << index;
2883
2884         spin_unlock_irqrestore(&ohci->lock, flags);
2885
2886         return ERR_PTR(ret);
2887 }
2888
2889 static int ohci_start_iso(struct fw_iso_context *base,
2890                           s32 cycle, u32 sync, u32 tags)
2891 {
2892         struct iso_context *ctx = container_of(base, struct iso_context, base);
2893         struct fw_ohci *ohci = ctx->context.ohci;
2894         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2895         int index;
2896
2897         /* the controller cannot start without any queued packets */
2898         if (ctx->context.last->branch_address == 0)
2899                 return -ENODATA;
2900
2901         switch (ctx->base.type) {
2902         case FW_ISO_CONTEXT_TRANSMIT:
2903                 index = ctx - ohci->it_context_list;
2904                 match = 0;
2905                 if (cycle >= 0)
2906                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2907                                 (cycle & 0x7fff) << 16;
2908
2909                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2910                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2911                 context_run(&ctx->context, match);
2912                 break;
2913
2914         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2915                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2916                 /* fall through */
2917         case FW_ISO_CONTEXT_RECEIVE:
2918                 index = ctx - ohci->ir_context_list;
2919                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2920                 if (cycle >= 0) {
2921                         match |= (cycle & 0x07fff) << 12;
2922                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2923                 }
2924
2925                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2926                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2927                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2928                 context_run(&ctx->context, control);
2929
2930                 ctx->sync = sync;
2931                 ctx->tags = tags;
2932
2933                 break;
2934         }
2935
2936         return 0;
2937 }
2938
2939 static int ohci_stop_iso(struct fw_iso_context *base)
2940 {
2941         struct fw_ohci *ohci = fw_ohci(base->card);
2942         struct iso_context *ctx = container_of(base, struct iso_context, base);
2943         int index;
2944
2945         switch (ctx->base.type) {
2946         case FW_ISO_CONTEXT_TRANSMIT:
2947                 index = ctx - ohci->it_context_list;
2948                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2949                 break;
2950
2951         case FW_ISO_CONTEXT_RECEIVE:
2952         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2953                 index = ctx - ohci->ir_context_list;
2954                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2955                 break;
2956         }
2957         flush_writes(ohci);
2958         context_stop(&ctx->context);
2959         tasklet_kill(&ctx->context.tasklet);
2960
2961         return 0;
2962 }
2963
2964 static void ohci_free_iso_context(struct fw_iso_context *base)
2965 {
2966         struct fw_ohci *ohci = fw_ohci(base->card);
2967         struct iso_context *ctx = container_of(base, struct iso_context, base);
2968         unsigned long flags;
2969         int index;
2970
2971         ohci_stop_iso(base);
2972         context_release(&ctx->context);
2973         free_page((unsigned long)ctx->header);
2974
2975         spin_lock_irqsave(&ohci->lock, flags);
2976
2977         switch (base->type) {
2978         case FW_ISO_CONTEXT_TRANSMIT:
2979                 index = ctx - ohci->it_context_list;
2980                 ohci->it_context_mask |= 1 << index;
2981                 break;
2982
2983         case FW_ISO_CONTEXT_RECEIVE:
2984                 index = ctx - ohci->ir_context_list;
2985                 ohci->ir_context_mask |= 1 << index;
2986                 ohci->ir_context_channels |= 1ULL << base->channel;
2987                 break;
2988
2989         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2990                 index = ctx - ohci->ir_context_list;
2991                 ohci->ir_context_mask |= 1 << index;
2992                 ohci->ir_context_channels |= ohci->mc_channels;
2993                 ohci->mc_channels = 0;
2994                 ohci->mc_allocated = false;
2995                 break;
2996         }
2997
2998         spin_unlock_irqrestore(&ohci->lock, flags);
2999 }
3000
3001 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3002 {
3003         struct fw_ohci *ohci = fw_ohci(base->card);
3004         unsigned long flags;
3005         int ret;
3006
3007         switch (base->type) {
3008         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3009
3010                 spin_lock_irqsave(&ohci->lock, flags);
3011
3012                 /* Don't allow multichannel to grab other contexts' channels. */
3013                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3014                         *channels = ohci->ir_context_channels;
3015                         ret = -EBUSY;
3016                 } else {
3017                         set_multichannel_mask(ohci, *channels);
3018                         ret = 0;
3019                 }
3020
3021                 spin_unlock_irqrestore(&ohci->lock, flags);
3022
3023                 break;
3024         default:
3025                 ret = -EINVAL;
3026         }
3027
3028         return ret;
3029 }
3030
3031 #ifdef CONFIG_PM
3032 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3033 {
3034         int i;
3035         struct iso_context *ctx;
3036
3037         for (i = 0 ; i < ohci->n_ir ; i++) {
3038                 ctx = &ohci->ir_context_list[i];
3039                 if (ctx->context.running)
3040                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3041         }
3042
3043         for (i = 0 ; i < ohci->n_it ; i++) {
3044                 ctx = &ohci->it_context_list[i];
3045                 if (ctx->context.running)
3046                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3047         }
3048 }
3049 #endif
3050
3051 static int queue_iso_transmit(struct iso_context *ctx,
3052                               struct fw_iso_packet *packet,
3053                               struct fw_iso_buffer *buffer,
3054                               unsigned long payload)
3055 {
3056         struct descriptor *d, *last, *pd;
3057         struct fw_iso_packet *p;
3058         __le32 *header;
3059         dma_addr_t d_bus, page_bus;
3060         u32 z, header_z, payload_z, irq;
3061         u32 payload_index, payload_end_index, next_page_index;
3062         int page, end_page, i, length, offset;
3063
3064         p = packet;
3065         payload_index = payload;
3066
3067         if (p->skip)
3068                 z = 1;
3069         else
3070                 z = 2;
3071         if (p->header_length > 0)
3072                 z++;
3073
3074         /* Determine the first page the payload isn't contained in. */
3075         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3076         if (p->payload_length > 0)
3077                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3078         else
3079                 payload_z = 0;
3080
3081         z += payload_z;
3082
3083         /* Get header size in number of descriptors. */
3084         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3085
3086         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3087         if (d == NULL)
3088                 return -ENOMEM;
3089
3090         if (!p->skip) {
3091                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3092                 d[0].req_count = cpu_to_le16(8);
3093                 /*
3094                  * Link the skip address to this descriptor itself.  This causes
3095                  * a context to skip a cycle whenever lost cycles or FIFO
3096                  * overruns occur, without dropping the data.  The application
3097                  * should then decide whether this is an error condition or not.
3098                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3099                  */
3100                 d[0].branch_address = cpu_to_le32(d_bus | z);
3101
3102                 header = (__le32 *) &d[1];
3103                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3104                                         IT_HEADER_TAG(p->tag) |
3105                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3106                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3107                                         IT_HEADER_SPEED(ctx->base.speed));
3108                 header[1] =
3109                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3110                                                           p->payload_length));
3111         }
3112
3113         if (p->header_length > 0) {
3114                 d[2].req_count    = cpu_to_le16(p->header_length);
3115                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3116                 memcpy(&d[z], p->header, p->header_length);
3117         }
3118
3119         pd = d + z - payload_z;
3120         payload_end_index = payload_index + p->payload_length;
3121         for (i = 0; i < payload_z; i++) {
3122                 page               = payload_index >> PAGE_SHIFT;
3123                 offset             = payload_index & ~PAGE_MASK;
3124                 next_page_index    = (page + 1) << PAGE_SHIFT;
3125                 length             =
3126                         min(next_page_index, payload_end_index) - payload_index;
3127                 pd[i].req_count    = cpu_to_le16(length);
3128
3129                 page_bus = page_private(buffer->pages[page]);
3130                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3131
3132                 payload_index += length;
3133         }
3134
3135         if (p->interrupt)