drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/compiler.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gfp.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel.h>
  28 #include <linux/mm.h>
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/pci.h>
  32 #include <linux/spinlock.h>
  33
  34 #include <asm/page.h>
  35 #include <asm/system.h>
  36
  37 #ifdef CONFIG_PPC_PMAC
  38 #include <asm/pmac_feature.h>
  39 #endif
  40
  41 #include "fw-ohci.h"
  42 #include "fw-transaction.h"
  43
  44 #define DESCRIPTOR_OUTPUT_MORE          0
  45 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  46 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  47 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  48 #define DESCRIPTOR_STATUS               (1 << 11)
  49 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  50 #define DESCRIPTOR_PING                 (1 << 7)
  51 #define DESCRIPTOR_YY                   (1 << 6)
  52 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  53 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  54 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  55 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  56 #define DESCRIPTOR_WAIT                 (3 << 0)
  57
  58 struct descriptor {
  59         __le16 req_count;
  60         __le16 control;
  61         __le32 data_address;
  62         __le32 branch_address;
  63         __le16 res_count;
  64         __le16 transfer_status;
  65 } __attribute__((aligned(16)));
  66
  67 struct db_descriptor {
  68         __le16 first_size;
  69         __le16 control;
  70         __le16 second_req_count;
  71         __le16 first_req_count;
  72         __le32 branch_address;
  73         __le16 second_res_count;
  74         __le16 first_res_count;
  75         __le32 reserved0;
  76         __le32 first_buffer;
  77         __le32 second_buffer;
  78         __le32 reserved1;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 struct ar_buffer {
  87         struct descriptor descriptor;
  88         struct ar_buffer *next;
  89         __le32 data[0];
  90 };
  91
  92 struct ar_context {
  93         struct fw_ohci *ohci;
  94         struct ar_buffer *current_buffer;
  95         struct ar_buffer *last_buffer;
  96         void *pointer;
  97         u32 regs;
  98         struct tasklet_struct tasklet;
  99 };
 100
 101 struct context;
 102
 103 typedef int (*descriptor_callback_t)(struct context *ctx,
 104                                      struct descriptor *d,
 105                                      struct descriptor *last);
 106
 107 /*
 108  * A buffer that contains a block of DMA-able coherent memory used for
 109  * storing a portion of a DMA descriptor program.
 110  */
 111 struct descriptor_buffer {
 112         struct list_head list;
 113         dma_addr_t buffer_bus;
 114         size_t buffer_size;
 115         size_t used;
 116         struct descriptor buffer[0];
 117 };
 118
 119 struct context {
 120         struct fw_ohci *ohci;
 121         u32 regs;
 122         int total_allocation;
 123
 124         /*
 125          * List of page-sized buffers for storing DMA descriptors.
 126          * Head of list contains buffers in use and tail of list contains
 127          * free buffers.
 128          */
 129         struct list_head buffer_list;
 130
 131         /*
 132          * Pointer to a buffer inside buffer_list that contains the tail
 133          * end of the current DMA program.
 134          */
 135         struct descriptor_buffer *buffer_tail;
 136
 137         /*
 138          * The descriptor containing the branch address of the first
 139          * descriptor that has not yet been filled by the device.
 140          */
 141         struct descriptor *last;
 142
 143         /*
 144          * The last descriptor in the DMA program.  It contains the branch
 145          * address that must be updated upon appending a new descriptor.
 146          */
 147         struct descriptor *prev;
 148
 149         descriptor_callback_t callback;
 150
 151         struct tasklet_struct tasklet;
 152 };
 153
 154 #define IT_HEADER_SY(v)          ((v) <<  0)
 155 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 156 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 157 #define IT_HEADER_TAG(v)         ((v) << 14)
 158 #define IT_HEADER_SPEED(v)       ((v) << 16)
 159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 160
 161 struct iso_context {
 162         struct fw_iso_context base;
 163         struct context context;
 164         int excess_bytes;
 165         void *header;
 166         size_t header_length;
 167 };
 168
 169 #define CONFIG_ROM_SIZE 1024
 170
 171 struct fw_ohci {
 172         struct fw_card card;
 173
 174         u32 version;
 175         __iomem char *registers;
 176         dma_addr_t self_id_bus;
 177         __le32 *self_id_cpu;
 178         struct tasklet_struct bus_reset_tasklet;
 179         int node_id;
 180         int generation;
 181         int request_generation; /* for timestamping incoming requests */
 182         u32 bus_seconds;
 183         bool old_uninorth;
 184         bool bus_reset_packet_quirk;
 185
 186         /*
 187          * Spinlock for accessing fw_ohci data.  Never call out of
 188          * this driver with this lock held.
 189          */
 190         spinlock_t lock;
 191         u32 self_id_buffer[512];
 192
 193         /* Config rom buffers */
 194         __be32 *config_rom;
 195         dma_addr_t config_rom_bus;
 196         __be32 *next_config_rom;
 197         dma_addr_t next_config_rom_bus;
 198         u32 next_header;
 199
 200         struct ar_context ar_request_ctx;
 201         struct ar_context ar_response_ctx;
 202         struct context at_request_ctx;
 203         struct context at_response_ctx;
 204
 205         u32 it_context_mask;
 206         struct iso_context *it_context_list;
 207         u32 ir_context_mask;
 208         struct iso_context *ir_context_list;
 209 };
 210
 211 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 212 {
 213         return container_of(card, struct fw_ohci, card);
 214 }
 215
 216 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 217 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 218 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 219 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 220 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 221 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 222
 223 #define CONTEXT_RUN     0x8000
 224 #define CONTEXT_WAKE    0x1000
 225 #define CONTEXT_DEAD    0x0800
 226 #define CONTEXT_ACTIVE  0x0400
 227
 228 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 229 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 230 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 231
 232 #define FW_OHCI_MAJOR                   240
 233 #define OHCI1394_REGISTER_SIZE          0x800
 234 #define OHCI_LOOP_COUNT                 500
 235 #define OHCI1394_PCI_HCI_Control        0x40
 236 #define SELF_ID_BUF_SIZE                0x800
 237 #define OHCI_TCODE_PHY_PACKET           0x0e
 238 #define OHCI_VERSION_1_1                0x010010
 239
 240 static char ohci_driver_name[] = KBUILD_MODNAME;
 241
 242 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
 243
 244 #define OHCI_PARAM_DEBUG_AT_AR          1
 245 #define OHCI_PARAM_DEBUG_SELFIDS        2
 246 #define OHCI_PARAM_DEBUG_IRQS           4
 247 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 248
 249 static int param_debug;
 250 module_param_named(debug, param_debug, int, 0644);
 251 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 252         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 253         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 254         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 255         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 256         ", or a combination, or all = -1)");
 257
 258 static void log_irqs(u32 evt)
 259 {
 260         if (likely(!(param_debug &
 261                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 262                 return;
 263
 264         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 265             !(evt & OHCI1394_busReset))
 266                 return;
 267
 268         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 269             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 270             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 271             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 272             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 273             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 274             evt & OHCI1394_isochRx              ? " IR"                 : "",
 275             evt & OHCI1394_isochTx              ? " IT"                 : "",
 276             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 277             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 278             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 279             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 280             evt & OHCI1394_busReset             ? " busReset"           : "",
 281             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 282                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 283                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 284                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 285                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 286                     OHCI1394_regAccessFail | OHCI1394_busReset)
 287                                                 ? " ?"                  : "");
 288 }
 289
 290 static const char *speed[] = {
 291         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 292 };
 293 static const char *power[] = {
 294         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 295         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 296 };
 297 static const char port[] = { '.', '-', 'p', 'c', };
 298
 299 static char _p(u32 *s, int shift)
 300 {
 301         return port[*s >> shift & 3];
 302 }
 303
 304 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
 305 {
 306         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 307                 return;
 308
 309         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
 310                   self_id_count, generation, node_id);
 311
 312         for (; self_id_count--; ++s)
 313                 if ((*s & 1 << 23) == 0)
 314                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
 315                             "%s gc=%d %s %s%s%s\n",
 316                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 317                             speed[*s >> 14 & 3], *s >> 16 & 63,
 318                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 319                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 320                 else
 321                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 322                             *s, *s >> 24 & 63,
 323                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 324                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 325 }
 326
 327 static const char *evts[] = {
 328         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 329         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 330         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 331         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 332         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 333         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 334         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 335         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 336         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 337         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 338         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 339         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 340         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 341         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 342         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 343         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 344         [0x20] = "pending/cancelled",
 345 };
 346 static const char *tcodes[] = {
 347         [0x0] = "QW req",               [0x1] = "BW req",
 348         [0x2] = "W resp",               [0x3] = "-reserved-",
 349         [0x4] = "QR req",               [0x5] = "BR req",
 350         [0x6] = "QR resp",              [0x7] = "BR resp",
 351         [0x8] = "cycle start",          [0x9] = "Lk req",
 352         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 353         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 354         [0xe] = "link internal",        [0xf] = "-reserved-",
 355 };
 356 static const char *phys[] = {
 357         [0x0] = "phy config packet",    [0x1] = "link-on packet",
 358         [0x2] = "self-id packet",       [0x3] = "-reserved-",
 359 };
 360
 361 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 362 {
 363         int tcode = header[0] >> 4 & 0xf;
 364         char specific[12];
 365
 366         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 367                 return;
 368
 369         if (unlikely(evt >= ARRAY_SIZE(evts)))
 370                         evt = 0x1f;
 371
 372         if (evt == OHCI1394_evt_bus_reset) {
 373                 fw_notify("A%c evt_bus_reset, generation %d\n",
 374                     dir, (header[2] >> 16) & 0xff);
 375                 return;
 376         }
 377
 378         if (header[0] == ~header[1]) {
 379                 fw_notify("A%c %s, %s, %08x\n",
 380                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
 381                 return;
 382         }
 383
 384         switch (tcode) {
 385         case 0x0: case 0x6: case 0x8:
 386                 snprintf(specific, sizeof(specific), " = %08x",
 387                          be32_to_cpu((__force __be32)header[3]));
 388                 break;
 389         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 390                 snprintf(specific, sizeof(specific), " %x,%x",
 391                          header[3] >> 16, header[3] & 0xffff);
 392                 break;
 393         default:
 394                 specific[0] = '\0';
 395         }
 396
 397         switch (tcode) {
 398         case 0xe: case 0xa:
 399                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
 400                 break;
 401         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 402                 fw_notify("A%c spd %x tl %02x, "
 403                     "%04x -> %04x, %s, "
 404                     "%s, %04x%08x%s\n",
 405                     dir, speed, header[0] >> 10 & 0x3f,
 406                     header[1] >> 16, header[0] >> 16, evts[evt],
 407                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
 408                 break;
 409         default:
 410                 fw_notify("A%c spd %x tl %02x, "
 411                     "%04x -> %04x, %s, "
 412                     "%s%s\n",
 413                     dir, speed, header[0] >> 10 & 0x3f,
 414                     header[1] >> 16, header[0] >> 16, evts[evt],
 415                     tcodes[tcode], specific);
 416         }
 417 }
 418
 419 #else
 420
 421 #define log_irqs(evt)
 422 #define log_selfids(node_id, generation, self_id_count, sid)
 423 #define log_ar_at_event(dir, speed, header, evt)
 424
 425 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
 426
 427 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 428 {
 429         writel(data, ohci->registers + offset);
 430 }
 431
 432 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 433 {
 434         return readl(ohci->registers + offset);
 435 }
 436
 437 static inline void flush_writes(const struct fw_ohci *ohci)
 438 {
 439         /* Do a dummy read to flush writes. */
 440         reg_read(ohci, OHCI1394_Version);
 441 }
 442
 443 static int
 444 ohci_update_phy_reg(struct fw_card *card, int addr,
 445                     int clear_bits, int set_bits)
 446 {
 447         struct fw_ohci *ohci = fw_ohci(card);
 448         u32 val, old;
 449
 450         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 451         flush_writes(ohci);
 452         msleep(2);
 453         val = reg_read(ohci, OHCI1394_PhyControl);
 454         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 455                 fw_error("failed to set phy reg bits.\n");
 456                 return -EBUSY;
 457         }
 458
 459         old = OHCI1394_PhyControl_ReadData(val);
 460         old = (old & ~clear_bits) | set_bits;
 461         reg_write(ohci, OHCI1394_PhyControl,
 462                   OHCI1394_PhyControl_Write(addr, old));
 463
 464         return 0;
 465 }
 466
 467 static int ar_context_add_page(struct ar_context *ctx)
 468 {
 469         struct device *dev = ctx->ohci->card.device;
 470         struct ar_buffer *ab;
 471         dma_addr_t uninitialized_var(ab_bus);
 472         size_t offset;
 473
 474         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
 475         if (ab == NULL)
 476                 return -ENOMEM;
 477
 478         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 479         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 480                                                     DESCRIPTOR_STATUS |
 481                                                     DESCRIPTOR_BRANCH_ALWAYS);
 482         offset = offsetof(struct ar_buffer, data);
 483         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 484         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 485         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 486         ab->descriptor.branch_address = 0;
 487
 488         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 489         ctx->last_buffer->next = ab;
 490         ctx->last_buffer = ab;
 491
 492         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 493         flush_writes(ctx->ohci);
 494
 495         return 0;
 496 }
 497
 498 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 499 #define cond_le32_to_cpu(v) \
 500         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
 501 #else
 502 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 503 #endif
 504
 505 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 506 {
 507         struct fw_ohci *ohci = ctx->ohci;
 508         struct fw_packet p;
 509         u32 status, length, tcode;
 510         int evt;
 511
 512         p.header[0] = cond_le32_to_cpu(buffer[0]);
 513         p.header[1] = cond_le32_to_cpu(buffer[1]);
 514         p.header[2] = cond_le32_to_cpu(buffer[2]);
 515
 516         tcode = (p.header[0] >> 4) & 0x0f;
 517         switch (tcode) {
 518         case TCODE_WRITE_QUADLET_REQUEST:
 519         case TCODE_READ_QUADLET_RESPONSE:
 520                 p.header[3] = (__force __u32) buffer[3];
 521                 p.header_length = 16;
 522                 p.payload_length = 0;
 523                 break;
 524
 525         case TCODE_READ_BLOCK_REQUEST :
 526                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 527                 p.header_length = 16;
 528                 p.payload_length = 0;
 529                 break;
 530
 531         case TCODE_WRITE_BLOCK_REQUEST:
 532         case TCODE_READ_BLOCK_RESPONSE:
 533         case TCODE_LOCK_REQUEST:
 534         case TCODE_LOCK_RESPONSE:
 535                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 536                 p.header_length = 16;
 537                 p.payload_length = p.header[3] >> 16;
 538                 break;
 539
 540         case TCODE_WRITE_RESPONSE:
 541         case TCODE_READ_QUADLET_REQUEST:
 542         case OHCI_TCODE_PHY_PACKET:
 543                 p.header_length = 12;
 544                 p.payload_length = 0;
 545                 break;
 546
 547         default:
 548                 /* FIXME: Stop context, discard everything, and restart? */
 549                 p.header_length = 0;
 550                 p.payload_length = 0;
 551         }
 552
 553         p.payload = (void *) buffer + p.header_length;
 554
 555         /* FIXME: What to do about evt_* errors? */
 556         length = (p.header_length + p.payload_length + 3) / 4;
 557         status = cond_le32_to_cpu(buffer[length]);
 558         evt    = (status >> 16) & 0x1f;
 559
 560         p.ack        = evt - 16;
 561         p.speed      = (status >> 21) & 0x7;
 562         p.timestamp  = status & 0xffff;
 563         p.generation = ohci->request_generation;
 564
 565         log_ar_at_event('R', p.speed, p.header, evt);
 566
 567         /*
 568          * The OHCI bus reset handler synthesizes a phy packet with
 569          * the new generation number when a bus reset happens (see
 570          * section 8.4.2.3).  This helps us determine when a request
 571          * was received and make sure we send the response in the same
 572          * generation.  We only need this for requests; for responses
 573          * we use the unique tlabel for finding the matching
 574          * request.
 575          *
 576          * Alas some chips sometimes emit bus reset packets with a
 577          * wrong generation.  We set the correct generation for these
 578          * at a slightly incorrect time (in bus_reset_tasklet).
 579          */
 580         if (evt == OHCI1394_evt_bus_reset) {
 581                 if (!ohci->bus_reset_packet_quirk)
 582                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 583         } else if (ctx == &ohci->ar_request_ctx) {
 584                 fw_core_handle_request(&ohci->card, &p);
 585         } else {
 586                 fw_core_handle_response(&ohci->card, &p);
 587         }
 588
 589         return buffer + length + 1;
 590 }
 591
 592 static void ar_context_tasklet(unsigned long data)
 593 {
 594         struct ar_context *ctx = (struct ar_context *)data;
 595         struct fw_ohci *ohci = ctx->ohci;
 596         struct ar_buffer *ab;
 597         struct descriptor *d;
 598         void *buffer, *end;
 599
 600         ab = ctx->current_buffer;
 601         d = &ab->descriptor;
 602
 603         if (d->res_count == 0) {
 604                 size_t size, rest, offset;
 605                 dma_addr_t start_bus;
 606                 void *start;
 607
 608                 /*
 609                  * This descriptor is finished and we may have a
 610                  * packet split across this and the next buffer. We
 611                  * reuse the page for reassembling the split packet.
 612                  */
 613
 614                 offset = offsetof(struct ar_buffer, data);
 615                 start = buffer = ab;
 616                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 617
 618                 ab = ab->next;
 619                 d = &ab->descriptor;
 620                 size = buffer + PAGE_SIZE - ctx->pointer;
 621                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 622                 memmove(buffer, ctx->pointer, size);
 623                 memcpy(buffer + size, ab->data, rest);
 624                 ctx->current_buffer = ab;
 625                 ctx->pointer = (void *) ab->data + rest;
 626                 end = buffer + size + rest;
 627
 628                 while (buffer < end)
 629                         buffer = handle_ar_packet(ctx, buffer);
 630
 631                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
 632                                   start, start_bus);
 633                 ar_context_add_page(ctx);
 634         } else {
 635                 buffer = ctx->pointer;
 636                 ctx->pointer = end =
 637                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 638
 639                 while (buffer < end)
 640                         buffer = handle_ar_packet(ctx, buffer);
 641         }
 642 }
 643
 644 static int
 645 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 646 {
 647         struct ar_buffer ab;
 648
 649         ctx->regs        = regs;
 650         ctx->ohci        = ohci;
 651         ctx->last_buffer = &ab;
 652         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 653
 654         ar_context_add_page(ctx);
 655         ar_context_add_page(ctx);
 656         ctx->current_buffer = ab.next;
 657         ctx->pointer = ctx->current_buffer->data;
 658
 659         return 0;
 660 }
 661
 662 static void ar_context_run(struct ar_context *ctx)
 663 {
 664         struct ar_buffer *ab = ctx->current_buffer;
 665         dma_addr_t ab_bus;
 666         size_t offset;
 667
 668         offset = offsetof(struct ar_buffer, data);
 669         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
 670
 671         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 672         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 673         flush_writes(ctx->ohci);
 674 }
 675
 676 static struct descriptor *
 677 find_branch_descriptor(struct descriptor *d, int z)
 678 {
 679         int b, key;
 680
 681         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
 682         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
 683
 684         /* figure out which descriptor the branch address goes in */
 685         if (z == 2 && (b == 3 || key == 2))
 686                 return d;
 687         else
 688                 return d + z - 1;
 689 }
 690
 691 static void context_tasklet(unsigned long data)
 692 {
 693         struct context *ctx = (struct context *) data;
 694         struct descriptor *d, *last;
 695         u32 address;
 696         int z;
 697         struct descriptor_buffer *desc;
 698
 699         desc = list_entry(ctx->buffer_list.next,
 700                         struct descriptor_buffer, list);
 701         last = ctx->last;
 702         while (last->branch_address != 0) {
 703                 struct descriptor_buffer *old_desc = desc;
 704                 address = le32_to_cpu(last->branch_address);
 705                 z = address & 0xf;
 706                 address &= ~0xf;
 707
 708                 /* If the branch address points to a buffer outside of the
 709                  * current buffer, advance to the next buffer. */
 710                 if (address < desc->buffer_bus ||
 711                                 address >= desc->buffer_bus + desc->used)
 712                         desc = list_entry(desc->list.next,
 713                                         struct descriptor_buffer, list);
 714                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
 715                 last = find_branch_descriptor(d, z);
 716
 717                 if (!ctx->callback(ctx, d, last))
 718                         break;
 719
 720                 if (old_desc != desc) {
 721                         /* If we've advanced to the next buffer, move the
 722                          * previous buffer to the free list. */
 723                         unsigned long flags;
 724                         old_desc->used = 0;
 725                         spin_lock_irqsave(&ctx->ohci->lock, flags);
 726                         list_move_tail(&old_desc->list, &ctx->buffer_list);
 727                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 728                 }
 729                 ctx->last = last;
 730         }
 731 }
 732
 733 /*
 734  * Allocate a new buffer and add it to the list of free buffers for this
 735  * context.  Must be called with ohci->lock held.
 736  */
 737 static int
 738 context_add_buffer(struct context *ctx)
 739 {
 740         struct descriptor_buffer *desc;
 741         dma_addr_t uninitialized_var(bus_addr);
 742         int offset;
 743
 744         /*
 745          * 16MB of descriptors should be far more than enough for any DMA
 746          * program.  This will catch run-away userspace or DoS attacks.
 747          */
 748         if (ctx->total_allocation >= 16*1024*1024)
 749                 return -ENOMEM;
 750
 751         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
 752                         &bus_addr, GFP_ATOMIC);
 753         if (!desc)
 754                 return -ENOMEM;
 755
 756         offset = (void *)&desc->buffer - (void *)desc;
 757         desc->buffer_size = PAGE_SIZE - offset;
 758         desc->buffer_bus = bus_addr + offset;
 759         desc->used = 0;
 760
 761         list_add_tail(&desc->list, &ctx->buffer_list);
 762         ctx->total_allocation += PAGE_SIZE;
 763
 764         return 0;
 765 }
 766
 767 static int
 768 context_init(struct context *ctx, struct fw_ohci *ohci,
 769              u32 regs, descriptor_callback_t callback)
 770 {
 771         ctx->ohci = ohci;
 772         ctx->regs = regs;
 773         ctx->total_allocation = 0;
 774
 775         INIT_LIST_HEAD(&ctx->buffer_list);
 776         if (context_add_buffer(ctx) < 0)
 777                 return -ENOMEM;
 778
 779         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
 780                         struct descriptor_buffer, list);
 781
 782         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 783         ctx->callback = callback;
 784
 785         /*
 786          * We put a dummy descriptor in the buffer that has a NULL
 787          * branch address and looks like it's been sent.  That way we
 788          * have a descriptor to append DMA programs to.
 789          */
 790         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
 791         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 792         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
 793         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
 794         ctx->last = ctx->buffer_tail->buffer;
 795         ctx->prev = ctx->buffer_tail->buffer;
 796
 797         return 0;
 798 }
 799
 800 static void
 801 context_release(struct context *ctx)
 802 {
 803         struct fw_card *card = &ctx->ohci->card;
 804         struct descriptor_buffer *desc, *tmp;
 805
 806         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
 807                 dma_free_coherent(card->device, PAGE_SIZE, desc,
 808                         desc->buffer_bus -
 809                         ((void *)&desc->buffer - (void *)desc));
 810 }
 811
 812 /* Must be called with ohci->lock held */
 813 static struct descriptor *
 814 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 815 {
 816         struct descriptor *d = NULL;
 817         struct descriptor_buffer *desc = ctx->buffer_tail;
 818
 819         if (z * sizeof(*d) > desc->buffer_size)
 820                 return NULL;
 821
 822         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
 823                 /* No room for the descriptor in this buffer, so advance to the
 824                  * next one. */
 825
 826                 if (desc->list.next == &ctx->buffer_list) {
 827                         /* If there is no free buffer next in the list,
 828                          * allocate one. */
 829                         if (context_add_buffer(ctx) < 0)
 830                                 return NULL;
 831                 }
 832                 desc = list_entry(desc->list.next,
 833                                 struct descriptor_buffer, list);
 834                 ctx->buffer_tail = desc;
 835         }
 836
 837         d = desc->buffer + desc->used / sizeof(*d);
 838         memset(d, 0, z * sizeof(*d));
 839         *d_bus = desc->buffer_bus + desc->used;
 840
 841         return d;
 842 }
 843
 844 static void context_run(struct context *ctx, u32 extra)
 845 {
 846         struct fw_ohci *ohci = ctx->ohci;
 847
 848         reg_write(ohci, COMMAND_PTR(ctx->regs),
 849                   le32_to_cpu(ctx->last->branch_address));
 850         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 851         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 852         flush_writes(ohci);
 853 }
 854
 855 static void context_append(struct context *ctx,
 856                            struct descriptor *d, int z, int extra)
 857 {
 858         dma_addr_t d_bus;
 859         struct descriptor_buffer *desc = ctx->buffer_tail;
 860
 861         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
 862
 863         desc->used += (z + extra) * sizeof(*d);
 864         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
 865         ctx->prev = find_branch_descriptor(d, z);
 866
 867         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 868         flush_writes(ctx->ohci);
 869 }
 870
 871 static void context_stop(struct context *ctx)
 872 {
 873         u32 reg;
 874         int i;
 875
 876         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 877         flush_writes(ctx->ohci);
 878
 879         for (i = 0; i < 10; i++) {
 880                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 881                 if ((reg & CONTEXT_ACTIVE) == 0)
 882                         break;
 883
 884                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 885                 mdelay(1);
 886         }
 887 }
 888
 889 struct driver_data {
 890         struct fw_packet *packet;
 891 };
 892
 893 /*
 894  * This function apppends a packet to the DMA queue for transmission.
 895  * Must always be called with the ochi->lock held to ensure proper
 896  * generation handling and locking around packet queue manipulation.
 897  */
 898 static int
 899 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 900 {
 901         struct fw_ohci *ohci = ctx->ohci;
 902         dma_addr_t d_bus, uninitialized_var(payload_bus);
 903         struct driver_data *driver_data;
 904         struct descriptor *d, *last;
 905         __le32 *header;
 906         int z, tcode;
 907         u32 reg;
 908
 909         d = context_get_descriptors(ctx, 4, &d_bus);
 910         if (d == NULL) {
 911                 packet->ack = RCODE_SEND_ERROR;
 912                 return -1;
 913         }
 914
 915         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 916         d[0].res_count = cpu_to_le16(packet->timestamp);
 917
 918         /*
 919          * The DMA format for asyncronous link packets is different
 920          * from the IEEE1394 layout, so shift the fields around
 921          * accordingly.  If header_length is 8, it's a PHY packet, to
 922          * which we need to prepend an extra quadlet.
 923          */
 924
 925         header = (__le32 *) &d[1];
 926         if (packet->header_length > 8) {
 927                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 928                                         (packet->speed << 16));
 929                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 930                                         (packet->header[0] & 0xffff0000));
 931                 header[2] = cpu_to_le32(packet->header[2]);
 932
 933                 tcode = (packet->header[0] >> 4) & 0x0f;
 934                 if (TCODE_IS_BLOCK_PACKET(tcode))
 935                         header[3] = cpu_to_le32(packet->header[3]);
 936                 else
 937                         header[3] = (__force __le32) packet->header[3];
 938
 939                 d[0].req_count = cpu_to_le16(packet->header_length);
 940         } else {
 941                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 942                                         (packet->speed << 16));
 943                 header[1] = cpu_to_le32(packet->header[0]);
 944                 header[2] = cpu_to_le32(packet->header[1]);
 945                 d[0].req_count = cpu_to_le16(12);
 946         }
 947
 948         driver_data = (struct driver_data *) &d[3];
 949         driver_data->packet = packet;
 950         packet->driver_data = driver_data;
 951
 952         if (packet->payload_length > 0) {
 953                 payload_bus =
 954                         dma_map_single(ohci->card.device, packet->payload,
 955                                        packet->payload_length, DMA_TO_DEVICE);
 956                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
 957                         packet->ack = RCODE_SEND_ERROR;
 958                         return -1;
 959                 }
 960
 961                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 962                 d[2].data_address = cpu_to_le32(payload_bus);
 963                 last = &d[2];
 964                 z = 3;
 965         } else {
 966                 last = &d[0];
 967                 z = 2;
 968         }
 969
 970         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 971                                      DESCRIPTOR_IRQ_ALWAYS |
 972                                      DESCRIPTOR_BRANCH_ALWAYS);
 973
 974         /*
 975          * If the controller and packet generations don't match, we need to
 976          * bail out and try again.  If IntEvent.busReset is set, the AT context
 977          * is halted, so appending to the context and trying to run it is
 978          * futile.  Most controllers do the right thing and just flush the AT
 979          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
 980          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
 981          * up stalling out.  So we just bail out in software and try again
 982          * later, and everyone is happy.
 983          * FIXME: Document how the locking works.
 984          */
 985         if (ohci->generation != packet->generation ||
 986             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
 987                 if (packet->payload_length > 0)
 988                         dma_unmap_single(ohci->card.device, payload_bus,
 989                                          packet->payload_length, DMA_TO_DEVICE);
 990                 packet->ack = RCODE_GENERATION;
 991                 return -1;
 992         }
 993
 994         context_append(ctx, d, z, 4 - z);
 995
 996         /* If the context isn't already running, start it up. */
 997         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 998         if ((reg & CONTEXT_RUN) == 0)
 999                 context_run(ctx, 0);
1000
1001         return 0;
1002 }
1003
1004 static int handle_at_packet(struct context *context,
1005                             struct descriptor *d,
1006                             struct descriptor *last)
1007 {
1008         struct driver_data *driver_data;
1009         struct fw_packet *packet;
1010         struct fw_ohci *ohci = context->ohci;
1011         dma_addr_t payload_bus;
1012         int evt;
1013
1014         if (last->transfer_status == 0)
1015                 /* This descriptor isn't done yet, stop iteration. */
1016                 return 0;
1017
1018         driver_data = (struct driver_data *) &d[3];
1019         packet = driver_data->packet;
1020         if (packet == NULL)
1021                 /* This packet was cancelled, just continue. */
1022                 return 1;
1023
1024         payload_bus = le32_to_cpu(last->data_address);
1025         if (payload_bus != 0)
1026                 dma_unmap_single(ohci->card.device, payload_bus,
1027                                  packet->payload_length, DMA_TO_DEVICE);
1028
1029         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1030         packet->timestamp = le16_to_cpu(last->res_count);
1031
1032         log_ar_at_event('T', packet->speed, packet->header, evt);
1033
1034         switch (evt) {
1035         case OHCI1394_evt_timeout:
1036                 /* Async response transmit timed out. */
1037                 packet->ack = RCODE_CANCELLED;
1038                 break;
1039
1040         case OHCI1394_evt_flushed:
1041                 /*
1042                  * The packet was flushed should give same error as
1043                  * when we try to use a stale generation count.
1044                  */
1045                 packet->ack = RCODE_GENERATION;
1046                 break;
1047
1048         case OHCI1394_evt_missing_ack:
1049                 /*
1050                  * Using a valid (current) generation count, but the
1051                  * node is not on the bus or not sending acks.
1052                  */
1053                 packet->ack = RCODE_NO_ACK;
1054                 break;
1055
1056         case ACK_COMPLETE + 0x10:
1057         case ACK_PENDING + 0x10:
1058         case ACK_BUSY_X + 0x10:
1059         case ACK_BUSY_A + 0x10:
1060         case ACK_BUSY_B + 0x10:
1061         case ACK_DATA_ERROR + 0x10:
1062         case ACK_TYPE_ERROR + 0x10:
1063                 packet->ack = evt - 0x10;
1064                 break;
1065
1066         default:
1067                 packet->ack = RCODE_SEND_ERROR;
1068                 break;
1069         }
1070
1071         packet->callback(packet, &ohci->card, packet->ack);
1072
1073         return 1;
1074 }
1075
1076 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1077 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1078 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1079 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1080 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1081
1082 static void
1083 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1084 {
1085         struct fw_packet response;
1086         int tcode, length, i;
1087
1088         tcode = HEADER_GET_TCODE(packet->header[0]);
1089         if (TCODE_IS_BLOCK_PACKET(tcode))
1090                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1091         else
1092                 length = 4;
1093
1094         i = csr - CSR_CONFIG_ROM;
1095         if (i + length > CONFIG_ROM_SIZE) {
1096                 fw_fill_response(&response, packet->header,
1097                                  RCODE_ADDRESS_ERROR, NULL, 0);
1098         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1099                 fw_fill_response(&response, packet->header,
1100                                  RCODE_TYPE_ERROR, NULL, 0);
1101         } else {
1102                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1103                                  (void *) ohci->config_rom + i, length);
1104         }
1105
1106         fw_core_handle_response(&ohci->card, &response);
1107 }
1108
1109 static void
1110 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1111 {
1112         struct fw_packet response;
1113         int tcode, length, ext_tcode, sel;
1114         __be32 *payload, lock_old;
1115         u32 lock_arg, lock_data;
1116
1117         tcode = HEADER_GET_TCODE(packet->header[0]);
1118         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1119         payload = packet->payload;
1120         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1121
1122         if (tcode == TCODE_LOCK_REQUEST &&
1123             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1124                 lock_arg = be32_to_cpu(payload[0]);
1125                 lock_data = be32_to_cpu(payload[1]);
1126         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1127                 lock_arg = 0;
1128                 lock_data = 0;
1129         } else {
1130                 fw_fill_response(&response, packet->header,
1131                                  RCODE_TYPE_ERROR, NULL, 0);
1132                 goto out;
1133         }
1134
1135         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1136         reg_write(ohci, OHCI1394_CSRData, lock_data);
1137         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1138         reg_write(ohci, OHCI1394_CSRControl, sel);
1139
1140         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1141                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1142         else
1143                 fw_notify("swap not done yet\n");
1144
1145         fw_fill_response(&response, packet->header,
1146                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1147  out:
1148         fw_core_handle_response(&ohci->card, &response);
1149 }
1150
1151 static void
1152 handle_local_request(struct context *ctx, struct fw_packet *packet)
1153 {
1154         u64 offset;
1155         u32 csr;
1156
1157         if (ctx == &ctx->ohci->at_request_ctx) {
1158                 packet->ack = ACK_PENDING;
1159                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1160         }
1161
1162         offset =
1163                 ((unsigned long long)
1164                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1165                 packet->header[2];
1166         csr = offset - CSR_REGISTER_BASE;
1167
1168         /* Handle config rom reads. */
1169         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1170                 handle_local_rom(ctx->ohci, packet, csr);
1171         else switch (csr) {
1172         case CSR_BUS_MANAGER_ID:
1173         case CSR_BANDWIDTH_AVAILABLE:
1174         case CSR_CHANNELS_AVAILABLE_HI:
1175         case CSR_CHANNELS_AVAILABLE_LO:
1176                 handle_local_lock(ctx->ohci, packet, csr);
1177                 break;
1178         default:
1179                 if (ctx == &ctx->ohci->at_request_ctx)
1180                         fw_core_handle_request(&ctx->ohci->card, packet);
1181                 else
1182                         fw_core_handle_response(&ctx->ohci->card, packet);
1183                 break;
1184         }
1185
1186         if (ctx == &ctx->ohci->at_response_ctx) {
1187                 packet->ack = ACK_COMPLETE;
1188                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1189         }
1190 }
1191
1192 static void
1193 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1194 {
1195         unsigned long flags;
1196         int retval;
1197
1198         spin_lock_irqsave(&ctx->ohci->lock, flags);
1199
1200         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1201             ctx->ohci->generation == packet->generation) {
1202                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1203                 handle_local_request(ctx, packet);
1204                 return;
1205         }
1206
1207         retval = at_context_queue_packet(ctx, packet);
1208         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1209
1210         if (retval < 0)
1211                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1212
1213 }
1214
1215 static void bus_reset_tasklet(unsigned long data)
1216 {
1217         struct fw_ohci *ohci = (struct fw_ohci *)data;
1218         int self_id_count, i, j, reg;
1219         int generation, new_generation;
1220         unsigned long flags;
1221         void *free_rom = NULL;
1222         dma_addr_t free_rom_bus = 0;
1223
1224         reg = reg_read(ohci, OHCI1394_NodeID);
1225         if (!(reg & OHCI1394_NodeID_idValid)) {
1226                 fw_notify("node ID not valid, new bus reset in progress\n");
1227                 return;
1228         }
1229         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1230                 fw_notify("malconfigured bus\n");
1231                 return;
1232         }
1233         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1234                                OHCI1394_NodeID_nodeNumber);
1235
1236         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1237         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1238                 fw_notify("inconsistent self IDs\n");
1239                 return;
1240         }
1241         /*
1242          * The count in the SelfIDCount register is the number of
1243          * bytes in the self ID receive buffer.  Since we also receive
1244          * the inverted quadlets and a header quadlet, we shift one
1245          * bit extra to get the actual number of self IDs.
1246          */
1247         self_id_count = (reg >> 3) & 0x3ff;
1248         if (self_id_count == 0) {
1249                 fw_notify("inconsistent self IDs\n");
1250                 return;
1251         }
1252         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1253         rmb();
1254
1255         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1256                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1257                         fw_notify("inconsistent self IDs\n");
1258                         return;
1259                 }
1260                 ohci->self_id_buffer[j] =
1261                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1262         }
1263         rmb();
1264
1265         /*
1266          * Check the consistency of the self IDs we just read.  The
1267          * problem we face is that a new bus reset can start while we
1268          * read out the self IDs from the DMA buffer. If this happens,
1269          * the DMA buffer will be overwritten with new self IDs and we
1270          * will read out inconsistent data.  The OHCI specification
1271          * (section 11.2) recommends a technique similar to
1272          * linux/seqlock.h, where we remember the generation of the
1273          * self IDs in the buffer before reading them out and compare
1274          * it to the current generation after reading them out.  If
1275          * the two generations match we know we have a consistent set
1276          * of self IDs.
1277          */
1278
1279         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1280         if (new_generation != generation) {
1281                 fw_notify("recursive bus reset detected, "
1282                           "discarding self ids\n");
1283                 return;
1284         }
1285
1286         /* FIXME: Document how the locking works. */
1287         spin_lock_irqsave(&ohci->lock, flags);
1288
1289         ohci->generation = generation;
1290         context_stop(&ohci->at_request_ctx);
1291         context_stop(&ohci->at_response_ctx);
1292         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1293
1294         if (ohci->bus_reset_packet_quirk)
1295                 ohci->request_generation = generation;
1296
1297         /*
1298          * This next bit is unrelated to the AT context stuff but we
1299          * have to do it under the spinlock also.  If a new config rom
1300          * was set up before this reset, the old one is now no longer
1301          * in use and we can free it. Update the config rom pointers
1302          * to point to the current config rom and clear the
1303          * next_config_rom pointer so a new udpate can take place.
1304          */
1305
1306         if (ohci->next_config_rom != NULL) {
1307                 if (ohci->next_config_rom != ohci->config_rom) {
1308                         free_rom      = ohci->config_rom;
1309                         free_rom_bus  = ohci->config_rom_bus;
1310                 }
1311                 ohci->config_rom      = ohci->next_config_rom;
1312                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1313                 ohci->next_config_rom = NULL;
1314
1315                 /*
1316                  * Restore config_rom image and manually update
1317                  * config_rom registers.  Writing the header quadlet
1318                  * will indicate that the config rom is ready, so we
1319                  * do that last.
1320                  */
1321                 reg_write(ohci, OHCI1394_BusOptions,
1322                           be32_to_cpu(ohci->config_rom[2]));
1323                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1324                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1325         }
1326
1327 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1328         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1329         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1330 #endif
1331
1332         spin_unlock_irqrestore(&ohci->lock, flags);
1333
1334         if (free_rom)
1335                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1336                                   free_rom, free_rom_bus);
1337
1338         log_selfids(ohci->node_id, generation,
1339                     self_id_count, ohci->self_id_buffer);
1340
1341         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1342                                  self_id_count, ohci->self_id_buffer);
1343 }
1344
1345 static irqreturn_t irq_handler(int irq, void *data)
1346 {
1347         struct fw_ohci *ohci = data;
1348         u32 event, iso_event, cycle_time;
1349         int i;
1350
1351         event = reg_read(ohci, OHCI1394_IntEventClear);
1352
1353         if (!event || !~event)
1354                 return IRQ_NONE;
1355
1356         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1357         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1358         log_irqs(event);
1359
1360         if (event & OHCI1394_selfIDComplete)
1361                 tasklet_schedule(&ohci->bus_reset_tasklet);
1362
1363         if (event & OHCI1394_RQPkt)
1364                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1365
1366         if (event & OHCI1394_RSPkt)
1367                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1368
1369         if (event & OHCI1394_reqTxComplete)
1370                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1371
1372         if (event & OHCI1394_respTxComplete)
1373                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1374
1375         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1376         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1377
1378         while (iso_event) {
1379                 i = ffs(iso_event) - 1;
1380                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1381                 iso_event &= ~(1 << i);
1382         }
1383
1384         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1385         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1386
1387         while (iso_event) {
1388                 i = ffs(iso_event) - 1;
1389                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1390                 iso_event &= ~(1 << i);
1391         }
1392
1393         if (unlikely(event & OHCI1394_regAccessFail))
1394                 fw_error("Register access failure - "
1395                          "please notify linux1394-devel@lists.sf.net\n");
1396
1397         if (unlikely(event & OHCI1394_postedWriteErr))
1398                 fw_error("PCI posted write error\n");
1399
1400         if (unlikely(event & OHCI1394_cycleTooLong)) {
1401                 if (printk_ratelimit())
1402                         fw_notify("isochronous cycle too long\n");
1403                 reg_write(ohci, OHCI1394_LinkControlSet,
1404                           OHCI1394_LinkControl_cycleMaster);
1405         }
1406
1407         if (event & OHCI1394_cycle64Seconds) {
1408                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1409                 if ((cycle_time & 0x80000000) == 0)
1410                         ohci->bus_seconds++;
1411         }
1412
1413         return IRQ_HANDLED;
1414 }
1415
1416 static int software_reset(struct fw_ohci *ohci)
1417 {
1418         int i;
1419
1420         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1421
1422         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1423                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1424                      OHCI1394_HCControl_softReset) == 0)
1425                         return 0;
1426                 msleep(1);
1427         }
1428
1429         return -EBUSY;
1430 }
1431
1432 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1433 {
1434         struct fw_ohci *ohci = fw_ohci(card);
1435         struct pci_dev *dev = to_pci_dev(card->device);
1436         u32 lps;
1437         int i;
1438
1439         if (software_reset(ohci)) {
1440                 fw_error("Failed to reset ohci card.\n");
1441                 return -EBUSY;
1442         }
1443
1444         /*
1445          * Now enable LPS, which we need in order to start accessing
1446          * most of the registers.  In fact, on some cards (ALI M5251),
1447          * accessing registers in the SClk domain without LPS enabled
1448          * will lock up the machine.  Wait 50msec to make sure we have
1449          * full link enabled.  However, with some cards (well, at least
1450          * a JMicron PCIe card), we have to try again sometimes.
1451          */
1452         reg_write(ohci, OHCI1394_HCControlSet,
1453                   OHCI1394_HCControl_LPS |
1454                   OHCI1394_HCControl_postedWriteEnable);
1455         flush_writes(ohci);
1456
1457         for (lps = 0, i = 0; !lps && i < 3; i++) {
1458                 msleep(50);
1459                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1460                       OHCI1394_HCControl_LPS;
1461         }
1462
1463         if (!lps) {
1464                 fw_error("Failed to set Link Power Status\n");
1465                 return -EIO;
1466         }
1467
1468         reg_write(ohci, OHCI1394_HCControlClear,
1469                   OHCI1394_HCControl_noByteSwapData);
1470
1471         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1472         reg_write(ohci, OHCI1394_LinkControlClear,
1473                   OHCI1394_LinkControl_rcvPhyPkt);
1474         reg_write(ohci, OHCI1394_LinkControlSet,
1475                   OHCI1394_LinkControl_rcvSelfID |
1476                   OHCI1394_LinkControl_cycleTimerEnable |
1477                   OHCI1394_LinkControl_cycleMaster);
1478
1479         reg_write(ohci, OHCI1394_ATRetries,
1480                   OHCI1394_MAX_AT_REQ_RETRIES |
1481                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1482                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1483
1484         ar_context_run(&ohci->ar_request_ctx);
1485         ar_context_run(&ohci->ar_response_ctx);
1486
1487         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1488         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1489         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1490         reg_write(ohci, OHCI1394_IntMaskSet,
1491                   OHCI1394_selfIDComplete |
1492                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1493                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1494                   OHCI1394_isochRx | OHCI1394_isochTx |
1495                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1496                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1497                   OHCI1394_masterIntEnable);
1498         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1499                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1500
1501         /* Activate link_on bit and contender bit in our self ID packets.*/
1502         if (ohci_update_phy_reg(card, 4, 0,
1503                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1504                 return -EIO;
1505
1506         /*
1507          * When the link is not yet enabled, the atomic config rom
1508          * update mechanism described below in ohci_set_config_rom()
1509          * is not active.  We have to update ConfigRomHeader and
1510          * BusOptions manually, and the write to ConfigROMmap takes
1511          * effect immediately.  We tie this to the enabling of the
1512          * link, so we have a valid config rom before enabling - the
1513          * OHCI requires that ConfigROMhdr and BusOptions have valid
1514          * values before enabling.
1515          *
1516          * However, when the ConfigROMmap is written, some controllers
1517          * always read back quadlets 0 and 2 from the config rom to
1518          * the ConfigRomHeader and BusOptions registers on bus reset.
1519          * They shouldn't do that in this initial case where the link
1520          * isn't enabled.  This means we have to use the same
1521          * workaround here, setting the bus header to 0 and then write
1522          * the right values in the bus reset tasklet.
1523          */
1524
1525         if (config_rom) {
1526                 ohci->next_config_rom =
1527                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1528                                            &ohci->next_config_rom_bus,
1529                                            GFP_KERNEL);
1530                 if (ohci->next_config_rom == NULL)
1531                         return -ENOMEM;
1532
1533                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1534                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1535         } else {
1536                 /*
1537                  * In the suspend case, config_rom is NULL, which
1538                  * means that we just reuse the old config rom.
1539                  */
1540                 ohci->next_config_rom = ohci->config_rom;
1541                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1542         }
1543
1544         ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1545         ohci->next_config_rom[0] = 0;
1546         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1547         reg_write(ohci, OHCI1394_BusOptions,
1548                   be32_to_cpu(ohci->next_config_rom[2]));
1549         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1550
1551         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1552
1553         if (request_irq(dev->irq, irq_handler,
1554                         IRQF_SHARED, ohci_driver_name, ohci)) {
1555                 fw_error("Failed to allocate shared interrupt %d.\n",
1556                          dev->irq);
1557                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1558                                   ohci->config_rom, ohci->config_rom_bus);
1559                 return -EIO;
1560         }
1561
1562         reg_write(ohci, OHCI1394_HCControlSet,
1563                   OHCI1394_HCControl_linkEnable |
1564                   OHCI1394_HCControl_BIBimageValid);
1565         flush_writes(ohci);
1566
1567         /*
1568          * We are ready to go, initiate bus reset to finish the
1569          * initialization.
1570          */
1571
1572         fw_core_initiate_bus_reset(&ohci->card, 1);
1573
1574         return 0;
1575 }
1576
1577 static int
1578 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1579 {
1580         struct fw_ohci *ohci;
1581         unsigned long flags;
1582         int retval = -EBUSY;
1583         __be32 *next_config_rom;
1584         dma_addr_t uninitialized_var(next_config_rom_bus);
1585
1586         ohci = fw_ohci(card);
1587
1588         /*
1589          * When the OHCI controller is enabled, the config rom update
1590          * mechanism is a bit tricky, but easy enough to use.  See
1591          * section 5.5.6 in the OHCI specification.
1592          *
1593          * The OHCI controller caches the new config rom address in a
1594          * shadow register (ConfigROMmapNext) and needs a bus reset
1595          * for the changes to take place.  When the bus reset is
1596          * detected, the controller loads the new values for the
1597          * ConfigRomHeader and BusOptions registers from the specified
1598          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1599          * shadow register. All automatically and atomically.
1600          *
1601          * Now, there's a twist to this story.  The automatic load of
1602          * ConfigRomHeader and BusOptions doesn't honor the
1603          * noByteSwapData bit, so with a be32 config rom, the
1604          * controller will load be32 values in to these registers
1605          * during the atomic update, even on litte endian
1606          * architectures.  The workaround we use is to put a 0 in the
1607          * header quadlet; 0 is endian agnostic and means that the
1608          * config rom isn't ready yet.  In the bus reset tasklet we
1609          * then set up the real values for the two registers.
1610          *
1611          * We use ohci->lock to avoid racing with the code that sets
1612          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1613          */
1614
1615         next_config_rom =
1616                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1617                                    &next_config_rom_bus, GFP_KERNEL);
1618         if (next_config_rom == NULL)
1619                 return -ENOMEM;
1620
1621         spin_lock_irqsave(&ohci->lock, flags);
1622
1623         if (ohci->next_config_rom == NULL) {
1624                 ohci->next_config_rom = next_config_rom;
1625                 ohci->next_config_rom_bus = next_config_rom_bus;
1626
1627                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1628                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1629                                   length * 4);
1630
1631                 ohci->next_header = config_rom[0];
1632                 ohci->next_config_rom[0] = 0;
1633
1634                 reg_write(ohci, OHCI1394_ConfigROMmap,
1635                           ohci->next_config_rom_bus);
1636                 retval = 0;
1637         }
1638
1639         spin_unlock_irqrestore(&ohci->lock, flags);
1640
1641         /*
1642          * Now initiate a bus reset to have the changes take
1643          * effect. We clean up the old config rom memory and DMA
1644          * mappings in the bus reset tasklet, since the OHCI
1645          * controller could need to access it before the bus reset
1646          * takes effect.
1647          */
1648         if (retval == 0)
1649                 fw_core_initiate_bus_reset(&ohci->card, 1);
1650         else
1651                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1652                                   next_config_rom, next_config_rom_bus);
1653
1654         return retval;
1655 }
1656
1657 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1658 {
1659         struct fw_ohci *ohci = fw_ohci(card);
1660
1661         at_context_transmit(&ohci->at_request_ctx, packet);
1662 }
1663
1664 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1665 {
1666         struct fw_ohci *ohci = fw_ohci(card);
1667
1668         at_context_transmit(&ohci->at_response_ctx, packet);
1669 }
1670
1671 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1672 {
1673         struct fw_ohci *ohci = fw_ohci(card);
1674         struct context *ctx = &ohci->at_request_ctx;
1675         struct driver_data *driver_data = packet->driver_data;
1676         int retval = -ENOENT;
1677
1678         tasklet_disable(&ctx->tasklet);
1679
1680         if (packet->ack != 0)
1681                 goto out;
1682
1683         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1684         driver_data->packet = NULL;
1685         packet->ack = RCODE_CANCELLED;
1686         packet->callback(packet, &ohci->card, packet->ack);
1687         retval = 0;
1688
1689  out:
1690         tasklet_enable(&ctx->tasklet);
1691
1692         return retval;
1693 }
1694
1695 static int
1696 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1697 {
1698 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1699         return 0;
1700 #else
1701         struct fw_ohci *ohci = fw_ohci(card);
1702         unsigned long flags;
1703         int n, retval = 0;
1704
1705         /*
1706          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1707          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1708          */
1709
1710         spin_lock_irqsave(&ohci->lock, flags);
1711
1712         if (ohci->generation != generation) {
1713                 retval = -ESTALE;
1714                 goto out;
1715         }
1716
1717         /*
1718          * Note, if the node ID contains a non-local bus ID, physical DMA is
1719          * enabled for _all_ nodes on remote buses.
1720          */
1721
1722         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1723         if (n < 32)
1724                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1725         else
1726                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1727
1728         flush_writes(ohci);
1729  out:
1730         spin_unlock_irqrestore(&ohci->lock, flags);
1731         return retval;
1732 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1733 }
1734
1735 static u64
1736 ohci_get_bus_time(struct fw_card *card)
1737 {
1738         struct fw_ohci *ohci = fw_ohci(card);
1739         u32 cycle_time;
1740         u64 bus_time;
1741
1742         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1743         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1744
1745         return bus_time;
1746 }
1747
1748 static int handle_ir_dualbuffer_packet(struct context *context,
1749                                        struct descriptor *d,
1750                                        struct descriptor *last)
1751 {
1752         struct iso_context *ctx =
1753                 container_of(context, struct iso_context, context);
1754         struct db_descriptor *db = (struct db_descriptor *) d;
1755         __le32 *ir_header;
1756         size_t header_length;
1757         void *p, *end;
1758         int i;
1759
1760         if (db->first_res_count != 0 && db->second_res_count != 0) {
1761                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1762                         /* This descriptor isn't done yet, stop iteration. */
1763                         return 0;
1764                 }
1765                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1766         }
1767
1768         header_length = le16_to_cpu(db->first_req_count) -
1769                 le16_to_cpu(db->first_res_count);
1770
1771         i = ctx->header_length;
1772         p = db + 1;
1773         end = p + header_length;
1774         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1775                 /*
1776                  * The iso header is byteswapped to little endian by
1777                  * the controller, but the remaining header quadlets
1778                  * are big endian.  We want to present all the headers
1779                  * as big endian, so we have to swap the first
1780                  * quadlet.
1781                  */
1782                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1783                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1784                 i += ctx->base.header_size;
1785                 ctx->excess_bytes +=
1786                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1787                 p += ctx->base.header_size + 4;
1788         }
1789         ctx->header_length = i;
1790
1791         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1792                 le16_to_cpu(db->second_res_count);
1793
1794         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1795                 ir_header = (__le32 *) (db + 1);
1796                 ctx->base.callback(&ctx->base,
1797                                    le32_to_cpu(ir_header[0]) & 0xffff,
1798                                    ctx->header_length, ctx->header,
1799                                    ctx->base.callback_data);
1800                 ctx->header_length = 0;
1801         }
1802
1803         return 1;
1804 }
1805
1806 static int handle_ir_packet_per_buffer(struct context *context,
1807                                        struct descriptor *d,
1808                                        struct descriptor *last)
1809 {
1810         struct iso_context *ctx =
1811                 container_of(context, struct iso_context, context);
1812         struct descriptor *pd;
1813         __le32 *ir_header;
1814         void *p;
1815         int i;
1816
1817         for (pd = d; pd <= last; pd++) {
1818                 if (pd->transfer_status)
1819                         break;
1820         }
1821         if (pd > last)
1822                 /* Descriptor(s) not done yet, stop iteration */
1823                 return 0;
1824
1825         i   = ctx->header_length;
1826         p   = last + 1;
1827
1828         if (ctx->base.header_size > 0 &&
1829                         i + ctx->base.header_size <= PAGE_SIZE) {
1830                 /*
1831                  * The iso header is byteswapped to little endian by
1832                  * the controller, but the remaining header quadlets
1833                  * are big endian.  We want to present all the headers
1834                  * as big endian, so we have to swap the first quadlet.
1835                  */
1836                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1837                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1838                 ctx->header_length += ctx->base.header_size;
1839         }
1840
1841         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1842                 ir_header = (__le32 *) p;
1843                 ctx->base.callback(&ctx->base,
1844                                    le32_to_cpu(ir_header[0]) & 0xffff,
1845                                    ctx->header_length, ctx->header,
1846                                    ctx->base.callback_data);
1847                 ctx->header_length = 0;
1848         }
1849
1850         return 1;
1851 }
1852
1853 static int handle_it_packet(struct context *context,
1854                             struct descriptor *d,
1855                             struct descriptor *last)
1856 {
1857         struct iso_context *ctx =
1858                 container_of(context, struct iso_context, context);
1859
1860         if (last->transfer_status == 0)
1861                 /* This descriptor isn't done yet, stop iteration. */
1862                 return 0;
1863
1864         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1865                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1866                                    0, NULL, ctx->base.callback_data);
1867
1868         return 1;
1869 }
1870
1871 static struct fw_iso_context *
1872 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1873 {
1874         struct fw_ohci *ohci = fw_ohci(card);
1875         struct iso_context *ctx, *list;
1876         descriptor_callback_t callback;
1877         u32 *mask, regs;
1878         unsigned long flags;
1879         int index, retval = -ENOMEM;
1880
1881         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1882                 mask = &ohci->it_context_mask;
1883                 list = ohci->it_context_list;
1884                 callback = handle_it_packet;
1885         } else {
1886                 mask = &ohci->ir_context_mask;
1887                 list = ohci->ir_context_list;
1888                 if (ohci->version >= OHCI_VERSION_1_1)
1889                         callback = handle_ir_dualbuffer_packet;
1890                 else
1891                         callback = handle_ir_packet_per_buffer;
1892         }
1893
1894         spin_lock_irqsave(&ohci->lock, flags);
1895         index = ffs(*mask) - 1;
1896         if (index >= 0)
1897                 *mask &= ~(1 << index);
1898         spin_unlock_irqrestore(&ohci->lock, flags);
1899
1900         if (index < 0)
1901                 return ERR_PTR(-EBUSY);
1902
1903         if (type == FW_ISO_CONTEXT_TRANSMIT)
1904                 regs = OHCI1394_IsoXmitContextBase(index);
1905         else
1906                 regs = OHCI1394_IsoRcvContextBase(index);
1907
1908         ctx = &list[index];
1909         memset(ctx, 0, sizeof(*ctx));
1910         ctx->header_length = 0;
1911         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1912         if (ctx->header == NULL)
1913                 goto out;
1914
1915         retval = context_init(&ctx->context, ohci, regs, callback);
1916         if (retval < 0)
1917                 goto out_with_header;
1918
1919         return &ctx->base;
1920
1921  out_with_header:
1922         free_page((unsigned long)ctx->header);
1923  out:
1924         spin_lock_irqsave(&ohci->lock, flags);
1925         *mask |= 1 << index;
1926         spin_unlock_irqrestore(&ohci->lock, flags);
1927
1928         return ERR_PTR(retval);
1929 }
1930
1931 static int ohci_start_iso(struct fw_iso_context *base,
1932                           s32 cycle, u32 sync, u32 tags)
1933 {
1934         struct iso_context *ctx = container_of(base, struct iso_context, base);
1935         struct fw_ohci *ohci = ctx->context.ohci;
1936         u32 control, match;
1937         int index;
1938
1939         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1940                 index = ctx - ohci->it_context_list;
1941                 match = 0;
1942                 if (cycle >= 0)
1943                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1944                                 (cycle & 0x7fff) << 16;
1945
1946                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1947                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1948                 context_run(&ctx->context, match);
1949         } else {
1950                 index = ctx - ohci->ir_context_list;
1951                 control = IR_CONTEXT_ISOCH_HEADER;
1952                 if (ohci->version >= OHCI_VERSION_1_1)
1953                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1954                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1955                 if (cycle >= 0) {
1956                         match |= (cycle & 0x07fff) << 12;
1957                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1958                 }
1959
1960                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1961                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1962                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1963                 context_run(&ctx->context, control);
1964         }
1965
1966         return 0;
1967 }
1968
1969 static int ohci_stop_iso(struct fw_iso_context *base)
1970 {
1971         struct fw_ohci *ohci = fw_ohci(base->card);
1972         struct iso_context *ctx = container_of(base, struct iso_context, base);
1973         int index;
1974
1975         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1976                 index = ctx - ohci->it_context_list;
1977                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1978         } else {
1979                 index = ctx - ohci->ir_context_list;
1980                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1981         }
1982         flush_writes(ohci);
1983         context_stop(&ctx->context);
1984
1985         return 0;
1986 }
1987
1988 static void ohci_free_iso_context(struct fw_iso_context *base)
1989 {
1990         struct fw_ohci *ohci = fw_ohci(base->card);
1991         struct iso_context *ctx = container_of(base, struct iso_context, base);
1992         unsigned long flags;
1993         int index;
1994
1995         ohci_stop_iso(base);
1996         context_release(&ctx->context);
1997         free_page((unsigned long)ctx->header);
1998
1999         spin_lock_irqsave(&ohci->lock, flags);
2000
2001         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2002                 index = ctx - ohci->it_context_list;
2003                 ohci->it_context_mask |= 1 << index;
2004         } else {
2005                 index = ctx - ohci->ir_context_list;
2006                 ohci->ir_context_mask |= 1 << index;
2007         }
2008
2009         spin_unlock_irqrestore(&ohci->lock, flags);
2010 }
2011
2012 static int
2013 ohci_queue_iso_transmit(struct fw_iso_context *base,
2014                         struct fw_iso_packet *packet,
2015                         struct fw_iso_buffer *buffer,
2016                         unsigned long payload)
2017 {
2018         struct iso_context *ctx = container_of(base, struct iso_context, base);
2019         struct descriptor *d, *last, *pd;
2020         struct fw_iso_packet *p;
2021         __le32 *header;
2022         dma_addr_t d_bus, page_bus;
2023         u32 z, header_z, payload_z, irq;
2024         u32 payload_index, payload_end_index, next_page_index;
2025         int page, end_page, i, length, offset;
2026
2027         /*
2028          * FIXME: Cycle lost behavior should be configurable: lose
2029          * packet, retransmit or terminate..
2030          */
2031
2032         p = packet;
2033         payload_index = payload;
2034
2035         if (p->skip)
2036                 z = 1;
2037         else
2038                 z = 2;
2039         if (p->header_length > 0)
2040                 z++;
2041
2042         /* Determine the first page the payload isn't contained in. */
2043         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2044         if (p->payload_length > 0)
2045                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2046         else
2047                 payload_z = 0;
2048
2049         z += payload_z;
2050
2051         /* Get header size in number of descriptors. */
2052         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2053
2054         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2055         if (d == NULL)
2056                 return -ENOMEM;
2057
2058         if (!p->skip) {
2059                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2060                 d[0].req_count = cpu_to_le16(8);
2061
2062                 header = (__le32 *) &d[1];
2063                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2064                                         IT_HEADER_TAG(p->tag) |
2065                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2066                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2067                                         IT_HEADER_SPEED(ctx->base.speed));
2068                 header[1] =
2069                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2070                                                           p->payload_length));
2071         }
2072
2073         if (p->header_length > 0) {
2074                 d[2].req_count    = cpu_to_le16(p->header_length);
2075                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2076                 memcpy(&d[z], p->header, p->header_length);
2077         }
2078
2079         pd = d + z - payload_z;
2080         payload_end_index = payload_index + p->payload_length;
2081         for (i = 0; i < payload_z; i++) {
2082                 page               = payload_index >> PAGE_SHIFT;
2083                 offset             = payload_index & ~PAGE_MASK;
2084                 next_page_index    = (page + 1) << PAGE_SHIFT;
2085                 length             =
2086                         min(next_page_index, payload_end_index) - payload_index;
2087                 pd[i].req_count    = cpu_to_le16(length);
2088
2089                 page_bus = page_private(buffer->pages[page]);
2090                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2091
2092                 payload_index += length;
2093         }
2094
2095         if (p->interrupt)
2096                 irq = DESCRIPTOR_IRQ_ALWAYS;
2097         else
2098                 irq = DESCRIPTOR_NO_IRQ;
2099
2100         last = z == 2 ? d : d + z - 1;
2101         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2102                                      DESCRIPTOR_STATUS |
2103                                      DESCRIPTOR_BRANCH_ALWAYS |
2104                                      irq);
2105
2106         context_append(&ctx->context, d, z, header_z);
2107
2108         return 0;
2109 }
2110
2111 static int
2112 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2113                                   struct fw_iso_packet *packet,
2114                                   struct fw_iso_buffer *buffer,
2115                                   unsigned long payload)
2116 {
2117         struct iso_context *ctx = container_of(base, struct iso_context, base);
2118         struct db_descriptor *db = NULL;
2119         struct descriptor *d;
2120         struct fw_iso_packet *p;
2121         dma_addr_t d_bus, page_bus;
2122         u32 z, header_z, length, rest;
2123         int page, offset, packet_count, header_size;
2124
2125         /*
2126          * FIXME: Cycle lost behavior should be configurable: lose
2127          * packet, retransmit or terminate..
2128          */
2129
2130         p = packet;
2131         z = 2;
2132
2133         /*
2134          * The OHCI controller puts the status word in the header
2135          * buffer too, so we need 4 extra bytes per packet.
2136          */
2137         packet_count = p->header_length / ctx->base.header_size;
2138         header_size = packet_count * (ctx->base.header_size + 4);
2139
2140         /* Get header size in number of descriptors. */
2141         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2142         page     = payload >> PAGE_SHIFT;
2143         offset   = payload & ~PAGE_MASK;
2144         rest     = p->payload_length;
2145
2146         /* FIXME: make packet-per-buffer/dual-buffer a context option */
2147         while (rest > 0) {
2148                 d = context_get_descriptors(&ctx->context,
2149                                             z + header_z, &d_bus);
2150                 if (d == NULL)
2151                         return -ENOMEM;
2152
2153                 db = (struct db_descriptor *) d;
2154                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2155                                           DESCRIPTOR_BRANCH_ALWAYS);
2156                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2157                 if (p->skip && rest == p->payload_length) {
2158                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2159                         db->first_req_count = db->first_size;
2160                 } else {
2161                         db->first_req_count = cpu_to_le16(header_size);
2162                 }
2163                 db->first_res_count = db->first_req_count;
2164                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2165
2166                 if (p->skip && rest == p->payload_length)
2167                         length = 4;
2168                 else if (offset + rest < PAGE_SIZE)
2169                         length = rest;
2170                 else
2171                         length = PAGE_SIZE - offset;
2172
2173                 db->second_req_count = cpu_to_le16(length);
2174                 db->second_res_count = db->second_req_count;
2175                 page_bus = page_private(buffer->pages[page]);
2176                 db->second_buffer = cpu_to_le32(page_bus + offset);
2177
2178                 if (p->interrupt && length == rest)
2179                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2180
2181                 context_append(&ctx->context, d, z, header_z);
2182                 offset = (offset + length) & ~PAGE_MASK;
2183                 rest -= length;
2184                 if (offset == 0)
2185                         page++;
2186         }
2187
2188         return 0;
2189 }
2190
2191 static int
2192 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2193                                          struct fw_iso_packet *packet,
2194                                          struct fw_iso_buffer *buffer,
2195                                          unsigned long payload)
2196 {
2197         struct iso_context *ctx = container_of(base, struct iso_context, base);
2198         struct descriptor *d = NULL, *pd = NULL;
2199         struct fw_iso_packet *p = packet;
2200         dma_addr_t d_bus, page_bus;
2201         u32 z, header_z, rest;
2202         int i, j, length;
2203         int page, offset, packet_count, header_size, payload_per_buffer;
2204
2205         /*
2206          * The OHCI controller puts the status word in the
2207          * buffer too, so we need 4 extra bytes per packet.
2208          */
2209         packet_count = p->header_length / ctx->base.header_size;
2210         header_size  = ctx->base.header_size + 4;
2211
2212         /* Get header size in number of descriptors. */
2213         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2214         page     = payload >> PAGE_SHIFT;
2215         offset   = payload & ~PAGE_MASK;
2216         payload_per_buffer = p->payload_length / packet_count;
2217
2218         for (i = 0; i < packet_count; i++) {
2219                 /* d points to the header descriptor */
2220                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2221                 d = context_get_descriptors(&ctx->context,
2222                                 z + header_z, &d_bus);
2223                 if (d == NULL)
2224                         return -ENOMEM;
2225
2226                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2227                                               DESCRIPTOR_INPUT_MORE);
2228                 if (p->skip && i == 0)
2229                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2230                 d->req_count    = cpu_to_le16(header_size);
2231                 d->res_count    = d->req_count;
2232                 d->transfer_status = 0;
2233                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2234
2235                 rest = payload_per_buffer;
2236                 for (j = 1; j < z; j++) {
2237                         pd = d + j;
2238                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2239                                                   DESCRIPTOR_INPUT_MORE);
2240
2241                         if (offset + rest < PAGE_SIZE)
2242                                 length = rest;
2243                         else
2244                                 length = PAGE_SIZE - offset;
2245                         pd->req_count = cpu_to_le16(length);
2246                         pd->res_count = pd->req_count;
2247                         pd->transfer_status = 0;
2248
2249                         page_bus = page_private(buffer->pages[page]);
2250                         pd->data_address = cpu_to_le32(page_bus + offset);
2251
2252                         offset = (offset + length) & ~PAGE_MASK;
2253                         rest -= length;
2254                         if (offset == 0)
2255                                 page++;
2256                 }
2257                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2258                                           DESCRIPTOR_INPUT_LAST |
2259                                           DESCRIPTOR_BRANCH_ALWAYS);
2260                 if (p->interrupt && i == packet_count - 1)
2261                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2262
2263                 context_append(&ctx->context, d, z, header_z);
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int
2270 ohci_queue_iso(struct fw_iso_context *base,
2271                struct fw_iso_packet *packet,
2272                struct fw_iso_buffer *buffer,
2273                unsigned long payload)
2274 {
2275         struct iso_context *ctx = container_of(base, struct iso_context, base);
2276         unsigned long flags;
2277         int retval;
2278
2279         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2280         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2281                 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2282         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
2283                 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2284                                                          buffer, payload);
2285         else
2286                 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2287                                                                 buffer,
2288                                                                 payload);
2289         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2290
2291         return retval;
2292 }
2293
2294 static const struct fw_card_driver ohci_driver = {
2295         .enable                 = ohci_enable,
2296         .update_phy_reg         = ohci_update_phy_reg,
2297         .set_config_rom         = ohci_set_config_rom,
2298         .send_request           = ohci_send_request,
2299         .send_response          = ohci_send_response,
2300         .cancel_packet          = ohci_cancel_packet,
2301         .enable_phys_dma        = ohci_enable_phys_dma,
2302         .get_bus_time           = ohci_get_bus_time,
2303
2304         .allocate_iso_context   = ohci_allocate_iso_context,
2305         .free_iso_context       = ohci_free_iso_context,
2306         .queue_iso              = ohci_queue_iso,
2307         .start_iso              = ohci_start_iso,
2308         .stop_iso               = ohci_stop_iso,
2309 };
2310
2311 #ifdef CONFIG_PPC_PMAC
2312 static void ohci_pmac_on(struct pci_dev *dev)
2313 {
2314         if (machine_is(powermac)) {
2315                 struct device_node *ofn = pci_device_to_OF_node(dev);
2316
2317                 if (ofn) {
2318                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2319                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2320                 }
2321         }
2322 }
2323
2324 static void ohci_pmac_off(struct pci_dev *dev)
2325 {
2326         if (machine_is(powermac)) {
2327                 struct device_node *ofn = pci_device_to_OF_node(dev);
2328
2329                 if (ofn) {
2330                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2331                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2332                 }
2333         }
2334 }
2335 #else
2336 #define ohci_pmac_on(dev)
2337 #define ohci_pmac_off(dev)
2338 #endif /* CONFIG_PPC_PMAC */
2339
2340 static int __devinit
2341 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2342 {
2343         struct fw_ohci *ohci;
2344         u32 bus_options, max_receive, link_speed;
2345         u64 guid;
2346         int err;
2347         size_t size;
2348
2349         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2350         if (ohci == NULL) {
2351                 fw_error("Could not malloc fw_ohci data.\n");
2352                 return -ENOMEM;
2353         }
2354
2355         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2356
2357         ohci_pmac_on(dev);
2358
2359         err = pci_enable_device(dev);
2360         if (err) {
2361                 fw_error("Failed to enable OHCI hardware.\n");
2362                 goto fail_free;
2363         }
2364
2365         pci_set_master(dev);
2366         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2367         pci_set_drvdata(dev, ohci);
2368
2369 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2370         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2371                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2372 #endif
2373         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2374
2375         spin_lock_init(&ohci->lock);
2376
2377         tasklet_init(&ohci->bus_reset_tasklet,
2378                      bus_reset_tasklet, (unsigned long)ohci);
2379
2380         err = pci_request_region(dev, 0, ohci_driver_name);
2381         if (err) {
2382                 fw_error("MMIO resource unavailable\n");
2383                 goto fail_disable;
2384         }
2385
2386         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2387         if (ohci->registers == NULL) {
2388                 fw_error("Failed to remap registers\n");
2389                 err = -ENXIO;
2390                 goto fail_iomem;
2391         }
2392
2393         ar_context_init(&ohci->ar_request_ctx, ohci,
2394                         OHCI1394_AsReqRcvContextControlSet);
2395
2396         ar_context_init(&ohci->ar_response_ctx, ohci,
2397                         OHCI1394_AsRspRcvContextControlSet);
2398
2399         context_init(&ohci->at_request_ctx, ohci,
2400                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2401
2402         context_init(&ohci->at_response_ctx, ohci,
2403                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2404
2405         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2406         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2407         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2408         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2409         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2410
2411         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2412         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2413         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2414         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2415         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2416
2417         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2418                 fw_error("Out of memory for it/ir contexts.\n");
2419                 err = -ENOMEM;
2420                 goto fail_registers;
2421         }
2422
2423         /* self-id dma buffer allocation */
2424         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2425                                                SELF_ID_BUF_SIZE,
2426                                                &ohci->self_id_bus,
2427                                                GFP_KERNEL);
2428         if (ohci->self_id_cpu == NULL) {
2429                 fw_error("Out of memory for self ID buffer.\n");
2430                 err = -ENOMEM;
2431                 goto fail_registers;
2432         }
2433
2434         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2435         max_receive = (bus_options >> 12) & 0xf;
2436         link_speed = bus_options & 0x7;
2437         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2438                 reg_read(ohci, OHCI1394_GUIDLo);
2439
2440         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2441         if (err < 0)
2442                 goto fail_self_id;
2443
2444         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2445         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2446                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
2447         return 0;
2448
2449  fail_self_id:
2450         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2451                           ohci->self_id_cpu, ohci->self_id_bus);
2452  fail_registers:
2453         kfree(ohci->it_context_list);
2454         kfree(ohci->ir_context_list);
2455         pci_iounmap(dev, ohci->registers);
2456  fail_iomem:
2457         pci_release_region(dev, 0);
2458  fail_disable:
2459         pci_disable_device(dev);
2460  fail_free:
2461         kfree(&ohci->card);
2462         ohci_pmac_off(dev);
2463
2464         return err;
2465 }
2466
2467 static void pci_remove(struct pci_dev *dev)
2468 {
2469         struct fw_ohci *ohci;
2470
2471         ohci = pci_get_drvdata(dev);
2472         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2473         flush_writes(ohci);
2474         fw_core_remove_card(&ohci->card);
2475
2476         /*
2477          * FIXME: Fail all pending packets here, now that the upper
2478          * layers can't queue any more.
2479          */
2480
2481         software_reset(ohci);
2482         free_irq(dev->irq, ohci);
2483         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2484                           ohci->self_id_cpu, ohci->self_id_bus);
2485         kfree(ohci->it_context_list);
2486         kfree(ohci->ir_context_list);
2487         pci_iounmap(dev, ohci->registers);
2488         pci_release_region(dev, 0);
2489         pci_disable_device(dev);
2490         kfree(&ohci->card);
2491         ohci_pmac_off(dev);
2492
2493         fw_notify("Removed fw-ohci device.\n");
2494 }
2495
2496 #ifdef CONFIG_PM
2497 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2498 {
2499         struct fw_ohci *ohci = pci_get_drvdata(dev);
2500         int err;
2501
2502         software_reset(ohci);
2503         free_irq(dev->irq, ohci);
2504         err = pci_save_state(dev);
2505         if (err) {
2506                 fw_error("pci_save_state failed\n");
2507                 return err;
2508         }
2509         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2510         if (err)
2511                 fw_error("pci_set_power_state failed with %d\n", err);
2512         ohci_pmac_off(dev);
2513
2514         return 0;
2515 }
2516
2517 static int pci_resume(struct pci_dev *dev)
2518 {
2519         struct fw_ohci *ohci = pci_get_drvdata(dev);
2520         int err;
2521
2522         ohci_pmac_on(dev);
2523         pci_set_power_state(dev, PCI_D0);
2524         pci_restore_state(dev);
2525         err = pci_enable_device(dev);
2526         if (err) {
2527                 fw_error("pci_enable_device failed\n");
2528                 return err;
2529         }
2530
2531         return ohci_enable(&ohci->card, NULL, 0);
2532 }
2533 #endif
2534
2535 static struct pci_device_id pci_table[] = {
2536         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2537         { }
2538 };
2539
2540 MODULE_DEVICE_TABLE(pci, pci_table);
2541
2542 static struct pci_driver fw_ohci_pci_driver = {
2543         .name           = ohci_driver_name,
2544         .id_table       = pci_table,
2545         .probe          = pci_probe,
2546         .remove         = pci_remove,
2547 #ifdef CONFIG_PM
2548         .resume         = pci_resume,
2549         .suspend        = pci_suspend,
2550 #endif
2551 };
2552
2553 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2554 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2555 MODULE_LICENSE("GPL");
2556
2557 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2558 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2559 MODULE_ALIAS("ohci1394");
2560 #endif
2561
2562 static int __init fw_ohci_init(void)
2563 {
2564         return pci_register_driver(&fw_ohci_pci_driver);
2565 }
2566
2567 static void __exit fw_ohci_cleanup(void)
2568 {
2569         pci_unregister_driver(&fw_ohci_pci_driver);
2570 }
2571
2572 module_init(fw_ohci_init);
2573 module_exit(fw_ohci_cleanup);