drivers/edac/r82600_edac.c

   1 /*
   2  * Radisys 82600 Embedded chipset Memory Controller kernel module
   3  * (C) 2005 EADS Astrium
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
   8  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
   9  *
  10  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11  *
  12  * Written with reference to 82600 High Integration Dual PCI System
  13  * Controller Data Book:
  14  * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15  * references to this document given in []
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/pci_ids.h>
  22 #include <linux/slab.h>
  23 #include "edac_mc.h"
  24
  25 #define R82600_REVISION " Ver: 2.0.0 " __DATE__
  26
  27 #define r82600_printk(level, fmt, arg...) \
  28         edac_printk(level, "r82600", fmt, ##arg)
  29
  30 #define r82600_mc_printk(mci, level, fmt, arg...) \
  31         edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  32
  33 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  34  * supports up to four banks of memory. The four banks can support a mix of
  35  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  36  * each of which can be any size from 16MB to 512MB. Both registered (control
  37  * signals buffered) and unbuffered DIMM types are supported. Mixing of
  38  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  39  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  40  * the CPU bus, 66MHz, 100MHz or 133MHz."
  41  */
  42
  43 #define R82600_NR_CSROWS 4
  44 #define R82600_NR_CHANS  1
  45 #define R82600_NR_DIMMS  4
  46
  47 #define R82600_BRIDGE_ID  0x8200
  48
  49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  50 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
  51                                  * all bits are R/W
  52                                  *
  53                                  * 7    SDRAM ISA Hole Enable
  54                                  * 6    Flash Page Mode Enable
  55                                  * 5    ECC Enable: 1=ECC 0=noECC
  56                                  * 4    DRAM DIMM Type: 1=
  57                                  * 3    BIOS Alias Disable
  58                                  * 2    SDRAM BIOS Flash Write Enable
  59                                  * 1:0  SDRAM Refresh Rate: 00=Disabled
  60                                  *          01=7.8usec (256Mbit SDRAMs)
  61                                  *          10=15.6us 11=125usec
  62                                  */
  63
  64 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
  65                                  * More SDRAM related control bits
  66                                  * all bits are R/W
  67                                  *
  68                                  * 15:8 Reserved.
  69                                  *
  70                                  * 7:5  Special SDRAM Mode Select
  71                                  *
  72                                  * 4    Force ECC
  73                                  *
  74                                  *        1=Drive ECC bits to 0 during
  75                                  *          write cycles (i.e. ECC test mode)
  76                                  *
  77                                  *        0=Normal ECC functioning
  78                                  *
  79                                  * 3    Enhanced Paging Enable
  80                                  *
  81                                  * 2    CAS# Latency 0=3clks 1=2clks
  82                                  *
  83                                  * 1    RAS# to CAS# Delay 0=3 1=2
  84                                  *
  85                                  * 0    RAS# Precharge     0=3 1=2
  86                                  */
  87
  88 #define R82600_EAP      0x80    /* ECC Error Address Pointer Register
  89                                  *
  90                                  * 31    Disable Hardware Scrubbing (RW)
  91                                  *        0=Scrub on corrected read
  92                                  *        1=Don't scrub on corrected read
  93                                  *
  94                                  * 30:12 Error Address Pointer (RO)
  95                                  *        Upper 19 bits of error address
  96                                  *
  97                                  * 11:4  Syndrome Bits (RO)
  98                                  *
  99                                  * 3     BSERR# on multibit error (RW)
 100                                  *        1=enable 0=disable
 101                                  *
 102                                  * 2     NMI on Single Bit Eror (RW)
 103                                  *        1=NMI triggered by SBE n.b. other
 104                                  *          prerequeists
 105                                  *        0=NMI not triggered
 106                                  *
 107                                  * 1     MBE (R/WC)
 108                                  *        read 1=MBE at EAP (see above)
 109                                  *        read 0=no MBE, or SBE occurred first
 110                                  *        write 1=Clear MBE status (must also
 111                                  *          clear SBE)
 112                                  *        write 0=NOP
 113                                  *
 114                                  * 1     SBE (R/WC)
 115                                  *        read 1=SBE at EAP (see above)
 116                                  *        read 0=no SBE, or MBE occurred first
 117                                  *        write 1=Clear SBE status (must also
 118                                  *          clear MBE)
 119                                  *        write 0=NOP
 120                                  */
 121
 122 #define R82600_DRBA     0x60    /* + 0x60..0x63 SDRAM Row Boundry Address
 123                                  *  Registers
 124                                  *
 125                                  * 7:0  Address lines 30:24 - upper limit of
 126                                  * each row [p57]
 127                                  */
 128
 129 struct r82600_error_info {
 130         u32 eapr;
 131 };
 132
 133 static unsigned int disable_hardware_scrub = 0;
 134
 135 static void r82600_get_error_info (struct mem_ctl_info *mci,
 136                 struct r82600_error_info *info)
 137 {
 138         struct pci_dev *pdev;
 139
 140         pdev = to_pci_dev(mci->dev);
 141         pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
 142
 143         if (info->eapr & BIT(0))
 144                 /* Clear error to allow next error to be reported [p.62] */
 145                 pci_write_bits32(pdev, R82600_EAP,
 146                                 ((u32) BIT(0) & (u32) BIT(1)),
 147                                 ((u32) BIT(0) & (u32) BIT(1)));
 148
 149         if (info->eapr & BIT(1))
 150                 /* Clear error to allow next error to be reported [p.62] */
 151                 pci_write_bits32(pdev, R82600_EAP,
 152                                 ((u32) BIT(0) & (u32) BIT(1)),
 153                                 ((u32) BIT(0) & (u32) BIT(1)));
 154 }
 155
 156 static int r82600_process_error_info (struct mem_ctl_info *mci,
 157                 struct r82600_error_info *info, int handle_errors)
 158 {
 159         int error_found;
 160         u32 eapaddr, page;
 161         u32 syndrome;
 162
 163         error_found = 0;
 164
 165         /* bits 30:12 store the upper 19 bits of the 32 bit error address */
 166         eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
 167         /* Syndrome in bits 11:4 [p.62]       */
 168         syndrome = (info->eapr >> 4) & 0xFF;
 169
 170         /* the R82600 reports at less than page *
 171          * granularity (upper 19 bits only)     */
 172         page = eapaddr >> PAGE_SHIFT;
 173
 174         if (info->eapr & BIT(0)) {  /* CE? */
 175                 error_found = 1;
 176
 177                 if (handle_errors)
 178                         edac_mc_handle_ce(mci, page, 0,  /* not avail */
 179                                         syndrome,
 180                                         edac_mc_find_csrow_by_page(mci, page),
 181                                         0,  /* channel */
 182                                         mci->ctl_name);
 183         }
 184
 185         if (info->eapr & BIT(1)) {  /* UE? */
 186                 error_found = 1;
 187
 188                 if (handle_errors)
 189                         /* 82600 doesn't give enough info */
 190                         edac_mc_handle_ue(mci, page, 0,
 191                                 edac_mc_find_csrow_by_page(mci, page),
 192                                 mci->ctl_name);
 193         }
 194
 195         return error_found;
 196 }
 197
 198 static void r82600_check(struct mem_ctl_info *mci)
 199 {
 200         struct r82600_error_info info;
 201
 202         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 203         r82600_get_error_info(mci, &info);
 204         r82600_process_error_info(mci, &info, 1);
 205 }
 206
 207 static inline int ecc_enabled(u8 dramcr)
 208 {
 209         return dramcr & BIT(5);
 210 }
 211
 212 static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 213                 u8 dramcr)
 214 {
 215         struct csrow_info *csrow;
 216         int index;
 217         u8 drbar;  /* SDRAM Row Boundry Address Register */
 218         u32 row_high_limit, row_high_limit_last;
 219         u32 reg_sdram, ecc_on, row_base;
 220
 221         ecc_on = ecc_enabled(dramcr);
 222         reg_sdram = dramcr & BIT(4);
 223         row_high_limit_last = 0;
 224
 225         for (index = 0; index < mci->nr_csrows; index++) {
 226                 csrow = &mci->csrows[index];
 227
 228                 /* find the DRAM Chip Select Base address and mask */
 229                 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
 230
 231                 debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
 232
 233                 row_high_limit = ((u32) drbar << 24);
 234 /*              row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
 235
 236                 debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
 237                         __func__, index, row_high_limit, row_high_limit_last);
 238
 239                 /* Empty row [p.57] */
 240                 if (row_high_limit == row_high_limit_last)
 241                         continue;
 242
 243                 row_base = row_high_limit_last;
 244
 245                 csrow->first_page = row_base >> PAGE_SHIFT;
 246                 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
 247                 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
 248                 /* Error address is top 19 bits - so granularity is      *
 249                  * 14 bits                                               */
 250                 csrow->grain = 1 << 14;
 251                 csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
 252                 /* FIXME - check that this is unknowable with this chipset */
 253                 csrow->dtype = DEV_UNKNOWN;
 254
 255                 /* Mode is global on 82600 */
 256                 csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
 257                 row_high_limit_last = row_high_limit;
 258         }
 259 }
 260
 261 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
 262 {
 263         struct mem_ctl_info *mci;
 264         u8 dramcr;
 265         u32 eapr;
 266         u32 scrub_disabled;
 267         u32 sdram_refresh_rate;
 268         struct r82600_error_info discard;
 269
 270         debugf0("%s()\n", __func__);
 271         pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
 272         pci_read_config_dword(pdev, R82600_EAP, &eapr);
 273         scrub_disabled = eapr & BIT(31);
 274         sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
 275         debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
 276                 sdram_refresh_rate);
 277         debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
 278         mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
 279
 280         if (mci == NULL)
 281                 return -ENOMEM;
 282
 283         debugf0("%s(): mci = %p\n", __func__, mci);
 284         mci->dev = &pdev->dev;
 285         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
 286         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 287         /* FIXME try to work out if the chip leads have been used for COM2
 288          * instead on this board? [MA6?] MAYBE:
 289          */
 290
 291         /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
 292          * EC bits are shared with the pins for COM2 (!), so if COM2  *
 293          * is enabled, we assume COM2 is wired up, and thus no EDAC   *
 294          * is possible.                                               */
 295         mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 296
 297         if (ecc_enabled(dramcr)) {
 298                 if (scrub_disabled)
 299                         debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
 300                                 "%#0x\n", __func__, mci, eapr);
 301         } else
 302                 mci->edac_cap = EDAC_FLAG_NONE;
 303
 304         mci->mod_name = EDAC_MOD_STR;
 305         mci->mod_ver = R82600_REVISION;
 306         mci->ctl_name = "R82600";
 307         mci->edac_check = r82600_check;
 308         mci->ctl_page_to_phys = NULL;
 309         r82600_init_csrows(mci, pdev, dramcr);
 310         r82600_get_error_info(mci, &discard);  /* clear counters */
 311
 312         /* Here we assume that we will never see multiple instances of this
 313          * type of memory controller.  The ID is therefore hardcoded to 0.
 314          */
 315         if (edac_mc_add_mc(mci,0)) {
 316                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 317                 goto fail;
 318         }
 319
 320         /* get this far and it's successful */
 321
 322         if (disable_hardware_scrub) {
 323                 debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
 324                         __func__);
 325                 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
 326         }
 327
 328         debugf3("%s(): success\n", __func__);
 329         return 0;
 330
 331 fail:
 332         edac_mc_free(mci);
 333         return -ENODEV;
 334 }
 335
 336 /* returns count (>= 0), or negative on error */
 337 static int __devinit r82600_init_one(struct pci_dev *pdev,
 338                 const struct pci_device_id *ent)
 339 {
 340         debugf0("%s()\n", __func__);
 341
 342         /* don't need to call pci_device_enable() */
 343         return r82600_probe1(pdev, ent->driver_data);
 344 }
 345
 346 static void __devexit r82600_remove_one(struct pci_dev *pdev)
 347 {
 348         struct mem_ctl_info *mci;
 349
 350         debugf0("%s()\n", __func__);
 351
 352         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 353                 return;
 354
 355         edac_mc_free(mci);
 356 }
 357
 358 static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
 359         {
 360                 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
 361         },
 362         {
 363                 0,
 364         }       /* 0 terminated list. */
 365 };
 366
 367 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
 368
 369 static struct pci_driver r82600_driver = {
 370         .name = EDAC_MOD_STR,
 371         .probe = r82600_init_one,
 372         .remove = __devexit_p(r82600_remove_one),
 373         .id_table = r82600_pci_tbl,
 374 };
 375
 376 static int __init r82600_init(void)
 377 {
 378         return pci_register_driver(&r82600_driver);
 379 }
 380
 381 static void __exit r82600_exit(void)
 382 {
 383         pci_unregister_driver(&r82600_driver);
 384 }
 385
 386 module_init(r82600_init);
 387 module_exit(r82600_exit);
 388
 389 MODULE_LICENSE("GPL");
 390 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
 391         "on behalf of EADS Astrium");
 392 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
 393
 394 module_param(disable_hardware_scrub, bool, 0644);
 395 MODULE_PARM_DESC(disable_hardware_scrub,
 396                  "If set, disable the chipset's automatic scrub for CEs");