1 /* Intel 7 core Memory Controller kernel module (Nehalem)
3 * This file may be distributed under the terms of the
4 * GNU General Public License version 2 only.
6 * Copyright (c) 2009 by:
7 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 * Red Hat Inc. http://www.redhat.com
11 * Forked and adapted from the i5400_edac driver
13 * Based on the following public Intel datasheets:
14 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
15 * Datasheet, Volume 2:
16 * http://download.intel.com/design/processor/datashts/320835.pdf
17 * Intel Xeon Processor 5500 Series Datasheet Volume 2
18 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
20 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/slab.h>
28 #include <linux/edac.h>
29 #include <linux/mmzone.h>
31 #include "edac_core.h"
35 * Alter this version for the module when modifications are made
37 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
38 #define EDAC_MOD_STR "i7core_edac"
40 /* HACK: temporary, just to enable all logs, for now */
42 #define debugf0(fmt, arg...) edac_printk(KERN_INFO, "i7core", fmt, ##arg)
47 #define i7core_printk(level, fmt, arg...) \
48 edac_printk(level, "i7core", fmt, ##arg)
50 #define i7core_mc_printk(mci, level, fmt, arg...) \
51 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
54 * i7core Memory Controller Registers
57 /* OFFSETS for Device 3 Function 0 */
59 #define MC_CONTROL 0x48
60 #define MC_STATUS 0x4c
61 #define MC_MAX_DOD 0x64
63 /* OFFSETS for Devices 4,5 and 6 Function 0 */
65 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
66 #define THREE_DIMMS_PRESENT (1 << 24)
67 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
68 #define QUAD_RANK_PRESENT (1 << 22)
69 #define REGISTERED_DIMM (1 << 15)
71 #define MC_CHANNEL_MAPPER 0x60
72 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
73 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
75 #define MC_CHANNEL_RANK_PRESENT 0x7c
76 #define RANK_PRESENT_MASK 0xffff
78 #define MC_CHANNEL_ADDR_MATCH 0xf0
79 #define MC_CHANNEL_ERROR_MASK 0xf8
80 #define MC_CHANNEL_ERROR_INJECT 0xfc
81 #define INJECT_ADDR_PARITY 0x10
82 #define INJECT_ECC 0x08
83 #define MASK_CACHELINE 0x06
84 #define MASK_FULL_CACHELINE 0x06
85 #define MASK_MSB32_CACHELINE 0x04
86 #define MASK_LSB32_CACHELINE 0x02
87 #define NO_MASK_CACHELINE 0x00
88 #define REPEAT_EN 0x01
90 /* OFFSETS for Devices 4,5 and 6 Function 1 */
91 #define MC_DOD_CH_DIMM0 0x48
92 #define MC_DOD_CH_DIMM1 0x4c
93 #define MC_DOD_CH_DIMM2 0x50
94 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
95 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
96 #define DIMM_PRESENT_MASK (1 << 9)
97 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
98 #define NUMBANK_MASK ((1 << 8) | (1 << 7))
99 #define NUMBANK(x) (((x) & NUMBANK_MASK) >> 7)
100 #define NUMRANK_MASK ((1 << 6) | (1 << 5))
101 #define NUMRANK(x) (((x) & NUMRANK_MASK) >> 5)
102 #define NUMROW_MASK ((1 << 4) | (1 << 3))
103 #define NUMROW(x) (((x) & NUMROW_MASK) >> 3)
104 #define NUMCOL_MASK 3
105 #define NUMCOL(x) ((x) & NUMCOL_MASK)
107 #define MC_RANK_PRESENT 0x7c
109 #define MC_SAG_CH_0 0x80
110 #define MC_SAG_CH_1 0x84
111 #define MC_SAG_CH_2 0x88
112 #define MC_SAG_CH_3 0x8c
113 #define MC_SAG_CH_4 0x90
114 #define MC_SAG_CH_5 0x94
115 #define MC_SAG_CH_6 0x98
116 #define MC_SAG_CH_7 0x9c
118 #define MC_RIR_LIMIT_CH_0 0x40
119 #define MC_RIR_LIMIT_CH_1 0x44
120 #define MC_RIR_LIMIT_CH_2 0x48
121 #define MC_RIR_LIMIT_CH_3 0x4C
122 #define MC_RIR_LIMIT_CH_4 0x50
123 #define MC_RIR_LIMIT_CH_5 0x54
124 #define MC_RIR_LIMIT_CH_6 0x58
125 #define MC_RIR_LIMIT_CH_7 0x5C
126 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
128 #define MC_RIR_WAY_CH 0x80
129 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
130 #define MC_RIR_WAY_RANK_MASK 0x7
137 #define NUM_MCR_FUNCS 4
138 #define NUM_CHAN_FUNCS 3
148 struct i7core_inject {
155 /* Error address mask */
156 int channel, dimm, rank, bank, page, col;
159 struct i7core_channel {
164 struct pci_id_descr {
168 struct pci_dev *pdev;
172 struct pci_dev *pci_mcr[NUM_MCR_FUNCS];
173 struct pci_dev *pci_ch[NUM_CHANS][NUM_CHAN_FUNCS];
174 struct i7core_info info;
175 struct i7core_inject inject;
176 struct i7core_channel channel[NUM_CHANS];
179 /* Device name and register DID (Device ID) */
180 struct i7core_dev_info {
181 const char *ctl_name; /* name for this device */
182 u16 fsb_mapping_errors; /* DID for the branchmap,control */
185 #define PCI_DESCR(device, function, device_id) \
187 .func = (function), \
188 .dev_id = (device_id)
190 struct pci_id_descr pci_devs[] = {
191 /* Memory controller */
192 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
193 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
194 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM is supported */
195 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
198 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
199 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
200 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
201 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
204 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
205 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
206 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
207 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
210 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
211 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
212 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
213 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
215 #define N_DEVS ARRAY_SIZE(pci_devs)
218 * pci_device_id table for which devices we are looking for
219 * This should match the first device at pci_devs table
221 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
222 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR)},
223 {0,} /* 0 terminated list. */
227 /* Table of devices attributes supported by this driver */
228 static const struct i7core_dev_info i7core_devs[] = {
230 .ctl_name = "i7 Core",
231 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
235 static struct edac_pci_ctl_info *i7core_pci;
237 /****************************************************************************
238 Anciliary status routines
239 ****************************************************************************/
241 /* MC_CONTROL bits */
242 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & 1 << (8 + ch))
243 #define ECCx8(pvt) ((pvt)->info.mc_control & 1 << 1)
246 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & 1 << 3)
247 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & 1 << ch)
249 /* MC_MAX_DOD read functions */
250 static inline int maxnumdimms(struct i7core_pvt *pvt)
252 return (pvt->info.max_dod & 0x3) + 1;
255 static inline int maxnumrank(struct i7core_pvt *pvt)
257 static int ranks[4] = { 1, 2, 4, -EINVAL };
259 return ranks[(pvt->info.max_dod >> 2) & 0x3];
262 static inline int maxnumbank(struct i7core_pvt *pvt)
264 static int banks[4] = { 4, 8, 16, -EINVAL };
266 return banks[(pvt->info.max_dod >> 4) & 0x3];
269 static inline int maxnumrow(struct i7core_pvt *pvt)
271 static int rows[8] = {
272 1 << 12, 1 << 13, 1 << 14, 1 << 15,
273 1 << 16, -EINVAL, -EINVAL, -EINVAL,
276 return rows[((pvt->info.max_dod >> 6) & 0x7)];
279 static inline int maxnumcol(struct i7core_pvt *pvt)
281 static int cols[8] = {
282 1 << 10, 1 << 11, 1 << 12, -EINVAL,
284 return cols[((pvt->info.max_dod >> 9) & 0x3) << 12];
288 /****************************************************************************
289 Memory check routines
290 ****************************************************************************/
291 static int get_dimm_config(struct mem_ctl_info *mci)
293 struct i7core_pvt *pvt = mci->pvt_info;
296 if (!pvt->pci_mcr[0])
299 /* Device 3 function 0 reads */
300 pci_read_config_dword(pvt->pci_mcr[0], MC_CONTROL,
301 &pvt->info.mc_control);
302 pci_read_config_dword(pvt->pci_mcr[0], MC_STATUS,
303 &pvt->info.mc_status);
304 pci_read_config_dword(pvt->pci_mcr[0], MC_MAX_DOD,
306 pci_read_config_dword(pvt->pci_mcr[0], MC_CHANNEL_MAPPER,
309 debugf0("MC control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
310 pvt->info.mc_control, pvt->info.mc_status,
311 pvt->info.max_dod, pvt->info.ch_map);
313 if (ECC_ENABLED(pvt))
314 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt)?8:4);
316 debugf0("ECC disabled\n");
318 /* FIXME: need to handle the error codes */
319 debugf0("DOD Maximum limits: DIMMS: %d, %d-ranked, %d-banked\n",
320 maxnumdimms(pvt), maxnumrank(pvt), maxnumbank(pvt));
321 debugf0("DOD Maximum rows x colums = 0x%x x 0x%x\n",
322 maxnumrow(pvt), maxnumcol(pvt));
324 debugf0("Memory channel configuration:\n");
326 for (i = 0; i < NUM_CHANS; i++) {
329 if (!CH_ACTIVE(pvt, i)) {
330 debugf0("Channel %i is not active\n", i);
333 if (CH_DISABLED(pvt, i)) {
334 debugf0("Channel %i is disabled\n", i);
338 /* Devices 4-6 function 0 */
339 pci_read_config_dword(pvt->pci_ch[i][0],
340 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
342 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT)? 4 : 2;
344 if (data & THREE_DIMMS_PRESENT)
345 pvt->channel[i].dimms = 3;
346 else if (data & SINGLE_QUAD_RANK_PRESENT)
347 pvt->channel[i].dimms = 1;
349 pvt->channel[i].dimms = 2;
351 debugf0("Ch%d (0x%08x): rd ch %d, wr ch %d, "
352 "%d ranks, %d %cDIMMs\n",
354 RDLCH(pvt->info.ch_map, i),
355 WRLCH(pvt->info.ch_map, i),
356 pvt->channel[i].ranks, pvt->channel[i].dimms,
357 (data & REGISTERED_DIMM)? 'R' : 'U' );
363 /****************************************************************************
364 Error insertion routines
365 ****************************************************************************/
367 /* The i7core has independent error injection features per channel.
368 However, to have a simpler code, we don't allow enabling error injection
369 on more than one channel.
370 Also, since a change at an inject parameter will be applied only at enable,
371 we're disabling error injection on all write calls to the sysfs nodes that
372 controls the error code injection.
374 static int disable_inject(struct mem_ctl_info *mci)
376 struct i7core_pvt *pvt = mci->pvt_info;
378 pvt->inject.enable = 0;
380 if (!pvt->pci_ch[pvt->inject.channel][0])
383 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
384 MC_CHANNEL_ERROR_MASK, 0);
390 * i7core inject inject.section
392 * accept and store error injection inject.section value
393 * bit 0 - refers to the lower 32-byte half cacheline
394 * bit 1 - refers to the upper 32-byte half cacheline
396 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
397 const char *data, size_t count)
399 struct i7core_pvt *pvt = mci->pvt_info;
403 if (pvt->inject.enable)
406 rc = strict_strtoul(data, 10, &value);
407 if ((rc < 0) || (value > 3))
410 pvt->inject.section = (u32) value;
414 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
417 struct i7core_pvt *pvt = mci->pvt_info;
418 return sprintf(data, "0x%08x\n", pvt->inject.section);
424 * accept and store error injection inject.section value
425 * bit 0 - repeat enable - Enable error repetition
426 * bit 1 - inject ECC error
427 * bit 2 - inject parity error
429 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
430 const char *data, size_t count)
432 struct i7core_pvt *pvt = mci->pvt_info;
436 if (pvt->inject.enable)
439 rc = strict_strtoul(data, 10, &value);
440 if ((rc < 0) || (value > 7))
443 pvt->inject.type = (u32) value;
447 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
450 struct i7core_pvt *pvt = mci->pvt_info;
451 return sprintf(data, "0x%08x\n", pvt->inject.type);
455 * i7core_inject_inject.eccmask_store
457 * The type of error (UE/CE) will depend on the inject.eccmask value:
458 * Any bits set to a 1 will flip the corresponding ECC bit
459 * Correctable errors can be injected by flipping 1 bit or the bits within
460 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
461 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
462 * uncorrectable error to be injected.
464 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
465 const char *data, size_t count)
467 struct i7core_pvt *pvt = mci->pvt_info;
471 if (pvt->inject.enable)
474 rc = strict_strtoul(data, 10, &value);
478 pvt->inject.eccmask = (u32) value;
482 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
485 struct i7core_pvt *pvt = mci->pvt_info;
486 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
492 * The type of error (UE/CE) will depend on the inject.eccmask value:
493 * Any bits set to a 1 will flip the corresponding ECC bit
494 * Correctable errors can be injected by flipping 1 bit or the bits within
495 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
496 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
497 * uncorrectable error to be injected.
499 static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
500 const char *data, size_t count)
502 struct i7core_pvt *pvt = mci->pvt_info;
507 if (pvt->inject.enable)
511 cmd = strsep((char **) &data, ":");
514 val = strsep((char **) &data, " \n\t");
518 if (!strcasecmp(val,"any"))
521 rc = strict_strtol(val, 10, &value);
522 if ((rc < 0) || (value < 0))
526 if (!strcasecmp(cmd,"channel")) {
528 pvt->inject.channel = value;
531 } else if (!strcasecmp(cmd,"dimm")) {
533 pvt->inject.dimm = value;
536 } else if (!strcasecmp(cmd,"rank")) {
538 pvt->inject.rank = value;
541 } else if (!strcasecmp(cmd,"bank")) {
543 pvt->inject.bank = value;
546 } else if (!strcasecmp(cmd,"page")) {
548 pvt->inject.page = value;
551 } else if (!strcasecmp(cmd,"col") ||
552 !strcasecmp(cmd,"column")) {
554 pvt->inject.col = value;
563 static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
566 struct i7core_pvt *pvt = mci->pvt_info;
567 char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];
569 if (pvt->inject.channel < 0)
570 sprintf(channel, "any");
572 sprintf(channel, "%d", pvt->inject.channel);
573 if (pvt->inject.dimm < 0)
574 sprintf(dimm, "any");
576 sprintf(dimm, "%d", pvt->inject.dimm);
577 if (pvt->inject.bank < 0)
578 sprintf(bank, "any");
580 sprintf(bank, "%d", pvt->inject.bank);
581 if (pvt->inject.rank < 0)
582 sprintf(rank, "any");
584 sprintf(rank, "%d", pvt->inject.rank);
585 if (pvt->inject.page < 0)
586 sprintf(page, "any");
588 sprintf(page, "0x%04x", pvt->inject.page);
589 if (pvt->inject.col < 0)
592 sprintf(col, "0x%04x", pvt->inject.col);
594 return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
595 "rank: %s\npage: %s\ncolumn: %s\n",
596 channel, dimm, bank, rank, page, col);
600 * This routine prepares the Memory Controller for error injection.
601 * The error will be injected when some process tries to write to the
602 * memory that matches the given criteria.
603 * The criteria can be set in terms of a mask where dimm, rank, bank, page
604 * and col can be specified.
605 * A -1 value for any of the mask items will make the MCU to ignore
606 * that matching criteria for error injection.
608 * It should be noticed that the error will only happen after a write operation
609 * on a memory that matches the condition. if REPEAT_EN is not enabled at
610 * inject mask, then it will produce just one error. Otherwise, it will repeat
611 * until the injectmask would be cleaned.
613 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
614 * is reliable enough to check if the MC is using the
615 * three channels. However, this is not clear at the datasheet.
617 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
618 const char *data, size_t count)
620 struct i7core_pvt *pvt = mci->pvt_info;
626 if (!pvt->pci_ch[pvt->inject.channel][0])
629 rc = strict_strtoul(data, 10, &enable);
634 pvt->inject.enable = 1;
640 /* Sets pvt->inject.dimm mask */
641 if (pvt->inject.dimm < 0)
644 if (pvt->channel[pvt->inject.channel].dimms > 2)
645 mask |= (pvt->inject.dimm & 0x3l) << 35;
647 mask |= (pvt->inject.dimm & 0x1l) << 36;
650 /* Sets pvt->inject.rank mask */
651 if (pvt->inject.rank < 0)
654 if (pvt->channel[pvt->inject.channel].dimms > 2)
655 mask |= (pvt->inject.rank & 0x1l) << 34;
657 mask |= (pvt->inject.rank & 0x3l) << 34;
660 /* Sets pvt->inject.bank mask */
661 if (pvt->inject.bank < 0)
664 mask |= (pvt->inject.bank & 0x15l) << 30;
666 /* Sets pvt->inject.page mask */
667 if (pvt->inject.page < 0)
670 mask |= (pvt->inject.page & 0xffffl) << 14;
672 /* Sets pvt->inject.column mask */
673 if (pvt->inject.col < 0)
676 mask |= (pvt->inject.col & 0x3fffl);
678 pci_write_config_qword(pvt->pci_ch[pvt->inject.channel][0],
679 MC_CHANNEL_ADDR_MATCH, mask);
681 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
682 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
686 * bits 1-2: MASK_HALF_CACHELINE
688 * bit 4: INJECT_ADDR_PARITY
691 injectmask = (pvt->inject.type & 1) &&
692 (pvt->inject.section & 0x3) << 1 &&
693 (pvt->inject.type & 0x6) << (3 - 1);
695 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
696 MC_CHANNEL_ERROR_MASK, injectmask);
699 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
700 mask, pvt->inject.eccmask, injectmask);
705 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
708 struct i7core_pvt *pvt = mci->pvt_info;
709 return sprintf(data, "%d\n", pvt->inject.enable);
715 static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
719 .name = "inject_section",
720 .mode = (S_IRUGO | S_IWUSR)
722 .show = i7core_inject_section_show,
723 .store = i7core_inject_section_store,
726 .name = "inject_type",
727 .mode = (S_IRUGO | S_IWUSR)
729 .show = i7core_inject_type_show,
730 .store = i7core_inject_type_store,
733 .name = "inject_eccmask",
734 .mode = (S_IRUGO | S_IWUSR)
736 .show = i7core_inject_eccmask_show,
737 .store = i7core_inject_eccmask_store,
740 .name = "inject_addrmatch",
741 .mode = (S_IRUGO | S_IWUSR)
743 .show = i7core_inject_addrmatch_show,
744 .store = i7core_inject_addrmatch_store,
747 .name = "inject_enable",
748 .mode = (S_IRUGO | S_IWUSR)
750 .show = i7core_inject_enable_show,
751 .store = i7core_inject_enable_store,
755 /****************************************************************************
756 Device initialization routines: put/get, init/exit
757 ****************************************************************************/
760 * i7core_put_devices 'put' all the devices that we have
763 static void i7core_put_devices(void)
767 for (i = 0; i < N_DEVS; i++)
768 pci_dev_put(pci_devs[i].pdev);
772 * i7core_get_devices Find and perform 'get' operation on the MCH's
773 * device/functions we want to reference for this driver
775 * Need to 'get' device 16 func 1 and func 2
777 static int i7core_get_devices(struct mem_ctl_info *mci, struct pci_dev *mcidev)
779 struct i7core_pvt *pvt = mci->pvt_info;
781 struct pci_dev *pdev = NULL;
784 memset(pvt, 0, sizeof(*pvt));
786 for (i = 0; i < N_DEVS; i++) {
787 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
788 pci_devs[i].dev_id, NULL);
790 /* End of list, leave */
791 i7core_printk(KERN_ERR,
792 "Device not found: PCI ID %04x:%04x "
793 "(dev %d, func %d)\n",
794 PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
795 pci_devs[i].dev,pci_devs[i].func);
796 if ((pci_devs[i].dev == 3) && (pci_devs[i].func == 2))
797 continue; /* Only on chips with RDIMMs */
799 i7core_put_devices();
801 pci_devs[i].pdev = pdev;
803 rc = pci_enable_device(pdev);
805 i7core_printk(KERN_ERR,
806 "Couldn't enable PCI ID %04x:%04x "
807 "(dev %d, func %d)\n",
808 PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
809 pci_devs[i].dev, pci_devs[i].func);
810 i7core_put_devices();
814 if (PCI_FUNC(pdev->devfn) != pci_devs[i].func) {
815 i7core_printk(KERN_ERR,
816 "Device PCI ID %04x:%04x "
817 "has function %d instead of %d\n",
818 PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
819 PCI_FUNC(pdev->devfn), pci_devs[i].func);
820 i7core_put_devices();
824 i7core_printk(KERN_INFO,
825 "Registered device %0x:%0x fn=%0x %0x\n",
826 PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
827 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
829 func = PCI_FUNC(pdev->devfn);
830 if (pci_devs[i].dev < 4) {
831 pvt->pci_mcr[func] = pdev;
833 pvt->pci_ch[pci_devs[i].dev - 4][func] = pdev;
837 i7core_printk(KERN_INFO, "Driver loaded.\n");
843 * i7core_probe Probe for ONE instance of device to see if it is
846 * 0 for FOUND a device
849 static int __devinit i7core_probe(struct pci_dev *pdev,
850 const struct pci_device_id *id)
852 struct mem_ctl_info *mci;
853 struct i7core_pvt *pvt;
856 int num_dimms_per_channel;
857 int dev_idx = id->driver_data;
859 if (dev_idx >= ARRAY_SIZE(i7core_devs))
862 num_channels = NUM_CHANS;
864 /* FIXME: FAKE data, since we currently don't now how to get this */
865 num_dimms_per_channel = 4;
866 num_csrows = num_dimms_per_channel;
868 /* allocate a new MC control structure */
869 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
873 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
875 mci->dev = &pdev->dev; /* record ptr to the generic device */
876 dev_set_drvdata(mci->dev, mci);
880 // pvt->system_address = pdev; /* Record this device in our private */
881 // pvt->maxch = num_channels;
882 // pvt->maxdimmperch = num_dimms_per_channel;
885 mci->mtype_cap = MEM_FLAG_FB_DDR2; /* FIXME: it uses DDR3 */
886 mci->edac_ctl_cap = EDAC_FLAG_NONE;
887 mci->edac_cap = EDAC_FLAG_NONE;
888 mci->mod_name = "i7core_edac.c";
889 mci->mod_ver = I7CORE_REVISION;
890 mci->ctl_name = i7core_devs[dev_idx].ctl_name;
891 mci->dev_name = pci_name(pdev);
892 mci->ctl_page_to_phys = NULL;
893 mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
895 /* 'get' the pci devices we want to reserve for our use */
896 if (i7core_get_devices(mci, pdev))
899 /* add this new MC control structure to EDAC's list of MCs */
900 if (edac_mc_add_mc(mci)) {
901 debugf0("MC: " __FILE__
902 ": %s(): failed edac_mc_add_mc()\n", __func__);
903 /* FIXME: perhaps some code should go here that disables error
904 * reporting if we just enabled it
909 /* allocating generic PCI control info */
910 i7core_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
913 "%s(): Unable to create PCI control\n",
916 "%s(): PCI error report via EDAC not setup\n",
920 /* Default error mask is any memory */
921 pvt->inject.channel = -1;
922 pvt->inject.dimm = -1;
923 pvt->inject.rank = -1;
924 pvt->inject.bank = -1;
925 pvt->inject.page = -1;
926 pvt->inject.col = -1;
928 /* Get dimm basic config */
929 get_dimm_config(mci);
934 i7core_put_devices();
942 * i7core_remove destructor for one instance of device
945 static void __devexit i7core_remove(struct pci_dev *pdev)
947 struct mem_ctl_info *mci;
949 debugf0(__FILE__ ": %s()\n", __func__);
952 edac_pci_release_generic_ctl(i7core_pci);
954 mci = edac_mc_del_mc(&pdev->dev);
958 /* retrieve references to resources, and free those resources */
959 i7core_put_devices();
964 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
967 * i7core_driver pci_driver structure for this module
970 static struct pci_driver i7core_driver = {
971 .name = "i7core_edac",
972 .probe = i7core_probe,
973 .remove = __devexit_p(i7core_remove),
974 .id_table = i7core_pci_tbl,
978 * i7core_init Module entry function
979 * Try to initialize this module for its devices
981 static int __init i7core_init(void)
985 debugf2("MC: " __FILE__ ": %s()\n", __func__);
987 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
990 pci_rc = pci_register_driver(&i7core_driver);
992 return (pci_rc < 0) ? pci_rc : 0;
996 * i7core_exit() Module exit function
997 * Unregister the driver
999 static void __exit i7core_exit(void)
1001 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1002 pci_unregister_driver(&i7core_driver);
1005 module_init(i7core_init);
1006 module_exit(i7core_exit);
1008 MODULE_LICENSE("GPL");
1009 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1010 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1011 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
1014 module_param(edac_op_state, int, 0444);
1015 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");