drivers/edac/i7core_edac.c

   1 /* Intel 7 core  Memory Controller kernel module (Nehalem)
   2  *
   3  * This file may be distributed under the terms of the
   4  * GNU General Public License version 2 only.
   5  *
   6  * Copyright (c) 2009 by:
   7  *       Mauro Carvalho Chehab <mchehab@redhat.com>
   8  *
   9  * Red Hat Inc. http://www.redhat.com
  10  *
  11  * Forked and adapted from the i5400_edac driver
  12  *
  13  * Based on the following public Intel datasheets:
  14  * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
  15  * Datasheet, Volume 2:
  16  *      http://download.intel.com/design/processor/datashts/320835.pdf
  17  * Intel Xeon Processor 5500 Series Datasheet Volume 2
  18  *      http://www.intel.com/Assets/PDF/datasheet/321322.pdf
  19  * also available at:
  20  *      http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/pci.h>
  26 #include <linux/pci_ids.h>
  27 #include <linux/slab.h>
  28 #include <linux/edac.h>
  29 #include <linux/mmzone.h>
  30 #include <linux/edac_mce.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/smp.h>
  33 #include <asm/processor.h>
  34
  35 #include "edac_core.h"
  36
  37 /*
  38  * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
  39  * registers start at bus 255, and are not reported by BIOS.
  40  * We currently find devices with only 2 sockets. In order to support more QPI
  41  * Quick Path Interconnect, just increment this number.
  42  */
  43 #define MAX_SOCKET_BUSES        2
  44
  45
  46 /*
  47  * Alter this version for the module when modifications are made
  48  */
  49 #define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
  50 #define EDAC_MOD_STR      "i7core_edac"
  51
  52 /*
  53  * Debug macros
  54  */
  55 #define i7core_printk(level, fmt, arg...)                       \
  56         edac_printk(level, "i7core", fmt, ##arg)
  57
  58 #define i7core_mc_printk(mci, level, fmt, arg...)               \
  59         edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
  60
  61 /*
  62  * i7core Memory Controller Registers
  63  */
  64
  65         /* OFFSETS for Device 0 Function 0 */
  66
  67 #define MC_CFG_CONTROL  0x90
  68
  69         /* OFFSETS for Device 3 Function 0 */
  70
  71 #define MC_CONTROL      0x48
  72 #define MC_STATUS       0x4c
  73 #define MC_MAX_DOD      0x64
  74
  75 /*
  76  * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
  77  * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  78  */
  79
  80 #define MC_TEST_ERR_RCV1        0x60
  81   #define DIMM2_COR_ERR(r)                      ((r) & 0x7fff)
  82
  83 #define MC_TEST_ERR_RCV0        0x64
  84   #define DIMM1_COR_ERR(r)                      (((r) >> 16) & 0x7fff)
  85   #define DIMM0_COR_ERR(r)                      ((r) & 0x7fff)
  86
  87 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
  88 #define MC_COR_ECC_CNT_0        0x80
  89 #define MC_COR_ECC_CNT_1        0x84
  90 #define MC_COR_ECC_CNT_2        0x88
  91 #define MC_COR_ECC_CNT_3        0x8c
  92 #define MC_COR_ECC_CNT_4        0x90
  93 #define MC_COR_ECC_CNT_5        0x94
  94
  95 #define DIMM_TOP_COR_ERR(r)                     (((r) >> 16) & 0x7fff)
  96 #define DIMM_BOT_COR_ERR(r)                     ((r) & 0x7fff)
  97
  98
  99         /* OFFSETS for Devices 4,5 and 6 Function 0 */
 100
 101 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
 102   #define THREE_DIMMS_PRESENT           (1 << 24)
 103   #define SINGLE_QUAD_RANK_PRESENT      (1 << 23)
 104   #define QUAD_RANK_PRESENT             (1 << 22)
 105   #define REGISTERED_DIMM               (1 << 15)
 106
 107 #define MC_CHANNEL_MAPPER       0x60
 108   #define RDLCH(r, ch)          ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
 109   #define WRLCH(r, ch)          ((((r) >> (ch * 6)) & 0x07) - 1)
 110
 111 #define MC_CHANNEL_RANK_PRESENT 0x7c
 112   #define RANK_PRESENT_MASK             0xffff
 113
 114 #define MC_CHANNEL_ADDR_MATCH   0xf0
 115 #define MC_CHANNEL_ERROR_MASK   0xf8
 116 #define MC_CHANNEL_ERROR_INJECT 0xfc
 117   #define INJECT_ADDR_PARITY    0x10
 118   #define INJECT_ECC            0x08
 119   #define MASK_CACHELINE        0x06
 120   #define MASK_FULL_CACHELINE   0x06
 121   #define MASK_MSB32_CACHELINE  0x04
 122   #define MASK_LSB32_CACHELINE  0x02
 123   #define NO_MASK_CACHELINE     0x00
 124   #define REPEAT_EN             0x01
 125
 126         /* OFFSETS for Devices 4,5 and 6 Function 1 */
 127
 128 #define MC_DOD_CH_DIMM0         0x48
 129 #define MC_DOD_CH_DIMM1         0x4c
 130 #define MC_DOD_CH_DIMM2         0x50
 131   #define RANKOFFSET_MASK       ((1 << 12) | (1 << 11) | (1 << 10))
 132   #define RANKOFFSET(x)         ((x & RANKOFFSET_MASK) >> 10)
 133   #define DIMM_PRESENT_MASK     (1 << 9)
 134   #define DIMM_PRESENT(x)       (((x) & DIMM_PRESENT_MASK) >> 9)
 135   #define MC_DOD_NUMBANK_MASK           ((1 << 8) | (1 << 7))
 136   #define MC_DOD_NUMBANK(x)             (((x) & MC_DOD_NUMBANK_MASK) >> 7)
 137   #define MC_DOD_NUMRANK_MASK           ((1 << 6) | (1 << 5))
 138   #define MC_DOD_NUMRANK(x)             (((x) & MC_DOD_NUMRANK_MASK) >> 5)
 139   #define MC_DOD_NUMROW_MASK            ((1 << 4) | (1 << 3) | (1 << 2))
 140   #define MC_DOD_NUMROW(x)              (((x) & MC_DOD_NUMROW_MASK) >> 2)
 141   #define MC_DOD_NUMCOL_MASK            3
 142   #define MC_DOD_NUMCOL(x)              ((x) & MC_DOD_NUMCOL_MASK)
 143
 144 #define MC_RANK_PRESENT         0x7c
 145
 146 #define MC_SAG_CH_0     0x80
 147 #define MC_SAG_CH_1     0x84
 148 #define MC_SAG_CH_2     0x88
 149 #define MC_SAG_CH_3     0x8c
 150 #define MC_SAG_CH_4     0x90
 151 #define MC_SAG_CH_5     0x94
 152 #define MC_SAG_CH_6     0x98
 153 #define MC_SAG_CH_7     0x9c
 154
 155 #define MC_RIR_LIMIT_CH_0       0x40
 156 #define MC_RIR_LIMIT_CH_1       0x44
 157 #define MC_RIR_LIMIT_CH_2       0x48
 158 #define MC_RIR_LIMIT_CH_3       0x4C
 159 #define MC_RIR_LIMIT_CH_4       0x50
 160 #define MC_RIR_LIMIT_CH_5       0x54
 161 #define MC_RIR_LIMIT_CH_6       0x58
 162 #define MC_RIR_LIMIT_CH_7       0x5C
 163 #define MC_RIR_LIMIT_MASK       ((1 << 10) - 1)
 164
 165 #define MC_RIR_WAY_CH           0x80
 166   #define MC_RIR_WAY_OFFSET_MASK        (((1 << 14) - 1) & ~0x7)
 167   #define MC_RIR_WAY_RANK_MASK          0x7
 168
 169 /*
 170  * i7core structs
 171  */
 172
 173 #define NUM_CHANS 3
 174 #define MAX_DIMMS 3             /* Max DIMMS per channel */
 175 #define MAX_MCR_FUNC  4
 176 #define MAX_CHAN_FUNC 3
 177
 178 struct i7core_info {
 179         u32     mc_control;
 180         u32     mc_status;
 181         u32     max_dod;
 182         u32     ch_map;
 183 };
 184
 185
 186 struct i7core_inject {
 187         int     enable;
 188
 189         u32     section;
 190         u32     type;
 191         u32     eccmask;
 192
 193         /* Error address mask */
 194         int channel, dimm, rank, bank, page, col;
 195 };
 196
 197 struct i7core_channel {
 198         u32             ranks;
 199         u32             dimms;
 200 };
 201
 202 struct pci_id_descr {
 203         int                     dev;
 204         int                     func;
 205         int                     dev_id;
 206 };
 207
 208 struct i7core_dev {
 209         struct list_head        list;
 210         u8                      socket;
 211         struct pci_dev          **pdev;
 212         struct mem_ctl_info     *mci;
 213 };
 214
 215 struct i7core_pvt {
 216         struct pci_dev  *pci_noncore;
 217         struct pci_dev  *pci_mcr[MAX_MCR_FUNC + 1];
 218         struct pci_dev  *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
 219
 220         struct i7core_dev *i7core_dev;
 221
 222         struct i7core_info      info;
 223         struct i7core_inject    inject;
 224         struct i7core_channel   channel[NUM_CHANS];
 225
 226         int             channels; /* Number of active channels */
 227
 228         int             ce_count_available;
 229         int             csrow_map[NUM_CHANS][MAX_DIMMS];
 230
 231                         /* ECC corrected errors counts per udimm */
 232         unsigned long   udimm_ce_count[MAX_DIMMS];
 233         int             udimm_last_ce_count[MAX_DIMMS];
 234                         /* ECC corrected errors counts per rdimm */
 235         unsigned long   rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
 236         int             rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
 237
 238         unsigned int    is_registered;
 239
 240         /* mcelog glue */
 241         struct edac_mce         edac_mce;
 242         struct mce              mce_entry[MCE_LOG_LEN];
 243         unsigned                mce_count;
 244         spinlock_t              mce_lock;
 245 };
 246
 247 /* Static vars */
 248 static LIST_HEAD(i7core_edac_list);
 249 static DEFINE_MUTEX(i7core_edac_lock);
 250
 251 #define PCI_DESCR(device, function, device_id)  \
 252         .dev = (device),                        \
 253         .func = (function),                     \
 254         .dev_id = (device_id)
 255
 256 struct pci_id_descr pci_dev_descr[] = {
 257                 /* Memory controller */
 258         { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
 259         { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
 260         { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS)  }, /* if RDIMM */
 261         { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
 262
 263                 /* Channel 0 */
 264         { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
 265         { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
 266         { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
 267         { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },
 268
 269                 /* Channel 1 */
 270         { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
 271         { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
 272         { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
 273         { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },
 274
 275                 /* Channel 2 */
 276         { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
 277         { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
 278         { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
 279         { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
 280
 281                 /* Generic Non-core registers */
 282         /*
 283          * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
 284          * On Xeon 55xx, however, it has a different id (8086:2c40). So,
 285          * the probing code needs to test for the other address in case of
 286          * failure of this one
 287          */
 288         { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE)  },
 289
 290 };
 291 #define N_DEVS ARRAY_SIZE(pci_dev_descr)
 292
 293 /*
 294  *      pci_device_id   table for which devices we are looking for
 295  */
 296 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
 297         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
 298         {0,}                    /* 0 terminated list. */
 299 };
 300
 301 static struct edac_pci_ctl_info *i7core_pci;
 302
 303 /****************************************************************************
 304                         Anciliary status routines
 305  ****************************************************************************/
 306
 307         /* MC_CONTROL bits */
 308 #define CH_ACTIVE(pvt, ch)      ((pvt)->info.mc_control & (1 << (8 + ch)))
 309 #define ECCx8(pvt)              ((pvt)->info.mc_control & (1 << 1))
 310
 311         /* MC_STATUS bits */
 312 #define ECC_ENABLED(pvt)        ((pvt)->info.mc_status & (1 << 4))
 313 #define CH_DISABLED(pvt, ch)    ((pvt)->info.mc_status & (1 << ch))
 314
 315         /* MC_MAX_DOD read functions */
 316 static inline int numdimms(u32 dimms)
 317 {
 318         return (dimms & 0x3) + 1;
 319 }
 320
 321 static inline int numrank(u32 rank)
 322 {
 323         static int ranks[4] = { 1, 2, 4, -EINVAL };
 324
 325         return ranks[rank & 0x3];
 326 }
 327
 328 static inline int numbank(u32 bank)
 329 {
 330         static int banks[4] = { 4, 8, 16, -EINVAL };
 331
 332         return banks[bank & 0x3];
 333 }
 334
 335 static inline int numrow(u32 row)
 336 {
 337         static int rows[8] = {
 338                 1 << 12, 1 << 13, 1 << 14, 1 << 15,
 339                 1 << 16, -EINVAL, -EINVAL, -EINVAL,
 340         };
 341
 342         return rows[row & 0x7];
 343 }
 344
 345 static inline int numcol(u32 col)
 346 {
 347         static int cols[8] = {
 348                 1 << 10, 1 << 11, 1 << 12, -EINVAL,
 349         };
 350         return cols[col & 0x3];
 351 }
 352
 353 static struct i7core_dev *get_i7core_dev(u8 socket)
 354 {
 355         struct i7core_dev *i7core_dev;
 356
 357         list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
 358                 if (i7core_dev->socket == socket)
 359                         return i7core_dev;
 360         }
 361
 362         return NULL;
 363 }
 364
 365 /****************************************************************************
 366                         Memory check routines
 367  ****************************************************************************/
 368 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
 369                                           unsigned func)
 370 {
 371         struct i7core_dev *i7core_dev = get_i7core_dev(socket);
 372         int i;
 373
 374         if (!i7core_dev)
 375                 return NULL;
 376
 377         for (i = 0; i < N_DEVS; i++) {
 378                 if (!i7core_dev->pdev[i])
 379                         continue;
 380
 381                 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
 382                     PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
 383                         return i7core_dev->pdev[i];
 384                 }
 385         }
 386
 387         return NULL;
 388 }
 389
 390 /**
 391  * i7core_get_active_channels() - gets the number of channels and csrows
 392  * @socket:     Quick Path Interconnect socket
 393  * @channels:   Number of channels that will be returned
 394  * @csrows:     Number of csrows found
 395  *
 396  * Since EDAC core needs to know in advance the number of available channels
 397  * and csrows, in order to allocate memory for csrows/channels, it is needed
 398  * to run two similar steps. At the first step, implemented on this function,
 399  * it checks the number of csrows/channels present at one socket.
 400  * this is used in order to properly allocate the size of mci components.
 401  *
 402  * It should be noticed that none of the current available datasheets explain
 403  * or even mention how csrows are seen by the memory controller. So, we need
 404  * to add a fake description for csrows.
 405  * So, this driver is attributing one DIMM memory for one csrow.
 406  */
 407 static int i7core_get_active_channels(u8 socket, unsigned *channels,
 408                                       unsigned *csrows)
 409 {
 410         struct pci_dev *pdev = NULL;
 411         int i, j;
 412         u32 status, control;
 413
 414         *channels = 0;
 415         *csrows = 0;
 416
 417         pdev = get_pdev_slot_func(socket, 3, 0);
 418         if (!pdev) {
 419                 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
 420                               socket);
 421                 return -ENODEV;
 422         }
 423
 424         /* Device 3 function 0 reads */
 425         pci_read_config_dword(pdev, MC_STATUS, &status);
 426         pci_read_config_dword(pdev, MC_CONTROL, &control);
 427
 428         for (i = 0; i < NUM_CHANS; i++) {
 429                 u32 dimm_dod[3];
 430                 /* Check if the channel is active */
 431                 if (!(control & (1 << (8 + i))))
 432                         continue;
 433
 434                 /* Check if the channel is disabled */
 435                 if (status & (1 << i))
 436                         continue;
 437
 438                 pdev = get_pdev_slot_func(socket, i + 4, 1);
 439                 if (!pdev) {
 440                         i7core_printk(KERN_ERR, "Couldn't find socket %d "
 441                                                 "fn %d.%d!!!\n",
 442                                                 socket, i + 4, 1);
 443                         return -ENODEV;
 444                 }
 445                 /* Devices 4-6 function 1 */
 446                 pci_read_config_dword(pdev,
 447                                 MC_DOD_CH_DIMM0, &dimm_dod[0]);
 448                 pci_read_config_dword(pdev,
 449                                 MC_DOD_CH_DIMM1, &dimm_dod[1]);
 450                 pci_read_config_dword(pdev,
 451                                 MC_DOD_CH_DIMM2, &dimm_dod[2]);
 452
 453                 (*channels)++;
 454
 455                 for (j = 0; j < 3; j++) {
 456                         if (!DIMM_PRESENT(dimm_dod[j]))
 457                                 continue;
 458                         (*csrows)++;
 459                 }
 460         }
 461
 462         debugf0("Number of active channels on socket %d: %d\n",
 463                 socket, *channels);
 464
 465         return 0;
 466 }
 467
 468 static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
 469 {
 470         struct i7core_pvt *pvt = mci->pvt_info;
 471         struct csrow_info *csr;
 472         struct pci_dev *pdev;
 473         int i, j;
 474         u8 socket = pvt->i7core_dev->socket;
 475         unsigned long last_page = 0;
 476         enum edac_type mode;
 477         enum mem_type mtype;
 478
 479         /* Get data from the MC register, function 0 */
 480         pdev = pvt->pci_mcr[0];
 481         if (!pdev)
 482                 return -ENODEV;
 483
 484         /* Device 3 function 0 reads */
 485         pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
 486         pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
 487         pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
 488         pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
 489
 490         debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
 491                 socket, pvt->info.mc_control, pvt->info.mc_status,
 492                 pvt->info.max_dod, pvt->info.ch_map);
 493
 494         if (ECC_ENABLED(pvt)) {
 495                 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
 496                 if (ECCx8(pvt))
 497                         mode = EDAC_S8ECD8ED;
 498                 else
 499                         mode = EDAC_S4ECD4ED;
 500         } else {
 501                 debugf0("ECC disabled\n");
 502                 mode = EDAC_NONE;
 503         }
 504
 505         /* FIXME: need to handle the error codes */
 506         debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
 507                 "x%x x 0x%x\n",
 508                 numdimms(pvt->info.max_dod),
 509                 numrank(pvt->info.max_dod >> 2),
 510                 numbank(pvt->info.max_dod >> 4),
 511                 numrow(pvt->info.max_dod >> 6),
 512                 numcol(pvt->info.max_dod >> 9));
 513
 514         for (i = 0; i < NUM_CHANS; i++) {
 515                 u32 data, dimm_dod[3], value[8];
 516
 517                 if (!CH_ACTIVE(pvt, i)) {
 518                         debugf0("Channel %i is not active\n", i);
 519                         continue;
 520                 }
 521                 if (CH_DISABLED(pvt, i)) {
 522                         debugf0("Channel %i is disabled\n", i);
 523                         continue;
 524                 }
 525
 526                 /* Devices 4-6 function 0 */
 527                 pci_read_config_dword(pvt->pci_ch[i][0],
 528                                 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
 529
 530                 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
 531                                                 4 : 2;
 532
 533                 if (data & REGISTERED_DIMM)
 534                         mtype = MEM_RDDR3;
 535                 else
 536                         mtype = MEM_DDR3;
 537 #if 0
 538                 if (data & THREE_DIMMS_PRESENT)
 539                         pvt->channel[i].dimms = 3;
 540                 else if (data & SINGLE_QUAD_RANK_PRESENT)
 541                         pvt->channel[i].dimms = 1;
 542                 else
 543                         pvt->channel[i].dimms = 2;
 544 #endif
 545
 546                 /* Devices 4-6 function 1 */
 547                 pci_read_config_dword(pvt->pci_ch[i][1],
 548                                 MC_DOD_CH_DIMM0, &dimm_dod[0]);
 549                 pci_read_config_dword(pvt->pci_ch[i][1],
 550                                 MC_DOD_CH_DIMM1, &dimm_dod[1]);
 551                 pci_read_config_dword(pvt->pci_ch[i][1],
 552                                 MC_DOD_CH_DIMM2, &dimm_dod[2]);
 553
 554                 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
 555                         "%d ranks, %cDIMMs\n",
 556                         i,
 557                         RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
 558                         data,
 559                         pvt->channel[i].ranks,
 560                         (data & REGISTERED_DIMM) ? 'R' : 'U');
 561
 562                 for (j = 0; j < 3; j++) {
 563                         u32 banks, ranks, rows, cols;
 564                         u32 size, npages;
 565
 566                         if (!DIMM_PRESENT(dimm_dod[j]))
 567                                 continue;
 568
 569                         banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
 570                         ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
 571                         rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
 572                         cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
 573
 574                         /* DDR3 has 8 I/O banks */
 575                         size = (rows * cols * banks * ranks) >> (20 - 3);
 576
 577                         pvt->channel[i].dimms++;
 578
 579                         debugf0("\tdimm %d %d Mb offset: %x, "
 580                                 "bank: %d, rank: %d, row: %#x, col: %#x\n",
 581                                 j, size,
 582                                 RANKOFFSET(dimm_dod[j]),
 583                                 banks, ranks, rows, cols);
 584
 585 #if PAGE_SHIFT > 20
 586                         npages = size >> (PAGE_SHIFT - 20);
 587 #else
 588                         npages = size << (20 - PAGE_SHIFT);
 589 #endif
 590
 591                         csr = &mci->csrows[*csrow];
 592                         csr->first_page = last_page + 1;
 593                         last_page += npages;
 594                         csr->last_page = last_page;
 595                         csr->nr_pages = npages;
 596
 597                         csr->page_mask = 0;
 598                         csr->grain = 8;
 599                         csr->csrow_idx = *csrow;
 600                         csr->nr_channels = 1;
 601
 602                         csr->channels[0].chan_idx = i;
 603                         csr->channels[0].ce_count = 0;
 604
 605                         pvt->csrow_map[i][j] = *csrow;
 606
 607                         switch (banks) {
 608                         case 4:
 609                                 csr->dtype = DEV_X4;
 610                                 break;
 611                         case 8:
 612                                 csr->dtype = DEV_X8;
 613                                 break;
 614                         case 16:
 615                                 csr->dtype = DEV_X16;
 616                                 break;
 617                         default:
 618                                 csr->dtype = DEV_UNKNOWN;
 619                         }
 620
 621                         csr->edac_mode = mode;
 622                         csr->mtype = mtype;
 623
 624                         (*csrow)++;
 625                 }
 626
 627                 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
 628                 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
 629                 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
 630                 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
 631                 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
 632                 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
 633                 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
 634                 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
 635                 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
 636                 for (j = 0; j < 8; j++)
 637                         debugf1("\t\t%#x\t%#x\t%#x\n",
 638                                 (value[j] >> 27) & 0x1,
 639                                 (value[j] >> 24) & 0x7,
 640                                 (value[j] && ((1 << 24) - 1)));
 641         }
 642
 643         return 0;
 644 }
 645
 646 /****************************************************************************
 647                         Error insertion routines
 648  ****************************************************************************/
 649
 650 /* The i7core has independent error injection features per channel.
 651    However, to have a simpler code, we don't allow enabling error injection
 652    on more than one channel.
 653    Also, since a change at an inject parameter will be applied only at enable,
 654    we're disabling error injection on all write calls to the sysfs nodes that
 655    controls the error code injection.
 656  */
 657 static int disable_inject(struct mem_ctl_info *mci)
 658 {
 659         struct i7core_pvt *pvt = mci->pvt_info;
 660
 661         pvt->inject.enable = 0;
 662
 663         if (!pvt->pci_ch[pvt->inject.channel][0])
 664                 return -ENODEV;
 665
 666         pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
 667                                 MC_CHANNEL_ERROR_INJECT, 0);
 668
 669         return 0;
 670 }
 671
 672 /*
 673  * i7core inject inject.section
 674  *
 675  *      accept and store error injection inject.section value
 676  *      bit 0 - refers to the lower 32-byte half cacheline
 677  *      bit 1 - refers to the upper 32-byte half cacheline
 678  */
 679 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
 680                                            const char *data, size_t count)
 681 {
 682         struct i7core_pvt *pvt = mci->pvt_info;
 683         unsigned long value;
 684         int rc;
 685
 686         if (pvt->inject.enable)
 687                 disable_inject(mci);
 688
 689         rc = strict_strtoul(data, 10, &value);
 690         if ((rc < 0) || (value > 3))
 691                 return -EIO;
 692
 693         pvt->inject.section = (u32) value;
 694         return count;
 695 }
 696
 697 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
 698                                               char *data)
 699 {
 700         struct i7core_pvt *pvt = mci->pvt_info;
 701         return sprintf(data, "0x%08x\n", pvt->inject.section);
 702 }
 703
 704 /*
 705  * i7core inject.type
 706  *
 707  *      accept and store error injection inject.section value
 708  *      bit 0 - repeat enable - Enable error repetition
 709  *      bit 1 - inject ECC error
 710  *      bit 2 - inject parity error
 711  */
 712 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
 713                                         const char *data, size_t count)
 714 {
 715         struct i7core_pvt *pvt = mci->pvt_info;
 716         unsigned long value;
 717         int rc;
 718
 719         if (pvt->inject.enable)
 720                 disable_inject(mci);
 721
 722         rc = strict_strtoul(data, 10, &value);
 723         if ((rc < 0) || (value > 7))
 724                 return -EIO;
 725
 726         pvt->inject.type = (u32) value;
 727         return count;
 728 }
 729
 730 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
 731                                               char *data)
 732 {
 733         struct i7core_pvt *pvt = mci->pvt_info;
 734         return sprintf(data, "0x%08x\n", pvt->inject.type);
 735 }
 736
 737 /*
 738  * i7core_inject_inject.eccmask_store
 739  *
 740  * The type of error (UE/CE) will depend on the inject.eccmask value:
 741  *   Any bits set to a 1 will flip the corresponding ECC bit
 742  *   Correctable errors can be injected by flipping 1 bit or the bits within
 743  *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 744  *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 745  *   uncorrectable error to be injected.
 746  */
 747 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
 748                                         const char *data, size_t count)
 749 {
 750         struct i7core_pvt *pvt = mci->pvt_info;
 751         unsigned long value;
 752         int rc;
 753
 754         if (pvt->inject.enable)
 755                 disable_inject(mci);
 756
 757         rc = strict_strtoul(data, 10, &value);
 758         if (rc < 0)
 759                 return -EIO;
 760
 761         pvt->inject.eccmask = (u32) value;
 762         return count;
 763 }
 764
 765 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
 766                                               char *data)
 767 {
 768         struct i7core_pvt *pvt = mci->pvt_info;
 769         return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
 770 }
 771
 772 /*
 773  * i7core_addrmatch
 774  *
 775  * The type of error (UE/CE) will depend on the inject.eccmask value:
 776  *   Any bits set to a 1 will flip the corresponding ECC bit
 777  *   Correctable errors can be injected by flipping 1 bit or the bits within
 778  *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 779  *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 780  *   uncorrectable error to be injected.
 781  */
 782 static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
 783                                         const char *data, size_t count)
 784 {
 785         struct i7core_pvt *pvt = mci->pvt_info;
 786         char *cmd, *val;
 787         long value;
 788         int rc;
 789
 790         if (pvt->inject.enable)
 791                 disable_inject(mci);
 792
 793         do {
 794                 cmd = strsep((char **) &data, ":");
 795                 if (!cmd)
 796                         break;
 797                 val = strsep((char **) &data, " \n\t");
 798                 if (!val)
 799                         return cmd - data;
 800
 801                 if (!strcasecmp(val, "any"))
 802                         value = -1;
 803                 else {
 804                         rc = strict_strtol(val, 10, &value);
 805                         if ((rc < 0) || (value < 0))
 806                                 return cmd - data;
 807                 }
 808
 809                 if (!strcasecmp(cmd, "channel")) {
 810                         if (value < 3)
 811                                 pvt->inject.channel = value;
 812                         else
 813                                 return cmd - data;
 814                 } else if (!strcasecmp(cmd, "dimm")) {
 815                         if (value < 3)
 816                                 pvt->inject.dimm = value;
 817                         else
 818                                 return cmd - data;
 819                 } else if (!strcasecmp(cmd, "rank")) {
 820                         if (value < 4)
 821                                 pvt->inject.rank = value;
 822                         else
 823                                 return cmd - data;
 824                 } else if (!strcasecmp(cmd, "bank")) {
 825                         if (value < 32)
 826                                 pvt->inject.bank = value;
 827                         else
 828                                 return cmd - data;
 829                 } else if (!strcasecmp(cmd, "page")) {
 830                         if (value <= 0xffff)
 831                                 pvt->inject.page = value;
 832                         else
 833                                 return cmd - data;
 834                 } else if (!strcasecmp(cmd, "col") ||
 835                            !strcasecmp(cmd, "column")) {
 836                         if (value <= 0x3fff)
 837                                 pvt->inject.col = value;
 838                         else
 839                                 return cmd - data;
 840                 }
 841         } while (1);
 842
 843         return count;
 844 }
 845
 846 static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
 847                                               char *data)
 848 {
 849         struct i7core_pvt *pvt = mci->pvt_info;
 850         char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];
 851
 852         if (pvt->inject.channel < 0)
 853                 sprintf(channel, "any");
 854         else
 855                 sprintf(channel, "%d", pvt->inject.channel);
 856         if (pvt->inject.dimm < 0)
 857                 sprintf(dimm, "any");
 858         else
 859                 sprintf(dimm, "%d", pvt->inject.dimm);
 860         if (pvt->inject.bank < 0)
 861                 sprintf(bank, "any");
 862         else
 863                 sprintf(bank, "%d", pvt->inject.bank);
 864         if (pvt->inject.rank < 0)
 865                 sprintf(rank, "any");
 866         else
 867                 sprintf(rank, "%d", pvt->inject.rank);
 868         if (pvt->inject.page < 0)
 869                 sprintf(page, "any");
 870         else
 871                 sprintf(page, "0x%04x", pvt->inject.page);
 872         if (pvt->inject.col < 0)
 873                 sprintf(col, "any");
 874         else
 875                 sprintf(col, "0x%04x", pvt->inject.col);
 876
 877         return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
 878                              "rank: %s\npage: %s\ncolumn: %s\n",
 879                        channel, dimm, bank, rank, page, col);
 880 }
 881
 882 static int write_and_test(struct pci_dev *dev, int where, u32 val)
 883 {
 884         u32 read;
 885         int count;
 886
 887         debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
 888                 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 889                 where, val);
 890
 891         for (count = 0; count < 10; count++) {
 892                 if (count)
 893                         msleep(100);
 894                 pci_write_config_dword(dev, where, val);
 895                 pci_read_config_dword(dev, where, &read);
 896
 897                 if (read == val)
 898                         return 0;
 899         }
 900
 901         i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
 902                 "write=%08x. Read=%08x\n",
 903                 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 904                 where, val, read);
 905
 906         return -EINVAL;
 907 }
 908
 909 /*
 910  * This routine prepares the Memory Controller for error injection.
 911  * The error will be injected when some process tries to write to the
 912  * memory that matches the given criteria.
 913  * The criteria can be set in terms of a mask where dimm, rank, bank, page
 914  * and col can be specified.
 915  * A -1 value for any of the mask items will make the MCU to ignore
 916  * that matching criteria for error injection.
 917  *
 918  * It should be noticed that the error will only happen after a write operation
 919  * on a memory that matches the condition. if REPEAT_EN is not enabled at
 920  * inject mask, then it will produce just one error. Otherwise, it will repeat
 921  * until the injectmask would be cleaned.
 922  *
 923  * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 924  *    is reliable enough to check if the MC is using the
 925  *    three channels. However, this is not clear at the datasheet.
 926  */
 927 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
 928                                        const char *data, size_t count)
 929 {
 930         struct i7core_pvt *pvt = mci->pvt_info;
 931         u32 injectmask;
 932         u64 mask = 0;
 933         int  rc;
 934         long enable;
 935
 936         if (!pvt->pci_ch[pvt->inject.channel][0])
 937                 return 0;
 938
 939         rc = strict_strtoul(data, 10, &enable);
 940         if ((rc < 0))
 941                 return 0;
 942
 943         if (enable) {
 944                 pvt->inject.enable = 1;
 945         } else {
 946                 disable_inject(mci);
 947                 return count;
 948         }
 949
 950         /* Sets pvt->inject.dimm mask */
 951         if (pvt->inject.dimm < 0)
 952                 mask |= 1L << 41;
 953         else {
 954                 if (pvt->channel[pvt->inject.channel].dimms > 2)
 955                         mask |= (pvt->inject.dimm & 0x3L) << 35;
 956                 else
 957                         mask |= (pvt->inject.dimm & 0x1L) << 36;
 958         }
 959
 960         /* Sets pvt->inject.rank mask */
 961         if (pvt->inject.rank < 0)
 962                 mask |= 1L << 40;
 963         else {
 964                 if (pvt->channel[pvt->inject.channel].dimms > 2)
 965                         mask |= (pvt->inject.rank & 0x1L) << 34;
 966                 else
 967                         mask |= (pvt->inject.rank & 0x3L) << 34;
 968         }
 969
 970         /* Sets pvt->inject.bank mask */
 971         if (pvt->inject.bank < 0)
 972                 mask |= 1L << 39;
 973         else
 974                 mask |= (pvt->inject.bank & 0x15L) << 30;
 975
 976         /* Sets pvt->inject.page mask */
 977         if (pvt->inject.page < 0)
 978                 mask |= 1L << 38;
 979         else
 980                 mask |= (pvt->inject.page & 0xffffL) << 14;
 981
 982         /* Sets pvt->inject.column mask */
 983         if (pvt->inject.col < 0)
 984                 mask |= 1L << 37;
 985         else
 986                 mask |= (pvt->inject.col & 0x3fffL);
 987
 988         /*
 989          * bit    0: REPEAT_EN
 990          * bits 1-2: MASK_HALF_CACHELINE
 991          * bit    3: INJECT_ECC
 992          * bit    4: INJECT_ADDR_PARITY
 993          */
 994
 995         injectmask = (pvt->inject.type & 1) |
 996                      (pvt->inject.section & 0x3) << 1 |
 997                      (pvt->inject.type & 0x6) << (3 - 1);
 998
 999         /* Unlock writes to registers - this register is write only */
1000         pci_write_config_dword(pvt->pci_noncore,
1001                                MC_CFG_CONTROL, 0x2);
1002
1003         write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1004                                MC_CHANNEL_ADDR_MATCH, mask);
1005         write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1006                                MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1007
1008         write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1009                                MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1010
1011         write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1012                                MC_CHANNEL_ERROR_INJECT, injectmask);
1013
1014         /*
1015          * This is something undocumented, based on my tests
1016          * Without writing 8 to this register, errors aren't injected. Not sure
1017          * why.
1018          */
1019         pci_write_config_dword(pvt->pci_noncore,
1020                                MC_CFG_CONTROL, 8);
1021
1022         debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1023                 " inject 0x%08x\n",
1024                 mask, pvt->inject.eccmask, injectmask);
1025
1026
1027         return count;
1028 }
1029
1030 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1031                                         char *data)
1032 {
1033         struct i7core_pvt *pvt = mci->pvt_info;
1034         u32 injectmask;
1035
1036         pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1037                                MC_CHANNEL_ERROR_INJECT, &injectmask);
1038
1039         debugf0("Inject error read: 0x%018x\n", injectmask);
1040
1041         if (injectmask & 0x0c)
1042                 pvt->inject.enable = 1;
1043
1044         return sprintf(data, "%d\n", pvt->inject.enable);
1045 }
1046
1047 static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
1048 {
1049         unsigned i, count, total = 0;
1050         struct i7core_pvt *pvt = mci->pvt_info;
1051
1052         if (!pvt->ce_count_available) {
1053                 count = sprintf(data, "data unavailable\n");
1054                 return 0;
1055         }
1056         if (!pvt->is_registered) {
1057                 count = sprintf(data, "all channels "
1058                                 "UDIMM0: %lu UDIMM1: %lu UDIMM2: %lu\n",
1059                                 pvt->udimm_ce_count[0],
1060                                 pvt->udimm_ce_count[1],
1061                                 pvt->udimm_ce_count[2]);
1062                 data  += count;
1063                 total += count;
1064         } else {
1065                 for (i = 0; i < NUM_CHANS; i++) {
1066                         count = sprintf(data, "channel %d RDIMM0: %lu "
1067                                         "RDIMM1: %lu RDIMM2: %lu\n",
1068                                         i,
1069                                         pvt->rdimm_ce_count[i][0],
1070                                         pvt->rdimm_ce_count[i][1],
1071                                         pvt->rdimm_ce_count[i][2]);
1072                         data  += count;
1073                         total += count;
1074                 }
1075         }
1076
1077         return total;
1078 }
1079
1080 /*
1081  * Sysfs struct
1082  */
1083 static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
1084         {
1085                 .attr = {
1086                         .name = "inject_section",
1087                         .mode = (S_IRUGO | S_IWUSR)
1088                 },
1089                 .show  = i7core_inject_section_show,
1090                 .store = i7core_inject_section_store,
1091         }, {
1092                 .attr = {
1093                         .name = "inject_type",
1094                         .mode = (S_IRUGO | S_IWUSR)
1095                 },
1096                 .show  = i7core_inject_type_show,
1097                 .store = i7core_inject_type_store,
1098         }, {
1099                 .attr = {
1100                         .name = "inject_eccmask",
1101                         .mode = (S_IRUGO | S_IWUSR)
1102                 },
1103                 .show  = i7core_inject_eccmask_show,
1104                 .store = i7core_inject_eccmask_store,
1105         }, {
1106                 .attr = {
1107                         .name = "inject_addrmatch",
1108                         .mode = (S_IRUGO | S_IWUSR)
1109                 },
1110                 .show  = i7core_inject_addrmatch_show,
1111                 .store = i7core_inject_addrmatch_store,
1112         }, {
1113                 .attr = {
1114                         .name = "inject_enable",
1115                         .mode = (S_IRUGO | S_IWUSR)
1116                 },
1117                 .show  = i7core_inject_enable_show,
1118                 .store = i7core_inject_enable_store,
1119         }, {
1120                 .attr = {
1121                         .name = "corrected_error_counts",
1122                         .mode = (S_IRUGO | S_IWUSR)
1123                 },
1124                 .show  = i7core_ce_regs_show,
1125                 .store = NULL,
1126         },
1127 };
1128
1129 /****************************************************************************
1130         Device initialization routines: put/get, init/exit
1131  ****************************************************************************/
1132
1133 /*
1134  *      i7core_put_devices      'put' all the devices that we have
1135  *                              reserved via 'get'
1136  */
1137 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1138 {
1139         int i;
1140
1141         debugf0(__FILE__ ": %s()\n", __func__);
1142         for (i = 0; i < N_DEVS; i++) {
1143                 struct pci_dev *pdev = i7core_dev->pdev[i];
1144                 if (!pdev)
1145                         continue;
1146                 debugf0("Removing dev %02x:%02x.%d\n",
1147                         pdev->bus->number,
1148                         PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1149                 pci_dev_put(pdev);
1150         }
1151         kfree(i7core_dev->pdev);
1152         list_del(&i7core_dev->list);
1153         kfree(i7core_dev);
1154 }
1155
1156 static void i7core_put_all_devices(void)
1157 {
1158         struct i7core_dev *i7core_dev;
1159
1160         list_for_each_entry(i7core_dev, &i7core_edac_list, list)
1161                 i7core_put_devices(i7core_dev);
1162 }
1163
1164 static void i7core_xeon_pci_fixup(void)
1165 {
1166         struct pci_dev *pdev = NULL;
1167         int i;
1168         /*
1169          * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1170          * aren't announced by acpi. So, we need to use a legacy scan probing
1171          * to detect them
1172          */
1173         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1174                               pci_dev_descr[0].dev_id, NULL);
1175         if (unlikely(!pdev)) {
1176                 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1177                         pcibios_scan_specific_bus(255-i);
1178         }
1179 }
1180
1181 /*
1182  *      i7core_get_devices      Find and perform 'get' operation on the MCH's
1183  *                      device/functions we want to reference for this driver
1184  *
1185  *                      Need to 'get' device 16 func 1 and func 2
1186  */
1187 int i7core_get_onedevice(struct pci_dev **prev, int devno)
1188 {
1189         struct i7core_dev *i7core_dev;
1190
1191         struct pci_dev *pdev = NULL;
1192         u8 bus = 0;
1193         u8 socket = 0;
1194
1195         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1196                               pci_dev_descr[devno].dev_id, *prev);
1197
1198         /*
1199          * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1200          * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1201          * to probe for the alternate address in case of failure
1202          */
1203         if (pci_dev_descr[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
1204                 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1205                                       PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
1206
1207         if (!pdev) {
1208                 if (*prev) {
1209                         *prev = pdev;
1210                         return 0;
1211                 }
1212
1213                 /*
1214                  * Dev 3 function 2 only exists on chips with RDIMMs
1215                  * so, it is ok to not found it
1216                  */
1217                 if ((pci_dev_descr[devno].dev == 3) && (pci_dev_descr[devno].func == 2)) {
1218                         *prev = pdev;
1219                         return 0;
1220                 }
1221
1222                 i7core_printk(KERN_ERR,
1223                         "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1224                         pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1225                         PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1226
1227                 /* End of list, leave */
1228                 return -ENODEV;
1229         }
1230         bus = pdev->bus->number;
1231
1232         if (bus == 0x3f)
1233                 socket = 0;
1234         else
1235                 socket = 255 - bus;
1236
1237         i7core_dev = get_i7core_dev(socket);
1238         if (!i7core_dev) {
1239                 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
1240                 if (!i7core_dev)
1241                         return -ENOMEM;
1242                 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * N_DEVS,
1243                                            GFP_KERNEL);
1244                 if (!i7core_dev->pdev)
1245                         return -ENOMEM;
1246                 i7core_dev->socket = socket;
1247                 list_add_tail(&i7core_dev->list, &i7core_edac_list);
1248         }
1249
1250         if (i7core_dev->pdev[devno]) {
1251                 i7core_printk(KERN_ERR,
1252                         "Duplicated device for "
1253                         "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1254                         bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1255                         PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1256                 pci_dev_put(pdev);
1257                 return -ENODEV;
1258         }
1259
1260         i7core_dev->pdev[devno] = pdev;
1261
1262         /* Sanity check */
1263         if (unlikely(PCI_SLOT(pdev->devfn) != pci_dev_descr[devno].dev ||
1264                         PCI_FUNC(pdev->devfn) != pci_dev_descr[devno].func)) {
1265                 i7core_printk(KERN_ERR,
1266                         "Device PCI ID %04x:%04x "
1267                         "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1268                         PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id,
1269                         bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1270                         bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func);
1271                 return -ENODEV;
1272         }
1273
1274         /* Be sure that the device is enabled */
1275         if (unlikely(pci_enable_device(pdev) < 0)) {
1276                 i7core_printk(KERN_ERR,
1277                         "Couldn't enable "
1278                         "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1279                         bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1280                         PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1281                 return -ENODEV;
1282         }
1283
1284         debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1285                 socket, bus, pci_dev_descr[devno].dev,
1286                 pci_dev_descr[devno].func,
1287                 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1288
1289         *prev = pdev;
1290
1291         return 0;
1292 }
1293
1294 static int i7core_get_devices(void)
1295 {
1296         int i;
1297         struct pci_dev *pdev = NULL;
1298
1299         for (i = 0; i < N_DEVS; i++) {
1300                 pdev = NULL;
1301                 do {
1302                         if (i7core_get_onedevice(&pdev, i) < 0) {
1303                                 i7core_put_all_devices();
1304                                 return -ENODEV;
1305                         }
1306                 } while (pdev);
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int mci_bind_devs(struct mem_ctl_info *mci,
1313                          struct i7core_dev *i7core_dev)
1314 {
1315         struct i7core_pvt *pvt = mci->pvt_info;
1316         struct pci_dev *pdev;
1317         int i, func, slot;
1318
1319         /* Associates i7core_dev and mci for future usage */
1320         pvt->i7core_dev = i7core_dev;
1321         i7core_dev->mci = mci;
1322
1323         pvt->is_registered = 0;
1324         for (i = 0; i < N_DEVS; i++) {
1325                 pdev = i7core_dev->pdev[i];
1326                 if (!pdev)
1327                         continue;
1328
1329                 func = PCI_FUNC(pdev->devfn);
1330                 slot = PCI_SLOT(pdev->devfn);
1331                 if (slot == 3) {
1332                         if (unlikely(func > MAX_MCR_FUNC))
1333                                 goto error;
1334                         pvt->pci_mcr[func] = pdev;
1335                 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1336                         if (unlikely(func > MAX_CHAN_FUNC))
1337                                 goto error;
1338                         pvt->pci_ch[slot - 4][func] = pdev;
1339                 } else if (!slot && !func)
1340                         pvt->pci_noncore = pdev;
1341                 else
1342                         goto error;
1343
1344                 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1345                         PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1346                         pdev, i7core_dev->socket);
1347
1348                 if (PCI_SLOT(pdev->devfn) == 3 &&
1349                         PCI_FUNC(pdev->devfn) == 2)
1350                         pvt->is_registered = 1;
1351         }
1352
1353         return 0;
1354
1355 error:
1356         i7core_printk(KERN_ERR, "Device %d, function %d "
1357                       "is out of the expected range\n",
1358                       slot, func);
1359         return -EINVAL;
1360 }
1361
1362 /****************************************************************************
1363                         Error check routines
1364  ****************************************************************************/
1365 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1366                                          int chan, int dimm, int add)
1367 {
1368         char *msg;
1369         struct i7core_pvt *pvt = mci->pvt_info;
1370         int row = pvt->csrow_map[chan][dimm], i;
1371
1372         for (i = 0; i < add; i++) {
1373                 msg = kasprintf(GFP_KERNEL, "Corrected error "
1374                                 "(Socket=%d channel=%d dimm=%d)",
1375                                 pvt->i7core_dev->socket, chan, dimm);
1376
1377                 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1378                 kfree (msg);
1379         }
1380 }
1381
1382 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1383                         int chan, int new0, int new1, int new2)
1384 {
1385         struct i7core_pvt *pvt = mci->pvt_info;
1386         int add0 = 0, add1 = 0, add2 = 0;
1387         /* Updates CE counters if it is not the first time here */
1388         if (pvt->ce_count_available) {
1389                 /* Updates CE counters */
1390
1391                 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1392                 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1393                 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1394
1395                 if (add2 < 0)
1396                         add2 += 0x7fff;
1397                 pvt->rdimm_ce_count[chan][2] += add2;
1398
1399                 if (add1 < 0)
1400                         add1 += 0x7fff;
1401                 pvt->rdimm_ce_count[chan][1] += add1;
1402
1403                 if (add0 < 0)
1404                         add0 += 0x7fff;
1405                 pvt->rdimm_ce_count[chan][0] += add0;
1406         } else
1407                 pvt->ce_count_available = 1;
1408
1409         /* Store the new values */
1410         pvt->rdimm_last_ce_count[chan][2] = new2;
1411         pvt->rdimm_last_ce_count[chan][1] = new1;
1412         pvt->rdimm_last_ce_count[chan][0] = new0;
1413
1414         /*updated the edac core */
1415         if (add0 != 0)
1416                 i7core_rdimm_update_csrow(mci, chan, 0, add0);
1417         if (add1 != 0)
1418                 i7core_rdimm_update_csrow(mci, chan, 1, add1);
1419         if (add2 != 0)
1420                 i7core_rdimm_update_csrow(mci, chan, 2, add2);
1421
1422 }
1423
1424 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1425 {
1426         struct i7core_pvt *pvt = mci->pvt_info;
1427         u32 rcv[3][2];
1428         int i, new0, new1, new2;
1429
1430         /*Read DEV 3: FUN 2:  MC_COR_ECC_CNT regs directly*/
1431         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1432                                                                 &rcv[0][0]);
1433         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1434                                                                 &rcv[0][1]);
1435         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1436                                                                 &rcv[1][0]);
1437         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1438                                                                 &rcv[1][1]);
1439         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1440                                                                 &rcv[2][0]);
1441         pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1442                                                                 &rcv[2][1]);
1443         for (i = 0 ; i < 3; i++) {
1444                 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1445                         (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1446                 /*if the channel has 3 dimms*/
1447                 if (pvt->channel[i].dimms > 2) {
1448                         new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1449                         new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1450                         new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1451                 } else {
1452                         new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1453                                         DIMM_BOT_COR_ERR(rcv[i][0]);
1454                         new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1455                                         DIMM_BOT_COR_ERR(rcv[i][1]);
1456                         new2 = 0;
1457                 }
1458
1459                 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1460         }
1461 }
1462
1463 /* This function is based on the device 3 function 4 registers as described on:
1464  * Intel Xeon Processor 5500 Series Datasheet Volume 2
1465  *      http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1466  * also available at:
1467  *      http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1468  */
1469 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1470 {
1471         struct i7core_pvt *pvt = mci->pvt_info;
1472         u32 rcv1, rcv0;
1473         int new0, new1, new2;
1474
1475         if (!pvt->pci_mcr[4]) {
1476                 debugf0("%s MCR registers not found\n", __func__);
1477                 return;
1478         }
1479
1480         /* Corrected test errors */
1481         pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1482         pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1483
1484         /* Store the new values */
1485         new2 = DIMM2_COR_ERR(rcv1);
1486         new1 = DIMM1_COR_ERR(rcv0);
1487         new0 = DIMM0_COR_ERR(rcv0);
1488
1489         /* Updates CE counters if it is not the first time here */
1490         if (pvt->ce_count_available) {
1491                 /* Updates CE counters */
1492                 int add0, add1, add2;
1493
1494                 add2 = new2 - pvt->udimm_last_ce_count[2];
1495                 add1 = new1 - pvt->udimm_last_ce_count[1];
1496                 add0 = new0 - pvt->udimm_last_ce_count[0];
1497
1498                 if (add2 < 0)
1499                         add2 += 0x7fff;
1500                 pvt->udimm_ce_count[2] += add2;
1501
1502                 if (add1 < 0)
1503                         add1 += 0x7fff;
1504                 pvt->udimm_ce_count[1] += add1;
1505
1506                 if (add0 < 0)
1507                         add0 += 0x7fff;
1508                 pvt->udimm_ce_count[0] += add0;
1509
1510                 if (add0 | add1 | add2)
1511                         i7core_printk(KERN_ERR, "New Corrected error(s): "
1512                                       "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1513                                       add0, add1, add2);
1514         } else
1515                 pvt->ce_count_available = 1;
1516
1517         /* Store the new values */
1518         pvt->udimm_last_ce_count[2] = new2;
1519         pvt->udimm_last_ce_count[1] = new1;
1520         pvt->udimm_last_ce_count[0] = new0;
1521 }
1522
1523 /*
1524  * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1525  * Architectures Software Developer’s Manual Volume 3B.
1526  * Nehalem are defined as family 0x06, model 0x1a
1527  *
1528  * The MCA registers used here are the following ones:
1529  *     struct mce field MCA Register
1530  *     m->status        MSR_IA32_MC8_STATUS
1531  *     m->addr          MSR_IA32_MC8_ADDR
1532  *     m->misc          MSR_IA32_MC8_MISC
1533  * In the case of Nehalem, the error information is masked at .status and .misc
1534  * fields
1535  */
1536 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1537                                     struct mce *m)
1538 {
1539         struct i7core_pvt *pvt = mci->pvt_info;
1540         char *type, *optype, *err, *msg;
1541         unsigned long error = m->status & 0x1ff0000l;
1542         u32 optypenum = (m->status >> 4) & 0x07;
1543         u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1544         u32 dimm = (m->misc >> 16) & 0x3;
1545         u32 channel = (m->misc >> 18) & 0x3;
1546         u32 syndrome = m->misc >> 32;
1547         u32 errnum = find_first_bit(&error, 32);
1548         int csrow;
1549
1550         if (m->mcgstatus & 1)
1551                 type = "FATAL";
1552         else
1553                 type = "NON_FATAL";
1554
1555         switch (optypenum) {
1556         case 0:
1557                 optype = "generic undef request";
1558                 break;
1559         case 1:
1560                 optype = "read error";
1561                 break;
1562         case 2:
1563                 optype = "write error";
1564                 break;
1565         case 3:
1566                 optype = "addr/cmd error";
1567                 break;
1568         case 4:
1569                 optype = "scrubbing error";
1570                 break;
1571         default:
1572                 optype = "reserved";
1573                 break;
1574         }
1575
1576         switch (errnum) {
1577         case 16:
1578                 err = "read ECC error";
1579                 break;
1580         case 17:
1581                 err = "RAS ECC error";
1582                 break;
1583         case 18:
1584                 err = "write parity error";
1585                 break;
1586         case 19:
1587                 err = "redundacy loss";
1588                 break;
1589         case 20:
1590                 err = "reserved";
1591                 break;
1592         case 21:
1593                 err = "memory range error";
1594                 break;
1595         case 22:
1596                 err = "RTID out of range";
1597                 break;
1598         case 23:
1599                 err = "address parity error";
1600                 break;
1601         case 24:
1602                 err = "byte enable parity error";
1603                 break;
1604         default:
1605                 err = "unknown";
1606         }
1607
1608         /* FIXME: should convert addr into bank and rank information */
1609         msg = kasprintf(GFP_ATOMIC,
1610                 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1611                 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1612                 type, (long long) m->addr, m->cpu, dimm, channel,
1613                 syndrome, core_err_cnt, (long long)m->status,
1614                 (long long)m->misc, optype, err);
1615
1616         debugf0("%s", msg);
1617
1618         csrow = pvt->csrow_map[channel][dimm];
1619
1620         /* Call the helper to output message */
1621         if (m->mcgstatus & 1)
1622                 edac_mc_handle_fbd_ue(mci, csrow, 0,
1623                                 0 /* FIXME: should be channel here */, msg);
1624         else if (!pvt->is_registered)
1625                 edac_mc_handle_fbd_ce(mci, csrow,
1626                                 0 /* FIXME: should be channel here */, msg);
1627
1628         kfree(msg);
1629 }
1630
1631 /*
1632  *      i7core_check_error      Retrieve and process errors reported by the
1633  *                              hardware. Called by the Core module.
1634  */
1635 static void i7core_check_error(struct mem_ctl_info *mci)
1636 {
1637         struct i7core_pvt *pvt = mci->pvt_info;
1638         int i;
1639         unsigned count = 0;
1640         struct mce *m = NULL;
1641         unsigned long flags;
1642
1643         /* Copy all mce errors into a temporary buffer */
1644         spin_lock_irqsave(&pvt->mce_lock, flags);
1645         if (pvt->mce_count) {
1646                 m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC);
1647
1648                 if (m) {
1649                         count = pvt->mce_count;
1650                         memcpy(m, &pvt->mce_entry, sizeof(*m) * count);
1651                 }
1652                 pvt->mce_count = 0;
1653         }
1654
1655         spin_unlock_irqrestore(&pvt->mce_lock, flags);
1656
1657         /* proccess mcelog errors */
1658         for (i = 0; i < count; i++)
1659                 i7core_mce_output_error(mci, &m[i]);
1660
1661         kfree(m);
1662
1663         /* check memory count errors */
1664         if (!pvt->is_registered)
1665                 i7core_udimm_check_mc_ecc_err(mci);
1666         else
1667                 i7core_rdimm_check_mc_ecc_err(mci);
1668 }
1669
1670 /*
1671  * i7core_mce_check_error       Replicates mcelog routine to get errors
1672  *                              This routine simply queues mcelog errors, and
1673  *                              return. The error itself should be handled later
1674  *                              by i7core_check_error.
1675  */
1676 static int i7core_mce_check_error(void *priv, struct mce *mce)
1677 {
1678         struct mem_ctl_info *mci = priv;
1679         struct i7core_pvt *pvt = mci->pvt_info;
1680         unsigned long flags;
1681
1682         /*
1683          * Just let mcelog handle it if the error is
1684          * outside the memory controller
1685          */
1686         if (((mce->status & 0xffff) >> 7) != 1)
1687                 return 0;
1688
1689         /* Bank 8 registers are the only ones that we know how to handle */
1690         if (mce->bank != 8)
1691                 return 0;
1692
1693         /* Only handle if it is the right mc controller */
1694         if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) {
1695                 debugf0("mc%d: ignoring mce log for socket %d. "
1696                         "Another mc should get it.\n",
1697                         pvt->i7core_dev->socket,
1698                         cpu_data(mce->cpu).phys_proc_id);
1699                 return 0;
1700         }
1701
1702         spin_lock_irqsave(&pvt->mce_lock, flags);
1703         if (pvt->mce_count < MCE_LOG_LEN) {
1704                 memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
1705                 pvt->mce_count++;
1706         }
1707         spin_unlock_irqrestore(&pvt->mce_lock, flags);
1708
1709         /* Handle fatal errors immediately */
1710         if (mce->mcgstatus & 1)
1711                 i7core_check_error(mci);
1712
1713         /* Advice mcelog that the error were handled */
1714         return 1;
1715 }
1716
1717 static int i7core_register_mci(struct i7core_dev *i7core_dev,
1718                                int num_channels, int num_csrows)
1719 {
1720         struct mem_ctl_info *mci;
1721         struct i7core_pvt *pvt;
1722         int csrow = 0;
1723         int rc;
1724
1725         /* allocate a new MC control structure */
1726         mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1727                             i7core_dev->socket);
1728         if (unlikely(!mci))
1729                 return -ENOMEM;
1730
1731         debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1732
1733         /* record ptr to the generic device */
1734         mci->dev = &i7core_dev->pdev[0]->dev;
1735
1736         pvt = mci->pvt_info;
1737         memset(pvt, 0, sizeof(*pvt));
1738
1739         /*
1740          * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1741          * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1742          * memory channels
1743          */
1744         mci->mtype_cap = MEM_FLAG_DDR3;
1745         mci->edac_ctl_cap = EDAC_FLAG_NONE;
1746         mci->edac_cap = EDAC_FLAG_NONE;
1747         mci->mod_name = "i7core_edac.c";
1748         mci->mod_ver = I7CORE_REVISION;
1749         mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1750                                   i7core_dev->socket);
1751         mci->dev_name = pci_name(i7core_dev->pdev[0]);
1752         mci->ctl_page_to_phys = NULL;
1753         mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
1754         /* Set the function pointer to an actual operation function */
1755         mci->edac_check = i7core_check_error;
1756
1757         /* Store pci devices at mci for faster access */
1758         rc = mci_bind_devs(mci, i7core_dev);
1759         if (unlikely(rc < 0))
1760                 goto fail;
1761
1762         /* Get dimm basic config */
1763         get_dimm_config(mci, &csrow);
1764
1765         /* add this new MC control structure to EDAC's list of MCs */
1766         if (unlikely(edac_mc_add_mc(mci))) {
1767                 debugf0("MC: " __FILE__
1768                         ": %s(): failed edac_mc_add_mc()\n", __func__);
1769                 /* FIXME: perhaps some code should go here that disables error
1770                  * reporting if we just enabled it
1771                  */
1772
1773                 rc = -EINVAL;
1774                 goto fail;
1775         }
1776
1777         /* allocating generic PCI control info */
1778         i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
1779                                                  EDAC_MOD_STR);
1780         if (unlikely(!i7core_pci)) {
1781                 printk(KERN_WARNING
1782                         "%s(): Unable to create PCI control\n",
1783                         __func__);
1784                 printk(KERN_WARNING
1785                         "%s(): PCI error report via EDAC not setup\n",
1786                         __func__);
1787         }
1788
1789         /* Default error mask is any memory */
1790         pvt->inject.channel = 0;
1791         pvt->inject.dimm = -1;
1792         pvt->inject.rank = -1;
1793         pvt->inject.bank = -1;
1794         pvt->inject.page = -1;
1795         pvt->inject.col = -1;
1796
1797         /* Registers on edac_mce in order to receive memory errors */
1798         pvt->edac_mce.priv = mci;
1799         pvt->edac_mce.check_error = i7core_mce_check_error;
1800         spin_lock_init(&pvt->mce_lock);
1801
1802         rc = edac_mce_register(&pvt->edac_mce);
1803         if (unlikely(rc < 0)) {
1804                 debugf0("MC: " __FILE__
1805                         ": %s(): failed edac_mce_register()\n", __func__);
1806         }
1807
1808 fail:
1809         edac_mc_free(mci);
1810         return rc;
1811 }
1812
1813 /*
1814  *      i7core_probe    Probe for ONE instance of device to see if it is
1815  *                      present.
1816  *      return:
1817  *              0 for FOUND a device
1818  *              < 0 for error code
1819  */
1820 static int __devinit i7core_probe(struct pci_dev *pdev,
1821                                   const struct pci_device_id *id)
1822 {
1823         int dev_idx = id->driver_data;
1824         int rc;
1825         struct i7core_dev *i7core_dev;
1826
1827         /*
1828          * All memory controllers are allocated at the first pass.
1829          */
1830         if (unlikely(dev_idx >= 1))
1831                 return -EINVAL;
1832
1833         /* get the pci devices we want to reserve for our use */
1834         mutex_lock(&i7core_edac_lock);
1835         rc = i7core_get_devices();
1836         if (unlikely(rc < 0))
1837                 goto fail0;
1838
1839         list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
1840                 int channels;
1841                 int csrows;
1842
1843                 /* Check the number of active and not disabled channels */
1844                 rc = i7core_get_active_channels(i7core_dev->socket,
1845                                                 &channels, &csrows);
1846                 if (unlikely(rc < 0))
1847                         goto fail1;
1848
1849                 rc = i7core_register_mci(i7core_dev, channels, csrows);
1850                 if (unlikely(rc < 0))
1851                         goto fail1;
1852         }
1853
1854         i7core_printk(KERN_INFO, "Driver loaded.\n");
1855
1856         mutex_unlock(&i7core_edac_lock);
1857         return 0;
1858
1859 fail1:
1860         i7core_put_all_devices();
1861 fail0:
1862         mutex_unlock(&i7core_edac_lock);
1863         return rc;
1864 }
1865
1866 /*
1867  *      i7core_remove   destructor for one instance of device
1868  *
1869  */
1870 static void __devexit i7core_remove(struct pci_dev *pdev)
1871 {
1872         struct mem_ctl_info *mci;
1873         struct i7core_dev *i7core_dev, *tmp;
1874
1875         debugf0(__FILE__ ": %s()\n", __func__);
1876
1877         if (i7core_pci)
1878                 edac_pci_release_generic_ctl(i7core_pci);
1879
1880         /*
1881          * we have a trouble here: pdev value for removal will be wrong, since
1882          * it will point to the X58 register used to detect that the machine
1883          * is a Nehalem or upper design. However, due to the way several PCI
1884          * devices are grouped together to provide MC functionality, we need
1885          * to use a different method for releasing the devices
1886          */
1887
1888         mutex_lock(&i7core_edac_lock);
1889         list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1890                 mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
1891                 if (mci) {
1892                         struct i7core_pvt *pvt = mci->pvt_info;
1893
1894                         i7core_dev = pvt->i7core_dev;
1895                         edac_mce_unregister(&pvt->edac_mce);
1896                         kfree(mci->ctl_name);
1897                         edac_mc_free(mci);
1898                         i7core_put_devices(i7core_dev);
1899                 } else {
1900                         i7core_printk(KERN_ERR,
1901                                       "Couldn't find mci for socket %d\n",
1902                                       i7core_dev->socket);
1903                 }
1904         }
1905         mutex_unlock(&i7core_edac_lock);
1906 }
1907
1908 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
1909
1910 /*
1911  *      i7core_driver   pci_driver structure for this module
1912  *
1913  */
1914 static struct pci_driver i7core_driver = {
1915         .name     = "i7core_edac",
1916         .probe    = i7core_probe,
1917         .remove   = __devexit_p(i7core_remove),
1918         .id_table = i7core_pci_tbl,
1919 };
1920
1921 /*
1922  *      i7core_init             Module entry function
1923  *                      Try to initialize this module for its devices
1924  */
1925 static int __init i7core_init(void)
1926 {
1927         int pci_rc;
1928
1929         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1930
1931         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1932         opstate_init();
1933
1934         i7core_xeon_pci_fixup();
1935
1936         pci_rc = pci_register_driver(&i7core_driver);
1937
1938         if (pci_rc >= 0)
1939                 return 0;
1940
1941         i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
1942                       pci_rc);
1943
1944         return pci_rc;
1945 }
1946
1947 /*
1948  *      i7core_exit()   Module exit function
1949  *                      Unregister the driver
1950  */
1951 static void __exit i7core_exit(void)
1952 {
1953         debugf2("MC: " __FILE__ ": %s()\n", __func__);
1954         pci_unregister_driver(&i7core_driver);
1955 }
1956
1957 module_init(i7core_init);
1958 module_exit(i7core_exit);
1959
1960 MODULE_LICENSE("GPL");
1961 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1962 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1963 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
1964                    I7CORE_REVISION);
1965
1966 module_param(edac_op_state, int, 0444);
1967 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");