1 /* Intel i7 core/Nehalem Memory Controller kernel module
3 * This driver supports yhe memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
11 * Copyright (c) 2009-2010 by:
12 * Mauro Carvalho Chehab <mchehab@redhat.com>
14 * Red Hat Inc. http://www.redhat.com
16 * Forked and adapted from the i5400_edac driver
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/edac.h>
35 #include <linux/mmzone.h>
36 #include <linux/edac_mce.h>
37 #include <linux/smp.h>
38 #include <asm/processor.h>
40 #include "edac_core.h"
43 static LIST_HEAD(i7core_edac_list);
44 static DEFINE_MUTEX(i7core_edac_lock);
48 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
49 * registers start at bus 255, and are not reported by BIOS.
50 * We currently find devices with only 2 sockets. In order to support more QPI
51 * Quick Path Interconnect, just increment this number.
53 #define MAX_SOCKET_BUSES 2
57 * Alter this version for the module when modifications are made
59 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
60 #define EDAC_MOD_STR "i7core_edac"
65 #define i7core_printk(level, fmt, arg...) \
66 edac_printk(level, "i7core", fmt, ##arg)
68 #define i7core_mc_printk(mci, level, fmt, arg...) \
69 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
72 * i7core Memory Controller Registers
75 /* OFFSETS for Device 0 Function 0 */
77 #define MC_CFG_CONTROL 0x90
79 /* OFFSETS for Device 3 Function 0 */
81 #define MC_CONTROL 0x48
82 #define MC_STATUS 0x4c
83 #define MC_MAX_DOD 0x64
86 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
87 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
90 #define MC_TEST_ERR_RCV1 0x60
91 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
93 #define MC_TEST_ERR_RCV0 0x64
94 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
95 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
97 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
98 #define MC_COR_ECC_CNT_0 0x80
99 #define MC_COR_ECC_CNT_1 0x84
100 #define MC_COR_ECC_CNT_2 0x88
101 #define MC_COR_ECC_CNT_3 0x8c
102 #define MC_COR_ECC_CNT_4 0x90
103 #define MC_COR_ECC_CNT_5 0x94
105 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
106 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
109 /* OFFSETS for Devices 4,5 and 6 Function 0 */
111 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
112 #define THREE_DIMMS_PRESENT (1 << 24)
113 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
114 #define QUAD_RANK_PRESENT (1 << 22)
115 #define REGISTERED_DIMM (1 << 15)
117 #define MC_CHANNEL_MAPPER 0x60
118 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
119 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
121 #define MC_CHANNEL_RANK_PRESENT 0x7c
122 #define RANK_PRESENT_MASK 0xffff
124 #define MC_CHANNEL_ADDR_MATCH 0xf0
125 #define MC_CHANNEL_ERROR_MASK 0xf8
126 #define MC_CHANNEL_ERROR_INJECT 0xfc
127 #define INJECT_ADDR_PARITY 0x10
128 #define INJECT_ECC 0x08
129 #define MASK_CACHELINE 0x06
130 #define MASK_FULL_CACHELINE 0x06
131 #define MASK_MSB32_CACHELINE 0x04
132 #define MASK_LSB32_CACHELINE 0x02
133 #define NO_MASK_CACHELINE 0x00
134 #define REPEAT_EN 0x01
136 /* OFFSETS for Devices 4,5 and 6 Function 1 */
138 #define MC_DOD_CH_DIMM0 0x48
139 #define MC_DOD_CH_DIMM1 0x4c
140 #define MC_DOD_CH_DIMM2 0x50
141 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
142 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
143 #define DIMM_PRESENT_MASK (1 << 9)
144 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
145 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
146 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
147 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
148 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
149 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
150 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
151 #define MC_DOD_NUMCOL_MASK 3
152 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
154 #define MC_RANK_PRESENT 0x7c
156 #define MC_SAG_CH_0 0x80
157 #define MC_SAG_CH_1 0x84
158 #define MC_SAG_CH_2 0x88
159 #define MC_SAG_CH_3 0x8c
160 #define MC_SAG_CH_4 0x90
161 #define MC_SAG_CH_5 0x94
162 #define MC_SAG_CH_6 0x98
163 #define MC_SAG_CH_7 0x9c
165 #define MC_RIR_LIMIT_CH_0 0x40
166 #define MC_RIR_LIMIT_CH_1 0x44
167 #define MC_RIR_LIMIT_CH_2 0x48
168 #define MC_RIR_LIMIT_CH_3 0x4C
169 #define MC_RIR_LIMIT_CH_4 0x50
170 #define MC_RIR_LIMIT_CH_5 0x54
171 #define MC_RIR_LIMIT_CH_6 0x58
172 #define MC_RIR_LIMIT_CH_7 0x5C
173 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
175 #define MC_RIR_WAY_CH 0x80
176 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
177 #define MC_RIR_WAY_RANK_MASK 0x7
184 #define MAX_DIMMS 3 /* Max DIMMS per channel */
185 #define MAX_MCR_FUNC 4
186 #define MAX_CHAN_FUNC 3
196 struct i7core_inject {
203 /* Error address mask */
204 int channel, dimm, rank, bank, page, col;
207 struct i7core_channel {
212 struct pci_id_descr {
219 struct pci_id_table {
220 const struct pci_id_descr *descr;
225 struct list_head list;
227 struct pci_dev **pdev;
229 struct mem_ctl_info *mci;
233 struct pci_dev *pci_noncore;
234 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
235 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
237 struct i7core_dev *i7core_dev;
239 struct i7core_info info;
240 struct i7core_inject inject;
241 struct i7core_channel channel[NUM_CHANS];
243 int channels; /* Number of active channels */
245 int ce_count_available;
246 int csrow_map[NUM_CHANS][MAX_DIMMS];
248 /* ECC corrected errors counts per udimm */
249 unsigned long udimm_ce_count[MAX_DIMMS];
250 int udimm_last_ce_count[MAX_DIMMS];
251 /* ECC corrected errors counts per rdimm */
252 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
253 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
255 unsigned int is_registered;
258 struct edac_mce edac_mce;
260 /* Fifo double buffers */
261 struct mce mce_entry[MCE_LOG_LEN];
262 struct mce mce_outentry[MCE_LOG_LEN];
264 /* Fifo in/out counters */
265 unsigned mce_in, mce_out;
267 /* Count indicator to show errors not got */
268 unsigned mce_overrun;
270 /* Struct to control EDAC polling */
271 struct edac_pci_ctl_info *i7core_pci;
274 #define PCI_DESCR(device, function, device_id) \
276 .func = (function), \
277 .dev_id = (device_id)
279 static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
280 /* Memory controller */
281 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
282 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
283 /* Exists only for RDIMM */
284 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
285 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
288 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
289 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
290 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
291 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
294 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
295 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
296 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
297 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
300 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
301 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
302 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
303 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
305 /* Generic Non-core registers */
307 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
308 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
309 * the probing code needs to test for the other address in case of
310 * failure of this one
312 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
316 static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
317 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
318 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
319 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
321 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
322 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
323 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
324 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
326 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
327 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
328 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
329 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
332 * This is the PCI device has an alternate address on some
333 * processors like Core i7 860
335 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
338 static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
339 /* Memory controller */
340 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
341 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
342 /* Exists only for RDIMM */
343 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
344 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
347 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
348 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
349 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
350 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
353 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
354 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
355 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
356 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
359 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
360 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
361 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
362 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
364 /* Generic Non-core registers */
365 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
369 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
370 static const struct pci_id_table pci_dev_table[] = {
371 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
372 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
373 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
377 * pci_device_id table for which devices we are looking for
379 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
380 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
381 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
382 {0,} /* 0 terminated list. */
385 /****************************************************************************
386 Anciliary status routines
387 ****************************************************************************/
389 /* MC_CONTROL bits */
390 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
391 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
394 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
395 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
397 /* MC_MAX_DOD read functions */
398 static inline int numdimms(u32 dimms)
400 return (dimms & 0x3) + 1;
403 static inline int numrank(u32 rank)
405 static int ranks[4] = { 1, 2, 4, -EINVAL };
407 return ranks[rank & 0x3];
410 static inline int numbank(u32 bank)
412 static int banks[4] = { 4, 8, 16, -EINVAL };
414 return banks[bank & 0x3];
417 static inline int numrow(u32 row)
419 static int rows[8] = {
420 1 << 12, 1 << 13, 1 << 14, 1 << 15,
421 1 << 16, -EINVAL, -EINVAL, -EINVAL,
424 return rows[row & 0x7];
427 static inline int numcol(u32 col)
429 static int cols[8] = {
430 1 << 10, 1 << 11, 1 << 12, -EINVAL,
432 return cols[col & 0x3];
435 static struct i7core_dev *get_i7core_dev(u8 socket)
437 struct i7core_dev *i7core_dev;
439 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
440 if (i7core_dev->socket == socket)
447 /****************************************************************************
448 Memory check routines
449 ****************************************************************************/
450 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
453 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
459 for (i = 0; i < i7core_dev->n_devs; i++) {
460 if (!i7core_dev->pdev[i])
463 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
464 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
465 return i7core_dev->pdev[i];
473 * i7core_get_active_channels() - gets the number of channels and csrows
474 * @socket: Quick Path Interconnect socket
475 * @channels: Number of channels that will be returned
476 * @csrows: Number of csrows found
478 * Since EDAC core needs to know in advance the number of available channels
479 * and csrows, in order to allocate memory for csrows/channels, it is needed
480 * to run two similar steps. At the first step, implemented on this function,
481 * it checks the number of csrows/channels present at one socket.
482 * this is used in order to properly allocate the size of mci components.
484 * It should be noticed that none of the current available datasheets explain
485 * or even mention how csrows are seen by the memory controller. So, we need
486 * to add a fake description for csrows.
487 * So, this driver is attributing one DIMM memory for one csrow.
489 static int i7core_get_active_channels(const u8 socket, unsigned *channels,
492 struct pci_dev *pdev = NULL;
499 pdev = get_pdev_slot_func(socket, 3, 0);
501 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
506 /* Device 3 function 0 reads */
507 pci_read_config_dword(pdev, MC_STATUS, &status);
508 pci_read_config_dword(pdev, MC_CONTROL, &control);
510 for (i = 0; i < NUM_CHANS; i++) {
512 /* Check if the channel is active */
513 if (!(control & (1 << (8 + i))))
516 /* Check if the channel is disabled */
517 if (status & (1 << i))
520 pdev = get_pdev_slot_func(socket, i + 4, 1);
522 i7core_printk(KERN_ERR, "Couldn't find socket %d "
527 /* Devices 4-6 function 1 */
528 pci_read_config_dword(pdev,
529 MC_DOD_CH_DIMM0, &dimm_dod[0]);
530 pci_read_config_dword(pdev,
531 MC_DOD_CH_DIMM1, &dimm_dod[1]);
532 pci_read_config_dword(pdev,
533 MC_DOD_CH_DIMM2, &dimm_dod[2]);
537 for (j = 0; j < 3; j++) {
538 if (!DIMM_PRESENT(dimm_dod[j]))
544 debugf0("Number of active channels on socket %d: %d\n",
550 static int get_dimm_config(const struct mem_ctl_info *mci, int *csrow)
552 struct i7core_pvt *pvt = mci->pvt_info;
553 struct csrow_info *csr;
554 struct pci_dev *pdev;
556 unsigned long last_page = 0;
560 /* Get data from the MC register, function 0 */
561 pdev = pvt->pci_mcr[0];
565 /* Device 3 function 0 reads */
566 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
567 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
568 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
569 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
571 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
572 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
573 pvt->info.max_dod, pvt->info.ch_map);
575 if (ECC_ENABLED(pvt)) {
576 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
578 mode = EDAC_S8ECD8ED;
580 mode = EDAC_S4ECD4ED;
582 debugf0("ECC disabled\n");
586 /* FIXME: need to handle the error codes */
587 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
589 numdimms(pvt->info.max_dod),
590 numrank(pvt->info.max_dod >> 2),
591 numbank(pvt->info.max_dod >> 4),
592 numrow(pvt->info.max_dod >> 6),
593 numcol(pvt->info.max_dod >> 9));
595 for (i = 0; i < NUM_CHANS; i++) {
596 u32 data, dimm_dod[3], value[8];
598 if (!pvt->pci_ch[i][0])
601 if (!CH_ACTIVE(pvt, i)) {
602 debugf0("Channel %i is not active\n", i);
605 if (CH_DISABLED(pvt, i)) {
606 debugf0("Channel %i is disabled\n", i);
610 /* Devices 4-6 function 0 */
611 pci_read_config_dword(pvt->pci_ch[i][0],
612 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
614 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
617 if (data & REGISTERED_DIMM)
622 if (data & THREE_DIMMS_PRESENT)
623 pvt->channel[i].dimms = 3;
624 else if (data & SINGLE_QUAD_RANK_PRESENT)
625 pvt->channel[i].dimms = 1;
627 pvt->channel[i].dimms = 2;
630 /* Devices 4-6 function 1 */
631 pci_read_config_dword(pvt->pci_ch[i][1],
632 MC_DOD_CH_DIMM0, &dimm_dod[0]);
633 pci_read_config_dword(pvt->pci_ch[i][1],
634 MC_DOD_CH_DIMM1, &dimm_dod[1]);
635 pci_read_config_dword(pvt->pci_ch[i][1],
636 MC_DOD_CH_DIMM2, &dimm_dod[2]);
638 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
639 "%d ranks, %cDIMMs\n",
641 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
643 pvt->channel[i].ranks,
644 (data & REGISTERED_DIMM) ? 'R' : 'U');
646 for (j = 0; j < 3; j++) {
647 u32 banks, ranks, rows, cols;
650 if (!DIMM_PRESENT(dimm_dod[j]))
653 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
654 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
655 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
656 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
658 /* DDR3 has 8 I/O banks */
659 size = (rows * cols * banks * ranks) >> (20 - 3);
661 pvt->channel[i].dimms++;
663 debugf0("\tdimm %d %d Mb offset: %x, "
664 "bank: %d, rank: %d, row: %#x, col: %#x\n",
666 RANKOFFSET(dimm_dod[j]),
667 banks, ranks, rows, cols);
669 npages = MiB_TO_PAGES(size);
671 csr = &mci->csrows[*csrow];
672 csr->first_page = last_page + 1;
674 csr->last_page = last_page;
675 csr->nr_pages = npages;
679 csr->csrow_idx = *csrow;
680 csr->nr_channels = 1;
682 csr->channels[0].chan_idx = i;
683 csr->channels[0].ce_count = 0;
685 pvt->csrow_map[i][j] = *csrow;
695 csr->dtype = DEV_X16;
698 csr->dtype = DEV_UNKNOWN;
701 csr->edac_mode = mode;
707 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
708 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
709 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
710 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
711 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
712 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
713 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
714 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
715 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
716 for (j = 0; j < 8; j++)
717 debugf1("\t\t%#x\t%#x\t%#x\n",
718 (value[j] >> 27) & 0x1,
719 (value[j] >> 24) & 0x7,
720 (value[j] && ((1 << 24) - 1)));
726 /****************************************************************************
727 Error insertion routines
728 ****************************************************************************/
730 /* The i7core has independent error injection features per channel.
731 However, to have a simpler code, we don't allow enabling error injection
732 on more than one channel.
733 Also, since a change at an inject parameter will be applied only at enable,
734 we're disabling error injection on all write calls to the sysfs nodes that
735 controls the error code injection.
737 static int disable_inject(const struct mem_ctl_info *mci)
739 struct i7core_pvt *pvt = mci->pvt_info;
741 pvt->inject.enable = 0;
743 if (!pvt->pci_ch[pvt->inject.channel][0])
746 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
747 MC_CHANNEL_ERROR_INJECT, 0);
753 * i7core inject inject.section
755 * accept and store error injection inject.section value
756 * bit 0 - refers to the lower 32-byte half cacheline
757 * bit 1 - refers to the upper 32-byte half cacheline
759 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
760 const char *data, size_t count)
762 struct i7core_pvt *pvt = mci->pvt_info;
766 if (pvt->inject.enable)
769 rc = strict_strtoul(data, 10, &value);
770 if ((rc < 0) || (value > 3))
773 pvt->inject.section = (u32) value;
777 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
780 struct i7core_pvt *pvt = mci->pvt_info;
781 return sprintf(data, "0x%08x\n", pvt->inject.section);
787 * accept and store error injection inject.section value
788 * bit 0 - repeat enable - Enable error repetition
789 * bit 1 - inject ECC error
790 * bit 2 - inject parity error
792 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
793 const char *data, size_t count)
795 struct i7core_pvt *pvt = mci->pvt_info;
799 if (pvt->inject.enable)
802 rc = strict_strtoul(data, 10, &value);
803 if ((rc < 0) || (value > 7))
806 pvt->inject.type = (u32) value;
810 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
813 struct i7core_pvt *pvt = mci->pvt_info;
814 return sprintf(data, "0x%08x\n", pvt->inject.type);
818 * i7core_inject_inject.eccmask_store
820 * The type of error (UE/CE) will depend on the inject.eccmask value:
821 * Any bits set to a 1 will flip the corresponding ECC bit
822 * Correctable errors can be injected by flipping 1 bit or the bits within
823 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
824 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
825 * uncorrectable error to be injected.
827 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
828 const char *data, size_t count)
830 struct i7core_pvt *pvt = mci->pvt_info;
834 if (pvt->inject.enable)
837 rc = strict_strtoul(data, 10, &value);
841 pvt->inject.eccmask = (u32) value;
845 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
848 struct i7core_pvt *pvt = mci->pvt_info;
849 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
855 * The type of error (UE/CE) will depend on the inject.eccmask value:
856 * Any bits set to a 1 will flip the corresponding ECC bit
857 * Correctable errors can be injected by flipping 1 bit or the bits within
858 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
859 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
860 * uncorrectable error to be injected.
863 #define DECLARE_ADDR_MATCH(param, limit) \
864 static ssize_t i7core_inject_store_##param( \
865 struct mem_ctl_info *mci, \
866 const char *data, size_t count) \
868 struct i7core_pvt *pvt; \
872 debugf1("%s()\n", __func__); \
873 pvt = mci->pvt_info; \
875 if (pvt->inject.enable) \
876 disable_inject(mci); \
878 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
881 rc = strict_strtoul(data, 10, &value); \
882 if ((rc < 0) || (value >= limit)) \
886 pvt->inject.param = value; \
891 static ssize_t i7core_inject_show_##param( \
892 struct mem_ctl_info *mci, \
895 struct i7core_pvt *pvt; \
897 pvt = mci->pvt_info; \
898 debugf1("%s() pvt=%p\n", __func__, pvt); \
899 if (pvt->inject.param < 0) \
900 return sprintf(data, "any\n"); \
902 return sprintf(data, "%d\n", pvt->inject.param);\
905 #define ATTR_ADDR_MATCH(param) \
909 .mode = (S_IRUGO | S_IWUSR) \
911 .show = i7core_inject_show_##param, \
912 .store = i7core_inject_store_##param, \
915 DECLARE_ADDR_MATCH(channel, 3);
916 DECLARE_ADDR_MATCH(dimm, 3);
917 DECLARE_ADDR_MATCH(rank, 4);
918 DECLARE_ADDR_MATCH(bank, 32);
919 DECLARE_ADDR_MATCH(page, 0x10000);
920 DECLARE_ADDR_MATCH(col, 0x4000);
922 static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
927 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
928 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
931 for (count = 0; count < 10; count++) {
934 pci_write_config_dword(dev, where, val);
935 pci_read_config_dword(dev, where, &read);
941 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
942 "write=%08x. Read=%08x\n",
943 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
950 * This routine prepares the Memory Controller for error injection.
951 * The error will be injected when some process tries to write to the
952 * memory that matches the given criteria.
953 * The criteria can be set in terms of a mask where dimm, rank, bank, page
954 * and col can be specified.
955 * A -1 value for any of the mask items will make the MCU to ignore
956 * that matching criteria for error injection.
958 * It should be noticed that the error will only happen after a write operation
959 * on a memory that matches the condition. if REPEAT_EN is not enabled at
960 * inject mask, then it will produce just one error. Otherwise, it will repeat
961 * until the injectmask would be cleaned.
963 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
964 * is reliable enough to check if the MC is using the
965 * three channels. However, this is not clear at the datasheet.
967 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
968 const char *data, size_t count)
970 struct i7core_pvt *pvt = mci->pvt_info;
976 if (!pvt->pci_ch[pvt->inject.channel][0])
979 rc = strict_strtoul(data, 10, &enable);
984 pvt->inject.enable = 1;
990 /* Sets pvt->inject.dimm mask */
991 if (pvt->inject.dimm < 0)
994 if (pvt->channel[pvt->inject.channel].dimms > 2)
995 mask |= (pvt->inject.dimm & 0x3LL) << 35;
997 mask |= (pvt->inject.dimm & 0x1LL) << 36;
1000 /* Sets pvt->inject.rank mask */
1001 if (pvt->inject.rank < 0)
1004 if (pvt->channel[pvt->inject.channel].dimms > 2)
1005 mask |= (pvt->inject.rank & 0x1LL) << 34;
1007 mask |= (pvt->inject.rank & 0x3LL) << 34;
1010 /* Sets pvt->inject.bank mask */
1011 if (pvt->inject.bank < 0)
1014 mask |= (pvt->inject.bank & 0x15LL) << 30;
1016 /* Sets pvt->inject.page mask */
1017 if (pvt->inject.page < 0)
1020 mask |= (pvt->inject.page & 0xffff) << 14;
1022 /* Sets pvt->inject.column mask */
1023 if (pvt->inject.col < 0)
1026 mask |= (pvt->inject.col & 0x3fff);
1030 * bits 1-2: MASK_HALF_CACHELINE
1032 * bit 4: INJECT_ADDR_PARITY
1035 injectmask = (pvt->inject.type & 1) |
1036 (pvt->inject.section & 0x3) << 1 |
1037 (pvt->inject.type & 0x6) << (3 - 1);
1039 /* Unlock writes to registers - this register is write only */
1040 pci_write_config_dword(pvt->pci_noncore,
1041 MC_CFG_CONTROL, 0x2);
1043 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1044 MC_CHANNEL_ADDR_MATCH, mask);
1045 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1046 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1048 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1049 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1051 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1052 MC_CHANNEL_ERROR_INJECT, injectmask);
1055 * This is something undocumented, based on my tests
1056 * Without writing 8 to this register, errors aren't injected. Not sure
1059 pci_write_config_dword(pvt->pci_noncore,
1062 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1064 mask, pvt->inject.eccmask, injectmask);
1070 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1073 struct i7core_pvt *pvt = mci->pvt_info;
1076 if (!pvt->pci_ch[pvt->inject.channel][0])
1079 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1080 MC_CHANNEL_ERROR_INJECT, &injectmask);
1082 debugf0("Inject error read: 0x%018x\n", injectmask);
1084 if (injectmask & 0x0c)
1085 pvt->inject.enable = 1;
1087 return sprintf(data, "%d\n", pvt->inject.enable);
1090 #define DECLARE_COUNTER(param) \
1091 static ssize_t i7core_show_counter_##param( \
1092 struct mem_ctl_info *mci, \
1095 struct i7core_pvt *pvt = mci->pvt_info; \
1097 debugf1("%s() \n", __func__); \
1098 if (!pvt->ce_count_available || (pvt->is_registered)) \
1099 return sprintf(data, "data unavailable\n"); \
1100 return sprintf(data, "%lu\n", \
1101 pvt->udimm_ce_count[param]); \
1104 #define ATTR_COUNTER(param) \
1107 .name = __stringify(udimm##param), \
1108 .mode = (S_IRUGO | S_IWUSR) \
1110 .show = i7core_show_counter_##param \
1121 static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1122 ATTR_ADDR_MATCH(channel),
1123 ATTR_ADDR_MATCH(dimm),
1124 ATTR_ADDR_MATCH(rank),
1125 ATTR_ADDR_MATCH(bank),
1126 ATTR_ADDR_MATCH(page),
1127 ATTR_ADDR_MATCH(col),
1128 { } /* End of list */
1131 static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1132 .name = "inject_addrmatch",
1133 .mcidev_attr = i7core_addrmatch_attrs,
1136 static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1140 { .attr = { .name = NULL } }
1143 static const struct mcidev_sysfs_group i7core_udimm_counters = {
1144 .name = "all_channel_counts",
1145 .mcidev_attr = i7core_udimm_counters_attrs,
1148 static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1151 .name = "inject_section",
1152 .mode = (S_IRUGO | S_IWUSR)
1154 .show = i7core_inject_section_show,
1155 .store = i7core_inject_section_store,
1158 .name = "inject_type",
1159 .mode = (S_IRUGO | S_IWUSR)
1161 .show = i7core_inject_type_show,
1162 .store = i7core_inject_type_store,
1165 .name = "inject_eccmask",
1166 .mode = (S_IRUGO | S_IWUSR)
1168 .show = i7core_inject_eccmask_show,
1169 .store = i7core_inject_eccmask_store,
1171 .grp = &i7core_inject_addrmatch,
1174 .name = "inject_enable",
1175 .mode = (S_IRUGO | S_IWUSR)
1177 .show = i7core_inject_enable_show,
1178 .store = i7core_inject_enable_store,
1180 { } /* End of list */
1183 static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1186 .name = "inject_section",
1187 .mode = (S_IRUGO | S_IWUSR)
1189 .show = i7core_inject_section_show,
1190 .store = i7core_inject_section_store,
1193 .name = "inject_type",
1194 .mode = (S_IRUGO | S_IWUSR)
1196 .show = i7core_inject_type_show,
1197 .store = i7core_inject_type_store,
1200 .name = "inject_eccmask",
1201 .mode = (S_IRUGO | S_IWUSR)
1203 .show = i7core_inject_eccmask_show,
1204 .store = i7core_inject_eccmask_store,
1206 .grp = &i7core_inject_addrmatch,
1209 .name = "inject_enable",
1210 .mode = (S_IRUGO | S_IWUSR)
1212 .show = i7core_inject_enable_show,
1213 .store = i7core_inject_enable_store,
1215 .grp = &i7core_udimm_counters,
1217 { } /* End of list */
1220 /****************************************************************************
1221 Device initialization routines: put/get, init/exit
1222 ****************************************************************************/
1225 * i7core_put_devices 'put' all the devices that we have
1226 * reserved via 'get'
1228 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1232 debugf0(__FILE__ ": %s()\n", __func__);
1233 for (i = 0; i < i7core_dev->n_devs; i++) {
1234 struct pci_dev *pdev = i7core_dev->pdev[i];
1237 debugf0("Removing dev %02x:%02x.%d\n",
1239 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1242 kfree(i7core_dev->pdev);
1243 list_del(&i7core_dev->list);
1247 static void i7core_put_all_devices(void)
1249 struct i7core_dev *i7core_dev, *tmp;
1251 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
1252 i7core_put_devices(i7core_dev);
1255 static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1257 struct pci_dev *pdev = NULL;
1260 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1261 * aren't announced by acpi. So, we need to use a legacy scan probing
1264 while (table && table->descr) {
1265 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1266 if (unlikely(!pdev)) {
1267 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1268 pcibios_scan_specific_bus(255-i);
1275 static unsigned i7core_pci_lastbus(void)
1277 int last_bus = 0, bus;
1278 struct pci_bus *b = NULL;
1280 while ((b = pci_find_next_bus(b)) != NULL) {
1282 debugf0("Found bus %d\n", bus);
1287 debugf0("Last bus %d\n", last_bus);
1293 * i7core_get_devices Find and perform 'get' operation on the MCH's
1294 * device/functions we want to reference for this driver
1296 * Need to 'get' device 16 func 1 and func 2
1298 int i7core_get_onedevice(struct pci_dev **prev, const int devno,
1299 const struct pci_id_descr *dev_descr,
1300 const unsigned n_devs,
1301 const unsigned last_bus)
1303 struct i7core_dev *i7core_dev;
1305 struct pci_dev *pdev = NULL;
1309 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1310 dev_descr->dev_id, *prev);
1313 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1314 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1315 * to probe for the alternate address in case of failure
1317 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1318 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1319 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1321 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1322 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1323 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1332 if (dev_descr->optional)
1338 i7core_printk(KERN_INFO,
1339 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1340 dev_descr->dev, dev_descr->func,
1341 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1343 /* End of list, leave */
1346 bus = pdev->bus->number;
1348 socket = last_bus - bus;
1350 i7core_dev = get_i7core_dev(socket);
1352 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
1355 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs,
1357 if (!i7core_dev->pdev) {
1361 i7core_dev->socket = socket;
1362 i7core_dev->n_devs = n_devs;
1363 list_add_tail(&i7core_dev->list, &i7core_edac_list);
1366 if (i7core_dev->pdev[devno]) {
1367 i7core_printk(KERN_ERR,
1368 "Duplicated device for "
1369 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1370 bus, dev_descr->dev, dev_descr->func,
1371 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1376 i7core_dev->pdev[devno] = pdev;
1379 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1380 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1381 i7core_printk(KERN_ERR,
1382 "Device PCI ID %04x:%04x "
1383 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1384 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1385 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1386 bus, dev_descr->dev, dev_descr->func);
1390 /* Be sure that the device is enabled */
1391 if (unlikely(pci_enable_device(pdev) < 0)) {
1392 i7core_printk(KERN_ERR,
1394 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1395 bus, dev_descr->dev, dev_descr->func,
1396 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1400 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1401 socket, bus, dev_descr->dev,
1403 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1410 static int i7core_get_devices(const struct pci_id_table *table)
1412 int i, rc, last_bus;
1413 struct pci_dev *pdev = NULL;
1414 const struct pci_id_descr *dev_descr;
1416 last_bus = i7core_pci_lastbus();
1418 while (table && table->descr) {
1419 dev_descr = table->descr;
1420 for (i = 0; i < table->n_devs; i++) {
1423 rc = i7core_get_onedevice(&pdev, i,
1432 i7core_put_all_devices();
1444 static int mci_bind_devs(struct mem_ctl_info *mci,
1445 struct i7core_dev *i7core_dev)
1447 struct i7core_pvt *pvt = mci->pvt_info;
1448 struct pci_dev *pdev;
1451 /* Associates i7core_dev and mci for future usage */
1452 pvt->i7core_dev = i7core_dev;
1453 i7core_dev->mci = mci;
1455 pvt->is_registered = 0;
1456 for (i = 0; i < i7core_dev->n_devs; i++) {
1457 pdev = i7core_dev->pdev[i];
1461 func = PCI_FUNC(pdev->devfn);
1462 slot = PCI_SLOT(pdev->devfn);
1464 if (unlikely(func > MAX_MCR_FUNC))
1466 pvt->pci_mcr[func] = pdev;
1467 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1468 if (unlikely(func > MAX_CHAN_FUNC))
1470 pvt->pci_ch[slot - 4][func] = pdev;
1471 } else if (!slot && !func)
1472 pvt->pci_noncore = pdev;
1476 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1477 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1478 pdev, i7core_dev->socket);
1480 if (PCI_SLOT(pdev->devfn) == 3 &&
1481 PCI_FUNC(pdev->devfn) == 2)
1482 pvt->is_registered = 1;
1488 i7core_printk(KERN_ERR, "Device %d, function %d "
1489 "is out of the expected range\n",
1494 /****************************************************************************
1495 Error check routines
1496 ****************************************************************************/
1497 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1503 struct i7core_pvt *pvt = mci->pvt_info;
1504 int row = pvt->csrow_map[chan][dimm], i;
1506 for (i = 0; i < add; i++) {
1507 msg = kasprintf(GFP_KERNEL, "Corrected error "
1508 "(Socket=%d channel=%d dimm=%d)",
1509 pvt->i7core_dev->socket, chan, dimm);
1511 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1516 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1522 struct i7core_pvt *pvt = mci->pvt_info;
1523 int add0 = 0, add1 = 0, add2 = 0;
1524 /* Updates CE counters if it is not the first time here */
1525 if (pvt->ce_count_available) {
1526 /* Updates CE counters */
1528 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1529 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1530 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1534 pvt->rdimm_ce_count[chan][2] += add2;
1538 pvt->rdimm_ce_count[chan][1] += add1;
1542 pvt->rdimm_ce_count[chan][0] += add0;
1544 pvt->ce_count_available = 1;
1546 /* Store the new values */
1547 pvt->rdimm_last_ce_count[chan][2] = new2;
1548 pvt->rdimm_last_ce_count[chan][1] = new1;
1549 pvt->rdimm_last_ce_count[chan][0] = new0;
1551 /*updated the edac core */
1553 i7core_rdimm_update_csrow(mci, chan, 0, add0);
1555 i7core_rdimm_update_csrow(mci, chan, 1, add1);
1557 i7core_rdimm_update_csrow(mci, chan, 2, add2);
1561 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1563 struct i7core_pvt *pvt = mci->pvt_info;
1565 int i, new0, new1, new2;
1567 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1568 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1570 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1572 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1574 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1576 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1578 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1580 for (i = 0 ; i < 3; i++) {
1581 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1582 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1583 /*if the channel has 3 dimms*/
1584 if (pvt->channel[i].dimms > 2) {
1585 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1586 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1587 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1589 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1590 DIMM_BOT_COR_ERR(rcv[i][0]);
1591 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1592 DIMM_BOT_COR_ERR(rcv[i][1]);
1596 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1600 /* This function is based on the device 3 function 4 registers as described on:
1601 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1602 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1603 * also available at:
1604 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1606 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1608 struct i7core_pvt *pvt = mci->pvt_info;
1610 int new0, new1, new2;
1612 if (!pvt->pci_mcr[4]) {
1613 debugf0("%s MCR registers not found\n", __func__);
1617 /* Corrected test errors */
1618 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1619 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1621 /* Store the new values */
1622 new2 = DIMM2_COR_ERR(rcv1);
1623 new1 = DIMM1_COR_ERR(rcv0);
1624 new0 = DIMM0_COR_ERR(rcv0);
1626 /* Updates CE counters if it is not the first time here */
1627 if (pvt->ce_count_available) {
1628 /* Updates CE counters */
1629 int add0, add1, add2;
1631 add2 = new2 - pvt->udimm_last_ce_count[2];
1632 add1 = new1 - pvt->udimm_last_ce_count[1];
1633 add0 = new0 - pvt->udimm_last_ce_count[0];
1637 pvt->udimm_ce_count[2] += add2;
1641 pvt->udimm_ce_count[1] += add1;
1645 pvt->udimm_ce_count[0] += add0;
1647 if (add0 | add1 | add2)
1648 i7core_printk(KERN_ERR, "New Corrected error(s): "
1649 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1652 pvt->ce_count_available = 1;
1654 /* Store the new values */
1655 pvt->udimm_last_ce_count[2] = new2;
1656 pvt->udimm_last_ce_count[1] = new1;
1657 pvt->udimm_last_ce_count[0] = new0;
1661 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1662 * Architectures Software Developer’s Manual Volume 3B.
1663 * Nehalem are defined as family 0x06, model 0x1a
1665 * The MCA registers used here are the following ones:
1666 * struct mce field MCA Register
1667 * m->status MSR_IA32_MC8_STATUS
1668 * m->addr MSR_IA32_MC8_ADDR
1669 * m->misc MSR_IA32_MC8_MISC
1670 * In the case of Nehalem, the error information is masked at .status and .misc
1673 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1674 const struct mce *m)
1676 struct i7core_pvt *pvt = mci->pvt_info;
1677 char *type, *optype, *err, *msg;
1678 unsigned long error = m->status & 0x1ff0000l;
1679 u32 optypenum = (m->status >> 4) & 0x07;
1680 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1681 u32 dimm = (m->misc >> 16) & 0x3;
1682 u32 channel = (m->misc >> 18) & 0x3;
1683 u32 syndrome = m->misc >> 32;
1684 u32 errnum = find_first_bit(&error, 32);
1687 if (m->mcgstatus & 1)
1692 switch (optypenum) {
1694 optype = "generic undef request";
1697 optype = "read error";
1700 optype = "write error";
1703 optype = "addr/cmd error";
1706 optype = "scrubbing error";
1709 optype = "reserved";
1715 err = "read ECC error";
1718 err = "RAS ECC error";
1721 err = "write parity error";
1724 err = "redundacy loss";
1730 err = "memory range error";
1733 err = "RTID out of range";
1736 err = "address parity error";
1739 err = "byte enable parity error";
1745 /* FIXME: should convert addr into bank and rank information */
1746 msg = kasprintf(GFP_ATOMIC,
1747 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1748 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1749 type, (long long) m->addr, m->cpu, dimm, channel,
1750 syndrome, core_err_cnt, (long long)m->status,
1751 (long long)m->misc, optype, err);
1755 csrow = pvt->csrow_map[channel][dimm];
1757 /* Call the helper to output message */
1758 if (m->mcgstatus & 1)
1759 edac_mc_handle_fbd_ue(mci, csrow, 0,
1760 0 /* FIXME: should be channel here */, msg);
1761 else if (!pvt->is_registered)
1762 edac_mc_handle_fbd_ce(mci, csrow,
1763 0 /* FIXME: should be channel here */, msg);
1769 * i7core_check_error Retrieve and process errors reported by the
1770 * hardware. Called by the Core module.
1772 static void i7core_check_error(struct mem_ctl_info *mci)
1774 struct i7core_pvt *pvt = mci->pvt_info;
1780 * MCE first step: Copy all mce errors into a temporary buffer
1781 * We use a double buffering here, to reduce the risk of
1785 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1788 goto check_ce_error;
1790 m = pvt->mce_outentry;
1791 if (pvt->mce_in + count > MCE_LOG_LEN) {
1792 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1794 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1800 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1802 pvt->mce_in += count;
1805 if (pvt->mce_overrun) {
1806 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1809 pvt->mce_overrun = 0;
1813 * MCE second step: parse errors and display
1815 for (i = 0; i < count; i++)
1816 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1819 * Now, let's increment CE error counts
1822 if (!pvt->is_registered)
1823 i7core_udimm_check_mc_ecc_err(mci);
1825 i7core_rdimm_check_mc_ecc_err(mci);
1829 * i7core_mce_check_error Replicates mcelog routine to get errors
1830 * This routine simply queues mcelog errors, and
1831 * return. The error itself should be handled later
1832 * by i7core_check_error.
1833 * WARNING: As this routine should be called at NMI time, extra care should
1834 * be taken to avoid deadlocks, and to be as fast as possible.
1836 static int i7core_mce_check_error(void *priv, struct mce *mce)
1838 struct mem_ctl_info *mci = priv;
1839 struct i7core_pvt *pvt = mci->pvt_info;
1842 * Just let mcelog handle it if the error is
1843 * outside the memory controller
1845 if (((mce->status & 0xffff) >> 7) != 1)
1848 /* Bank 8 registers are the only ones that we know how to handle */
1853 /* Only handle if it is the right mc controller */
1854 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
1859 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1865 /* Copy memory error at the ringbuffer */
1866 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1868 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1870 /* Handle fatal errors immediately */
1871 if (mce->mcgstatus & 1)
1872 i7core_check_error(mci);
1874 /* Advice mcelog that the error were handled */
1878 static int i7core_register_mci(struct i7core_dev *i7core_dev,
1879 const int num_channels, const int num_csrows)
1881 struct mem_ctl_info *mci;
1882 struct i7core_pvt *pvt;
1886 /* allocate a new MC control structure */
1887 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1888 i7core_dev->socket);
1892 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1893 __func__, mci, &i7core_dev->pdev[0]->dev);
1895 /* record ptr to the generic device */
1896 mci->dev = &i7core_dev->pdev[0]->dev;
1898 pvt = mci->pvt_info;
1899 memset(pvt, 0, sizeof(*pvt));
1902 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1903 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1906 mci->mtype_cap = MEM_FLAG_DDR3;
1907 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1908 mci->edac_cap = EDAC_FLAG_NONE;
1909 mci->mod_name = "i7core_edac.c";
1910 mci->mod_ver = I7CORE_REVISION;
1911 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1912 i7core_dev->socket);
1913 mci->dev_name = pci_name(i7core_dev->pdev[0]);
1914 mci->ctl_page_to_phys = NULL;
1916 if (pvt->is_registered)
1917 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
1919 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
1921 /* Set the function pointer to an actual operation function */
1922 mci->edac_check = i7core_check_error;
1924 /* Store pci devices at mci for faster access */
1925 rc = mci_bind_devs(mci, i7core_dev);
1926 if (unlikely(rc < 0))
1929 /* Get dimm basic config */
1930 get_dimm_config(mci, &csrow);
1932 /* add this new MC control structure to EDAC's list of MCs */
1933 if (unlikely(edac_mc_add_mc(mci))) {
1934 debugf0("MC: " __FILE__
1935 ": %s(): failed edac_mc_add_mc()\n", __func__);
1936 /* FIXME: perhaps some code should go here that disables error
1937 * reporting if we just enabled it
1944 /* Default error mask is any memory */
1945 pvt->inject.channel = 0;
1946 pvt->inject.dimm = -1;
1947 pvt->inject.rank = -1;
1948 pvt->inject.bank = -1;
1949 pvt->inject.page = -1;
1950 pvt->inject.col = -1;
1952 /* Registers on edac_mce in order to receive memory errors */
1953 pvt->edac_mce.priv = mci;
1954 pvt->edac_mce.check_error = i7core_mce_check_error;
1956 /* allocating generic PCI control info */
1957 pvt->i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
1959 if (unlikely(!pvt->i7core_pci)) {
1961 "%s(): Unable to create PCI control\n",
1964 "%s(): PCI error report via EDAC not setup\n",
1968 rc = edac_mce_register(&pvt->edac_mce);
1969 if (unlikely(rc < 0)) {
1970 debugf0("MC: " __FILE__
1971 ": %s(): failed edac_mce_register()\n", __func__);
1981 * i7core_probe Probe for ONE instance of device to see if it is
1984 * 0 for FOUND a device
1985 * < 0 for error code
1988 static int __devinit i7core_probe(struct pci_dev *pdev,
1989 const struct pci_device_id *id)
1992 struct i7core_dev *i7core_dev;
1994 /* get the pci devices we want to reserve for our use */
1995 mutex_lock(&i7core_edac_lock);
1998 * All memory controllers are allocated at the first pass.
2000 if (unlikely(probed >= 1)) {
2001 mutex_unlock(&i7core_edac_lock);
2006 rc = i7core_get_devices(pci_dev_table);
2007 if (unlikely(rc < 0))
2010 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
2014 /* Check the number of active and not disabled channels */
2015 rc = i7core_get_active_channels(i7core_dev->socket,
2016 &channels, &csrows);
2017 if (unlikely(rc < 0))
2020 rc = i7core_register_mci(i7core_dev, channels, csrows);
2021 if (unlikely(rc < 0))
2025 i7core_printk(KERN_INFO, "Driver loaded.\n");
2027 mutex_unlock(&i7core_edac_lock);
2031 i7core_put_all_devices();
2033 mutex_unlock(&i7core_edac_lock);
2038 * i7core_remove destructor for one instance of device
2041 static void __devexit i7core_remove(struct pci_dev *pdev)
2043 struct mem_ctl_info *mci;
2044 struct i7core_dev *i7core_dev, *tmp;
2045 struct i7core_pvt *pvt;
2047 debugf0(__FILE__ ": %s()\n", __func__);
2050 * we have a trouble here: pdev value for removal will be wrong, since
2051 * it will point to the X58 register used to detect that the machine
2052 * is a Nehalem or upper design. However, due to the way several PCI
2053 * devices are grouped together to provide MC functionality, we need
2054 * to use a different method for releasing the devices
2057 mutex_lock(&i7core_edac_lock);
2058 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
2059 mci = find_mci_by_dev(&i7core_dev->pdev[0]->dev);
2060 if (unlikely(!mci || !mci->pvt_info)) {
2061 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2062 __func__, &i7core_dev->pdev[0]->dev);
2064 i7core_printk(KERN_ERR,
2065 "Couldn't find mci hanler\n");
2067 pvt = mci->pvt_info;
2068 i7core_dev = pvt->i7core_dev;
2070 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2071 __func__, mci, &i7core_dev->pdev[0]->dev);
2073 /* Disable MCE NMI handler */
2074 edac_mce_unregister(&pvt->edac_mce);
2076 /* Disable EDAC polling */
2077 if (likely(pvt->i7core_pci))
2078 edac_pci_release_generic_ctl(pvt->i7core_pci);
2080 i7core_printk(KERN_ERR,
2081 "Couldn't find mem_ctl_info for socket %d\n",
2082 i7core_dev->socket);
2083 pvt->i7core_pci = NULL;
2085 /* Remove MC sysfs nodes */
2086 edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
2089 kfree(mci->ctl_name);
2092 /* Release PCI resources */
2093 i7core_put_devices(i7core_dev);
2098 mutex_unlock(&i7core_edac_lock);
2101 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2104 * i7core_driver pci_driver structure for this module
2107 static struct pci_driver i7core_driver = {
2108 .name = "i7core_edac",
2109 .probe = i7core_probe,
2110 .remove = __devexit_p(i7core_remove),
2111 .id_table = i7core_pci_tbl,
2115 * i7core_init Module entry function
2116 * Try to initialize this module for its devices
2118 static int __init i7core_init(void)
2122 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2124 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2127 i7core_xeon_pci_fixup(pci_dev_table);
2129 pci_rc = pci_register_driver(&i7core_driver);
2134 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2141 * i7core_exit() Module exit function
2142 * Unregister the driver
2144 static void __exit i7core_exit(void)
2146 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2147 pci_unregister_driver(&i7core_driver);
2150 module_init(i7core_init);
2151 module_exit(i7core_exit);
2153 MODULE_LICENSE("GPL");
2154 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2155 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2156 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2159 module_param(edac_op_state, int, 0444);
2160 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");