drivers/edac/e752x_edac.c

   1 /*
   2  * Intel e752x Memory Controller kernel module
   3  * (C) 2004 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * See "enum e752x_chips" below for supported chipsets
   8  *
   9  * Written by Tom Zimmerman
  10  *
  11  * Contributors:
  12  *      Thayne Harbaugh at realmsys.com (?)
  13  *      Wang Zhenyu at intel.com
  14  *      Dave Jiang at mvista.com
  15  *
  16  * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  17  *
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <linux/pci_ids.h>
  24 #include <linux/slab.h>
  25 #include "edac_mc.h"
  26
  27 #define E752X_REVISION  " Ver: 2.0.1 " __DATE__
  28 #define EDAC_MOD_STR    "e752x_edac"
  29
  30 static int force_function_unhide;
  31
  32 #define e752x_printk(level, fmt, arg...) \
  33         edac_printk(level, "e752x", fmt, ##arg)
  34
  35 #define e752x_mc_printk(mci, level, fmt, arg...) \
  36         edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
  37
  38 #ifndef PCI_DEVICE_ID_INTEL_7520_0
  39 #define PCI_DEVICE_ID_INTEL_7520_0      0x3590
  40 #endif                          /* PCI_DEVICE_ID_INTEL_7520_0      */
  41
  42 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
  43 #define PCI_DEVICE_ID_INTEL_7520_1_ERR  0x3591
  44 #endif                          /* PCI_DEVICE_ID_INTEL_7520_1_ERR  */
  45
  46 #ifndef PCI_DEVICE_ID_INTEL_7525_0
  47 #define PCI_DEVICE_ID_INTEL_7525_0      0x359E
  48 #endif                          /* PCI_DEVICE_ID_INTEL_7525_0      */
  49
  50 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
  51 #define PCI_DEVICE_ID_INTEL_7525_1_ERR  0x3593
  52 #endif                          /* PCI_DEVICE_ID_INTEL_7525_1_ERR  */
  53
  54 #ifndef PCI_DEVICE_ID_INTEL_7320_0
  55 #define PCI_DEVICE_ID_INTEL_7320_0      0x3592
  56 #endif                          /* PCI_DEVICE_ID_INTEL_7320_0 */
  57
  58 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
  59 #define PCI_DEVICE_ID_INTEL_7320_1_ERR  0x3593
  60 #endif                          /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
  61
  62 #define E752X_NR_CSROWS         8       /* number of csrows */
  63
  64 /* E752X register addresses - device 0 function 0 */
  65 #define E752X_DRB               0x60    /* DRAM row boundary register (8b) */
  66 #define E752X_DRA               0x70    /* DRAM row attribute register (8b) */
  67                                         /*
  68                                          * 31:30   Device width row 7
  69                                          *      01=x8 10=x4 11=x8 DDR2
  70                                          * 27:26   Device width row 6
  71                                          * 23:22   Device width row 5
  72                                          * 19:20   Device width row 4
  73                                          * 15:14   Device width row 3
  74                                          * 11:10   Device width row 2
  75                                          *  7:6    Device width row 1
  76                                          *  3:2    Device width row 0
  77                                          */
  78 #define E752X_DRC               0x7C    /* DRAM controller mode reg (32b) */
  79                                         /* FIXME:IS THIS RIGHT? */
  80                                         /*
  81                                          * 22    Number channels 0=1,1=2
  82                                          * 19:18 DRB Granularity 32/64MB
  83                                          */
  84 #define E752X_DRM               0x80    /* Dimm mapping register */
  85 #define E752X_DDRCSR            0x9A    /* DDR control and status reg (16b) */
  86                                         /*
  87                                          * 14:12 1 single A, 2 single B, 3 dual
  88                                          */
  89 #define E752X_TOLM              0xC4    /* DRAM top of low memory reg (16b) */
  90 #define E752X_REMAPBASE         0xC6    /* DRAM remap base address reg (16b) */
  91 #define E752X_REMAPLIMIT        0xC8    /* DRAM remap limit address reg (16b) */
  92 #define E752X_REMAPOFFSET       0xCA    /* DRAM remap limit offset reg (16b) */
  93
  94 /* E752X register addresses - device 0 function 1 */
  95 #define E752X_FERR_GLOBAL       0x40    /* Global first error register (32b) */
  96 #define E752X_NERR_GLOBAL       0x44    /* Global next error register (32b) */
  97 #define E752X_HI_FERR           0x50    /* Hub interface first error reg (8b) */
  98 #define E752X_HI_NERR           0x52    /* Hub interface next error reg (8b) */
  99 #define E752X_HI_ERRMASK        0x54    /* Hub interface error mask reg (8b) */
 100 #define E752X_HI_SMICMD         0x5A    /* Hub interface SMI command reg (8b) */
 101 #define E752X_SYSBUS_FERR       0x60    /* System buss first error reg (16b) */
 102 #define E752X_SYSBUS_NERR       0x62    /* System buss next error reg (16b) */
 103 #define E752X_SYSBUS_ERRMASK    0x64    /* System buss error mask reg (16b) */
 104 #define E752X_SYSBUS_SMICMD     0x6A    /* System buss SMI command reg (16b) */
 105 #define E752X_BUF_FERR          0x70    /* Memory buffer first error reg (8b) */
 106 #define E752X_BUF_NERR          0x72    /* Memory buffer next error reg (8b) */
 107 #define E752X_BUF_ERRMASK       0x74    /* Memory buffer error mask reg (8b) */
 108 #define E752X_BUF_SMICMD        0x7A    /* Memory buffer SMI command reg (8b) */
 109 #define E752X_DRAM_FERR         0x80    /* DRAM first error register (16b) */
 110 #define E752X_DRAM_NERR         0x82    /* DRAM next error register (16b) */
 111 #define E752X_DRAM_ERRMASK      0x84    /* DRAM error mask register (8b) */
 112 #define E752X_DRAM_SMICMD       0x8A    /* DRAM SMI command register (8b) */
 113 #define E752X_DRAM_RETR_ADD     0xAC    /* DRAM Retry address register (32b) */
 114 #define E752X_DRAM_SEC1_ADD     0xA0    /* DRAM first correctable memory */
 115                                         /*     error address register (32b) */
 116                                         /*
 117                                          * 31    Reserved
 118                                          * 30:2  CE address (64 byte block 34:6)
 119                                          * 1     Reserved
 120                                          * 0     HiLoCS
 121                                          */
 122 #define E752X_DRAM_SEC2_ADD     0xC8    /* DRAM first correctable memory */
 123                                         /*     error address register (32b) */
 124                                         /*
 125                                          * 31    Reserved
 126                                          * 30:2  CE address (64 byte block 34:6)
 127                                          * 1     Reserved
 128                                          * 0     HiLoCS
 129                                          */
 130 #define E752X_DRAM_DED_ADD      0xA4    /* DRAM first uncorrectable memory */
 131                                         /*     error address register (32b) */
 132                                         /*
 133                                          * 31    Reserved
 134                                          * 30:2  CE address (64 byte block 34:6)
 135                                          * 1     Reserved
 136                                          * 0     HiLoCS
 137                                          */
 138 #define E752X_DRAM_SCRB_ADD     0xA8    /* DRAM first uncorrectable scrub memory */
 139                                         /*     error address register (32b) */
 140                                         /*
 141                                          * 31    Reserved
 142                                          * 30:2  CE address (64 byte block 34:6)
 143                                          * 1     Reserved
 144                                          * 0     HiLoCS
 145                                          */
 146 #define E752X_DRAM_SEC1_SYNDROME 0xC4   /* DRAM first correctable memory */
 147                                         /*     error syndrome register (16b) */
 148 #define E752X_DRAM_SEC2_SYNDROME 0xC6   /* DRAM second correctable memory */
 149                                         /*     error syndrome register (16b) */
 150 #define E752X_DEVPRES1          0xF4    /* Device Present 1 register (8b) */
 151
 152 /* ICH5R register addresses - device 30 function 0 */
 153 #define ICH5R_PCI_STAT          0x06    /* PCI status register (16b) */
 154 #define ICH5R_PCI_2ND_STAT      0x1E    /* PCI status secondary reg (16b) */
 155 #define ICH5R_PCI_BRIDGE_CTL    0x3E    /* PCI bridge control register (16b) */
 156
 157 enum e752x_chips {
 158         E7520 = 0,
 159         E7525 = 1,
 160         E7320 = 2
 161 };
 162
 163 struct e752x_pvt {
 164         struct pci_dev *bridge_ck;
 165         struct pci_dev *dev_d0f0;
 166         struct pci_dev *dev_d0f1;
 167         u32 tolm;
 168         u32 remapbase;
 169         u32 remaplimit;
 170         int mc_symmetric;
 171         u8 map[8];
 172         int map_type;
 173         const struct e752x_dev_info *dev_info;
 174 };
 175
 176 struct e752x_dev_info {
 177         u16 err_dev;
 178         u16 ctl_dev;
 179         const char *ctl_name;
 180 };
 181
 182 struct e752x_error_info {
 183         u32 ferr_global;
 184         u32 nerr_global;
 185         u8 hi_ferr;
 186         u8 hi_nerr;
 187         u16 sysbus_ferr;
 188         u16 sysbus_nerr;
 189         u8 buf_ferr;
 190         u8 buf_nerr;
 191         u16 dram_ferr;
 192         u16 dram_nerr;
 193         u32 dram_sec1_add;
 194         u32 dram_sec2_add;
 195         u16 dram_sec1_syndrome;
 196         u16 dram_sec2_syndrome;
 197         u32 dram_ded_add;
 198         u32 dram_scrb_add;
 199         u32 dram_retr_add;
 200 };
 201
 202 static const struct e752x_dev_info e752x_devs[] = {
 203         [E7520] = {
 204                 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
 205                 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
 206                 .ctl_name = "E7520"
 207         },
 208         [E7525] = {
 209                 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
 210                 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
 211                 .ctl_name = "E7525"
 212         },
 213         [E7320] = {
 214                 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
 215                 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
 216                 .ctl_name = "E7320"
 217         },
 218 };
 219
 220 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
 221                 unsigned long page)
 222 {
 223         u32 remap;
 224         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 225
 226         debugf3("%s()\n", __func__);
 227
 228         if (page < pvt->tolm)
 229                 return page;
 230
 231         if ((page >= 0x100000) && (page < pvt->remapbase))
 232                 return page;
 233
 234         remap = (page - pvt->tolm) + pvt->remapbase;
 235
 236         if (remap < pvt->remaplimit)
 237                 return remap;
 238
 239         e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
 240         return pvt->tolm - 1;
 241 }
 242
 243 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
 244                 u32 sec1_add, u16 sec1_syndrome)
 245 {
 246         u32 page;
 247         int row;
 248         int channel;
 249         int i;
 250         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 251
 252         debugf3("%s()\n", __func__);
 253
 254         /* convert the addr to 4k page */
 255         page = sec1_add >> (PAGE_SHIFT - 4);
 256
 257         /* FIXME - check for -1 */
 258         if (pvt->mc_symmetric) {
 259                 /* chip select are bits 14 & 13 */
 260                 row = ((page >> 1) & 3);
 261                 e752x_printk(KERN_WARNING,
 262                         "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
 263                         pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
 264                         pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
 265
 266                 /* test for channel remapping */
 267                 for (i = 0; i < 8; i++) {
 268                         if (pvt->map[i] == row)
 269                                 break;
 270                 }
 271
 272                 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
 273
 274                 if (i < 8)
 275                         row = i;
 276                 else
 277                         e752x_mc_printk(mci, KERN_WARNING,
 278                                 "row %d not found in remap table\n", row);
 279         } else
 280                 row = edac_mc_find_csrow_by_page(mci, page);
 281
 282         /* 0 = channel A, 1 = channel B */
 283         channel = !(error_one & 1);
 284
 285         if (!pvt->map_type)
 286                 row = 7 - row;
 287
 288         /* e752x mc reads 34:6 of the DRAM linear address */
 289         edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
 290                         sec1_syndrome, row, channel, "e752x CE");
 291 }
 292
 293 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
 294                 u32 sec1_add, u16 sec1_syndrome, int *error_found,
 295                 int handle_error)
 296 {
 297         *error_found = 1;
 298
 299         if (handle_error)
 300                 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
 301 }
 302
 303 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
 304                 u32 ded_add, u32 scrb_add)
 305 {
 306         u32 error_2b, block_page;
 307         int row;
 308         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 309
 310         debugf3("%s()\n", __func__);
 311
 312         if (error_one & 0x0202) {
 313                 error_2b = ded_add;
 314
 315                 /* convert to 4k address */
 316                 block_page = error_2b >> (PAGE_SHIFT - 4);
 317
 318                 row = pvt->mc_symmetric ?
 319                         /* chip select are bits 14 & 13 */
 320                         ((block_page >> 1) & 3) :
 321                         edac_mc_find_csrow_by_page(mci, block_page);
 322
 323                 /* e752x mc reads 34:6 of the DRAM linear address */
 324                 edac_mc_handle_ue(mci, block_page,
 325                                         offset_in_page(error_2b << 4),
 326                                         row, "e752x UE from Read");
 327         }
 328         if (error_one & 0x0404) {
 329                 error_2b = scrb_add;
 330
 331                 /* convert to 4k address */
 332                 block_page = error_2b >> (PAGE_SHIFT - 4);
 333
 334                 row = pvt->mc_symmetric ?
 335                         /* chip select are bits 14 & 13 */
 336                         ((block_page >> 1) & 3) :
 337                         edac_mc_find_csrow_by_page(mci, block_page);
 338
 339                 /* e752x mc reads 34:6 of the DRAM linear address */
 340                 edac_mc_handle_ue(mci, block_page,
 341                                         offset_in_page(error_2b << 4),
 342                                         row, "e752x UE from Scruber");
 343         }
 344 }
 345
 346 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
 347                 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
 348 {
 349         *error_found = 1;
 350
 351         if (handle_error)
 352                 do_process_ue(mci, error_one, ded_add, scrb_add);
 353 }
 354
 355 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
 356                 int *error_found, int handle_error)
 357 {
 358         *error_found = 1;
 359
 360         if (!handle_error)
 361                 return;
 362
 363         debugf3("%s()\n", __func__);
 364         edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
 365 }
 366
 367 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
 368                 u32 retry_add)
 369 {
 370         u32 error_1b, page;
 371         int row;
 372         struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
 373
 374         error_1b = retry_add;
 375         page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
 376         row = pvt->mc_symmetric ?
 377                 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
 378                 edac_mc_find_csrow_by_page(mci, page);
 379         e752x_mc_printk(mci, KERN_WARNING,
 380                 "CE page 0x%lx, row %d : Memory read retry\n",
 381                 (long unsigned int) page, row);
 382 }
 383
 384 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
 385                 u32 retry_add, int *error_found, int handle_error)
 386 {
 387         *error_found = 1;
 388
 389         if (handle_error)
 390                 do_process_ded_retry(mci, error, retry_add);
 391 }
 392
 393 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
 394                 int *error_found, int handle_error)
 395 {
 396         *error_found = 1;
 397
 398         if (handle_error)
 399                 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
 400 }
 401
 402 static char *global_message[11] = {
 403         "PCI Express C1", "PCI Express C", "PCI Express B1",
 404         "PCI Express B", "PCI Express A1", "PCI Express A",
 405         "DMA Controler", "HUB Interface", "System Bus",
 406         "DRAM Controler", "Internal Buffer"
 407 };
 408
 409 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
 410
 411 static void do_global_error(int fatal, u32 errors)
 412 {
 413         int i;
 414
 415         for (i = 0; i < 11; i++) {
 416                 if (errors & (1 << i))
 417                         e752x_printk(KERN_WARNING, "%sError %s\n",
 418                                 fatal_message[fatal], global_message[i]);
 419         }
 420 }
 421
 422 static inline void global_error(int fatal, u32 errors, int *error_found,
 423                 int handle_error)
 424 {
 425         *error_found = 1;
 426
 427         if (handle_error)
 428                 do_global_error(fatal, errors);
 429 }
 430
 431 static char *hub_message[7] = {
 432         "HI Address or Command Parity", "HI Illegal Access",
 433         "HI Internal Parity", "Out of Range Access",
 434         "HI Data Parity", "Enhanced Config Access",
 435         "Hub Interface Target Abort"
 436 };
 437
 438 static void do_hub_error(int fatal, u8 errors)
 439 {
 440         int i;
 441
 442         for (i = 0; i < 7; i++) {
 443                 if (errors & (1 << i))
 444                         e752x_printk(KERN_WARNING, "%sError %s\n",
 445                                 fatal_message[fatal], hub_message[i]);
 446         }
 447 }
 448
 449 static inline void hub_error(int fatal, u8 errors, int *error_found,
 450                 int handle_error)
 451 {
 452         *error_found = 1;
 453
 454         if (handle_error)
 455                 do_hub_error(fatal, errors);
 456 }
 457
 458 static char *membuf_message[4] = {
 459         "Internal PMWB to DRAM parity",
 460         "Internal PMWB to System Bus Parity",
 461         "Internal System Bus or IO to PMWB Parity",
 462         "Internal DRAM to PMWB Parity"
 463 };
 464
 465 static void do_membuf_error(u8 errors)
 466 {
 467         int i;
 468
 469         for (i = 0; i < 4; i++) {
 470                 if (errors & (1 << i))
 471                         e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
 472                                 membuf_message[i]);
 473         }
 474 }
 475
 476 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
 477 {
 478         *error_found = 1;
 479
 480         if (handle_error)
 481                 do_membuf_error(errors);
 482 }
 483
 484 static char *sysbus_message[10] = {
 485         "Addr or Request Parity",
 486         "Data Strobe Glitch",
 487         "Addr Strobe Glitch",
 488         "Data Parity",
 489         "Addr Above TOM",
 490         "Non DRAM Lock Error",
 491         "MCERR", "BINIT",
 492         "Memory Parity",
 493         "IO Subsystem Parity"
 494 };
 495
 496 static void do_sysbus_error(int fatal, u32 errors)
 497 {
 498         int i;
 499
 500         for (i = 0; i < 10; i++) {
 501                 if (errors & (1 << i))
 502                         e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
 503                                 fatal_message[fatal], sysbus_message[i]);
 504         }
 505 }
 506
 507 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
 508                 int handle_error)
 509 {
 510         *error_found = 1;
 511
 512         if (handle_error)
 513                 do_sysbus_error(fatal, errors);
 514 }
 515
 516 static void e752x_check_hub_interface(struct e752x_error_info *info,
 517                 int *error_found, int handle_error)
 518 {
 519         u8 stat8;
 520
 521         //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
 522
 523         stat8 = info->hi_ferr;
 524
 525         if(stat8 & 0x7f) { /* Error, so process */
 526                 stat8 &= 0x7f;
 527
 528                 if(stat8 & 0x2b)
 529                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 530
 531                 if(stat8 & 0x54)
 532                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 533         }
 534
 535         //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
 536
 537         stat8 = info->hi_nerr;
 538
 539         if(stat8 & 0x7f) { /* Error, so process */
 540                 stat8 &= 0x7f;
 541
 542                 if (stat8 & 0x2b)
 543                         hub_error(1, stat8 & 0x2b, error_found, handle_error);
 544
 545                 if(stat8 & 0x54)
 546                         hub_error(0, stat8 & 0x54, error_found, handle_error);
 547         }
 548 }
 549
 550 static void e752x_check_sysbus(struct e752x_error_info *info,
 551                 int *error_found, int handle_error)
 552 {
 553         u32 stat32, error32;
 554
 555         //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
 556         stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
 557
 558         if (stat32 == 0)
 559                 return;  /* no errors */
 560
 561         error32 = (stat32 >> 16) & 0x3ff;
 562         stat32 = stat32 & 0x3ff;
 563
 564         if(stat32 & 0x087)
 565                 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
 566
 567         if(stat32 & 0x378)
 568                 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
 569
 570         if(error32 & 0x087)
 571                 sysbus_error(1, error32 & 0x087, error_found, handle_error);
 572
 573         if(error32 & 0x378)
 574                 sysbus_error(0, error32 & 0x378, error_found, handle_error);
 575 }
 576
 577 static void e752x_check_membuf (struct e752x_error_info *info,
 578                 int *error_found, int handle_error)
 579 {
 580         u8 stat8;
 581
 582         stat8 = info->buf_ferr;
 583
 584         if (stat8 & 0x0f) { /* Error, so process */
 585                 stat8 &= 0x0f;
 586                 membuf_error(stat8, error_found, handle_error);
 587         }
 588
 589         stat8 = info->buf_nerr;
 590
 591         if (stat8 & 0x0f) { /* Error, so process */
 592                 stat8 &= 0x0f;
 593                 membuf_error(stat8, error_found, handle_error);
 594         }
 595 }
 596
 597 static void e752x_check_dram (struct mem_ctl_info *mci,
 598                 struct e752x_error_info *info, int *error_found,
 599                 int handle_error)
 600 {
 601         u16 error_one, error_next;
 602
 603         error_one = info->dram_ferr;
 604         error_next = info->dram_nerr;
 605
 606         /* decode and report errors */
 607         if(error_one & 0x0101)  /* check first error correctable */
 608                 process_ce(mci, error_one, info->dram_sec1_add,
 609                            info->dram_sec1_syndrome, error_found,
 610                            handle_error);
 611
 612         if(error_next & 0x0101)  /* check next error correctable */
 613                 process_ce(mci, error_next, info->dram_sec2_add,
 614                            info->dram_sec2_syndrome, error_found,
 615                            handle_error);
 616
 617         if(error_one & 0x4040)
 618                 process_ue_no_info_wr(mci, error_found, handle_error);
 619
 620         if(error_next & 0x4040)
 621                 process_ue_no_info_wr(mci, error_found, handle_error);
 622
 623         if(error_one & 0x2020)
 624                 process_ded_retry(mci, error_one, info->dram_retr_add,
 625                                   error_found, handle_error);
 626
 627         if(error_next & 0x2020)
 628                 process_ded_retry(mci, error_next, info->dram_retr_add,
 629                                   error_found, handle_error);
 630
 631         if(error_one & 0x0808)
 632                 process_threshold_ce(mci, error_one, error_found,
 633                                      handle_error);
 634
 635         if(error_next & 0x0808)
 636                 process_threshold_ce(mci, error_next, error_found,
 637                                      handle_error);
 638
 639         if(error_one & 0x0606)
 640                 process_ue(mci, error_one, info->dram_ded_add,
 641                            info->dram_scrb_add, error_found, handle_error);
 642
 643         if(error_next & 0x0606)
 644                 process_ue(mci, error_next, info->dram_ded_add,
 645                            info->dram_scrb_add, error_found, handle_error);
 646 }
 647
 648 static void e752x_get_error_info (struct mem_ctl_info *mci,
 649                 struct e752x_error_info *info)
 650 {
 651         struct pci_dev *dev;
 652         struct e752x_pvt *pvt;
 653
 654         memset(info, 0, sizeof(*info));
 655         pvt = (struct e752x_pvt *) mci->pvt_info;
 656         dev = pvt->dev_d0f1;
 657         pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
 658
 659         if (info->ferr_global) {
 660                 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
 661                 pci_read_config_word(dev, E752X_SYSBUS_FERR,
 662                                 &info->sysbus_ferr);
 663                 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
 664                 pci_read_config_word(dev, E752X_DRAM_FERR,
 665                                 &info->dram_ferr);
 666                 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
 667                                 &info->dram_sec1_add);
 668                 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
 669                                 &info->dram_sec1_syndrome);
 670                 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
 671                                 &info->dram_ded_add);
 672                 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
 673                                 &info->dram_scrb_add);
 674                 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
 675                                 &info->dram_retr_add);
 676
 677                 if (info->hi_ferr & 0x7f)
 678                         pci_write_config_byte(dev, E752X_HI_FERR,
 679                                         info->hi_ferr);
 680
 681                 if (info->sysbus_ferr)
 682                         pci_write_config_word(dev, E752X_SYSBUS_FERR,
 683                                         info->sysbus_ferr);
 684
 685                 if (info->buf_ferr & 0x0f)
 686                         pci_write_config_byte(dev, E752X_BUF_FERR,
 687                                         info->buf_ferr);
 688
 689                 if (info->dram_ferr)
 690                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
 691                                         info->dram_ferr, info->dram_ferr);
 692
 693                 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
 694                                 info->ferr_global);
 695         }
 696
 697         pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
 698
 699         if (info->nerr_global) {
 700                 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
 701                 pci_read_config_word(dev, E752X_SYSBUS_NERR,
 702                                 &info->sysbus_nerr);
 703                 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
 704                 pci_read_config_word(dev, E752X_DRAM_NERR,
 705                                 &info->dram_nerr);
 706                 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
 707                                 &info->dram_sec2_add);
 708                 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
 709                                 &info->dram_sec2_syndrome);
 710
 711                 if (info->hi_nerr & 0x7f)
 712                         pci_write_config_byte(dev, E752X_HI_NERR,
 713                                         info->hi_nerr);
 714
 715                 if (info->sysbus_nerr)
 716                         pci_write_config_word(dev, E752X_SYSBUS_NERR,
 717                                         info->sysbus_nerr);
 718
 719                 if (info->buf_nerr & 0x0f)
 720                         pci_write_config_byte(dev, E752X_BUF_NERR,
 721                                         info->buf_nerr);
 722
 723                 if (info->dram_nerr)
 724                         pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
 725                                         info->dram_nerr, info->dram_nerr);
 726
 727                 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
 728                                 info->nerr_global);
 729         }
 730 }
 731
 732 static int e752x_process_error_info (struct mem_ctl_info *mci,
 733                 struct e752x_error_info *info, int handle_errors)
 734 {
 735         u32 error32, stat32;
 736         int error_found;
 737
 738         error_found = 0;
 739         error32 = (info->ferr_global >> 18) & 0x3ff;
 740         stat32 = (info->ferr_global >> 4) & 0x7ff;
 741
 742         if (error32)
 743                 global_error(1, error32, &error_found, handle_errors);
 744
 745         if (stat32)
 746                 global_error(0, stat32, &error_found, handle_errors);
 747
 748         error32 = (info->nerr_global >> 18) & 0x3ff;
 749         stat32 = (info->nerr_global >> 4) & 0x7ff;
 750
 751         if (error32)
 752                 global_error(1, error32, &error_found, handle_errors);
 753
 754         if (stat32)
 755                 global_error(0, stat32, &error_found, handle_errors);
 756
 757         e752x_check_hub_interface(info, &error_found, handle_errors);
 758         e752x_check_sysbus(info, &error_found, handle_errors);
 759         e752x_check_membuf(info, &error_found, handle_errors);
 760         e752x_check_dram(mci, info, &error_found, handle_errors);
 761         return error_found;
 762 }
 763
 764 static void e752x_check(struct mem_ctl_info *mci)
 765 {
 766         struct e752x_error_info info;
 767
 768         debugf3("%s()\n", __func__);
 769         e752x_get_error_info(mci, &info);
 770         e752x_process_error_info(mci, &info, 1);
 771 }
 772
 773 /* Return 1 if dual channel mode is active.  Else return 0. */
 774 static inline int dual_channel_active(u16 ddrcsr)
 775 {
 776         return (((ddrcsr >> 12) & 3) == 3);
 777 }
 778
 779 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 780                 u16 ddrcsr)
 781 {
 782         struct csrow_info *csrow;
 783         unsigned long last_cumul_size;
 784         int index, mem_dev, drc_chan;
 785         int drc_drbg;  /* DRB granularity 0=64mb, 1=128mb */
 786         int drc_ddim;  /* DRAM Data Integrity Mode 0=none, 2=edac */
 787         u8 value;
 788         u32 dra, drc, cumul_size;
 789
 790         dra = 0;
 791         for (index=0; index < 4; index++) {
 792                 u8 dra_reg;
 793                 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
 794                 dra |= dra_reg << (index * 8);
 795         }
 796         pci_read_config_dword(pdev, E752X_DRC, &drc);
 797         drc_chan = dual_channel_active(ddrcsr);
 798         drc_drbg = drc_chan + 1;  /* 128 in dual mode, 64 in single */
 799         drc_ddim = (drc >> 20) & 0x3;
 800
 801         /* The dram row boundary (DRB) reg values are boundary address for
 802          * each DRAM row with a granularity of 64 or 128MB (single/dual
 803          * channel operation).  DRB regs are cumulative; therefore DRB7 will
 804          * contain the total memory contained in all eight rows.
 805          */
 806         for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
 807                 /* mem_dev 0=x8, 1=x4 */
 808                 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
 809                 csrow = &mci->csrows[index];
 810
 811                 mem_dev = (mem_dev == 2);
 812                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
 813                 /* convert a 128 or 64 MiB DRB to a page size. */
 814                 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
 815                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 816                         cumul_size);
 817                 if (cumul_size == last_cumul_size)
 818                         continue;       /* not populated */
 819
 820                 csrow->first_page = last_cumul_size;
 821                 csrow->last_page = cumul_size - 1;
 822                 csrow->nr_pages = cumul_size - last_cumul_size;
 823                 last_cumul_size = cumul_size;
 824                 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
 825                 csrow->mtype = MEM_RDDR;        /* only one type supported */
 826                 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
 827
 828                 /*
 829                  * if single channel or x8 devices then SECDED
 830                  * if dual channel and x4 then S4ECD4ED
 831                  */
 832                 if (drc_ddim) {
 833                         if (drc_chan && mem_dev) {
 834                                 csrow->edac_mode = EDAC_S4ECD4ED;
 835                                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
 836                         } else {
 837                                 csrow->edac_mode = EDAC_SECDED;
 838                                 mci->edac_cap |= EDAC_FLAG_SECDED;
 839                         }
 840                 } else
 841                         csrow->edac_mode = EDAC_NONE;
 842         }
 843 }
 844
 845 static void e752x_init_mem_map_table(struct pci_dev *pdev,
 846                 struct e752x_pvt *pvt)
 847 {
 848         int index;
 849         u8 value, last, row, stat8;
 850
 851         last = 0;
 852         row = 0;
 853
 854         for (index = 0; index < 8; index += 2) {
 855                 pci_read_config_byte(pdev, E752X_DRB + index, &value);
 856                 /* test if there is a dimm in this slot */
 857                 if (value == last) {
 858                         /* no dimm in the slot, so flag it as empty */
 859                         pvt->map[index] = 0xff;
 860                         pvt->map[index + 1] = 0xff;
 861                 } else {        /* there is a dimm in the slot */
 862                         pvt->map[index] = row;
 863                         row++;
 864                         last = value;
 865                         /* test the next value to see if the dimm is double
 866                          * sided
 867                          */
 868                         pci_read_config_byte(pdev, E752X_DRB + index + 1,
 869                                              &value);
 870                         pvt->map[index + 1] = (value == last) ?
 871                             0xff :      /* the dimm is single sided,
 872                                            so flag as empty */
 873                             row;        /* this is a double sided dimm
 874                                            to save the next row # */
 875                         row++;
 876                         last = value;
 877                 }
 878         }
 879
 880         /* set the map type.  1 = normal, 0 = reversed */
 881         pci_read_config_byte(pdev, E752X_DRM, &stat8);
 882         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
 883 }
 884
 885 /* Return 0 on success or 1 on failure. */
 886 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
 887                 struct e752x_pvt *pvt)
 888 {
 889         struct pci_dev *dev;
 890
 891         pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
 892                                         pvt->dev_info->err_dev,
 893                                         pvt->bridge_ck);
 894
 895         if (pvt->bridge_ck == NULL)
 896                 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
 897                                                         PCI_DEVFN(0, 1));
 898
 899         if (pvt->bridge_ck == NULL) {
 900                 e752x_printk(KERN_ERR, "error reporting device not found:"
 901                        "vendor %x device 0x%x (broken BIOS?)\n",
 902                        PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
 903                 return 1;
 904         }
 905
 906         dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
 907                              NULL);
 908
 909         if (dev == NULL)
 910                 goto fail;
 911
 912         pvt->dev_d0f0 = dev;
 913         pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
 914
 915         return 0;
 916
 917 fail:
 918         pci_dev_put(pvt->bridge_ck);
 919         return 1;
 920 }
 921
 922 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
 923 {
 924         struct pci_dev *dev;
 925
 926         dev = pvt->dev_d0f1;
 927         /* Turn off error disable & SMI in case the BIOS turned it on */
 928         pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
 929         pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
 930         pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
 931         pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
 932         pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
 933         pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
 934         pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
 935         pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
 936 }
 937
 938 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
 939 {
 940         u16 pci_data;
 941         u8 stat8;
 942         struct mem_ctl_info *mci;
 943         struct e752x_pvt *pvt;
 944         u16 ddrcsr;
 945         int drc_chan;   /* Number of channels 0=1chan,1=2chan */
 946         struct e752x_error_info discard;
 947
 948         debugf0("%s(): mci\n", __func__);
 949         debugf0("Starting Probe1\n");
 950
 951         /* check to see if device 0 function 1 is enabled; if it isn't, we
 952          * assume the BIOS has reserved it for a reason and is expecting
 953          * exclusive access, we take care not to violate that assumption and
 954          * fail the probe. */
 955         pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
 956         if (!force_function_unhide && !(stat8 & (1 << 5))) {
 957                 printk(KERN_INFO "Contact your BIOS vendor to see if the "
 958                         "E752x error registers can be safely un-hidden\n");
 959                 return -ENOMEM;
 960         }
 961         stat8 |= (1 << 5);
 962         pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
 963
 964         pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
 965         /* FIXME: should check >>12 or 0xf, true for all? */
 966         /* Dual channel = 1, Single channel = 0 */
 967         drc_chan = dual_channel_active(ddrcsr);
 968
 969         mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
 970
 971         if (mci == NULL) {
 972                 return -ENOMEM;
 973         }
 974
 975         debugf3("%s(): init mci\n", __func__);
 976         mci->mtype_cap = MEM_FLAG_RDDR;
 977         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
 978             EDAC_FLAG_S4ECD4ED;
 979         /* FIXME - what if different memory types are in different csrows? */
 980         mci->mod_name = EDAC_MOD_STR;
 981         mci->mod_ver = E752X_REVISION;
 982         mci->dev = &pdev->dev;
 983
 984         debugf3("%s(): init pvt\n", __func__);
 985         pvt = (struct e752x_pvt *) mci->pvt_info;
 986         pvt->dev_info = &e752x_devs[dev_idx];
 987         pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
 988
 989         if (e752x_get_devs(pdev, dev_idx, pvt)) {
 990                 edac_mc_free(mci);
 991                 return -ENODEV;
 992         }
 993
 994         debugf3("%s(): more mci init\n", __func__);
 995         mci->ctl_name = pvt->dev_info->ctl_name;
 996         mci->edac_check = e752x_check;
 997         mci->ctl_page_to_phys = ctl_page_to_phys;
 998
 999         e752x_init_csrows(mci, pdev, ddrcsr);
1000         e752x_init_mem_map_table(pdev, pvt);
1001
1002         /* set the map type.  1 = normal, 0 = reversed */
1003         pci_read_config_byte(pdev, E752X_DRM, &stat8);
1004         pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1005
1006         mci->edac_cap |= EDAC_FLAG_NONE;
1007         debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1008
1009         /* load the top of low memory, remap base, and remap limit vars */
1010         pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1011         pvt->tolm = ((u32) pci_data) << 4;
1012         pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1013         pvt->remapbase = ((u32) pci_data) << 14;
1014         pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1015         pvt->remaplimit = ((u32) pci_data) << 14;
1016         e752x_printk(KERN_INFO,
1017                 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1018                 pvt->remapbase, pvt->remaplimit);
1019
1020         /* Here we assume that we will never see multiple instances of this
1021          * type of memory controller.  The ID is therefore hardcoded to 0.
1022          */
1023         if (edac_mc_add_mc(mci,0)) {
1024                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1025                 goto fail;
1026         }
1027
1028         e752x_init_error_reporting_regs(pvt);
1029         e752x_get_error_info(mci, &discard); /* clear other MCH errors */
1030
1031         /* get this far and it's successful */
1032         debugf3("%s(): success\n", __func__);
1033         return 0;
1034
1035 fail:
1036         pci_dev_put(pvt->dev_d0f0);
1037         pci_dev_put(pvt->dev_d0f1);
1038         pci_dev_put(pvt->bridge_ck);
1039         edac_mc_free(mci);
1040
1041         return -ENODEV;
1042 }
1043
1044 /* returns count (>= 0), or negative on error */
1045 static int __devinit e752x_init_one(struct pci_dev *pdev,
1046                 const struct pci_device_id *ent)
1047 {
1048         debugf0("%s()\n", __func__);
1049
1050         /* wake up and enable device */
1051         if(pci_enable_device(pdev) < 0)
1052                 return -EIO;
1053
1054         return e752x_probe1(pdev, ent->driver_data);
1055 }
1056
1057 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1058 {
1059         struct mem_ctl_info *mci;
1060         struct e752x_pvt *pvt;
1061
1062         debugf0("%s()\n", __func__);
1063
1064         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1065                 return;
1066
1067         pvt = (struct e752x_pvt *) mci->pvt_info;
1068         pci_dev_put(pvt->dev_d0f0);
1069         pci_dev_put(pvt->dev_d0f1);
1070         pci_dev_put(pvt->bridge_ck);
1071         edac_mc_free(mci);
1072 }
1073
1074 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1075         {
1076                 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1077                 E7520
1078         },
1079         {
1080                 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1081                 E7525
1082         },
1083         {
1084                 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1085                 E7320
1086         },
1087         {
1088                 0,
1089         }       /* 0 terminated list. */
1090 };
1091
1092 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1093
1094 static struct pci_driver e752x_driver = {
1095         .name = EDAC_MOD_STR,
1096         .probe = e752x_init_one,
1097         .remove = __devexit_p(e752x_remove_one),
1098         .id_table = e752x_pci_tbl,
1099 };
1100
1101 static int __init e752x_init(void)
1102 {
1103         int pci_rc;
1104
1105         debugf3("%s()\n", __func__);
1106         pci_rc = pci_register_driver(&e752x_driver);
1107         return (pci_rc < 0) ? pci_rc : 0;
1108 }
1109
1110 static void __exit e752x_exit(void)
1111 {
1112         debugf3("%s()\n", __func__);
1113         pci_unregister_driver(&e752x_driver);
1114 }
1115
1116 module_init(e752x_init);
1117 module_exit(e752x_exit);
1118
1119 MODULE_LICENSE("GPL");
1120 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1121 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1122
1123 module_param(force_function_unhide, int, 0444);
1124 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1125 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1126