drivers/edac/cpc925_edac.c

   1 /*
   2  * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
   3  *
   4  * Copyright (c) 2008 Wind River Systems, Inc.
   5  *
   6  * Authors:     Cao Qingtao <qingtao.cao@windriver.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  15  * See the GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/edac.h>
  26 #include <linux/of.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/gfp.h>
  29
  30 #include "edac_core.h"
  31 #include "edac_module.h"
  32
  33 #define CPC925_EDAC_REVISION    " Ver: 1.0.0"
  34 #define CPC925_EDAC_MOD_STR     "cpc925_edac"
  35
  36 #define cpc925_printk(level, fmt, arg...) \
  37         edac_printk(level, "CPC925", fmt, ##arg)
  38
  39 #define cpc925_mc_printk(mci, level, fmt, arg...) \
  40         edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)
  41
  42 /*
  43  * CPC925 registers are of 32 bits with bit0 defined at the
  44  * most significant bit and bit31 at that of least significant.
  45  */
  46 #define CPC925_BITS_PER_REG     32
  47 #define CPC925_BIT(nr)          (1UL << (CPC925_BITS_PER_REG - 1 - nr))
  48
  49 /*
  50  * EDAC device names for the error detections of
  51  * CPU Interface and Hypertransport Link.
  52  */
  53 #define CPC925_CPU_ERR_DEV      "cpu"
  54 #define CPC925_HT_LINK_DEV      "htlink"
  55
  56 /* Suppose DDR Refresh cycle is 15.6 microsecond */
  57 #define CPC925_REF_FREQ         0xFA69
  58 #define CPC925_SCRUB_BLOCK_SIZE 64      /* bytes */
  59 #define CPC925_NR_CSROWS        8
  60
  61 /*
  62  * All registers and bits definitions are taken from
  63  * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
  64  */
  65
  66 /*
  67  * CPU and Memory Controller Registers
  68  */
  69 /************************************************************
  70  *      Processor Interface Exception Mask Register (APIMASK)
  71  ************************************************************/
  72 #define REG_APIMASK_OFFSET      0x30070
  73 enum apimask_bits {
  74         APIMASK_DART    = CPC925_BIT(0), /* DART Exception */
  75         APIMASK_ADI0    = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
  76         APIMASK_ADI1    = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
  77         APIMASK_STAT    = CPC925_BIT(3), /* Status Exception */
  78         APIMASK_DERR    = CPC925_BIT(4), /* Data Error Exception */
  79         APIMASK_ADRS0   = CPC925_BIT(5), /* Addressing Exception on PI0 */
  80         APIMASK_ADRS1   = CPC925_BIT(6), /* Addressing Exception on PI1 */
  81                                          /* BIT(7) Reserved */
  82         APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
  83         APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
  84         APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
  85         APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
  86
  87         CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 |
  88                            APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 |
  89                            APIMASK_ADRS1),
  90         ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
  91                            APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
  92 };
  93 #define APIMASK_ADI(n)          CPC925_BIT(((n)+1))
  94
  95 /************************************************************
  96  *      Processor Interface Exception Register (APIEXCP)
  97  ************************************************************/
  98 #define REG_APIEXCP_OFFSET      0x30060
  99 enum apiexcp_bits {
 100         APIEXCP_DART    = CPC925_BIT(0), /* DART Exception */
 101         APIEXCP_ADI0    = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
 102         APIEXCP_ADI1    = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
 103         APIEXCP_STAT    = CPC925_BIT(3), /* Status Exception */
 104         APIEXCP_DERR    = CPC925_BIT(4), /* Data Error Exception */
 105         APIEXCP_ADRS0   = CPC925_BIT(5), /* Addressing Exception on PI0 */
 106         APIEXCP_ADRS1   = CPC925_BIT(6), /* Addressing Exception on PI1 */
 107                                          /* BIT(7) Reserved */
 108         APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
 109         APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
 110         APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
 111         APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
 112
 113         CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 |
 114                              APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 |
 115                              APIEXCP_ADRS1),
 116         UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L),
 117         CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L),
 118         ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED),
 119 };
 120
 121 /************************************************************
 122  *      Memory Bus Configuration Register (MBCR)
 123 ************************************************************/
 124 #define REG_MBCR_OFFSET         0x2190
 125 #define MBCR_64BITCFG_SHIFT     23
 126 #define MBCR_64BITCFG_MASK      (1UL << MBCR_64BITCFG_SHIFT)
 127 #define MBCR_64BITBUS_SHIFT     22
 128 #define MBCR_64BITBUS_MASK      (1UL << MBCR_64BITBUS_SHIFT)
 129
 130 /************************************************************
 131  *      Memory Bank Mode Register (MBMR)
 132 ************************************************************/
 133 #define REG_MBMR_OFFSET         0x21C0
 134 #define MBMR_MODE_MAX_VALUE     0xF
 135 #define MBMR_MODE_SHIFT         25
 136 #define MBMR_MODE_MASK          (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)
 137 #define MBMR_BBA_SHIFT          24
 138 #define MBMR_BBA_MASK           (1UL << MBMR_BBA_SHIFT)
 139
 140 /************************************************************
 141  *      Memory Bank Boundary Address Register (MBBAR)
 142  ************************************************************/
 143 #define REG_MBBAR_OFFSET        0x21D0
 144 #define MBBAR_BBA_MAX_VALUE     0xFF
 145 #define MBBAR_BBA_SHIFT         24
 146 #define MBBAR_BBA_MASK          (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)
 147
 148 /************************************************************
 149  *      Memory Scrub Control Register (MSCR)
 150  ************************************************************/
 151 #define REG_MSCR_OFFSET         0x2400
 152 #define MSCR_SCRUB_MOD_MASK     0xC0000000 /* scrub_mod - bit0:1*/
 153 #define MSCR_BACKGR_SCRUB       0x40000000 /* 01 */
 154 #define MSCR_SI_SHIFT           16      /* si - bit8:15*/
 155 #define MSCR_SI_MAX_VALUE       0xFF
 156 #define MSCR_SI_MASK            (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)
 157
 158 /************************************************************
 159  *      Memory Scrub Range Start Register (MSRSR)
 160  ************************************************************/
 161 #define REG_MSRSR_OFFSET        0x2410
 162
 163 /************************************************************
 164  *      Memory Scrub Range End Register (MSRER)
 165  ************************************************************/
 166 #define REG_MSRER_OFFSET        0x2420
 167
 168 /************************************************************
 169  *      Memory Scrub Pattern Register (MSPR)
 170  ************************************************************/
 171 #define REG_MSPR_OFFSET         0x2430
 172
 173 /************************************************************
 174  *      Memory Check Control Register (MCCR)
 175  ************************************************************/
 176 #define REG_MCCR_OFFSET         0x2440
 177 enum mccr_bits {
 178         MCCR_ECC_EN     = CPC925_BIT(0), /* ECC high and low check */
 179 };
 180
 181 /************************************************************
 182  *      Memory Check Range End Register (MCRER)
 183  ************************************************************/
 184 #define REG_MCRER_OFFSET        0x2450
 185
 186 /************************************************************
 187  *      Memory Error Address Register (MEAR)
 188  ************************************************************/
 189 #define REG_MEAR_OFFSET         0x2460
 190 #define MEAR_BCNT_MAX_VALUE     0x3
 191 #define MEAR_BCNT_SHIFT         30
 192 #define MEAR_BCNT_MASK          (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)
 193 #define MEAR_RANK_MAX_VALUE     0x7
 194 #define MEAR_RANK_SHIFT         27
 195 #define MEAR_RANK_MASK          (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)
 196 #define MEAR_COL_MAX_VALUE      0x7FF
 197 #define MEAR_COL_SHIFT          16
 198 #define MEAR_COL_MASK           (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)
 199 #define MEAR_BANK_MAX_VALUE     0x3
 200 #define MEAR_BANK_SHIFT         14
 201 #define MEAR_BANK_MASK          (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)
 202 #define MEAR_ROW_MASK           0x00003FFF
 203
 204 /************************************************************
 205  *      Memory Error Syndrome Register (MESR)
 206  ************************************************************/
 207 #define REG_MESR_OFFSET         0x2470
 208 #define MESR_ECC_SYN_H_MASK     0xFF00
 209 #define MESR_ECC_SYN_L_MASK     0x00FF
 210
 211 /************************************************************
 212  *      Memory Mode Control Register (MMCR)
 213  ************************************************************/
 214 #define REG_MMCR_OFFSET         0x2500
 215 enum mmcr_bits {
 216         MMCR_REG_DIMM_MODE = CPC925_BIT(3),
 217 };
 218
 219 /*
 220  * HyperTransport Link Registers
 221  */
 222 /************************************************************
 223  *  Error Handling/Enumeration Scratch Pad Register (ERRCTRL)
 224  ************************************************************/
 225 #define REG_ERRCTRL_OFFSET      0x70140
 226 enum errctrl_bits {                      /* nonfatal interrupts for */
 227         ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */
 228         ERRCTRL_CRC_NF  = CPC925_BIT(1), /* CRC error */
 229         ERRCTRL_RSP_NF  = CPC925_BIT(2), /* Response error */
 230         ERRCTRL_EOC_NF  = CPC925_BIT(3), /* End-Of-Chain error */
 231         ERRCTRL_OVF_NF  = CPC925_BIT(4), /* Overflow error */
 232         ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */
 233
 234         ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */
 235         ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */
 236
 237         HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF |
 238                              ERRCTRL_RSP_NF | ERRCTRL_EOC_NF |
 239                              ERRCTRL_OVF_NF | ERRCTRL_PROT_NF),
 240         HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL),
 241 };
 242
 243 /************************************************************
 244  *  Link Configuration and Link Control Register (LINKCTRL)
 245  ************************************************************/
 246 #define REG_LINKCTRL_OFFSET     0x70110
 247 enum linkctrl_bits {
 248         LINKCTRL_CRC_ERR        = (CPC925_BIT(22) | CPC925_BIT(23)),
 249         LINKCTRL_LINK_FAIL      = CPC925_BIT(27),
 250
 251         HT_LINKCTRL_DETECTED    = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL),
 252 };
 253
 254 /************************************************************
 255  *  Link FreqCap/Error/Freq/Revision ID Register (LINKERR)
 256  ************************************************************/
 257 #define REG_LINKERR_OFFSET      0x70120
 258 enum linkerr_bits {
 259         LINKERR_EOC_ERR         = CPC925_BIT(17), /* End-Of-Chain error */
 260         LINKERR_OVF_ERR         = CPC925_BIT(18), /* Receive Buffer Overflow */
 261         LINKERR_PROT_ERR        = CPC925_BIT(19), /* Protocol error */
 262
 263         HT_LINKERR_DETECTED     = (LINKERR_EOC_ERR | LINKERR_OVF_ERR |
 264                                    LINKERR_PROT_ERR),
 265 };
 266
 267 /************************************************************
 268  *      Bridge Control Register (BRGCTRL)
 269  ************************************************************/
 270 #define REG_BRGCTRL_OFFSET      0x70300
 271 enum brgctrl_bits {
 272         BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */
 273         BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */
 274 };
 275
 276 /* Private structure for edac memory controller */
 277 struct cpc925_mc_pdata {
 278         void __iomem *vbase;
 279         unsigned long total_mem;
 280         const char *name;
 281         int edac_idx;
 282 };
 283
 284 /* Private structure for common edac device */
 285 struct cpc925_dev_info {
 286         void __iomem *vbase;
 287         struct platform_device *pdev;
 288         char *ctl_name;
 289         int edac_idx;
 290         struct edac_device_ctl_info *edac_dev;
 291         void (*init)(struct cpc925_dev_info *dev_info);
 292         void (*exit)(struct cpc925_dev_info *dev_info);
 293         void (*check)(struct edac_device_ctl_info *edac_dev);
 294 };
 295
 296 /* Get total memory size from Open Firmware DTB */
 297 static void get_total_mem(struct cpc925_mc_pdata *pdata)
 298 {
 299         struct device_node *np = NULL;
 300         const unsigned int *reg, *reg_end;
 301         int len, sw, aw;
 302         unsigned long start, size;
 303
 304         np = of_find_node_by_type(NULL, "memory");
 305         if (!np)
 306                 return;
 307
 308         aw = of_n_addr_cells(np);
 309         sw = of_n_size_cells(np);
 310         reg = (const unsigned int *)of_get_property(np, "reg", &len);
 311         reg_end = reg + len/4;
 312
 313         pdata->total_mem = 0;
 314         do {
 315                 start = of_read_number(reg, aw);
 316                 reg += aw;
 317                 size = of_read_number(reg, sw);
 318                 reg += sw;
 319                 debugf1("%s: start 0x%lx, size 0x%lx\n", __func__,
 320                         start, size);
 321                 pdata->total_mem += size;
 322         } while (reg < reg_end);
 323
 324         of_node_put(np);
 325         debugf0("%s: total_mem 0x%lx\n", __func__, pdata->total_mem);
 326 }
 327
 328 static void cpc925_init_csrows(struct mem_ctl_info *mci)
 329 {
 330         struct cpc925_mc_pdata *pdata = mci->pvt_info;
 331         struct csrow_info *csrow;
 332         struct dimm_info *dimm;
 333         int index, j;
 334         u32 mbmr, mbbar, bba;
 335         unsigned long row_size, last_nr_pages = 0;
 336
 337         get_total_mem(pdata);
 338
 339         for (index = 0; index < mci->nr_csrows; index++) {
 340                 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
 341                                    0x20 * index);
 342                 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
 343                                    0x20 + index);
 344                 bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) |
 345                        ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT);
 346
 347                 if (bba == 0)
 348                         continue; /* not populated */
 349
 350                 csrow = &mci->csrows[index];
 351
 352                 row_size = bba * (1UL << 28);   /* 256M */
 353                 csrow->first_page = last_nr_pages;
 354                 csrow->nr_pages = row_size >> PAGE_SHIFT;
 355                 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
 356                 last_nr_pages = csrow->last_page + 1;
 357
 358                 for (j = 0; j < csrow->nr_channels; j++) {
 359                         dimm = csrow->channels[j].dimm;
 360                         dimm->mtype = MEM_RDDR;
 361                         dimm->edac_mode = EDAC_SECDED;
 362
 363                         switch (csrow->nr_channels) {
 364                         case 1: /* Single channel */
 365                                 dimm->grain = 32; /* four-beat burst of 32 bytes */
 366                                 break;
 367                         case 2: /* Dual channel */
 368                         default:
 369                                 dimm->grain = 64; /* four-beat burst of 64 bytes */
 370                                 break;
 371                         }
 372
 373                         switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) {
 374                         case 6: /* 0110, no way to differentiate X8 VS X16 */
 375                         case 5: /* 0101 */
 376                         case 8: /* 1000 */
 377                                 dimm->dtype = DEV_X16;
 378                                 break;
 379                         case 7: /* 0111 */
 380                         case 9: /* 1001 */
 381                                 dimm->dtype = DEV_X8;
 382                                 break;
 383                         default:
 384                                 dimm->dtype = DEV_UNKNOWN;
 385                                 break;
 386                         }
 387                 }
 388         }
 389 }
 390
 391 /* Enable memory controller ECC detection */
 392 static void cpc925_mc_init(struct mem_ctl_info *mci)
 393 {
 394         struct cpc925_mc_pdata *pdata = mci->pvt_info;
 395         u32 apimask;
 396         u32 mccr;
 397
 398         /* Enable various ECC error exceptions */
 399         apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
 400         if ((apimask & ECC_MASK_ENABLE) == 0) {
 401                 apimask |= ECC_MASK_ENABLE;
 402                 __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
 403         }
 404
 405         /* Enable ECC detection */
 406         mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
 407         if ((mccr & MCCR_ECC_EN) == 0) {
 408                 mccr |= MCCR_ECC_EN;
 409                 __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
 410         }
 411 }
 412
 413 /* Disable memory controller ECC detection */
 414 static void cpc925_mc_exit(struct mem_ctl_info *mci)
 415 {
 416         /*
 417          * WARNING:
 418          * We are supposed to clear the ECC error detection bits,
 419          * and it will be no problem to do so. However, once they
 420          * are cleared here if we want to re-install CPC925 EDAC
 421          * module later, setting them up in cpc925_mc_init() will
 422          * trigger machine check exception.
 423          * Also, it's ok to leave ECC error detection bits enabled,
 424          * since they are reset to 1 by default or by boot loader.
 425          */
 426
 427         return;
 428 }
 429
 430 /*
 431  * Revert DDR column/row/bank addresses into page frame number and
 432  * offset in page.
 433  *
 434  * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs),
 435  * physical address(PA) bits to column address(CA) bits mappings are:
 436  * CA   0   1   2   3   4   5   6   7   8   9   10
 437  * PA   59  58  57  56  55  54  53  52  51  50  49
 438  *
 439  * physical address(PA) bits to bank address(BA) bits mappings are:
 440  * BA   0   1
 441  * PA   43  44
 442  *
 443  * physical address(PA) bits to row address(RA) bits mappings are:
 444  * RA   0   1   2   3   4   5   6   7   8   9   10   11   12
 445  * PA   36  35  34  48  47  46  45  40  41  42  39   38   37
 446  */
 447 static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
 448                 unsigned long *pfn, unsigned long *offset, int *csrow)
 449 {
 450         u32 bcnt, rank, col, bank, row;
 451         u32 c;
 452         unsigned long pa;
 453         int i;
 454
 455         bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT;
 456         rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT;
 457         col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT;
 458         bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;
 459         row = mear & MEAR_ROW_MASK;
 460
 461         *csrow = rank;
 462
 463 #ifdef CONFIG_EDAC_DEBUG
 464         if (mci->csrows[rank].first_page == 0) {
 465                 cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a "
 466                         "non-populated csrow, broken hardware?\n");
 467                 return;
 468         }
 469 #endif
 470
 471         /* Revert csrow number */
 472         pa = mci->csrows[rank].first_page << PAGE_SHIFT;
 473
 474         /* Revert column address */
 475         col += bcnt;
 476         for (i = 0; i < 11; i++) {
 477                 c = col & 0x1;
 478                 col >>= 1;
 479                 pa |= c << (14 - i);
 480         }
 481
 482         /* Revert bank address */
 483         pa |= bank << 19;
 484
 485         /* Revert row address, in 4 steps */
 486         for (i = 0; i < 3; i++) {
 487                 c = row & 0x1;
 488                 row >>= 1;
 489                 pa |= c << (26 - i);
 490         }
 491
 492         for (i = 0; i < 3; i++) {
 493                 c = row & 0x1;
 494                 row >>= 1;
 495                 pa |= c << (21 + i);
 496         }
 497
 498         for (i = 0; i < 4; i++) {
 499                 c = row & 0x1;
 500                 row >>= 1;
 501                 pa |= c << (18 - i);
 502         }
 503
 504         for (i = 0; i < 3; i++) {
 505                 c = row & 0x1;
 506                 row >>= 1;
 507                 pa |= c << (29 - i);
 508         }
 509
 510         *offset = pa & (PAGE_SIZE - 1);
 511         *pfn = pa >> PAGE_SHIFT;
 512
 513         debugf0("%s: ECC physical address 0x%lx\n", __func__, pa);
 514 }
 515
 516 static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
 517 {
 518         if ((syndrome & MESR_ECC_SYN_H_MASK) == 0)
 519                 return 0;
 520
 521         if ((syndrome & MESR_ECC_SYN_L_MASK) == 0)
 522                 return 1;
 523
 524         cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n",
 525                          syndrome);
 526         return 1;
 527 }
 528
 529 /* Check memory controller registers for ECC errors */
 530 static void cpc925_mc_check(struct mem_ctl_info *mci)
 531 {
 532         struct cpc925_mc_pdata *pdata = mci->pvt_info;
 533         u32 apiexcp;
 534         u32 mear;
 535         u32 mesr;
 536         u16 syndrome;
 537         unsigned long pfn = 0, offset = 0;
 538         int csrow = 0, channel = 0;
 539
 540         /* APIEXCP is cleared when read */
 541         apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
 542         if ((apiexcp & ECC_EXCP_DETECTED) == 0)
 543                 return;
 544
 545         mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
 546         syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK);
 547
 548         mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
 549
 550         /* Revert column/row addresses into page frame number, etc */
 551         cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow);
 552
 553         if (apiexcp & CECC_EXCP_DETECTED) {
 554                 cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
 555                 channel = cpc925_mc_find_channel(mci, syndrome);
 556                 edac_mc_handle_ce(mci, pfn, offset, syndrome,
 557                                   csrow, channel, mci->ctl_name);
 558         }
 559
 560         if (apiexcp & UECC_EXCP_DETECTED) {
 561                 cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
 562                 edac_mc_handle_ue(mci, pfn, offset, csrow, mci->ctl_name);
 563         }
 564
 565         cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
 566         cpc925_mc_printk(mci, KERN_INFO, "APIMASK               0x%08x\n",
 567                 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
 568         cpc925_mc_printk(mci, KERN_INFO, "APIEXCP               0x%08x\n",
 569                 apiexcp);
 570         cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl        0x%08x\n",
 571                 __raw_readl(pdata->vbase + REG_MSCR_OFFSET));
 572         cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start   0x%08x\n",
 573                 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
 574         cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End     0x%08x\n",
 575                 __raw_readl(pdata->vbase + REG_MSRER_OFFSET));
 576         cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern     0x%08x\n",
 577                 __raw_readl(pdata->vbase + REG_MSPR_OFFSET));
 578         cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl          0x%08x\n",
 579                 __raw_readl(pdata->vbase + REG_MCCR_OFFSET));
 580         cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End       0x%08x\n",
 581                 __raw_readl(pdata->vbase + REG_MCRER_OFFSET));
 582         cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address       0x%08x\n",
 583                 mesr);
 584         cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome      0x%08x\n",
 585                 syndrome);
 586 }
 587
 588 /******************** CPU err device********************************/
 589 static u32 cpc925_cpu_mask_disabled(void)
 590 {
 591         struct device_node *cpus;
 592         struct device_node *cpunode = NULL;
 593         static u32 mask = 0;
 594
 595         /* use cached value if available */
 596         if (mask != 0)
 597                 return mask;
 598
 599         mask = APIMASK_ADI0 | APIMASK_ADI1;
 600
 601         cpus = of_find_node_by_path("/cpus");
 602         if (cpus == NULL) {
 603                 cpc925_printk(KERN_DEBUG, "No /cpus node !\n");
 604                 return 0;
 605         }
 606
 607         while ((cpunode = of_get_next_child(cpus, cpunode)) != NULL) {
 608                 const u32 *reg = of_get_property(cpunode, "reg", NULL);
 609
 610                 if (strcmp(cpunode->type, "cpu")) {
 611                         cpc925_printk(KERN_ERR, "Not a cpu node in /cpus: %s\n", cpunode->name);
 612                         continue;
 613                 }
 614
 615                 if (reg == NULL || *reg > 2) {
 616                         cpc925_printk(KERN_ERR, "Bad reg value at %s\n", cpunode->full_name);
 617                         continue;
 618                 }
 619
 620                 mask &= ~APIMASK_ADI(*reg);
 621         }
 622
 623         if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
 624                 /* We assume that each CPU sits on it's own PI and that
 625                  * for present CPUs the reg property equals to the PI
 626                  * interface id */
 627                 cpc925_printk(KERN_WARNING,
 628                                 "Assuming PI id is equal to CPU MPIC id!\n");
 629         }
 630
 631         of_node_put(cpunode);
 632         of_node_put(cpus);
 633
 634         return mask;
 635 }
 636
 637 /* Enable CPU Errors detection */
 638 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
 639 {
 640         u32 apimask;
 641         u32 cpumask;
 642
 643         apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
 644
 645         cpumask = cpc925_cpu_mask_disabled();
 646         if (apimask & cpumask) {
 647                 cpc925_printk(KERN_WARNING, "CPU(s) not present, "
 648                                 "but enabled in APIMASK, disabling\n");
 649                 apimask &= ~cpumask;
 650         }
 651
 652         if ((apimask & CPU_MASK_ENABLE) == 0)
 653                 apimask |= CPU_MASK_ENABLE;
 654
 655         __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
 656 }
 657
 658 /* Disable CPU Errors detection */
 659 static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info)
 660 {
 661         /*
 662          * WARNING:
 663          * We are supposed to clear the CPU error detection bits,
 664          * and it will be no problem to do so. However, once they
 665          * are cleared here if we want to re-install CPC925 EDAC
 666          * module later, setting them up in cpc925_cpu_init() will
 667          * trigger machine check exception.
 668          * Also, it's ok to leave CPU error detection bits enabled,
 669          * since they are reset to 1 by default.
 670          */
 671
 672         return;
 673 }
 674
 675 /* Check for CPU Errors */
 676 static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
 677 {
 678         struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
 679         u32 apiexcp;
 680         u32 apimask;
 681
 682         /* APIEXCP is cleared when read */
 683         apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
 684         if ((apiexcp & CPU_EXCP_DETECTED) == 0)
 685                 return;
 686
 687         if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
 688                 return;
 689
 690         apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
 691         cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
 692                                  "Processor Interface register dump:\n");
 693         cpc925_printk(KERN_INFO, "APIMASK               0x%08x\n", apimask);
 694         cpc925_printk(KERN_INFO, "APIEXCP               0x%08x\n", apiexcp);
 695
 696         edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
 697 }
 698
 699 /******************** HT Link err device****************************/
 700 /* Enable HyperTransport Link Error detection */
 701 static void cpc925_htlink_init(struct cpc925_dev_info *dev_info)
 702 {
 703         u32 ht_errctrl;
 704
 705         ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
 706         if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) {
 707                 ht_errctrl |= HT_ERRCTRL_ENABLE;
 708                 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
 709         }
 710 }
 711
 712 /* Disable HyperTransport Link Error detection */
 713 static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info)
 714 {
 715         u32 ht_errctrl;
 716
 717         ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
 718         ht_errctrl &= ~HT_ERRCTRL_ENABLE;
 719         __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
 720 }
 721
 722 /* Check for HyperTransport Link errors */
 723 static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev)
 724 {
 725         struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
 726         u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
 727         u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
 728         u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
 729         u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
 730
 731         if (!((brgctrl & BRGCTRL_DETSERR) ||
 732               (linkctrl & HT_LINKCTRL_DETECTED) ||
 733               (errctrl & HT_ERRCTRL_DETECTED) ||
 734               (linkerr & HT_LINKERR_DETECTED)))
 735                 return;
 736
 737         cpc925_printk(KERN_INFO, "HT Link Fault\n"
 738                                  "HT register dump:\n");
 739         cpc925_printk(KERN_INFO, "Bridge Ctrl                   0x%08x\n",
 740                       brgctrl);
 741         cpc925_printk(KERN_INFO, "Link Config Ctrl              0x%08x\n",
 742                       linkctrl);
 743         cpc925_printk(KERN_INFO, "Error Enum and Ctrl           0x%08x\n",
 744                       errctrl);
 745         cpc925_printk(KERN_INFO, "Link Error                    0x%08x\n",
 746                       linkerr);
 747
 748         /* Clear by write 1 */
 749         if (brgctrl & BRGCTRL_DETSERR)
 750                 __raw_writel(BRGCTRL_DETSERR,
 751                                 dev_info->vbase + REG_BRGCTRL_OFFSET);
 752
 753         if (linkctrl & HT_LINKCTRL_DETECTED)
 754                 __raw_writel(HT_LINKCTRL_DETECTED,
 755                                 dev_info->vbase + REG_LINKCTRL_OFFSET);
 756
 757         /* Initiate Secondary Bus Reset to clear the chain failure */
 758         if (errctrl & ERRCTRL_CHN_FAL)
 759                 __raw_writel(BRGCTRL_SECBUSRESET,
 760                                 dev_info->vbase + REG_BRGCTRL_OFFSET);
 761
 762         if (errctrl & ERRCTRL_RSP_ERR)
 763                 __raw_writel(ERRCTRL_RSP_ERR,
 764                                 dev_info->vbase + REG_ERRCTRL_OFFSET);
 765
 766         if (linkerr & HT_LINKERR_DETECTED)
 767                 __raw_writel(HT_LINKERR_DETECTED,
 768                                 dev_info->vbase + REG_LINKERR_OFFSET);
 769
 770         edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
 771 }
 772
 773 static struct cpc925_dev_info cpc925_devs[] = {
 774         {
 775         .ctl_name = CPC925_CPU_ERR_DEV,
 776         .init = cpc925_cpu_init,
 777         .exit = cpc925_cpu_exit,
 778         .check = cpc925_cpu_check,
 779         },
 780         {
 781         .ctl_name = CPC925_HT_LINK_DEV,
 782         .init = cpc925_htlink_init,
 783         .exit = cpc925_htlink_exit,
 784         .check = cpc925_htlink_check,
 785         },
 786         {0}, /* Terminated by NULL */
 787 };
 788
 789 /*
 790  * Add CPU Err detection and HyperTransport Link Err detection
 791  * as common "edac_device", they have no corresponding device
 792  * nodes in the Open Firmware DTB and we have to add platform
 793  * devices for them. Also, they will share the MMIO with that
 794  * of memory controller.
 795  */
 796 static void cpc925_add_edac_devices(void __iomem *vbase)
 797 {
 798         struct cpc925_dev_info *dev_info;
 799
 800         if (!vbase) {
 801                 cpc925_printk(KERN_ERR, "MMIO not established yet\n");
 802                 return;
 803         }
 804
 805         for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
 806                 dev_info->vbase = vbase;
 807                 dev_info->pdev = platform_device_register_simple(
 808                                         dev_info->ctl_name, 0, NULL, 0);
 809                 if (IS_ERR(dev_info->pdev)) {
 810                         cpc925_printk(KERN_ERR,
 811                                 "Can't register platform device for %s\n",
 812                                 dev_info->ctl_name);
 813                         continue;
 814                 }
 815
 816                 /*
 817                  * Don't have to allocate private structure but
 818                  * make use of cpc925_devs[] instead.
 819                  */
 820                 dev_info->edac_idx = edac_device_alloc_index();
 821                 dev_info->edac_dev =
 822                         edac_device_alloc_ctl_info(0, dev_info->ctl_name,
 823                                 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx);
 824                 if (!dev_info->edac_dev) {
 825                         cpc925_printk(KERN_ERR, "No memory for edac device\n");
 826                         goto err1;
 827                 }
 828
 829                 dev_info->edac_dev->pvt_info = dev_info;
 830                 dev_info->edac_dev->dev = &dev_info->pdev->dev;
 831                 dev_info->edac_dev->ctl_name = dev_info->ctl_name;
 832                 dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR;
 833                 dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev);
 834
 835                 if (edac_op_state == EDAC_OPSTATE_POLL)
 836                         dev_info->edac_dev->edac_check = dev_info->check;
 837
 838                 if (dev_info->init)
 839                         dev_info->init(dev_info);
 840
 841                 if (edac_device_add_device(dev_info->edac_dev) > 0) {
 842                         cpc925_printk(KERN_ERR,
 843                                 "Unable to add edac device for %s\n",
 844                                 dev_info->ctl_name);
 845                         goto err2;
 846                 }
 847
 848                 debugf0("%s: Successfully added edac device for %s\n",
 849                         __func__, dev_info->ctl_name);
 850
 851                 continue;
 852
 853 err2:
 854                 if (dev_info->exit)
 855                         dev_info->exit(dev_info);
 856                 edac_device_free_ctl_info(dev_info->edac_dev);
 857 err1:
 858                 platform_device_unregister(dev_info->pdev);
 859         }
 860 }
 861
 862 /*
 863  * Delete the common "edac_device" for CPU Err Detection
 864  * and HyperTransport Link Err Detection
 865  */
 866 static void cpc925_del_edac_devices(void)
 867 {
 868         struct cpc925_dev_info *dev_info;
 869
 870         for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
 871                 if (dev_info->edac_dev) {
 872                         edac_device_del_device(dev_info->edac_dev->dev);
 873                         edac_device_free_ctl_info(dev_info->edac_dev);
 874                         platform_device_unregister(dev_info->pdev);
 875                 }
 876
 877                 if (dev_info->exit)
 878                         dev_info->exit(dev_info);
 879
 880                 debugf0("%s: Successfully deleted edac device for %s\n",
 881                         __func__, dev_info->ctl_name);
 882         }
 883 }
 884
 885 /* Convert current back-ground scrub rate into byte/sec bandwidth */
 886 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
 887 {
 888         struct cpc925_mc_pdata *pdata = mci->pvt_info;
 889         int bw;
 890         u32 mscr;
 891         u8 si;
 892
 893         mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
 894         si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
 895
 896         debugf0("%s, Mem Scrub Ctrl Register 0x%x\n", __func__, mscr);
 897
 898         if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
 899             (si == 0)) {
 900                 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
 901                 bw = 0;
 902         } else
 903                 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
 904
 905         return bw;
 906 }
 907
 908 /* Return 0 for single channel; 1 for dual channel */
 909 static int cpc925_mc_get_channels(void __iomem *vbase)
 910 {
 911         int dual = 0;
 912         u32 mbcr;
 913
 914         mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
 915
 916         /*
 917          * Dual channel only when 128-bit wide physical bus
 918          * and 128-bit configuration.
 919          */
 920         if (((mbcr & MBCR_64BITCFG_MASK) == 0) &&
 921             ((mbcr & MBCR_64BITBUS_MASK) == 0))
 922                 dual = 1;
 923
 924         debugf0("%s: %s channel\n", __func__,
 925                 (dual > 0) ? "Dual" : "Single");
 926
 927         return dual;
 928 }
 929
 930 static int __devinit cpc925_probe(struct platform_device *pdev)
 931 {
 932         static int edac_mc_idx;
 933         struct mem_ctl_info *mci;
 934         void __iomem *vbase;
 935         struct cpc925_mc_pdata *pdata;
 936         struct resource *r;
 937         int res = 0, nr_channels;
 938
 939         debugf0("%s: %s platform device found!\n", __func__, pdev->name);
 940
 941         if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
 942                 res = -ENOMEM;
 943                 goto out;
 944         }
 945
 946         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 947         if (!r) {
 948                 cpc925_printk(KERN_ERR, "Unable to get resource\n");
 949                 res = -ENOENT;
 950                 goto err1;
 951         }
 952
 953         if (!devm_request_mem_region(&pdev->dev,
 954                                      r->start,
 955                                      resource_size(r),
 956                                      pdev->name)) {
 957                 cpc925_printk(KERN_ERR, "Unable to request mem region\n");
 958                 res = -EBUSY;
 959                 goto err1;
 960         }
 961
 962         vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 963         if (!vbase) {
 964                 cpc925_printk(KERN_ERR, "Unable to ioremap device\n");
 965                 res = -ENOMEM;
 966                 goto err2;
 967         }
 968
 969         nr_channels = cpc925_mc_get_channels(vbase) + 1;
 970         mci = edac_mc_alloc(sizeof(struct cpc925_mc_pdata),
 971                         CPC925_NR_CSROWS, nr_channels, edac_mc_idx);
 972         if (!mci) {
 973                 cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
 974                 res = -ENOMEM;
 975                 goto err2;
 976         }
 977
 978         pdata = mci->pvt_info;
 979         pdata->vbase = vbase;
 980         pdata->edac_idx = edac_mc_idx++;
 981         pdata->name = pdev->name;
 982
 983         mci->dev = &pdev->dev;
 984         platform_set_drvdata(pdev, mci);
 985         mci->dev_name = dev_name(&pdev->dev);
 986         mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
 987         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 988         mci->edac_cap = EDAC_FLAG_SECDED;
 989         mci->mod_name = CPC925_EDAC_MOD_STR;
 990         mci->mod_ver = CPC925_EDAC_REVISION;
 991         mci->ctl_name = pdev->name;
 992
 993         if (edac_op_state == EDAC_OPSTATE_POLL)
 994                 mci->edac_check = cpc925_mc_check;
 995
 996         mci->ctl_page_to_phys = NULL;
 997         mci->scrub_mode = SCRUB_SW_SRC;
 998         mci->set_sdram_scrub_rate = NULL;
 999         mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate;
1000
1001         cpc925_init_csrows(mci);
1002
1003         /* Setup memory controller registers */
1004         cpc925_mc_init(mci);
1005
1006         if (edac_mc_add_mc(mci) > 0) {
1007                 cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n");
1008                 goto err3;
1009         }
1010
1011         cpc925_add_edac_devices(vbase);
1012
1013         /* get this far and it's successful */
1014         debugf0("%s: success\n", __func__);
1015
1016         res = 0;
1017         goto out;
1018
1019 err3:
1020         cpc925_mc_exit(mci);
1021         edac_mc_free(mci);
1022 err2:
1023         devm_release_mem_region(&pdev->dev, r->start, resource_size(r));
1024 err1:
1025         devres_release_group(&pdev->dev, cpc925_probe);
1026 out:
1027         return res;
1028 }
1029
1030 static int cpc925_remove(struct platform_device *pdev)
1031 {
1032         struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1033
1034         /*
1035          * Delete common edac devices before edac mc, because
1036          * the former share the MMIO of the latter.
1037          */
1038         cpc925_del_edac_devices();
1039         cpc925_mc_exit(mci);
1040
1041         edac_mc_del_mc(&pdev->dev);
1042         edac_mc_free(mci);
1043
1044         return 0;
1045 }
1046
1047 static struct platform_driver cpc925_edac_driver = {
1048         .probe = cpc925_probe,
1049         .remove = cpc925_remove,
1050         .driver = {
1051                    .name = "cpc925_edac",
1052         }
1053 };
1054
1055 static int __init cpc925_edac_init(void)
1056 {
1057         int ret = 0;
1058
1059         printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n");
1060         printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n");
1061
1062         /* Only support POLL mode so far */
1063         edac_op_state = EDAC_OPSTATE_POLL;
1064
1065         ret = platform_driver_register(&cpc925_edac_driver);
1066         if (ret) {
1067                 printk(KERN_WARNING "Failed to register %s\n",
1068                         CPC925_EDAC_MOD_STR);
1069         }
1070
1071         return ret;
1072 }
1073
1074 static void __exit cpc925_edac_exit(void)
1075 {
1076         platform_driver_unregister(&cpc925_edac_driver);
1077 }
1078
1079 module_init(cpc925_edac_init);
1080 module_exit(cpc925_edac_exit);
1081
1082 MODULE_LICENSE("GPL");
1083 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");
1084 MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module");