drivers/dma/ste_dma40_ll.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2007-2010
   3  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   4  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <plat/ste_dma40.h>
  10
  11 #include "ste_dma40_ll.h"
  12
  13 /* Sets up proper LCSP1 and LCSP3 register for a logical channel */
  14 void d40_log_cfg(struct stedma40_chan_cfg *cfg,
  15                  u32 *lcsp1, u32 *lcsp3)
  16 {
  17         u32 l3 = 0; /* dst */
  18         u32 l1 = 0; /* src */
  19
  20         /* src is mem? -> increase address pos */
  21         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
  22             cfg->dir ==  STEDMA40_MEM_TO_MEM)
  23                 l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
  24
  25         /* dst is mem? -> increase address pos */
  26         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
  27             cfg->dir ==  STEDMA40_MEM_TO_MEM)
  28                 l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
  29
  30         /* src is hw? -> master port 1 */
  31         if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
  32             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
  33                 l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
  34
  35         /* dst is hw? -> master port 1 */
  36         if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
  37             cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
  38                 l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
  39
  40         l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
  41         l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
  42         l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
  43
  44         l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
  45         l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
  46         l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
  47
  48         *lcsp1 = l1;
  49         *lcsp3 = l3;
  50
  51 }
  52
  53 /* Sets up SRC and DST CFG register for both logical and physical channels */
  54 void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
  55                  u32 *src_cfg, u32 *dst_cfg, bool is_log)
  56 {
  57         u32 src = 0;
  58         u32 dst = 0;
  59
  60         if (!is_log) {
  61                 /* Physical channel */
  62                 if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
  63                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
  64                         /* Set master port to 1 */
  65                         src |= 1 << D40_SREG_CFG_MST_POS;
  66                         src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);
  67
  68                         if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
  69                                 src |= 1 << D40_SREG_CFG_PHY_TM_POS;
  70                         else
  71                                 src |= 3 << D40_SREG_CFG_PHY_TM_POS;
  72                 }
  73                 if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
  74                     (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
  75                         /* Set master port to 1 */
  76                         dst |= 1 << D40_SREG_CFG_MST_POS;
  77                         dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
  78
  79                         if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
  80                                 dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
  81                         else
  82                                 dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
  83                 }
  84                 /* Interrupt on end of transfer for destination */
  85                 dst |= 1 << D40_SREG_CFG_TIM_POS;
  86
  87                 /* Generate interrupt on error */
  88                 src |= 1 << D40_SREG_CFG_EIM_POS;
  89                 dst |= 1 << D40_SREG_CFG_EIM_POS;
  90
  91                 /* PSIZE */
  92                 if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
  93                         src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
  94                         src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
  95                 }
  96                 if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
  97                         dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
  98                         dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
  99                 }
 100
 101                 /* Element size */
 102                 src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
 103                 dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
 104
 105         } else {
 106                 /* Logical channel */
 107                 dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
 108                 src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
 109         }
 110
 111         if (cfg->high_priority) {
 112                 src |= 1 << D40_SREG_CFG_PRI_POS;
 113                 dst |= 1 << D40_SREG_CFG_PRI_POS;
 114         }
 115
 116         if (cfg->src_info.big_endian)
 117                 src |= 1 << D40_SREG_CFG_LBE_POS;
 118         if (cfg->dst_info.big_endian)
 119                 dst |= 1 << D40_SREG_CFG_LBE_POS;
 120
 121         *src_cfg = src;
 122         *dst_cfg = dst;
 123 }
 124
 125 static int d40_phy_fill_lli(struct d40_phy_lli *lli,
 126                             dma_addr_t data,
 127                             u32 data_size,
 128                             int psize,
 129                             dma_addr_t next_lli,
 130                             u32 reg_cfg,
 131                             bool term_int,
 132                             u32 data_width,
 133                             bool is_device)
 134 {
 135         int num_elems;
 136
 137         if (psize == STEDMA40_PSIZE_PHY_1)
 138                 num_elems = 1;
 139         else
 140                 num_elems = 2 << psize;
 141
 142         /* Must be aligned */
 143         if (!IS_ALIGNED(data, 0x1 << data_width))
 144                 return -EINVAL;
 145
 146         /* Transfer size can't be smaller than (num_elms * elem_size) */
 147         if (data_size < num_elems * (0x1 << data_width))
 148                 return -EINVAL;
 149
 150         /* The number of elements. IE now many chunks */
 151         lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
 152
 153         /*
 154          * Distance to next element sized entry.
 155          * Usually the size of the element unless you want gaps.
 156          */
 157         if (!is_device)
 158                 lli->reg_elt |= (0x1 << data_width) <<
 159                         D40_SREG_ELEM_PHY_EIDX_POS;
 160
 161         /* Where the data is */
 162         lli->reg_ptr = data;
 163         lli->reg_cfg = reg_cfg;
 164
 165         /* If this scatter list entry is the last one, no next link */
 166         if (next_lli == 0)
 167                 lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
 168         else
 169                 lli->reg_lnk = next_lli;
 170
 171         /* Set/clear interrupt generation on this link item.*/
 172         if (term_int)
 173                 lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
 174         else
 175                 lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
 176
 177         /* Post link */
 178         lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
 179
 180         return 0;
 181 }
 182
 183 static int d40_seg_size(int size, int data_width1, int data_width2)
 184 {
 185         u32 max_w = max(data_width1, data_width2);
 186         u32 min_w = min(data_width1, data_width2);
 187         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
 188
 189         if (seg_max > STEDMA40_MAX_SEG_SIZE)
 190                 seg_max -= (1 << max_w);
 191
 192         if (size <= seg_max)
 193                 return size;
 194
 195         if (size <= 2 * seg_max)
 196                 return ALIGN(size / 2, 1 << max_w);
 197
 198         return seg_max;
 199 }
 200
 201 struct d40_phy_lli *d40_phy_buf_to_lli(struct d40_phy_lli *lli,
 202                                        dma_addr_t addr,
 203                                        u32 size,
 204                                        int psize,
 205                                        dma_addr_t lli_phys,
 206                                        u32 reg_cfg,
 207                                        bool term_int,
 208                                        u32 data_width1,
 209                                        u32 data_width2,
 210                                        bool is_device)
 211 {
 212         int err;
 213         dma_addr_t next = lli_phys;
 214         int size_rest = size;
 215         int size_seg = 0;
 216
 217         do {
 218                 size_seg = d40_seg_size(size_rest, data_width1, data_width2);
 219                 size_rest -= size_seg;
 220
 221                 if (term_int && size_rest == 0)
 222                         next = 0;
 223                 else
 224                         next = ALIGN(next + sizeof(struct d40_phy_lli),
 225                                      D40_LLI_ALIGN);
 226
 227                 err = d40_phy_fill_lli(lli,
 228                                        addr,
 229                                        size_seg,
 230                                        psize,
 231                                        next,
 232                                        reg_cfg,
 233                                        !next,
 234                                        data_width1,
 235                                        is_device);
 236
 237                 if (err)
 238                         goto err;
 239
 240                 lli++;
 241                 if (!is_device)
 242                         addr += size_seg;
 243         } while (size_rest);
 244
 245         return lli;
 246
 247  err:
 248         return NULL;
 249 }
 250
 251 int d40_phy_sg_to_lli(struct scatterlist *sg,
 252                       int sg_len,
 253                       dma_addr_t target,
 254                       struct d40_phy_lli *lli_sg,
 255                       dma_addr_t lli_phys,
 256                       u32 reg_cfg,
 257                       u32 data_width1,
 258                       u32 data_width2,
 259                       int psize)
 260 {
 261         int total_size = 0;
 262         int i;
 263         struct scatterlist *current_sg = sg;
 264         dma_addr_t dst;
 265         struct d40_phy_lli *lli = lli_sg;
 266         dma_addr_t l_phys = lli_phys;
 267
 268         for_each_sg(sg, current_sg, sg_len, i) {
 269
 270                 total_size += sg_dma_len(current_sg);
 271
 272                 if (target)
 273                         dst = target;
 274                 else
 275                         dst = sg_phys(current_sg);
 276
 277                 l_phys = ALIGN(lli_phys + (lli - lli_sg) *
 278                                sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
 279
 280                 lli = d40_phy_buf_to_lli(lli,
 281                                          dst,
 282                                          sg_dma_len(current_sg),
 283                                          psize,
 284                                          l_phys,
 285                                          reg_cfg,
 286                                          sg_len - 1 == i,
 287                                          data_width1,
 288                                          data_width2,
 289                                          target == dst);
 290                 if (lli == NULL)
 291                         return -EINVAL;
 292         }
 293
 294         return total_size;
 295 }
 296
 297
 298 void d40_phy_lli_write(void __iomem *virtbase,
 299                        u32 phy_chan_num,
 300                        struct d40_phy_lli *lli_dst,
 301                        struct d40_phy_lli *lli_src)
 302 {
 303
 304         writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
 305                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
 306         writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
 307                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
 308         writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
 309                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
 310         writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
 311                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
 312
 313         writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
 314                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
 315         writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
 316                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
 317         writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
 318                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
 319         writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
 320                phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
 321
 322 }
 323
 324 /* DMA logical lli operations */
 325
 326 static void d40_log_lli_link(struct d40_log_lli *lli_dst,
 327                              struct d40_log_lli *lli_src,
 328                              int next)
 329 {
 330         u32 slos = 0;
 331         u32 dlos = 0;
 332
 333         if (next != -EINVAL) {
 334                 slos = next * 2;
 335                 dlos = next * 2 + 1;
 336         } else {
 337                 lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
 338                 lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
 339         }
 340
 341         lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
 342                 (slos << D40_MEM_LCSP1_SLOS_POS);
 343
 344         lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
 345                 (dlos << D40_MEM_LCSP1_SLOS_POS);
 346 }
 347
 348 void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
 349                            struct d40_log_lli *lli_dst,
 350                            struct d40_log_lli *lli_src,
 351                            int next)
 352 {
 353         d40_log_lli_link(lli_dst, lli_src, next);
 354
 355         writel(lli_src->lcsp02, &lcpa[0].lcsp0);
 356         writel(lli_src->lcsp13, &lcpa[0].lcsp1);
 357         writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
 358         writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
 359 }
 360
 361 void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
 362                            struct d40_log_lli *lli_dst,
 363                            struct d40_log_lli *lli_src,
 364                            int next)
 365 {
 366         d40_log_lli_link(lli_dst, lli_src, next);
 367
 368         writel(lli_src->lcsp02, &lcla[0].lcsp02);
 369         writel(lli_src->lcsp13, &lcla[0].lcsp13);
 370         writel(lli_dst->lcsp02, &lcla[1].lcsp02);
 371         writel(lli_dst->lcsp13, &lcla[1].lcsp13);
 372 }
 373
 374 static void d40_log_fill_lli(struct d40_log_lli *lli,
 375                              dma_addr_t data, u32 data_size,
 376                              u32 reg_cfg,
 377                              u32 data_width,
 378                              bool addr_inc)
 379 {
 380         lli->lcsp13 = reg_cfg;
 381
 382         /* The number of elements to transfer */
 383         lli->lcsp02 = ((data_size >> data_width) <<
 384                        D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
 385
 386         BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
 387
 388         /* 16 LSBs address of the current element */
 389         lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
 390         /* 16 MSBs address of the current element */
 391         lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;
 392
 393         if (addr_inc)
 394                 lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
 395
 396 }
 397
 398 int d40_log_sg_to_dev(struct scatterlist *sg,
 399                       int sg_len,
 400                       struct d40_log_lli_bidir *lli,
 401                       struct d40_def_lcsp *lcsp,
 402                       u32 src_data_width,
 403                       u32 dst_data_width,
 404                       enum dma_data_direction direction,
 405                       dma_addr_t dev_addr)
 406 {
 407         int total_size = 0;
 408         struct scatterlist *current_sg = sg;
 409         int i;
 410         struct d40_log_lli *lli_src = lli->src;
 411         struct d40_log_lli *lli_dst = lli->dst;
 412
 413         for_each_sg(sg, current_sg, sg_len, i) {
 414                 total_size += sg_dma_len(current_sg);
 415
 416                 if (direction == DMA_TO_DEVICE) {
 417                         lli_src =
 418                                 d40_log_buf_to_lli(lli_src,
 419                                                    sg_phys(current_sg),
 420                                                    sg_dma_len(current_sg),
 421                                                    lcsp->lcsp1, src_data_width,
 422                                                    dst_data_width,
 423                                                    true);
 424                         lli_dst =
 425                                 d40_log_buf_to_lli(lli_dst,
 426                                                    dev_addr,
 427                                                    sg_dma_len(current_sg),
 428                                                    lcsp->lcsp3, dst_data_width,
 429                                                    src_data_width,
 430                                                    false);
 431                 } else {
 432                         lli_dst =
 433                                 d40_log_buf_to_lli(lli_dst,
 434                                                    sg_phys(current_sg),
 435                                                    sg_dma_len(current_sg),
 436                                                    lcsp->lcsp3, dst_data_width,
 437                                                    src_data_width,
 438                                                    true);
 439                         lli_src =
 440                                 d40_log_buf_to_lli(lli_src,
 441                                                    dev_addr,
 442                                                    sg_dma_len(current_sg),
 443                                                    lcsp->lcsp1, src_data_width,
 444                                                    dst_data_width,
 445                                                    false);
 446                 }
 447         }
 448         return total_size;
 449 }
 450
 451 struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
 452                                        dma_addr_t addr,
 453                                        int size,
 454                                        u32 lcsp13, /* src or dst*/
 455                                        u32 data_width1,
 456                                        u32 data_width2,
 457                                        bool addr_inc)
 458 {
 459         struct d40_log_lli *lli = lli_sg;
 460         int size_rest = size;
 461         int size_seg = 0;
 462
 463         do {
 464                 size_seg = d40_seg_size(size_rest, data_width1, data_width2);
 465                 size_rest -= size_seg;
 466
 467                 d40_log_fill_lli(lli,
 468                                  addr,
 469                                  size_seg,
 470                                  lcsp13, data_width1,
 471                                  addr_inc);
 472                 if (addr_inc)
 473                         addr += size_seg;
 474                 lli++;
 475         } while (size_rest);
 476
 477         return lli;
 478 }
 479
 480 int d40_log_sg_to_lli(struct scatterlist *sg,
 481                       int sg_len,
 482                       struct d40_log_lli *lli_sg,
 483                       u32 lcsp13, /* src or dst*/
 484                       u32 data_width1, u32 data_width2)
 485 {
 486         int total_size = 0;
 487         struct scatterlist *current_sg = sg;
 488         int i;
 489         struct d40_log_lli *lli = lli_sg;
 490
 491         for_each_sg(sg, current_sg, sg_len, i) {
 492                 total_size += sg_dma_len(current_sg);
 493                 lli = d40_log_buf_to_lli(lli,
 494                                          sg_phys(current_sg),
 495                                          sg_dma_len(current_sg),
 496                                          lcsp13,
 497                                          data_width1, data_width2, true);
 498         }
 499         return total_size;
 500 }