drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include <asm/dmaengine.h>
  31
  32 #include "shdma.h"
  33
  34 /* DMA descriptor control */
  35 enum sh_dmae_desc_status {
  36         DESC_IDLE,
  37         DESC_PREPARED,
  38         DESC_SUBMITTED,
  39         DESC_COMPLETED, /* completed, have to call callback */
  40         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  41 };
  42
  43 #define NR_DESCS_PER_CHANNEL 32
  44 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  45 #define LOG2_DEFAULT_XFER_SIZE  2
  46
  47 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  48 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
  49
  50 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  51
  52 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  53 {
  54         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  55 }
  56
  57 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  58 {
  59         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  60 }
  61
  62 static u16 dmaor_read(struct sh_dmae_device *shdev)
  63 {
  64         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
  65 }
  66
  67 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  68 {
  69         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
  70 }
  71
  72 /*
  73  * Reset DMA controller
  74  *
  75  * SH7780 has two DMAOR register
  76  */
  77 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
  78 {
  79         unsigned short dmaor = dmaor_read(shdev);
  80
  81         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
  82 }
  83
  84 static int sh_dmae_rst(struct sh_dmae_device *shdev)
  85 {
  86         unsigned short dmaor;
  87
  88         sh_dmae_ctl_stop(shdev);
  89         dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
  90
  91         dmaor_write(shdev, dmaor);
  92         if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
  93                 pr_warning("dma-sh: Can't initialize DMAOR.\n");
  94                 return -EINVAL;
  95         }
  96         return 0;
  97 }
  98
  99 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 100 {
 101         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 102
 103         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 104                 return true; /* working */
 105
 106         return false; /* waiting */
 107 }
 108
 109 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 110 {
 111         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 112                                                 struct sh_dmae_device, common);
 113         struct sh_dmae_pdata *pdata = shdev->pdata;
 114         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 115                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 116
 117         if (cnt >= pdata->ts_shift_num)
 118                 cnt = 0;
 119
 120         return pdata->ts_shift[cnt];
 121 }
 122
 123 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 124 {
 125         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 126                                                 struct sh_dmae_device, common);
 127         struct sh_dmae_pdata *pdata = shdev->pdata;
 128         int i;
 129
 130         for (i = 0; i < pdata->ts_shift_num; i++)
 131                 if (pdata->ts_shift[i] == l2size)
 132                         break;
 133
 134         if (i == pdata->ts_shift_num)
 135                 i = 0;
 136
 137         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 138                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 139 }
 140
 141 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 142 {
 143         sh_dmae_writel(sh_chan, hw->sar, SAR);
 144         sh_dmae_writel(sh_chan, hw->dar, DAR);
 145         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 146 }
 147
 148 static void dmae_start(struct sh_dmae_chan *sh_chan)
 149 {
 150         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 151
 152         chcr |= CHCR_DE | CHCR_IE;
 153         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
 154 }
 155
 156 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 157 {
 158         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 159
 160         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 161         sh_dmae_writel(sh_chan, chcr, CHCR);
 162 }
 163
 164 static void dmae_init(struct sh_dmae_chan *sh_chan)
 165 {
 166         /*
 167          * Default configuration for dual address memory-memory transfer.
 168          * 0x400 represents auto-request.
 169          */
 170         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 171                                                    LOG2_DEFAULT_XFER_SIZE);
 172         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 173         sh_dmae_writel(sh_chan, chcr, CHCR);
 174 }
 175
 176 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 177 {
 178         /* When DMA was working, can not set data to CHCR */
 179         if (dmae_is_busy(sh_chan))
 180                 return -EBUSY;
 181
 182         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 183         sh_dmae_writel(sh_chan, val, CHCR);
 184
 185         return 0;
 186 }
 187
 188 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 189 {
 190         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 191                                                 struct sh_dmae_device, common);
 192         struct sh_dmae_pdata *pdata = shdev->pdata;
 193         struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 194         u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
 195         int shift = chan_pdata->dmars_bit;
 196
 197         if (dmae_is_busy(sh_chan))
 198                 return -EBUSY;
 199
 200         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 201                      addr);
 202
 203         return 0;
 204 }
 205
 206 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 207 {
 208         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 209         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 210         dma_async_tx_callback callback = tx->callback;
 211         dma_cookie_t cookie;
 212
 213         spin_lock_bh(&sh_chan->desc_lock);
 214
 215         cookie = sh_chan->common.cookie;
 216         cookie++;
 217         if (cookie < 0)
 218                 cookie = 1;
 219
 220         sh_chan->common.cookie = cookie;
 221         tx->cookie = cookie;
 222
 223         /* Mark all chunks of this descriptor as submitted, move to the queue */
 224         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 225                 /*
 226                  * All chunks are on the global ld_free, so, we have to find
 227                  * the end of the chain ourselves
 228                  */
 229                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 230                                       chunk->async_tx.cookie > 0 ||
 231                                       chunk->async_tx.cookie == -EBUSY ||
 232                                       &chunk->node == &sh_chan->ld_free))
 233                         break;
 234                 chunk->mark = DESC_SUBMITTED;
 235                 /* Callback goes to the last chunk */
 236                 chunk->async_tx.callback = NULL;
 237                 chunk->cookie = cookie;
 238                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 239                 last = chunk;
 240         }
 241
 242         last->async_tx.callback = callback;
 243         last->async_tx.callback_param = tx->callback_param;
 244
 245         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 246                 tx->cookie, &last->async_tx, sh_chan->id,
 247                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 248
 249         spin_unlock_bh(&sh_chan->desc_lock);
 250
 251         return cookie;
 252 }
 253
 254 /* Called with desc_lock held */
 255 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 256 {
 257         struct sh_desc *desc;
 258
 259         list_for_each_entry(desc, &sh_chan->ld_free, node)
 260                 if (desc->mark != DESC_PREPARED) {
 261                         BUG_ON(desc->mark != DESC_IDLE);
 262                         list_del(&desc->node);
 263                         return desc;
 264                 }
 265
 266         return NULL;
 267 }
 268
 269 static struct sh_dmae_slave_config *sh_dmae_find_slave(
 270         struct sh_dmae_chan *sh_chan, enum sh_dmae_slave_chan_id slave_id)
 271 {
 272         struct dma_device *dma_dev = sh_chan->common.device;
 273         struct sh_dmae_device *shdev = container_of(dma_dev,
 274                                         struct sh_dmae_device, common);
 275         struct sh_dmae_pdata *pdata = shdev->pdata;
 276         int i;
 277
 278         if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
 279                 return NULL;
 280
 281         for (i = 0; i < pdata->slave_num; i++)
 282                 if (pdata->slave[i].slave_id == slave_id)
 283                         return pdata->slave + i;
 284
 285         return NULL;
 286 }
 287
 288 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 289 {
 290         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 291         struct sh_desc *desc;
 292         struct sh_dmae_slave *param = chan->private;
 293
 294         pm_runtime_get_sync(sh_chan->dev);
 295
 296         /*
 297          * This relies on the guarantee from dmaengine that alloc_chan_resources
 298          * never runs concurrently with itself or free_chan_resources.
 299          */
 300         if (param) {
 301                 struct sh_dmae_slave_config *cfg;
 302
 303                 cfg = sh_dmae_find_slave(sh_chan, param->slave_id);
 304                 if (!cfg)
 305                         return -EINVAL;
 306
 307                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used))
 308                         return -EBUSY;
 309
 310                 param->config = cfg;
 311
 312                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 313                 dmae_set_chcr(sh_chan, cfg->chcr);
 314         } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
 315                 dmae_init(sh_chan);
 316         }
 317
 318         spin_lock_bh(&sh_chan->desc_lock);
 319         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 320                 spin_unlock_bh(&sh_chan->desc_lock);
 321                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 322                 if (!desc) {
 323                         spin_lock_bh(&sh_chan->desc_lock);
 324                         break;
 325                 }
 326                 dma_async_tx_descriptor_init(&desc->async_tx,
 327                                         &sh_chan->common);
 328                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 329                 desc->mark = DESC_IDLE;
 330
 331                 spin_lock_bh(&sh_chan->desc_lock);
 332                 list_add(&desc->node, &sh_chan->ld_free);
 333                 sh_chan->descs_allocated++;
 334         }
 335         spin_unlock_bh(&sh_chan->desc_lock);
 336
 337         if (!sh_chan->descs_allocated)
 338                 pm_runtime_put(sh_chan->dev);
 339
 340         return sh_chan->descs_allocated;
 341 }
 342
 343 /*
 344  * sh_dma_free_chan_resources - Free all resources of the channel.
 345  */
 346 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 347 {
 348         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 349         struct sh_desc *desc, *_desc;
 350         LIST_HEAD(list);
 351         int descs = sh_chan->descs_allocated;
 352
 353         dmae_halt(sh_chan);
 354
 355         /* Prepared and not submitted descriptors can still be on the queue */
 356         if (!list_empty(&sh_chan->ld_queue))
 357                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 358
 359         if (chan->private) {
 360                 /* The caller is holding dma_list_mutex */
 361                 struct sh_dmae_slave *param = chan->private;
 362                 clear_bit(param->slave_id, sh_dmae_slave_used);
 363         }
 364
 365         spin_lock_bh(&sh_chan->desc_lock);
 366
 367         list_splice_init(&sh_chan->ld_free, &list);
 368         sh_chan->descs_allocated = 0;
 369
 370         spin_unlock_bh(&sh_chan->desc_lock);
 371
 372         if (descs > 0)
 373                 pm_runtime_put(sh_chan->dev);
 374
 375         list_for_each_entry_safe(desc, _desc, &list, node)
 376                 kfree(desc);
 377 }
 378
 379 /**
 380  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 381  * @sh_chan:    DMA channel
 382  * @flags:      DMA transfer flags
 383  * @dest:       destination DMA address, incremented when direction equals
 384  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
 385  * @src:        source DMA address, incremented when direction equals
 386  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
 387  * @len:        DMA transfer length
 388  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 389  * @direction:  needed for slave DMA to decide which address to keep constant,
 390  *              equals DMA_BIDIRECTIONAL for MEMCPY
 391  * Returns 0 or an error
 392  * Locks: called with desc_lock held
 393  */
 394 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 395         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 396         struct sh_desc **first, enum dma_data_direction direction)
 397 {
 398         struct sh_desc *new;
 399         size_t copy_size;
 400
 401         if (!*len)
 402                 return NULL;
 403
 404         /* Allocate the link descriptor from the free list */
 405         new = sh_dmae_get_desc(sh_chan);
 406         if (!new) {
 407                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 408                 return NULL;
 409         }
 410
 411         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 412
 413         new->hw.sar = *src;
 414         new->hw.dar = *dest;
 415         new->hw.tcr = copy_size;
 416
 417         if (!*first) {
 418                 /* First desc */
 419                 new->async_tx.cookie = -EBUSY;
 420                 *first = new;
 421         } else {
 422                 /* Other desc - invisible to the user */
 423                 new->async_tx.cookie = -EINVAL;
 424         }
 425
 426         dev_dbg(sh_chan->dev,
 427                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 428                 copy_size, *len, *src, *dest, &new->async_tx,
 429                 new->async_tx.cookie, sh_chan->xmit_shift);
 430
 431         new->mark = DESC_PREPARED;
 432         new->async_tx.flags = flags;
 433         new->direction = direction;
 434
 435         *len -= copy_size;
 436         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
 437                 *src += copy_size;
 438         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
 439                 *dest += copy_size;
 440
 441         return new;
 442 }
 443
 444 /*
 445  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 446  *
 447  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 448  * converted to scatter-gather to guarantee consistent locking and a correct
 449  * list manipulation. For slave DMA direction carries the usual meaning, and,
 450  * logically, the SG list is RAM and the addr variable contains slave address,
 451  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
 452  * and the SG list contains only one element and points at the source buffer.
 453  */
 454 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 455         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 456         enum dma_data_direction direction, unsigned long flags)
 457 {
 458         struct scatterlist *sg;
 459         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 460         LIST_HEAD(tx_list);
 461         int chunks = 0;
 462         int i;
 463
 464         if (!sg_len)
 465                 return NULL;
 466
 467         for_each_sg(sgl, sg, sg_len, i)
 468                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 469                         (SH_DMA_TCR_MAX + 1);
 470
 471         /* Have to lock the whole loop to protect against concurrent release */
 472         spin_lock_bh(&sh_chan->desc_lock);
 473
 474         /*
 475          * Chaining:
 476          * first descriptor is what user is dealing with in all API calls, its
 477          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 478          *      number
 479          * if more than one chunk is needed further chunks have cookie = -EINVAL
 480          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 481          * all chunks are linked onto the tx_list head with their .node heads
 482          *      only during this function, then they are immediately spliced
 483          *      back onto the free list in form of a chain
 484          */
 485         for_each_sg(sgl, sg, sg_len, i) {
 486                 dma_addr_t sg_addr = sg_dma_address(sg);
 487                 size_t len = sg_dma_len(sg);
 488
 489                 if (!len)
 490                         goto err_get_desc;
 491
 492                 do {
 493                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 494                                 i, sg, len, (unsigned long long)sg_addr);
 495
 496                         if (direction == DMA_FROM_DEVICE)
 497                                 new = sh_dmae_add_desc(sh_chan, flags,
 498                                                 &sg_addr, addr, &len, &first,
 499                                                 direction);
 500                         else
 501                                 new = sh_dmae_add_desc(sh_chan, flags,
 502                                                 addr, &sg_addr, &len, &first,
 503                                                 direction);
 504                         if (!new)
 505                                 goto err_get_desc;
 506
 507                         new->chunks = chunks--;
 508                         list_add_tail(&new->node, &tx_list);
 509                 } while (len);
 510         }
 511
 512         if (new != first)
 513                 new->async_tx.cookie = -ENOSPC;
 514
 515         /* Put them back on the free list, so, they don't get lost */
 516         list_splice_tail(&tx_list, &sh_chan->ld_free);
 517
 518         spin_unlock_bh(&sh_chan->desc_lock);
 519
 520         return &first->async_tx;
 521
 522 err_get_desc:
 523         list_for_each_entry(new, &tx_list, node)
 524                 new->mark = DESC_IDLE;
 525         list_splice(&tx_list, &sh_chan->ld_free);
 526
 527         spin_unlock_bh(&sh_chan->desc_lock);
 528
 529         return NULL;
 530 }
 531
 532 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 533         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 534         size_t len, unsigned long flags)
 535 {
 536         struct sh_dmae_chan *sh_chan;
 537         struct scatterlist sg;
 538
 539         if (!chan || !len)
 540                 return NULL;
 541
 542         chan->private = NULL;
 543
 544         sh_chan = to_sh_chan(chan);
 545
 546         sg_init_table(&sg, 1);
 547         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 548                     offset_in_page(dma_src));
 549         sg_dma_address(&sg) = dma_src;
 550         sg_dma_len(&sg) = len;
 551
 552         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
 553                                flags);
 554 }
 555
 556 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 557         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 558         enum dma_data_direction direction, unsigned long flags)
 559 {
 560         struct sh_dmae_slave *param;
 561         struct sh_dmae_chan *sh_chan;
 562
 563         if (!chan)
 564                 return NULL;
 565
 566         sh_chan = to_sh_chan(chan);
 567         param = chan->private;
 568
 569         /* Someone calling slave DMA on a public channel? */
 570         if (!param || !sg_len) {
 571                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 572                          __func__, param, sg_len, param ? param->slave_id : -1);
 573                 return NULL;
 574         }
 575
 576         /*
 577          * if (param != NULL), this is a successfully requested slave channel,
 578          * therefore param->config != NULL too.
 579          */
 580         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &param->config->addr,
 581                                direction, flags);
 582 }
 583
 584 static void sh_dmae_terminate_all(struct dma_chan *chan)
 585 {
 586         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 587
 588         if (!chan)
 589                 return;
 590
 591         dmae_halt(sh_chan);
 592
 593         spin_lock_bh(&sh_chan->desc_lock);
 594         if (!list_empty(&sh_chan->ld_queue)) {
 595                 /* Record partial transfer */
 596                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
 597                                                   struct sh_desc, node);
 598                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
 599                         sh_chan->xmit_shift;
 600
 601         }
 602         spin_unlock_bh(&sh_chan->desc_lock);
 603
 604         sh_dmae_chan_ld_cleanup(sh_chan, true);
 605 }
 606
 607 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 608 {
 609         struct sh_desc *desc, *_desc;
 610         /* Is the "exposed" head of a chain acked? */
 611         bool head_acked = false;
 612         dma_cookie_t cookie = 0;
 613         dma_async_tx_callback callback = NULL;
 614         void *param = NULL;
 615
 616         spin_lock_bh(&sh_chan->desc_lock);
 617         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 618                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 619
 620                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 621                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 622                        desc->mark != DESC_COMPLETED &&
 623                        desc->mark != DESC_WAITING);
 624
 625                 /*
 626                  * queue is ordered, and we use this loop to (1) clean up all
 627                  * completed descriptors, and to (2) update descriptor flags of
 628                  * any chunks in a (partially) completed chain
 629                  */
 630                 if (!all && desc->mark == DESC_SUBMITTED &&
 631                     desc->cookie != cookie)
 632                         break;
 633
 634                 if (tx->cookie > 0)
 635                         cookie = tx->cookie;
 636
 637                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 638                         if (sh_chan->completed_cookie != desc->cookie - 1)
 639                                 dev_dbg(sh_chan->dev,
 640                                         "Completing cookie %d, expected %d\n",
 641                                         desc->cookie,
 642                                         sh_chan->completed_cookie + 1);
 643                         sh_chan->completed_cookie = desc->cookie;
 644                 }
 645
 646                 /* Call callback on the last chunk */
 647                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 648                         desc->mark = DESC_WAITING;
 649                         callback = tx->callback;
 650                         param = tx->callback_param;
 651                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 652                                 tx->cookie, tx, sh_chan->id);
 653                         BUG_ON(desc->chunks != 1);
 654                         break;
 655                 }
 656
 657                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 658                         if (desc->mark == DESC_COMPLETED) {
 659                                 BUG_ON(tx->cookie < 0);
 660                                 desc->mark = DESC_WAITING;
 661                         }
 662                         head_acked = async_tx_test_ack(tx);
 663                 } else {
 664                         switch (desc->mark) {
 665                         case DESC_COMPLETED:
 666                                 desc->mark = DESC_WAITING;
 667                                 /* Fall through */
 668                         case DESC_WAITING:
 669                                 if (head_acked)
 670                                         async_tx_ack(&desc->async_tx);
 671                         }
 672                 }
 673
 674                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 675                         tx, tx->cookie);
 676
 677                 if (((desc->mark == DESC_COMPLETED ||
 678                       desc->mark == DESC_WAITING) &&
 679                      async_tx_test_ack(&desc->async_tx)) || all) {
 680                         /* Remove from ld_queue list */
 681                         desc->mark = DESC_IDLE;
 682                         list_move(&desc->node, &sh_chan->ld_free);
 683                 }
 684         }
 685         spin_unlock_bh(&sh_chan->desc_lock);
 686
 687         if (callback)
 688                 callback(param);
 689
 690         return callback;
 691 }
 692
 693 /*
 694  * sh_chan_ld_cleanup - Clean up link descriptors
 695  *
 696  * This function cleans up the ld_queue of DMA channel.
 697  */
 698 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 699 {
 700         while (__ld_cleanup(sh_chan, all))
 701                 ;
 702 }
 703
 704 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 705 {
 706         struct sh_desc *desc;
 707
 708         spin_lock_bh(&sh_chan->desc_lock);
 709         /* DMA work check */
 710         if (dmae_is_busy(sh_chan)) {
 711                 spin_unlock_bh(&sh_chan->desc_lock);
 712                 return;
 713         }
 714
 715         /* Find the first not transferred desciptor */
 716         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 717                 if (desc->mark == DESC_SUBMITTED) {
 718                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
 719                                 desc->async_tx.cookie, sh_chan->id,
 720                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
 721                         /* Get the ld start address from ld_queue */
 722                         dmae_set_reg(sh_chan, &desc->hw);
 723                         dmae_start(sh_chan);
 724                         break;
 725                 }
 726
 727         spin_unlock_bh(&sh_chan->desc_lock);
 728 }
 729
 730 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 731 {
 732         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 733         sh_chan_xfer_ld_queue(sh_chan);
 734 }
 735
 736 static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
 737                                         dma_cookie_t cookie,
 738                                         dma_cookie_t *done,
 739                                         dma_cookie_t *used)
 740 {
 741         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 742         dma_cookie_t last_used;
 743         dma_cookie_t last_complete;
 744         enum dma_status status;
 745
 746         sh_dmae_chan_ld_cleanup(sh_chan, false);
 747
 748         last_used = chan->cookie;
 749         last_complete = sh_chan->completed_cookie;
 750         BUG_ON(last_complete < 0);
 751
 752         if (done)
 753                 *done = last_complete;
 754
 755         if (used)
 756                 *used = last_used;
 757
 758         spin_lock_bh(&sh_chan->desc_lock);
 759
 760         status = dma_async_is_complete(cookie, last_complete, last_used);
 761
 762         /*
 763          * If we don't find cookie on the queue, it has been aborted and we have
 764          * to report error
 765          */
 766         if (status != DMA_SUCCESS) {
 767                 struct sh_desc *desc;
 768                 status = DMA_ERROR;
 769                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 770                         if (desc->cookie == cookie) {
 771                                 status = DMA_IN_PROGRESS;
 772                                 break;
 773                         }
 774         }
 775
 776         spin_unlock_bh(&sh_chan->desc_lock);
 777
 778         return status;
 779 }
 780
 781 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 782 {
 783         irqreturn_t ret = IRQ_NONE;
 784         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 785         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 786
 787         if (chcr & CHCR_TE) {
 788                 /* DMA stop */
 789                 dmae_halt(sh_chan);
 790
 791                 ret = IRQ_HANDLED;
 792                 tasklet_schedule(&sh_chan->tasklet);
 793         }
 794
 795         return ret;
 796 }
 797
 798 #if defined(CONFIG_CPU_SH4)
 799 static irqreturn_t sh_dmae_err(int irq, void *data)
 800 {
 801         struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
 802         int i;
 803
 804         /* halt the dma controller */
 805         sh_dmae_ctl_stop(shdev);
 806
 807         /* We cannot detect, which channel caused the error, have to reset all */
 808         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 809                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 810                 if (sh_chan) {
 811                         struct sh_desc *desc;
 812                         /* Stop the channel */
 813                         dmae_halt(sh_chan);
 814                         /* Complete all  */
 815                         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 816                                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 817                                 desc->mark = DESC_IDLE;
 818                                 if (tx->callback)
 819                                         tx->callback(tx->callback_param);
 820                         }
 821                         list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
 822                 }
 823         }
 824         sh_dmae_rst(shdev);
 825
 826         return IRQ_HANDLED;
 827 }
 828 #endif
 829
 830 static void dmae_do_tasklet(unsigned long data)
 831 {
 832         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 833         struct sh_desc *desc;
 834         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 835         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 836
 837         spin_lock(&sh_chan->desc_lock);
 838         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 839                 if (desc->mark == DESC_SUBMITTED &&
 840                     ((desc->direction == DMA_FROM_DEVICE &&
 841                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
 842                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
 843                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
 844                                 desc->async_tx.cookie, &desc->async_tx,
 845                                 desc->hw.dar);
 846                         desc->mark = DESC_COMPLETED;
 847                         break;
 848                 }
 849         }
 850         spin_unlock(&sh_chan->desc_lock);
 851
 852         /* Next desc */
 853         sh_chan_xfer_ld_queue(sh_chan);
 854         sh_dmae_chan_ld_cleanup(sh_chan, false);
 855 }
 856
 857 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 858                                         int irq, unsigned long flags)
 859 {
 860         int err;
 861         struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 862         struct platform_device *pdev = to_platform_device(shdev->common.dev);
 863         struct sh_dmae_chan *new_sh_chan;
 864
 865         /* alloc channel */
 866         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
 867         if (!new_sh_chan) {
 868                 dev_err(shdev->common.dev,
 869                         "No free memory for allocating dma channels!\n");
 870                 return -ENOMEM;
 871         }
 872
 873         /* copy struct dma_device */
 874         new_sh_chan->common.device = &shdev->common;
 875
 876         new_sh_chan->dev = shdev->common.dev;
 877         new_sh_chan->id = id;
 878         new_sh_chan->irq = irq;
 879         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
 880
 881         /* Init DMA tasklet */
 882         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
 883                         (unsigned long)new_sh_chan);
 884
 885         /* Init the channel */
 886         dmae_init(new_sh_chan);
 887
 888         spin_lock_init(&new_sh_chan->desc_lock);
 889
 890         /* Init descripter manage list */
 891         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
 892         INIT_LIST_HEAD(&new_sh_chan->ld_free);
 893
 894         /* Add the channel to DMA device channel list */
 895         list_add_tail(&new_sh_chan->common.device_node,
 896                         &shdev->common.channels);
 897         shdev->common.chancnt++;
 898
 899         if (pdev->id >= 0)
 900                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 901                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
 902         else
 903                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
 904                          "sh-dma%d", new_sh_chan->id);
 905
 906         /* set up channel irq */
 907         err = request_irq(irq, &sh_dmae_interrupt, flags,
 908                           new_sh_chan->dev_id, new_sh_chan);
 909         if (err) {
 910                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
 911                         "with return %d\n", id, err);
 912                 goto err_no_irq;
 913         }
 914
 915         shdev->chan[id] = new_sh_chan;
 916         return 0;
 917
 918 err_no_irq:
 919         /* remove from dmaengine device node */
 920         list_del(&new_sh_chan->common.device_node);
 921         kfree(new_sh_chan);
 922         return err;
 923 }
 924
 925 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 926 {
 927         int i;
 928
 929         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
 930                 if (shdev->chan[i]) {
 931                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 932
 933                         free_irq(sh_chan->irq, sh_chan);
 934
 935                         list_del(&sh_chan->common.device_node);
 936                         kfree(sh_chan);
 937                         shdev->chan[i] = NULL;
 938                 }
 939         }
 940         shdev->common.chancnt = 0;
 941 }
 942
 943 static int __init sh_dmae_probe(struct platform_device *pdev)
 944 {
 945         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
 946         unsigned long irqflags = IRQF_DISABLED,
 947                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
 948         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
 949         int err, i, irq_cnt = 0, irqres = 0;
 950         struct sh_dmae_device *shdev;
 951         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 952
 953         /* get platform data */
 954         if (!pdata || !pdata->channel_num)
 955                 return -ENODEV;
 956
 957         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 958         /* DMARS area is optional, if absent, this controller cannot do slave DMA */
 959         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 960         /*
 961          * IRQ resources:
 962          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 963          *    the error IRQ, in which case it is the only IRQ in this resource:
 964          *    start == end. If it is the only IRQ resource, all channels also
 965          *    use the same IRQ.
 966          * 2. DMA channel IRQ resources can be specified one per resource or in
 967          *    ranges (start != end)
 968          * 3. iff all events (channels and, optionally, error) on this
 969          *    controller use the same IRQ, only one IRQ resource can be
 970          *    specified, otherwise there must be one IRQ per channel, even if
 971          *    some of them are equal
 972          * 4. if all IRQs on this controller are equal or if some specific IRQs
 973          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 974          *    requested with the IRQF_SHARED flag
 975          */
 976         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 977         if (!chan || !errirq_res)
 978                 return -ENODEV;
 979
 980         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
 981                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
 982                 return -EBUSY;
 983         }
 984
 985         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
 986                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
 987                 err = -EBUSY;
 988                 goto ermrdmars;
 989         }
 990
 991         err = -ENOMEM;
 992         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
 993         if (!shdev) {
 994                 dev_err(&pdev->dev, "Not enough memory\n");
 995                 goto ealloc;
 996         }
 997
 998         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
 999         if (!shdev->chan_reg)
1000                 goto emapchan;
1001         if (dmars) {
1002                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1003                 if (!shdev->dmars)
1004                         goto emapdmars;
1005         }
1006
1007         /* platform data */
1008         shdev->pdata = pdata;
1009
1010         pm_runtime_enable(&pdev->dev);
1011         pm_runtime_get_sync(&pdev->dev);
1012
1013         /* reset dma controller */
1014         err = sh_dmae_rst(shdev);
1015         if (err)
1016                 goto rst_err;
1017
1018         INIT_LIST_HEAD(&shdev->common.channels);
1019
1020         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1021         if (dmars)
1022                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1023
1024         shdev->common.device_alloc_chan_resources
1025                 = sh_dmae_alloc_chan_resources;
1026         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1027         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1028         shdev->common.device_is_tx_complete = sh_dmae_is_complete;
1029         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1030
1031         /* Compulsory for DMA_SLAVE fields */
1032         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1033         shdev->common.device_terminate_all = sh_dmae_terminate_all;
1034
1035         shdev->common.dev = &pdev->dev;
1036         /* Default transfer size of 32 bytes requires 32-byte alignment */
1037         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1038
1039 #if defined(CONFIG_CPU_SH4)
1040         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1041
1042         if (!chanirq_res)
1043                 chanirq_res = errirq_res;
1044         else
1045                 irqres++;
1046
1047         if (chanirq_res == errirq_res ||
1048             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1049                 irqflags = IRQF_SHARED;
1050
1051         errirq = errirq_res->start;
1052
1053         err = request_irq(errirq, sh_dmae_err, irqflags,
1054                           "DMAC Address Error", shdev);
1055         if (err) {
1056                 dev_err(&pdev->dev,
1057                         "DMA failed requesting irq #%d, error %d\n",
1058                         errirq, err);
1059                 goto eirq_err;
1060         }
1061
1062 #else
1063         chanirq_res = errirq_res;
1064 #endif /* CONFIG_CPU_SH4 */
1065
1066         if (chanirq_res->start == chanirq_res->end &&
1067             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1068                 /* Special case - all multiplexed */
1069                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1070                         chan_irq[irq_cnt] = chanirq_res->start;
1071                         chan_flag[irq_cnt] = IRQF_SHARED;
1072                 }
1073         } else {
1074                 do {
1075                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1076                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1077                                     IORESOURCE_IRQ_SHAREABLE)
1078                                         chan_flag[irq_cnt] = IRQF_SHARED;
1079                                 else
1080                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1081                                 dev_dbg(&pdev->dev,
1082                                         "Found IRQ %d for channel %d\n",
1083                                         i, irq_cnt);
1084                                 chan_irq[irq_cnt++] = i;
1085                         }
1086                         chanirq_res = platform_get_resource(pdev,
1087                                                 IORESOURCE_IRQ, ++irqres);
1088                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1089         }
1090
1091         if (irq_cnt < pdata->channel_num)
1092                 goto eirqres;
1093
1094         /* Create DMA Channel */
1095         for (i = 0; i < pdata->channel_num; i++) {
1096                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1097                 if (err)
1098                         goto chan_probe_err;
1099         }
1100
1101         pm_runtime_put(&pdev->dev);
1102
1103         platform_set_drvdata(pdev, shdev);
1104         dma_async_device_register(&shdev->common);
1105
1106         return err;
1107
1108 chan_probe_err:
1109         sh_dmae_chan_remove(shdev);
1110 eirqres:
1111 #if defined(CONFIG_CPU_SH4)
1112         free_irq(errirq, shdev);
1113 eirq_err:
1114 #endif
1115 rst_err:
1116         pm_runtime_put(&pdev->dev);
1117         if (dmars)
1118                 iounmap(shdev->dmars);
1119 emapdmars:
1120         iounmap(shdev->chan_reg);
1121 emapchan:
1122         kfree(shdev);
1123 ealloc:
1124         if (dmars)
1125                 release_mem_region(dmars->start, resource_size(dmars));
1126 ermrdmars:
1127         release_mem_region(chan->start, resource_size(chan));
1128
1129         return err;
1130 }
1131
1132 static int __exit sh_dmae_remove(struct platform_device *pdev)
1133 {
1134         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1135         struct resource *res;
1136         int errirq = platform_get_irq(pdev, 0);
1137
1138         dma_async_device_unregister(&shdev->common);
1139
1140         if (errirq > 0)
1141                 free_irq(errirq, shdev);
1142
1143         /* channel data remove */
1144         sh_dmae_chan_remove(shdev);
1145
1146         pm_runtime_disable(&pdev->dev);
1147
1148         if (shdev->dmars)
1149                 iounmap(shdev->dmars);
1150         iounmap(shdev->chan_reg);
1151
1152         kfree(shdev);
1153
1154         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1155         if (res)
1156                 release_mem_region(res->start, resource_size(res));
1157         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1158         if (res)
1159                 release_mem_region(res->start, resource_size(res));
1160
1161         return 0;
1162 }
1163
1164 static void sh_dmae_shutdown(struct platform_device *pdev)
1165 {
1166         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1167         sh_dmae_ctl_stop(shdev);
1168 }
1169
1170 static struct platform_driver sh_dmae_driver = {
1171         .remove         = __exit_p(sh_dmae_remove),
1172         .shutdown       = sh_dmae_shutdown,
1173         .driver = {
1174                 .name   = "sh-dma-engine",
1175         },
1176 };
1177
1178 static int __init sh_dmae_init(void)
1179 {
1180         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1181 }
1182 module_init(sh_dmae_init);
1183
1184 static void __exit sh_dmae_exit(void)
1185 {
1186         platform_driver_unregister(&sh_dmae_driver);
1187 }
1188 module_exit(sh_dmae_exit);
1189
1190 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1191 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1192 MODULE_LICENSE("GPL");