drivers/dma/shdma.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   7  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   8  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   9  *
  10  * This is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * - DMA of SuperH does not have Hardware DMA chain mode.
  16  * - MAX DMA size is 16MB.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/notifier.h>
  31 #include <linux/kdebug.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/rculist.h>
  34 #include "shdma.h"
  35
  36 /* DMA descriptor control */
  37 enum sh_dmae_desc_status {
  38         DESC_IDLE,
  39         DESC_PREPARED,
  40         DESC_SUBMITTED,
  41         DESC_COMPLETED, /* completed, have to call callback */
  42         DESC_WAITING,   /* callback called, waiting for ack / re-submit */
  43 };
  44
  45 #define NR_DESCS_PER_CHANNEL 32
  46 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  47 #define LOG2_DEFAULT_XFER_SIZE  2
  48
  49 /*
  50  * Used for write-side mutual exclusion for the global device list,
  51  * read-side synchronization by way of RCU, and per-controller data.
  52  */
  53 static DEFINE_SPINLOCK(sh_dmae_lock);
  54 static LIST_HEAD(sh_dmae_devices);
  55
  56 /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
  57 static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)];
  58
  59 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
  60
  61 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  62 {
  63         __raw_writel(data, sh_dc->base + reg / sizeof(u32));
  64 }
  65
  66 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  67 {
  68         return __raw_readl(sh_dc->base + reg / sizeof(u32));
  69 }
  70
  71 static u16 dmaor_read(struct sh_dmae_device *shdev)
  72 {
  73         return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
  74 }
  75
  76 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
  77 {
  78         __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
  79 }
  80
  81 /*
  82  * Reset DMA controller
  83  *
  84  * SH7780 has two DMAOR register
  85  */
  86 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
  87 {
  88         unsigned short dmaor;
  89         unsigned long flags;
  90
  91         spin_lock_irqsave(&sh_dmae_lock, flags);
  92
  93         dmaor = dmaor_read(shdev);
  94         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
  95
  96         spin_unlock_irqrestore(&sh_dmae_lock, flags);
  97 }
  98
  99 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 100 {
 101         unsigned short dmaor;
 102         unsigned long flags;
 103
 104         spin_lock_irqsave(&sh_dmae_lock, flags);
 105
 106         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 107
 108         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 109
 110         dmaor = dmaor_read(shdev);
 111
 112         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 113
 114         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 115                 dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
 116                 return -EIO;
 117         }
 118         return 0;
 119 }
 120
 121 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 122 {
 123         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 124
 125         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 126                 return true; /* working */
 127
 128         return false; /* waiting */
 129 }
 130
 131 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 132 {
 133         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 134                                                 struct sh_dmae_device, common);
 135         struct sh_dmae_pdata *pdata = shdev->pdata;
 136         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 137                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 138
 139         if (cnt >= pdata->ts_shift_num)
 140                 cnt = 0;
 141
 142         return pdata->ts_shift[cnt];
 143 }
 144
 145 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 146 {
 147         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 148                                                 struct sh_dmae_device, common);
 149         struct sh_dmae_pdata *pdata = shdev->pdata;
 150         int i;
 151
 152         for (i = 0; i < pdata->ts_shift_num; i++)
 153                 if (pdata->ts_shift[i] == l2size)
 154                         break;
 155
 156         if (i == pdata->ts_shift_num)
 157                 i = 0;
 158
 159         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 160                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 161 }
 162
 163 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 164 {
 165         sh_dmae_writel(sh_chan, hw->sar, SAR);
 166         sh_dmae_writel(sh_chan, hw->dar, DAR);
 167         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 168 }
 169
 170 static void dmae_start(struct sh_dmae_chan *sh_chan)
 171 {
 172         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 173
 174         chcr |= CHCR_DE | CHCR_IE;
 175         sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
 176 }
 177
 178 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 179 {
 180         u32 chcr = sh_dmae_readl(sh_chan, CHCR);
 181
 182         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 183         sh_dmae_writel(sh_chan, chcr, CHCR);
 184 }
 185
 186 static void dmae_init(struct sh_dmae_chan *sh_chan)
 187 {
 188         /*
 189          * Default configuration for dual address memory-memory transfer.
 190          * 0x400 represents auto-request.
 191          */
 192         u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
 193                                                    LOG2_DEFAULT_XFER_SIZE);
 194         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 195         sh_dmae_writel(sh_chan, chcr, CHCR);
 196 }
 197
 198 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 199 {
 200         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 201         if (dmae_is_busy(sh_chan))
 202                 return -EBUSY;
 203
 204         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 205         sh_dmae_writel(sh_chan, val, CHCR);
 206
 207         return 0;
 208 }
 209
 210 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 211 {
 212         struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
 213                                                 struct sh_dmae_device, common);
 214         struct sh_dmae_pdata *pdata = shdev->pdata;
 215         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
 216         u16 __iomem *addr = shdev->dmars;
 217         int shift = chan_pdata->dmars_bit;
 218
 219         if (dmae_is_busy(sh_chan))
 220                 return -EBUSY;
 221
 222         /* in the case of a missing DMARS resource use first memory window */
 223         if (!addr)
 224                 addr = (u16 __iomem *)shdev->chan_reg;
 225         addr += chan_pdata->dmars / sizeof(u16);
 226
 227         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 228                      addr);
 229
 230         return 0;
 231 }
 232
 233 static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 234 {
 235         struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
 236         struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
 237         dma_async_tx_callback callback = tx->callback;
 238         dma_cookie_t cookie;
 239
 240         spin_lock_bh(&sh_chan->desc_lock);
 241
 242         cookie = sh_chan->common.cookie;
 243         cookie++;
 244         if (cookie < 0)
 245                 cookie = 1;
 246
 247         sh_chan->common.cookie = cookie;
 248         tx->cookie = cookie;
 249
 250         /* Mark all chunks of this descriptor as submitted, move to the queue */
 251         list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
 252                 /*
 253                  * All chunks are on the global ld_free, so, we have to find
 254                  * the end of the chain ourselves
 255                  */
 256                 if (chunk != desc && (chunk->mark == DESC_IDLE ||
 257                                       chunk->async_tx.cookie > 0 ||
 258                                       chunk->async_tx.cookie == -EBUSY ||
 259                                       &chunk->node == &sh_chan->ld_free))
 260                         break;
 261                 chunk->mark = DESC_SUBMITTED;
 262                 /* Callback goes to the last chunk */
 263                 chunk->async_tx.callback = NULL;
 264                 chunk->cookie = cookie;
 265                 list_move_tail(&chunk->node, &sh_chan->ld_queue);
 266                 last = chunk;
 267         }
 268
 269         last->async_tx.callback = callback;
 270         last->async_tx.callback_param = tx->callback_param;
 271
 272         dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
 273                 tx->cookie, &last->async_tx, sh_chan->id,
 274                 desc->hw.sar, desc->hw.tcr, desc->hw.dar);
 275
 276         spin_unlock_bh(&sh_chan->desc_lock);
 277
 278         return cookie;
 279 }
 280
 281 /* Called with desc_lock held */
 282 static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
 283 {
 284         struct sh_desc *desc;
 285
 286         list_for_each_entry(desc, &sh_chan->ld_free, node)
 287                 if (desc->mark != DESC_PREPARED) {
 288                         BUG_ON(desc->mark != DESC_IDLE);
 289                         list_del(&desc->node);
 290                         return desc;
 291                 }
 292
 293         return NULL;
 294 }
 295
 296 static const struct sh_dmae_slave_config *sh_dmae_find_slave(
 297         struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param)
 298 {
 299         struct dma_device *dma_dev = sh_chan->common.device;
 300         struct sh_dmae_device *shdev = container_of(dma_dev,
 301                                         struct sh_dmae_device, common);
 302         struct sh_dmae_pdata *pdata = shdev->pdata;
 303         int i;
 304
 305         if (param->slave_id >= SH_DMA_SLAVE_NUMBER)
 306                 return NULL;
 307
 308         for (i = 0; i < pdata->slave_num; i++)
 309                 if (pdata->slave[i].slave_id == param->slave_id)
 310                         return pdata->slave + i;
 311
 312         return NULL;
 313 }
 314
 315 static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
 316 {
 317         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 318         struct sh_desc *desc;
 319         struct sh_dmae_slave *param = chan->private;
 320         int ret;
 321
 322         pm_runtime_get_sync(sh_chan->dev);
 323
 324         /*
 325          * This relies on the guarantee from dmaengine that alloc_chan_resources
 326          * never runs concurrently with itself or free_chan_resources.
 327          */
 328         if (param) {
 329                 const struct sh_dmae_slave_config *cfg;
 330
 331                 cfg = sh_dmae_find_slave(sh_chan, param);
 332                 if (!cfg) {
 333                         ret = -EINVAL;
 334                         goto efindslave;
 335                 }
 336
 337                 if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) {
 338                         ret = -EBUSY;
 339                         goto etestused;
 340                 }
 341
 342                 param->config = cfg;
 343
 344                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 345                 dmae_set_chcr(sh_chan, cfg->chcr);
 346         } else {
 347                 dmae_init(sh_chan);
 348         }
 349
 350         spin_lock_bh(&sh_chan->desc_lock);
 351         while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
 352                 spin_unlock_bh(&sh_chan->desc_lock);
 353                 desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
 354                 if (!desc) {
 355                         spin_lock_bh(&sh_chan->desc_lock);
 356                         break;
 357                 }
 358                 dma_async_tx_descriptor_init(&desc->async_tx,
 359                                         &sh_chan->common);
 360                 desc->async_tx.tx_submit = sh_dmae_tx_submit;
 361                 desc->mark = DESC_IDLE;
 362
 363                 spin_lock_bh(&sh_chan->desc_lock);
 364                 list_add(&desc->node, &sh_chan->ld_free);
 365                 sh_chan->descs_allocated++;
 366         }
 367         spin_unlock_bh(&sh_chan->desc_lock);
 368
 369         if (!sh_chan->descs_allocated) {
 370                 ret = -ENOMEM;
 371                 goto edescalloc;
 372         }
 373
 374         return sh_chan->descs_allocated;
 375
 376 edescalloc:
 377         if (param)
 378                 clear_bit(param->slave_id, sh_dmae_slave_used);
 379 etestused:
 380 efindslave:
 381         pm_runtime_put(sh_chan->dev);
 382         return ret;
 383 }
 384
 385 /*
 386  * sh_dma_free_chan_resources - Free all resources of the channel.
 387  */
 388 static void sh_dmae_free_chan_resources(struct dma_chan *chan)
 389 {
 390         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 391         struct sh_desc *desc, *_desc;
 392         LIST_HEAD(list);
 393         int descs = sh_chan->descs_allocated;
 394
 395         /* Protect against ISR */
 396         spin_lock_irq(&sh_chan->desc_lock);
 397         dmae_halt(sh_chan);
 398         spin_unlock_irq(&sh_chan->desc_lock);
 399
 400         /* Now no new interrupts will occur */
 401
 402         /* Prepared and not submitted descriptors can still be on the queue */
 403         if (!list_empty(&sh_chan->ld_queue))
 404                 sh_dmae_chan_ld_cleanup(sh_chan, true);
 405
 406         if (chan->private) {
 407                 /* The caller is holding dma_list_mutex */
 408                 struct sh_dmae_slave *param = chan->private;
 409                 clear_bit(param->slave_id, sh_dmae_slave_used);
 410                 chan->private = NULL;
 411         }
 412
 413         spin_lock_bh(&sh_chan->desc_lock);
 414
 415         list_splice_init(&sh_chan->ld_free, &list);
 416         sh_chan->descs_allocated = 0;
 417
 418         spin_unlock_bh(&sh_chan->desc_lock);
 419
 420         if (descs > 0)
 421                 pm_runtime_put(sh_chan->dev);
 422
 423         list_for_each_entry_safe(desc, _desc, &list, node)
 424                 kfree(desc);
 425 }
 426
 427 /**
 428  * sh_dmae_add_desc - get, set up and return one transfer descriptor
 429  * @sh_chan:    DMA channel
 430  * @flags:      DMA transfer flags
 431  * @dest:       destination DMA address, incremented when direction equals
 432  *              DMA_FROM_DEVICE or DMA_BIDIRECTIONAL
 433  * @src:        source DMA address, incremented when direction equals
 434  *              DMA_TO_DEVICE or DMA_BIDIRECTIONAL
 435  * @len:        DMA transfer length
 436  * @first:      if NULL, set to the current descriptor and cookie set to -EBUSY
 437  * @direction:  needed for slave DMA to decide which address to keep constant,
 438  *              equals DMA_BIDIRECTIONAL for MEMCPY
 439  * Returns 0 or an error
 440  * Locks: called with desc_lock held
 441  */
 442 static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
 443         unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
 444         struct sh_desc **first, enum dma_data_direction direction)
 445 {
 446         struct sh_desc *new;
 447         size_t copy_size;
 448
 449         if (!*len)
 450                 return NULL;
 451
 452         /* Allocate the link descriptor from the free list */
 453         new = sh_dmae_get_desc(sh_chan);
 454         if (!new) {
 455                 dev_err(sh_chan->dev, "No free link descriptor available\n");
 456                 return NULL;
 457         }
 458
 459         copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1);
 460
 461         new->hw.sar = *src;
 462         new->hw.dar = *dest;
 463         new->hw.tcr = copy_size;
 464
 465         if (!*first) {
 466                 /* First desc */
 467                 new->async_tx.cookie = -EBUSY;
 468                 *first = new;
 469         } else {
 470                 /* Other desc - invisible to the user */
 471                 new->async_tx.cookie = -EINVAL;
 472         }
 473
 474         dev_dbg(sh_chan->dev,
 475                 "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n",
 476                 copy_size, *len, *src, *dest, &new->async_tx,
 477                 new->async_tx.cookie, sh_chan->xmit_shift);
 478
 479         new->mark = DESC_PREPARED;
 480         new->async_tx.flags = flags;
 481         new->direction = direction;
 482
 483         *len -= copy_size;
 484         if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE)
 485                 *src += copy_size;
 486         if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE)
 487                 *dest += copy_size;
 488
 489         return new;
 490 }
 491
 492 /*
 493  * sh_dmae_prep_sg - prepare transfer descriptors from an SG list
 494  *
 495  * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
 496  * converted to scatter-gather to guarantee consistent locking and a correct
 497  * list manipulation. For slave DMA direction carries the usual meaning, and,
 498  * logically, the SG list is RAM and the addr variable contains slave address,
 499  * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL
 500  * and the SG list contains only one element and points at the source buffer.
 501  */
 502 static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
 503         struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
 504         enum dma_data_direction direction, unsigned long flags)
 505 {
 506         struct scatterlist *sg;
 507         struct sh_desc *first = NULL, *new = NULL /* compiler... */;
 508         LIST_HEAD(tx_list);
 509         int chunks = 0;
 510         int i;
 511
 512         if (!sg_len)
 513                 return NULL;
 514
 515         for_each_sg(sgl, sg, sg_len, i)
 516                 chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) /
 517                         (SH_DMA_TCR_MAX + 1);
 518
 519         /* Have to lock the whole loop to protect against concurrent release */
 520         spin_lock_bh(&sh_chan->desc_lock);
 521
 522         /*
 523          * Chaining:
 524          * first descriptor is what user is dealing with in all API calls, its
 525          *      cookie is at first set to -EBUSY, at tx-submit to a positive
 526          *      number
 527          * if more than one chunk is needed further chunks have cookie = -EINVAL
 528          * the last chunk, if not equal to the first, has cookie = -ENOSPC
 529          * all chunks are linked onto the tx_list head with their .node heads
 530          *      only during this function, then they are immediately spliced
 531          *      back onto the free list in form of a chain
 532          */
 533         for_each_sg(sgl, sg, sg_len, i) {
 534                 dma_addr_t sg_addr = sg_dma_address(sg);
 535                 size_t len = sg_dma_len(sg);
 536
 537                 if (!len)
 538                         goto err_get_desc;
 539
 540                 do {
 541                         dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
 542                                 i, sg, len, (unsigned long long)sg_addr);
 543
 544                         if (direction == DMA_FROM_DEVICE)
 545                                 new = sh_dmae_add_desc(sh_chan, flags,
 546                                                 &sg_addr, addr, &len, &first,
 547                                                 direction);
 548                         else
 549                                 new = sh_dmae_add_desc(sh_chan, flags,
 550                                                 addr, &sg_addr, &len, &first,
 551                                                 direction);
 552                         if (!new)
 553                                 goto err_get_desc;
 554
 555                         new->chunks = chunks--;
 556                         list_add_tail(&new->node, &tx_list);
 557                 } while (len);
 558         }
 559
 560         if (new != first)
 561                 new->async_tx.cookie = -ENOSPC;
 562
 563         /* Put them back on the free list, so, they don't get lost */
 564         list_splice_tail(&tx_list, &sh_chan->ld_free);
 565
 566         spin_unlock_bh(&sh_chan->desc_lock);
 567
 568         return &first->async_tx;
 569
 570 err_get_desc:
 571         list_for_each_entry(new, &tx_list, node)
 572                 new->mark = DESC_IDLE;
 573         list_splice(&tx_list, &sh_chan->ld_free);
 574
 575         spin_unlock_bh(&sh_chan->desc_lock);
 576
 577         return NULL;
 578 }
 579
 580 static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
 581         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 582         size_t len, unsigned long flags)
 583 {
 584         struct sh_dmae_chan *sh_chan;
 585         struct scatterlist sg;
 586
 587         if (!chan || !len)
 588                 return NULL;
 589
 590         sh_chan = to_sh_chan(chan);
 591
 592         sg_init_table(&sg, 1);
 593         sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
 594                     offset_in_page(dma_src));
 595         sg_dma_address(&sg) = dma_src;
 596         sg_dma_len(&sg) = len;
 597
 598         return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL,
 599                                flags);
 600 }
 601
 602 static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
 603         struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
 604         enum dma_data_direction direction, unsigned long flags)
 605 {
 606         struct sh_dmae_slave *param;
 607         struct sh_dmae_chan *sh_chan;
 608         dma_addr_t slave_addr;
 609
 610         if (!chan)
 611                 return NULL;
 612
 613         sh_chan = to_sh_chan(chan);
 614         param = chan->private;
 615
 616         /* Someone calling slave DMA on a public channel? */
 617         if (!param || !sg_len) {
 618                 dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n",
 619                          __func__, param, sg_len, param ? param->slave_id : -1);
 620                 return NULL;
 621         }
 622
 623         slave_addr = param->config->addr;
 624
 625         /*
 626          * if (param != NULL), this is a successfully requested slave channel,
 627          * therefore param->config != NULL too.
 628          */
 629         return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr,
 630                                direction, flags);
 631 }
 632
 633 static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 634                            unsigned long arg)
 635 {
 636         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 637
 638         /* Only supports DMA_TERMINATE_ALL */
 639         if (cmd != DMA_TERMINATE_ALL)
 640                 return -ENXIO;
 641
 642         if (!chan)
 643                 return -EINVAL;
 644
 645         spin_lock_bh(&sh_chan->desc_lock);
 646         dmae_halt(sh_chan);
 647
 648         if (!list_empty(&sh_chan->ld_queue)) {
 649                 /* Record partial transfer */
 650                 struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
 651                                                   struct sh_desc, node);
 652                 desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
 653                         sh_chan->xmit_shift;
 654
 655         }
 656         spin_unlock_bh(&sh_chan->desc_lock);
 657
 658         sh_dmae_chan_ld_cleanup(sh_chan, true);
 659
 660         return 0;
 661 }
 662
 663 static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 664 {
 665         struct sh_desc *desc, *_desc;
 666         /* Is the "exposed" head of a chain acked? */
 667         bool head_acked = false;
 668         dma_cookie_t cookie = 0;
 669         dma_async_tx_callback callback = NULL;
 670         void *param = NULL;
 671
 672         spin_lock_bh(&sh_chan->desc_lock);
 673         list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
 674                 struct dma_async_tx_descriptor *tx = &desc->async_tx;
 675
 676                 BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
 677                 BUG_ON(desc->mark != DESC_SUBMITTED &&
 678                        desc->mark != DESC_COMPLETED &&
 679                        desc->mark != DESC_WAITING);
 680
 681                 /*
 682                  * queue is ordered, and we use this loop to (1) clean up all
 683                  * completed descriptors, and to (2) update descriptor flags of
 684                  * any chunks in a (partially) completed chain
 685                  */
 686                 if (!all && desc->mark == DESC_SUBMITTED &&
 687                     desc->cookie != cookie)
 688                         break;
 689
 690                 if (tx->cookie > 0)
 691                         cookie = tx->cookie;
 692
 693                 if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
 694                         if (sh_chan->completed_cookie != desc->cookie - 1)
 695                                 dev_dbg(sh_chan->dev,
 696                                         "Completing cookie %d, expected %d\n",
 697                                         desc->cookie,
 698                                         sh_chan->completed_cookie + 1);
 699                         sh_chan->completed_cookie = desc->cookie;
 700                 }
 701
 702                 /* Call callback on the last chunk */
 703                 if (desc->mark == DESC_COMPLETED && tx->callback) {
 704                         desc->mark = DESC_WAITING;
 705                         callback = tx->callback;
 706                         param = tx->callback_param;
 707                         dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
 708                                 tx->cookie, tx, sh_chan->id);
 709                         BUG_ON(desc->chunks != 1);
 710                         break;
 711                 }
 712
 713                 if (tx->cookie > 0 || tx->cookie == -EBUSY) {
 714                         if (desc->mark == DESC_COMPLETED) {
 715                                 BUG_ON(tx->cookie < 0);
 716                                 desc->mark = DESC_WAITING;
 717                         }
 718                         head_acked = async_tx_test_ack(tx);
 719                 } else {
 720                         switch (desc->mark) {
 721                         case DESC_COMPLETED:
 722                                 desc->mark = DESC_WAITING;
 723                                 /* Fall through */
 724                         case DESC_WAITING:
 725                                 if (head_acked)
 726                                         async_tx_ack(&desc->async_tx);
 727                         }
 728                 }
 729
 730                 dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
 731                         tx, tx->cookie);
 732
 733                 if (((desc->mark == DESC_COMPLETED ||
 734                       desc->mark == DESC_WAITING) &&
 735                      async_tx_test_ack(&desc->async_tx)) || all) {
 736                         /* Remove from ld_queue list */
 737                         desc->mark = DESC_IDLE;
 738                         list_move(&desc->node, &sh_chan->ld_free);
 739                 }
 740         }
 741
 742         if (all && !callback)
 743                 /*
 744                  * Terminating and the loop completed normally: forgive
 745                  * uncompleted cookies
 746                  */
 747                 sh_chan->completed_cookie = sh_chan->common.cookie;
 748
 749         spin_unlock_bh(&sh_chan->desc_lock);
 750
 751         if (callback)
 752                 callback(param);
 753
 754         return callback;
 755 }
 756
 757 /*
 758  * sh_chan_ld_cleanup - Clean up link descriptors
 759  *
 760  * This function cleans up the ld_queue of DMA channel.
 761  */
 762 static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
 763 {
 764         while (__ld_cleanup(sh_chan, all))
 765                 ;
 766 }
 767
 768 static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
 769 {
 770         struct sh_desc *desc;
 771
 772         spin_lock_bh(&sh_chan->desc_lock);
 773         /* DMA work check */
 774         if (dmae_is_busy(sh_chan)) {
 775                 spin_unlock_bh(&sh_chan->desc_lock);
 776                 return;
 777         }
 778
 779         /* Find the first not transferred descriptor */
 780         list_for_each_entry(desc, &sh_chan->ld_queue, node)
 781                 if (desc->mark == DESC_SUBMITTED) {
 782                         dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
 783                                 desc->async_tx.cookie, sh_chan->id,
 784                                 desc->hw.tcr, desc->hw.sar, desc->hw.dar);
 785                         /* Get the ld start address from ld_queue */
 786                         dmae_set_reg(sh_chan, &desc->hw);
 787                         dmae_start(sh_chan);
 788                         break;
 789                 }
 790
 791         spin_unlock_bh(&sh_chan->desc_lock);
 792 }
 793
 794 static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
 795 {
 796         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 797         sh_chan_xfer_ld_queue(sh_chan);
 798 }
 799
 800 static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 801                                         dma_cookie_t cookie,
 802                                         struct dma_tx_state *txstate)
 803 {
 804         struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
 805         dma_cookie_t last_used;
 806         dma_cookie_t last_complete;
 807         enum dma_status status;
 808
 809         sh_dmae_chan_ld_cleanup(sh_chan, false);
 810
 811         /* First read completed cookie to avoid a skew */
 812         last_complete = sh_chan->completed_cookie;
 813         rmb();
 814         last_used = chan->cookie;
 815         BUG_ON(last_complete < 0);
 816         dma_set_tx_state(txstate, last_complete, last_used, 0);
 817
 818         spin_lock_bh(&sh_chan->desc_lock);
 819
 820         status = dma_async_is_complete(cookie, last_complete, last_used);
 821
 822         /*
 823          * If we don't find cookie on the queue, it has been aborted and we have
 824          * to report error
 825          */
 826         if (status != DMA_SUCCESS) {
 827                 struct sh_desc *desc;
 828                 status = DMA_ERROR;
 829                 list_for_each_entry(desc, &sh_chan->ld_queue, node)
 830                         if (desc->cookie == cookie) {
 831                                 status = DMA_IN_PROGRESS;
 832                                 break;
 833                         }
 834         }
 835
 836         spin_unlock_bh(&sh_chan->desc_lock);
 837
 838         return status;
 839 }
 840
 841 static irqreturn_t sh_dmae_interrupt(int irq, void *data)
 842 {
 843         irqreturn_t ret = IRQ_NONE;
 844         struct sh_dmae_chan *sh_chan = data;
 845         u32 chcr;
 846
 847         spin_lock(&sh_chan->desc_lock);
 848
 849         chcr = sh_dmae_readl(sh_chan, CHCR);
 850
 851         if (chcr & CHCR_TE) {
 852                 /* DMA stop */
 853                 dmae_halt(sh_chan);
 854
 855                 ret = IRQ_HANDLED;
 856                 tasklet_schedule(&sh_chan->tasklet);
 857         }
 858
 859         spin_unlock(&sh_chan->desc_lock);
 860
 861         return ret;
 862 }
 863
 864 /* Called from error IRQ or NMI */
 865 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 866 {
 867         unsigned int handled = 0;
 868         int i;
 869
 870         /* halt the dma controller */
 871         sh_dmae_ctl_stop(shdev);
 872
 873         /* We cannot detect, which channel caused the error, have to reset all */
 874         for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
 875                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 876                 struct sh_desc *desc;
 877                 LIST_HEAD(dl);
 878
 879                 if (!sh_chan)
 880                         continue;
 881
 882                 spin_lock(&sh_chan->desc_lock);
 883
 884                 /* Stop the channel */
 885                 dmae_halt(sh_chan);
 886
 887                 list_splice_init(&sh_chan->ld_queue, &dl);
 888
 889                 spin_unlock(&sh_chan->desc_lock);
 890
 891                 /* Complete all  */
 892                 list_for_each_entry(desc, &dl, node) {
 893                         struct dma_async_tx_descriptor *tx = &desc->async_tx;
 894                         desc->mark = DESC_IDLE;
 895                         if (tx->callback)
 896                                 tx->callback(tx->callback_param);
 897                 }
 898
 899                 spin_lock(&sh_chan->desc_lock);
 900                 list_splice(&dl, &sh_chan->ld_free);
 901                 spin_unlock(&sh_chan->desc_lock);
 902
 903                 handled++;
 904         }
 905
 906         sh_dmae_rst(shdev);
 907
 908         return !!handled;
 909 }
 910
 911 static irqreturn_t sh_dmae_err(int irq, void *data)
 912 {
 913         struct sh_dmae_device *shdev = data;
 914
 915         if (!(dmaor_read(shdev) & DMAOR_AE))
 916                 return IRQ_NONE;
 917
 918         sh_dmae_reset(data);
 919         return IRQ_HANDLED;
 920 }
 921
 922 static void dmae_do_tasklet(unsigned long data)
 923 {
 924         struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
 925         struct sh_desc *desc;
 926         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 927         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 928
 929         spin_lock(&sh_chan->desc_lock);
 930         list_for_each_entry(desc, &sh_chan->ld_queue, node) {
 931                 if (desc->mark == DESC_SUBMITTED &&
 932                     ((desc->direction == DMA_FROM_DEVICE &&
 933                       (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
 934                      (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
 935                         dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
 936                                 desc->async_tx.cookie, &desc->async_tx,
 937                                 desc->hw.dar);
 938                         desc->mark = DESC_COMPLETED;
 939                         break;
 940                 }
 941         }
 942         spin_unlock(&sh_chan->desc_lock);
 943
 944         /* Next desc */
 945         sh_chan_xfer_ld_queue(sh_chan);
 946         sh_dmae_chan_ld_cleanup(sh_chan, false);
 947 }
 948
 949 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
 950 {
 951         /* Fast path out if NMIF is not asserted for this controller */
 952         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
 953                 return false;
 954
 955         return sh_dmae_reset(shdev);
 956 }
 957
 958 static int sh_dmae_nmi_handler(struct notifier_block *self,
 959                                unsigned long cmd, void *data)
 960 {
 961         struct sh_dmae_device *shdev;
 962         int ret = NOTIFY_DONE;
 963         bool triggered;
 964
 965         /*
 966          * Only concern ourselves with NMI events.
 967          *
 968          * Normally we would check the die chain value, but as this needs
 969          * to be architecture independent, check for NMI context instead.
 970          */
 971         if (!in_nmi())
 972                 return NOTIFY_DONE;
 973
 974         rcu_read_lock();
 975         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
 976                 /*
 977                  * Only stop if one of the controllers has NMIF asserted,
 978                  * we do not want to interfere with regular address error
 979                  * handling or NMI events that don't concern the DMACs.
 980                  */
 981                 triggered = sh_dmae_nmi_notify(shdev);
 982                 if (triggered == true)
 983                         ret = NOTIFY_OK;
 984         }
 985         rcu_read_unlock();
 986
 987         return ret;
 988 }
 989
 990 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
 991         .notifier_call  = sh_dmae_nmi_handler,
 992
 993         /* Run before NMI debug handler and KGDB */
 994         .priority       = 1,
 995 };
 996
 997 static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 998                                         int irq, unsigned long flags)
 999 {
1000         int err;
1001         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
1002         struct platform_device *pdev = to_platform_device(shdev->common.dev);
1003         struct sh_dmae_chan *new_sh_chan;
1004
1005         /* alloc channel */
1006         new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
1007         if (!new_sh_chan) {
1008                 dev_err(shdev->common.dev,
1009                         "No free memory for allocating dma channels!\n");
1010                 return -ENOMEM;
1011         }
1012
1013         /* copy struct dma_device */
1014         new_sh_chan->common.device = &shdev->common;
1015
1016         new_sh_chan->dev = shdev->common.dev;
1017         new_sh_chan->id = id;
1018         new_sh_chan->irq = irq;
1019         new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
1020
1021         /* Init DMA tasklet */
1022         tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
1023                         (unsigned long)new_sh_chan);
1024
1025         spin_lock_init(&new_sh_chan->desc_lock);
1026
1027         /* Init descripter manage list */
1028         INIT_LIST_HEAD(&new_sh_chan->ld_queue);
1029         INIT_LIST_HEAD(&new_sh_chan->ld_free);
1030
1031         /* Add the channel to DMA device channel list */
1032         list_add_tail(&new_sh_chan->common.device_node,
1033                         &shdev->common.channels);
1034         shdev->common.chancnt++;
1035
1036         if (pdev->id >= 0)
1037                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1038                          "sh-dmae%d.%d", pdev->id, new_sh_chan->id);
1039         else
1040                 snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
1041                          "sh-dma%d", new_sh_chan->id);
1042
1043         /* set up channel irq */
1044         err = request_irq(irq, &sh_dmae_interrupt, flags,
1045                           new_sh_chan->dev_id, new_sh_chan);
1046         if (err) {
1047                 dev_err(shdev->common.dev, "DMA channel %d request_irq error "
1048                         "with return %d\n", id, err);
1049                 goto err_no_irq;
1050         }
1051
1052         shdev->chan[id] = new_sh_chan;
1053         return 0;
1054
1055 err_no_irq:
1056         /* remove from dmaengine device node */
1057         list_del(&new_sh_chan->common.device_node);
1058         kfree(new_sh_chan);
1059         return err;
1060 }
1061
1062 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
1063 {
1064         int i;
1065
1066         for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
1067                 if (shdev->chan[i]) {
1068                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
1069
1070                         free_irq(sh_chan->irq, sh_chan);
1071
1072                         list_del(&sh_chan->common.device_node);
1073                         kfree(sh_chan);
1074                         shdev->chan[i] = NULL;
1075                 }
1076         }
1077         shdev->common.chancnt = 0;
1078 }
1079
1080 static int __init sh_dmae_probe(struct platform_device *pdev)
1081 {
1082         struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
1083         unsigned long irqflags = IRQF_DISABLED,
1084                 chan_flag[SH_DMAC_MAX_CHANNELS] = {};
1085         int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
1086         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
1087         struct sh_dmae_device *shdev;
1088         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
1089
1090         /* get platform data */
1091         if (!pdata || !pdata->channel_num)
1092                 return -ENODEV;
1093
1094         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095         /* DMARS area is optional */
1096         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1097         /*
1098          * IRQ resources:
1099          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
1100          *    the error IRQ, in which case it is the only IRQ in this resource:
1101          *    start == end. If it is the only IRQ resource, all channels also
1102          *    use the same IRQ.
1103          * 2. DMA channel IRQ resources can be specified one per resource or in
1104          *    ranges (start != end)
1105          * 3. iff all events (channels and, optionally, error) on this
1106          *    controller use the same IRQ, only one IRQ resource can be
1107          *    specified, otherwise there must be one IRQ per channel, even if
1108          *    some of them are equal
1109          * 4. if all IRQs on this controller are equal or if some specific IRQs
1110          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
1111          *    requested with the IRQF_SHARED flag
1112          */
1113         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1114         if (!chan || !errirq_res)
1115                 return -ENODEV;
1116
1117         if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
1118                 dev_err(&pdev->dev, "DMAC register region already claimed\n");
1119                 return -EBUSY;
1120         }
1121
1122         if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
1123                 dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
1124                 err = -EBUSY;
1125                 goto ermrdmars;
1126         }
1127
1128         err = -ENOMEM;
1129         shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
1130         if (!shdev) {
1131                 dev_err(&pdev->dev, "Not enough memory\n");
1132                 goto ealloc;
1133         }
1134
1135         shdev->chan_reg = ioremap(chan->start, resource_size(chan));
1136         if (!shdev->chan_reg)
1137                 goto emapchan;
1138         if (dmars) {
1139                 shdev->dmars = ioremap(dmars->start, resource_size(dmars));
1140                 if (!shdev->dmars)
1141                         goto emapdmars;
1142         }
1143
1144         /* platform data */
1145         shdev->pdata = pdata;
1146
1147         platform_set_drvdata(pdev, shdev);
1148
1149         pm_runtime_enable(&pdev->dev);
1150         pm_runtime_get_sync(&pdev->dev);
1151
1152         spin_lock_irq(&sh_dmae_lock);
1153         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
1154         spin_unlock_irq(&sh_dmae_lock);
1155
1156         /* reset dma controller - only needed as a test */
1157         err = sh_dmae_rst(shdev);
1158         if (err)
1159                 goto rst_err;
1160
1161         INIT_LIST_HEAD(&shdev->common.channels);
1162
1163         dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
1164         if (pdata->slave && pdata->slave_num)
1165                 dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
1166
1167         shdev->common.device_alloc_chan_resources
1168                 = sh_dmae_alloc_chan_resources;
1169         shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
1170         shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
1171         shdev->common.device_tx_status = sh_dmae_tx_status;
1172         shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
1173
1174         /* Compulsory for DMA_SLAVE fields */
1175         shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg;
1176         shdev->common.device_control = sh_dmae_control;
1177
1178         shdev->common.dev = &pdev->dev;
1179         /* Default transfer size of 32 bytes requires 32-byte alignment */
1180         shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
1181
1182 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1183         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1184
1185         if (!chanirq_res)
1186                 chanirq_res = errirq_res;
1187         else
1188                 irqres++;
1189
1190         if (chanirq_res == errirq_res ||
1191             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
1192                 irqflags = IRQF_SHARED;
1193
1194         errirq = errirq_res->start;
1195
1196         err = request_irq(errirq, sh_dmae_err, irqflags,
1197                           "DMAC Address Error", shdev);
1198         if (err) {
1199                 dev_err(&pdev->dev,
1200                         "DMA failed requesting irq #%d, error %d\n",
1201                         errirq, err);
1202                 goto eirq_err;
1203         }
1204
1205 #else
1206         chanirq_res = errirq_res;
1207 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
1208
1209         if (chanirq_res->start == chanirq_res->end &&
1210             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
1211                 /* Special case - all multiplexed */
1212                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
1213                         if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
1214                                 chan_irq[irq_cnt] = chanirq_res->start;
1215                                 chan_flag[irq_cnt] = IRQF_SHARED;
1216                         } else {
1217                                 irq_cap = 1;
1218                                 break;
1219                         }
1220                 }
1221         } else {
1222                 do {
1223                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
1224                                 if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
1225                                         irq_cap = 1;
1226                                         break;
1227                                 }
1228
1229                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
1230                                     IORESOURCE_IRQ_SHAREABLE)
1231                                         chan_flag[irq_cnt] = IRQF_SHARED;
1232                                 else
1233                                         chan_flag[irq_cnt] = IRQF_DISABLED;
1234                                 dev_dbg(&pdev->dev,
1235                                         "Found IRQ %d for channel %d\n",
1236                                         i, irq_cnt);
1237                                 chan_irq[irq_cnt++] = i;
1238                         }
1239
1240                         if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
1241                                 break;
1242
1243                         chanirq_res = platform_get_resource(pdev,
1244                                                 IORESOURCE_IRQ, ++irqres);
1245                 } while (irq_cnt < pdata->channel_num && chanirq_res);
1246         }
1247
1248         /* Create DMA Channel */
1249         for (i = 0; i < irq_cnt; i++) {
1250                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
1251                 if (err)
1252                         goto chan_probe_err;
1253         }
1254
1255         if (irq_cap)
1256                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
1257                            "channels when a maximum of %d are supported.\n",
1258                            pdata->channel_num, SH_DMAC_MAX_CHANNELS);
1259
1260         pm_runtime_put(&pdev->dev);
1261
1262         dma_async_device_register(&shdev->common);
1263
1264         return err;
1265
1266 chan_probe_err:
1267         sh_dmae_chan_remove(shdev);
1268
1269 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
1270         free_irq(errirq, shdev);
1271 eirq_err:
1272 #endif
1273 rst_err:
1274         spin_lock_irq(&sh_dmae_lock);
1275         list_del_rcu(&shdev->node);
1276         spin_unlock_irq(&sh_dmae_lock);
1277
1278         pm_runtime_put(&pdev->dev);
1279         pm_runtime_disable(&pdev->dev);
1280
1281         if (dmars)
1282                 iounmap(shdev->dmars);
1283
1284         platform_set_drvdata(pdev, NULL);
1285 emapdmars:
1286         iounmap(shdev->chan_reg);
1287         synchronize_rcu();
1288 emapchan:
1289         kfree(shdev);
1290 ealloc:
1291         if (dmars)
1292                 release_mem_region(dmars->start, resource_size(dmars));
1293 ermrdmars:
1294         release_mem_region(chan->start, resource_size(chan));
1295
1296         return err;
1297 }
1298
1299 static int __exit sh_dmae_remove(struct platform_device *pdev)
1300 {
1301         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1302         struct resource *res;
1303         int errirq = platform_get_irq(pdev, 0);
1304
1305         dma_async_device_unregister(&shdev->common);
1306
1307         if (errirq > 0)
1308                 free_irq(errirq, shdev);
1309
1310         spin_lock_irq(&sh_dmae_lock);
1311         list_del_rcu(&shdev->node);
1312         spin_unlock_irq(&sh_dmae_lock);
1313
1314         /* channel data remove */
1315         sh_dmae_chan_remove(shdev);
1316
1317         pm_runtime_disable(&pdev->dev);
1318
1319         if (shdev->dmars)
1320                 iounmap(shdev->dmars);
1321         iounmap(shdev->chan_reg);
1322
1323         platform_set_drvdata(pdev, NULL);
1324
1325         synchronize_rcu();
1326         kfree(shdev);
1327
1328         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329         if (res)
1330                 release_mem_region(res->start, resource_size(res));
1331         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1332         if (res)
1333                 release_mem_region(res->start, resource_size(res));
1334
1335         return 0;
1336 }
1337
1338 static void sh_dmae_shutdown(struct platform_device *pdev)
1339 {
1340         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
1341         sh_dmae_ctl_stop(shdev);
1342 }
1343
1344 static int sh_dmae_runtime_suspend(struct device *dev)
1345 {
1346         return 0;
1347 }
1348
1349 static int sh_dmae_runtime_resume(struct device *dev)
1350 {
1351         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1352
1353         return sh_dmae_rst(shdev);
1354 }
1355
1356 #ifdef CONFIG_PM
1357 static int sh_dmae_suspend(struct device *dev)
1358 {
1359         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1360         int i;
1361
1362         for (i = 0; i < shdev->pdata->channel_num; i++) {
1363                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1364                 if (sh_chan->descs_allocated)
1365                         sh_chan->pm_error = pm_runtime_put_sync(dev);
1366         }
1367
1368         return 0;
1369 }
1370
1371 static int sh_dmae_resume(struct device *dev)
1372 {
1373         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
1374         int i;
1375
1376         for (i = 0; i < shdev->pdata->channel_num; i++) {
1377                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
1378                 struct sh_dmae_slave *param = sh_chan->common.private;
1379
1380                 if (!sh_chan->descs_allocated)
1381                         continue;
1382
1383                 if (!sh_chan->pm_error)
1384                         pm_runtime_get_sync(dev);
1385
1386                 if (param) {
1387                         const struct sh_dmae_slave_config *cfg = param->config;
1388                         dmae_set_dmars(sh_chan, cfg->mid_rid);
1389                         dmae_set_chcr(sh_chan, cfg->chcr);
1390                 } else {
1391                         dmae_init(sh_chan);
1392                 }
1393         }
1394
1395         return 0;
1396 }
1397 #else
1398 #define sh_dmae_suspend NULL
1399 #define sh_dmae_resume NULL
1400 #endif
1401
1402 const struct dev_pm_ops sh_dmae_pm = {
1403         .suspend                = sh_dmae_suspend,
1404         .resume                 = sh_dmae_resume,
1405         .runtime_suspend        = sh_dmae_runtime_suspend,
1406         .runtime_resume         = sh_dmae_runtime_resume,
1407 };
1408
1409 static struct platform_driver sh_dmae_driver = {
1410         .remove         = __exit_p(sh_dmae_remove),
1411         .shutdown       = sh_dmae_shutdown,
1412         .driver = {
1413                 .owner  = THIS_MODULE,
1414                 .name   = "sh-dma-engine",
1415                 .pm     = &sh_dmae_pm,
1416         },
1417 };
1418
1419 static int __init sh_dmae_init(void)
1420 {
1421         /* Wire up NMI handling */
1422         int err = register_die_notifier(&sh_dmae_nmi_notifier);
1423         if (err)
1424                 return err;
1425
1426         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
1427 }
1428 module_init(sh_dmae_init);
1429
1430 static void __exit sh_dmae_exit(void)
1431 {
1432         platform_driver_unregister(&sh_dmae_driver);
1433
1434         unregister_die_notifier(&sh_dmae_nmi_notifier);
1435 }
1436 module_exit(sh_dmae_exit);
1437
1438 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
1439 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
1440 MODULE_LICENSE("GPL");
1441 MODULE_ALIAS("platform:sh-dma-engine");