drivers/dma/fsldma.c

   1 /*
   2  * Freescale MPC85xx, MPC83xx DMA Engine support
   3  *
   4  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author:
   7  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
   8  *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
   9  *
  10  * Description:
  11  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  12  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
  13  *   The support for MPC8349 DMA contorller is also added.
  14  *
  15  * This driver instructs the DMA controller to issue the PCI Read Multiple
  16  * command for PCI read operations, instead of using the default PCI Read Line
  17  * command. Please be aware that this setting may result in read pre-fetching
  18  * on some platforms.
  19  *
  20  * This is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  */
  26
  27 #include <linux/init.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/delay.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/dmapool.h>
  35 #include <linux/of_platform.h>
  36
  37 #include "fsldma.h"
  38
  39 static void dma_init(struct fsl_dma_chan *fsl_chan)
  40 {
  41         /* Reset the channel */
  42         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
  43
  44         switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
  45         case FSL_DMA_IP_85XX:
  46                 /* Set the channel to below modes:
  47                  * EIE - Error interrupt enable
  48                  * EOSIE - End of segments interrupt enable (basic mode)
  49                  * EOLNIE - End of links interrupt enable
  50                  */
  51                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
  52                                 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
  53                 break;
  54         case FSL_DMA_IP_83XX:
  55                 /* Set the channel to below modes:
  56                  * EOTIE - End-of-transfer interrupt enable
  57                  * PRC_RM - PCI read multiple
  58                  */
  59                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE
  60                                 | FSL_DMA_MR_PRC_RM, 32);
  61                 break;
  62         }
  63
  64 }
  65
  66 static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
  67 {
  68         DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
  69 }
  70
  71 static u32 get_sr(struct fsl_dma_chan *fsl_chan)
  72 {
  73         return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
  74 }
  75
  76 static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
  77                                 struct fsl_dma_ld_hw *hw, u32 count)
  78 {
  79         hw->count = CPU_TO_DMA(fsl_chan, count, 32);
  80 }
  81
  82 static void set_desc_src(struct fsl_dma_chan *fsl_chan,
  83                                 struct fsl_dma_ld_hw *hw, dma_addr_t src)
  84 {
  85         u64 snoop_bits;
  86
  87         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  88                 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
  89         hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
  90 }
  91
  92 static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
  93                                 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
  94 {
  95         u64 snoop_bits;
  96
  97         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
  98                 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
  99         hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
 100 }
 101
 102 static void set_desc_next(struct fsl_dma_chan *fsl_chan,
 103                                 struct fsl_dma_ld_hw *hw, dma_addr_t next)
 104 {
 105         u64 snoop_bits;
 106
 107         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
 108                 ? FSL_DMA_SNEN : 0;
 109         hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
 110 }
 111
 112 static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 113 {
 114         DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
 115 }
 116
 117 static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
 118 {
 119         return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
 120 }
 121
 122 static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
 123 {
 124         DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
 125 }
 126
 127 static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
 128 {
 129         return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
 130 }
 131
 132 static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
 133 {
 134         return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
 135 }
 136
 137 static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
 138 {
 139         u32 sr = get_sr(fsl_chan);
 140         return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 141 }
 142
 143 static void dma_start(struct fsl_dma_chan *fsl_chan)
 144 {
 145         u32 mr_set = 0;
 146
 147         if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
 148                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
 149                 mr_set |= FSL_DMA_MR_EMP_EN;
 150         } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
 151                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 152                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 153                                 & ~FSL_DMA_MR_EMP_EN, 32);
 154         }
 155
 156         if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
 157                 mr_set |= FSL_DMA_MR_EMS_EN;
 158         else
 159                 mr_set |= FSL_DMA_MR_CS;
 160
 161         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 162                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 163                         | mr_set, 32);
 164 }
 165
 166 static void dma_halt(struct fsl_dma_chan *fsl_chan)
 167 {
 168         int i;
 169
 170         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 171                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
 172                 32);
 173         DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 174                 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
 175                 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
 176
 177         for (i = 0; i < 100; i++) {
 178                 if (dma_is_idle(fsl_chan))
 179                         break;
 180                 udelay(10);
 181         }
 182         if (i >= 100 && !dma_is_idle(fsl_chan))
 183                 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
 184 }
 185
 186 static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
 187                         struct fsl_desc_sw *desc)
 188 {
 189         u64 snoop_bits;
 190
 191         snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
 192                 ? FSL_DMA_SNEN : 0;
 193
 194         desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 195                 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
 196                         | snoop_bits, 64);
 197 }
 198
 199 static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
 200                 struct fsl_desc_sw *new_desc)
 201 {
 202         struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
 203
 204         if (list_empty(&fsl_chan->ld_queue))
 205                 return;
 206
 207         /* Link to the new descriptor physical address and
 208          * Enable End-of-segment interrupt for
 209          * the last link descriptor.
 210          * (the previous node's next link descriptor)
 211          *
 212          * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
 213          */
 214         queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
 215                         new_desc->async_tx.phys | FSL_DMA_EOSIE |
 216                         (((fsl_chan->feature & FSL_DMA_IP_MASK)
 217                                 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
 218 }
 219
 220 /**
 221  * fsl_chan_set_src_loop_size - Set source address hold transfer size
 222  * @fsl_chan : Freescale DMA channel
 223  * @size     : Address loop size, 0 for disable loop
 224  *
 225  * The set source address hold transfer size. The source
 226  * address hold or loop transfer size is when the DMA transfer
 227  * data from source address (SA), if the loop size is 4, the DMA will
 228  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
 229  * SA + 1 ... and so on.
 230  */
 231 static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 232 {
 233         switch (size) {
 234         case 0:
 235                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 236                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 237                         (~FSL_DMA_MR_SAHE), 32);
 238                 break;
 239         case 1:
 240         case 2:
 241         case 4:
 242         case 8:
 243                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 244                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 245                         FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
 246                         32);
 247                 break;
 248         }
 249 }
 250
 251 /**
 252  * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
 253  * @fsl_chan : Freescale DMA channel
 254  * @size     : Address loop size, 0 for disable loop
 255  *
 256  * The set destination address hold transfer size. The destination
 257  * address hold or loop transfer size is when the DMA transfer
 258  * data to destination address (TA), if the loop size is 4, the DMA will
 259  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
 260  * TA + 1 ... and so on.
 261  */
 262 static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
 263 {
 264         switch (size) {
 265         case 0:
 266                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 267                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
 268                         (~FSL_DMA_MR_DAHE), 32);
 269                 break;
 270         case 1:
 271         case 2:
 272         case 4:
 273         case 8:
 274                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 275                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
 276                         FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
 277                         32);
 278                 break;
 279         }
 280 }
 281
 282 /**
 283  * fsl_chan_toggle_ext_pause - Toggle channel external pause status
 284  * @fsl_chan : Freescale DMA channel
 285  * @size     : Pause control size, 0 for disable external pause control.
 286  *             The maximum is 1024.
 287  *
 288  * The Freescale DMA channel can be controlled by the external
 289  * signal DREQ#. The pause control size is how many bytes are allowed
 290  * to transfer before pausing the channel, after which a new assertion
 291  * of DREQ# resumes channel operation.
 292  */
 293 static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
 294 {
 295         if (size > 1024)
 296                 return;
 297
 298         if (size) {
 299                 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
 300                         DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
 301                                 | ((__ilog2(size) << 24) & 0x0f000000),
 302                         32);
 303                 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
 304         } else
 305                 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 306 }
 307
 308 /**
 309  * fsl_chan_toggle_ext_start - Toggle channel external start status
 310  * @fsl_chan : Freescale DMA channel
 311  * @enable   : 0 is disabled, 1 is enabled.
 312  *
 313  * If enable the external start, the channel can be started by an
 314  * external DMA start pin. So the dma_start() does not start the
 315  * transfer immediately. The DMA channel will wait for the
 316  * control pin asserted.
 317  */
 318 static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
 319 {
 320         if (enable)
 321                 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
 322         else
 323                 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 324 }
 325
 326 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 327 {
 328         struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
 329         struct fsl_desc_sw *desc;
 330         unsigned long flags;
 331         dma_cookie_t cookie;
 332
 333         /* cookie increment and adding to ld_queue must be atomic */
 334         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 335
 336         cookie = fsl_chan->common.cookie;
 337         list_for_each_entry(desc, &tx->tx_list, node) {
 338                 cookie++;
 339                 if (cookie < 0)
 340                         cookie = 1;
 341
 342                 desc->async_tx.cookie = cookie;
 343         }
 344
 345         fsl_chan->common.cookie = cookie;
 346         append_ld_queue(fsl_chan, tx_to_fsl_desc(tx));
 347         list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev);
 348
 349         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 350
 351         return cookie;
 352 }
 353
 354 /**
 355  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
 356  * @fsl_chan : Freescale DMA channel
 357  *
 358  * Return - The descriptor allocated. NULL for failed.
 359  */
 360 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
 361                                         struct fsl_dma_chan *fsl_chan)
 362 {
 363         dma_addr_t pdesc;
 364         struct fsl_desc_sw *desc_sw;
 365
 366         desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
 367         if (desc_sw) {
 368                 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
 369                 dma_async_tx_descriptor_init(&desc_sw->async_tx,
 370                                                 &fsl_chan->common);
 371                 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
 372                 desc_sw->async_tx.phys = pdesc;
 373         }
 374
 375         return desc_sw;
 376 }
 377
 378
 379 /**
 380  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
 381  * @fsl_chan : Freescale DMA channel
 382  *
 383  * This function will create a dma pool for descriptor allocation.
 384  *
 385  * Return - The number of descriptors allocated.
 386  */
 387 static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
 388 {
 389         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 390
 391         /* Has this channel already been allocated? */
 392         if (fsl_chan->desc_pool)
 393                 return 1;
 394
 395         /* We need the descriptor to be aligned to 32bytes
 396          * for meeting FSL DMA specification requirement.
 397          */
 398         fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
 399                         fsl_chan->dev, sizeof(struct fsl_desc_sw),
 400                         32, 0);
 401         if (!fsl_chan->desc_pool) {
 402                 dev_err(fsl_chan->dev, "No memory for channel %d "
 403                         "descriptor dma pool.\n", fsl_chan->id);
 404                 return 0;
 405         }
 406
 407         return 1;
 408 }
 409
 410 /**
 411  * fsl_dma_free_chan_resources - Free all resources of the channel.
 412  * @fsl_chan : Freescale DMA channel
 413  */
 414 static void fsl_dma_free_chan_resources(struct dma_chan *chan)
 415 {
 416         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 417         struct fsl_desc_sw *desc, *_desc;
 418         unsigned long flags;
 419
 420         dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
 421         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 422         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 423 #ifdef FSL_DMA_LD_DEBUG
 424                 dev_dbg(fsl_chan->dev,
 425                                 "LD %p will be released.\n", desc);
 426 #endif
 427                 list_del(&desc->node);
 428                 /* free link descriptor */
 429                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 430         }
 431         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 432         dma_pool_destroy(fsl_chan->desc_pool);
 433
 434         fsl_chan->desc_pool = NULL;
 435 }
 436
 437 static struct dma_async_tx_descriptor *
 438 fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
 439 {
 440         struct fsl_dma_chan *fsl_chan;
 441         struct fsl_desc_sw *new;
 442
 443         if (!chan)
 444                 return NULL;
 445
 446         fsl_chan = to_fsl_chan(chan);
 447
 448         new = fsl_dma_alloc_descriptor(fsl_chan);
 449         if (!new) {
 450                 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
 451                 return NULL;
 452         }
 453
 454         new->async_tx.cookie = -EBUSY;
 455         new->async_tx.flags = flags;
 456
 457         /* Insert the link descriptor to the LD ring */
 458         list_add_tail(&new->node, &new->async_tx.tx_list);
 459
 460         /* Set End-of-link to the last link descriptor of new list*/
 461         set_ld_eol(fsl_chan, new);
 462
 463         return &new->async_tx;
 464 }
 465
 466 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
 467         struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
 468         size_t len, unsigned long flags)
 469 {
 470         struct fsl_dma_chan *fsl_chan;
 471         struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
 472         struct list_head *list;
 473         size_t copy;
 474
 475         if (!chan)
 476                 return NULL;
 477
 478         if (!len)
 479                 return NULL;
 480
 481         fsl_chan = to_fsl_chan(chan);
 482
 483         do {
 484
 485                 /* Allocate the link descriptor from DMA pool */
 486                 new = fsl_dma_alloc_descriptor(fsl_chan);
 487                 if (!new) {
 488                         dev_err(fsl_chan->dev,
 489                                         "No free memory for link descriptor\n");
 490                         goto fail;
 491                 }
 492 #ifdef FSL_DMA_LD_DEBUG
 493                 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
 494 #endif
 495
 496                 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 497
 498                 set_desc_cnt(fsl_chan, &new->hw, copy);
 499                 set_desc_src(fsl_chan, &new->hw, dma_src);
 500                 set_desc_dest(fsl_chan, &new->hw, dma_dest);
 501
 502                 if (!first)
 503                         first = new;
 504                 else
 505                         set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
 506
 507                 new->async_tx.cookie = 0;
 508                 async_tx_ack(&new->async_tx);
 509
 510                 prev = new;
 511                 len -= copy;
 512                 dma_src += copy;
 513                 dma_dest += copy;
 514
 515                 /* Insert the link descriptor to the LD ring */
 516                 list_add_tail(&new->node, &first->async_tx.tx_list);
 517         } while (len);
 518
 519         new->async_tx.flags = flags; /* client is in control of this ack */
 520         new->async_tx.cookie = -EBUSY;
 521
 522         /* Set End-of-link to the last link descriptor of new list*/
 523         set_ld_eol(fsl_chan, new);
 524
 525         return &first->async_tx;
 526
 527 fail:
 528         if (!first)
 529                 return NULL;
 530
 531         list = &first->async_tx.tx_list;
 532         list_for_each_entry_safe_reverse(new, prev, list, node) {
 533                 list_del(&new->node);
 534                 dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
 535         }
 536
 537         return NULL;
 538 }
 539
 540 /**
 541  * fsl_dma_update_completed_cookie - Update the completed cookie.
 542  * @fsl_chan : Freescale DMA channel
 543  */
 544 static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
 545 {
 546         struct fsl_desc_sw *cur_desc, *desc;
 547         dma_addr_t ld_phy;
 548
 549         ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
 550
 551         if (ld_phy) {
 552                 cur_desc = NULL;
 553                 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
 554                         if (desc->async_tx.phys == ld_phy) {
 555                                 cur_desc = desc;
 556                                 break;
 557                         }
 558
 559                 if (cur_desc && cur_desc->async_tx.cookie) {
 560                         if (dma_is_idle(fsl_chan))
 561                                 fsl_chan->completed_cookie =
 562                                         cur_desc->async_tx.cookie;
 563                         else
 564                                 fsl_chan->completed_cookie =
 565                                         cur_desc->async_tx.cookie - 1;
 566                 }
 567         }
 568 }
 569
 570 /**
 571  * fsl_chan_ld_cleanup - Clean up link descriptors
 572  * @fsl_chan : Freescale DMA channel
 573  *
 574  * This function clean up the ld_queue of DMA channel.
 575  * If 'in_intr' is set, the function will move the link descriptor to
 576  * the recycle list. Otherwise, free it directly.
 577  */
 578 static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
 579 {
 580         struct fsl_desc_sw *desc, *_desc;
 581         unsigned long flags;
 582
 583         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 584
 585         dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
 586                         fsl_chan->completed_cookie);
 587         list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
 588                 dma_async_tx_callback callback;
 589                 void *callback_param;
 590
 591                 if (dma_async_is_complete(desc->async_tx.cookie,
 592                             fsl_chan->completed_cookie, fsl_chan->common.cookie)
 593                                 == DMA_IN_PROGRESS)
 594                         break;
 595
 596                 callback = desc->async_tx.callback;
 597                 callback_param = desc->async_tx.callback_param;
 598
 599                 /* Remove from ld_queue list */
 600                 list_del(&desc->node);
 601
 602                 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
 603                                 desc);
 604                 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
 605
 606                 /* Run the link descriptor callback function */
 607                 if (callback) {
 608                         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 609                         dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
 610                                         desc);
 611                         callback(callback_param);
 612                         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 613                 }
 614         }
 615         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 616 }
 617
 618 /**
 619  * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
 620  * @fsl_chan : Freescale DMA channel
 621  */
 622 static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
 623 {
 624         struct list_head *ld_node;
 625         dma_addr_t next_dest_addr;
 626         unsigned long flags;
 627
 628         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 629
 630         if (!dma_is_idle(fsl_chan))
 631                 goto out_unlock;
 632
 633         dma_halt(fsl_chan);
 634
 635         /* If there are some link descriptors
 636          * not transfered in queue. We need to start it.
 637          */
 638
 639         /* Find the first un-transfer desciptor */
 640         for (ld_node = fsl_chan->ld_queue.next;
 641                 (ld_node != &fsl_chan->ld_queue)
 642                         && (dma_async_is_complete(
 643                                 to_fsl_desc(ld_node)->async_tx.cookie,
 644                                 fsl_chan->completed_cookie,
 645                                 fsl_chan->common.cookie) == DMA_SUCCESS);
 646                 ld_node = ld_node->next);
 647
 648         if (ld_node != &fsl_chan->ld_queue) {
 649                 /* Get the ld start address from ld_queue */
 650                 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
 651                 dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
 652                                 (unsigned long long)next_dest_addr);
 653                 set_cdar(fsl_chan, next_dest_addr);
 654                 dma_start(fsl_chan);
 655         } else {
 656                 set_cdar(fsl_chan, 0);
 657                 set_ndar(fsl_chan, 0);
 658         }
 659
 660 out_unlock:
 661         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 662 }
 663
 664 /**
 665  * fsl_dma_memcpy_issue_pending - Issue the DMA start command
 666  * @fsl_chan : Freescale DMA channel
 667  */
 668 static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
 669 {
 670         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 671
 672 #ifdef FSL_DMA_LD_DEBUG
 673         struct fsl_desc_sw *ld;
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&fsl_chan->desc_lock, flags);
 677         if (list_empty(&fsl_chan->ld_queue)) {
 678                 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 679                 return;
 680         }
 681
 682         dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
 683         list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
 684                 int i;
 685                 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
 686                                 fsl_chan->id, ld->async_tx.phys);
 687                 for (i = 0; i < 8; i++)
 688                         dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
 689                                         i, *(((u32 *)&ld->hw) + i));
 690         }
 691         dev_dbg(fsl_chan->dev, "----------------\n");
 692         spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
 693 #endif
 694
 695         fsl_chan_xfer_ld_queue(fsl_chan);
 696 }
 697
 698 /**
 699  * fsl_dma_is_complete - Determine the DMA status
 700  * @fsl_chan : Freescale DMA channel
 701  */
 702 static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
 703                                         dma_cookie_t cookie,
 704                                         dma_cookie_t *done,
 705                                         dma_cookie_t *used)
 706 {
 707         struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
 708         dma_cookie_t last_used;
 709         dma_cookie_t last_complete;
 710
 711         fsl_chan_ld_cleanup(fsl_chan);
 712
 713         last_used = chan->cookie;
 714         last_complete = fsl_chan->completed_cookie;
 715
 716         if (done)
 717                 *done = last_complete;
 718
 719         if (used)
 720                 *used = last_used;
 721
 722         return dma_async_is_complete(cookie, last_complete, last_used);
 723 }
 724
 725 static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
 726 {
 727         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 728         u32 stat;
 729         int update_cookie = 0;
 730         int xfer_ld_q = 0;
 731
 732         stat = get_sr(fsl_chan);
 733         dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
 734                                                 fsl_chan->id, stat);
 735         set_sr(fsl_chan, stat);         /* Clear the event register */
 736
 737         stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
 738         if (!stat)
 739                 return IRQ_NONE;
 740
 741         if (stat & FSL_DMA_SR_TE)
 742                 dev_err(fsl_chan->dev, "Transfer Error!\n");
 743
 744         /* Programming Error
 745          * The DMA_INTERRUPT async_tx is a NULL transfer, which will
 746          * triger a PE interrupt.
 747          */
 748         if (stat & FSL_DMA_SR_PE) {
 749                 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
 750                 if (get_bcr(fsl_chan) == 0) {
 751                         /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
 752                          * Now, update the completed cookie, and continue the
 753                          * next uncompleted transfer.
 754                          */
 755                         update_cookie = 1;
 756                         xfer_ld_q = 1;
 757                 }
 758                 stat &= ~FSL_DMA_SR_PE;
 759         }
 760
 761         /* If the link descriptor segment transfer finishes,
 762          * we will recycle the used descriptor.
 763          */
 764         if (stat & FSL_DMA_SR_EOSI) {
 765                 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
 766                 dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
 767                         (unsigned long long)get_cdar(fsl_chan),
 768                         (unsigned long long)get_ndar(fsl_chan));
 769                 stat &= ~FSL_DMA_SR_EOSI;
 770                 update_cookie = 1;
 771         }
 772
 773         /* For MPC8349, EOCDI event need to update cookie
 774          * and start the next transfer if it exist.
 775          */
 776         if (stat & FSL_DMA_SR_EOCDI) {
 777                 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
 778                 stat &= ~FSL_DMA_SR_EOCDI;
 779                 update_cookie = 1;
 780                 xfer_ld_q = 1;
 781         }
 782
 783         /* If it current transfer is the end-of-transfer,
 784          * we should clear the Channel Start bit for
 785          * prepare next transfer.
 786          */
 787         if (stat & FSL_DMA_SR_EOLNI) {
 788                 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
 789                 stat &= ~FSL_DMA_SR_EOLNI;
 790                 xfer_ld_q = 1;
 791         }
 792
 793         if (update_cookie)
 794                 fsl_dma_update_completed_cookie(fsl_chan);
 795         if (xfer_ld_q)
 796                 fsl_chan_xfer_ld_queue(fsl_chan);
 797         if (stat)
 798                 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
 799                                         stat);
 800
 801         dev_dbg(fsl_chan->dev, "event: Exit\n");
 802         tasklet_schedule(&fsl_chan->tasklet);
 803         return IRQ_HANDLED;
 804 }
 805
 806 static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
 807 {
 808         struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
 809         u32 gsr;
 810         int ch_nr;
 811
 812         gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
 813                         : in_le32(fdev->reg_base);
 814         ch_nr = (32 - ffs(gsr)) / 8;
 815
 816         return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
 817                         fdev->chan[ch_nr]) : IRQ_NONE;
 818 }
 819
 820 static void dma_do_tasklet(unsigned long data)
 821 {
 822         struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
 823         fsl_chan_ld_cleanup(fsl_chan);
 824 }
 825
 826 static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
 827         struct device_node *node, u32 feature, const char *compatible)
 828 {
 829         struct fsl_dma_chan *new_fsl_chan;
 830         int err;
 831
 832         /* alloc channel */
 833         new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
 834         if (!new_fsl_chan) {
 835                 dev_err(fdev->dev, "No free memory for allocating "
 836                                 "dma channels!\n");
 837                 return -ENOMEM;
 838         }
 839
 840         /* get dma channel register base */
 841         err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
 842         if (err) {
 843                 dev_err(fdev->dev, "Can't get %s property 'reg'\n",
 844                                 node->full_name);
 845                 goto err_no_reg;
 846         }
 847
 848         new_fsl_chan->feature = feature;
 849
 850         if (!fdev->feature)
 851                 fdev->feature = new_fsl_chan->feature;
 852
 853         /* If the DMA device's feature is different than its channels',
 854          * report the bug.
 855          */
 856         WARN_ON(fdev->feature != new_fsl_chan->feature);
 857
 858         new_fsl_chan->dev = fdev->dev;
 859         new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
 860                         new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
 861
 862         new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
 863         if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
 864                 dev_err(fdev->dev, "There is no %d channel!\n",
 865                                 new_fsl_chan->id);
 866                 err = -EINVAL;
 867                 goto err_no_chan;
 868         }
 869         fdev->chan[new_fsl_chan->id] = new_fsl_chan;
 870         tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
 871                         (unsigned long)new_fsl_chan);
 872
 873         /* Init the channel */
 874         dma_init(new_fsl_chan);
 875
 876         /* Clear cdar registers */
 877         set_cdar(new_fsl_chan, 0);
 878
 879         switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
 880         case FSL_DMA_IP_85XX:
 881                 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
 882         case FSL_DMA_IP_83XX:
 883                 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
 884                 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
 885                 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
 886         }
 887
 888         spin_lock_init(&new_fsl_chan->desc_lock);
 889         INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
 890
 891         new_fsl_chan->common.device = &fdev->common;
 892
 893         /* Add the channel to DMA device channel list */
 894         list_add_tail(&new_fsl_chan->common.device_node,
 895                         &fdev->common.channels);
 896         fdev->common.chancnt++;
 897
 898         new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
 899         if (new_fsl_chan->irq != NO_IRQ) {
 900                 err = request_irq(new_fsl_chan->irq,
 901                                         &fsl_dma_chan_do_interrupt, IRQF_SHARED,
 902                                         "fsldma-channel", new_fsl_chan);
 903                 if (err) {
 904                         dev_err(fdev->dev, "DMA channel %s request_irq error "
 905                                 "with return %d\n", node->full_name, err);
 906                         goto err_no_irq;
 907                 }
 908         }
 909
 910         dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
 911                  compatible,
 912                  new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
 913
 914         return 0;
 915
 916 err_no_irq:
 917         list_del(&new_fsl_chan->common.device_node);
 918 err_no_chan:
 919         iounmap(new_fsl_chan->reg_base);
 920 err_no_reg:
 921         kfree(new_fsl_chan);
 922         return err;
 923 }
 924
 925 static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
 926 {
 927         if (fchan->irq != NO_IRQ)
 928                 free_irq(fchan->irq, fchan);
 929         list_del(&fchan->common.device_node);
 930         iounmap(fchan->reg_base);
 931         kfree(fchan);
 932 }
 933
 934 static int __devinit of_fsl_dma_probe(struct of_device *dev,
 935                         const struct of_device_id *match)
 936 {
 937         int err;
 938         struct fsl_dma_device *fdev;
 939         struct device_node *child;
 940
 941         fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
 942         if (!fdev) {
 943                 dev_err(&dev->dev, "No enough memory for 'priv'\n");
 944                 return -ENOMEM;
 945         }
 946         fdev->dev = &dev->dev;
 947         INIT_LIST_HEAD(&fdev->common.channels);
 948
 949         /* get DMA controller register base */
 950         err = of_address_to_resource(dev->node, 0, &fdev->reg);
 951         if (err) {
 952                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
 953                                 dev->node->full_name);
 954                 goto err_no_reg;
 955         }
 956
 957         dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
 958                         "controller at 0x%llx...\n",
 959                         match->compatible, (unsigned long long)fdev->reg.start);
 960         fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
 961                                                 - fdev->reg.start + 1);
 962
 963         dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
 964         dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
 965         fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
 966         fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
 967         fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
 968         fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
 969         fdev->common.device_is_tx_complete = fsl_dma_is_complete;
 970         fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
 971         fdev->common.dev = &dev->dev;
 972
 973         fdev->irq = irq_of_parse_and_map(dev->node, 0);
 974         if (fdev->irq != NO_IRQ) {
 975                 err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
 976                                         "fsldma-device", fdev);
 977                 if (err) {
 978                         dev_err(&dev->dev, "DMA device request_irq error "
 979                                 "with return %d\n", err);
 980                         goto err;
 981                 }
 982         }
 983
 984         dev_set_drvdata(&(dev->dev), fdev);
 985
 986         /* We cannot use of_platform_bus_probe() because there is no
 987          * of_platform_bus_remove.  Instead, we manually instantiate every DMA
 988          * channel object.
 989          */
 990         for_each_child_of_node(dev->node, child) {
 991                 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
 992                         fsl_dma_chan_probe(fdev, child,
 993                                 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
 994                                 "fsl,eloplus-dma-channel");
 995                 if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
 996                         fsl_dma_chan_probe(fdev, child,
 997                                 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
 998                                 "fsl,elo-dma-channel");
 999         }
1000
1001         dma_async_device_register(&fdev->common);
1002         return 0;
1003
1004 err:
1005         iounmap(fdev->reg_base);
1006 err_no_reg:
1007         kfree(fdev);
1008         return err;
1009 }
1010
1011 static int of_fsl_dma_remove(struct of_device *of_dev)
1012 {
1013         struct fsl_dma_device *fdev;
1014         unsigned int i;
1015
1016         fdev = dev_get_drvdata(&of_dev->dev);
1017
1018         dma_async_device_unregister(&fdev->common);
1019
1020         for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
1021                 if (fdev->chan[i])
1022                         fsl_dma_chan_remove(fdev->chan[i]);
1023
1024         if (fdev->irq != NO_IRQ)
1025                 free_irq(fdev->irq, fdev);
1026
1027         iounmap(fdev->reg_base);
1028
1029         kfree(fdev);
1030         dev_set_drvdata(&of_dev->dev, NULL);
1031
1032         return 0;
1033 }
1034
1035 static struct of_device_id of_fsl_dma_ids[] = {
1036         { .compatible = "fsl,eloplus-dma", },
1037         { .compatible = "fsl,elo-dma", },
1038         {}
1039 };
1040
1041 static struct of_platform_driver of_fsl_dma_driver = {
1042         .name = "fsl-elo-dma",
1043         .match_table = of_fsl_dma_ids,
1044         .probe = of_fsl_dma_probe,
1045         .remove = of_fsl_dma_remove,
1046 };
1047
1048 static __init int of_fsl_dma_init(void)
1049 {
1050         int ret;
1051
1052         pr_info("Freescale Elo / Elo Plus DMA driver\n");
1053
1054         ret = of_register_platform_driver(&of_fsl_dma_driver);
1055         if (ret)
1056                 pr_err("fsldma: failed to register platform driver\n");
1057
1058         return ret;
1059 }
1060
1061 static void __exit of_fsl_dma_exit(void)
1062 {
1063         of_unregister_platform_driver(&of_fsl_dma_driver);
1064 }
1065
1066 subsys_initcall(of_fsl_dma_init);
1067 module_exit(of_fsl_dma_exit);
1068
1069 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1070 MODULE_LICENSE("GPL");