drivers/char/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/system.h>
  77 #include <asm/io.h>
  78 #include <asm/irq.h>
  79 #include <asm/dma.h>
  80 #include <asm/types.h>
  81 #include <asm/uaccess.h>
  82
  83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  84 #define SYNCLINK_GENERIC_HDLC 1
  85 #else
  86 #define SYNCLINK_GENERIC_HDLC 0
  87 #endif
  88
  89 /*
  90  * module identification
  91  */
  92 static char *driver_name     = "SyncLink GT";
  93 static char *tty_driver_name = "synclink_gt";
  94 static char *tty_dev_prefix  = "ttySLG";
  95 MODULE_LICENSE("GPL");
  96 #define MGSL_MAGIC 0x5401
  97 #define MAX_DEVICES 32
  98
  99 static struct pci_device_id pci_table[] = {
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {0,}, /* terminate list */
 105 };
 106 MODULE_DEVICE_TABLE(pci, pci_table);
 107
 108 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 109 static void remove_one(struct pci_dev *dev);
 110 static struct pci_driver pci_driver = {
 111         .name           = "synclink_gt",
 112         .id_table       = pci_table,
 113         .probe          = init_one,
 114         .remove         = __devexit_p(remove_one),
 115 };
 116
 117 static bool pci_registered;
 118
 119 /*
 120  * module configuration and status
 121  */
 122 static struct slgt_info *slgt_device_list;
 123 static int slgt_device_count;
 124
 125 static int ttymajor;
 126 static int debug_level;
 127 static int maxframe[MAX_DEVICES];
 128
 129 module_param(ttymajor, int, 0);
 130 module_param(debug_level, int, 0);
 131 module_param_array(maxframe, int, NULL, 0);
 132
 133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 136
 137 /*
 138  * tty support and callbacks
 139  */
 140 static struct tty_driver *serial_driver;
 141
 142 static int  open(struct tty_struct *tty, struct file * filp);
 143 static void close(struct tty_struct *tty, struct file * filp);
 144 static void hangup(struct tty_struct *tty);
 145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 146
 147 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 148 static int put_char(struct tty_struct *tty, unsigned char ch);
 149 static void send_xchar(struct tty_struct *tty, char ch);
 150 static void wait_until_sent(struct tty_struct *tty, int timeout);
 151 static int  write_room(struct tty_struct *tty);
 152 static void flush_chars(struct tty_struct *tty);
 153 static void flush_buffer(struct tty_struct *tty);
 154 static void tx_hold(struct tty_struct *tty);
 155 static void tx_release(struct tty_struct *tty);
 156
 157 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 158 static int  chars_in_buffer(struct tty_struct *tty);
 159 static void throttle(struct tty_struct * tty);
 160 static void unthrottle(struct tty_struct * tty);
 161 static int set_break(struct tty_struct *tty, int break_state);
 162
 163 /*
 164  * generic HDLC support and callbacks
 165  */
 166 #if SYNCLINK_GENERIC_HDLC
 167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 168 static void hdlcdev_tx_done(struct slgt_info *info);
 169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 170 static int  hdlcdev_init(struct slgt_info *info);
 171 static void hdlcdev_exit(struct slgt_info *info);
 172 #endif
 173
 174
 175 /*
 176  * device specific structures, macros and functions
 177  */
 178
 179 #define SLGT_MAX_PORTS 4
 180 #define SLGT_REG_SIZE  256
 181
 182 /*
 183  * conditional wait facility
 184  */
 185 struct cond_wait {
 186         struct cond_wait *next;
 187         wait_queue_head_t q;
 188         wait_queue_t wait;
 189         unsigned int data;
 190 };
 191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 194 static void flush_cond_wait(struct cond_wait **head);
 195
 196 /*
 197  * DMA buffer descriptor and access macros
 198  */
 199 struct slgt_desc
 200 {
 201         __le16 count;
 202         __le16 status;
 203         __le32 pbuf;  /* physical address of data buffer */
 204         __le32 next;  /* physical address of next descriptor */
 205
 206         /* driver book keeping */
 207         char *buf;          /* virtual  address of data buffer */
 208         unsigned int pdesc; /* physical address of this descriptor */
 209         dma_addr_t buf_dma_addr;
 210         unsigned short buf_count;
 211 };
 212
 213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 215 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 216 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 217 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 218 #define desc_count(a)      (le16_to_cpu((a).count))
 219 #define desc_status(a)     (le16_to_cpu((a).status))
 220 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 221 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 222 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 223 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 224 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 225
 226 struct _input_signal_events {
 227         int ri_up;
 228         int ri_down;
 229         int dsr_up;
 230         int dsr_down;
 231         int dcd_up;
 232         int dcd_down;
 233         int cts_up;
 234         int cts_down;
 235 };
 236
 237 /*
 238  * device instance data structure
 239  */
 240 struct slgt_info {
 241         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 242         struct tty_port port;
 243
 244         struct slgt_info *next_device;  /* device list link */
 245
 246         int magic;
 247
 248         char device_name[25];
 249         struct pci_dev *pdev;
 250
 251         int port_count;  /* count of ports on adapter */
 252         int adapter_num; /* adapter instance number */
 253         int port_num;    /* port instance number */
 254
 255         /* array of pointers to port contexts on this adapter */
 256         struct slgt_info *port_array[SLGT_MAX_PORTS];
 257
 258         int                     line;           /* tty line instance number */
 259
 260         struct mgsl_icount      icount;
 261
 262         int                     timeout;
 263         int                     x_char;         /* xon/xoff character */
 264         unsigned int            read_status_mask;
 265         unsigned int            ignore_status_mask;
 266
 267         wait_queue_head_t       status_event_wait_q;
 268         wait_queue_head_t       event_wait_q;
 269         struct timer_list       tx_timer;
 270         struct timer_list       rx_timer;
 271
 272         unsigned int            gpio_present;
 273         struct cond_wait        *gpio_wait_q;
 274
 275         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 276
 277         struct work_struct task;
 278         u32 pending_bh;
 279         bool bh_requested;
 280         bool bh_running;
 281
 282         int isr_overflow;
 283         bool irq_requested;     /* true if IRQ requested */
 284         bool irq_occurred;      /* for diagnostics use */
 285
 286         /* device configuration */
 287
 288         unsigned int bus_type;
 289         unsigned int irq_level;
 290         unsigned long irq_flags;
 291
 292         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 293         u32 phys_reg_addr;
 294         bool reg_addr_requested;
 295
 296         MGSL_PARAMS params;       /* communications parameters */
 297         u32 idle_mode;
 298         u32 max_frame_size;       /* as set by device config */
 299
 300         unsigned int rbuf_fill_level;
 301         unsigned int rx_pio;
 302         unsigned int if_mode;
 303         unsigned int base_clock;
 304         unsigned int xsync;
 305         unsigned int xctrl;
 306
 307         /* device status */
 308
 309         bool rx_enabled;
 310         bool rx_restart;
 311
 312         bool tx_enabled;
 313         bool tx_active;
 314
 315         unsigned char signals;    /* serial signal states */
 316         int init_error;  /* initialization error */
 317
 318         unsigned char *tx_buf;
 319         int tx_count;
 320
 321         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 322         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 323         bool drop_rts_on_tx_done;
 324         struct  _input_signal_events    input_signal_events;
 325
 326         int dcd_chkcount;       /* check counts to prevent */
 327         int cts_chkcount;       /* too many IRQs if a signal */
 328         int dsr_chkcount;       /* is floating */
 329         int ri_chkcount;
 330
 331         char *bufs;             /* virtual address of DMA buffer lists */
 332         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 333
 334         unsigned int rbuf_count;
 335         struct slgt_desc *rbufs;
 336         unsigned int rbuf_current;
 337         unsigned int rbuf_index;
 338         unsigned int rbuf_fill_index;
 339         unsigned short rbuf_fill_count;
 340
 341         unsigned int tbuf_count;
 342         struct slgt_desc *tbufs;
 343         unsigned int tbuf_current;
 344         unsigned int tbuf_start;
 345
 346         unsigned char *tmp_rbuf;
 347         unsigned int tmp_rbuf_count;
 348
 349         /* SPPP/Cisco HDLC device parts */
 350
 351         int netcount;
 352         spinlock_t netlock;
 353 #if SYNCLINK_GENERIC_HDLC
 354         struct net_device *netdev;
 355 #endif
 356
 357 };
 358
 359 static MGSL_PARAMS default_params = {
 360         .mode            = MGSL_MODE_HDLC,
 361         .loopback        = 0,
 362         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 363         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 364         .clock_speed     = 0,
 365         .addr_filter     = 0xff,
 366         .crc_type        = HDLC_CRC_16_CCITT,
 367         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 368         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 369         .data_rate       = 9600,
 370         .data_bits       = 8,
 371         .stop_bits       = 1,
 372         .parity          = ASYNC_PARITY_NONE
 373 };
 374
 375
 376 #define BH_RECEIVE  1
 377 #define BH_TRANSMIT 2
 378 #define BH_STATUS   4
 379 #define IO_PIN_SHUTDOWN_LIMIT 100
 380
 381 #define DMABUFSIZE 256
 382 #define DESC_LIST_SIZE 4096
 383
 384 #define MASK_PARITY  BIT1
 385 #define MASK_FRAMING BIT0
 386 #define MASK_BREAK   BIT14
 387 #define MASK_OVERRUN BIT4
 388
 389 #define GSR   0x00 /* global status */
 390 #define JCR   0x04 /* JTAG control */
 391 #define IODR  0x08 /* GPIO direction */
 392 #define IOER  0x0c /* GPIO interrupt enable */
 393 #define IOVR  0x10 /* GPIO value */
 394 #define IOSR  0x14 /* GPIO interrupt status */
 395 #define TDR   0x80 /* tx data */
 396 #define RDR   0x80 /* rx data */
 397 #define TCR   0x82 /* tx control */
 398 #define TIR   0x84 /* tx idle */
 399 #define TPR   0x85 /* tx preamble */
 400 #define RCR   0x86 /* rx control */
 401 #define VCR   0x88 /* V.24 control */
 402 #define CCR   0x89 /* clock control */
 403 #define BDR   0x8a /* baud divisor */
 404 #define SCR   0x8c /* serial control */
 405 #define SSR   0x8e /* serial status */
 406 #define RDCSR 0x90 /* rx DMA control/status */
 407 #define TDCSR 0x94 /* tx DMA control/status */
 408 #define RDDAR 0x98 /* rx DMA descriptor address */
 409 #define TDDAR 0x9c /* tx DMA descriptor address */
 410 #define XSR   0x40 /* extended sync pattern */
 411 #define XCR   0x44 /* extended control */
 412
 413 #define RXIDLE      BIT14
 414 #define RXBREAK     BIT14
 415 #define IRQ_TXDATA  BIT13
 416 #define IRQ_TXIDLE  BIT12
 417 #define IRQ_TXUNDER BIT11 /* HDLC */
 418 #define IRQ_RXDATA  BIT10
 419 #define IRQ_RXIDLE  BIT9  /* HDLC */
 420 #define IRQ_RXBREAK BIT9  /* async */
 421 #define IRQ_RXOVER  BIT8
 422 #define IRQ_DSR     BIT7
 423 #define IRQ_CTS     BIT6
 424 #define IRQ_DCD     BIT5
 425 #define IRQ_RI      BIT4
 426 #define IRQ_ALL     0x3ff0
 427 #define IRQ_MASTER  BIT0
 428
 429 #define slgt_irq_on(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 431 #define slgt_irq_off(info, mask) \
 432         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 433
 434 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 436 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 438 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 439 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 440
 441 static void  msc_set_vcr(struct slgt_info *info);
 442
 443 static int  startup(struct slgt_info *info);
 444 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 445 static void shutdown(struct slgt_info *info);
 446 static void program_hw(struct slgt_info *info);
 447 static void change_params(struct slgt_info *info);
 448
 449 static int  register_test(struct slgt_info *info);
 450 static int  irq_test(struct slgt_info *info);
 451 static int  loopback_test(struct slgt_info *info);
 452 static int  adapter_test(struct slgt_info *info);
 453
 454 static void reset_adapter(struct slgt_info *info);
 455 static void reset_port(struct slgt_info *info);
 456 static void async_mode(struct slgt_info *info);
 457 static void sync_mode(struct slgt_info *info);
 458
 459 static void rx_stop(struct slgt_info *info);
 460 static void rx_start(struct slgt_info *info);
 461 static void reset_rbufs(struct slgt_info *info);
 462 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 463 static void rdma_reset(struct slgt_info *info);
 464 static bool rx_get_frame(struct slgt_info *info);
 465 static bool rx_get_buf(struct slgt_info *info);
 466
 467 static void tx_start(struct slgt_info *info);
 468 static void tx_stop(struct slgt_info *info);
 469 static void tx_set_idle(struct slgt_info *info);
 470 static unsigned int free_tbuf_count(struct slgt_info *info);
 471 static unsigned int tbuf_bytes(struct slgt_info *info);
 472 static void reset_tbufs(struct slgt_info *info);
 473 static void tdma_reset(struct slgt_info *info);
 474 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 475
 476 static void get_signals(struct slgt_info *info);
 477 static void set_signals(struct slgt_info *info);
 478 static void enable_loopback(struct slgt_info *info);
 479 static void set_rate(struct slgt_info *info, u32 data_rate);
 480
 481 static int  bh_action(struct slgt_info *info);
 482 static void bh_handler(struct work_struct *work);
 483 static void bh_transmit(struct slgt_info *info);
 484 static void isr_serial(struct slgt_info *info);
 485 static void isr_rdma(struct slgt_info *info);
 486 static void isr_txeom(struct slgt_info *info, unsigned short status);
 487 static void isr_tdma(struct slgt_info *info);
 488
 489 static int  alloc_dma_bufs(struct slgt_info *info);
 490 static void free_dma_bufs(struct slgt_info *info);
 491 static int  alloc_desc(struct slgt_info *info);
 492 static void free_desc(struct slgt_info *info);
 493 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 494 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 495
 496 static int  alloc_tmp_rbuf(struct slgt_info *info);
 497 static void free_tmp_rbuf(struct slgt_info *info);
 498
 499 static void tx_timeout(unsigned long context);
 500 static void rx_timeout(unsigned long context);
 501
 502 /*
 503  * ioctl handlers
 504  */
 505 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 506 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 507 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 508 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 509 static int  set_txidle(struct slgt_info *info, int idle_mode);
 510 static int  tx_enable(struct slgt_info *info, int enable);
 511 static int  tx_abort(struct slgt_info *info);
 512 static int  rx_enable(struct slgt_info *info, int enable);
 513 static int  modem_input_wait(struct slgt_info *info,int arg);
 514 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 515 static int  tiocmget(struct tty_struct *tty, struct file *file);
 516 static int  tiocmset(struct tty_struct *tty, struct file *file,
 517                      unsigned int set, unsigned int clear);
 518 static int set_break(struct tty_struct *tty, int break_state);
 519 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 520 static int  set_interface(struct slgt_info *info, int if_mode);
 521 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 523 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 524 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 525 static int  set_xsync(struct slgt_info *info, int if_mode);
 526 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 527 static int  set_xctrl(struct slgt_info *info, int if_mode);
 528
 529 /*
 530  * driver functions
 531  */
 532 static void add_device(struct slgt_info *info);
 533 static void device_init(int adapter_num, struct pci_dev *pdev);
 534 static int  claim_resources(struct slgt_info *info);
 535 static void release_resources(struct slgt_info *info);
 536
 537 /*
 538  * DEBUG OUTPUT CODE
 539  */
 540 #ifndef DBGINFO
 541 #define DBGINFO(fmt)
 542 #endif
 543 #ifndef DBGERR
 544 #define DBGERR(fmt)
 545 #endif
 546 #ifndef DBGBH
 547 #define DBGBH(fmt)
 548 #endif
 549 #ifndef DBGISR
 550 #define DBGISR(fmt)
 551 #endif
 552
 553 #ifdef DBGDATA
 554 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 555 {
 556         int i;
 557         int linecount;
 558         printk("%s %s data:\n",info->device_name, label);
 559         while(count) {
 560                 linecount = (count > 16) ? 16 : count;
 561                 for(i=0; i < linecount; i++)
 562                         printk("%02X ",(unsigned char)data[i]);
 563                 for(;i<17;i++)
 564                         printk("   ");
 565                 for(i=0;i<linecount;i++) {
 566                         if (data[i]>=040 && data[i]<=0176)
 567                                 printk("%c",data[i]);
 568                         else
 569                                 printk(".");
 570                 }
 571                 printk("\n");
 572                 data  += linecount;
 573                 count -= linecount;
 574         }
 575 }
 576 #else
 577 #define DBGDATA(info, buf, size, label)
 578 #endif
 579
 580 #ifdef DBGTBUF
 581 static void dump_tbufs(struct slgt_info *info)
 582 {
 583         int i;
 584         printk("tbuf_current=%d\n", info->tbuf_current);
 585         for (i=0 ; i < info->tbuf_count ; i++) {
 586                 printk("%d: count=%04X status=%04X\n",
 587                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 588         }
 589 }
 590 #else
 591 #define DBGTBUF(info)
 592 #endif
 593
 594 #ifdef DBGRBUF
 595 static void dump_rbufs(struct slgt_info *info)
 596 {
 597         int i;
 598         printk("rbuf_current=%d\n", info->rbuf_current);
 599         for (i=0 ; i < info->rbuf_count ; i++) {
 600                 printk("%d: count=%04X status=%04X\n",
 601                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 602         }
 603 }
 604 #else
 605 #define DBGRBUF(info)
 606 #endif
 607
 608 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 609 {
 610 #ifdef SANITY_CHECK
 611         if (!info) {
 612                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 613                 return 1;
 614         }
 615         if (info->magic != MGSL_MAGIC) {
 616                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 617                 return 1;
 618         }
 619 #else
 620         if (!info)
 621                 return 1;
 622 #endif
 623         return 0;
 624 }
 625
 626 /**
 627  * line discipline callback wrappers
 628  *
 629  * The wrappers maintain line discipline references
 630  * while calling into the line discipline.
 631  *
 632  * ldisc_receive_buf  - pass receive data to line discipline
 633  */
 634 static void ldisc_receive_buf(struct tty_struct *tty,
 635                               const __u8 *data, char *flags, int count)
 636 {
 637         struct tty_ldisc *ld;
 638         if (!tty)
 639                 return;
 640         ld = tty_ldisc_ref(tty);
 641         if (ld) {
 642                 if (ld->ops->receive_buf)
 643                         ld->ops->receive_buf(tty, data, flags, count);
 644                 tty_ldisc_deref(ld);
 645         }
 646 }
 647
 648 /* tty callbacks */
 649
 650 static int open(struct tty_struct *tty, struct file *filp)
 651 {
 652         struct slgt_info *info;
 653         int retval, line;
 654         unsigned long flags;
 655
 656         line = tty->index;
 657         if ((line < 0) || (line >= slgt_device_count)) {
 658                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 659                 return -ENODEV;
 660         }
 661
 662         info = slgt_device_list;
 663         while(info && info->line != line)
 664                 info = info->next_device;
 665         if (sanity_check(info, tty->name, "open"))
 666                 return -ENODEV;
 667         if (info->init_error) {
 668                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 669                 return -ENODEV;
 670         }
 671
 672         tty->driver_data = info;
 673         info->port.tty = tty;
 674
 675         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 676
 677         /* If port is closing, signal caller to try again */
 678         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 679                 if (info->port.flags & ASYNC_CLOSING)
 680                         interruptible_sleep_on(&info->port.close_wait);
 681                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 682                         -EAGAIN : -ERESTARTSYS);
 683                 goto cleanup;
 684         }
 685
 686         mutex_lock(&info->port.mutex);
 687         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 688
 689         spin_lock_irqsave(&info->netlock, flags);
 690         if (info->netcount) {
 691                 retval = -EBUSY;
 692                 spin_unlock_irqrestore(&info->netlock, flags);
 693                 mutex_unlock(&info->port.mutex);
 694                 goto cleanup;
 695         }
 696         info->port.count++;
 697         spin_unlock_irqrestore(&info->netlock, flags);
 698
 699         if (info->port.count == 1) {
 700                 /* 1st open on this device, init hardware */
 701                 retval = startup(info);
 702                 if (retval < 0) {
 703                         mutex_unlock(&info->port.mutex);
 704                         goto cleanup;
 705                 }
 706         }
 707         mutex_unlock(&info->port.mutex);
 708         retval = block_til_ready(tty, filp, info);
 709         if (retval) {
 710                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 711                 goto cleanup;
 712         }
 713
 714         retval = 0;
 715
 716 cleanup:
 717         if (retval) {
 718                 if (tty->count == 1)
 719                         info->port.tty = NULL; /* tty layer will release tty struct */
 720                 if(info->port.count)
 721                         info->port.count--;
 722         }
 723
 724         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 725         return retval;
 726 }
 727
 728 static void close(struct tty_struct *tty, struct file *filp)
 729 {
 730         struct slgt_info *info = tty->driver_data;
 731
 732         if (sanity_check(info, tty->name, "close"))
 733                 return;
 734         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 735
 736         if (tty_port_close_start(&info->port, tty, filp) == 0)
 737                 goto cleanup;
 738
 739         mutex_lock(&info->port.mutex);
 740         if (info->port.flags & ASYNC_INITIALIZED)
 741                 wait_until_sent(tty, info->timeout);
 742         flush_buffer(tty);
 743         tty_ldisc_flush(tty);
 744
 745         shutdown(info);
 746         mutex_unlock(&info->port.mutex);
 747
 748         tty_port_close_end(&info->port, tty);
 749         info->port.tty = NULL;
 750 cleanup:
 751         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 752 }
 753
 754 static void hangup(struct tty_struct *tty)
 755 {
 756         struct slgt_info *info = tty->driver_data;
 757         unsigned long flags;
 758
 759         if (sanity_check(info, tty->name, "hangup"))
 760                 return;
 761         DBGINFO(("%s hangup\n", info->device_name));
 762
 763         flush_buffer(tty);
 764
 765         mutex_lock(&info->port.mutex);
 766         shutdown(info);
 767
 768         spin_lock_irqsave(&info->port.lock, flags);
 769         info->port.count = 0;
 770         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 771         info->port.tty = NULL;
 772         spin_unlock_irqrestore(&info->port.lock, flags);
 773         mutex_unlock(&info->port.mutex);
 774
 775         wake_up_interruptible(&info->port.open_wait);
 776 }
 777
 778 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 779 {
 780         struct slgt_info *info = tty->driver_data;
 781         unsigned long flags;
 782
 783         DBGINFO(("%s set_termios\n", tty->driver->name));
 784
 785         change_params(info);
 786
 787         /* Handle transition to B0 status */
 788         if (old_termios->c_cflag & CBAUD &&
 789             !(tty->termios->c_cflag & CBAUD)) {
 790                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 791                 spin_lock_irqsave(&info->lock,flags);
 792                 set_signals(info);
 793                 spin_unlock_irqrestore(&info->lock,flags);
 794         }
 795
 796         /* Handle transition away from B0 status */
 797         if (!(old_termios->c_cflag & CBAUD) &&
 798             tty->termios->c_cflag & CBAUD) {
 799                 info->signals |= SerialSignal_DTR;
 800                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 801                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 802                         info->signals |= SerialSignal_RTS;
 803                 }
 804                 spin_lock_irqsave(&info->lock,flags);
 805                 set_signals(info);
 806                 spin_unlock_irqrestore(&info->lock,flags);
 807         }
 808
 809         /* Handle turning off CRTSCTS */
 810         if (old_termios->c_cflag & CRTSCTS &&
 811             !(tty->termios->c_cflag & CRTSCTS)) {
 812                 tty->hw_stopped = 0;
 813                 tx_release(tty);
 814         }
 815 }
 816
 817 static void update_tx_timer(struct slgt_info *info)
 818 {
 819         /*
 820          * use worst case speed of 1200bps to calculate transmit timeout
 821          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 822          */
 823         if (info->params.mode == MGSL_MODE_HDLC) {
 824                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 825                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 826         }
 827 }
 828
 829 static int write(struct tty_struct *tty,
 830                  const unsigned char *buf, int count)
 831 {
 832         int ret = 0;
 833         struct slgt_info *info = tty->driver_data;
 834         unsigned long flags;
 835
 836         if (sanity_check(info, tty->name, "write"))
 837                 return -EIO;
 838
 839         DBGINFO(("%s write count=%d\n", info->device_name, count));
 840
 841         if (!info->tx_buf || (count > info->max_frame_size))
 842                 return -EIO;
 843
 844         if (!count || tty->stopped || tty->hw_stopped)
 845                 return 0;
 846
 847         spin_lock_irqsave(&info->lock, flags);
 848
 849         if (info->tx_count) {
 850                 /* send accumulated data from send_char() */
 851                 if (!tx_load(info, info->tx_buf, info->tx_count))
 852                         goto cleanup;
 853                 info->tx_count = 0;
 854         }
 855
 856         if (tx_load(info, buf, count))
 857                 ret = count;
 858
 859 cleanup:
 860         spin_unlock_irqrestore(&info->lock, flags);
 861         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 862         return ret;
 863 }
 864
 865 static int put_char(struct tty_struct *tty, unsigned char ch)
 866 {
 867         struct slgt_info *info = tty->driver_data;
 868         unsigned long flags;
 869         int ret = 0;
 870
 871         if (sanity_check(info, tty->name, "put_char"))
 872                 return 0;
 873         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 874         if (!info->tx_buf)
 875                 return 0;
 876         spin_lock_irqsave(&info->lock,flags);
 877         if (info->tx_count < info->max_frame_size) {
 878                 info->tx_buf[info->tx_count++] = ch;
 879                 ret = 1;
 880         }
 881         spin_unlock_irqrestore(&info->lock,flags);
 882         return ret;
 883 }
 884
 885 static void send_xchar(struct tty_struct *tty, char ch)
 886 {
 887         struct slgt_info *info = tty->driver_data;
 888         unsigned long flags;
 889
 890         if (sanity_check(info, tty->name, "send_xchar"))
 891                 return;
 892         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 893         info->x_char = ch;
 894         if (ch) {
 895                 spin_lock_irqsave(&info->lock,flags);
 896                 if (!info->tx_enabled)
 897                         tx_start(info);
 898                 spin_unlock_irqrestore(&info->lock,flags);
 899         }
 900 }
 901
 902 static void wait_until_sent(struct tty_struct *tty, int timeout)
 903 {
 904         struct slgt_info *info = tty->driver_data;
 905         unsigned long orig_jiffies, char_time;
 906
 907         if (!info )
 908                 return;
 909         if (sanity_check(info, tty->name, "wait_until_sent"))
 910                 return;
 911         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 912         if (!(info->port.flags & ASYNC_INITIALIZED))
 913                 goto exit;
 914
 915         orig_jiffies = jiffies;
 916
 917         /* Set check interval to 1/5 of estimated time to
 918          * send a character, and make it at least 1. The check
 919          * interval should also be less than the timeout.
 920          * Note: use tight timings here to satisfy the NIST-PCTS.
 921          */
 922
 923         if (info->params.data_rate) {
 924                 char_time = info->timeout/(32 * 5);
 925                 if (!char_time)
 926                         char_time++;
 927         } else
 928                 char_time = 1;
 929
 930         if (timeout)
 931                 char_time = min_t(unsigned long, char_time, timeout);
 932
 933         while (info->tx_active) {
 934                 msleep_interruptible(jiffies_to_msecs(char_time));
 935                 if (signal_pending(current))
 936                         break;
 937                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 938                         break;
 939         }
 940 exit:
 941         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 942 }
 943
 944 static int write_room(struct tty_struct *tty)
 945 {
 946         struct slgt_info *info = tty->driver_data;
 947         int ret;
 948
 949         if (sanity_check(info, tty->name, "write_room"))
 950                 return 0;
 951         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 952         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 953         return ret;
 954 }
 955
 956 static void flush_chars(struct tty_struct *tty)
 957 {
 958         struct slgt_info *info = tty->driver_data;
 959         unsigned long flags;
 960
 961         if (sanity_check(info, tty->name, "flush_chars"))
 962                 return;
 963         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 964
 965         if (info->tx_count <= 0 || tty->stopped ||
 966             tty->hw_stopped || !info->tx_buf)
 967                 return;
 968
 969         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 970
 971         spin_lock_irqsave(&info->lock,flags);
 972         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 973                 info->tx_count = 0;
 974         spin_unlock_irqrestore(&info->lock,flags);
 975 }
 976
 977 static void flush_buffer(struct tty_struct *tty)
 978 {
 979         struct slgt_info *info = tty->driver_data;
 980         unsigned long flags;
 981
 982         if (sanity_check(info, tty->name, "flush_buffer"))
 983                 return;
 984         DBGINFO(("%s flush_buffer\n", info->device_name));
 985
 986         spin_lock_irqsave(&info->lock, flags);
 987         info->tx_count = 0;
 988         spin_unlock_irqrestore(&info->lock, flags);
 989
 990         tty_wakeup(tty);
 991 }
 992
 993 /*
 994  * throttle (stop) transmitter
 995  */
 996 static void tx_hold(struct tty_struct *tty)
 997 {
 998         struct slgt_info *info = tty->driver_data;
 999         unsigned long flags;
1000
1001         if (sanity_check(info, tty->name, "tx_hold"))
1002                 return;
1003         DBGINFO(("%s tx_hold\n", info->device_name));
1004         spin_lock_irqsave(&info->lock,flags);
1005         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1006                 tx_stop(info);
1007         spin_unlock_irqrestore(&info->lock,flags);
1008 }
1009
1010 /*
1011  * release (start) transmitter
1012  */
1013 static void tx_release(struct tty_struct *tty)
1014 {
1015         struct slgt_info *info = tty->driver_data;
1016         unsigned long flags;
1017
1018         if (sanity_check(info, tty->name, "tx_release"))
1019                 return;
1020         DBGINFO(("%s tx_release\n", info->device_name));
1021         spin_lock_irqsave(&info->lock, flags);
1022         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1023                 info->tx_count = 0;
1024         spin_unlock_irqrestore(&info->lock, flags);
1025 }
1026
1027 /*
1028  * Service an IOCTL request
1029  *
1030  * Arguments
1031  *
1032  *      tty     pointer to tty instance data
1033  *      file    pointer to associated file object for device
1034  *      cmd     IOCTL command code
1035  *      arg     command argument/context
1036  *
1037  * Return 0 if success, otherwise error code
1038  */
1039 static int ioctl(struct tty_struct *tty, struct file *file,
1040                  unsigned int cmd, unsigned long arg)
1041 {
1042         struct slgt_info *info = tty->driver_data;
1043         void __user *argp = (void __user *)arg;
1044         int ret;
1045
1046         if (sanity_check(info, tty->name, "ioctl"))
1047                 return -ENODEV;
1048         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1049
1050         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1051             (cmd != TIOCMIWAIT)) {
1052                 if (tty->flags & (1 << TTY_IO_ERROR))
1053                     return -EIO;
1054         }
1055
1056         switch (cmd) {
1057         case MGSL_IOCWAITEVENT:
1058                 return wait_mgsl_event(info, argp);
1059         case TIOCMIWAIT:
1060                 return modem_input_wait(info,(int)arg);
1061         case MGSL_IOCSGPIO:
1062                 return set_gpio(info, argp);
1063         case MGSL_IOCGGPIO:
1064                 return get_gpio(info, argp);
1065         case MGSL_IOCWAITGPIO:
1066                 return wait_gpio(info, argp);
1067         case MGSL_IOCGXSYNC:
1068                 return get_xsync(info, argp);
1069         case MGSL_IOCSXSYNC:
1070                 return set_xsync(info, (int)arg);
1071         case MGSL_IOCGXCTRL:
1072                 return get_xctrl(info, argp);
1073         case MGSL_IOCSXCTRL:
1074                 return set_xctrl(info, (int)arg);
1075         }
1076         mutex_lock(&info->port.mutex);
1077         switch (cmd) {
1078         case MGSL_IOCGPARAMS:
1079                 ret = get_params(info, argp);
1080                 break;
1081         case MGSL_IOCSPARAMS:
1082                 ret = set_params(info, argp);
1083                 break;
1084         case MGSL_IOCGTXIDLE:
1085                 ret = get_txidle(info, argp);
1086                 break;
1087         case MGSL_IOCSTXIDLE:
1088                 ret = set_txidle(info, (int)arg);
1089                 break;
1090         case MGSL_IOCTXENABLE:
1091                 ret = tx_enable(info, (int)arg);
1092                 break;
1093         case MGSL_IOCRXENABLE:
1094                 ret = rx_enable(info, (int)arg);
1095                 break;
1096         case MGSL_IOCTXABORT:
1097                 ret = tx_abort(info);
1098                 break;
1099         case MGSL_IOCGSTATS:
1100                 ret = get_stats(info, argp);
1101                 break;
1102         case MGSL_IOCGIF:
1103                 ret = get_interface(info, argp);
1104                 break;
1105         case MGSL_IOCSIF:
1106                 ret = set_interface(info,(int)arg);
1107                 break;
1108         default:
1109                 ret = -ENOIOCTLCMD;
1110         }
1111         mutex_unlock(&info->port.mutex);
1112         return ret;
1113 }
1114
1115 static int get_icount(struct tty_struct *tty,
1116                                 struct serial_icounter_struct *icount)
1117
1118 {
1119         struct slgt_info *info = tty->driver_data;
1120         struct mgsl_icount cnow;        /* kernel counter temps */
1121         unsigned long flags;
1122
1123         spin_lock_irqsave(&info->lock,flags);
1124         cnow = info->icount;
1125         spin_unlock_irqrestore(&info->lock,flags);
1126
1127         icount->cts = cnow.cts;
1128         icount->dsr = cnow.dsr;
1129         icount->rng = cnow.rng;
1130         icount->dcd = cnow.dcd;
1131         icount->rx = cnow.rx;
1132         icount->tx = cnow.tx;
1133         icount->frame = cnow.frame;
1134         icount->overrun = cnow.overrun;
1135         icount->parity = cnow.parity;
1136         icount->brk = cnow.brk;
1137         icount->buf_overrun = cnow.buf_overrun;
1138
1139         return 0;
1140 }
1141
1142 /*
1143  * support for 32 bit ioctl calls on 64 bit systems
1144  */
1145 #ifdef CONFIG_COMPAT
1146 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1147 {
1148         struct MGSL_PARAMS32 tmp_params;
1149
1150         DBGINFO(("%s get_params32\n", info->device_name));
1151         memset(&tmp_params, 0, sizeof(tmp_params));
1152         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1153         tmp_params.loopback        = info->params.loopback;
1154         tmp_params.flags           = info->params.flags;
1155         tmp_params.encoding        = info->params.encoding;
1156         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1157         tmp_params.addr_filter     = info->params.addr_filter;
1158         tmp_params.crc_type        = info->params.crc_type;
1159         tmp_params.preamble_length = info->params.preamble_length;
1160         tmp_params.preamble        = info->params.preamble;
1161         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1162         tmp_params.data_bits       = info->params.data_bits;
1163         tmp_params.stop_bits       = info->params.stop_bits;
1164         tmp_params.parity          = info->params.parity;
1165         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1166                 return -EFAULT;
1167         return 0;
1168 }
1169
1170 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1171 {
1172         struct MGSL_PARAMS32 tmp_params;
1173
1174         DBGINFO(("%s set_params32\n", info->device_name));
1175         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1176                 return -EFAULT;
1177
1178         spin_lock(&info->lock);
1179         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1180                 info->base_clock = tmp_params.clock_speed;
1181         } else {
1182                 info->params.mode            = tmp_params.mode;
1183                 info->params.loopback        = tmp_params.loopback;
1184                 info->params.flags           = tmp_params.flags;
1185                 info->params.encoding        = tmp_params.encoding;
1186                 info->params.clock_speed     = tmp_params.clock_speed;
1187                 info->params.addr_filter     = tmp_params.addr_filter;
1188                 info->params.crc_type        = tmp_params.crc_type;
1189                 info->params.preamble_length = tmp_params.preamble_length;
1190                 info->params.preamble        = tmp_params.preamble;
1191                 info->params.data_rate       = tmp_params.data_rate;
1192                 info->params.data_bits       = tmp_params.data_bits;
1193                 info->params.stop_bits       = tmp_params.stop_bits;
1194                 info->params.parity          = tmp_params.parity;
1195         }
1196         spin_unlock(&info->lock);
1197
1198         program_hw(info);
1199
1200         return 0;
1201 }
1202
1203 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1204                          unsigned int cmd, unsigned long arg)
1205 {
1206         struct slgt_info *info = tty->driver_data;
1207         int rc = -ENOIOCTLCMD;
1208
1209         if (sanity_check(info, tty->name, "compat_ioctl"))
1210                 return -ENODEV;
1211         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1212
1213         switch (cmd) {
1214
1215         case MGSL_IOCSPARAMS32:
1216                 rc = set_params32(info, compat_ptr(arg));
1217                 break;
1218
1219         case MGSL_IOCGPARAMS32:
1220                 rc = get_params32(info, compat_ptr(arg));
1221                 break;
1222
1223         case MGSL_IOCGPARAMS:
1224         case MGSL_IOCSPARAMS:
1225         case MGSL_IOCGTXIDLE:
1226         case MGSL_IOCGSTATS:
1227         case MGSL_IOCWAITEVENT:
1228         case MGSL_IOCGIF:
1229         case MGSL_IOCSGPIO:
1230         case MGSL_IOCGGPIO:
1231         case MGSL_IOCWAITGPIO:
1232         case MGSL_IOCGXSYNC:
1233         case MGSL_IOCGXCTRL:
1234         case MGSL_IOCSTXIDLE:
1235         case MGSL_IOCTXENABLE:
1236         case MGSL_IOCRXENABLE:
1237         case MGSL_IOCTXABORT:
1238         case TIOCMIWAIT:
1239         case MGSL_IOCSIF:
1240         case MGSL_IOCSXSYNC:
1241         case MGSL_IOCSXCTRL:
1242                 rc = ioctl(tty, file, cmd, arg);
1243                 break;
1244         }
1245
1246         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1247         return rc;
1248 }
1249 #else
1250 #define slgt_compat_ioctl NULL
1251 #endif /* ifdef CONFIG_COMPAT */
1252
1253 /*
1254  * proc fs support
1255  */
1256 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1257 {
1258         char stat_buf[30];
1259         unsigned long flags;
1260
1261         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1262                       info->device_name, info->phys_reg_addr,
1263                       info->irq_level, info->max_frame_size);
1264
1265         /* output current serial signal states */
1266         spin_lock_irqsave(&info->lock,flags);
1267         get_signals(info);
1268         spin_unlock_irqrestore(&info->lock,flags);
1269
1270         stat_buf[0] = 0;
1271         stat_buf[1] = 0;
1272         if (info->signals & SerialSignal_RTS)
1273                 strcat(stat_buf, "|RTS");
1274         if (info->signals & SerialSignal_CTS)
1275                 strcat(stat_buf, "|CTS");
1276         if (info->signals & SerialSignal_DTR)
1277                 strcat(stat_buf, "|DTR");
1278         if (info->signals & SerialSignal_DSR)
1279                 strcat(stat_buf, "|DSR");
1280         if (info->signals & SerialSignal_DCD)
1281                 strcat(stat_buf, "|CD");
1282         if (info->signals & SerialSignal_RI)
1283                 strcat(stat_buf, "|RI");
1284
1285         if (info->params.mode != MGSL_MODE_ASYNC) {
1286                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1287                                info->icount.txok, info->icount.rxok);
1288                 if (info->icount.txunder)
1289                         seq_printf(m, " txunder:%d", info->icount.txunder);
1290                 if (info->icount.txabort)
1291                         seq_printf(m, " txabort:%d", info->icount.txabort);
1292                 if (info->icount.rxshort)
1293                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1294                 if (info->icount.rxlong)
1295                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1296                 if (info->icount.rxover)
1297                         seq_printf(m, " rxover:%d", info->icount.rxover);
1298                 if (info->icount.rxcrc)
1299                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1300         } else {
1301                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1302                                info->icount.tx, info->icount.rx);
1303                 if (info->icount.frame)
1304                         seq_printf(m, " fe:%d", info->icount.frame);
1305                 if (info->icount.parity)
1306                         seq_printf(m, " pe:%d", info->icount.parity);
1307                 if (info->icount.brk)
1308                         seq_printf(m, " brk:%d", info->icount.brk);
1309                 if (info->icount.overrun)
1310                         seq_printf(m, " oe:%d", info->icount.overrun);
1311         }
1312
1313         /* Append serial signal status to end */
1314         seq_printf(m, " %s\n", stat_buf+1);
1315
1316         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1317                        info->tx_active,info->bh_requested,info->bh_running,
1318                        info->pending_bh);
1319 }
1320
1321 /* Called to print information about devices
1322  */
1323 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1324 {
1325         struct slgt_info *info;
1326
1327         seq_puts(m, "synclink_gt driver\n");
1328
1329         info = slgt_device_list;
1330         while( info ) {
1331                 line_info(m, info);
1332                 info = info->next_device;
1333         }
1334         return 0;
1335 }
1336
1337 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1338 {
1339         return single_open(file, synclink_gt_proc_show, NULL);
1340 }
1341
1342 static const struct file_operations synclink_gt_proc_fops = {
1343         .owner          = THIS_MODULE,
1344         .open           = synclink_gt_proc_open,
1345         .read           = seq_read,
1346         .llseek         = seq_lseek,
1347         .release        = single_release,
1348 };
1349
1350 /*
1351  * return count of bytes in transmit buffer
1352  */
1353 static int chars_in_buffer(struct tty_struct *tty)
1354 {
1355         struct slgt_info *info = tty->driver_data;
1356         int count;
1357         if (sanity_check(info, tty->name, "chars_in_buffer"))
1358                 return 0;
1359         count = tbuf_bytes(info);
1360         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1361         return count;
1362 }
1363
1364 /*
1365  * signal remote device to throttle send data (our receive data)
1366  */
1367 static void throttle(struct tty_struct * tty)
1368 {
1369         struct slgt_info *info = tty->driver_data;
1370         unsigned long flags;
1371
1372         if (sanity_check(info, tty->name, "throttle"))
1373                 return;
1374         DBGINFO(("%s throttle\n", info->device_name));
1375         if (I_IXOFF(tty))
1376                 send_xchar(tty, STOP_CHAR(tty));
1377         if (tty->termios->c_cflag & CRTSCTS) {
1378                 spin_lock_irqsave(&info->lock,flags);
1379                 info->signals &= ~SerialSignal_RTS;
1380                 set_signals(info);
1381                 spin_unlock_irqrestore(&info->lock,flags);
1382         }
1383 }
1384
1385 /*
1386  * signal remote device to stop throttling send data (our receive data)
1387  */
1388 static void unthrottle(struct tty_struct * tty)
1389 {
1390         struct slgt_info *info = tty->driver_data;
1391         unsigned long flags;
1392
1393         if (sanity_check(info, tty->name, "unthrottle"))
1394                 return;
1395         DBGINFO(("%s unthrottle\n", info->device_name));
1396         if (I_IXOFF(tty)) {
1397                 if (info->x_char)
1398                         info->x_char = 0;
1399                 else
1400                         send_xchar(tty, START_CHAR(tty));
1401         }
1402         if (tty->termios->c_cflag & CRTSCTS) {
1403                 spin_lock_irqsave(&info->lock,flags);
1404                 info->signals |= SerialSignal_RTS;
1405                 set_signals(info);
1406                 spin_unlock_irqrestore(&info->lock,flags);
1407         }
1408 }
1409
1410 /*
1411  * set or clear transmit break condition
1412  * break_state  -1=set break condition, 0=clear
1413  */
1414 static int set_break(struct tty_struct *tty, int break_state)
1415 {
1416         struct slgt_info *info = tty->driver_data;
1417         unsigned short value;
1418         unsigned long flags;
1419
1420         if (sanity_check(info, tty->name, "set_break"))
1421                 return -EINVAL;
1422         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1423
1424         spin_lock_irqsave(&info->lock,flags);
1425         value = rd_reg16(info, TCR);
1426         if (break_state == -1)
1427                 value |= BIT6;
1428         else
1429                 value &= ~BIT6;
1430         wr_reg16(info, TCR, value);
1431         spin_unlock_irqrestore(&info->lock,flags);
1432         return 0;
1433 }
1434
1435 #if SYNCLINK_GENERIC_HDLC
1436
1437 /**
1438  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1439  * set encoding and frame check sequence (FCS) options
1440  *
1441  * dev       pointer to network device structure
1442  * encoding  serial encoding setting
1443  * parity    FCS setting
1444  *
1445  * returns 0 if success, otherwise error code
1446  */
1447 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1448                           unsigned short parity)
1449 {
1450         struct slgt_info *info = dev_to_port(dev);
1451         unsigned char  new_encoding;
1452         unsigned short new_crctype;
1453
1454         /* return error if TTY interface open */
1455         if (info->port.count)
1456                 return -EBUSY;
1457
1458         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1459
1460         switch (encoding)
1461         {
1462         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1463         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1464         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1465         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1466         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1467         default: return -EINVAL;
1468         }
1469
1470         switch (parity)
1471         {
1472         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1473         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1474         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1475         default: return -EINVAL;
1476         }
1477
1478         info->params.encoding = new_encoding;
1479         info->params.crc_type = new_crctype;
1480
1481         /* if network interface up, reprogram hardware */
1482         if (info->netcount)
1483                 program_hw(info);
1484
1485         return 0;
1486 }
1487
1488 /**
1489  * called by generic HDLC layer to send frame
1490  *
1491  * skb  socket buffer containing HDLC frame
1492  * dev  pointer to network device structure
1493  */
1494 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1495                                       struct net_device *dev)
1496 {
1497         struct slgt_info *info = dev_to_port(dev);
1498         unsigned long flags;
1499
1500         DBGINFO(("%s hdlc_xmit\n", dev->name));
1501
1502         if (!skb->len)
1503                 return NETDEV_TX_OK;
1504
1505         /* stop sending until this frame completes */
1506         netif_stop_queue(dev);
1507
1508         /* update network statistics */
1509         dev->stats.tx_packets++;
1510         dev->stats.tx_bytes += skb->len;
1511
1512         /* save start time for transmit timeout detection */
1513         dev->trans_start = jiffies;
1514
1515         spin_lock_irqsave(&info->lock, flags);
1516         tx_load(info, skb->data, skb->len);
1517         spin_unlock_irqrestore(&info->lock, flags);
1518
1519         /* done with socket buffer, so free it */
1520         dev_kfree_skb(skb);
1521
1522         return NETDEV_TX_OK;
1523 }
1524
1525 /**
1526  * called by network layer when interface enabled
1527  * claim resources and initialize hardware
1528  *
1529  * dev  pointer to network device structure
1530  *
1531  * returns 0 if success, otherwise error code
1532  */
1533 static int hdlcdev_open(struct net_device *dev)
1534 {
1535         struct slgt_info *info = dev_to_port(dev);
1536         int rc;
1537         unsigned long flags;
1538
1539         if (!try_module_get(THIS_MODULE))
1540                 return -EBUSY;
1541
1542         DBGINFO(("%s hdlcdev_open\n", dev->name));
1543
1544         /* generic HDLC layer open processing */
1545         if ((rc = hdlc_open(dev)))
1546                 return rc;
1547
1548         /* arbitrate between network and tty opens */
1549         spin_lock_irqsave(&info->netlock, flags);
1550         if (info->port.count != 0 || info->netcount != 0) {
1551                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1552                 spin_unlock_irqrestore(&info->netlock, flags);
1553                 return -EBUSY;
1554         }
1555         info->netcount=1;
1556         spin_unlock_irqrestore(&info->netlock, flags);
1557
1558         /* claim resources and init adapter */
1559         if ((rc = startup(info)) != 0) {
1560                 spin_lock_irqsave(&info->netlock, flags);
1561                 info->netcount=0;
1562                 spin_unlock_irqrestore(&info->netlock, flags);
1563                 return rc;
1564         }
1565
1566         /* assert DTR and RTS, apply hardware settings */
1567         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1568         program_hw(info);
1569
1570         /* enable network layer transmit */
1571         dev->trans_start = jiffies;
1572         netif_start_queue(dev);
1573
1574         /* inform generic HDLC layer of current DCD status */
1575         spin_lock_irqsave(&info->lock, flags);
1576         get_signals(info);
1577         spin_unlock_irqrestore(&info->lock, flags);
1578         if (info->signals & SerialSignal_DCD)
1579                 netif_carrier_on(dev);
1580         else
1581                 netif_carrier_off(dev);
1582         return 0;
1583 }
1584
1585 /**
1586  * called by network layer when interface is disabled
1587  * shutdown hardware and release resources
1588  *
1589  * dev  pointer to network device structure
1590  *
1591  * returns 0 if success, otherwise error code
1592  */
1593 static int hdlcdev_close(struct net_device *dev)
1594 {
1595         struct slgt_info *info = dev_to_port(dev);
1596         unsigned long flags;
1597
1598         DBGINFO(("%s hdlcdev_close\n", dev->name));
1599
1600         netif_stop_queue(dev);
1601
1602         /* shutdown adapter and release resources */
1603         shutdown(info);
1604
1605         hdlc_close(dev);
1606
1607         spin_lock_irqsave(&info->netlock, flags);
1608         info->netcount=0;
1609         spin_unlock_irqrestore(&info->netlock, flags);
1610
1611         module_put(THIS_MODULE);
1612         return 0;
1613 }
1614
1615 /**
1616  * called by network layer to process IOCTL call to network device
1617  *
1618  * dev  pointer to network device structure
1619  * ifr  pointer to network interface request structure
1620  * cmd  IOCTL command code
1621  *
1622  * returns 0 if success, otherwise error code
1623  */
1624 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1625 {
1626         const size_t size = sizeof(sync_serial_settings);
1627         sync_serial_settings new_line;
1628         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1629         struct slgt_info *info = dev_to_port(dev);
1630         unsigned int flags;
1631
1632         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1633
1634         /* return error if TTY interface open */
1635         if (info->port.count)
1636                 return -EBUSY;
1637
1638         if (cmd != SIOCWANDEV)
1639                 return hdlc_ioctl(dev, ifr, cmd);
1640
1641         memset(&new_line, 0, sizeof(new_line));
1642
1643         switch(ifr->ifr_settings.type) {
1644         case IF_GET_IFACE: /* return current sync_serial_settings */
1645
1646                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1647                 if (ifr->ifr_settings.size < size) {
1648                         ifr->ifr_settings.size = size; /* data size wanted */
1649                         return -ENOBUFS;
1650                 }
1651
1652                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1653                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1654                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1655                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1656
1657                 switch (flags){
1658                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1659                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1660                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1661                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1662                 default: new_line.clock_type = CLOCK_DEFAULT;
1663                 }
1664
1665                 new_line.clock_rate = info->params.clock_speed;
1666                 new_line.loopback   = info->params.loopback ? 1:0;
1667
1668                 if (copy_to_user(line, &new_line, size))
1669                         return -EFAULT;
1670                 return 0;
1671
1672         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1673
1674                 if(!capable(CAP_NET_ADMIN))
1675                         return -EPERM;
1676                 if (copy_from_user(&new_line, line, size))
1677                         return -EFAULT;
1678
1679                 switch (new_line.clock_type)
1680                 {
1681                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1682                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1683                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1684                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1685                 case CLOCK_DEFAULT:  flags = info->params.flags &
1686                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1687                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1688                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1689                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1690                 default: return -EINVAL;
1691                 }
1692
1693                 if (new_line.loopback != 0 && new_line.loopback != 1)
1694                         return -EINVAL;
1695
1696                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1697                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1698                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1699                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1700                 info->params.flags |= flags;
1701
1702                 info->params.loopback = new_line.loopback;
1703
1704                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1705                         info->params.clock_speed = new_line.clock_rate;
1706                 else
1707                         info->params.clock_speed = 0;
1708
1709                 /* if network interface up, reprogram hardware */
1710                 if (info->netcount)
1711                         program_hw(info);
1712                 return 0;
1713
1714         default:
1715                 return hdlc_ioctl(dev, ifr, cmd);
1716         }
1717 }
1718
1719 /**
1720  * called by network layer when transmit timeout is detected
1721  *
1722  * dev  pointer to network device structure
1723  */
1724 static void hdlcdev_tx_timeout(struct net_device *dev)
1725 {
1726         struct slgt_info *info = dev_to_port(dev);
1727         unsigned long flags;
1728
1729         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1730
1731         dev->stats.tx_errors++;
1732         dev->stats.tx_aborted_errors++;
1733
1734         spin_lock_irqsave(&info->lock,flags);
1735         tx_stop(info);
1736         spin_unlock_irqrestore(&info->lock,flags);
1737
1738         netif_wake_queue(dev);
1739 }
1740
1741 /**
1742  * called by device driver when transmit completes
1743  * reenable network layer transmit if stopped
1744  *
1745  * info  pointer to device instance information
1746  */
1747 static void hdlcdev_tx_done(struct slgt_info *info)
1748 {
1749         if (netif_queue_stopped(info->netdev))
1750                 netif_wake_queue(info->netdev);
1751 }
1752
1753 /**
1754  * called by device driver when frame received
1755  * pass frame to network layer
1756  *
1757  * info  pointer to device instance information
1758  * buf   pointer to buffer contianing frame data
1759  * size  count of data bytes in buf
1760  */
1761 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1762 {
1763         struct sk_buff *skb = dev_alloc_skb(size);
1764         struct net_device *dev = info->netdev;
1765
1766         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1767
1768         if (skb == NULL) {
1769                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1770                 dev->stats.rx_dropped++;
1771                 return;
1772         }
1773
1774         memcpy(skb_put(skb, size), buf, size);
1775
1776         skb->protocol = hdlc_type_trans(skb, dev);
1777
1778         dev->stats.rx_packets++;
1779         dev->stats.rx_bytes += size;
1780
1781         netif_rx(skb);
1782 }
1783
1784 static const struct net_device_ops hdlcdev_ops = {
1785         .ndo_open       = hdlcdev_open,
1786         .ndo_stop       = hdlcdev_close,
1787         .ndo_change_mtu = hdlc_change_mtu,
1788         .ndo_start_xmit = hdlc_start_xmit,
1789         .ndo_do_ioctl   = hdlcdev_ioctl,
1790         .ndo_tx_timeout = hdlcdev_tx_timeout,
1791 };
1792
1793 /**
1794  * called by device driver when adding device instance
1795  * do generic HDLC initialization
1796  *
1797  * info  pointer to device instance information
1798  *
1799  * returns 0 if success, otherwise error code
1800  */
1801 static int hdlcdev_init(struct slgt_info *info)
1802 {
1803         int rc;
1804         struct net_device *dev;
1805         hdlc_device *hdlc;
1806
1807         /* allocate and initialize network and HDLC layer objects */
1808
1809         if (!(dev = alloc_hdlcdev(info))) {
1810                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1811                 return -ENOMEM;
1812         }
1813
1814         /* for network layer reporting purposes only */
1815         dev->mem_start = info->phys_reg_addr;
1816         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1817         dev->irq       = info->irq_level;
1818
1819         /* network layer callbacks and settings */
1820         dev->netdev_ops     = &hdlcdev_ops;
1821         dev->watchdog_timeo = 10 * HZ;
1822         dev->tx_queue_len   = 50;
1823
1824         /* generic HDLC layer callbacks and settings */
1825         hdlc         = dev_to_hdlc(dev);
1826         hdlc->attach = hdlcdev_attach;
1827         hdlc->xmit   = hdlcdev_xmit;
1828
1829         /* register objects with HDLC layer */
1830         if ((rc = register_hdlc_device(dev))) {
1831                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1832                 free_netdev(dev);
1833                 return rc;
1834         }
1835
1836         info->netdev = dev;
1837         return 0;
1838 }
1839
1840 /**
1841  * called by device driver when removing device instance
1842  * do generic HDLC cleanup
1843  *
1844  * info  pointer to device instance information
1845  */
1846 static void hdlcdev_exit(struct slgt_info *info)
1847 {
1848         unregister_hdlc_device(info->netdev);
1849         free_netdev(info->netdev);
1850         info->netdev = NULL;
1851 }
1852
1853 #endif /* ifdef CONFIG_HDLC */
1854
1855 /*
1856  * get async data from rx DMA buffers
1857  */
1858 static void rx_async(struct slgt_info *info)
1859 {
1860         struct tty_struct *tty = info->port.tty;
1861         struct mgsl_icount *icount = &info->icount;
1862         unsigned int start, end;
1863         unsigned char *p;
1864         unsigned char status;
1865         struct slgt_desc *bufs = info->rbufs;
1866         int i, count;
1867         int chars = 0;
1868         int stat;
1869         unsigned char ch;
1870
1871         start = end = info->rbuf_current;
1872
1873         while(desc_complete(bufs[end])) {
1874                 count = desc_count(bufs[end]) - info->rbuf_index;
1875                 p     = bufs[end].buf + info->rbuf_index;
1876
1877                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1878                 DBGDATA(info, p, count, "rx");
1879
1880                 for(i=0 ; i < count; i+=2, p+=2) {
1881                         ch = *p;
1882                         icount->rx++;
1883
1884                         stat = 0;
1885
1886                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1887                                 if (status & BIT1)
1888                                         icount->parity++;
1889                                 else if (status & BIT0)
1890                                         icount->frame++;
1891                                 /* discard char if tty control flags say so */
1892                                 if (status & info->ignore_status_mask)
1893                                         continue;
1894                                 if (status & BIT1)
1895                                         stat = TTY_PARITY;
1896                                 else if (status & BIT0)
1897                                         stat = TTY_FRAME;
1898                         }
1899                         if (tty) {
1900                                 tty_insert_flip_char(tty, ch, stat);
1901                                 chars++;
1902                         }
1903                 }
1904
1905                 if (i < count) {
1906                         /* receive buffer not completed */
1907                         info->rbuf_index += i;
1908                         mod_timer(&info->rx_timer, jiffies + 1);
1909                         break;
1910                 }
1911
1912                 info->rbuf_index = 0;
1913                 free_rbufs(info, end, end);
1914
1915                 if (++end == info->rbuf_count)
1916                         end = 0;
1917
1918                 /* if entire list searched then no frame available */
1919                 if (end == start)
1920                         break;
1921         }
1922
1923         if (tty && chars)
1924                 tty_flip_buffer_push(tty);
1925 }
1926
1927 /*
1928  * return next bottom half action to perform
1929  */
1930 static int bh_action(struct slgt_info *info)
1931 {
1932         unsigned long flags;
1933         int rc;
1934
1935         spin_lock_irqsave(&info->lock,flags);
1936
1937         if (info->pending_bh & BH_RECEIVE) {
1938                 info->pending_bh &= ~BH_RECEIVE;
1939                 rc = BH_RECEIVE;
1940         } else if (info->pending_bh & BH_TRANSMIT) {
1941                 info->pending_bh &= ~BH_TRANSMIT;
1942                 rc = BH_TRANSMIT;
1943         } else if (info->pending_bh & BH_STATUS) {
1944                 info->pending_bh &= ~BH_STATUS;
1945                 rc = BH_STATUS;
1946         } else {
1947                 /* Mark BH routine as complete */
1948                 info->bh_running = false;
1949                 info->bh_requested = false;
1950                 rc = 0;
1951         }
1952
1953         spin_unlock_irqrestore(&info->lock,flags);
1954
1955         return rc;
1956 }
1957
1958 /*
1959  * perform bottom half processing
1960  */
1961 static void bh_handler(struct work_struct *work)
1962 {
1963         struct slgt_info *info = container_of(work, struct slgt_info, task);
1964         int action;
1965
1966         if (!info)
1967                 return;
1968         info->bh_running = true;
1969
1970         while((action = bh_action(info))) {
1971                 switch (action) {
1972                 case BH_RECEIVE:
1973                         DBGBH(("%s bh receive\n", info->device_name));
1974                         switch(info->params.mode) {
1975                         case MGSL_MODE_ASYNC:
1976                                 rx_async(info);
1977                                 break;
1978                         case MGSL_MODE_HDLC:
1979                                 while(rx_get_frame(info));
1980                                 break;
1981                         case MGSL_MODE_RAW:
1982                         case MGSL_MODE_MONOSYNC:
1983                         case MGSL_MODE_BISYNC:
1984                         case MGSL_MODE_XSYNC:
1985                                 while(rx_get_buf(info));
1986                                 break;
1987                         }
1988                         /* restart receiver if rx DMA buffers exhausted */
1989                         if (info->rx_restart)
1990                                 rx_start(info);
1991                         break;
1992                 case BH_TRANSMIT:
1993                         bh_transmit(info);
1994                         break;
1995                 case BH_STATUS:
1996                         DBGBH(("%s bh status\n", info->device_name));
1997                         info->ri_chkcount = 0;
1998                         info->dsr_chkcount = 0;
1999                         info->dcd_chkcount = 0;
2000                         info->cts_chkcount = 0;
2001                         break;
2002                 default:
2003                         DBGBH(("%s unknown action\n", info->device_name));
2004                         break;
2005                 }
2006         }
2007         DBGBH(("%s bh_handler exit\n", info->device_name));
2008 }
2009
2010 static void bh_transmit(struct slgt_info *info)
2011 {
2012         struct tty_struct *tty = info->port.tty;
2013
2014         DBGBH(("%s bh_transmit\n", info->device_name));
2015         if (tty)
2016                 tty_wakeup(tty);
2017 }
2018
2019 static void dsr_change(struct slgt_info *info, unsigned short status)
2020 {
2021         if (status & BIT3) {
2022                 info->signals |= SerialSignal_DSR;
2023                 info->input_signal_events.dsr_up++;
2024         } else {
2025                 info->signals &= ~SerialSignal_DSR;
2026                 info->input_signal_events.dsr_down++;
2027         }
2028         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2029         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2030                 slgt_irq_off(info, IRQ_DSR);
2031                 return;
2032         }
2033         info->icount.dsr++;
2034         wake_up_interruptible(&info->status_event_wait_q);
2035         wake_up_interruptible(&info->event_wait_q);
2036         info->pending_bh |= BH_STATUS;
2037 }
2038
2039 static void cts_change(struct slgt_info *info, unsigned short status)
2040 {
2041         if (status & BIT2) {
2042                 info->signals |= SerialSignal_CTS;
2043                 info->input_signal_events.cts_up++;
2044         } else {
2045                 info->signals &= ~SerialSignal_CTS;
2046                 info->input_signal_events.cts_down++;
2047         }
2048         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2049         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2050                 slgt_irq_off(info, IRQ_CTS);
2051                 return;
2052         }
2053         info->icount.cts++;
2054         wake_up_interruptible(&info->status_event_wait_q);
2055         wake_up_interruptible(&info->event_wait_q);
2056         info->pending_bh |= BH_STATUS;
2057
2058         if (info->port.flags & ASYNC_CTS_FLOW) {
2059                 if (info->port.tty) {
2060                         if (info->port.tty->hw_stopped) {
2061                                 if (info->signals & SerialSignal_CTS) {
2062                                         info->port.tty->hw_stopped = 0;
2063                                         info->pending_bh |= BH_TRANSMIT;
2064                                         return;
2065                                 }
2066                         } else {
2067                                 if (!(info->signals & SerialSignal_CTS))
2068                                         info->port.tty->hw_stopped = 1;
2069                         }
2070                 }
2071         }
2072 }
2073
2074 static void dcd_change(struct slgt_info *info, unsigned short status)
2075 {
2076         if (status & BIT1) {
2077                 info->signals |= SerialSignal_DCD;
2078                 info->input_signal_events.dcd_up++;
2079         } else {
2080                 info->signals &= ~SerialSignal_DCD;
2081                 info->input_signal_events.dcd_down++;
2082         }
2083         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2084         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2085                 slgt_irq_off(info, IRQ_DCD);
2086                 return;
2087         }
2088         info->icount.dcd++;
2089 #if SYNCLINK_GENERIC_HDLC
2090         if (info->netcount) {
2091                 if (info->signals & SerialSignal_DCD)
2092                         netif_carrier_on(info->netdev);
2093                 else
2094                         netif_carrier_off(info->netdev);
2095         }
2096 #endif
2097         wake_up_interruptible(&info->status_event_wait_q);
2098         wake_up_interruptible(&info->event_wait_q);
2099         info->pending_bh |= BH_STATUS;
2100
2101         if (info->port.flags & ASYNC_CHECK_CD) {
2102                 if (info->signals & SerialSignal_DCD)
2103                         wake_up_interruptible(&info->port.open_wait);
2104                 else {
2105                         if (info->port.tty)
2106                                 tty_hangup(info->port.tty);
2107                 }
2108         }
2109 }
2110
2111 static void ri_change(struct slgt_info *info, unsigned short status)
2112 {
2113         if (status & BIT0) {
2114                 info->signals |= SerialSignal_RI;
2115                 info->input_signal_events.ri_up++;
2116         } else {
2117                 info->signals &= ~SerialSignal_RI;
2118                 info->input_signal_events.ri_down++;
2119         }
2120         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2121         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2122                 slgt_irq_off(info, IRQ_RI);
2123                 return;
2124         }
2125         info->icount.rng++;
2126         wake_up_interruptible(&info->status_event_wait_q);
2127         wake_up_interruptible(&info->event_wait_q);
2128         info->pending_bh |= BH_STATUS;
2129 }
2130
2131 static void isr_rxdata(struct slgt_info *info)
2132 {
2133         unsigned int count = info->rbuf_fill_count;
2134         unsigned int i = info->rbuf_fill_index;
2135         unsigned short reg;
2136
2137         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2138                 reg = rd_reg16(info, RDR);
2139                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2140                 if (desc_complete(info->rbufs[i])) {
2141                         /* all buffers full */
2142                         rx_stop(info);
2143                         info->rx_restart = 1;
2144                         continue;
2145                 }
2146                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2147                 /* async mode saves status byte to buffer for each data byte */
2148                 if (info->params.mode == MGSL_MODE_ASYNC)
2149                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2150                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2151                         /* buffer full or end of frame */
2152                         set_desc_count(info->rbufs[i], count);
2153                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2154                         info->rbuf_fill_count = count = 0;
2155                         if (++i == info->rbuf_count)
2156                                 i = 0;
2157                         info->pending_bh |= BH_RECEIVE;
2158                 }
2159         }
2160
2161         info->rbuf_fill_index = i;
2162         info->rbuf_fill_count = count;
2163 }
2164
2165 static void isr_serial(struct slgt_info *info)
2166 {
2167         unsigned short status = rd_reg16(info, SSR);
2168
2169         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2170
2171         wr_reg16(info, SSR, status); /* clear pending */
2172
2173         info->irq_occurred = true;
2174
2175         if (info->params.mode == MGSL_MODE_ASYNC) {
2176                 if (status & IRQ_TXIDLE) {
2177                         if (info->tx_active)
2178                                 isr_txeom(info, status);
2179                 }
2180                 if (info->rx_pio && (status & IRQ_RXDATA))
2181                         isr_rxdata(info);
2182                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2183                         info->icount.brk++;
2184                         /* process break detection if tty control allows */
2185                         if (info->port.tty) {
2186                                 if (!(status & info->ignore_status_mask)) {
2187                                         if (info->read_status_mask & MASK_BREAK) {
2188                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2189                                                 if (info->port.flags & ASYNC_SAK)
2190                                                         do_SAK(info->port.tty);
2191                                         }
2192                                 }
2193                         }
2194                 }
2195         } else {
2196                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2197                         isr_txeom(info, status);
2198                 if (info->rx_pio && (status & IRQ_RXDATA))
2199                         isr_rxdata(info);
2200                 if (status & IRQ_RXIDLE) {
2201                         if (status & RXIDLE)
2202                                 info->icount.rxidle++;
2203                         else
2204                                 info->icount.exithunt++;
2205                         wake_up_interruptible(&info->event_wait_q);
2206                 }
2207
2208                 if (status & IRQ_RXOVER)
2209                         rx_start(info);
2210         }
2211
2212         if (status & IRQ_DSR)
2213                 dsr_change(info, status);
2214         if (status & IRQ_CTS)
2215                 cts_change(info, status);
2216         if (status & IRQ_DCD)
2217                 dcd_change(info, status);
2218         if (status & IRQ_RI)
2219                 ri_change(info, status);
2220 }
2221
2222 static void isr_rdma(struct slgt_info *info)
2223 {
2224         unsigned int status = rd_reg32(info, RDCSR);
2225
2226         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2227
2228         /* RDCSR (rx DMA control/status)
2229          *
2230          * 31..07  reserved
2231          * 06      save status byte to DMA buffer
2232          * 05      error
2233          * 04      eol (end of list)
2234          * 03      eob (end of buffer)
2235          * 02      IRQ enable
2236          * 01      reset
2237          * 00      enable
2238          */
2239         wr_reg32(info, RDCSR, status);  /* clear pending */
2240
2241         if (status & (BIT5 + BIT4)) {
2242                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2243                 info->rx_restart = true;
2244         }
2245         info->pending_bh |= BH_RECEIVE;
2246 }
2247
2248 static void isr_tdma(struct slgt_info *info)
2249 {
2250         unsigned int status = rd_reg32(info, TDCSR);
2251
2252         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2253
2254         /* TDCSR (tx DMA control/status)
2255          *
2256          * 31..06  reserved
2257          * 05      error
2258          * 04      eol (end of list)
2259          * 03      eob (end of buffer)
2260          * 02      IRQ enable
2261          * 01      reset
2262          * 00      enable
2263          */
2264         wr_reg32(info, TDCSR, status);  /* clear pending */
2265
2266         if (status & (BIT5 + BIT4 + BIT3)) {
2267                 // another transmit buffer has completed
2268                 // run bottom half to get more send data from user
2269                 info->pending_bh |= BH_TRANSMIT;
2270         }
2271 }
2272
2273 /*
2274  * return true if there are unsent tx DMA buffers, otherwise false
2275  *
2276  * if there are unsent buffers then info->tbuf_start
2277  * is set to index of first unsent buffer
2278  */
2279 static bool unsent_tbufs(struct slgt_info *info)
2280 {
2281         unsigned int i = info->tbuf_current;
2282         bool rc = false;
2283
2284         /*
2285          * search backwards from last loaded buffer (precedes tbuf_current)
2286          * for first unsent buffer (desc_count > 0)
2287          */
2288
2289         do {
2290                 if (i)
2291                         i--;
2292                 else
2293                         i = info->tbuf_count - 1;
2294                 if (!desc_count(info->tbufs[i]))
2295                         break;
2296                 info->tbuf_start = i;
2297                 rc = true;
2298         } while (i != info->tbuf_current);
2299
2300         return rc;
2301 }
2302
2303 static void isr_txeom(struct slgt_info *info, unsigned short status)
2304 {
2305         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2306
2307         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2308         tdma_reset(info);
2309         if (status & IRQ_TXUNDER) {
2310                 unsigned short val = rd_reg16(info, TCR);
2311                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2312                 wr_reg16(info, TCR, val); /* clear reset bit */
2313         }
2314
2315         if (info->tx_active) {
2316                 if (info->params.mode != MGSL_MODE_ASYNC) {
2317                         if (status & IRQ_TXUNDER)
2318                                 info->icount.txunder++;
2319                         else if (status & IRQ_TXIDLE)
2320                                 info->icount.txok++;
2321                 }
2322
2323                 if (unsent_tbufs(info)) {
2324                         tx_start(info);
2325                         update_tx_timer(info);
2326                         return;
2327                 }
2328                 info->tx_active = false;
2329
2330                 del_timer(&info->tx_timer);
2331
2332                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2333                         info->signals &= ~SerialSignal_RTS;
2334                         info->drop_rts_on_tx_done = false;
2335                         set_signals(info);
2336                 }
2337
2338 #if SYNCLINK_GENERIC_HDLC
2339                 if (info->netcount)
2340                         hdlcdev_tx_done(info);
2341                 else
2342 #endif
2343                 {
2344                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2345                                 tx_stop(info);
2346                                 return;
2347                         }
2348                         info->pending_bh |= BH_TRANSMIT;
2349                 }
2350         }
2351 }
2352
2353 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2354 {
2355         struct cond_wait *w, *prev;
2356
2357         /* wake processes waiting for specific transitions */
2358         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2359                 if (w->data & changed) {
2360                         w->data = state;
2361                         wake_up_interruptible(&w->q);
2362                         if (prev != NULL)
2363                                 prev->next = w->next;
2364                         else
2365                                 info->gpio_wait_q = w->next;
2366                 } else
2367                         prev = w;
2368         }
2369 }
2370
2371 /* interrupt service routine
2372  *
2373  *      irq     interrupt number
2374  *      dev_id  device ID supplied during interrupt registration
2375  */
2376 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2377 {
2378         struct slgt_info *info = dev_id;
2379         unsigned int gsr;
2380         unsigned int i;
2381
2382         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2383
2384         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2385                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2386                 info->irq_occurred = true;
2387                 for(i=0; i < info->port_count ; i++) {
2388                         if (info->port_array[i] == NULL)
2389                                 continue;
2390                         spin_lock(&info->port_array[i]->lock);
2391                         if (gsr & (BIT8 << i))
2392                                 isr_serial(info->port_array[i]);
2393                         if (gsr & (BIT16 << (i*2)))
2394                                 isr_rdma(info->port_array[i]);
2395                         if (gsr & (BIT17 << (i*2)))
2396                                 isr_tdma(info->port_array[i]);
2397                         spin_unlock(&info->port_array[i]->lock);
2398                 }
2399         }
2400
2401         if (info->gpio_present) {
2402                 unsigned int state;
2403                 unsigned int changed;
2404                 spin_lock(&info->lock);
2405                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2406                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2407                         /* read latched state of GPIO signals */
2408                         state = rd_reg32(info, IOVR);
2409                         /* clear pending GPIO interrupt bits */
2410                         wr_reg32(info, IOSR, changed);
2411                         for (i=0 ; i < info->port_count ; i++) {
2412                                 if (info->port_array[i] != NULL)
2413                                         isr_gpio(info->port_array[i], changed, state);
2414                         }
2415                 }
2416                 spin_unlock(&info->lock);
2417         }
2418
2419         for(i=0; i < info->port_count ; i++) {
2420                 struct slgt_info *port = info->port_array[i];
2421                 if (port == NULL)
2422                         continue;
2423                 spin_lock(&port->lock);
2424                 if ((port->port.count || port->netcount) &&
2425                     port->pending_bh && !port->bh_running &&
2426                     !port->bh_requested) {
2427                         DBGISR(("%s bh queued\n", port->device_name));
2428                         schedule_work(&port->task);
2429                         port->bh_requested = true;
2430                 }
2431                 spin_unlock(&port->lock);
2432         }
2433
2434         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2435         return IRQ_HANDLED;
2436 }
2437
2438 static int startup(struct slgt_info *info)
2439 {
2440         DBGINFO(("%s startup\n", info->device_name));
2441
2442         if (info->port.flags & ASYNC_INITIALIZED)
2443                 return 0;
2444
2445         if (!info->tx_buf) {
2446                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2447                 if (!info->tx_buf) {
2448                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2449                         return -ENOMEM;
2450                 }
2451         }
2452
2453         info->pending_bh = 0;
2454
2455         memset(&info->icount, 0, sizeof(info->icount));
2456
2457         /* program hardware for current parameters */
2458         change_params(info);
2459
2460         if (info->port.tty)
2461                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2462
2463         info->port.flags |= ASYNC_INITIALIZED;
2464
2465         return 0;
2466 }
2467
2468 /*
2469  *  called by close() and hangup() to shutdown hardware
2470  */
2471 static void shutdown(struct slgt_info *info)
2472 {
2473         unsigned long flags;
2474
2475         if (!(info->port.flags & ASYNC_INITIALIZED))
2476                 return;
2477
2478         DBGINFO(("%s shutdown\n", info->device_name));
2479
2480         /* clear status wait queue because status changes */
2481         /* can't happen after shutting down the hardware */
2482         wake_up_interruptible(&info->status_event_wait_q);
2483         wake_up_interruptible(&info->event_wait_q);
2484
2485         del_timer_sync(&info->tx_timer);
2486         del_timer_sync(&info->rx_timer);
2487
2488         kfree(info->tx_buf);
2489         info->tx_buf = NULL;
2490
2491         spin_lock_irqsave(&info->lock,flags);
2492
2493         tx_stop(info);
2494         rx_stop(info);
2495
2496         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2497
2498         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2499                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2500                 set_signals(info);
2501         }
2502
2503         flush_cond_wait(&info->gpio_wait_q);
2504
2505         spin_unlock_irqrestore(&info->lock,flags);
2506
2507         if (info->port.tty)
2508                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2509
2510         info->port.flags &= ~ASYNC_INITIALIZED;
2511 }
2512
2513 static void program_hw(struct slgt_info *info)
2514 {
2515         unsigned long flags;
2516
2517         spin_lock_irqsave(&info->lock,flags);
2518
2519         rx_stop(info);
2520         tx_stop(info);
2521
2522         if (info->params.mode != MGSL_MODE_ASYNC ||
2523             info->netcount)
2524                 sync_mode(info);
2525         else
2526                 async_mode(info);
2527
2528         set_signals(info);
2529
2530         info->dcd_chkcount = 0;
2531         info->cts_chkcount = 0;
2532         info->ri_chkcount = 0;
2533         info->dsr_chkcount = 0;
2534
2535         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2536         get_signals(info);
2537
2538         if (info->netcount ||
2539             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2540                 rx_start(info);
2541
2542         spin_unlock_irqrestore(&info->lock,flags);
2543 }
2544
2545 /*
2546  * reconfigure adapter based on new parameters
2547  */
2548 static void change_params(struct slgt_info *info)
2549 {
2550         unsigned cflag;
2551         int bits_per_char;
2552
2553         if (!info->port.tty || !info->port.tty->termios)
2554                 return;
2555         DBGINFO(("%s change_params\n", info->device_name));
2556
2557         cflag = info->port.tty->termios->c_cflag;
2558
2559         /* if B0 rate (hangup) specified then negate DTR and RTS */
2560         /* otherwise assert DTR and RTS */
2561         if (cflag & CBAUD)
2562                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2563         else
2564                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2565
2566         /* byte size and parity */
2567
2568         switch (cflag & CSIZE) {
2569         case CS5: info->params.data_bits = 5; break;
2570         case CS6: info->params.data_bits = 6; break;
2571         case CS7: info->params.data_bits = 7; break;
2572         case CS8: info->params.data_bits = 8; break;
2573         default:  info->params.data_bits = 7; break;
2574         }
2575
2576         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2577
2578         if (cflag & PARENB)
2579                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2580         else
2581                 info->params.parity = ASYNC_PARITY_NONE;
2582
2583         /* calculate number of jiffies to transmit a full
2584          * FIFO (32 bytes) at specified data rate
2585          */
2586         bits_per_char = info->params.data_bits +
2587                         info->params.stop_bits + 1;
2588
2589         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2590
2591         if (info->params.data_rate) {
2592                 info->timeout = (32*HZ*bits_per_char) /
2593                                 info->params.data_rate;
2594         }
2595         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2596
2597         if (cflag & CRTSCTS)
2598                 info->port.flags |= ASYNC_CTS_FLOW;
2599         else
2600                 info->port.flags &= ~ASYNC_CTS_FLOW;
2601
2602         if (cflag & CLOCAL)
2603                 info->port.flags &= ~ASYNC_CHECK_CD;
2604         else
2605                 info->port.flags |= ASYNC_CHECK_CD;
2606
2607         /* process tty input control flags */
2608
2609         info->read_status_mask = IRQ_RXOVER;
2610         if (I_INPCK(info->port.tty))
2611                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2612         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2613                 info->read_status_mask |= MASK_BREAK;
2614         if (I_IGNPAR(info->port.tty))
2615                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2616         if (I_IGNBRK(info->port.tty)) {
2617                 info->ignore_status_mask |= MASK_BREAK;
2618                 /* If ignoring parity and break indicators, ignore
2619                  * overruns too.  (For real raw support).
2620                  */
2621                 if (I_IGNPAR(info->port.tty))
2622                         info->ignore_status_mask |= MASK_OVERRUN;
2623         }
2624
2625         program_hw(info);
2626 }
2627
2628 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2629 {
2630         DBGINFO(("%s get_stats\n",  info->device_name));
2631         if (!user_icount) {
2632                 memset(&info->icount, 0, sizeof(info->icount));
2633         } else {
2634                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2635                         return -EFAULT;
2636         }
2637         return 0;
2638 }
2639
2640 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2641 {
2642         DBGINFO(("%s get_params\n", info->device_name));
2643         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2644                 return -EFAULT;
2645         return 0;
2646 }
2647
2648 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2649 {
2650         unsigned long flags;
2651         MGSL_PARAMS tmp_params;
2652
2653         DBGINFO(("%s set_params\n", info->device_name));
2654         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2655                 return -EFAULT;
2656
2657         spin_lock_irqsave(&info->lock, flags);
2658         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2659                 info->base_clock = tmp_params.clock_speed;
2660         else
2661                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2662         spin_unlock_irqrestore(&info->lock, flags);
2663
2664         program_hw(info);
2665
2666         return 0;
2667 }
2668
2669 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2670 {
2671         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2672         if (put_user(info->idle_mode, idle_mode))
2673                 return -EFAULT;
2674         return 0;
2675 }
2676
2677 static int set_txidle(struct slgt_info *info, int idle_mode)
2678 {
2679         unsigned long flags;
2680         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2681         spin_lock_irqsave(&info->lock,flags);
2682         info->idle_mode = idle_mode;
2683         if (info->params.mode != MGSL_MODE_ASYNC)
2684                 tx_set_idle(info);
2685         spin_unlock_irqrestore(&info->lock,flags);
2686         return 0;
2687 }
2688
2689 static int tx_enable(struct slgt_info *info, int enable)
2690 {
2691         unsigned long flags;
2692         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2693         spin_lock_irqsave(&info->lock,flags);
2694         if (enable) {
2695                 if (!info->tx_enabled)
2696                         tx_start(info);
2697         } else {
2698                 if (info->tx_enabled)
2699                         tx_stop(info);
2700         }
2701         spin_unlock_irqrestore(&info->lock,flags);
2702         return 0;
2703 }
2704
2705 /*
2706  * abort transmit HDLC frame
2707  */
2708 static int tx_abort(struct slgt_info *info)
2709 {
2710         unsigned long flags;
2711         DBGINFO(("%s tx_abort\n", info->device_name));
2712         spin_lock_irqsave(&info->lock,flags);
2713         tdma_reset(info);
2714         spin_unlock_irqrestore(&info->lock,flags);
2715         return 0;
2716 }
2717
2718 static int rx_enable(struct slgt_info *info, int enable)
2719 {
2720         unsigned long flags;
2721         unsigned int rbuf_fill_level;
2722         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2723         spin_lock_irqsave(&info->lock,flags);
2724         /*
2725          * enable[31..16] = receive DMA buffer fill level
2726          * 0 = noop (leave fill level unchanged)
2727          * fill level must be multiple of 4 and <= buffer size
2728          */
2729         rbuf_fill_level = ((unsigned int)enable) >> 16;
2730         if (rbuf_fill_level) {
2731                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2732                         spin_unlock_irqrestore(&info->lock, flags);
2733                         return -EINVAL;
2734                 }
2735                 info->rbuf_fill_level = rbuf_fill_level;
2736                 if (rbuf_fill_level < 128)
2737                         info->rx_pio = 1; /* PIO mode */
2738                 else
2739                         info->rx_pio = 0; /* DMA mode */
2740                 rx_stop(info); /* restart receiver to use new fill level */
2741         }
2742
2743         /*
2744          * enable[1..0] = receiver enable command
2745          * 0 = disable
2746          * 1 = enable
2747          * 2 = enable or force hunt mode if already enabled
2748          */
2749         enable &= 3;
2750         if (enable) {
2751                 if (!info->rx_enabled)
2752                         rx_start(info);
2753                 else if (enable == 2) {
2754                         /* force hunt mode (write 1 to RCR[3]) */
2755                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2756                 }
2757         } else {
2758                 if (info->rx_enabled)
2759                         rx_stop(info);
2760         }
2761         spin_unlock_irqrestore(&info->lock,flags);
2762         return 0;
2763 }
2764
2765 /*
2766  *  wait for specified event to occur
2767  */
2768 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2769 {
2770         unsigned long flags;
2771         int s;
2772         int rc=0;
2773         struct mgsl_icount cprev, cnow;
2774         int events;
2775         int mask;
2776         struct  _input_signal_events oldsigs, newsigs;
2777         DECLARE_WAITQUEUE(wait, current);
2778
2779         if (get_user(mask, mask_ptr))
2780                 return -EFAULT;
2781
2782         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2783
2784         spin_lock_irqsave(&info->lock,flags);
2785
2786         /* return immediately if state matches requested events */
2787         get_signals(info);
2788         s = info->signals;
2789
2790         events = mask &
2791                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2792                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2793                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2794                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2795         if (events) {
2796                 spin_unlock_irqrestore(&info->lock,flags);
2797                 goto exit;
2798         }
2799
2800         /* save current irq counts */
2801         cprev = info->icount;
2802         oldsigs = info->input_signal_events;
2803
2804         /* enable hunt and idle irqs if needed */
2805         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2806                 unsigned short val = rd_reg16(info, SCR);
2807                 if (!(val & IRQ_RXIDLE))
2808                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2809         }
2810
2811         set_current_state(TASK_INTERRUPTIBLE);
2812         add_wait_queue(&info->event_wait_q, &wait);
2813
2814         spin_unlock_irqrestore(&info->lock,flags);
2815
2816         for(;;) {
2817                 schedule();
2818                 if (signal_pending(current)) {
2819                         rc = -ERESTARTSYS;
2820                         break;
2821                 }
2822
2823                 /* get current irq counts */
2824                 spin_lock_irqsave(&info->lock,flags);
2825                 cnow = info->icount;
2826                 newsigs = info->input_signal_events;
2827                 set_current_state(TASK_INTERRUPTIBLE);
2828                 spin_unlock_irqrestore(&info->lock,flags);
2829
2830                 /* if no change, wait aborted for some reason */
2831                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2832                     newsigs.dsr_down == oldsigs.dsr_down &&
2833                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2834                     newsigs.dcd_down == oldsigs.dcd_down &&
2835                     newsigs.cts_up   == oldsigs.cts_up   &&
2836                     newsigs.cts_down == oldsigs.cts_down &&
2837                     newsigs.ri_up    == oldsigs.ri_up    &&
2838                     newsigs.ri_down  == oldsigs.ri_down  &&
2839                     cnow.exithunt    == cprev.exithunt   &&
2840                     cnow.rxidle      == cprev.rxidle) {
2841                         rc = -EIO;
2842                         break;
2843                 }
2844
2845                 events = mask &
2846                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2847                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2848                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2849                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2850                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2851                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2852                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2853                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2854                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2855                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2856                 if (events)
2857                         break;
2858
2859                 cprev = cnow;
2860                 oldsigs = newsigs;
2861         }
2862
2863         remove_wait_queue(&info->event_wait_q, &wait);
2864         set_current_state(TASK_RUNNING);
2865
2866
2867         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2868                 spin_lock_irqsave(&info->lock,flags);
2869                 if (!waitqueue_active(&info->event_wait_q)) {
2870                         /* disable enable exit hunt mode/idle rcvd IRQs */
2871                         wr_reg16(info, SCR,
2872                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2873                 }
2874                 spin_unlock_irqrestore(&info->lock,flags);
2875         }
2876 exit:
2877         if (rc == 0)
2878                 rc = put_user(events, mask_ptr);
2879         return rc;
2880 }
2881
2882 static int get_interface(struct slgt_info *info, int __user *if_mode)
2883 {
2884         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2885         if (put_user(info->if_mode, if_mode))
2886                 return -EFAULT;
2887         return 0;
2888 }
2889
2890 static int set_interface(struct slgt_info *info, int if_mode)
2891 {
2892         unsigned long flags;
2893         unsigned short val;
2894
2895         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2896         spin_lock_irqsave(&info->lock,flags);
2897         info->if_mode = if_mode;
2898
2899         msc_set_vcr(info);
2900
2901         /* TCR (tx control) 07  1=RTS driver control */
2902         val = rd_reg16(info, TCR);
2903         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2904                 val |= BIT7;
2905         else
2906                 val &= ~BIT7;
2907         wr_reg16(info, TCR, val);
2908
2909         spin_unlock_irqrestore(&info->lock,flags);
2910         return 0;
2911 }
2912
2913 static int get_xsync(struct slgt_info *info, int __user *xsync)
2914 {
2915         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2916         if (put_user(info->xsync, xsync))
2917                 return -EFAULT;
2918         return 0;
2919 }
2920
2921 /*
2922  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2923  *
2924  * sync pattern is contained in least significant bytes of value
2925  * most significant byte of sync pattern is oldest (1st sent/detected)
2926  */
2927 static int set_xsync(struct slgt_info *info, int xsync)
2928 {
2929         unsigned long flags;
2930
2931         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2932         spin_lock_irqsave(&info->lock, flags);
2933         info->xsync = xsync;
2934         wr_reg32(info, XSR, xsync);
2935         spin_unlock_irqrestore(&info->lock, flags);
2936         return 0;
2937 }
2938
2939 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2940 {
2941         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2942         if (put_user(info->xctrl, xctrl))
2943                 return -EFAULT;
2944         return 0;
2945 }
2946
2947 /*
2948  * set extended control options
2949  *
2950  * xctrl[31:19] reserved, must be zero
2951  * xctrl[18:17] extended sync pattern length in bytes
2952  *              00 = 1 byte  in xsr[7:0]
2953  *              01 = 2 bytes in xsr[15:0]
2954  *              10 = 3 bytes in xsr[23:0]
2955  *              11 = 4 bytes in xsr[31:0]
2956  * xctrl[16]    1 = enable terminal count, 0=disabled
2957  * xctrl[15:0]  receive terminal count for fixed length packets
2958  *              value is count minus one (0 = 1 byte packet)
2959  *              when terminal count is reached, receiver
2960  *              automatically returns to hunt mode and receive
2961  *              FIFO contents are flushed to DMA buffers with
2962  *              end of frame (EOF) status
2963  */
2964 static int set_xctrl(struct slgt_info *info, int xctrl)
2965 {
2966         unsigned long flags;
2967
2968         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2969         spin_lock_irqsave(&info->lock, flags);
2970         info->xctrl = xctrl;
2971         wr_reg32(info, XCR, xctrl);
2972         spin_unlock_irqrestore(&info->lock, flags);
2973         return 0;
2974 }
2975
2976 /*
2977  * set general purpose IO pin state and direction
2978  *
2979  * user_gpio fields:
2980  * state   each bit indicates a pin state
2981  * smask   set bit indicates pin state to set
2982  * dir     each bit indicates a pin direction (0=input, 1=output)
2983  * dmask   set bit indicates pin direction to set
2984  */
2985 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2986 {
2987         unsigned long flags;
2988         struct gpio_desc gpio;
2989         __u32 data;
2990
2991         if (!info->gpio_present)
2992                 return -EINVAL;
2993         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2994                 return -EFAULT;
2995         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2996                  info->device_name, gpio.state, gpio.smask,
2997                  gpio.dir, gpio.dmask));
2998
2999         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3000         if (gpio.dmask) {
3001                 data = rd_reg32(info, IODR);
3002                 data |= gpio.dmask & gpio.dir;
3003                 data &= ~(gpio.dmask & ~gpio.dir);
3004                 wr_reg32(info, IODR, data);
3005         }
3006         if (gpio.smask) {
3007                 data = rd_reg32(info, IOVR);
3008                 data |= gpio.smask & gpio.state;
3009                 data &= ~(gpio.smask & ~gpio.state);
3010                 wr_reg32(info, IOVR, data);
3011         }
3012         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3013
3014         return 0;
3015 }
3016
3017 /*
3018  * get general purpose IO pin state and direction
3019  */
3020 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3021 {
3022         struct gpio_desc gpio;
3023         if (!info->gpio_present)
3024                 return -EINVAL;
3025         gpio.state = rd_reg32(info, IOVR);
3026         gpio.smask = 0xffffffff;
3027         gpio.dir   = rd_reg32(info, IODR);
3028         gpio.dmask = 0xffffffff;
3029         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3030                 return -EFAULT;
3031         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3032                  info->device_name, gpio.state, gpio.dir));
3033         return 0;
3034 }
3035
3036 /*
3037  * conditional wait facility
3038  */
3039 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3040 {
3041         init_waitqueue_head(&w->q);
3042         init_waitqueue_entry(&w->wait, current);
3043         w->data = data;
3044 }
3045
3046 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3047 {
3048         set_current_state(TASK_INTERRUPTIBLE);
3049         add_wait_queue(&w->q, &w->wait);
3050         w->next = *head;
3051         *head = w;
3052 }
3053
3054 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3055 {
3056         struct cond_wait *w, *prev;
3057         remove_wait_queue(&cw->q, &cw->wait);
3058         set_current_state(TASK_RUNNING);
3059         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3060                 if (w == cw) {
3061                         if (prev != NULL)
3062                                 prev->next = w->next;
3063                         else
3064                                 *head = w->next;
3065                         break;
3066                 }
3067         }
3068 }
3069
3070 static void flush_cond_wait(struct cond_wait **head)
3071 {
3072         while (*head != NULL) {
3073                 wake_up_interruptible(&(*head)->q);
3074                 *head = (*head)->next;
3075         }
3076 }
3077
3078 /*
3079  * wait for general purpose I/O pin(s) to enter specified state
3080  *
3081  * user_gpio fields:
3082  * state - bit indicates target pin state
3083  * smask - set bit indicates watched pin
3084  *
3085  * The wait ends when at least one watched pin enters the specified
3086  * state. When 0 (no error) is returned, user_gpio->state is set to the
3087  * state of all GPIO pins when the wait ends.
3088  *
3089  * Note: Each pin may be a dedicated input, dedicated output, or
3090  * configurable input/output. The number and configuration of pins
3091  * varies with the specific adapter model. Only input pins (dedicated
3092  * or configured) can be monitored with this function.
3093  */
3094 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3095 {
3096         unsigned long flags;
3097         int rc = 0;
3098         struct gpio_desc gpio;
3099         struct cond_wait wait;
3100         u32 state;
3101
3102         if (!info->gpio_present)
3103                 return -EINVAL;
3104         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3105                 return -EFAULT;
3106         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3107                  info->device_name, gpio.state, gpio.smask));
3108         /* ignore output pins identified by set IODR bit */
3109         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3110                 return -EINVAL;
3111         init_cond_wait(&wait, gpio.smask);
3112
3113         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3114         /* enable interrupts for watched pins */
3115         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3116         /* get current pin states */
3117         state = rd_reg32(info, IOVR);
3118
3119         if (gpio.smask & ~(state ^ gpio.state)) {
3120                 /* already in target state */
3121                 gpio.state = state;
3122         } else {
3123                 /* wait for target state */
3124                 add_cond_wait(&info->gpio_wait_q, &wait);
3125                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3126                 schedule();
3127                 if (signal_pending(current))
3128                         rc = -ERESTARTSYS;
3129                 else
3130                         gpio.state = wait.data;
3131                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3132                 remove_cond_wait(&info->gpio_wait_q, &wait);
3133         }
3134
3135         /* disable all GPIO interrupts if no waiting processes */
3136         if (info->gpio_wait_q == NULL)
3137                 wr_reg32(info, IOER, 0);
3138         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3139
3140         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3141                 rc = -EFAULT;
3142         return rc;
3143 }
3144
3145 static int modem_input_wait(struct slgt_info *info,int arg)
3146 {
3147         unsigned long flags;
3148         int rc;
3149         struct mgsl_icount cprev, cnow;
3150         DECLARE_WAITQUEUE(wait, current);
3151
3152         /* save current irq counts */
3153         spin_lock_irqsave(&info->lock,flags);
3154         cprev = info->icount;
3155         add_wait_queue(&info->status_event_wait_q, &wait);
3156         set_current_state(TASK_INTERRUPTIBLE);
3157         spin_unlock_irqrestore(&info->lock,flags);
3158
3159         for(;;) {
3160                 schedule();
3161                 if (signal_pending(current)) {
3162                         rc = -ERESTARTSYS;
3163                         break;
3164                 }
3165
3166                 /* get new irq counts */
3167                 spin_lock_irqsave(&info->lock,flags);
3168                 cnow = info->icount;
3169                 set_current_state(TASK_INTERRUPTIBLE);
3170                 spin_unlock_irqrestore(&info->lock,flags);
3171
3172                 /* if no change, wait aborted for some reason */
3173                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3174                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3175                         rc = -EIO;
3176                         break;
3177                 }
3178
3179                 /* check for change in caller specified modem input */
3180                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3181                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3182                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3183                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3184                         rc = 0;
3185                         break;
3186                 }
3187
3188                 cprev = cnow;
3189         }
3190         remove_wait_queue(&info->status_event_wait_q, &wait);
3191         set_current_state(TASK_RUNNING);
3192         return rc;
3193 }
3194
3195 /*
3196  *  return state of serial control and status signals
3197  */
3198 static int tiocmget(struct tty_struct *tty, struct file *file)
3199 {
3200         struct slgt_info *info = tty->driver_data;
3201         unsigned int result;
3202         unsigned long flags;
3203
3204         spin_lock_irqsave(&info->lock,flags);
3205         get_signals(info);
3206         spin_unlock_irqrestore(&info->lock,flags);
3207
3208         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3209                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3210                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3211                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3212                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3213                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3214
3215         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3216         return result;
3217 }
3218
3219 /*
3220  * set modem control signals (DTR/RTS)
3221  *
3222  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3223  *              TIOCMSET = set/clear signal values
3224  *      value   bit mask for command
3225  */
3226 static int tiocmset(struct tty_struct *tty, struct file *file,
3227                     unsigned int set, unsigned int clear)
3228 {
3229         struct slgt_info *info = tty->driver_data;
3230         unsigned long flags;
3231
3232         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3233
3234         if (set & TIOCM_RTS)
3235                 info->signals |= SerialSignal_RTS;
3236         if (set & TIOCM_DTR)
3237                 info->signals |= SerialSignal_DTR;
3238         if (clear & TIOCM_RTS)
3239                 info->signals &= ~SerialSignal_RTS;
3240         if (clear & TIOCM_DTR)
3241                 info->signals &= ~SerialSignal_DTR;
3242
3243         spin_lock_irqsave(&info->lock,flags);
3244         set_signals(info);
3245         spin_unlock_irqrestore(&info->lock,flags);
3246         return 0;
3247 }
3248
3249 static int carrier_raised(struct tty_port *port)
3250 {
3251         unsigned long flags;
3252         struct slgt_info *info = container_of(port, struct slgt_info, port);
3253
3254         spin_lock_irqsave(&info->lock,flags);
3255         get_signals(info);
3256         spin_unlock_irqrestore(&info->lock,flags);
3257         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3258 }
3259
3260 static void dtr_rts(struct tty_port *port, int on)
3261 {
3262         unsigned long flags;
3263         struct slgt_info *info = container_of(port, struct slgt_info, port);
3264
3265         spin_lock_irqsave(&info->lock,flags);
3266         if (on)
3267                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3268         else
3269                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3270         set_signals(info);
3271         spin_unlock_irqrestore(&info->lock,flags);
3272 }
3273
3274
3275 /*
3276  *  block current process until the device is ready to open
3277  */
3278 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3279                            struct slgt_info *info)
3280 {
3281         DECLARE_WAITQUEUE(wait, current);
3282         int             retval;
3283         bool            do_clocal = false;
3284         bool            extra_count = false;
3285         unsigned long   flags;
3286         int             cd;
3287         struct tty_port *port = &info->port;
3288
3289         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3290
3291         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3292                 /* nonblock mode is set or port is not enabled */
3293                 port->flags |= ASYNC_NORMAL_ACTIVE;
3294                 return 0;
3295         }
3296
3297         if (tty->termios->c_cflag & CLOCAL)
3298                 do_clocal = true;
3299
3300         /* Wait for carrier detect and the line to become
3301          * free (i.e., not in use by the callout).  While we are in
3302          * this loop, port->count is dropped by one, so that
3303          * close() knows when to free things.  We restore it upon
3304          * exit, either normal or abnormal.
3305          */
3306
3307         retval = 0;
3308         add_wait_queue(&port->open_wait, &wait);
3309
3310         spin_lock_irqsave(&info->lock, flags);
3311         if (!tty_hung_up_p(filp)) {
3312                 extra_count = true;
3313                 port->count--;
3314         }
3315         spin_unlock_irqrestore(&info->lock, flags);
3316         port->blocked_open++;
3317
3318         while (1) {
3319                 if ((tty->termios->c_cflag & CBAUD))
3320                         tty_port_raise_dtr_rts(port);
3321
3322                 set_current_state(TASK_INTERRUPTIBLE);
3323
3324                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3325                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3326                                         -EAGAIN : -ERESTARTSYS;
3327                         break;
3328                 }
3329
3330                 cd = tty_port_carrier_raised(port);
3331
3332                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3333                         break;
3334
3335                 if (signal_pending(current)) {
3336                         retval = -ERESTARTSYS;
3337                         break;
3338                 }
3339
3340                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3341                 tty_unlock();
3342                 schedule();
3343                 tty_lock();
3344         }
3345
3346         set_current_state(TASK_RUNNING);
3347         remove_wait_queue(&port->open_wait, &wait);
3348
3349         if (extra_count)
3350                 port->count++;
3351         port->blocked_open--;
3352
3353         if (!retval)
3354                 port->flags |= ASYNC_NORMAL_ACTIVE;
3355
3356         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3357         return retval;
3358 }
3359
3360 static int alloc_tmp_rbuf(struct slgt_info *info)
3361 {
3362         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3363         if (info->tmp_rbuf == NULL)
3364                 return -ENOMEM;
3365         return 0;
3366 }
3367
3368 static void free_tmp_rbuf(struct slgt_info *info)
3369 {
3370         kfree(info->tmp_rbuf);
3371         info->tmp_rbuf = NULL;
3372 }
3373
3374 /*
3375  * allocate DMA descriptor lists.
3376  */
3377 static int alloc_desc(struct slgt_info *info)
3378 {
3379         unsigned int i;
3380         unsigned int pbufs;
3381
3382         /* allocate memory to hold descriptor lists */
3383         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3384         if (info->bufs == NULL)
3385                 return -ENOMEM;
3386
3387         memset(info->bufs, 0, DESC_LIST_SIZE);
3388
3389         info->rbufs = (struct slgt_desc*)info->bufs;
3390         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3391
3392         pbufs = (unsigned int)info->bufs_dma_addr;
3393
3394         /*
3395          * Build circular lists of descriptors
3396          */
3397
3398         for (i=0; i < info->rbuf_count; i++) {
3399                 /* physical address of this descriptor */
3400                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3401
3402                 /* physical address of next descriptor */
3403                 if (i == info->rbuf_count - 1)
3404                         info->rbufs[i].next = cpu_to_le32(pbufs);
3405                 else
3406                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3407                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3408         }
3409
3410         for (i=0; i < info->tbuf_count; i++) {
3411                 /* physical address of this descriptor */
3412                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3413
3414                 /* physical address of next descriptor */
3415                 if (i == info->tbuf_count - 1)
3416                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3417                 else
3418                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3419         }
3420
3421         return 0;
3422 }
3423
3424 static void free_desc(struct slgt_info *info)
3425 {
3426         if (info->bufs != NULL) {
3427                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3428                 info->bufs  = NULL;
3429                 info->rbufs = NULL;
3430                 info->tbufs = NULL;
3431         }
3432 }
3433
3434 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3435 {
3436         int i;
3437         for (i=0; i < count; i++) {
3438                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3439                         return -ENOMEM;
3440                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3441         }
3442         return 0;
3443 }
3444
3445 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3446 {
3447         int i;
3448         for (i=0; i < count; i++) {
3449                 if (bufs[i].buf == NULL)
3450                         continue;
3451                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3452                 bufs[i].buf = NULL;
3453         }
3454 }
3455
3456 static int alloc_dma_bufs(struct slgt_info *info)
3457 {
3458         info->rbuf_count = 32;
3459         info->tbuf_count = 32;
3460
3461         if (alloc_desc(info) < 0 ||
3462             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3463             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3464             alloc_tmp_rbuf(info) < 0) {
3465                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3466                 return -ENOMEM;
3467         }
3468         reset_rbufs(info);
3469         return 0;
3470 }
3471
3472 static void free_dma_bufs(struct slgt_info *info)
3473 {
3474         if (info->bufs) {
3475                 free_bufs(info, info->rbufs, info->rbuf_count);
3476                 free_bufs(info, info->tbufs, info->tbuf_count);
3477                 free_desc(info);
3478         }
3479         free_tmp_rbuf(info);
3480 }
3481
3482 static int claim_resources(struct slgt_info *info)
3483 {
3484         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3485                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3486                         info->device_name, info->phys_reg_addr));
3487                 info->init_error = DiagStatus_AddressConflict;
3488                 goto errout;
3489         }
3490         else
3491                 info->reg_addr_requested = true;
3492
3493         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3494         if (!info->reg_addr) {
3495                 DBGERR(("%s cant map device registers, addr=%08X\n",
3496                         info->device_name, info->phys_reg_addr));
3497                 info->init_error = DiagStatus_CantAssignPciResources;
3498                 goto errout;
3499         }
3500         return 0;
3501
3502 errout:
3503         release_resources(info);
3504         return -ENODEV;
3505 }
3506
3507 static void release_resources(struct slgt_info *info)
3508 {
3509         if (info->irq_requested) {
3510                 free_irq(info->irq_level, info);
3511                 info->irq_requested = false;
3512         }
3513
3514         if (info->reg_addr_requested) {
3515                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3516                 info->reg_addr_requested = false;
3517         }
3518
3519         if (info->reg_addr) {
3520                 iounmap(info->reg_addr);
3521                 info->reg_addr = NULL;
3522         }
3523 }
3524
3525 /* Add the specified device instance data structure to the
3526  * global linked list of devices and increment the device count.
3527  */
3528 static void add_device(struct slgt_info *info)
3529 {
3530         char *devstr;
3531
3532         info->next_device = NULL;
3533         info->line = slgt_device_count;
3534         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3535
3536         if (info->line < MAX_DEVICES) {
3537                 if (maxframe[info->line])
3538                         info->max_frame_size = maxframe[info->line];
3539         }
3540
3541         slgt_device_count++;
3542
3543         if (!slgt_device_list)
3544                 slgt_device_list = info;
3545         else {
3546                 struct slgt_info *current_dev = slgt_device_list;
3547                 while(current_dev->next_device)
3548                         current_dev = current_dev->next_device;
3549                 current_dev->next_device = info;
3550         }
3551
3552         if (info->max_frame_size < 4096)
3553                 info->max_frame_size = 4096;
3554         else if (info->max_frame_size > 65535)
3555                 info->max_frame_size = 65535;
3556
3557         switch(info->pdev->device) {
3558         case SYNCLINK_GT_DEVICE_ID:
3559                 devstr = "GT";
3560                 break;
3561         case SYNCLINK_GT2_DEVICE_ID:
3562                 devstr = "GT2";
3563                 break;
3564         case SYNCLINK_GT4_DEVICE_ID:
3565                 devstr = "GT4";
3566                 break;
3567         case SYNCLINK_AC_DEVICE_ID:
3568                 devstr = "AC";
3569                 info->params.mode = MGSL_MODE_ASYNC;
3570                 break;
3571         default:
3572                 devstr = "(unknown model)";
3573         }
3574         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3575                 devstr, info->device_name, info->phys_reg_addr,
3576                 info->irq_level, info->max_frame_size);
3577
3578 #if SYNCLINK_GENERIC_HDLC
3579         hdlcdev_init(info);
3580 #endif
3581 }
3582
3583 static const struct tty_port_operations slgt_port_ops = {
3584         .carrier_raised = carrier_raised,
3585         .dtr_rts = dtr_rts,
3586 };
3587
3588 /*
3589  *  allocate device instance structure, return NULL on failure
3590  */
3591 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3592 {
3593         struct slgt_info *info;
3594
3595         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3596
3597         if (!info) {
3598                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3599                         driver_name, adapter_num, port_num));
3600         } else {
3601                 tty_port_init(&info->port);
3602                 info->port.ops = &slgt_port_ops;
3603                 info->magic = MGSL_MAGIC;
3604                 INIT_WORK(&info->task, bh_handler);
3605                 info->max_frame_size = 4096;
3606                 info->base_clock = 14745600;
3607                 info->rbuf_fill_level = DMABUFSIZE;
3608                 info->port.close_delay = 5*HZ/10;
3609                 info->port.closing_wait = 30*HZ;
3610                 init_waitqueue_head(&info->status_event_wait_q);
3611                 init_waitqueue_head(&info->event_wait_q);
3612                 spin_lock_init(&info->netlock);
3613                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3614                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3615                 info->adapter_num = adapter_num;
3616                 info->port_num = port_num;
3617
3618                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3619                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3620
3621                 /* Copy configuration info to device instance data */
3622                 info->pdev = pdev;
3623                 info->irq_level = pdev->irq;
3624                 info->phys_reg_addr = pci_resource_start(pdev,0);
3625
3626                 info->bus_type = MGSL_BUS_TYPE_PCI;
3627                 info->irq_flags = IRQF_SHARED;
3628
3629                 info->init_error = -1; /* assume error, set to 0 on successful init */
3630         }
3631
3632         return info;
3633 }
3634
3635 static void device_init(int adapter_num, struct pci_dev *pdev)
3636 {
3637         struct slgt_info *port_array[SLGT_MAX_PORTS];
3638         int i;
3639         int port_count = 1;
3640
3641         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3642                 port_count = 2;
3643         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3644                 port_count = 4;
3645
3646         /* allocate device instances for all ports */
3647         for (i=0; i < port_count; ++i) {
3648                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3649                 if (port_array[i] == NULL) {
3650                         for (--i; i >= 0; --i)
3651                                 kfree(port_array[i]);
3652                         return;
3653                 }
3654         }
3655
3656         /* give copy of port_array to all ports and add to device list  */
3657         for (i=0; i < port_count; ++i) {
3658                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3659                 add_device(port_array[i]);
3660                 port_array[i]->port_count = port_count;
3661                 spin_lock_init(&port_array[i]->lock);
3662         }
3663
3664         /* Allocate and claim adapter resources */
3665         if (!claim_resources(port_array[0])) {
3666
3667                 alloc_dma_bufs(port_array[0]);
3668
3669                 /* copy resource information from first port to others */
3670                 for (i = 1; i < port_count; ++i) {
3671                         port_array[i]->irq_level = port_array[0]->irq_level;
3672                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3673                         alloc_dma_bufs(port_array[i]);
3674                 }
3675
3676                 if (request_irq(port_array[0]->irq_level,
3677                                         slgt_interrupt,
3678                                         port_array[0]->irq_flags,
3679                                         port_array[0]->device_name,
3680                                         port_array[0]) < 0) {
3681                         DBGERR(("%s request_irq failed IRQ=%d\n",
3682                                 port_array[0]->device_name,
3683                                 port_array[0]->irq_level));
3684                 } else {
3685                         port_array[0]->irq_requested = true;
3686                         adapter_test(port_array[0]);
3687                         for (i=1 ; i < port_count ; i++) {
3688                                 port_array[i]->init_error = port_array[0]->init_error;
3689                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3690                         }
3691                 }
3692         }
3693
3694         for (i=0; i < port_count; ++i)
3695                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3696 }
3697
3698 static int __devinit init_one(struct pci_dev *dev,
3699                               const struct pci_device_id *ent)
3700 {
3701         if (pci_enable_device(dev)) {
3702                 printk("error enabling pci device %p\n", dev);
3703                 return -EIO;
3704         }
3705         pci_set_master(dev);
3706         device_init(slgt_device_count, dev);
3707         return 0;
3708 }
3709
3710 static void __devexit remove_one(struct pci_dev *dev)
3711 {
3712 }
3713
3714 static const struct tty_operations ops = {
3715         .open = open,
3716         .close = close,
3717         .write = write,
3718         .put_char = put_char,
3719         .flush_chars = flush_chars,
3720         .write_room = write_room,
3721         .chars_in_buffer = chars_in_buffer,
3722         .flush_buffer = flush_buffer,
3723         .ioctl = ioctl,
3724         .compat_ioctl = slgt_compat_ioctl,
3725         .throttle = throttle,
3726         .unthrottle = unthrottle,
3727         .send_xchar = send_xchar,
3728         .break_ctl = set_break,
3729         .wait_until_sent = wait_until_sent,
3730         .set_termios = set_termios,
3731         .stop = tx_hold,
3732         .start = tx_release,
3733         .hangup = hangup,
3734         .tiocmget = tiocmget,
3735         .tiocmset = tiocmset,
3736         .get_icount = get_icount,
3737         .proc_fops = &synclink_gt_proc_fops,
3738 };
3739
3740 static void slgt_cleanup(void)
3741 {
3742         int rc;
3743         struct slgt_info *info;
3744         struct slgt_info *tmp;
3745
3746         printk(KERN_INFO "unload %s\n", driver_name);
3747
3748         if (serial_driver) {
3749                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3750                         tty_unregister_device(serial_driver, info->line);
3751                 if ((rc = tty_unregister_driver(serial_driver)))
3752                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3753                 put_tty_driver(serial_driver);
3754         }
3755
3756         /* reset devices */
3757         info = slgt_device_list;
3758         while(info) {
3759                 reset_port(info);
3760                 info = info->next_device;
3761         }
3762
3763         /* release devices */
3764         info = slgt_device_list;
3765         while(info) {
3766 #if SYNCLINK_GENERIC_HDLC
3767                 hdlcdev_exit(info);
3768 #endif
3769                 free_dma_bufs(info);
3770                 free_tmp_rbuf(info);
3771                 if (info->port_num == 0)
3772                         release_resources(info);
3773                 tmp = info;
3774                 info = info->next_device;
3775                 kfree(tmp);
3776         }
3777
3778         if (pci_registered)
3779                 pci_unregister_driver(&pci_driver);
3780 }
3781
3782 /*
3783  *  Driver initialization entry point.
3784  */
3785 static int __init slgt_init(void)
3786 {
3787         int rc;
3788
3789         printk(KERN_INFO "%s\n", driver_name);
3790
3791         serial_driver = alloc_tty_driver(MAX_DEVICES);
3792         if (!serial_driver) {
3793                 printk("%s can't allocate tty driver\n", driver_name);
3794                 return -ENOMEM;
3795         }
3796
3797         /* Initialize the tty_driver structure */
3798
3799         serial_driver->owner = THIS_MODULE;
3800         serial_driver->driver_name = tty_driver_name;
3801         serial_driver->name = tty_dev_prefix;
3802         serial_driver->major = ttymajor;
3803         serial_driver->minor_start = 64;
3804         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3805         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3806         serial_driver->init_termios = tty_std_termios;
3807         serial_driver->init_termios.c_cflag =
3808                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3809         serial_driver->init_termios.c_ispeed = 9600;
3810         serial_driver->init_termios.c_ospeed = 9600;
3811         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3812         tty_set_operations(serial_driver, &ops);
3813         if ((rc = tty_register_driver(serial_driver)) < 0) {
3814                 DBGERR(("%s can't register serial driver\n", driver_name));
3815                 put_tty_driver(serial_driver);
3816                 serial_driver = NULL;
3817                 goto error;
3818         }
3819
3820         printk(KERN_INFO "%s, tty major#%d\n",
3821                driver_name, serial_driver->major);
3822
3823         slgt_device_count = 0;
3824         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3825                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3826                 goto error;
3827         }
3828         pci_registered = true;
3829
3830         if (!slgt_device_list)
3831                 printk("%s no devices found\n",driver_name);
3832
3833         return 0;
3834
3835 error:
3836         slgt_cleanup();
3837         return rc;
3838 }
3839
3840 static void __exit slgt_exit(void)
3841 {
3842         slgt_cleanup();
3843 }
3844
3845 module_init(slgt_init);
3846 module_exit(slgt_exit);
3847
3848 /*
3849  * register access routines
3850  */
3851
3852 #define CALC_REGADDR() \
3853         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3854         if (addr >= 0x80) \
3855                 reg_addr += (info->port_num) * 32; \
3856         else if (addr >= 0x40)  \
3857                 reg_addr += (info->port_num) * 16;
3858
3859 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3860 {
3861         CALC_REGADDR();
3862         return readb((void __iomem *)reg_addr);
3863 }
3864
3865 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3866 {
3867         CALC_REGADDR();
3868         writeb(value, (void __iomem *)reg_addr);
3869 }
3870
3871 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3872 {
3873         CALC_REGADDR();
3874         return readw((void __iomem *)reg_addr);
3875 }
3876
3877 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3878 {
3879         CALC_REGADDR();
3880         writew(value, (void __iomem *)reg_addr);
3881 }
3882
3883 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3884 {
3885         CALC_REGADDR();
3886         return readl((void __iomem *)reg_addr);
3887 }
3888
3889 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3890 {
3891         CALC_REGADDR();
3892         writel(value, (void __iomem *)reg_addr);
3893 }
3894
3895 static void rdma_reset(struct slgt_info *info)
3896 {
3897         unsigned int i;
3898
3899         /* set reset bit */
3900         wr_reg32(info, RDCSR, BIT1);
3901
3902         /* wait for enable bit cleared */
3903         for(i=0 ; i < 1000 ; i++)
3904                 if (!(rd_reg32(info, RDCSR) & BIT0))
3905                         break;
3906 }
3907
3908 static void tdma_reset(struct slgt_info *info)
3909 {
3910         unsigned int i;
3911
3912         /* set reset bit */
3913         wr_reg32(info, TDCSR, BIT1);
3914
3915         /* wait for enable bit cleared */
3916         for(i=0 ; i < 1000 ; i++)
3917                 if (!(rd_reg32(info, TDCSR) & BIT0))
3918                         break;
3919 }
3920
3921 /*
3922  * enable internal loopback
3923  * TxCLK and RxCLK are generated from BRG
3924  * and TxD is looped back to RxD internally.
3925  */
3926 static void enable_loopback(struct slgt_info *info)
3927 {
3928         /* SCR (serial control) BIT2=looopback enable */
3929         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3930
3931         if (info->params.mode != MGSL_MODE_ASYNC) {
3932                 /* CCR (clock control)
3933                  * 07..05  tx clock source (010 = BRG)
3934                  * 04..02  rx clock source (010 = BRG)
3935                  * 01      auxclk enable   (0 = disable)
3936                  * 00      BRG enable      (1 = enable)
3937                  *
3938                  * 0100 1001
3939                  */
3940                 wr_reg8(info, CCR, 0x49);
3941
3942                 /* set speed if available, otherwise use default */
3943                 if (info->params.clock_speed)
3944                         set_rate(info, info->params.clock_speed);
3945                 else
3946                         set_rate(info, 3686400);
3947         }
3948 }
3949
3950 /*
3951  *  set baud rate generator to specified rate
3952  */
3953 static void set_rate(struct slgt_info *info, u32 rate)
3954 {
3955         unsigned int div;
3956         unsigned int osc = info->base_clock;
3957
3958         /* div = osc/rate - 1
3959          *
3960          * Round div up if osc/rate is not integer to
3961          * force to next slowest rate.
3962          */
3963
3964         if (rate) {
3965                 div = osc/rate;
3966                 if (!(osc % rate) && div)
3967                         div--;
3968                 wr_reg16(info, BDR, (unsigned short)div);
3969         }
3970 }
3971
3972 static void rx_stop(struct slgt_info *info)
3973 {
3974         unsigned short val;
3975
3976         /* disable and reset receiver */
3977         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3978         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3979         wr_reg16(info, RCR, val);                  /* clear reset bit */
3980
3981         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3982
3983         /* clear pending rx interrupts */
3984         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3985
3986         rdma_reset(info);
3987
3988         info->rx_enabled = false;
3989         info->rx_restart = false;
3990 }
3991
3992 static void rx_start(struct slgt_info *info)
3993 {
3994         unsigned short val;
3995
3996         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3997
3998         /* clear pending rx overrun IRQ */
3999         wr_reg16(info, SSR, IRQ_RXOVER);
4000
4001         /* reset and disable receiver */
4002         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4003         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4004         wr_reg16(info, RCR, val);                  /* clear reset bit */
4005
4006         rdma_reset(info);
4007         reset_rbufs(info);
4008
4009         if (info->rx_pio) {
4010                 /* rx request when rx FIFO not empty */
4011                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4012                 slgt_irq_on(info, IRQ_RXDATA);
4013                 if (info->params.mode == MGSL_MODE_ASYNC) {
4014                         /* enable saving of rx status */
4015                         wr_reg32(info, RDCSR, BIT6);
4016                 }
4017         } else {
4018                 /* rx request when rx FIFO half full */
4019                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4020                 /* set 1st descriptor address */
4021                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4022
4023                 if (info->params.mode != MGSL_MODE_ASYNC) {
4024                         /* enable rx DMA and DMA interrupt */
4025                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4026                 } else {
4027                         /* enable saving of rx status, rx DMA and DMA interrupt */
4028                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4029                 }
4030         }
4031
4032         slgt_irq_on(info, IRQ_RXOVER);
4033
4034         /* enable receiver */
4035         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4036
4037         info->rx_restart = false;
4038         info->rx_enabled = true;
4039 }
4040
4041 static void tx_start(struct slgt_info *info)
4042 {
4043         if (!info->tx_enabled) {
4044                 wr_reg16(info, TCR,
4045                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4046                 info->tx_enabled = true;
4047         }
4048
4049         if (desc_count(info->tbufs[info->tbuf_start])) {
4050                 info->drop_rts_on_tx_done = false;
4051
4052                 if (info->params.mode != MGSL_MODE_ASYNC) {
4053                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4054                                 get_signals(info);
4055                                 if (!(info->signals & SerialSignal_RTS)) {
4056                                         info->signals |= SerialSignal_RTS;
4057                                         set_signals(info);
4058                                         info->drop_rts_on_tx_done = true;
4059                                 }
4060                         }
4061
4062                         slgt_irq_off(info, IRQ_TXDATA);
4063                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4064                         /* clear tx idle and underrun status bits */
4065                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4066                 } else {
4067                         slgt_irq_off(info, IRQ_TXDATA);
4068                         slgt_irq_on(info, IRQ_TXIDLE);
4069                         /* clear tx idle status bit */
4070                         wr_reg16(info, SSR, IRQ_TXIDLE);
4071                 }
4072                 /* set 1st descriptor address and start DMA */
4073                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4074                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4075                 info->tx_active = true;
4076         }
4077 }
4078
4079 static void tx_stop(struct slgt_info *info)
4080 {
4081         unsigned short val;
4082
4083         del_timer(&info->tx_timer);
4084
4085         tdma_reset(info);
4086
4087         /* reset and disable transmitter */
4088         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4089         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4090
4091         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4092
4093         /* clear tx idle and underrun status bit */
4094         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4095
4096         reset_tbufs(info);
4097
4098         info->tx_enabled = false;
4099         info->tx_active = false;
4100 }
4101
4102 static void reset_port(struct slgt_info *info)
4103 {
4104         if (!info->reg_addr)
4105                 return;
4106
4107         tx_stop(info);
4108         rx_stop(info);
4109
4110         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4111         set_signals(info);
4112
4113         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4114 }
4115
4116 static void reset_adapter(struct slgt_info *info)
4117 {
4118         int i;
4119         for (i=0; i < info->port_count; ++i) {
4120                 if (info->port_array[i])
4121                         reset_port(info->port_array[i]);
4122         }
4123 }
4124
4125 static void async_mode(struct slgt_info *info)
4126 {
4127         unsigned short val;
4128
4129         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4130         tx_stop(info);
4131         rx_stop(info);
4132
4133         /* TCR (tx control)
4134          *
4135          * 15..13  mode, 010=async
4136          * 12..10  encoding, 000=NRZ
4137          * 09      parity enable
4138          * 08      1=odd parity, 0=even parity
4139          * 07      1=RTS driver control
4140          * 06      1=break enable
4141          * 05..04  character length
4142          *         00=5 bits
4143          *         01=6 bits
4144          *         10=7 bits
4145          *         11=8 bits
4146          * 03      0=1 stop bit, 1=2 stop bits
4147          * 02      reset
4148          * 01      enable
4149          * 00      auto-CTS enable
4150          */
4151         val = 0x4000;
4152
4153         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4154                 val |= BIT7;
4155
4156         if (info->params.parity != ASYNC_PARITY_NONE) {
4157                 val |= BIT9;
4158                 if (info->params.parity == ASYNC_PARITY_ODD)
4159                         val |= BIT8;
4160         }
4161
4162         switch (info->params.data_bits)
4163         {
4164         case 6: val |= BIT4; break;
4165         case 7: val |= BIT5; break;
4166         case 8: val |= BIT5 + BIT4; break;
4167         }
4168
4169         if (info->params.stop_bits != 1)
4170                 val |= BIT3;
4171
4172         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4173                 val |= BIT0;
4174
4175         wr_reg16(info, TCR, val);
4176
4177         /* RCR (rx control)
4178          *
4179          * 15..13  mode, 010=async
4180          * 12..10  encoding, 000=NRZ
4181          * 09      parity enable
4182          * 08      1=odd parity, 0=even parity
4183          * 07..06  reserved, must be 0
4184          * 05..04  character length
4185          *         00=5 bits
4186          *         01=6 bits
4187          *         10=7 bits
4188          *         11=8 bits
4189          * 03      reserved, must be zero
4190          * 02      reset
4191          * 01      enable
4192          * 00      auto-DCD enable
4193          */
4194         val = 0x4000;
4195
4196         if (info->params.parity != ASYNC_PARITY_NONE) {
4197                 val |= BIT9;
4198                 if (info->params.parity == ASYNC_PARITY_ODD)
4199                         val |= BIT8;
4200         }
4201
4202         switch (info->params.data_bits)
4203         {
4204         case 6: val |= BIT4; break;
4205         case 7: val |= BIT5; break;
4206         case 8: val |= BIT5 + BIT4; break;
4207         }
4208
4209         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4210                 val |= BIT0;
4211
4212         wr_reg16(info, RCR, val);
4213
4214         /* CCR (clock control)
4215          *
4216          * 07..05  011 = tx clock source is BRG/16
4217          * 04..02  010 = rx clock source is BRG
4218          * 01      0 = auxclk disabled
4219          * 00      1 = BRG enabled
4220          *
4221          * 0110 1001
4222          */
4223         wr_reg8(info, CCR, 0x69);
4224
4225         msc_set_vcr(info);
4226
4227         /* SCR (serial control)
4228          *
4229          * 15  1=tx req on FIFO half empty
4230          * 14  1=rx req on FIFO half full
4231          * 13  tx data  IRQ enable
4232          * 12  tx idle  IRQ enable
4233          * 11  rx break on IRQ enable
4234          * 10  rx data  IRQ enable
4235          * 09  rx break off IRQ enable
4236          * 08  overrun  IRQ enable
4237          * 07  DSR      IRQ enable
4238          * 06  CTS      IRQ enable
4239          * 05  DCD      IRQ enable
4240          * 04  RI       IRQ enable
4241          * 03  0=16x sampling, 1=8x sampling
4242          * 02  1=txd->rxd internal loopback enable
4243          * 01  reserved, must be zero
4244          * 00  1=master IRQ enable
4245          */
4246         val = BIT15 + BIT14 + BIT0;
4247         /* JCR[8] : 1 = x8 async mode feature available */
4248         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4249             ((info->base_clock < (info->params.data_rate * 16)) ||
4250              (info->base_clock % (info->params.data_rate * 16)))) {
4251                 /* use 8x sampling */
4252                 val |= BIT3;
4253                 set_rate(info, info->params.data_rate * 8);
4254         } else {
4255                 /* use 16x sampling */
4256                 set_rate(info, info->params.data_rate * 16);
4257         }
4258         wr_reg16(info, SCR, val);
4259
4260         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4261
4262         if (info->params.loopback)
4263                 enable_loopback(info);
4264 }
4265
4266 static void sync_mode(struct slgt_info *info)
4267 {
4268         unsigned short val;
4269
4270         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4271         tx_stop(info);
4272         rx_stop(info);
4273
4274         /* TCR (tx control)
4275          *
4276          * 15..13  mode
4277          *         000=HDLC/SDLC
4278          *         001=raw bit synchronous
4279          *         010=asynchronous/isochronous
4280          *         011=monosync byte synchronous
4281          *         100=bisync byte synchronous
4282          *         101=xsync byte synchronous
4283          * 12..10  encoding
4284          * 09      CRC enable
4285          * 08      CRC32
4286          * 07      1=RTS driver control
4287          * 06      preamble enable
4288          * 05..04  preamble length
4289          * 03      share open/close flag
4290          * 02      reset
4291          * 01      enable
4292          * 00      auto-CTS enable
4293          */
4294         val = BIT2;
4295
4296         switch(info->params.mode) {
4297         case MGSL_MODE_XSYNC:
4298                 val |= BIT15 + BIT13;
4299                 break;
4300         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4301         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4302         case MGSL_MODE_RAW:      val |= BIT13; break;
4303         }
4304         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4305                 val |= BIT7;
4306
4307         switch(info->params.encoding)
4308         {
4309         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4310         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4311         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4312         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4313         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4314         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4315         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4316         }
4317
4318         switch (info->params.crc_type & HDLC_CRC_MASK)
4319         {
4320         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4321         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4322         }
4323
4324         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4325                 val |= BIT6;
4326
4327         switch (info->params.preamble_length)
4328         {
4329         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4330         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4331         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4332         }
4333
4334         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4335                 val |= BIT0;
4336
4337         wr_reg16(info, TCR, val);
4338
4339         /* TPR (transmit preamble) */
4340
4341         switch (info->params.preamble)
4342         {
4343         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4344         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4345         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4346         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4347         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4348         default:                          val = 0x7e; break;
4349         }
4350         wr_reg8(info, TPR, (unsigned char)val);
4351
4352         /* RCR (rx control)
4353          *
4354          * 15..13  mode
4355          *         000=HDLC/SDLC
4356          *         001=raw bit synchronous
4357          *         010=asynchronous/isochronous
4358          *         011=monosync byte synchronous
4359          *         100=bisync byte synchronous
4360          *         101=xsync byte synchronous
4361          * 12..10  encoding
4362          * 09      CRC enable
4363          * 08      CRC32
4364          * 07..03  reserved, must be 0
4365          * 02      reset
4366          * 01      enable
4367          * 00      auto-DCD enable
4368          */
4369         val = 0;
4370
4371         switch(info->params.mode) {
4372         case MGSL_MODE_XSYNC:
4373                 val |= BIT15 + BIT13;
4374                 break;
4375         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4376         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4377         case MGSL_MODE_RAW:      val |= BIT13; break;
4378         }
4379
4380         switch(info->params.encoding)
4381         {
4382         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4383         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4384         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4385         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4386         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4387         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4388         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4389         }
4390
4391         switch (info->params.crc_type & HDLC_CRC_MASK)
4392         {
4393         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4394         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4395         }
4396
4397         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4398                 val |= BIT0;
4399
4400         wr_reg16(info, RCR, val);
4401
4402         /* CCR (clock control)
4403          *
4404          * 07..05  tx clock source
4405          * 04..02  rx clock source
4406          * 01      auxclk enable
4407          * 00      BRG enable
4408          */
4409         val = 0;
4410
4411         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4412         {
4413                 // when RxC source is DPLL, BRG generates 16X DPLL
4414                 // reference clock, so take TxC from BRG/16 to get
4415                 // transmit clock at actual data rate
4416                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4417                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4418                 else
4419                         val |= BIT6;    /* 010, txclk = BRG */
4420         }
4421         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4422                 val |= BIT7;    /* 100, txclk = DPLL Input */
4423         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4424                 val |= BIT5;    /* 001, txclk = RXC Input */
4425
4426         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4427                 val |= BIT3;    /* 010, rxclk = BRG */
4428         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4429                 val |= BIT4;    /* 100, rxclk = DPLL */
4430         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4431                 val |= BIT2;    /* 001, rxclk = TXC Input */
4432
4433         if (info->params.clock_speed)
4434                 val |= BIT1 + BIT0;
4435
4436         wr_reg8(info, CCR, (unsigned char)val);
4437
4438         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4439         {
4440                 // program DPLL mode
4441                 switch(info->params.encoding)
4442                 {
4443                 case HDLC_ENCODING_BIPHASE_MARK:
4444                 case HDLC_ENCODING_BIPHASE_SPACE:
4445                         val = BIT7; break;
4446                 case HDLC_ENCODING_BIPHASE_LEVEL:
4447                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4448                         val = BIT7 + BIT6; break;
4449                 default: val = BIT6;    // NRZ encodings
4450                 }
4451                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4452
4453                 // DPLL requires a 16X reference clock from BRG
4454                 set_rate(info, info->params.clock_speed * 16);
4455         }
4456         else
4457                 set_rate(info, info->params.clock_speed);
4458
4459         tx_set_idle(info);
4460
4461         msc_set_vcr(info);
4462
4463         /* SCR (serial control)
4464          *
4465          * 15  1=tx req on FIFO half empty
4466          * 14  1=rx req on FIFO half full
4467          * 13  tx data  IRQ enable
4468          * 12  tx idle  IRQ enable
4469          * 11  underrun IRQ enable
4470          * 10  rx data  IRQ enable
4471          * 09  rx idle  IRQ enable
4472          * 08  overrun  IRQ enable
4473          * 07  DSR      IRQ enable
4474          * 06  CTS      IRQ enable
4475          * 05  DCD      IRQ enable
4476          * 04  RI       IRQ enable
4477          * 03  reserved, must be zero
4478          * 02  1=txd->rxd internal loopback enable
4479          * 01  reserved, must be zero
4480          * 00  1=master IRQ enable
4481          */
4482         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4483
4484         if (info->params.loopback)
4485                 enable_loopback(info);
4486 }
4487
4488 /*
4489  *  set transmit idle mode
4490  */
4491 static void tx_set_idle(struct slgt_info *info)
4492 {
4493         unsigned char val;
4494         unsigned short tcr;
4495
4496         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4497          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4498          */
4499         tcr = rd_reg16(info, TCR);
4500         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4501                 /* disable preamble, set idle size to 16 bits */
4502                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4503                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4504                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4505         } else if (!(tcr & BIT6)) {
4506                 /* preamble is disabled, set idle size to 8 bits */
4507                 tcr &= ~(BIT5 + BIT4);
4508         }
4509         wr_reg16(info, TCR, tcr);
4510
4511         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4512                 /* LSB of custom tx idle specified in tx idle register */
4513                 val = (unsigned char)(info->idle_mode & 0xff);
4514         } else {
4515                 /* standard 8 bit idle patterns */
4516                 switch(info->idle_mode)
4517                 {
4518                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4519                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4520                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4521                 case HDLC_TXIDLE_ZEROS:
4522                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4523                 default:                         val = 0xff;
4524                 }
4525         }
4526
4527         wr_reg8(info, TIR, val);
4528 }
4529
4530 /*
4531  * get state of V24 status (input) signals
4532  */
4533 static void get_signals(struct slgt_info *info)
4534 {
4535         unsigned short status = rd_reg16(info, SSR);
4536
4537         /* clear all serial signals except DTR and RTS */
4538         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4539
4540         if (status & BIT3)
4541                 info->signals |= SerialSignal_DSR;
4542         if (status & BIT2)
4543                 info->signals |= SerialSignal_CTS;
4544         if (status & BIT1)
4545                 info->signals |= SerialSignal_DCD;
4546         if (status & BIT0)
4547                 info->signals |= SerialSignal_RI;
4548 }
4549
4550 /*
4551  * set V.24 Control Register based on current configuration
4552  */
4553 static void msc_set_vcr(struct slgt_info *info)
4554 {
4555         unsigned char val = 0;
4556
4557         /* VCR (V.24 control)
4558          *
4559          * 07..04  serial IF select
4560          * 03      DTR
4561          * 02      RTS
4562          * 01      LL
4563          * 00      RL
4564          */
4565
4566         switch(info->if_mode & MGSL_INTERFACE_MASK)
4567         {
4568         case MGSL_INTERFACE_RS232:
4569                 val |= BIT5; /* 0010 */
4570                 break;
4571         case MGSL_INTERFACE_V35:
4572                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4573                 break;
4574         case MGSL_INTERFACE_RS422:
4575                 val |= BIT6; /* 0100 */
4576                 break;
4577         }
4578
4579         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4580                 val |= BIT4;
4581         if (info->signals & SerialSignal_DTR)
4582                 val |= BIT3;
4583         if (info->signals & SerialSignal_RTS)
4584                 val |= BIT2;
4585         if (info->if_mode & MGSL_INTERFACE_LL)
4586                 val |= BIT1;
4587         if (info->if_mode & MGSL_INTERFACE_RL)
4588                 val |= BIT0;
4589         wr_reg8(info, VCR, val);
4590 }
4591
4592 /*
4593  * set state of V24 control (output) signals
4594  */
4595 static void set_signals(struct slgt_info *info)
4596 {
4597         unsigned char val = rd_reg8(info, VCR);
4598         if (info->signals & SerialSignal_DTR)
4599                 val |= BIT3;
4600         else
4601                 val &= ~BIT3;
4602         if (info->signals & SerialSignal_RTS)
4603                 val |= BIT2;
4604         else
4605                 val &= ~BIT2;
4606         wr_reg8(info, VCR, val);
4607 }
4608
4609 /*
4610  * free range of receive DMA buffers (i to last)
4611  */
4612 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4613 {
4614         int done = 0;
4615
4616         while(!done) {
4617                 /* reset current buffer for reuse */
4618                 info->rbufs[i].status = 0;
4619                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4620                 if (i == last)
4621                         done = 1;
4622                 if (++i == info->rbuf_count)
4623                         i = 0;
4624         }
4625         info->rbuf_current = i;
4626 }
4627
4628 /*
4629  * mark all receive DMA buffers as free
4630  */
4631 static void reset_rbufs(struct slgt_info *info)
4632 {
4633         free_rbufs(info, 0, info->rbuf_count - 1);
4634         info->rbuf_fill_index = 0;
4635         info->rbuf_fill_count = 0;
4636 }
4637
4638 /*
4639  * pass receive HDLC frame to upper layer
4640  *
4641  * return true if frame available, otherwise false
4642  */
4643 static bool rx_get_frame(struct slgt_info *info)
4644 {
4645         unsigned int start, end;
4646         unsigned short status;
4647         unsigned int framesize = 0;
4648         unsigned long flags;
4649         struct tty_struct *tty = info->port.tty;
4650         unsigned char addr_field = 0xff;
4651         unsigned int crc_size = 0;
4652
4653         switch (info->params.crc_type & HDLC_CRC_MASK) {
4654         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4655         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4656         }
4657
4658 check_again:
4659
4660         framesize = 0;
4661         addr_field = 0xff;
4662         start = end = info->rbuf_current;
4663
4664         for (;;) {
4665                 if (!desc_complete(info->rbufs[end]))
4666                         goto cleanup;
4667
4668                 if (framesize == 0 && info->params.addr_filter != 0xff)
4669                         addr_field = info->rbufs[end].buf[0];
4670
4671                 framesize += desc_count(info->rbufs[end]);
4672
4673                 if (desc_eof(info->rbufs[end]))
4674                         break;
4675
4676                 if (++end == info->rbuf_count)
4677                         end = 0;
4678
4679                 if (end == info->rbuf_current) {
4680                         if (info->rx_enabled){
4681                                 spin_lock_irqsave(&info->lock,flags);
4682                                 rx_start(info);
4683                                 spin_unlock_irqrestore(&info->lock,flags);
4684                         }
4685                         goto cleanup;
4686                 }
4687         }
4688
4689         /* status
4690          *
4691          * 15      buffer complete
4692          * 14..06  reserved
4693          * 05..04  residue
4694          * 02      eof (end of frame)
4695          * 01      CRC error
4696          * 00      abort
4697          */
4698         status = desc_status(info->rbufs[end]);
4699
4700         /* ignore CRC bit if not using CRC (bit is undefined) */
4701         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4702                 status &= ~BIT1;
4703
4704         if (framesize == 0 ||
4705                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4706                 free_rbufs(info, start, end);
4707                 goto check_again;
4708         }
4709
4710         if (framesize < (2 + crc_size) || status & BIT0) {
4711                 info->icount.rxshort++;
4712                 framesize = 0;
4713         } else if (status & BIT1) {
4714                 info->icount.rxcrc++;
4715                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4716                         framesize = 0;
4717         }
4718
4719 #if SYNCLINK_GENERIC_HDLC
4720         if (framesize == 0) {
4721                 info->netdev->stats.rx_errors++;
4722                 info->netdev->stats.rx_frame_errors++;
4723         }
4724 #endif
4725
4726         DBGBH(("%s rx frame status=%04X size=%d\n",
4727                 info->device_name, status, framesize));
4728         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4729
4730         if (framesize) {
4731                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4732                         framesize -= crc_size;
4733                         crc_size = 0;
4734                 }
4735
4736                 if (framesize > info->max_frame_size + crc_size)
4737                         info->icount.rxlong++;
4738                 else {
4739                         /* copy dma buffer(s) to contiguous temp buffer */
4740                         int copy_count = framesize;
4741                         int i = start;
4742                         unsigned char *p = info->tmp_rbuf;
4743                         info->tmp_rbuf_count = framesize;
4744
4745                         info->icount.rxok++;
4746
4747                         while(copy_count) {
4748                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4749                                 memcpy(p, info->rbufs[i].buf, partial_count);
4750                                 p += partial_count;
4751                                 copy_count -= partial_count;
4752                                 if (++i == info->rbuf_count)
4753                                         i = 0;
4754                         }
4755
4756                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4757                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4758                                 framesize++;
4759                         }
4760
4761 #if SYNCLINK_GENERIC_HDLC
4762                         if (info->netcount)
4763                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4764                         else
4765 #endif
4766                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4767                 }
4768         }
4769         free_rbufs(info, start, end);
4770         return true;
4771
4772 cleanup:
4773         return false;
4774 }
4775
4776 /*
4777  * pass receive buffer (RAW synchronous mode) to tty layer
4778  * return true if buffer available, otherwise false
4779  */
4780 static bool rx_get_buf(struct slgt_info *info)
4781 {
4782         unsigned int i = info->rbuf_current;
4783         unsigned int count;
4784
4785         if (!desc_complete(info->rbufs[i]))
4786                 return false;
4787         count = desc_count(info->rbufs[i]);
4788         switch(info->params.mode) {
4789         case MGSL_MODE_MONOSYNC:
4790         case MGSL_MODE_BISYNC:
4791         case MGSL_MODE_XSYNC:
4792                 /* ignore residue in byte synchronous modes */
4793                 if (desc_residue(info->rbufs[i]))
4794                         count--;
4795                 break;
4796         }
4797         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4798         DBGINFO(("rx_get_buf size=%d\n", count));
4799         if (count)
4800                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4801                                   info->flag_buf, count);
4802         free_rbufs(info, i, i);
4803         return true;
4804 }
4805
4806 static void reset_tbufs(struct slgt_info *info)
4807 {
4808         unsigned int i;
4809         info->tbuf_current = 0;
4810         for (i=0 ; i < info->tbuf_count ; i++) {
4811                 info->tbufs[i].status = 0;
4812                 info->tbufs[i].count  = 0;
4813         }
4814 }
4815
4816 /*
4817  * return number of free transmit DMA buffers
4818  */
4819 static unsigned int free_tbuf_count(struct slgt_info *info)
4820 {
4821         unsigned int count = 0;
4822         unsigned int i = info->tbuf_current;
4823
4824         do
4825         {
4826                 if (desc_count(info->tbufs[i]))
4827                         break; /* buffer in use */
4828                 ++count;
4829                 if (++i == info->tbuf_count)
4830                         i=0;
4831         } while (i != info->tbuf_current);
4832
4833         /* if tx DMA active, last zero count buffer is in use */
4834         if (count && (rd_reg32(info, TDCSR) & BIT0))
4835                 --count;
4836
4837         return count;
4838 }
4839
4840 /*
4841  * return number of bytes in unsent transmit DMA buffers
4842  * and the serial controller tx FIFO
4843  */
4844 static unsigned int tbuf_bytes(struct slgt_info *info)
4845 {
4846         unsigned int total_count = 0;
4847         unsigned int i = info->tbuf_current;
4848         unsigned int reg_value;
4849         unsigned int count;
4850         unsigned int active_buf_count = 0;
4851
4852         /*
4853          * Add descriptor counts for all tx DMA buffers.
4854          * If count is zero (cleared by DMA controller after read),
4855          * the buffer is complete or is actively being read from.
4856          *
4857          * Record buf_count of last buffer with zero count starting
4858          * from current ring position. buf_count is mirror
4859          * copy of count and is not cleared by serial controller.
4860          * If DMA controller is active, that buffer is actively
4861          * being read so add to total.
4862          */
4863         do {
4864                 count = desc_count(info->tbufs[i]);
4865                 if (count)
4866                         total_count += count;
4867                 else if (!total_count)
4868                         active_buf_count = info->tbufs[i].buf_count;
4869                 if (++i == info->tbuf_count)
4870                         i = 0;
4871         } while (i != info->tbuf_current);
4872
4873         /* read tx DMA status register */
4874         reg_value = rd_reg32(info, TDCSR);
4875
4876         /* if tx DMA active, last zero count buffer is in use */
4877         if (reg_value & BIT0)
4878                 total_count += active_buf_count;
4879
4880         /* add tx FIFO count = reg_value[15..8] */
4881         total_count += (reg_value >> 8) & 0xff;
4882
4883         /* if transmitter active add one byte for shift register */
4884         if (info->tx_active)
4885                 total_count++;
4886
4887         return total_count;
4888 }
4889
4890 /*
4891  * load data into transmit DMA buffer ring and start transmitter if needed
4892  * return true if data accepted, otherwise false (buffers full)
4893  */
4894 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4895 {
4896         unsigned short count;
4897         unsigned int i;
4898         struct slgt_desc *d;
4899
4900         /* check required buffer space */
4901         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4902                 return false;
4903
4904         DBGDATA(info, buf, size, "tx");
4905
4906         /*
4907          * copy data to one or more DMA buffers in circular ring
4908          * tbuf_start   = first buffer for this data
4909          * tbuf_current = next free buffer
4910          *
4911          * Copy all data before making data visible to DMA controller by
4912          * setting descriptor count of the first buffer.
4913          * This prevents an active DMA controller from reading the first DMA
4914          * buffers of a frame and stopping before the final buffers are filled.
4915          */
4916
4917         info->tbuf_start = i = info->tbuf_current;
4918
4919         while (size) {
4920                 d = &info->tbufs[i];
4921
4922                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4923                 memcpy(d->buf, buf, count);
4924
4925                 size -= count;
4926                 buf  += count;
4927
4928                 /*
4929                  * set EOF bit for last buffer of HDLC frame or
4930                  * for every buffer in raw mode
4931                  */
4932                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4933                     info->params.mode == MGSL_MODE_RAW)
4934                         set_desc_eof(*d, 1);
4935                 else
4936                         set_desc_eof(*d, 0);
4937
4938                 /* set descriptor count for all but first buffer */
4939                 if (i != info->tbuf_start)
4940                         set_desc_count(*d, count);
4941                 d->buf_count = count;
4942
4943                 if (++i == info->tbuf_count)
4944                         i = 0;
4945         }
4946
4947         info->tbuf_current = i;
4948
4949         /* set first buffer count to make new data visible to DMA controller */
4950         d = &info->tbufs[info->tbuf_start];
4951         set_desc_count(*d, d->buf_count);
4952
4953         /* start transmitter if needed and update transmit timeout */
4954         if (!info->tx_active)
4955                 tx_start(info);
4956         update_tx_timer(info);
4957
4958         return true;
4959 }
4960
4961 static int register_test(struct slgt_info *info)
4962 {
4963         static unsigned short patterns[] =
4964                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4965         static unsigned int count = ARRAY_SIZE(patterns);
4966         unsigned int i;
4967         int rc = 0;
4968
4969         for (i=0 ; i < count ; i++) {
4970                 wr_reg16(info, TIR, patterns[i]);
4971                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4972                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4973                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4974                         rc = -ENODEV;
4975                         break;
4976                 }
4977         }
4978         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4979         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4980         return rc;
4981 }
4982
4983 static int irq_test(struct slgt_info *info)
4984 {
4985         unsigned long timeout;
4986         unsigned long flags;
4987         struct tty_struct *oldtty = info->port.tty;
4988         u32 speed = info->params.data_rate;
4989
4990         info->params.data_rate = 921600;
4991         info->port.tty = NULL;
4992
4993         spin_lock_irqsave(&info->lock, flags);
4994         async_mode(info);
4995         slgt_irq_on(info, IRQ_TXIDLE);
4996
4997         /* enable transmitter */
4998         wr_reg16(info, TCR,
4999                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
5000
5001         /* write one byte and wait for tx idle */
5002         wr_reg16(info, TDR, 0);
5003
5004         /* assume failure */
5005         info->init_error = DiagStatus_IrqFailure;
5006         info->irq_occurred = false;
5007
5008         spin_unlock_irqrestore(&info->lock, flags);
5009
5010         timeout=100;
5011         while(timeout-- && !info->irq_occurred)
5012                 msleep_interruptible(10);
5013
5014         spin_lock_irqsave(&info->lock,flags);
5015         reset_port(info);
5016         spin_unlock_irqrestore(&info->lock,flags);
5017
5018         info->params.data_rate = speed;
5019         info->port.tty = oldtty;
5020
5021         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5022         return info->irq_occurred ? 0 : -ENODEV;
5023 }
5024
5025 static int loopback_test_rx(struct slgt_info *info)
5026 {
5027         unsigned char *src, *dest;
5028         int count;
5029
5030         if (desc_complete(info->rbufs[0])) {
5031                 count = desc_count(info->rbufs[0]);
5032                 src   = info->rbufs[0].buf;
5033                 dest  = info->tmp_rbuf;
5034
5035                 for( ; count ; count-=2, src+=2) {
5036                         /* src=data byte (src+1)=status byte */
5037                         if (!(*(src+1) & (BIT9 + BIT8))) {
5038                                 *dest = *src;
5039                                 dest++;
5040                                 info->tmp_rbuf_count++;
5041                         }
5042                 }
5043                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5044                 return 1;
5045         }
5046         return 0;
5047 }
5048
5049 static int loopback_test(struct slgt_info *info)
5050 {
5051 #define TESTFRAMESIZE 20
5052
5053         unsigned long timeout;
5054         u16 count = TESTFRAMESIZE;
5055         unsigned char buf[TESTFRAMESIZE];
5056         int rc = -ENODEV;
5057         unsigned long flags;
5058
5059         struct tty_struct *oldtty = info->port.tty;
5060         MGSL_PARAMS params;
5061
5062         memcpy(&params, &info->params, sizeof(params));
5063
5064         info->params.mode = MGSL_MODE_ASYNC;
5065         info->params.data_rate = 921600;
5066         info->params.loopback = 1;
5067         info->port.tty = NULL;
5068
5069         /* build and send transmit frame */
5070         for (count = 0; count < TESTFRAMESIZE; ++count)
5071                 buf[count] = (unsigned char)count;
5072
5073         info->tmp_rbuf_count = 0;
5074         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5075
5076         /* program hardware for HDLC and enabled receiver */
5077         spin_lock_irqsave(&info->lock,flags);
5078         async_mode(info);
5079         rx_start(info);
5080         tx_load(info, buf, count);
5081         spin_unlock_irqrestore(&info->lock, flags);
5082
5083         /* wait for receive complete */
5084         for (timeout = 100; timeout; --timeout) {
5085                 msleep_interruptible(10);
5086                 if (loopback_test_rx(info)) {
5087                         rc = 0;
5088                         break;
5089                 }
5090         }
5091
5092         /* verify received frame length and contents */
5093         if (!rc && (info->tmp_rbuf_count != count ||
5094                   memcmp(buf, info->tmp_rbuf, count))) {
5095                 rc = -ENODEV;
5096         }
5097
5098         spin_lock_irqsave(&info->lock,flags);
5099         reset_adapter(info);
5100         spin_unlock_irqrestore(&info->lock,flags);
5101
5102         memcpy(&info->params, &params, sizeof(info->params));
5103         info->port.tty = oldtty;
5104
5105         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5106         return rc;
5107 }
5108
5109 static int adapter_test(struct slgt_info *info)
5110 {
5111         DBGINFO(("testing %s\n", info->device_name));
5112         if (register_test(info) < 0) {
5113                 printk("register test failure %s addr=%08X\n",
5114                         info->device_name, info->phys_reg_addr);
5115         } else if (irq_test(info) < 0) {
5116                 printk("IRQ test failure %s IRQ=%d\n",
5117                         info->device_name, info->irq_level);
5118         } else if (loopback_test(info) < 0) {
5119                 printk("loopback test failure %s\n", info->device_name);
5120         }
5121         return info->init_error;
5122 }
5123
5124 /*
5125  * transmit timeout handler
5126  */
5127 static void tx_timeout(unsigned long context)
5128 {
5129         struct slgt_info *info = (struct slgt_info*)context;
5130         unsigned long flags;
5131
5132         DBGINFO(("%s tx_timeout\n", info->device_name));
5133         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5134                 info->icount.txtimeout++;
5135         }
5136         spin_lock_irqsave(&info->lock,flags);
5137         tx_stop(info);
5138         spin_unlock_irqrestore(&info->lock,flags);
5139
5140 #if SYNCLINK_GENERIC_HDLC
5141         if (info->netcount)
5142                 hdlcdev_tx_done(info);
5143         else
5144 #endif
5145                 bh_transmit(info);
5146 }
5147
5148 /*
5149  * receive buffer polling timer
5150  */
5151 static void rx_timeout(unsigned long context)
5152 {
5153         struct slgt_info *info = (struct slgt_info*)context;
5154         unsigned long flags;
5155
5156         DBGINFO(("%s rx_timeout\n", info->device_name));
5157         spin_lock_irqsave(&info->lock, flags);
5158         info->pending_bh |= BH_RECEIVE;
5159         spin_unlock_irqrestore(&info->lock, flags);
5160         bh_handler(&info->task);
5161 }
5162