drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.25 2006/02/06 21:20:33 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/io.h>
  79 #include <asm/irq.h>
  80 #include <asm/dma.h>
  81 #include <asm/types.h>
  82 #include <asm/uaccess.h>
  83
  84 #include "linux/synclink.h"
  85
  86 #ifdef CONFIG_HDLC_MODULE
  87 #define CONFIG_HDLC 1
  88 #endif
  89
  90 /*
  91  * module identification
  92  */
  93 static char *driver_name     = "SyncLink GT";
  94 static char *driver_version  = "$Revision: 4.25 $";
  95 static char *tty_driver_name = "synclink_gt";
  96 static char *tty_dev_prefix  = "ttySLG";
  97 MODULE_LICENSE("GPL");
  98 #define MGSL_MAGIC 0x5401
  99 #define MAX_DEVICES 12
 100
 101 static struct pci_device_id pci_table[] = {
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {0,}, /* terminate list */
 107 };
 108 MODULE_DEVICE_TABLE(pci, pci_table);
 109
 110 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 111 static void remove_one(struct pci_dev *dev);
 112 static struct pci_driver pci_driver = {
 113         .name           = "synclink_gt",
 114         .id_table       = pci_table,
 115         .probe          = init_one,
 116         .remove         = __devexit_p(remove_one),
 117 };
 118
 119 static int pci_registered;
 120
 121 /*
 122  * module configuration and status
 123  */
 124 static struct slgt_info *slgt_device_list;
 125 static int slgt_device_count;
 126
 127 static int ttymajor;
 128 static int debug_level;
 129 static int maxframe[MAX_DEVICES];
 130 static int dosyncppp[MAX_DEVICES];
 131
 132 module_param(ttymajor, int, 0);
 133 module_param(debug_level, int, 0);
 134 module_param_array(maxframe, int, NULL, 0);
 135 module_param_array(dosyncppp, int, NULL, 0);
 136
 137 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 138 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 139 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 140 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 141
 142 /*
 143  * tty support and callbacks
 144  */
 145 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 146
 147 static struct tty_driver *serial_driver;
 148
 149 static int  open(struct tty_struct *tty, struct file * filp);
 150 static void close(struct tty_struct *tty, struct file * filp);
 151 static void hangup(struct tty_struct *tty);
 152 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 153
 154 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 155 static void put_char(struct tty_struct *tty, unsigned char ch);
 156 static void send_xchar(struct tty_struct *tty, char ch);
 157 static void wait_until_sent(struct tty_struct *tty, int timeout);
 158 static int  write_room(struct tty_struct *tty);
 159 static void flush_chars(struct tty_struct *tty);
 160 static void flush_buffer(struct tty_struct *tty);
 161 static void tx_hold(struct tty_struct *tty);
 162 static void tx_release(struct tty_struct *tty);
 163
 164 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 165 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 166 static int  chars_in_buffer(struct tty_struct *tty);
 167 static void throttle(struct tty_struct * tty);
 168 static void unthrottle(struct tty_struct * tty);
 169 static void set_break(struct tty_struct *tty, int break_state);
 170
 171 /*
 172  * generic HDLC support and callbacks
 173  */
 174 #ifdef CONFIG_HDLC
 175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 176 static void hdlcdev_tx_done(struct slgt_info *info);
 177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 178 static int  hdlcdev_init(struct slgt_info *info);
 179 static void hdlcdev_exit(struct slgt_info *info);
 180 #endif
 181
 182
 183 /*
 184  * device specific structures, macros and functions
 185  */
 186
 187 #define SLGT_MAX_PORTS 4
 188 #define SLGT_REG_SIZE  256
 189
 190 /*
 191  * conditional wait facility
 192  */
 193 struct cond_wait {
 194         struct cond_wait *next;
 195         wait_queue_head_t q;
 196         wait_queue_t wait;
 197         unsigned int data;
 198 };
 199 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 200 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 202 static void flush_cond_wait(struct cond_wait **head);
 203
 204 /*
 205  * DMA buffer descriptor and access macros
 206  */
 207 struct slgt_desc
 208 {
 209         unsigned short count;
 210         unsigned short status;
 211         unsigned int pbuf;  /* physical address of data buffer */
 212         unsigned int next;  /* physical address of next descriptor */
 213
 214         /* driver book keeping */
 215         char *buf;          /* virtual  address of data buffer */
 216         unsigned int pdesc; /* physical address of this descriptor */
 217         dma_addr_t buf_dma_addr;
 218 };
 219
 220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 222 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 223 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 224 #define desc_count(a)      (le16_to_cpu((a).count))
 225 #define desc_status(a)     (le16_to_cpu((a).status))
 226 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 227 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 228 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 229 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 230 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 231
 232 struct _input_signal_events {
 233         int ri_up;
 234         int ri_down;
 235         int dsr_up;
 236         int dsr_down;
 237         int dcd_up;
 238         int dcd_down;
 239         int cts_up;
 240         int cts_down;
 241 };
 242
 243 /*
 244  * device instance data structure
 245  */
 246 struct slgt_info {
 247         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252         int flags;
 253
 254         char device_name[25];
 255         struct pci_dev *pdev;
 256
 257         int port_count;  /* count of ports on adapter */
 258         int adapter_num; /* adapter instance number */
 259         int port_num;    /* port instance number */
 260
 261         /* array of pointers to port contexts on this adapter */
 262         struct slgt_info *port_array[SLGT_MAX_PORTS];
 263
 264         int                     count;          /* count of opens */
 265         int                     line;           /* tty line instance number */
 266         unsigned short          close_delay;
 267         unsigned short          closing_wait;   /* time to wait before closing */
 268
 269         struct mgsl_icount      icount;
 270
 271         struct tty_struct       *tty;
 272         int                     timeout;
 273         int                     x_char;         /* xon/xoff character */
 274         int                     blocked_open;   /* # of blocked opens */
 275         unsigned int            read_status_mask;
 276         unsigned int            ignore_status_mask;
 277
 278         wait_queue_head_t       open_wait;
 279         wait_queue_head_t       close_wait;
 280
 281         wait_queue_head_t       status_event_wait_q;
 282         wait_queue_head_t       event_wait_q;
 283         struct timer_list       tx_timer;
 284         struct timer_list       rx_timer;
 285
 286         unsigned int            gpio_present;
 287         struct cond_wait        *gpio_wait_q;
 288
 289         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 290
 291         struct work_struct task;
 292         u32 pending_bh;
 293         int bh_requested;
 294         int bh_running;
 295
 296         int isr_overflow;
 297         int irq_requested;      /* nonzero if IRQ requested */
 298         int irq_occurred;       /* for diagnostics use */
 299
 300         /* device configuration */
 301
 302         unsigned int bus_type;
 303         unsigned int irq_level;
 304         unsigned long irq_flags;
 305
 306         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 307         u32 phys_reg_addr;
 308         int reg_addr_requested;
 309
 310         MGSL_PARAMS params;       /* communications parameters */
 311         u32 idle_mode;
 312         u32 max_frame_size;       /* as set by device config */
 313
 314         unsigned int raw_rx_size;
 315         unsigned int if_mode;
 316
 317         /* device status */
 318
 319         int rx_enabled;
 320         int rx_restart;
 321
 322         int tx_enabled;
 323         int tx_active;
 324
 325         unsigned char signals;    /* serial signal states */
 326         int init_error;  /* initialization error */
 327
 328         unsigned char *tx_buf;
 329         int tx_count;
 330
 331         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 332         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 333         BOOLEAN drop_rts_on_tx_done;
 334         struct  _input_signal_events    input_signal_events;
 335
 336         int dcd_chkcount;       /* check counts to prevent */
 337         int cts_chkcount;       /* too many IRQs if a signal */
 338         int dsr_chkcount;       /* is floating */
 339         int ri_chkcount;
 340
 341         char *bufs;             /* virtual address of DMA buffer lists */
 342         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 343
 344         unsigned int rbuf_count;
 345         struct slgt_desc *rbufs;
 346         unsigned int rbuf_current;
 347         unsigned int rbuf_index;
 348
 349         unsigned int tbuf_count;
 350         struct slgt_desc *tbufs;
 351         unsigned int tbuf_current;
 352         unsigned int tbuf_start;
 353
 354         unsigned char *tmp_rbuf;
 355         unsigned int tmp_rbuf_count;
 356
 357         /* SPPP/Cisco HDLC device parts */
 358
 359         int netcount;
 360         int dosyncppp;
 361         spinlock_t netlock;
 362 #ifdef CONFIG_HDLC
 363         struct net_device *netdev;
 364 #endif
 365
 366 };
 367
 368 static MGSL_PARAMS default_params = {
 369         .mode            = MGSL_MODE_HDLC,
 370         .loopback        = 0,
 371         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 372         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 373         .clock_speed     = 0,
 374         .addr_filter     = 0xff,
 375         .crc_type        = HDLC_CRC_16_CCITT,
 376         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 377         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 378         .data_rate       = 9600,
 379         .data_bits       = 8,
 380         .stop_bits       = 1,
 381         .parity          = ASYNC_PARITY_NONE
 382 };
 383
 384
 385 #define BH_RECEIVE  1
 386 #define BH_TRANSMIT 2
 387 #define BH_STATUS   4
 388 #define IO_PIN_SHUTDOWN_LIMIT 100
 389
 390 #define DMABUFSIZE 256
 391 #define DESC_LIST_SIZE 4096
 392
 393 #define MASK_PARITY  BIT1
 394 #define MASK_FRAMING BIT0
 395 #define MASK_BREAK   BIT14
 396 #define MASK_OVERRUN BIT4
 397
 398 #define GSR   0x00 /* global status */
 399 #define JCR   0x04 /* JTAG control */
 400 #define IODR  0x08 /* GPIO direction */
 401 #define IOER  0x0c /* GPIO interrupt enable */
 402 #define IOVR  0x10 /* GPIO value */
 403 #define IOSR  0x14 /* GPIO interrupt status */
 404 #define TDR   0x80 /* tx data */
 405 #define RDR   0x80 /* rx data */
 406 #define TCR   0x82 /* tx control */
 407 #define TIR   0x84 /* tx idle */
 408 #define TPR   0x85 /* tx preamble */
 409 #define RCR   0x86 /* rx control */
 410 #define VCR   0x88 /* V.24 control */
 411 #define CCR   0x89 /* clock control */
 412 #define BDR   0x8a /* baud divisor */
 413 #define SCR   0x8c /* serial control */
 414 #define SSR   0x8e /* serial status */
 415 #define RDCSR 0x90 /* rx DMA control/status */
 416 #define TDCSR 0x94 /* tx DMA control/status */
 417 #define RDDAR 0x98 /* rx DMA descriptor address */
 418 #define TDDAR 0x9c /* tx DMA descriptor address */
 419
 420 #define RXIDLE      BIT14
 421 #define RXBREAK     BIT14
 422 #define IRQ_TXDATA  BIT13
 423 #define IRQ_TXIDLE  BIT12
 424 #define IRQ_TXUNDER BIT11 /* HDLC */
 425 #define IRQ_RXDATA  BIT10
 426 #define IRQ_RXIDLE  BIT9  /* HDLC */
 427 #define IRQ_RXBREAK BIT9  /* async */
 428 #define IRQ_RXOVER  BIT8
 429 #define IRQ_DSR     BIT7
 430 #define IRQ_CTS     BIT6
 431 #define IRQ_DCD     BIT5
 432 #define IRQ_RI      BIT4
 433 #define IRQ_ALL     0x3ff0
 434 #define IRQ_MASTER  BIT0
 435
 436 #define slgt_irq_on(info, mask) \
 437         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 438 #define slgt_irq_off(info, mask) \
 439         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 440
 441 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 442 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 443 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 444 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 445 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 446 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 447
 448 static void  msc_set_vcr(struct slgt_info *info);
 449
 450 static int  startup(struct slgt_info *info);
 451 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 452 static void shutdown(struct slgt_info *info);
 453 static void program_hw(struct slgt_info *info);
 454 static void change_params(struct slgt_info *info);
 455
 456 static int  register_test(struct slgt_info *info);
 457 static int  irq_test(struct slgt_info *info);
 458 static int  loopback_test(struct slgt_info *info);
 459 static int  adapter_test(struct slgt_info *info);
 460
 461 static void reset_adapter(struct slgt_info *info);
 462 static void reset_port(struct slgt_info *info);
 463 static void async_mode(struct slgt_info *info);
 464 static void hdlc_mode(struct slgt_info *info);
 465
 466 static void rx_stop(struct slgt_info *info);
 467 static void rx_start(struct slgt_info *info);
 468 static void reset_rbufs(struct slgt_info *info);
 469 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 470 static void rdma_reset(struct slgt_info *info);
 471 static int  rx_get_frame(struct slgt_info *info);
 472 static int  rx_get_buf(struct slgt_info *info);
 473
 474 static void tx_start(struct slgt_info *info);
 475 static void tx_stop(struct slgt_info *info);
 476 static void tx_set_idle(struct slgt_info *info);
 477 static unsigned int free_tbuf_count(struct slgt_info *info);
 478 static void reset_tbufs(struct slgt_info *info);
 479 static void tdma_reset(struct slgt_info *info);
 480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 481
 482 static void get_signals(struct slgt_info *info);
 483 static void set_signals(struct slgt_info *info);
 484 static void enable_loopback(struct slgt_info *info);
 485 static void set_rate(struct slgt_info *info, u32 data_rate);
 486
 487 static int  bh_action(struct slgt_info *info);
 488 static void bh_handler(void* context);
 489 static void bh_transmit(struct slgt_info *info);
 490 static void isr_serial(struct slgt_info *info);
 491 static void isr_rdma(struct slgt_info *info);
 492 static void isr_txeom(struct slgt_info *info, unsigned short status);
 493 static void isr_tdma(struct slgt_info *info);
 494 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
 495
 496 static int  alloc_dma_bufs(struct slgt_info *info);
 497 static void free_dma_bufs(struct slgt_info *info);
 498 static int  alloc_desc(struct slgt_info *info);
 499 static void free_desc(struct slgt_info *info);
 500 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 501 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 502
 503 static int  alloc_tmp_rbuf(struct slgt_info *info);
 504 static void free_tmp_rbuf(struct slgt_info *info);
 505
 506 static void tx_timeout(unsigned long context);
 507 static void rx_timeout(unsigned long context);
 508
 509 /*
 510  * ioctl handlers
 511  */
 512 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 513 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 514 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 515 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 516 static int  set_txidle(struct slgt_info *info, int idle_mode);
 517 static int  tx_enable(struct slgt_info *info, int enable);
 518 static int  tx_abort(struct slgt_info *info);
 519 static int  rx_enable(struct slgt_info *info, int enable);
 520 static int  modem_input_wait(struct slgt_info *info,int arg);
 521 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 522 static int  tiocmget(struct tty_struct *tty, struct file *file);
 523 static int  tiocmset(struct tty_struct *tty, struct file *file,
 524                      unsigned int set, unsigned int clear);
 525 static void set_break(struct tty_struct *tty, int break_state);
 526 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 527 static int  set_interface(struct slgt_info *info, int if_mode);
 528 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 529 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 530 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 531
 532 /*
 533  * driver functions
 534  */
 535 static void add_device(struct slgt_info *info);
 536 static void device_init(int adapter_num, struct pci_dev *pdev);
 537 static int  claim_resources(struct slgt_info *info);
 538 static void release_resources(struct slgt_info *info);
 539
 540 /*
 541  * DEBUG OUTPUT CODE
 542  */
 543 #ifndef DBGINFO
 544 #define DBGINFO(fmt)
 545 #endif
 546 #ifndef DBGERR
 547 #define DBGERR(fmt)
 548 #endif
 549 #ifndef DBGBH
 550 #define DBGBH(fmt)
 551 #endif
 552 #ifndef DBGISR
 553 #define DBGISR(fmt)
 554 #endif
 555
 556 #ifdef DBGDATA
 557 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 558 {
 559         int i;
 560         int linecount;
 561         printk("%s %s data:\n",info->device_name, label);
 562         while(count) {
 563                 linecount = (count > 16) ? 16 : count;
 564                 for(i=0; i < linecount; i++)
 565                         printk("%02X ",(unsigned char)data[i]);
 566                 for(;i<17;i++)
 567                         printk("   ");
 568                 for(i=0;i<linecount;i++) {
 569                         if (data[i]>=040 && data[i]<=0176)
 570                                 printk("%c",data[i]);
 571                         else
 572                                 printk(".");
 573                 }
 574                 printk("\n");
 575                 data  += linecount;
 576                 count -= linecount;
 577         }
 578 }
 579 #else
 580 #define DBGDATA(info, buf, size, label)
 581 #endif
 582
 583 #ifdef DBGTBUF
 584 static void dump_tbufs(struct slgt_info *info)
 585 {
 586         int i;
 587         printk("tbuf_current=%d\n", info->tbuf_current);
 588         for (i=0 ; i < info->tbuf_count ; i++) {
 589                 printk("%d: count=%04X status=%04X\n",
 590                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 591         }
 592 }
 593 #else
 594 #define DBGTBUF(info)
 595 #endif
 596
 597 #ifdef DBGRBUF
 598 static void dump_rbufs(struct slgt_info *info)
 599 {
 600         int i;
 601         printk("rbuf_current=%d\n", info->rbuf_current);
 602         for (i=0 ; i < info->rbuf_count ; i++) {
 603                 printk("%d: count=%04X status=%04X\n",
 604                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 605         }
 606 }
 607 #else
 608 #define DBGRBUF(info)
 609 #endif
 610
 611 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 612 {
 613 #ifdef SANITY_CHECK
 614         if (!info) {
 615                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 616                 return 1;
 617         }
 618         if (info->magic != MGSL_MAGIC) {
 619                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 620                 return 1;
 621         }
 622 #else
 623         if (!info)
 624                 return 1;
 625 #endif
 626         return 0;
 627 }
 628
 629 /**
 630  * line discipline callback wrappers
 631  *
 632  * The wrappers maintain line discipline references
 633  * while calling into the line discipline.
 634  *
 635  * ldisc_receive_buf  - pass receive data to line discipline
 636  */
 637 static void ldisc_receive_buf(struct tty_struct *tty,
 638                               const __u8 *data, char *flags, int count)
 639 {
 640         struct tty_ldisc *ld;
 641         if (!tty)
 642                 return;
 643         ld = tty_ldisc_ref(tty);
 644         if (ld) {
 645                 if (ld->receive_buf)
 646                         ld->receive_buf(tty, data, flags, count);
 647                 tty_ldisc_deref(ld);
 648         }
 649 }
 650
 651 /* tty callbacks */
 652
 653 static int open(struct tty_struct *tty, struct file *filp)
 654 {
 655         struct slgt_info *info;
 656         int retval, line;
 657         unsigned long flags;
 658
 659         line = tty->index;
 660         if ((line < 0) || (line >= slgt_device_count)) {
 661                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 662                 return -ENODEV;
 663         }
 664
 665         info = slgt_device_list;
 666         while(info && info->line != line)
 667                 info = info->next_device;
 668         if (sanity_check(info, tty->name, "open"))
 669                 return -ENODEV;
 670         if (info->init_error) {
 671                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 672                 return -ENODEV;
 673         }
 674
 675         tty->driver_data = info;
 676         info->tty = tty;
 677
 678         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
 679
 680         /* If port is closing, signal caller to try again */
 681         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 682                 if (info->flags & ASYNC_CLOSING)
 683                         interruptible_sleep_on(&info->close_wait);
 684                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 685                         -EAGAIN : -ERESTARTSYS);
 686                 goto cleanup;
 687         }
 688
 689         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 690
 691         spin_lock_irqsave(&info->netlock, flags);
 692         if (info->netcount) {
 693                 retval = -EBUSY;
 694                 spin_unlock_irqrestore(&info->netlock, flags);
 695                 goto cleanup;
 696         }
 697         info->count++;
 698         spin_unlock_irqrestore(&info->netlock, flags);
 699
 700         if (info->count == 1) {
 701                 /* 1st open on this device, init hardware */
 702                 retval = startup(info);
 703                 if (retval < 0)
 704                         goto cleanup;
 705         }
 706
 707         retval = block_til_ready(tty, filp, info);
 708         if (retval) {
 709                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 710                 goto cleanup;
 711         }
 712
 713         retval = 0;
 714
 715 cleanup:
 716         if (retval) {
 717                 if (tty->count == 1)
 718                         info->tty = NULL; /* tty layer will release tty struct */
 719                 if(info->count)
 720                         info->count--;
 721         }
 722
 723         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 724         return retval;
 725 }
 726
 727 static void close(struct tty_struct *tty, struct file *filp)
 728 {
 729         struct slgt_info *info = tty->driver_data;
 730
 731         if (sanity_check(info, tty->name, "close"))
 732                 return;
 733         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
 734
 735         if (!info->count)
 736                 return;
 737
 738         if (tty_hung_up_p(filp))
 739                 goto cleanup;
 740
 741         if ((tty->count == 1) && (info->count != 1)) {
 742                 /*
 743                  * tty->count is 1 and the tty structure will be freed.
 744                  * info->count should be one in this case.
 745                  * if it's not, correct it so that the port is shutdown.
 746                  */
 747                 DBGERR(("%s close: bad refcount; tty->count=1, "
 748                        "info->count=%d\n", info->device_name, info->count));
 749                 info->count = 1;
 750         }
 751
 752         info->count--;
 753
 754         /* if at least one open remaining, leave hardware active */
 755         if (info->count)
 756                 goto cleanup;
 757
 758         info->flags |= ASYNC_CLOSING;
 759
 760         /* set tty->closing to notify line discipline to
 761          * only process XON/XOFF characters. Only the N_TTY
 762          * discipline appears to use this (ppp does not).
 763          */
 764         tty->closing = 1;
 765
 766         /* wait for transmit data to clear all layers */
 767
 768         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 769                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 770                 tty_wait_until_sent(tty, info->closing_wait);
 771         }
 772
 773         if (info->flags & ASYNC_INITIALIZED)
 774                 wait_until_sent(tty, info->timeout);
 775         if (tty->driver->flush_buffer)
 776                 tty->driver->flush_buffer(tty);
 777         tty_ldisc_flush(tty);
 778
 779         shutdown(info);
 780
 781         tty->closing = 0;
 782         info->tty = NULL;
 783
 784         if (info->blocked_open) {
 785                 if (info->close_delay) {
 786                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 787                 }
 788                 wake_up_interruptible(&info->open_wait);
 789         }
 790
 791         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 792
 793         wake_up_interruptible(&info->close_wait);
 794
 795 cleanup:
 796         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
 797 }
 798
 799 static void hangup(struct tty_struct *tty)
 800 {
 801         struct slgt_info *info = tty->driver_data;
 802
 803         if (sanity_check(info, tty->name, "hangup"))
 804                 return;
 805         DBGINFO(("%s hangup\n", info->device_name));
 806
 807         flush_buffer(tty);
 808         shutdown(info);
 809
 810         info->count = 0;
 811         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 812         info->tty = NULL;
 813
 814         wake_up_interruptible(&info->open_wait);
 815 }
 816
 817 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 818 {
 819         struct slgt_info *info = tty->driver_data;
 820         unsigned long flags;
 821
 822         DBGINFO(("%s set_termios\n", tty->driver->name));
 823
 824         /* just return if nothing has changed */
 825         if ((tty->termios->c_cflag == old_termios->c_cflag)
 826             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 827                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 828                 return;
 829
 830         change_params(info);
 831
 832         /* Handle transition to B0 status */
 833         if (old_termios->c_cflag & CBAUD &&
 834             !(tty->termios->c_cflag & CBAUD)) {
 835                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 836                 spin_lock_irqsave(&info->lock,flags);
 837                 set_signals(info);
 838                 spin_unlock_irqrestore(&info->lock,flags);
 839         }
 840
 841         /* Handle transition away from B0 status */
 842         if (!(old_termios->c_cflag & CBAUD) &&
 843             tty->termios->c_cflag & CBAUD) {
 844                 info->signals |= SerialSignal_DTR;
 845                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 846                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 847                         info->signals |= SerialSignal_RTS;
 848                 }
 849                 spin_lock_irqsave(&info->lock,flags);
 850                 set_signals(info);
 851                 spin_unlock_irqrestore(&info->lock,flags);
 852         }
 853
 854         /* Handle turning off CRTSCTS */
 855         if (old_termios->c_cflag & CRTSCTS &&
 856             !(tty->termios->c_cflag & CRTSCTS)) {
 857                 tty->hw_stopped = 0;
 858                 tx_release(tty);
 859         }
 860 }
 861
 862 static int write(struct tty_struct *tty,
 863                  const unsigned char *buf, int count)
 864 {
 865         int ret = 0;
 866         struct slgt_info *info = tty->driver_data;
 867         unsigned long flags;
 868
 869         if (sanity_check(info, tty->name, "write"))
 870                 goto cleanup;
 871         DBGINFO(("%s write count=%d\n", info->device_name, count));
 872
 873         if (!info->tx_buf)
 874                 goto cleanup;
 875
 876         if (count > info->max_frame_size) {
 877                 ret = -EIO;
 878                 goto cleanup;
 879         }
 880
 881         if (!count)
 882                 goto cleanup;
 883
 884         if (info->params.mode == MGSL_MODE_RAW) {
 885                 unsigned int bufs_needed = (count/DMABUFSIZE);
 886                 unsigned int bufs_free = free_tbuf_count(info);
 887                 if (count % DMABUFSIZE)
 888                         ++bufs_needed;
 889                 if (bufs_needed > bufs_free)
 890                         goto cleanup;
 891         } else {
 892                 if (info->tx_active)
 893                         goto cleanup;
 894                 if (info->tx_count) {
 895                         /* send accumulated data from send_char() calls */
 896                         /* as frame and wait before accepting more data. */
 897                         tx_load(info, info->tx_buf, info->tx_count);
 898                         goto start;
 899                 }
 900         }
 901
 902         ret = info->tx_count = count;
 903         tx_load(info, buf, count);
 904         goto start;
 905
 906 start:
 907         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 908                 spin_lock_irqsave(&info->lock,flags);
 909                 if (!info->tx_active)
 910                         tx_start(info);
 911                 spin_unlock_irqrestore(&info->lock,flags);
 912         }
 913
 914 cleanup:
 915         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 916         return ret;
 917 }
 918
 919 static void put_char(struct tty_struct *tty, unsigned char ch)
 920 {
 921         struct slgt_info *info = tty->driver_data;
 922         unsigned long flags;
 923
 924         if (sanity_check(info, tty->name, "put_char"))
 925                 return;
 926         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 927         if (!info->tx_buf)
 928                 return;
 929         spin_lock_irqsave(&info->lock,flags);
 930         if (!info->tx_active && (info->tx_count < info->max_frame_size))
 931                 info->tx_buf[info->tx_count++] = ch;
 932         spin_unlock_irqrestore(&info->lock,flags);
 933 }
 934
 935 static void send_xchar(struct tty_struct *tty, char ch)
 936 {
 937         struct slgt_info *info = tty->driver_data;
 938         unsigned long flags;
 939
 940         if (sanity_check(info, tty->name, "send_xchar"))
 941                 return;
 942         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 943         info->x_char = ch;
 944         if (ch) {
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 if (!info->tx_enabled)
 947                         tx_start(info);
 948                 spin_unlock_irqrestore(&info->lock,flags);
 949         }
 950 }
 951
 952 static void wait_until_sent(struct tty_struct *tty, int timeout)
 953 {
 954         struct slgt_info *info = tty->driver_data;
 955         unsigned long orig_jiffies, char_time;
 956
 957         if (!info )
 958                 return;
 959         if (sanity_check(info, tty->name, "wait_until_sent"))
 960                 return;
 961         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 962         if (!(info->flags & ASYNC_INITIALIZED))
 963                 goto exit;
 964
 965         orig_jiffies = jiffies;
 966
 967         /* Set check interval to 1/5 of estimated time to
 968          * send a character, and make it at least 1. The check
 969          * interval should also be less than the timeout.
 970          * Note: use tight timings here to satisfy the NIST-PCTS.
 971          */
 972
 973         if (info->params.data_rate) {
 974                 char_time = info->timeout/(32 * 5);
 975                 if (!char_time)
 976                         char_time++;
 977         } else
 978                 char_time = 1;
 979
 980         if (timeout)
 981                 char_time = min_t(unsigned long, char_time, timeout);
 982
 983         while (info->tx_active) {
 984                 msleep_interruptible(jiffies_to_msecs(char_time));
 985                 if (signal_pending(current))
 986                         break;
 987                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 988                         break;
 989         }
 990
 991 exit:
 992         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 993 }
 994
 995 static int write_room(struct tty_struct *tty)
 996 {
 997         struct slgt_info *info = tty->driver_data;
 998         int ret;
 999
1000         if (sanity_check(info, tty->name, "write_room"))
1001                 return 0;
1002         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1003         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1004         return ret;
1005 }
1006
1007 static void flush_chars(struct tty_struct *tty)
1008 {
1009         struct slgt_info *info = tty->driver_data;
1010         unsigned long flags;
1011
1012         if (sanity_check(info, tty->name, "flush_chars"))
1013                 return;
1014         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1015
1016         if (info->tx_count <= 0 || tty->stopped ||
1017             tty->hw_stopped || !info->tx_buf)
1018                 return;
1019
1020         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1021
1022         spin_lock_irqsave(&info->lock,flags);
1023         if (!info->tx_active && info->tx_count) {
1024                 tx_load(info, info->tx_buf,info->tx_count);
1025                 tx_start(info);
1026         }
1027         spin_unlock_irqrestore(&info->lock,flags);
1028 }
1029
1030 static void flush_buffer(struct tty_struct *tty)
1031 {
1032         struct slgt_info *info = tty->driver_data;
1033         unsigned long flags;
1034
1035         if (sanity_check(info, tty->name, "flush_buffer"))
1036                 return;
1037         DBGINFO(("%s flush_buffer\n", info->device_name));
1038
1039         spin_lock_irqsave(&info->lock,flags);
1040         if (!info->tx_active)
1041                 info->tx_count = 0;
1042         spin_unlock_irqrestore(&info->lock,flags);
1043
1044         wake_up_interruptible(&tty->write_wait);
1045         tty_wakeup(tty);
1046 }
1047
1048 /*
1049  * throttle (stop) transmitter
1050  */
1051 static void tx_hold(struct tty_struct *tty)
1052 {
1053         struct slgt_info *info = tty->driver_data;
1054         unsigned long flags;
1055
1056         if (sanity_check(info, tty->name, "tx_hold"))
1057                 return;
1058         DBGINFO(("%s tx_hold\n", info->device_name));
1059         spin_lock_irqsave(&info->lock,flags);
1060         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1061                 tx_stop(info);
1062         spin_unlock_irqrestore(&info->lock,flags);
1063 }
1064
1065 /*
1066  * release (start) transmitter
1067  */
1068 static void tx_release(struct tty_struct *tty)
1069 {
1070         struct slgt_info *info = tty->driver_data;
1071         unsigned long flags;
1072
1073         if (sanity_check(info, tty->name, "tx_release"))
1074                 return;
1075         DBGINFO(("%s tx_release\n", info->device_name));
1076         spin_lock_irqsave(&info->lock,flags);
1077         if (!info->tx_active && info->tx_count) {
1078                 tx_load(info, info->tx_buf, info->tx_count);
1079                 tx_start(info);
1080         }
1081         spin_unlock_irqrestore(&info->lock,flags);
1082 }
1083
1084 /*
1085  * Service an IOCTL request
1086  *
1087  * Arguments
1088  *
1089  *      tty     pointer to tty instance data
1090  *      file    pointer to associated file object for device
1091  *      cmd     IOCTL command code
1092  *      arg     command argument/context
1093  *
1094  * Return 0 if success, otherwise error code
1095  */
1096 static int ioctl(struct tty_struct *tty, struct file *file,
1097                  unsigned int cmd, unsigned long arg)
1098 {
1099         struct slgt_info *info = tty->driver_data;
1100         struct mgsl_icount cnow;        /* kernel counter temps */
1101         struct serial_icounter_struct __user *p_cuser;  /* user space */
1102         unsigned long flags;
1103         void __user *argp = (void __user *)arg;
1104
1105         if (sanity_check(info, tty->name, "ioctl"))
1106                 return -ENODEV;
1107         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1108
1109         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1110             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1111                 if (tty->flags & (1 << TTY_IO_ERROR))
1112                     return -EIO;
1113         }
1114
1115         switch (cmd) {
1116         case MGSL_IOCGPARAMS:
1117                 return get_params(info, argp);
1118         case MGSL_IOCSPARAMS:
1119                 return set_params(info, argp);
1120         case MGSL_IOCGTXIDLE:
1121                 return get_txidle(info, argp);
1122         case MGSL_IOCSTXIDLE:
1123                 return set_txidle(info, (int)arg);
1124         case MGSL_IOCTXENABLE:
1125                 return tx_enable(info, (int)arg);
1126         case MGSL_IOCRXENABLE:
1127                 return rx_enable(info, (int)arg);
1128         case MGSL_IOCTXABORT:
1129                 return tx_abort(info);
1130         case MGSL_IOCGSTATS:
1131                 return get_stats(info, argp);
1132         case MGSL_IOCWAITEVENT:
1133                 return wait_mgsl_event(info, argp);
1134         case TIOCMIWAIT:
1135                 return modem_input_wait(info,(int)arg);
1136         case MGSL_IOCGIF:
1137                 return get_interface(info, argp);
1138         case MGSL_IOCSIF:
1139                 return set_interface(info,(int)arg);
1140         case MGSL_IOCSGPIO:
1141                 return set_gpio(info, argp);
1142         case MGSL_IOCGGPIO:
1143                 return get_gpio(info, argp);
1144         case MGSL_IOCWAITGPIO:
1145                 return wait_gpio(info, argp);
1146         case TIOCGICOUNT:
1147                 spin_lock_irqsave(&info->lock,flags);
1148                 cnow = info->icount;
1149                 spin_unlock_irqrestore(&info->lock,flags);
1150                 p_cuser = argp;
1151                 if (put_user(cnow.cts, &p_cuser->cts) ||
1152                     put_user(cnow.dsr, &p_cuser->dsr) ||
1153                     put_user(cnow.rng, &p_cuser->rng) ||
1154                     put_user(cnow.dcd, &p_cuser->dcd) ||
1155                     put_user(cnow.rx, &p_cuser->rx) ||
1156                     put_user(cnow.tx, &p_cuser->tx) ||
1157                     put_user(cnow.frame, &p_cuser->frame) ||
1158                     put_user(cnow.overrun, &p_cuser->overrun) ||
1159                     put_user(cnow.parity, &p_cuser->parity) ||
1160                     put_user(cnow.brk, &p_cuser->brk) ||
1161                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1162                         return -EFAULT;
1163                 return 0;
1164         default:
1165                 return -ENOIOCTLCMD;
1166         }
1167         return 0;
1168 }
1169
1170 /*
1171  * proc fs support
1172  */
1173 static inline int line_info(char *buf, struct slgt_info *info)
1174 {
1175         char stat_buf[30];
1176         int ret;
1177         unsigned long flags;
1178
1179         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1180                       info->device_name, info->phys_reg_addr,
1181                       info->irq_level, info->max_frame_size);
1182
1183         /* output current serial signal states */
1184         spin_lock_irqsave(&info->lock,flags);
1185         get_signals(info);
1186         spin_unlock_irqrestore(&info->lock,flags);
1187
1188         stat_buf[0] = 0;
1189         stat_buf[1] = 0;
1190         if (info->signals & SerialSignal_RTS)
1191                 strcat(stat_buf, "|RTS");
1192         if (info->signals & SerialSignal_CTS)
1193                 strcat(stat_buf, "|CTS");
1194         if (info->signals & SerialSignal_DTR)
1195                 strcat(stat_buf, "|DTR");
1196         if (info->signals & SerialSignal_DSR)
1197                 strcat(stat_buf, "|DSR");
1198         if (info->signals & SerialSignal_DCD)
1199                 strcat(stat_buf, "|CD");
1200         if (info->signals & SerialSignal_RI)
1201                 strcat(stat_buf, "|RI");
1202
1203         if (info->params.mode != MGSL_MODE_ASYNC) {
1204                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1205                                info->icount.txok, info->icount.rxok);
1206                 if (info->icount.txunder)
1207                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1208                 if (info->icount.txabort)
1209                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1210                 if (info->icount.rxshort)
1211                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1212                 if (info->icount.rxlong)
1213                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1214                 if (info->icount.rxover)
1215                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1216                 if (info->icount.rxcrc)
1217                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1218         } else {
1219                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1220                                info->icount.tx, info->icount.rx);
1221                 if (info->icount.frame)
1222                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1223                 if (info->icount.parity)
1224                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1225                 if (info->icount.brk)
1226                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1227                 if (info->icount.overrun)
1228                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1229         }
1230
1231         /* Append serial signal status to end */
1232         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1233
1234         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1235                        info->tx_active,info->bh_requested,info->bh_running,
1236                        info->pending_bh);
1237
1238         return ret;
1239 }
1240
1241 /* Called to print information about devices
1242  */
1243 static int read_proc(char *page, char **start, off_t off, int count,
1244                      int *eof, void *data)
1245 {
1246         int len = 0, l;
1247         off_t   begin = 0;
1248         struct slgt_info *info;
1249
1250         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1251
1252         info = slgt_device_list;
1253         while( info ) {
1254                 l = line_info(page + len, info);
1255                 len += l;
1256                 if (len+begin > off+count)
1257                         goto done;
1258                 if (len+begin < off) {
1259                         begin += len;
1260                         len = 0;
1261                 }
1262                 info = info->next_device;
1263         }
1264
1265         *eof = 1;
1266 done:
1267         if (off >= len+begin)
1268                 return 0;
1269         *start = page + (off-begin);
1270         return ((count < begin+len-off) ? count : begin+len-off);
1271 }
1272
1273 /*
1274  * return count of bytes in transmit buffer
1275  */
1276 static int chars_in_buffer(struct tty_struct *tty)
1277 {
1278         struct slgt_info *info = tty->driver_data;
1279         if (sanity_check(info, tty->name, "chars_in_buffer"))
1280                 return 0;
1281         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1282         return info->tx_count;
1283 }
1284
1285 /*
1286  * signal remote device to throttle send data (our receive data)
1287  */
1288 static void throttle(struct tty_struct * tty)
1289 {
1290         struct slgt_info *info = tty->driver_data;
1291         unsigned long flags;
1292
1293         if (sanity_check(info, tty->name, "throttle"))
1294                 return;
1295         DBGINFO(("%s throttle\n", info->device_name));
1296         if (I_IXOFF(tty))
1297                 send_xchar(tty, STOP_CHAR(tty));
1298         if (tty->termios->c_cflag & CRTSCTS) {
1299                 spin_lock_irqsave(&info->lock,flags);
1300                 info->signals &= ~SerialSignal_RTS;
1301                 set_signals(info);
1302                 spin_unlock_irqrestore(&info->lock,flags);
1303         }
1304 }
1305
1306 /*
1307  * signal remote device to stop throttling send data (our receive data)
1308  */
1309 static void unthrottle(struct tty_struct * tty)
1310 {
1311         struct slgt_info *info = tty->driver_data;
1312         unsigned long flags;
1313
1314         if (sanity_check(info, tty->name, "unthrottle"))
1315                 return;
1316         DBGINFO(("%s unthrottle\n", info->device_name));
1317         if (I_IXOFF(tty)) {
1318                 if (info->x_char)
1319                         info->x_char = 0;
1320                 else
1321                         send_xchar(tty, START_CHAR(tty));
1322         }
1323         if (tty->termios->c_cflag & CRTSCTS) {
1324                 spin_lock_irqsave(&info->lock,flags);
1325                 info->signals |= SerialSignal_RTS;
1326                 set_signals(info);
1327                 spin_unlock_irqrestore(&info->lock,flags);
1328         }
1329 }
1330
1331 /*
1332  * set or clear transmit break condition
1333  * break_state  -1=set break condition, 0=clear
1334  */
1335 static void set_break(struct tty_struct *tty, int break_state)
1336 {
1337         struct slgt_info *info = tty->driver_data;
1338         unsigned short value;
1339         unsigned long flags;
1340
1341         if (sanity_check(info, tty->name, "set_break"))
1342                 return;
1343         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1344
1345         spin_lock_irqsave(&info->lock,flags);
1346         value = rd_reg16(info, TCR);
1347         if (break_state == -1)
1348                 value |= BIT6;
1349         else
1350                 value &= ~BIT6;
1351         wr_reg16(info, TCR, value);
1352         spin_unlock_irqrestore(&info->lock,flags);
1353 }
1354
1355 #ifdef CONFIG_HDLC
1356
1357 /**
1358  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1359  * set encoding and frame check sequence (FCS) options
1360  *
1361  * dev       pointer to network device structure
1362  * encoding  serial encoding setting
1363  * parity    FCS setting
1364  *
1365  * returns 0 if success, otherwise error code
1366  */
1367 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1368                           unsigned short parity)
1369 {
1370         struct slgt_info *info = dev_to_port(dev);
1371         unsigned char  new_encoding;
1372         unsigned short new_crctype;
1373
1374         /* return error if TTY interface open */
1375         if (info->count)
1376                 return -EBUSY;
1377
1378         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1379
1380         switch (encoding)
1381         {
1382         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1383         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1384         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1385         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1386         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1387         default: return -EINVAL;
1388         }
1389
1390         switch (parity)
1391         {
1392         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1393         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1394         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1395         default: return -EINVAL;
1396         }
1397
1398         info->params.encoding = new_encoding;
1399         info->params.crc_type = new_crctype;
1400
1401         /* if network interface up, reprogram hardware */
1402         if (info->netcount)
1403                 program_hw(info);
1404
1405         return 0;
1406 }
1407
1408 /**
1409  * called by generic HDLC layer to send frame
1410  *
1411  * skb  socket buffer containing HDLC frame
1412  * dev  pointer to network device structure
1413  *
1414  * returns 0 if success, otherwise error code
1415  */
1416 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1417 {
1418         struct slgt_info *info = dev_to_port(dev);
1419         struct net_device_stats *stats = hdlc_stats(dev);
1420         unsigned long flags;
1421
1422         DBGINFO(("%s hdlc_xmit\n", dev->name));
1423
1424         /* stop sending until this frame completes */
1425         netif_stop_queue(dev);
1426
1427         /* copy data to device buffers */
1428         info->tx_count = skb->len;
1429         tx_load(info, skb->data, skb->len);
1430
1431         /* update network statistics */
1432         stats->tx_packets++;
1433         stats->tx_bytes += skb->len;
1434
1435         /* done with socket buffer, so free it */
1436         dev_kfree_skb(skb);
1437
1438         /* save start time for transmit timeout detection */
1439         dev->trans_start = jiffies;
1440
1441         /* start hardware transmitter if necessary */
1442         spin_lock_irqsave(&info->lock,flags);
1443         if (!info->tx_active)
1444                 tx_start(info);
1445         spin_unlock_irqrestore(&info->lock,flags);
1446
1447         return 0;
1448 }
1449
1450 /**
1451  * called by network layer when interface enabled
1452  * claim resources and initialize hardware
1453  *
1454  * dev  pointer to network device structure
1455  *
1456  * returns 0 if success, otherwise error code
1457  */
1458 static int hdlcdev_open(struct net_device *dev)
1459 {
1460         struct slgt_info *info = dev_to_port(dev);
1461         int rc;
1462         unsigned long flags;
1463
1464         DBGINFO(("%s hdlcdev_open\n", dev->name));
1465
1466         /* generic HDLC layer open processing */
1467         if ((rc = hdlc_open(dev)))
1468                 return rc;
1469
1470         /* arbitrate between network and tty opens */
1471         spin_lock_irqsave(&info->netlock, flags);
1472         if (info->count != 0 || info->netcount != 0) {
1473                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1474                 spin_unlock_irqrestore(&info->netlock, flags);
1475                 return -EBUSY;
1476         }
1477         info->netcount=1;
1478         spin_unlock_irqrestore(&info->netlock, flags);
1479
1480         /* claim resources and init adapter */
1481         if ((rc = startup(info)) != 0) {
1482                 spin_lock_irqsave(&info->netlock, flags);
1483                 info->netcount=0;
1484                 spin_unlock_irqrestore(&info->netlock, flags);
1485                 return rc;
1486         }
1487
1488         /* assert DTR and RTS, apply hardware settings */
1489         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1490         program_hw(info);
1491
1492         /* enable network layer transmit */
1493         dev->trans_start = jiffies;
1494         netif_start_queue(dev);
1495
1496         /* inform generic HDLC layer of current DCD status */
1497         spin_lock_irqsave(&info->lock, flags);
1498         get_signals(info);
1499         spin_unlock_irqrestore(&info->lock, flags);
1500         if (info->signals & SerialSignal_DCD)
1501                 netif_carrier_on(dev);
1502         else
1503                 netif_carrier_off(dev);
1504         return 0;
1505 }
1506
1507 /**
1508  * called by network layer when interface is disabled
1509  * shutdown hardware and release resources
1510  *
1511  * dev  pointer to network device structure
1512  *
1513  * returns 0 if success, otherwise error code
1514  */
1515 static int hdlcdev_close(struct net_device *dev)
1516 {
1517         struct slgt_info *info = dev_to_port(dev);
1518         unsigned long flags;
1519
1520         DBGINFO(("%s hdlcdev_close\n", dev->name));
1521
1522         netif_stop_queue(dev);
1523
1524         /* shutdown adapter and release resources */
1525         shutdown(info);
1526
1527         hdlc_close(dev);
1528
1529         spin_lock_irqsave(&info->netlock, flags);
1530         info->netcount=0;
1531         spin_unlock_irqrestore(&info->netlock, flags);
1532
1533         return 0;
1534 }
1535
1536 /**
1537  * called by network layer to process IOCTL call to network device
1538  *
1539  * dev  pointer to network device structure
1540  * ifr  pointer to network interface request structure
1541  * cmd  IOCTL command code
1542  *
1543  * returns 0 if success, otherwise error code
1544  */
1545 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1546 {
1547         const size_t size = sizeof(sync_serial_settings);
1548         sync_serial_settings new_line;
1549         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1550         struct slgt_info *info = dev_to_port(dev);
1551         unsigned int flags;
1552
1553         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1554
1555         /* return error if TTY interface open */
1556         if (info->count)
1557                 return -EBUSY;
1558
1559         if (cmd != SIOCWANDEV)
1560                 return hdlc_ioctl(dev, ifr, cmd);
1561
1562         switch(ifr->ifr_settings.type) {
1563         case IF_GET_IFACE: /* return current sync_serial_settings */
1564
1565                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1566                 if (ifr->ifr_settings.size < size) {
1567                         ifr->ifr_settings.size = size; /* data size wanted */
1568                         return -ENOBUFS;
1569                 }
1570
1571                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1572                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1573                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1574                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1575
1576                 switch (flags){
1577                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1578                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1579                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1580                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1581                 default: new_line.clock_type = CLOCK_DEFAULT;
1582                 }
1583
1584                 new_line.clock_rate = info->params.clock_speed;
1585                 new_line.loopback   = info->params.loopback ? 1:0;
1586
1587                 if (copy_to_user(line, &new_line, size))
1588                         return -EFAULT;
1589                 return 0;
1590
1591         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1592
1593                 if(!capable(CAP_NET_ADMIN))
1594                         return -EPERM;
1595                 if (copy_from_user(&new_line, line, size))
1596                         return -EFAULT;
1597
1598                 switch (new_line.clock_type)
1599                 {
1600                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1601                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1602                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1603                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1604                 case CLOCK_DEFAULT:  flags = info->params.flags &
1605                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1606                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1607                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1608                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1609                 default: return -EINVAL;
1610                 }
1611
1612                 if (new_line.loopback != 0 && new_line.loopback != 1)
1613                         return -EINVAL;
1614
1615                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1616                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1617                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1618                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1619                 info->params.flags |= flags;
1620
1621                 info->params.loopback = new_line.loopback;
1622
1623                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1624                         info->params.clock_speed = new_line.clock_rate;
1625                 else
1626                         info->params.clock_speed = 0;
1627
1628                 /* if network interface up, reprogram hardware */
1629                 if (info->netcount)
1630                         program_hw(info);
1631                 return 0;
1632
1633         default:
1634                 return hdlc_ioctl(dev, ifr, cmd);
1635         }
1636 }
1637
1638 /**
1639  * called by network layer when transmit timeout is detected
1640  *
1641  * dev  pointer to network device structure
1642  */
1643 static void hdlcdev_tx_timeout(struct net_device *dev)
1644 {
1645         struct slgt_info *info = dev_to_port(dev);
1646         struct net_device_stats *stats = hdlc_stats(dev);
1647         unsigned long flags;
1648
1649         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1650
1651         stats->tx_errors++;
1652         stats->tx_aborted_errors++;
1653
1654         spin_lock_irqsave(&info->lock,flags);
1655         tx_stop(info);
1656         spin_unlock_irqrestore(&info->lock,flags);
1657
1658         netif_wake_queue(dev);
1659 }
1660
1661 /**
1662  * called by device driver when transmit completes
1663  * reenable network layer transmit if stopped
1664  *
1665  * info  pointer to device instance information
1666  */
1667 static void hdlcdev_tx_done(struct slgt_info *info)
1668 {
1669         if (netif_queue_stopped(info->netdev))
1670                 netif_wake_queue(info->netdev);
1671 }
1672
1673 /**
1674  * called by device driver when frame received
1675  * pass frame to network layer
1676  *
1677  * info  pointer to device instance information
1678  * buf   pointer to buffer contianing frame data
1679  * size  count of data bytes in buf
1680  */
1681 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1682 {
1683         struct sk_buff *skb = dev_alloc_skb(size);
1684         struct net_device *dev = info->netdev;
1685         struct net_device_stats *stats = hdlc_stats(dev);
1686
1687         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1688
1689         if (skb == NULL) {
1690                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1691                 stats->rx_dropped++;
1692                 return;
1693         }
1694
1695         memcpy(skb_put(skb, size),buf,size);
1696
1697         skb->protocol = hdlc_type_trans(skb, info->netdev);
1698
1699         stats->rx_packets++;
1700         stats->rx_bytes += size;
1701
1702         netif_rx(skb);
1703
1704         info->netdev->last_rx = jiffies;
1705 }
1706
1707 /**
1708  * called by device driver when adding device instance
1709  * do generic HDLC initialization
1710  *
1711  * info  pointer to device instance information
1712  *
1713  * returns 0 if success, otherwise error code
1714  */
1715 static int hdlcdev_init(struct slgt_info *info)
1716 {
1717         int rc;
1718         struct net_device *dev;
1719         hdlc_device *hdlc;
1720
1721         /* allocate and initialize network and HDLC layer objects */
1722
1723         if (!(dev = alloc_hdlcdev(info))) {
1724                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1725                 return -ENOMEM;
1726         }
1727
1728         /* for network layer reporting purposes only */
1729         dev->mem_start = info->phys_reg_addr;
1730         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1731         dev->irq       = info->irq_level;
1732
1733         /* network layer callbacks and settings */
1734         dev->do_ioctl       = hdlcdev_ioctl;
1735         dev->open           = hdlcdev_open;
1736         dev->stop           = hdlcdev_close;
1737         dev->tx_timeout     = hdlcdev_tx_timeout;
1738         dev->watchdog_timeo = 10*HZ;
1739         dev->tx_queue_len   = 50;
1740
1741         /* generic HDLC layer callbacks and settings */
1742         hdlc         = dev_to_hdlc(dev);
1743         hdlc->attach = hdlcdev_attach;
1744         hdlc->xmit   = hdlcdev_xmit;
1745
1746         /* register objects with HDLC layer */
1747         if ((rc = register_hdlc_device(dev))) {
1748                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1749                 free_netdev(dev);
1750                 return rc;
1751         }
1752
1753         info->netdev = dev;
1754         return 0;
1755 }
1756
1757 /**
1758  * called by device driver when removing device instance
1759  * do generic HDLC cleanup
1760  *
1761  * info  pointer to device instance information
1762  */
1763 static void hdlcdev_exit(struct slgt_info *info)
1764 {
1765         unregister_hdlc_device(info->netdev);
1766         free_netdev(info->netdev);
1767         info->netdev = NULL;
1768 }
1769
1770 #endif /* ifdef CONFIG_HDLC */
1771
1772 /*
1773  * get async data from rx DMA buffers
1774  */
1775 static void rx_async(struct slgt_info *info)
1776 {
1777         struct tty_struct *tty = info->tty;
1778         struct mgsl_icount *icount = &info->icount;
1779         unsigned int start, end;
1780         unsigned char *p;
1781         unsigned char status;
1782         struct slgt_desc *bufs = info->rbufs;
1783         int i, count;
1784         int chars = 0;
1785         int stat;
1786         unsigned char ch;
1787
1788         start = end = info->rbuf_current;
1789
1790         while(desc_complete(bufs[end])) {
1791                 count = desc_count(bufs[end]) - info->rbuf_index;
1792                 p     = bufs[end].buf + info->rbuf_index;
1793
1794                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1795                 DBGDATA(info, p, count, "rx");
1796
1797                 for(i=0 ; i < count; i+=2, p+=2) {
1798                         ch = *p;
1799                         icount->rx++;
1800
1801                         stat = 0;
1802
1803                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1804                                 if (status & BIT1)
1805                                         icount->parity++;
1806                                 else if (status & BIT0)
1807                                         icount->frame++;
1808                                 /* discard char if tty control flags say so */
1809                                 if (status & info->ignore_status_mask)
1810                                         continue;
1811                                 if (status & BIT1)
1812                                         stat = TTY_PARITY;
1813                                 else if (status & BIT0)
1814                                         stat = TTY_FRAME;
1815                         }
1816                         if (tty) {
1817                                 tty_insert_flip_char(tty, ch, stat);
1818                                 chars++;
1819                         }
1820                 }
1821
1822                 if (i < count) {
1823                         /* receive buffer not completed */
1824                         info->rbuf_index += i;
1825                         info->rx_timer.expires = jiffies + 1;
1826                         add_timer(&info->rx_timer);
1827                         break;
1828                 }
1829
1830                 info->rbuf_index = 0;
1831                 free_rbufs(info, end, end);
1832
1833                 if (++end == info->rbuf_count)
1834                         end = 0;
1835
1836                 /* if entire list searched then no frame available */
1837                 if (end == start)
1838                         break;
1839         }
1840
1841         if (tty && chars)
1842                 tty_flip_buffer_push(tty);
1843 }
1844
1845 /*
1846  * return next bottom half action to perform
1847  */
1848 static int bh_action(struct slgt_info *info)
1849 {
1850         unsigned long flags;
1851         int rc;
1852
1853         spin_lock_irqsave(&info->lock,flags);
1854
1855         if (info->pending_bh & BH_RECEIVE) {
1856                 info->pending_bh &= ~BH_RECEIVE;
1857                 rc = BH_RECEIVE;
1858         } else if (info->pending_bh & BH_TRANSMIT) {
1859                 info->pending_bh &= ~BH_TRANSMIT;
1860                 rc = BH_TRANSMIT;
1861         } else if (info->pending_bh & BH_STATUS) {
1862                 info->pending_bh &= ~BH_STATUS;
1863                 rc = BH_STATUS;
1864         } else {
1865                 /* Mark BH routine as complete */
1866                 info->bh_running   = 0;
1867                 info->bh_requested = 0;
1868                 rc = 0;
1869         }
1870
1871         spin_unlock_irqrestore(&info->lock,flags);
1872
1873         return rc;
1874 }
1875
1876 /*
1877  * perform bottom half processing
1878  */
1879 static void bh_handler(void* context)
1880 {
1881         struct slgt_info *info = context;
1882         int action;
1883
1884         if (!info)
1885                 return;
1886         info->bh_running = 1;
1887
1888         while((action = bh_action(info))) {
1889                 switch (action) {
1890                 case BH_RECEIVE:
1891                         DBGBH(("%s bh receive\n", info->device_name));
1892                         switch(info->params.mode) {
1893                         case MGSL_MODE_ASYNC:
1894                                 rx_async(info);
1895                                 break;
1896                         case MGSL_MODE_HDLC:
1897                                 while(rx_get_frame(info));
1898                                 break;
1899                         case MGSL_MODE_RAW:
1900                                 while(rx_get_buf(info));
1901                                 break;
1902                         }
1903                         /* restart receiver if rx DMA buffers exhausted */
1904                         if (info->rx_restart)
1905                                 rx_start(info);
1906                         break;
1907                 case BH_TRANSMIT:
1908                         bh_transmit(info);
1909                         break;
1910                 case BH_STATUS:
1911                         DBGBH(("%s bh status\n", info->device_name));
1912                         info->ri_chkcount = 0;
1913                         info->dsr_chkcount = 0;
1914                         info->dcd_chkcount = 0;
1915                         info->cts_chkcount = 0;
1916                         break;
1917                 default:
1918                         DBGBH(("%s unknown action\n", info->device_name));
1919                         break;
1920                 }
1921         }
1922         DBGBH(("%s bh_handler exit\n", info->device_name));
1923 }
1924
1925 static void bh_transmit(struct slgt_info *info)
1926 {
1927         struct tty_struct *tty = info->tty;
1928
1929         DBGBH(("%s bh_transmit\n", info->device_name));
1930         if (tty) {
1931                 tty_wakeup(tty);
1932                 wake_up_interruptible(&tty->write_wait);
1933         }
1934 }
1935
1936 static void dsr_change(struct slgt_info *info)
1937 {
1938         get_signals(info);
1939         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1940         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1941                 slgt_irq_off(info, IRQ_DSR);
1942                 return;
1943         }
1944         info->icount.dsr++;
1945         if (info->signals & SerialSignal_DSR)
1946                 info->input_signal_events.dsr_up++;
1947         else
1948                 info->input_signal_events.dsr_down++;
1949         wake_up_interruptible(&info->status_event_wait_q);
1950         wake_up_interruptible(&info->event_wait_q);
1951         info->pending_bh |= BH_STATUS;
1952 }
1953
1954 static void cts_change(struct slgt_info *info)
1955 {
1956         get_signals(info);
1957         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1958         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1959                 slgt_irq_off(info, IRQ_CTS);
1960                 return;
1961         }
1962         info->icount.cts++;
1963         if (info->signals & SerialSignal_CTS)
1964                 info->input_signal_events.cts_up++;
1965         else
1966                 info->input_signal_events.cts_down++;
1967         wake_up_interruptible(&info->status_event_wait_q);
1968         wake_up_interruptible(&info->event_wait_q);
1969         info->pending_bh |= BH_STATUS;
1970
1971         if (info->flags & ASYNC_CTS_FLOW) {
1972                 if (info->tty) {
1973                         if (info->tty->hw_stopped) {
1974                                 if (info->signals & SerialSignal_CTS) {
1975                                         info->tty->hw_stopped = 0;
1976                                         info->pending_bh |= BH_TRANSMIT;
1977                                         return;
1978                                 }
1979                         } else {
1980                                 if (!(info->signals & SerialSignal_CTS))
1981                                         info->tty->hw_stopped = 1;
1982                         }
1983                 }
1984         }
1985 }
1986
1987 static void dcd_change(struct slgt_info *info)
1988 {
1989         get_signals(info);
1990         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1991         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1992                 slgt_irq_off(info, IRQ_DCD);
1993                 return;
1994         }
1995         info->icount.dcd++;
1996         if (info->signals & SerialSignal_DCD) {
1997                 info->input_signal_events.dcd_up++;
1998         } else {
1999                 info->input_signal_events.dcd_down++;
2000         }
2001 #ifdef CONFIG_HDLC
2002         if (info->netcount) {
2003                 if (info->signals & SerialSignal_DCD)
2004                         netif_carrier_on(info->netdev);
2005                 else
2006                         netif_carrier_off(info->netdev);
2007         }
2008 #endif
2009         wake_up_interruptible(&info->status_event_wait_q);
2010         wake_up_interruptible(&info->event_wait_q);
2011         info->pending_bh |= BH_STATUS;
2012
2013         if (info->flags & ASYNC_CHECK_CD) {
2014                 if (info->signals & SerialSignal_DCD)
2015                         wake_up_interruptible(&info->open_wait);
2016                 else {
2017                         if (info->tty)
2018                                 tty_hangup(info->tty);
2019                 }
2020         }
2021 }
2022
2023 static void ri_change(struct slgt_info *info)
2024 {
2025         get_signals(info);
2026         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2027         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2028                 slgt_irq_off(info, IRQ_RI);
2029                 return;
2030         }
2031         info->icount.dcd++;
2032         if (info->signals & SerialSignal_RI) {
2033                 info->input_signal_events.ri_up++;
2034         } else {
2035                 info->input_signal_events.ri_down++;
2036         }
2037         wake_up_interruptible(&info->status_event_wait_q);
2038         wake_up_interruptible(&info->event_wait_q);
2039         info->pending_bh |= BH_STATUS;
2040 }
2041
2042 static void isr_serial(struct slgt_info *info)
2043 {
2044         unsigned short status = rd_reg16(info, SSR);
2045
2046         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2047
2048         wr_reg16(info, SSR, status); /* clear pending */
2049
2050         info->irq_occurred = 1;
2051
2052         if (info->params.mode == MGSL_MODE_ASYNC) {
2053                 if (status & IRQ_TXIDLE) {
2054                         if (info->tx_count)
2055                                 isr_txeom(info, status);
2056                 }
2057                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2058                         info->icount.brk++;
2059                         /* process break detection if tty control allows */
2060                         if (info->tty) {
2061                                 if (!(status & info->ignore_status_mask)) {
2062                                         if (info->read_status_mask & MASK_BREAK) {
2063                                                 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2064                                                 if (info->flags & ASYNC_SAK)
2065                                                         do_SAK(info->tty);
2066                                         }
2067                                 }
2068                         }
2069                 }
2070         } else {
2071                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2072                         isr_txeom(info, status);
2073
2074                 if (status & IRQ_RXIDLE) {
2075                         if (status & RXIDLE)
2076                                 info->icount.rxidle++;
2077                         else
2078                                 info->icount.exithunt++;
2079                         wake_up_interruptible(&info->event_wait_q);
2080                 }
2081
2082                 if (status & IRQ_RXOVER)
2083                         rx_start(info);
2084         }
2085
2086         if (status & IRQ_DSR)
2087                 dsr_change(info);
2088         if (status & IRQ_CTS)
2089                 cts_change(info);
2090         if (status & IRQ_DCD)
2091                 dcd_change(info);
2092         if (status & IRQ_RI)
2093                 ri_change(info);
2094 }
2095
2096 static void isr_rdma(struct slgt_info *info)
2097 {
2098         unsigned int status = rd_reg32(info, RDCSR);
2099
2100         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2101
2102         /* RDCSR (rx DMA control/status)
2103          *
2104          * 31..07  reserved
2105          * 06      save status byte to DMA buffer
2106          * 05      error
2107          * 04      eol (end of list)
2108          * 03      eob (end of buffer)
2109          * 02      IRQ enable
2110          * 01      reset
2111          * 00      enable
2112          */
2113         wr_reg32(info, RDCSR, status);  /* clear pending */
2114
2115         if (status & (BIT5 + BIT4)) {
2116                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2117                 info->rx_restart = 1;
2118         }
2119         info->pending_bh |= BH_RECEIVE;
2120 }
2121
2122 static void isr_tdma(struct slgt_info *info)
2123 {
2124         unsigned int status = rd_reg32(info, TDCSR);
2125
2126         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2127
2128         /* TDCSR (tx DMA control/status)
2129          *
2130          * 31..06  reserved
2131          * 05      error
2132          * 04      eol (end of list)
2133          * 03      eob (end of buffer)
2134          * 02      IRQ enable
2135          * 01      reset
2136          * 00      enable
2137          */
2138         wr_reg32(info, TDCSR, status);  /* clear pending */
2139
2140         if (status & (BIT5 + BIT4 + BIT3)) {
2141                 // another transmit buffer has completed
2142                 // run bottom half to get more send data from user
2143                 info->pending_bh |= BH_TRANSMIT;
2144         }
2145 }
2146
2147 static void isr_txeom(struct slgt_info *info, unsigned short status)
2148 {
2149         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2150
2151         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2152         tdma_reset(info);
2153         reset_tbufs(info);
2154         if (status & IRQ_TXUNDER) {
2155                 unsigned short val = rd_reg16(info, TCR);
2156                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2157                 wr_reg16(info, TCR, val); /* clear reset bit */
2158         }
2159
2160         if (info->tx_active) {
2161                 if (info->params.mode != MGSL_MODE_ASYNC) {
2162                         if (status & IRQ_TXUNDER)
2163                                 info->icount.txunder++;
2164                         else if (status & IRQ_TXIDLE)
2165                                 info->icount.txok++;
2166                 }
2167
2168                 info->tx_active = 0;
2169                 info->tx_count = 0;
2170
2171                 del_timer(&info->tx_timer);
2172
2173                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2174                         info->signals &= ~SerialSignal_RTS;
2175                         info->drop_rts_on_tx_done = 0;
2176                         set_signals(info);
2177                 }
2178
2179 #ifdef CONFIG_HDLC
2180                 if (info->netcount)
2181                         hdlcdev_tx_done(info);
2182                 else
2183 #endif
2184                 {
2185                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2186                                 tx_stop(info);
2187                                 return;
2188                         }
2189                         info->pending_bh |= BH_TRANSMIT;
2190                 }
2191         }
2192 }
2193
2194 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2195 {
2196         struct cond_wait *w, *prev;
2197
2198         /* wake processes waiting for specific transitions */
2199         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2200                 if (w->data & changed) {
2201                         w->data = state;
2202                         wake_up_interruptible(&w->q);
2203                         if (prev != NULL)
2204                                 prev->next = w->next;
2205                         else
2206                                 info->gpio_wait_q = w->next;
2207                 } else
2208                         prev = w;
2209         }
2210 }
2211
2212 /* interrupt service routine
2213  *
2214  *      irq     interrupt number
2215  *      dev_id  device ID supplied during interrupt registration
2216  *      regs    interrupted processor context
2217  */
2218 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2219 {
2220         struct slgt_info *info;
2221         unsigned int gsr;
2222         unsigned int i;
2223
2224         DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2225
2226         info = dev_id;
2227         if (!info)
2228                 return IRQ_NONE;
2229
2230         spin_lock(&info->lock);
2231
2232         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2233                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2234                 info->irq_occurred = 1;
2235                 for(i=0; i < info->port_count ; i++) {
2236                         if (info->port_array[i] == NULL)
2237                                 continue;
2238                         if (gsr & (BIT8 << i))
2239                                 isr_serial(info->port_array[i]);
2240                         if (gsr & (BIT16 << (i*2)))
2241                                 isr_rdma(info->port_array[i]);
2242                         if (gsr & (BIT17 << (i*2)))
2243                                 isr_tdma(info->port_array[i]);
2244                 }
2245         }
2246
2247         if (info->gpio_present) {
2248                 unsigned int state;
2249                 unsigned int changed;
2250                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2251                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2252                         /* read latched state of GPIO signals */
2253                         state = rd_reg32(info, IOVR);
2254                         /* clear pending GPIO interrupt bits */
2255                         wr_reg32(info, IOSR, changed);
2256                         for (i=0 ; i < info->port_count ; i++) {
2257                                 if (info->port_array[i] != NULL)
2258                                         isr_gpio(info->port_array[i], changed, state);
2259                         }
2260                 }
2261         }
2262
2263         for(i=0; i < info->port_count ; i++) {
2264                 struct slgt_info *port = info->port_array[i];
2265
2266                 if (port && (port->count || port->netcount) &&
2267                     port->pending_bh && !port->bh_running &&
2268                     !port->bh_requested) {
2269                         DBGISR(("%s bh queued\n", port->device_name));
2270                         schedule_work(&port->task);
2271                         port->bh_requested = 1;
2272                 }
2273         }
2274
2275         spin_unlock(&info->lock);
2276
2277         DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2278         return IRQ_HANDLED;
2279 }
2280
2281 static int startup(struct slgt_info *info)
2282 {
2283         DBGINFO(("%s startup\n", info->device_name));
2284
2285         if (info->flags & ASYNC_INITIALIZED)
2286                 return 0;
2287
2288         if (!info->tx_buf) {
2289                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2290                 if (!info->tx_buf) {
2291                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2292                         return -ENOMEM;
2293                 }
2294         }
2295
2296         info->pending_bh = 0;
2297
2298         memset(&info->icount, 0, sizeof(info->icount));
2299
2300         /* program hardware for current parameters */
2301         change_params(info);
2302
2303         if (info->tty)
2304                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2305
2306         info->flags |= ASYNC_INITIALIZED;
2307
2308         return 0;
2309 }
2310
2311 /*
2312  *  called by close() and hangup() to shutdown hardware
2313  */
2314 static void shutdown(struct slgt_info *info)
2315 {
2316         unsigned long flags;
2317
2318         if (!(info->flags & ASYNC_INITIALIZED))
2319                 return;
2320
2321         DBGINFO(("%s shutdown\n", info->device_name));
2322
2323         /* clear status wait queue because status changes */
2324         /* can't happen after shutting down the hardware */
2325         wake_up_interruptible(&info->status_event_wait_q);
2326         wake_up_interruptible(&info->event_wait_q);
2327
2328         del_timer_sync(&info->tx_timer);
2329         del_timer_sync(&info->rx_timer);
2330
2331         kfree(info->tx_buf);
2332         info->tx_buf = NULL;
2333
2334         spin_lock_irqsave(&info->lock,flags);
2335
2336         tx_stop(info);
2337         rx_stop(info);
2338
2339         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2340
2341         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2342                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2343                 set_signals(info);
2344         }
2345
2346         flush_cond_wait(&info->gpio_wait_q);
2347
2348         spin_unlock_irqrestore(&info->lock,flags);
2349
2350         if (info->tty)
2351                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2352
2353         info->flags &= ~ASYNC_INITIALIZED;
2354 }
2355
2356 static void program_hw(struct slgt_info *info)
2357 {
2358         unsigned long flags;
2359
2360         spin_lock_irqsave(&info->lock,flags);
2361
2362         rx_stop(info);
2363         tx_stop(info);
2364
2365         if (info->params.mode == MGSL_MODE_HDLC ||
2366             info->params.mode == MGSL_MODE_RAW ||
2367             info->netcount)
2368                 hdlc_mode(info);
2369         else
2370                 async_mode(info);
2371
2372         set_signals(info);
2373
2374         info->dcd_chkcount = 0;
2375         info->cts_chkcount = 0;
2376         info->ri_chkcount = 0;
2377         info->dsr_chkcount = 0;
2378
2379         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2380         get_signals(info);
2381
2382         if (info->netcount ||
2383             (info->tty && info->tty->termios->c_cflag & CREAD))
2384                 rx_start(info);
2385
2386         spin_unlock_irqrestore(&info->lock,flags);
2387 }
2388
2389 /*
2390  * reconfigure adapter based on new parameters
2391  */
2392 static void change_params(struct slgt_info *info)
2393 {
2394         unsigned cflag;
2395         int bits_per_char;
2396
2397         if (!info->tty || !info->tty->termios)
2398                 return;
2399         DBGINFO(("%s change_params\n", info->device_name));
2400
2401         cflag = info->tty->termios->c_cflag;
2402
2403         /* if B0 rate (hangup) specified then negate DTR and RTS */
2404         /* otherwise assert DTR and RTS */
2405         if (cflag & CBAUD)
2406                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2407         else
2408                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2409
2410         /* byte size and parity */
2411
2412         switch (cflag & CSIZE) {
2413         case CS5: info->params.data_bits = 5; break;
2414         case CS6: info->params.data_bits = 6; break;
2415         case CS7: info->params.data_bits = 7; break;
2416         case CS8: info->params.data_bits = 8; break;
2417         default:  info->params.data_bits = 7; break;
2418         }
2419
2420         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2421
2422         if (cflag & PARENB)
2423                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2424         else
2425                 info->params.parity = ASYNC_PARITY_NONE;
2426
2427         /* calculate number of jiffies to transmit a full
2428          * FIFO (32 bytes) at specified data rate
2429          */
2430         bits_per_char = info->params.data_bits +
2431                         info->params.stop_bits + 1;
2432
2433         info->params.data_rate = tty_get_baud_rate(info->tty);
2434
2435         if (info->params.data_rate) {
2436                 info->timeout = (32*HZ*bits_per_char) /
2437                                 info->params.data_rate;
2438         }
2439         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2440
2441         if (cflag & CRTSCTS)
2442                 info->flags |= ASYNC_CTS_FLOW;
2443         else
2444                 info->flags &= ~ASYNC_CTS_FLOW;
2445
2446         if (cflag & CLOCAL)
2447                 info->flags &= ~ASYNC_CHECK_CD;
2448         else
2449                 info->flags |= ASYNC_CHECK_CD;
2450
2451         /* process tty input control flags */
2452
2453         info->read_status_mask = IRQ_RXOVER;
2454         if (I_INPCK(info->tty))
2455                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2456         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2457                 info->read_status_mask |= MASK_BREAK;
2458         if (I_IGNPAR(info->tty))
2459                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2460         if (I_IGNBRK(info->tty)) {
2461                 info->ignore_status_mask |= MASK_BREAK;
2462                 /* If ignoring parity and break indicators, ignore
2463                  * overruns too.  (For real raw support).
2464                  */
2465                 if (I_IGNPAR(info->tty))
2466                         info->ignore_status_mask |= MASK_OVERRUN;
2467         }
2468
2469         program_hw(info);
2470 }
2471
2472 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2473 {
2474         DBGINFO(("%s get_stats\n",  info->device_name));
2475         if (!user_icount) {
2476                 memset(&info->icount, 0, sizeof(info->icount));
2477         } else {
2478                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2479                         return -EFAULT;
2480         }
2481         return 0;
2482 }
2483
2484 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2485 {
2486         DBGINFO(("%s get_params\n", info->device_name));
2487         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2488                 return -EFAULT;
2489         return 0;
2490 }
2491
2492 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2493 {
2494         unsigned long flags;
2495         MGSL_PARAMS tmp_params;
2496
2497         DBGINFO(("%s set_params\n", info->device_name));
2498         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2499                 return -EFAULT;
2500
2501         spin_lock_irqsave(&info->lock, flags);
2502         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2503         spin_unlock_irqrestore(&info->lock, flags);
2504
2505         change_params(info);
2506
2507         return 0;
2508 }
2509
2510 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2511 {
2512         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2513         if (put_user(info->idle_mode, idle_mode))
2514                 return -EFAULT;
2515         return 0;
2516 }
2517
2518 static int set_txidle(struct slgt_info *info, int idle_mode)
2519 {
2520         unsigned long flags;
2521         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2522         spin_lock_irqsave(&info->lock,flags);
2523         info->idle_mode = idle_mode;
2524         if (info->params.mode != MGSL_MODE_ASYNC)
2525                 tx_set_idle(info);
2526         spin_unlock_irqrestore(&info->lock,flags);
2527         return 0;
2528 }
2529
2530 static int tx_enable(struct slgt_info *info, int enable)
2531 {
2532         unsigned long flags;
2533         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2534         spin_lock_irqsave(&info->lock,flags);
2535         if (enable) {
2536                 if (!info->tx_enabled)
2537                         tx_start(info);
2538         } else {
2539                 if (info->tx_enabled)
2540                         tx_stop(info);
2541         }
2542         spin_unlock_irqrestore(&info->lock,flags);
2543         return 0;
2544 }
2545
2546 /*
2547  * abort transmit HDLC frame
2548  */
2549 static int tx_abort(struct slgt_info *info)
2550 {
2551         unsigned long flags;
2552         DBGINFO(("%s tx_abort\n", info->device_name));
2553         spin_lock_irqsave(&info->lock,flags);
2554         tdma_reset(info);
2555         spin_unlock_irqrestore(&info->lock,flags);
2556         return 0;
2557 }
2558
2559 static int rx_enable(struct slgt_info *info, int enable)
2560 {
2561         unsigned long flags;
2562         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2563         spin_lock_irqsave(&info->lock,flags);
2564         if (enable) {
2565                 if (!info->rx_enabled)
2566                         rx_start(info);
2567         } else {
2568                 if (info->rx_enabled)
2569                         rx_stop(info);
2570         }
2571         spin_unlock_irqrestore(&info->lock,flags);
2572         return 0;
2573 }
2574
2575 /*
2576  *  wait for specified event to occur
2577  */
2578 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2579 {
2580         unsigned long flags;
2581         int s;
2582         int rc=0;
2583         struct mgsl_icount cprev, cnow;
2584         int events;
2585         int mask;
2586         struct  _input_signal_events oldsigs, newsigs;
2587         DECLARE_WAITQUEUE(wait, current);
2588
2589         if (get_user(mask, mask_ptr))
2590                 return -EFAULT;
2591
2592         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2593
2594         spin_lock_irqsave(&info->lock,flags);
2595
2596         /* return immediately if state matches requested events */
2597         get_signals(info);
2598         s = info->signals;
2599
2600         events = mask &
2601                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2602                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2603                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2604                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2605         if (events) {
2606                 spin_unlock_irqrestore(&info->lock,flags);
2607                 goto exit;
2608         }
2609
2610         /* save current irq counts */
2611         cprev = info->icount;
2612         oldsigs = info->input_signal_events;
2613
2614         /* enable hunt and idle irqs if needed */
2615         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2616                 unsigned short val = rd_reg16(info, SCR);
2617                 if (!(val & IRQ_RXIDLE))
2618                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2619         }
2620
2621         set_current_state(TASK_INTERRUPTIBLE);
2622         add_wait_queue(&info->event_wait_q, &wait);
2623
2624         spin_unlock_irqrestore(&info->lock,flags);
2625
2626         for(;;) {
2627                 schedule();
2628                 if (signal_pending(current)) {
2629                         rc = -ERESTARTSYS;
2630                         break;
2631                 }
2632
2633                 /* get current irq counts */
2634                 spin_lock_irqsave(&info->lock,flags);
2635                 cnow = info->icount;
2636                 newsigs = info->input_signal_events;
2637                 set_current_state(TASK_INTERRUPTIBLE);
2638                 spin_unlock_irqrestore(&info->lock,flags);
2639
2640                 /* if no change, wait aborted for some reason */
2641                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2642                     newsigs.dsr_down == oldsigs.dsr_down &&
2643                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2644                     newsigs.dcd_down == oldsigs.dcd_down &&
2645                     newsigs.cts_up   == oldsigs.cts_up   &&
2646                     newsigs.cts_down == oldsigs.cts_down &&
2647                     newsigs.ri_up    == oldsigs.ri_up    &&
2648                     newsigs.ri_down  == oldsigs.ri_down  &&
2649                     cnow.exithunt    == cprev.exithunt   &&
2650                     cnow.rxidle      == cprev.rxidle) {
2651                         rc = -EIO;
2652                         break;
2653                 }
2654
2655                 events = mask &
2656                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2657                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2658                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2659                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2660                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2661                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2662                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2663                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2664                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2665                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2666                 if (events)
2667                         break;
2668
2669                 cprev = cnow;
2670                 oldsigs = newsigs;
2671         }
2672
2673         remove_wait_queue(&info->event_wait_q, &wait);
2674         set_current_state(TASK_RUNNING);
2675
2676
2677         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2678                 spin_lock_irqsave(&info->lock,flags);
2679                 if (!waitqueue_active(&info->event_wait_q)) {
2680                         /* disable enable exit hunt mode/idle rcvd IRQs */
2681                         wr_reg16(info, SCR,
2682                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2683                 }
2684                 spin_unlock_irqrestore(&info->lock,flags);
2685         }
2686 exit:
2687         if (rc == 0)
2688                 rc = put_user(events, mask_ptr);
2689         return rc;
2690 }
2691
2692 static int get_interface(struct slgt_info *info, int __user *if_mode)
2693 {
2694         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2695         if (put_user(info->if_mode, if_mode))
2696                 return -EFAULT;
2697         return 0;
2698 }
2699
2700 static int set_interface(struct slgt_info *info, int if_mode)
2701 {
2702         unsigned long flags;
2703         unsigned short val;
2704
2705         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2706         spin_lock_irqsave(&info->lock,flags);
2707         info->if_mode = if_mode;
2708
2709         msc_set_vcr(info);
2710
2711         /* TCR (tx control) 07  1=RTS driver control */
2712         val = rd_reg16(info, TCR);
2713         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2714                 val |= BIT7;
2715         else
2716                 val &= ~BIT7;
2717         wr_reg16(info, TCR, val);
2718
2719         spin_unlock_irqrestore(&info->lock,flags);
2720         return 0;
2721 }
2722
2723 /*
2724  * set general purpose IO pin state and direction
2725  *
2726  * user_gpio fields:
2727  * state   each bit indicates a pin state
2728  * smask   set bit indicates pin state to set
2729  * dir     each bit indicates a pin direction (0=input, 1=output)
2730  * dmask   set bit indicates pin direction to set
2731  */
2732 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2733 {
2734         unsigned long flags;
2735         struct gpio_desc gpio;
2736         __u32 data;
2737
2738         if (!info->gpio_present)
2739                 return -EINVAL;
2740         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2741                 return -EFAULT;
2742         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2743                  info->device_name, gpio.state, gpio.smask,
2744                  gpio.dir, gpio.dmask));
2745
2746         spin_lock_irqsave(&info->lock,flags);
2747         if (gpio.dmask) {
2748                 data = rd_reg32(info, IODR);
2749                 data |= gpio.dmask & gpio.dir;
2750                 data &= ~(gpio.dmask & ~gpio.dir);
2751                 wr_reg32(info, IODR, data);
2752         }
2753         if (gpio.smask) {
2754                 data = rd_reg32(info, IOVR);
2755                 data |= gpio.smask & gpio.state;
2756                 data &= ~(gpio.smask & ~gpio.state);
2757                 wr_reg32(info, IOVR, data);
2758         }
2759         spin_unlock_irqrestore(&info->lock,flags);
2760
2761         return 0;
2762 }
2763
2764 /*
2765  * get general purpose IO pin state and direction
2766  */
2767 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2768 {
2769         struct gpio_desc gpio;
2770         if (!info->gpio_present)
2771                 return -EINVAL;
2772         gpio.state = rd_reg32(info, IOVR);
2773         gpio.smask = 0xffffffff;
2774         gpio.dir   = rd_reg32(info, IODR);
2775         gpio.dmask = 0xffffffff;
2776         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2777                 return -EFAULT;
2778         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2779                  info->device_name, gpio.state, gpio.dir));
2780         return 0;
2781 }
2782
2783 /*
2784  * conditional wait facility
2785  */
2786 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2787 {
2788         init_waitqueue_head(&w->q);
2789         init_waitqueue_entry(&w->wait, current);
2790         w->data = data;
2791 }
2792
2793 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2794 {
2795         set_current_state(TASK_INTERRUPTIBLE);
2796         add_wait_queue(&w->q, &w->wait);
2797         w->next = *head;
2798         *head = w;
2799 }
2800
2801 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2802 {
2803         struct cond_wait *w, *prev;
2804         remove_wait_queue(&cw->q, &cw->wait);
2805         set_current_state(TASK_RUNNING);
2806         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2807                 if (w == cw) {
2808                         if (prev != NULL)
2809                                 prev->next = w->next;
2810                         else
2811                                 *head = w->next;
2812                         break;
2813                 }
2814         }
2815 }
2816
2817 static void flush_cond_wait(struct cond_wait **head)
2818 {
2819         while (*head != NULL) {
2820                 wake_up_interruptible(&(*head)->q);
2821                 *head = (*head)->next;
2822         }
2823 }
2824
2825 /*
2826  * wait for general purpose I/O pin(s) to enter specified state
2827  *
2828  * user_gpio fields:
2829  * state - bit indicates target pin state
2830  * smask - set bit indicates watched pin
2831  *
2832  * The wait ends when at least one watched pin enters the specified
2833  * state. When 0 (no error) is returned, user_gpio->state is set to the
2834  * state of all GPIO pins when the wait ends.
2835  *
2836  * Note: Each pin may be a dedicated input, dedicated output, or
2837  * configurable input/output. The number and configuration of pins
2838  * varies with the specific adapter model. Only input pins (dedicated
2839  * or configured) can be monitored with this function.
2840  */
2841 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2842 {
2843         unsigned long flags;
2844         int rc = 0;
2845         struct gpio_desc gpio;
2846         struct cond_wait wait;
2847         u32 state;
2848
2849         if (!info->gpio_present)
2850                 return -EINVAL;
2851         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2852                 return -EFAULT;
2853         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2854                  info->device_name, gpio.state, gpio.smask));
2855         /* ignore output pins identified by set IODR bit */
2856         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2857                 return -EINVAL;
2858         init_cond_wait(&wait, gpio.smask);
2859
2860         spin_lock_irqsave(&info->lock, flags);
2861         /* enable interrupts for watched pins */
2862         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2863         /* get current pin states */
2864         state = rd_reg32(info, IOVR);
2865
2866         if (gpio.smask & ~(state ^ gpio.state)) {
2867                 /* already in target state */
2868                 gpio.state = state;
2869         } else {
2870                 /* wait for target state */
2871                 add_cond_wait(&info->gpio_wait_q, &wait);
2872                 spin_unlock_irqrestore(&info->lock, flags);
2873                 schedule();
2874                 if (signal_pending(current))
2875                         rc = -ERESTARTSYS;
2876                 else
2877                         gpio.state = wait.data;
2878                 spin_lock_irqsave(&info->lock, flags);
2879                 remove_cond_wait(&info->gpio_wait_q, &wait);
2880         }
2881
2882         /* disable all GPIO interrupts if no waiting processes */
2883         if (info->gpio_wait_q == NULL)
2884                 wr_reg32(info, IOER, 0);
2885         spin_unlock_irqrestore(&info->lock,flags);
2886
2887         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2888                 rc = -EFAULT;
2889         return rc;
2890 }
2891
2892 static int modem_input_wait(struct slgt_info *info,int arg)
2893 {
2894         unsigned long flags;
2895         int rc;
2896         struct mgsl_icount cprev, cnow;
2897         DECLARE_WAITQUEUE(wait, current);
2898
2899         /* save current irq counts */
2900         spin_lock_irqsave(&info->lock,flags);
2901         cprev = info->icount;
2902         add_wait_queue(&info->status_event_wait_q, &wait);
2903         set_current_state(TASK_INTERRUPTIBLE);
2904         spin_unlock_irqrestore(&info->lock,flags);
2905
2906         for(;;) {
2907                 schedule();
2908                 if (signal_pending(current)) {
2909                         rc = -ERESTARTSYS;
2910                         break;
2911                 }
2912
2913                 /* get new irq counts */
2914                 spin_lock_irqsave(&info->lock,flags);
2915                 cnow = info->icount;
2916                 set_current_state(TASK_INTERRUPTIBLE);
2917                 spin_unlock_irqrestore(&info->lock,flags);
2918
2919                 /* if no change, wait aborted for some reason */
2920                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2921                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2922                         rc = -EIO;
2923                         break;
2924                 }
2925
2926                 /* check for change in caller specified modem input */
2927                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2928                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2929                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2930                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2931                         rc = 0;
2932                         break;
2933                 }
2934
2935                 cprev = cnow;
2936         }
2937         remove_wait_queue(&info->status_event_wait_q, &wait);
2938         set_current_state(TASK_RUNNING);
2939         return rc;
2940 }
2941
2942 /*
2943  *  return state of serial control and status signals
2944  */
2945 static int tiocmget(struct tty_struct *tty, struct file *file)
2946 {
2947         struct slgt_info *info = tty->driver_data;
2948         unsigned int result;
2949         unsigned long flags;
2950
2951         spin_lock_irqsave(&info->lock,flags);
2952         get_signals(info);
2953         spin_unlock_irqrestore(&info->lock,flags);
2954
2955         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2956                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2957                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2958                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2959                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2960                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2961
2962         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2963         return result;
2964 }
2965
2966 /*
2967  * set modem control signals (DTR/RTS)
2968  *
2969  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2970  *              TIOCMSET = set/clear signal values
2971  *      value   bit mask for command
2972  */
2973 static int tiocmset(struct tty_struct *tty, struct file *file,
2974                     unsigned int set, unsigned int clear)
2975 {
2976         struct slgt_info *info = tty->driver_data;
2977         unsigned long flags;
2978
2979         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2980
2981         if (set & TIOCM_RTS)
2982                 info->signals |= SerialSignal_RTS;
2983         if (set & TIOCM_DTR)
2984                 info->signals |= SerialSignal_DTR;
2985         if (clear & TIOCM_RTS)
2986                 info->signals &= ~SerialSignal_RTS;
2987         if (clear & TIOCM_DTR)
2988                 info->signals &= ~SerialSignal_DTR;
2989
2990         spin_lock_irqsave(&info->lock,flags);
2991         set_signals(info);
2992         spin_unlock_irqrestore(&info->lock,flags);
2993         return 0;
2994 }
2995
2996 /*
2997  *  block current process until the device is ready to open
2998  */
2999 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3000                            struct slgt_info *info)
3001 {
3002         DECLARE_WAITQUEUE(wait, current);
3003         int             retval;
3004         int             do_clocal = 0, extra_count = 0;
3005         unsigned long   flags;
3006
3007         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3008
3009         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3010                 /* nonblock mode is set or port is not enabled */
3011                 info->flags |= ASYNC_NORMAL_ACTIVE;
3012                 return 0;
3013         }
3014
3015         if (tty->termios->c_cflag & CLOCAL)
3016                 do_clocal = 1;
3017
3018         /* Wait for carrier detect and the line to become
3019          * free (i.e., not in use by the callout).  While we are in
3020          * this loop, info->count is dropped by one, so that
3021          * close() knows when to free things.  We restore it upon
3022          * exit, either normal or abnormal.
3023          */
3024
3025         retval = 0;
3026         add_wait_queue(&info->open_wait, &wait);
3027
3028         spin_lock_irqsave(&info->lock, flags);
3029         if (!tty_hung_up_p(filp)) {
3030                 extra_count = 1;
3031                 info->count--;
3032         }
3033         spin_unlock_irqrestore(&info->lock, flags);
3034         info->blocked_open++;
3035
3036         while (1) {
3037                 if ((tty->termios->c_cflag & CBAUD)) {
3038                         spin_lock_irqsave(&info->lock,flags);
3039                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3040                         set_signals(info);
3041                         spin_unlock_irqrestore(&info->lock,flags);
3042                 }
3043
3044                 set_current_state(TASK_INTERRUPTIBLE);
3045
3046                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3047                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3048                                         -EAGAIN : -ERESTARTSYS;
3049                         break;
3050                 }
3051
3052                 spin_lock_irqsave(&info->lock,flags);
3053                 get_signals(info);
3054                 spin_unlock_irqrestore(&info->lock,flags);
3055
3056                 if (!(info->flags & ASYNC_CLOSING) &&
3057                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3058                         break;
3059                 }
3060
3061                 if (signal_pending(current)) {
3062                         retval = -ERESTARTSYS;
3063                         break;
3064                 }
3065
3066                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3067                 schedule();
3068         }
3069
3070         set_current_state(TASK_RUNNING);
3071         remove_wait_queue(&info->open_wait, &wait);
3072
3073         if (extra_count)
3074                 info->count++;
3075         info->blocked_open--;
3076
3077         if (!retval)
3078                 info->flags |= ASYNC_NORMAL_ACTIVE;
3079
3080         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3081         return retval;
3082 }
3083
3084 static int alloc_tmp_rbuf(struct slgt_info *info)
3085 {
3086         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3087         if (info->tmp_rbuf == NULL)
3088                 return -ENOMEM;
3089         return 0;
3090 }
3091
3092 static void free_tmp_rbuf(struct slgt_info *info)
3093 {
3094         kfree(info->tmp_rbuf);
3095         info->tmp_rbuf = NULL;
3096 }
3097
3098 /*
3099  * allocate DMA descriptor lists.
3100  */
3101 static int alloc_desc(struct slgt_info *info)
3102 {
3103         unsigned int i;
3104         unsigned int pbufs;
3105
3106         /* allocate memory to hold descriptor lists */
3107         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3108         if (info->bufs == NULL)
3109                 return -ENOMEM;
3110
3111         memset(info->bufs, 0, DESC_LIST_SIZE);
3112
3113         info->rbufs = (struct slgt_desc*)info->bufs;
3114         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3115
3116         pbufs = (unsigned int)info->bufs_dma_addr;
3117
3118         /*
3119          * Build circular lists of descriptors
3120          */
3121
3122         for (i=0; i < info->rbuf_count; i++) {
3123                 /* physical address of this descriptor */
3124                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3125
3126                 /* physical address of next descriptor */
3127                 if (i == info->rbuf_count - 1)
3128                         info->rbufs[i].next = cpu_to_le32(pbufs);
3129                 else
3130                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3131                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3132         }
3133
3134         for (i=0; i < info->tbuf_count; i++) {
3135                 /* physical address of this descriptor */
3136                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3137
3138                 /* physical address of next descriptor */
3139                 if (i == info->tbuf_count - 1)
3140                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3141                 else
3142                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3143         }
3144
3145         return 0;
3146 }
3147
3148 static void free_desc(struct slgt_info *info)
3149 {
3150         if (info->bufs != NULL) {
3151                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3152                 info->bufs  = NULL;
3153                 info->rbufs = NULL;
3154                 info->tbufs = NULL;
3155         }
3156 }
3157
3158 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3159 {
3160         int i;
3161         for (i=0; i < count; i++) {
3162                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3163                         return -ENOMEM;
3164                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3165         }
3166         return 0;
3167 }
3168
3169 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3170 {
3171         int i;
3172         for (i=0; i < count; i++) {
3173                 if (bufs[i].buf == NULL)
3174                         continue;
3175                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3176                 bufs[i].buf = NULL;
3177         }
3178 }
3179
3180 static int alloc_dma_bufs(struct slgt_info *info)
3181 {
3182         info->rbuf_count = 32;
3183         info->tbuf_count = 32;
3184
3185         if (alloc_desc(info) < 0 ||
3186             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3187             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3188             alloc_tmp_rbuf(info) < 0) {
3189                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3190                 return -ENOMEM;
3191         }
3192         reset_rbufs(info);
3193         return 0;
3194 }
3195
3196 static void free_dma_bufs(struct slgt_info *info)
3197 {
3198         if (info->bufs) {
3199                 free_bufs(info, info->rbufs, info->rbuf_count);
3200                 free_bufs(info, info->tbufs, info->tbuf_count);
3201                 free_desc(info);
3202         }
3203         free_tmp_rbuf(info);
3204 }
3205
3206 static int claim_resources(struct slgt_info *info)
3207 {
3208         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3209                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3210                         info->device_name, info->phys_reg_addr));
3211                 info->init_error = DiagStatus_AddressConflict;
3212                 goto errout;
3213         }
3214         else
3215                 info->reg_addr_requested = 1;
3216
3217         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3218         if (!info->reg_addr) {
3219                 DBGERR(("%s cant map device registers, addr=%08X\n",
3220                         info->device_name, info->phys_reg_addr));
3221                 info->init_error = DiagStatus_CantAssignPciResources;
3222                 goto errout;
3223         }
3224         return 0;
3225
3226 errout:
3227         release_resources(info);
3228         return -ENODEV;
3229 }
3230
3231 static void release_resources(struct slgt_info *info)
3232 {
3233         if (info->irq_requested) {
3234                 free_irq(info->irq_level, info);
3235                 info->irq_requested = 0;
3236         }
3237
3238         if (info->reg_addr_requested) {
3239                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3240                 info->reg_addr_requested = 0;
3241         }
3242
3243         if (info->reg_addr) {
3244                 iounmap(info->reg_addr);
3245                 info->reg_addr = NULL;
3246         }
3247 }
3248
3249 /* Add the specified device instance data structure to the
3250  * global linked list of devices and increment the device count.
3251  */
3252 static void add_device(struct slgt_info *info)
3253 {
3254         char *devstr;
3255
3256         info->next_device = NULL;
3257         info->line = slgt_device_count;
3258         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3259
3260         if (info->line < MAX_DEVICES) {
3261                 if (maxframe[info->line])
3262                         info->max_frame_size = maxframe[info->line];
3263                 info->dosyncppp = dosyncppp[info->line];
3264         }
3265
3266         slgt_device_count++;
3267
3268         if (!slgt_device_list)
3269                 slgt_device_list = info;
3270         else {
3271                 struct slgt_info *current_dev = slgt_device_list;
3272                 while(current_dev->next_device)
3273                         current_dev = current_dev->next_device;
3274                 current_dev->next_device = info;
3275         }
3276
3277         if (info->max_frame_size < 4096)
3278                 info->max_frame_size = 4096;
3279         else if (info->max_frame_size > 65535)
3280                 info->max_frame_size = 65535;
3281
3282         switch(info->pdev->device) {
3283         case SYNCLINK_GT_DEVICE_ID:
3284                 devstr = "GT";
3285                 break;
3286         case SYNCLINK_GT2_DEVICE_ID:
3287                 devstr = "GT2";
3288                 break;
3289         case SYNCLINK_GT4_DEVICE_ID:
3290                 devstr = "GT4";
3291                 break;
3292         case SYNCLINK_AC_DEVICE_ID:
3293                 devstr = "AC";
3294                 info->params.mode = MGSL_MODE_ASYNC;
3295                 break;
3296         default:
3297                 devstr = "(unknown model)";
3298         }
3299         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3300                 devstr, info->device_name, info->phys_reg_addr,
3301                 info->irq_level, info->max_frame_size);
3302
3303 #ifdef CONFIG_HDLC
3304         hdlcdev_init(info);
3305 #endif
3306 }
3307
3308 /*
3309  *  allocate device instance structure, return NULL on failure
3310  */
3311 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3312 {
3313         struct slgt_info *info;
3314
3315         info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3316
3317         if (!info) {
3318                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3319                         driver_name, adapter_num, port_num));
3320         } else {
3321                 memset(info, 0, sizeof(struct slgt_info));
3322                 info->magic = MGSL_MAGIC;
3323                 INIT_WORK(&info->task, bh_handler, info);
3324                 info->max_frame_size = 4096;
3325                 info->raw_rx_size = DMABUFSIZE;
3326                 info->close_delay = 5*HZ/10;
3327                 info->closing_wait = 30*HZ;
3328                 init_waitqueue_head(&info->open_wait);
3329                 init_waitqueue_head(&info->close_wait);
3330                 init_waitqueue_head(&info->status_event_wait_q);
3331                 init_waitqueue_head(&info->event_wait_q);
3332                 spin_lock_init(&info->netlock);
3333                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3334                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3335                 info->adapter_num = adapter_num;
3336                 info->port_num = port_num;
3337
3338                 init_timer(&info->tx_timer);
3339                 info->tx_timer.data = (unsigned long)info;
3340                 info->tx_timer.function = tx_timeout;
3341
3342                 init_timer(&info->rx_timer);
3343                 info->rx_timer.data = (unsigned long)info;
3344                 info->rx_timer.function = rx_timeout;
3345
3346                 /* Copy configuration info to device instance data */
3347                 info->pdev = pdev;
3348                 info->irq_level = pdev->irq;
3349                 info->phys_reg_addr = pci_resource_start(pdev,0);
3350
3351                 info->bus_type = MGSL_BUS_TYPE_PCI;
3352                 info->irq_flags = IRQF_SHARED;
3353
3354                 info->init_error = -1; /* assume error, set to 0 on successful init */
3355         }
3356
3357         return info;
3358 }
3359
3360 static void device_init(int adapter_num, struct pci_dev *pdev)
3361 {
3362         struct slgt_info *port_array[SLGT_MAX_PORTS];
3363         int i;
3364         int port_count = 1;
3365
3366         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3367                 port_count = 2;
3368         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3369                 port_count = 4;
3370
3371         /* allocate device instances for all ports */
3372         for (i=0; i < port_count; ++i) {
3373                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3374                 if (port_array[i] == NULL) {
3375                         for (--i; i >= 0; --i)
3376                                 kfree(port_array[i]);
3377                         return;
3378                 }
3379         }
3380
3381         /* give copy of port_array to all ports and add to device list  */
3382         for (i=0; i < port_count; ++i) {
3383                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3384                 add_device(port_array[i]);
3385                 port_array[i]->port_count = port_count;
3386                 spin_lock_init(&port_array[i]->lock);
3387         }
3388
3389         /* Allocate and claim adapter resources */
3390         if (!claim_resources(port_array[0])) {
3391
3392                 alloc_dma_bufs(port_array[0]);
3393
3394                 /* copy resource information from first port to others */
3395                 for (i = 1; i < port_count; ++i) {
3396                         port_array[i]->lock      = port_array[0]->lock;
3397                         port_array[i]->irq_level = port_array[0]->irq_level;
3398                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3399                         alloc_dma_bufs(port_array[i]);
3400                 }
3401
3402                 if (request_irq(port_array[0]->irq_level,
3403                                         slgt_interrupt,
3404                                         port_array[0]->irq_flags,
3405                                         port_array[0]->device_name,
3406                                         port_array[0]) < 0) {
3407                         DBGERR(("%s request_irq failed IRQ=%d\n",
3408                                 port_array[0]->device_name,
3409                                 port_array[0]->irq_level));
3410                 } else {
3411                         port_array[0]->irq_requested = 1;
3412                         adapter_test(port_array[0]);
3413                         for (i=1 ; i < port_count ; i++) {
3414                                 port_array[i]->init_error = port_array[0]->init_error;
3415                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3416                         }
3417                 }
3418         }
3419 }
3420
3421 static int __devinit init_one(struct pci_dev *dev,
3422                               const struct pci_device_id *ent)
3423 {
3424         if (pci_enable_device(dev)) {
3425                 printk("error enabling pci device %p\n", dev);
3426                 return -EIO;
3427         }
3428         pci_set_master(dev);
3429         device_init(slgt_device_count, dev);
3430         return 0;
3431 }
3432
3433 static void __devexit remove_one(struct pci_dev *dev)
3434 {
3435 }
3436
3437 static struct tty_operations ops = {
3438         .open = open,
3439         .close = close,
3440         .write = write,
3441         .put_char = put_char,
3442         .flush_chars = flush_chars,
3443         .write_room = write_room,
3444         .chars_in_buffer = chars_in_buffer,
3445         .flush_buffer = flush_buffer,
3446         .ioctl = ioctl,
3447         .throttle = throttle,
3448         .unthrottle = unthrottle,
3449         .send_xchar = send_xchar,
3450         .break_ctl = set_break,
3451         .wait_until_sent = wait_until_sent,
3452         .read_proc = read_proc,
3453         .set_termios = set_termios,
3454         .stop = tx_hold,
3455         .start = tx_release,
3456         .hangup = hangup,
3457         .tiocmget = tiocmget,
3458         .tiocmset = tiocmset,
3459 };
3460
3461 static void slgt_cleanup(void)
3462 {
3463         int rc;
3464         struct slgt_info *info;
3465         struct slgt_info *tmp;
3466
3467         printk("unload %s %s\n", driver_name, driver_version);
3468
3469         if (serial_driver) {
3470                 if ((rc = tty_unregister_driver(serial_driver)))
3471                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3472                 put_tty_driver(serial_driver);
3473         }
3474
3475         /* reset devices */
3476         info = slgt_device_list;
3477         while(info) {
3478                 reset_port(info);
3479                 info = info->next_device;
3480         }
3481
3482         /* release devices */
3483         info = slgt_device_list;
3484         while(info) {
3485 #ifdef CONFIG_HDLC
3486                 hdlcdev_exit(info);
3487 #endif
3488                 free_dma_bufs(info);
3489                 free_tmp_rbuf(info);
3490                 if (info->port_num == 0)
3491                         release_resources(info);
3492                 tmp = info;
3493                 info = info->next_device;
3494                 kfree(tmp);
3495         }
3496
3497         if (pci_registered)
3498                 pci_unregister_driver(&pci_driver);
3499 }
3500
3501 /*
3502  *  Driver initialization entry point.
3503  */
3504 static int __init slgt_init(void)
3505 {
3506         int rc;
3507
3508         printk("%s %s\n", driver_name, driver_version);
3509
3510         slgt_device_count = 0;
3511         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3512                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3513                 return rc;
3514         }
3515         pci_registered = 1;
3516
3517         if (!slgt_device_list) {
3518                 printk("%s no devices found\n",driver_name);
3519                 return -ENODEV;
3520         }
3521
3522         serial_driver = alloc_tty_driver(MAX_DEVICES);
3523         if (!serial_driver) {
3524                 rc = -ENOMEM;
3525                 goto error;
3526         }
3527
3528         /* Initialize the tty_driver structure */
3529
3530         serial_driver->owner = THIS_MODULE;
3531         serial_driver->driver_name = tty_driver_name;
3532         serial_driver->name = tty_dev_prefix;
3533         serial_driver->major = ttymajor;
3534         serial_driver->minor_start = 64;
3535         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3536         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3537         serial_driver->init_termios = tty_std_termios;
3538         serial_driver->init_termios.c_cflag =
3539                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3540         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3541         tty_set_operations(serial_driver, &ops);
3542         if ((rc = tty_register_driver(serial_driver)) < 0) {
3543                 DBGERR(("%s can't register serial driver\n", driver_name));
3544                 put_tty_driver(serial_driver);
3545                 serial_driver = NULL;
3546                 goto error;
3547         }
3548
3549         printk("%s %s, tty major#%d\n",
3550                 driver_name, driver_version,
3551                 serial_driver->major);
3552
3553         return 0;
3554
3555 error:
3556         slgt_cleanup();
3557         return rc;
3558 }
3559
3560 static void __exit slgt_exit(void)
3561 {
3562         slgt_cleanup();
3563 }
3564
3565 module_init(slgt_init);
3566 module_exit(slgt_exit);
3567
3568 /*
3569  * register access routines
3570  */
3571
3572 #define CALC_REGADDR() \
3573         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3574         if (addr >= 0x80) \
3575                 reg_addr += (info->port_num) * 32;
3576
3577 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3578 {
3579         CALC_REGADDR();
3580         return readb((void __iomem *)reg_addr);
3581 }
3582
3583 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3584 {
3585         CALC_REGADDR();
3586         writeb(value, (void __iomem *)reg_addr);
3587 }
3588
3589 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3590 {
3591         CALC_REGADDR();
3592         return readw((void __iomem *)reg_addr);
3593 }
3594
3595 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3596 {
3597         CALC_REGADDR();
3598         writew(value, (void __iomem *)reg_addr);
3599 }
3600
3601 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3602 {
3603         CALC_REGADDR();
3604         return readl((void __iomem *)reg_addr);
3605 }
3606
3607 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3608 {
3609         CALC_REGADDR();
3610         writel(value, (void __iomem *)reg_addr);
3611 }
3612
3613 static void rdma_reset(struct slgt_info *info)
3614 {
3615         unsigned int i;
3616
3617         /* set reset bit */
3618         wr_reg32(info, RDCSR, BIT1);
3619
3620         /* wait for enable bit cleared */
3621         for(i=0 ; i < 1000 ; i++)
3622                 if (!(rd_reg32(info, RDCSR) & BIT0))
3623                         break;
3624 }
3625
3626 static void tdma_reset(struct slgt_info *info)
3627 {
3628         unsigned int i;
3629
3630         /* set reset bit */
3631         wr_reg32(info, TDCSR, BIT1);
3632
3633         /* wait for enable bit cleared */
3634         for(i=0 ; i < 1000 ; i++)
3635                 if (!(rd_reg32(info, TDCSR) & BIT0))
3636                         break;
3637 }
3638
3639 /*
3640  * enable internal loopback
3641  * TxCLK and RxCLK are generated from BRG
3642  * and TxD is looped back to RxD internally.
3643  */
3644 static void enable_loopback(struct slgt_info *info)
3645 {
3646         /* SCR (serial control) BIT2=looopback enable */
3647         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3648
3649         if (info->params.mode != MGSL_MODE_ASYNC) {
3650                 /* CCR (clock control)
3651                  * 07..05  tx clock source (010 = BRG)
3652                  * 04..02  rx clock source (010 = BRG)
3653                  * 01      auxclk enable   (0 = disable)
3654                  * 00      BRG enable      (1 = enable)
3655                  *
3656                  * 0100 1001
3657                  */
3658                 wr_reg8(info, CCR, 0x49);
3659
3660                 /* set speed if available, otherwise use default */
3661                 if (info->params.clock_speed)
3662                         set_rate(info, info->params.clock_speed);
3663                 else
3664                         set_rate(info, 3686400);
3665         }
3666 }
3667
3668 /*
3669  *  set baud rate generator to specified rate
3670  */
3671 static void set_rate(struct slgt_info *info, u32 rate)
3672 {
3673         unsigned int div;
3674         static unsigned int osc = 14745600;
3675
3676         /* div = osc/rate - 1
3677          *
3678          * Round div up if osc/rate is not integer to
3679          * force to next slowest rate.
3680          */
3681
3682         if (rate) {
3683                 div = osc/rate;
3684                 if (!(osc % rate) && div)
3685                         div--;
3686                 wr_reg16(info, BDR, (unsigned short)div);
3687         }
3688 }
3689
3690 static void rx_stop(struct slgt_info *info)
3691 {
3692         unsigned short val;
3693
3694         /* disable and reset receiver */
3695         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3696         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3697         wr_reg16(info, RCR, val);                  /* clear reset bit */
3698
3699         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3700
3701         /* clear pending rx interrupts */
3702         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3703
3704         rdma_reset(info);
3705
3706         info->rx_enabled = 0;
3707         info->rx_restart = 0;
3708 }
3709
3710 static void rx_start(struct slgt_info *info)
3711 {
3712         unsigned short val;
3713
3714         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3715
3716         /* clear pending rx overrun IRQ */
3717         wr_reg16(info, SSR, IRQ_RXOVER);
3718
3719         /* reset and disable receiver */
3720         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3721         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3722         wr_reg16(info, RCR, val);                  /* clear reset bit */
3723
3724         rdma_reset(info);
3725         reset_rbufs(info);
3726
3727         /* set 1st descriptor address */
3728         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3729
3730         if (info->params.mode != MGSL_MODE_ASYNC) {
3731                 /* enable rx DMA and DMA interrupt */
3732                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3733         } else {
3734                 /* enable saving of rx status, rx DMA and DMA interrupt */
3735                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3736         }
3737
3738         slgt_irq_on(info, IRQ_RXOVER);
3739
3740         /* enable receiver */
3741         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3742
3743         info->rx_restart = 0;
3744         info->rx_enabled = 1;
3745 }
3746
3747 static void tx_start(struct slgt_info *info)
3748 {
3749         if (!info->tx_enabled) {
3750                 wr_reg16(info, TCR,
3751                         (unsigned short)(rd_reg16(info, TCR) | BIT1));
3752                 info->tx_enabled = TRUE;
3753         }
3754
3755         if (info->tx_count) {
3756                 info->drop_rts_on_tx_done = 0;
3757
3758                 if (info->params.mode != MGSL_MODE_ASYNC) {
3759                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3760                                 get_signals(info);
3761                                 if (!(info->signals & SerialSignal_RTS)) {
3762                                         info->signals |= SerialSignal_RTS;
3763                                         set_signals(info);
3764                                         info->drop_rts_on_tx_done = 1;
3765                                 }
3766                         }
3767
3768                         slgt_irq_off(info, IRQ_TXDATA);
3769                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3770                         /* clear tx idle and underrun status bits */
3771                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3772
3773                         if (!(rd_reg32(info, TDCSR) & BIT0)) {
3774                                 /* tx DMA stopped, restart tx DMA */
3775                                 tdma_reset(info);
3776                                 /* set 1st descriptor address */
3777                                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3778                                 if (info->params.mode == MGSL_MODE_RAW)
3779                                         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3780                                 else
3781                                         wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3782                         }
3783
3784                         if (info->params.mode != MGSL_MODE_RAW) {
3785                                 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3786                                 add_timer(&info->tx_timer);
3787                         }
3788                 } else {
3789                         tdma_reset(info);
3790                         /* set 1st descriptor address */
3791                         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3792
3793                         slgt_irq_off(info, IRQ_TXDATA);
3794                         slgt_irq_on(info, IRQ_TXIDLE);
3795                         /* clear tx idle status bit */
3796                         wr_reg16(info, SSR, IRQ_TXIDLE);
3797
3798                         /* enable tx DMA */
3799                         wr_reg32(info, TDCSR, BIT0);
3800                 }
3801
3802                 info->tx_active = 1;
3803         }
3804 }
3805
3806 static void tx_stop(struct slgt_info *info)
3807 {
3808         unsigned short val;
3809
3810         del_timer(&info->tx_timer);
3811
3812         tdma_reset(info);
3813
3814         /* reset and disable transmitter */
3815         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3816         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3817         wr_reg16(info, TCR, val);                  /* clear reset */
3818
3819         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3820
3821         /* clear tx idle and underrun status bit */
3822         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3823
3824         reset_tbufs(info);
3825
3826         info->tx_enabled = 0;
3827         info->tx_active  = 0;
3828 }
3829
3830 static void reset_port(struct slgt_info *info)
3831 {
3832         if (!info->reg_addr)
3833                 return;
3834
3835         tx_stop(info);
3836         rx_stop(info);
3837
3838         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3839         set_signals(info);
3840
3841         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3842 }
3843
3844 static void reset_adapter(struct slgt_info *info)
3845 {
3846         int i;
3847         for (i=0; i < info->port_count; ++i) {
3848                 if (info->port_array[i])
3849                         reset_port(info->port_array[i]);
3850         }
3851 }
3852
3853 static void async_mode(struct slgt_info *info)
3854 {
3855         unsigned short val;
3856
3857         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3858         tx_stop(info);
3859         rx_stop(info);
3860
3861         /* TCR (tx control)
3862          *
3863          * 15..13  mode, 010=async
3864          * 12..10  encoding, 000=NRZ
3865          * 09      parity enable
3866          * 08      1=odd parity, 0=even parity
3867          * 07      1=RTS driver control
3868          * 06      1=break enable
3869          * 05..04  character length
3870          *         00=5 bits
3871          *         01=6 bits
3872          *         10=7 bits
3873          *         11=8 bits
3874          * 03      0=1 stop bit, 1=2 stop bits
3875          * 02      reset
3876          * 01      enable
3877          * 00      auto-CTS enable
3878          */
3879         val = 0x4000;
3880
3881         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3882                 val |= BIT7;
3883
3884         if (info->params.parity != ASYNC_PARITY_NONE) {
3885                 val |= BIT9;
3886                 if (info->params.parity == ASYNC_PARITY_ODD)
3887                         val |= BIT8;
3888         }
3889
3890         switch (info->params.data_bits)
3891         {
3892         case 6: val |= BIT4; break;
3893         case 7: val |= BIT5; break;
3894         case 8: val |= BIT5 + BIT4; break;
3895         }
3896
3897         if (info->params.stop_bits != 1)
3898                 val |= BIT3;
3899
3900         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3901                 val |= BIT0;
3902
3903         wr_reg16(info, TCR, val);
3904
3905         /* RCR (rx control)
3906          *
3907          * 15..13  mode, 010=async
3908          * 12..10  encoding, 000=NRZ
3909          * 09      parity enable
3910          * 08      1=odd parity, 0=even parity
3911          * 07..06  reserved, must be 0
3912          * 05..04  character length
3913          *         00=5 bits
3914          *         01=6 bits
3915          *         10=7 bits
3916          *         11=8 bits
3917          * 03      reserved, must be zero
3918          * 02      reset
3919          * 01      enable
3920          * 00      auto-DCD enable
3921          */
3922         val = 0x4000;
3923
3924         if (info->params.parity != ASYNC_PARITY_NONE) {
3925                 val |= BIT9;
3926                 if (info->params.parity == ASYNC_PARITY_ODD)
3927                         val |= BIT8;
3928         }
3929
3930         switch (info->params.data_bits)
3931         {
3932         case 6: val |= BIT4; break;
3933         case 7: val |= BIT5; break;
3934         case 8: val |= BIT5 + BIT4; break;
3935         }
3936
3937         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3938                 val |= BIT0;
3939
3940         wr_reg16(info, RCR, val);
3941
3942         /* CCR (clock control)
3943          *
3944          * 07..05  011 = tx clock source is BRG/16
3945          * 04..02  010 = rx clock source is BRG
3946          * 01      0 = auxclk disabled
3947          * 00      1 = BRG enabled
3948          *
3949          * 0110 1001
3950          */
3951         wr_reg8(info, CCR, 0x69);
3952
3953         msc_set_vcr(info);
3954
3955         /* SCR (serial control)
3956          *
3957          * 15  1=tx req on FIFO half empty
3958          * 14  1=rx req on FIFO half full
3959          * 13  tx data  IRQ enable
3960          * 12  tx idle  IRQ enable
3961          * 11  rx break on IRQ enable
3962          * 10  rx data  IRQ enable
3963          * 09  rx break off IRQ enable
3964          * 08  overrun  IRQ enable
3965          * 07  DSR      IRQ enable
3966          * 06  CTS      IRQ enable
3967          * 05  DCD      IRQ enable
3968          * 04  RI       IRQ enable
3969          * 03  reserved, must be zero
3970          * 02  1=txd->rxd internal loopback enable
3971          * 01  reserved, must be zero
3972          * 00  1=master IRQ enable
3973          */
3974         val = BIT15 + BIT14 + BIT0;
3975         wr_reg16(info, SCR, val);
3976
3977         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3978
3979         set_rate(info, info->params.data_rate * 16);
3980
3981         if (info->params.loopback)
3982                 enable_loopback(info);
3983 }
3984
3985 static void hdlc_mode(struct slgt_info *info)
3986 {
3987         unsigned short val;
3988
3989         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3990         tx_stop(info);
3991         rx_stop(info);
3992
3993         /* TCR (tx control)
3994          *
3995          * 15..13  mode, 000=HDLC 001=raw sync
3996          * 12..10  encoding
3997          * 09      CRC enable
3998          * 08      CRC32
3999          * 07      1=RTS driver control
4000          * 06      preamble enable
4001          * 05..04  preamble length
4002          * 03      share open/close flag
4003          * 02      reset
4004          * 01      enable
4005          * 00      auto-CTS enable
4006          */
4007         val = 0;
4008
4009         if (info->params.mode == MGSL_MODE_RAW)
4010                 val |= BIT13;
4011         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4012                 val |= BIT7;
4013
4014         switch(info->params.encoding)
4015         {
4016         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4017         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4018         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4019         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4020         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4021         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4022         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4023         }
4024
4025         switch (info->params.crc_type & HDLC_CRC_MASK)
4026         {
4027         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4028         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4029         }
4030
4031         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4032                 val |= BIT6;
4033
4034         switch (info->params.preamble_length)
4035         {
4036         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4037         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4038         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4039         }
4040
4041         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4042                 val |= BIT0;
4043
4044         wr_reg16(info, TCR, val);
4045
4046         /* TPR (transmit preamble) */
4047
4048         switch (info->params.preamble)
4049         {
4050         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4051         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4052         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4053         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4054         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4055         default:                          val = 0x7e; break;
4056         }
4057         wr_reg8(info, TPR, (unsigned char)val);
4058
4059         /* RCR (rx control)
4060          *
4061          * 15..13  mode, 000=HDLC 001=raw sync
4062          * 12..10  encoding
4063          * 09      CRC enable
4064          * 08      CRC32
4065          * 07..03  reserved, must be 0
4066          * 02      reset
4067          * 01      enable
4068          * 00      auto-DCD enable
4069          */
4070         val = 0;
4071
4072         if (info->params.mode == MGSL_MODE_RAW)
4073                 val |= BIT13;
4074
4075         switch(info->params.encoding)
4076         {
4077         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4078         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4079         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4080         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4081         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4082         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4083         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4084         }
4085
4086         switch (info->params.crc_type & HDLC_CRC_MASK)
4087         {
4088         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4089         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4090         }
4091
4092         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4093                 val |= BIT0;
4094
4095         wr_reg16(info, RCR, val);
4096
4097         /* CCR (clock control)
4098          *
4099          * 07..05  tx clock source
4100          * 04..02  rx clock source
4101          * 01      auxclk enable
4102          * 00      BRG enable
4103          */
4104         val = 0;
4105
4106         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4107         {
4108                 // when RxC source is DPLL, BRG generates 16X DPLL
4109                 // reference clock, so take TxC from BRG/16 to get
4110                 // transmit clock at actual data rate
4111                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4112                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4113                 else
4114                         val |= BIT6;    /* 010, txclk = BRG */
4115         }
4116         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4117                 val |= BIT7;    /* 100, txclk = DPLL Input */
4118         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4119                 val |= BIT5;    /* 001, txclk = RXC Input */
4120
4121         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4122                 val |= BIT3;    /* 010, rxclk = BRG */
4123         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4124                 val |= BIT4;    /* 100, rxclk = DPLL */
4125         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4126                 val |= BIT2;    /* 001, rxclk = TXC Input */
4127
4128         if (info->params.clock_speed)
4129                 val |= BIT1 + BIT0;
4130
4131         wr_reg8(info, CCR, (unsigned char)val);
4132
4133         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4134         {
4135                 // program DPLL mode
4136                 switch(info->params.encoding)
4137                 {
4138                 case HDLC_ENCODING_BIPHASE_MARK:
4139                 case HDLC_ENCODING_BIPHASE_SPACE:
4140                         val = BIT7; break;
4141                 case HDLC_ENCODING_BIPHASE_LEVEL:
4142                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4143                         val = BIT7 + BIT6; break;
4144                 default: val = BIT6;    // NRZ encodings
4145                 }
4146                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4147
4148                 // DPLL requires a 16X reference clock from BRG
4149                 set_rate(info, info->params.clock_speed * 16);
4150         }
4151         else
4152                 set_rate(info, info->params.clock_speed);
4153
4154         tx_set_idle(info);
4155
4156         msc_set_vcr(info);
4157
4158         /* SCR (serial control)
4159          *
4160          * 15  1=tx req on FIFO half empty
4161          * 14  1=rx req on FIFO half full
4162          * 13  tx data  IRQ enable
4163          * 12  tx idle  IRQ enable
4164          * 11  underrun IRQ enable
4165          * 10  rx data  IRQ enable
4166          * 09  rx idle  IRQ enable
4167          * 08  overrun  IRQ enable
4168          * 07  DSR      IRQ enable
4169          * 06  CTS      IRQ enable
4170          * 05  DCD      IRQ enable
4171          * 04  RI       IRQ enable
4172          * 03  reserved, must be zero
4173          * 02  1=txd->rxd internal loopback enable
4174          * 01  reserved, must be zero
4175          * 00  1=master IRQ enable
4176          */
4177         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4178
4179         if (info->params.loopback)
4180                 enable_loopback(info);
4181 }
4182
4183 /*
4184  *  set transmit idle mode
4185  */
4186 static void tx_set_idle(struct slgt_info *info)
4187 {
4188         unsigned char val;
4189         unsigned short tcr;
4190
4191         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4192          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4193          */
4194         tcr = rd_reg16(info, TCR);
4195         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4196                 /* disable preamble, set idle size to 16 bits */
4197                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4198                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4199                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4200         } else if (!(tcr & BIT6)) {
4201                 /* preamble is disabled, set idle size to 8 bits */
4202                 tcr &= ~(BIT5 + BIT4);
4203         }
4204         wr_reg16(info, TCR, tcr);
4205
4206         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4207                 /* LSB of custom tx idle specified in tx idle register */
4208                 val = (unsigned char)(info->idle_mode & 0xff);
4209         } else {
4210                 /* standard 8 bit idle patterns */
4211                 switch(info->idle_mode)
4212                 {
4213                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4214                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4215                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4216                 case HDLC_TXIDLE_ZEROS:
4217                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4218                 default:                         val = 0xff;
4219                 }
4220         }
4221
4222         wr_reg8(info, TIR, val);
4223 }
4224
4225 /*
4226  * get state of V24 status (input) signals
4227  */
4228 static void get_signals(struct slgt_info *info)
4229 {
4230         unsigned short status = rd_reg16(info, SSR);
4231
4232         /* clear all serial signals except DTR and RTS */
4233         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4234
4235         if (status & BIT3)
4236                 info->signals |= SerialSignal_DSR;
4237         if (status & BIT2)
4238                 info->signals |= SerialSignal_CTS;
4239         if (status & BIT1)
4240                 info->signals |= SerialSignal_DCD;
4241         if (status & BIT0)
4242                 info->signals |= SerialSignal_RI;
4243 }
4244
4245 /*
4246  * set V.24 Control Register based on current configuration
4247  */
4248 static void msc_set_vcr(struct slgt_info *info)
4249 {
4250         unsigned char val = 0;
4251
4252         /* VCR (V.24 control)
4253          *
4254          * 07..04  serial IF select
4255          * 03      DTR
4256          * 02      RTS
4257          * 01      LL
4258          * 00      RL
4259          */
4260
4261         switch(info->if_mode & MGSL_INTERFACE_MASK)
4262         {
4263         case MGSL_INTERFACE_RS232:
4264                 val |= BIT5; /* 0010 */
4265                 break;
4266         case MGSL_INTERFACE_V35:
4267                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4268                 break;
4269         case MGSL_INTERFACE_RS422:
4270                 val |= BIT6; /* 0100 */
4271                 break;
4272         }
4273
4274         if (info->signals & SerialSignal_DTR)
4275                 val |= BIT3;
4276         if (info->signals & SerialSignal_RTS)
4277                 val |= BIT2;
4278         if (info->if_mode & MGSL_INTERFACE_LL)
4279                 val |= BIT1;
4280         if (info->if_mode & MGSL_INTERFACE_RL)
4281                 val |= BIT0;
4282         wr_reg8(info, VCR, val);
4283 }
4284
4285 /*
4286  * set state of V24 control (output) signals
4287  */
4288 static void set_signals(struct slgt_info *info)
4289 {
4290         unsigned char val = rd_reg8(info, VCR);
4291         if (info->signals & SerialSignal_DTR)
4292                 val |= BIT3;
4293         else
4294                 val &= ~BIT3;
4295         if (info->signals & SerialSignal_RTS)
4296                 val |= BIT2;
4297         else
4298                 val &= ~BIT2;
4299         wr_reg8(info, VCR, val);
4300 }
4301
4302 /*
4303  * free range of receive DMA buffers (i to last)
4304  */
4305 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4306 {
4307         int done = 0;
4308
4309         while(!done) {
4310                 /* reset current buffer for reuse */
4311                 info->rbufs[i].status = 0;
4312                 if (info->params.mode == MGSL_MODE_RAW)
4313                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4314                 else
4315                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4316
4317                 if (i == last)
4318                         done = 1;
4319                 if (++i == info->rbuf_count)
4320                         i = 0;
4321         }
4322         info->rbuf_current = i;
4323 }
4324
4325 /*
4326  * mark all receive DMA buffers as free
4327  */
4328 static void reset_rbufs(struct slgt_info *info)
4329 {
4330         free_rbufs(info, 0, info->rbuf_count - 1);
4331 }
4332
4333 /*
4334  * pass receive HDLC frame to upper layer
4335  *
4336  * return 1 if frame available, otherwise 0
4337  */
4338 static int rx_get_frame(struct slgt_info *info)
4339 {
4340         unsigned int start, end;
4341         unsigned short status;
4342         unsigned int framesize = 0;
4343         int rc = 0;
4344         unsigned long flags;
4345         struct tty_struct *tty = info->tty;
4346         unsigned char addr_field = 0xff;
4347         unsigned int crc_size = 0;
4348
4349         switch (info->params.crc_type & HDLC_CRC_MASK) {
4350         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4351         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4352         }
4353
4354 check_again:
4355
4356         framesize = 0;
4357         addr_field = 0xff;
4358         start = end = info->rbuf_current;
4359
4360         for (;;) {
4361                 if (!desc_complete(info->rbufs[end]))
4362                         goto cleanup;
4363
4364                 if (framesize == 0 && info->params.addr_filter != 0xff)
4365                         addr_field = info->rbufs[end].buf[0];
4366
4367                 framesize += desc_count(info->rbufs[end]);
4368
4369                 if (desc_eof(info->rbufs[end]))
4370                         break;
4371
4372                 if (++end == info->rbuf_count)
4373                         end = 0;
4374
4375                 if (end == info->rbuf_current) {
4376                         if (info->rx_enabled){
4377                                 spin_lock_irqsave(&info->lock,flags);
4378                                 rx_start(info);
4379                                 spin_unlock_irqrestore(&info->lock,flags);
4380                         }
4381                         goto cleanup;
4382                 }
4383         }
4384
4385         /* status
4386          *
4387          * 15      buffer complete
4388          * 14..06  reserved
4389          * 05..04  residue
4390          * 02      eof (end of frame)
4391          * 01      CRC error
4392          * 00      abort
4393          */
4394         status = desc_status(info->rbufs[end]);
4395
4396         /* ignore CRC bit if not using CRC (bit is undefined) */
4397         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4398                 status &= ~BIT1;
4399
4400         if (framesize == 0 ||
4401                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4402                 free_rbufs(info, start, end);
4403                 goto check_again;
4404         }
4405
4406         if (framesize < (2 + crc_size) || status & BIT0) {
4407                 info->icount.rxshort++;
4408                 framesize = 0;
4409         } else if (status & BIT1) {
4410                 info->icount.rxcrc++;
4411                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4412                         framesize = 0;
4413         }
4414
4415 #ifdef CONFIG_HDLC
4416         if (framesize == 0) {
4417                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4418                 stats->rx_errors++;
4419                 stats->rx_frame_errors++;
4420         }
4421 #endif
4422
4423         DBGBH(("%s rx frame status=%04X size=%d\n",
4424                 info->device_name, status, framesize));
4425         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4426
4427         if (framesize) {
4428                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4429                         framesize -= crc_size;
4430                         crc_size = 0;
4431                 }
4432
4433                 if (framesize > info->max_frame_size + crc_size)
4434                         info->icount.rxlong++;
4435                 else {
4436                         /* copy dma buffer(s) to contiguous temp buffer */
4437                         int copy_count = framesize;
4438                         int i = start;
4439                         unsigned char *p = info->tmp_rbuf;
4440                         info->tmp_rbuf_count = framesize;
4441
4442                         info->icount.rxok++;
4443
4444                         while(copy_count) {
4445                                 int partial_count = min(copy_count, DMABUFSIZE);
4446                                 memcpy(p, info->rbufs[i].buf, partial_count);
4447                                 p += partial_count;
4448                                 copy_count -= partial_count;
4449                                 if (++i == info->rbuf_count)
4450                                         i = 0;
4451                         }
4452
4453                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4454                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4455                                 framesize++;
4456                         }
4457
4458 #ifdef CONFIG_HDLC
4459                         if (info->netcount)
4460                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4461                         else
4462 #endif
4463                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4464                 }
4465         }
4466         free_rbufs(info, start, end);
4467         rc = 1;
4468
4469 cleanup:
4470         return rc;
4471 }
4472
4473 /*
4474  * pass receive buffer (RAW synchronous mode) to tty layer
4475  * return 1 if buffer available, otherwise 0
4476  */
4477 static int rx_get_buf(struct slgt_info *info)
4478 {
4479         unsigned int i = info->rbuf_current;
4480
4481         if (!desc_complete(info->rbufs[i]))
4482                 return 0;
4483         DBGDATA(info, info->rbufs[i].buf, desc_count(info->rbufs[i]), "rx");
4484         DBGINFO(("rx_get_buf size=%d\n", desc_count(info->rbufs[i])));
4485         ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4486                           info->flag_buf, desc_count(info->rbufs[i]));
4487         free_rbufs(info, i, i);
4488         return 1;
4489 }
4490
4491 static void reset_tbufs(struct slgt_info *info)
4492 {
4493         unsigned int i;
4494         info->tbuf_current = 0;
4495         for (i=0 ; i < info->tbuf_count ; i++) {
4496                 info->tbufs[i].status = 0;
4497                 info->tbufs[i].count  = 0;
4498         }
4499 }
4500
4501 /*
4502  * return number of free transmit DMA buffers
4503  */
4504 static unsigned int free_tbuf_count(struct slgt_info *info)
4505 {
4506         unsigned int count = 0;
4507         unsigned int i = info->tbuf_current;
4508
4509         do
4510         {
4511                 if (desc_count(info->tbufs[i]))
4512                         break; /* buffer in use */
4513                 ++count;
4514                 if (++i == info->tbuf_count)
4515                         i=0;
4516         } while (i != info->tbuf_current);
4517
4518         /* last buffer with zero count may be in use, assume it is */
4519         if (count)
4520                 --count;
4521
4522         return count;
4523 }
4524
4525 /*
4526  * load transmit DMA buffer(s) with data
4527  */
4528 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4529 {
4530         unsigned short count;
4531         unsigned int i;
4532         struct slgt_desc *d;
4533
4534         if (size == 0)
4535                 return;
4536
4537         DBGDATA(info, buf, size, "tx");
4538
4539         info->tbuf_start = i = info->tbuf_current;
4540
4541         while (size) {
4542                 d = &info->tbufs[i];
4543                 if (++i == info->tbuf_count)
4544                         i = 0;
4545
4546                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4547                 memcpy(d->buf, buf, count);
4548
4549                 size -= count;
4550                 buf  += count;
4551
4552                 if (!size && info->params.mode != MGSL_MODE_RAW)
4553                         set_desc_eof(*d, 1); /* HDLC: set EOF of last desc */
4554                 else
4555                         set_desc_eof(*d, 0);
4556
4557                 set_desc_count(*d, count);
4558         }
4559
4560         info->tbuf_current = i;
4561 }
4562
4563 static int register_test(struct slgt_info *info)
4564 {
4565         static unsigned short patterns[] =
4566                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4567         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4568         unsigned int i;
4569         int rc = 0;
4570
4571         for (i=0 ; i < count ; i++) {
4572                 wr_reg16(info, TIR, patterns[i]);
4573                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4574                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4575                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4576                         rc = -ENODEV;
4577                         break;
4578                 }
4579         }
4580         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4581         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4582         return rc;
4583 }
4584
4585 static int irq_test(struct slgt_info *info)
4586 {
4587         unsigned long timeout;
4588         unsigned long flags;
4589         struct tty_struct *oldtty = info->tty;
4590         u32 speed = info->params.data_rate;
4591
4592         info->params.data_rate = 921600;
4593         info->tty = NULL;
4594
4595         spin_lock_irqsave(&info->lock, flags);
4596         async_mode(info);
4597         slgt_irq_on(info, IRQ_TXIDLE);
4598
4599         /* enable transmitter */
4600         wr_reg16(info, TCR,
4601                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4602
4603         /* write one byte and wait for tx idle */
4604         wr_reg16(info, TDR, 0);
4605
4606         /* assume failure */
4607         info->init_error = DiagStatus_IrqFailure;
4608         info->irq_occurred = FALSE;
4609
4610         spin_unlock_irqrestore(&info->lock, flags);
4611
4612         timeout=100;
4613         while(timeout-- && !info->irq_occurred)
4614                 msleep_interruptible(10);
4615
4616         spin_lock_irqsave(&info->lock,flags);
4617         reset_port(info);
4618         spin_unlock_irqrestore(&info->lock,flags);
4619
4620         info->params.data_rate = speed;
4621         info->tty = oldtty;
4622
4623         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4624         return info->irq_occurred ? 0 : -ENODEV;
4625 }
4626
4627 static int loopback_test_rx(struct slgt_info *info)
4628 {
4629         unsigned char *src, *dest;
4630         int count;
4631
4632         if (desc_complete(info->rbufs[0])) {
4633                 count = desc_count(info->rbufs[0]);
4634                 src   = info->rbufs[0].buf;
4635                 dest  = info->tmp_rbuf;
4636
4637                 for( ; count ; count-=2, src+=2) {
4638                         /* src=data byte (src+1)=status byte */
4639                         if (!(*(src+1) & (BIT9 + BIT8))) {
4640                                 *dest = *src;
4641                                 dest++;
4642                                 info->tmp_rbuf_count++;
4643                         }
4644                 }
4645                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4646                 return 1;
4647         }
4648         return 0;
4649 }
4650
4651 static int loopback_test(struct slgt_info *info)
4652 {
4653 #define TESTFRAMESIZE 20
4654
4655         unsigned long timeout;
4656         u16 count = TESTFRAMESIZE;
4657         unsigned char buf[TESTFRAMESIZE];
4658         int rc = -ENODEV;
4659         unsigned long flags;
4660
4661         struct tty_struct *oldtty = info->tty;
4662         MGSL_PARAMS params;
4663
4664         memcpy(&params, &info->params, sizeof(params));
4665
4666         info->params.mode = MGSL_MODE_ASYNC;
4667         info->params.data_rate = 921600;
4668         info->params.loopback = 1;
4669         info->tty = NULL;
4670
4671         /* build and send transmit frame */
4672         for (count = 0; count < TESTFRAMESIZE; ++count)
4673                 buf[count] = (unsigned char)count;
4674
4675         info->tmp_rbuf_count = 0;
4676         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4677
4678         /* program hardware for HDLC and enabled receiver */
4679         spin_lock_irqsave(&info->lock,flags);
4680         async_mode(info);
4681         rx_start(info);
4682         info->tx_count = count;
4683         tx_load(info, buf, count);
4684         tx_start(info);
4685         spin_unlock_irqrestore(&info->lock, flags);
4686
4687         /* wait for receive complete */
4688         for (timeout = 100; timeout; --timeout) {
4689                 msleep_interruptible(10);
4690                 if (loopback_test_rx(info)) {
4691                         rc = 0;
4692                         break;
4693                 }
4694         }
4695
4696         /* verify received frame length and contents */
4697         if (!rc && (info->tmp_rbuf_count != count ||
4698                   memcmp(buf, info->tmp_rbuf, count))) {
4699                 rc = -ENODEV;
4700         }
4701
4702         spin_lock_irqsave(&info->lock,flags);
4703         reset_adapter(info);
4704         spin_unlock_irqrestore(&info->lock,flags);
4705
4706         memcpy(&info->params, &params, sizeof(info->params));
4707         info->tty = oldtty;
4708
4709         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4710         return rc;
4711 }
4712
4713 static int adapter_test(struct slgt_info *info)
4714 {
4715         DBGINFO(("testing %s\n", info->device_name));
4716         if (register_test(info) < 0) {
4717                 printk("register test failure %s addr=%08X\n",
4718                         info->device_name, info->phys_reg_addr);
4719         } else if (irq_test(info) < 0) {
4720                 printk("IRQ test failure %s IRQ=%d\n",
4721                         info->device_name, info->irq_level);
4722         } else if (loopback_test(info) < 0) {
4723                 printk("loopback test failure %s\n", info->device_name);
4724         }
4725         return info->init_error;
4726 }
4727
4728 /*
4729  * transmit timeout handler
4730  */
4731 static void tx_timeout(unsigned long context)
4732 {
4733         struct slgt_info *info = (struct slgt_info*)context;
4734         unsigned long flags;
4735
4736         DBGINFO(("%s tx_timeout\n", info->device_name));
4737         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4738                 info->icount.txtimeout++;
4739         }
4740         spin_lock_irqsave(&info->lock,flags);
4741         info->tx_active = 0;
4742         info->tx_count = 0;
4743         spin_unlock_irqrestore(&info->lock,flags);
4744
4745 #ifdef CONFIG_HDLC
4746         if (info->netcount)
4747                 hdlcdev_tx_done(info);
4748         else
4749 #endif
4750                 bh_transmit(info);
4751 }
4752
4753 /*
4754  * receive buffer polling timer
4755  */
4756 static void rx_timeout(unsigned long context)
4757 {
4758         struct slgt_info *info = (struct slgt_info*)context;
4759         unsigned long flags;
4760
4761         DBGINFO(("%s rx_timeout\n", info->device_name));
4762         spin_lock_irqsave(&info->lock, flags);
4763         info->pending_bh |= BH_RECEIVE;
4764         spin_unlock_irqrestore(&info->lock, flags);
4765         bh_handler(info);
4766 }
4767