drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  14 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  17 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  18 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  19 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  20 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  21 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  22 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  23 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  24 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  25 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  26 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  27 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  28 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  29 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  30 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  31 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  32 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  33 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  34 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  35 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  36 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  37 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  38 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  39 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  40 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  41 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  42 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  43 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  44 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  45 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  46 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  47 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  48 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  49 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  50 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  51 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  52 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  53
  54 /* cover 915 and 945 variants */
  55 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  56                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  57                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  58                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  59                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  60                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  61
  62 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  63                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  64                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  65                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  66                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  67                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  68
  69 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  70                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  71                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  72                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  73                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  74
  75 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  76                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  77
  78 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  79                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  80                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  81                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  82                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)
  85
  86 extern int agp_memory_reserved;
  87
  88
  89 /* Intel 815 register */
  90 #define INTEL_815_APCONT        0x51
  91 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  92
  93 /* Intel i820 registers */
  94 #define INTEL_I820_RDCR         0x51
  95 #define INTEL_I820_ERRSTS       0xc8
  96
  97 /* Intel i840 registers */
  98 #define INTEL_I840_MCHCFG       0x50
  99 #define INTEL_I840_ERRSTS       0xc8
 100
 101 /* Intel i850 registers */
 102 #define INTEL_I850_MCHCFG       0x50
 103 #define INTEL_I850_ERRSTS       0xc8
 104
 105 /* intel 915G registers */
 106 #define I915_GMADDR     0x18
 107 #define I915_MMADDR     0x10
 108 #define I915_PTEADDR    0x1C
 109 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 110 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 111 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 112 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 113 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 114 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 115 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 116 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 117
 118 #define I915_IFPADDR    0x60
 119
 120 /* Intel 965G registers */
 121 #define I965_MSAC 0x62
 122 #define I965_IFPADDR    0x70
 123
 124 /* Intel 7505 registers */
 125 #define INTEL_I7505_APSIZE      0x74
 126 #define INTEL_I7505_NCAPID      0x60
 127 #define INTEL_I7505_NISTAT      0x6c
 128 #define INTEL_I7505_ATTBASE     0x78
 129 #define INTEL_I7505_ERRSTS      0x42
 130 #define INTEL_I7505_AGPCTRL     0x70
 131 #define INTEL_I7505_MCHCFG      0x50
 132
 133 static const struct aper_size_info_fixed intel_i810_sizes[] =
 134 {
 135         {64, 16384, 4},
 136         /* The 32M mode still requires a 64k gatt */
 137         {32, 8192, 4}
 138 };
 139
 140 #define AGP_DCACHE_MEMORY       1
 141 #define AGP_PHYS_MEMORY         2
 142 #define INTEL_AGP_CACHED_MEMORY 3
 143
 144 static struct gatt_mask intel_i810_masks[] =
 145 {
 146         {.mask = I810_PTE_VALID, .type = 0},
 147         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 148         {.mask = I810_PTE_VALID, .type = 0},
 149         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 150          .type = INTEL_AGP_CACHED_MEMORY}
 151 };
 152
 153 static struct _intel_private {
 154         struct pci_dev *pcidev; /* device one */
 155         u8 __iomem *registers;
 156         u32 __iomem *gtt;               /* I915G */
 157         int num_dcache_entries;
 158         /* gtt_entries is the number of gtt entries that are already mapped
 159          * to stolen memory.  Stolen memory is larger than the memory mapped
 160          * through gtt_entries, as it includes some reserved space for the BIOS
 161          * popup and for the GTT.
 162          */
 163         int gtt_entries;                        /* i830+ */
 164         union {
 165                 void __iomem *i9xx_flush_page;
 166                 void *i8xx_flush_page;
 167         };
 168         struct page *i8xx_page;
 169         struct resource ifp_resource;
 170         int resource_valid;
 171 } intel_private;
 172
 173 static int intel_i810_fetch_size(void)
 174 {
 175         u32 smram_miscc;
 176         struct aper_size_info_fixed *values;
 177
 178         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 179         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 180
 181         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 182                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 183                 return 0;
 184         }
 185         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 186                 agp_bridge->previous_size =
 187                         agp_bridge->current_size = (void *) (values + 1);
 188                 agp_bridge->aperture_size_idx = 1;
 189                 return values[1].size;
 190         } else {
 191                 agp_bridge->previous_size =
 192                         agp_bridge->current_size = (void *) (values);
 193                 agp_bridge->aperture_size_idx = 0;
 194                 return values[0].size;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int intel_i810_configure(void)
 201 {
 202         struct aper_size_info_fixed *current_size;
 203         u32 temp;
 204         int i;
 205
 206         current_size = A_SIZE_FIX(agp_bridge->current_size);
 207
 208         if (!intel_private.registers) {
 209                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 210                 temp &= 0xfff80000;
 211
 212                 intel_private.registers = ioremap(temp, 128 * 4096);
 213                 if (!intel_private.registers) {
 214                         dev_err(&intel_private.pcidev->dev,
 215                                 "can't remap memory\n");
 216                         return -ENOMEM;
 217                 }
 218         }
 219
 220         if ((readl(intel_private.registers+I810_DRAM_CTL)
 221                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 222                 /* This will need to be dynamically assigned */
 223                 dev_info(&intel_private.pcidev->dev,
 224                          "detected 4MB dedicated video ram\n");
 225                 intel_private.num_dcache_entries = 1024;
 226         }
 227         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 228         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 229         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 230         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 231
 232         if (agp_bridge->driver->needs_scratch_page) {
 233                 for (i = 0; i < current_size->num_entries; i++) {
 234                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 235                 }
 236                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 237         }
 238         global_cache_flush();
 239         return 0;
 240 }
 241
 242 static void intel_i810_cleanup(void)
 243 {
 244         writel(0, intel_private.registers+I810_PGETBL_CTL);
 245         readl(intel_private.registers); /* PCI Posting. */
 246         iounmap(intel_private.registers);
 247 }
 248
 249 static void intel_i810_tlbflush(struct agp_memory *mem)
 250 {
 251         return;
 252 }
 253
 254 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 255 {
 256         return;
 257 }
 258
 259 /* Exists to support ARGB cursors */
 260 static struct page *i8xx_alloc_pages(void)
 261 {
 262         struct page *page;
 263
 264         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 265         if (page == NULL)
 266                 return NULL;
 267
 268         if (set_pages_uc(page, 4) < 0) {
 269                 set_pages_wb(page, 4);
 270                 __free_pages(page, 2);
 271                 return NULL;
 272         }
 273         get_page(page);
 274         atomic_inc(&agp_bridge->current_memory_agp);
 275         return page;
 276 }
 277
 278 static void i8xx_destroy_pages(struct page *page)
 279 {
 280         if (page == NULL)
 281                 return;
 282
 283         set_pages_wb(page, 4);
 284         put_page(page);
 285         __free_pages(page, 2);
 286         atomic_dec(&agp_bridge->current_memory_agp);
 287 }
 288
 289 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 290                                         int type)
 291 {
 292         if (type < AGP_USER_TYPES)
 293                 return type;
 294         else if (type == AGP_USER_CACHED_MEMORY)
 295                 return INTEL_AGP_CACHED_MEMORY;
 296         else
 297                 return 0;
 298 }
 299
 300 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 301                                 int type)
 302 {
 303         int i, j, num_entries;
 304         void *temp;
 305         int ret = -EINVAL;
 306         int mask_type;
 307
 308         if (mem->page_count == 0)
 309                 goto out;
 310
 311         temp = agp_bridge->current_size;
 312         num_entries = A_SIZE_FIX(temp)->num_entries;
 313
 314         if ((pg_start + mem->page_count) > num_entries)
 315                 goto out_err;
 316
 317
 318         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 319                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 320                         ret = -EBUSY;
 321                         goto out_err;
 322                 }
 323         }
 324
 325         if (type != mem->type)
 326                 goto out_err;
 327
 328         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 329
 330         switch (mask_type) {
 331         case AGP_DCACHE_MEMORY:
 332                 if (!mem->is_flushed)
 333                         global_cache_flush();
 334                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 335                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 336                                intel_private.registers+I810_PTE_BASE+(i*4));
 337                 }
 338                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 339                 break;
 340         case AGP_PHYS_MEMORY:
 341         case AGP_NORMAL_MEMORY:
 342                 if (!mem->is_flushed)
 343                         global_cache_flush();
 344                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 345                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 346                                                                mem->pages[i],
 347                                                                mask_type),
 348                                intel_private.registers+I810_PTE_BASE+(j*4));
 349                 }
 350                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 351                 break;
 352         default:
 353                 goto out_err;
 354         }
 355
 356         agp_bridge->driver->tlb_flush(mem);
 357 out:
 358         ret = 0;
 359 out_err:
 360         mem->is_flushed = true;
 361         return ret;
 362 }
 363
 364 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 365                                 int type)
 366 {
 367         int i;
 368
 369         if (mem->page_count == 0)
 370                 return 0;
 371
 372         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 373                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 374         }
 375         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 376
 377         agp_bridge->driver->tlb_flush(mem);
 378         return 0;
 379 }
 380
 381 /*
 382  * The i810/i830 requires a physical address to program its mouse
 383  * pointer into hardware.
 384  * However the Xserver still writes to it through the agp aperture.
 385  */
 386 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 387 {
 388         struct agp_memory *new;
 389         struct page *page;
 390
 391         switch (pg_count) {
 392         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 393                 break;
 394         case 4:
 395                 /* kludge to get 4 physical pages for ARGB cursor */
 396                 page = i8xx_alloc_pages();
 397                 break;
 398         default:
 399                 return NULL;
 400         }
 401
 402         if (page == NULL)
 403                 return NULL;
 404
 405         new = agp_create_memory(pg_count);
 406         if (new == NULL)
 407                 return NULL;
 408
 409         new->pages[0] = page;
 410         if (pg_count == 4) {
 411                 /* kludge to get 4 physical pages for ARGB cursor */
 412                 new->pages[1] = new->pages[0] + 1;
 413                 new->pages[2] = new->pages[1] + 1;
 414                 new->pages[3] = new->pages[2] + 1;
 415         }
 416         new->page_count = pg_count;
 417         new->num_scratch_pages = pg_count;
 418         new->type = AGP_PHYS_MEMORY;
 419         new->physical = page_to_phys(new->pages[0]);
 420         return new;
 421 }
 422
 423 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 424 {
 425         struct agp_memory *new;
 426
 427         if (type == AGP_DCACHE_MEMORY) {
 428                 if (pg_count != intel_private.num_dcache_entries)
 429                         return NULL;
 430
 431                 new = agp_create_memory(1);
 432                 if (new == NULL)
 433                         return NULL;
 434
 435                 new->type = AGP_DCACHE_MEMORY;
 436                 new->page_count = pg_count;
 437                 new->num_scratch_pages = 0;
 438                 agp_free_page_array(new);
 439                 return new;
 440         }
 441         if (type == AGP_PHYS_MEMORY)
 442                 return alloc_agpphysmem_i8xx(pg_count, type);
 443         return NULL;
 444 }
 445
 446 static void intel_i810_free_by_type(struct agp_memory *curr)
 447 {
 448         agp_free_key(curr->key);
 449         if (curr->type == AGP_PHYS_MEMORY) {
 450                 if (curr->page_count == 4)
 451                         i8xx_destroy_pages(curr->pages[0]);
 452                 else {
 453                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 454                                                              AGP_PAGE_DESTROY_UNMAP);
 455                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 456                                                              AGP_PAGE_DESTROY_FREE);
 457                 }
 458                 agp_free_page_array(curr);
 459         }
 460         kfree(curr);
 461 }
 462
 463 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 464                                             struct page *page, int type)
 465 {
 466         unsigned long addr = phys_to_gart(page_to_phys(page));
 467         /* Type checking must be done elsewhere */
 468         return addr | bridge->driver->masks[type].mask;
 469 }
 470
 471 static struct aper_size_info_fixed intel_i830_sizes[] =
 472 {
 473         {128, 32768, 5},
 474         /* The 64M mode still requires a 128k gatt */
 475         {64, 16384, 5},
 476         {256, 65536, 6},
 477         {512, 131072, 7},
 478 };
 479
 480 static void intel_i830_init_gtt_entries(void)
 481 {
 482         u16 gmch_ctrl;
 483         int gtt_entries;
 484         u8 rdct;
 485         int local = 0;
 486         static const int ddt[4] = { 0, 16, 32, 64 };
 487         int size; /* reserved space (in kb) at the top of stolen memory */
 488
 489         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 490
 491         if (IS_I965) {
 492                 u32 pgetbl_ctl;
 493                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 494
 495                 /* The 965 has a field telling us the size of the GTT,
 496                  * which may be larger than what is necessary to map the
 497                  * aperture.
 498                  */
 499                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 500                 case I965_PGETBL_SIZE_128KB:
 501                         size = 128;
 502                         break;
 503                 case I965_PGETBL_SIZE_256KB:
 504                         size = 256;
 505                         break;
 506                 case I965_PGETBL_SIZE_512KB:
 507                         size = 512;
 508                         break;
 509                 case I965_PGETBL_SIZE_1MB:
 510                         size = 1024;
 511                         break;
 512                 case I965_PGETBL_SIZE_2MB:
 513                         size = 2048;
 514                         break;
 515                 case I965_PGETBL_SIZE_1_5MB:
 516                         size = 1024 + 512;
 517                         break;
 518                 default:
 519                         dev_info(&intel_private.pcidev->dev,
 520                                  "unknown page table size, assuming 512KB\n");
 521                         size = 512;
 522                 }
 523                 size += 4; /* add in BIOS popup space */
 524         } else if (IS_G33 && !IS_IGD) {
 525         /* G33's GTT size defined in gmch_ctrl */
 526                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 527                 case G33_PGETBL_SIZE_1M:
 528                         size = 1024;
 529                         break;
 530                 case G33_PGETBL_SIZE_2M:
 531                         size = 2048;
 532                         break;
 533                 default:
 534                         dev_info(&agp_bridge->dev->dev,
 535                                  "unknown page table size 0x%x, assuming 512KB\n",
 536                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 537                         size = 512;
 538                 }
 539                 size += 4;
 540         } else if (IS_G4X || IS_IGD) {
 541                 /* On 4 series hardware, GTT stolen is separate from graphics
 542                  * stolen, ignore it in stolen gtt entries counting.  However,
 543                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 544                  */
 545                 size = 4;
 546         } else {
 547                 /* On previous hardware, the GTT size was just what was
 548                  * required to map the aperture.
 549                  */
 550                 size = agp_bridge->driver->fetch_size() + 4;
 551         }
 552
 553         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 554             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 555                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 556                 case I830_GMCH_GMS_STOLEN_512:
 557                         gtt_entries = KB(512) - KB(size);
 558                         break;
 559                 case I830_GMCH_GMS_STOLEN_1024:
 560                         gtt_entries = MB(1) - KB(size);
 561                         break;
 562                 case I830_GMCH_GMS_STOLEN_8192:
 563                         gtt_entries = MB(8) - KB(size);
 564                         break;
 565                 case I830_GMCH_GMS_LOCAL:
 566                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 567                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 568                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 569                         local = 1;
 570                         break;
 571                 default:
 572                         gtt_entries = 0;
 573                         break;
 574                 }
 575         } else {
 576                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 577                 case I855_GMCH_GMS_STOLEN_1M:
 578                         gtt_entries = MB(1) - KB(size);
 579                         break;
 580                 case I855_GMCH_GMS_STOLEN_4M:
 581                         gtt_entries = MB(4) - KB(size);
 582                         break;
 583                 case I855_GMCH_GMS_STOLEN_8M:
 584                         gtt_entries = MB(8) - KB(size);
 585                         break;
 586                 case I855_GMCH_GMS_STOLEN_16M:
 587                         gtt_entries = MB(16) - KB(size);
 588                         break;
 589                 case I855_GMCH_GMS_STOLEN_32M:
 590                         gtt_entries = MB(32) - KB(size);
 591                         break;
 592                 case I915_GMCH_GMS_STOLEN_48M:
 593                         /* Check it's really I915G */
 594                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 595                                 gtt_entries = MB(48) - KB(size);
 596                         else
 597                                 gtt_entries = 0;
 598                         break;
 599                 case I915_GMCH_GMS_STOLEN_64M:
 600                         /* Check it's really I915G */
 601                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 602                                 gtt_entries = MB(64) - KB(size);
 603                         else
 604                                 gtt_entries = 0;
 605                         break;
 606                 case G33_GMCH_GMS_STOLEN_128M:
 607                         if (IS_G33 || IS_I965 || IS_G4X)
 608                                 gtt_entries = MB(128) - KB(size);
 609                         else
 610                                 gtt_entries = 0;
 611                         break;
 612                 case G33_GMCH_GMS_STOLEN_256M:
 613                         if (IS_G33 || IS_I965 || IS_G4X)
 614                                 gtt_entries = MB(256) - KB(size);
 615                         else
 616                                 gtt_entries = 0;
 617                         break;
 618                 case INTEL_GMCH_GMS_STOLEN_96M:
 619                         if (IS_I965 || IS_G4X)
 620                                 gtt_entries = MB(96) - KB(size);
 621                         else
 622                                 gtt_entries = 0;
 623                         break;
 624                 case INTEL_GMCH_GMS_STOLEN_160M:
 625                         if (IS_I965 || IS_G4X)
 626                                 gtt_entries = MB(160) - KB(size);
 627                         else
 628                                 gtt_entries = 0;
 629                         break;
 630                 case INTEL_GMCH_GMS_STOLEN_224M:
 631                         if (IS_I965 || IS_G4X)
 632                                 gtt_entries = MB(224) - KB(size);
 633                         else
 634                                 gtt_entries = 0;
 635                         break;
 636                 case INTEL_GMCH_GMS_STOLEN_352M:
 637                         if (IS_I965 || IS_G4X)
 638                                 gtt_entries = MB(352) - KB(size);
 639                         else
 640                                 gtt_entries = 0;
 641                         break;
 642                 default:
 643                         gtt_entries = 0;
 644                         break;
 645                 }
 646         }
 647         if (gtt_entries > 0) {
 648                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 649                        gtt_entries / KB(1), local ? "local" : "stolen");
 650                 gtt_entries /= KB(4);
 651         } else {
 652                 dev_info(&agp_bridge->dev->dev,
 653                        "no pre-allocated video memory detected\n");
 654                 gtt_entries = 0;
 655         }
 656
 657         intel_private.gtt_entries = gtt_entries;
 658 }
 659
 660 static void intel_i830_fini_flush(void)
 661 {
 662         kunmap(intel_private.i8xx_page);
 663         intel_private.i8xx_flush_page = NULL;
 664         unmap_page_from_agp(intel_private.i8xx_page);
 665
 666         __free_page(intel_private.i8xx_page);
 667         intel_private.i8xx_page = NULL;
 668 }
 669
 670 static void intel_i830_setup_flush(void)
 671 {
 672         /* return if we've already set the flush mechanism up */
 673         if (intel_private.i8xx_page)
 674                 return;
 675
 676         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 677         if (!intel_private.i8xx_page)
 678                 return;
 679
 680         /* make page uncached */
 681         map_page_into_agp(intel_private.i8xx_page);
 682
 683         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 684         if (!intel_private.i8xx_flush_page)
 685                 intel_i830_fini_flush();
 686 }
 687
 688 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 689 {
 690         unsigned int *pg = intel_private.i8xx_flush_page;
 691         int i;
 692
 693         for (i = 0; i < 256; i += 2)
 694                 *(pg + i) = i;
 695
 696         wmb();
 697 }
 698
 699 /* The intel i830 automatically initializes the agp aperture during POST.
 700  * Use the memory already set aside for in the GTT.
 701  */
 702 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 703 {
 704         int page_order;
 705         struct aper_size_info_fixed *size;
 706         int num_entries;
 707         u32 temp;
 708
 709         size = agp_bridge->current_size;
 710         page_order = size->page_order;
 711         num_entries = size->num_entries;
 712         agp_bridge->gatt_table_real = NULL;
 713
 714         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 715         temp &= 0xfff80000;
 716
 717         intel_private.registers = ioremap(temp, 128 * 4096);
 718         if (!intel_private.registers)
 719                 return -ENOMEM;
 720
 721         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 722         global_cache_flush();   /* FIXME: ?? */
 723
 724         /* we have to call this as early as possible after the MMIO base address is known */
 725         intel_i830_init_gtt_entries();
 726
 727         agp_bridge->gatt_table = NULL;
 728
 729         agp_bridge->gatt_bus_addr = temp;
 730
 731         return 0;
 732 }
 733
 734 /* Return the gatt table to a sane state. Use the top of stolen
 735  * memory for the GTT.
 736  */
 737 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 738 {
 739         return 0;
 740 }
 741
 742 static int intel_i830_fetch_size(void)
 743 {
 744         u16 gmch_ctrl;
 745         struct aper_size_info_fixed *values;
 746
 747         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 748
 749         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 750             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 751                 /* 855GM/852GM/865G has 128MB aperture size */
 752                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 753                 agp_bridge->aperture_size_idx = 0;
 754                 return values[0].size;
 755         }
 756
 757         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 758
 759         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 760                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 761                 agp_bridge->aperture_size_idx = 0;
 762                 return values[0].size;
 763         } else {
 764                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 765                 agp_bridge->aperture_size_idx = 1;
 766                 return values[1].size;
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int intel_i830_configure(void)
 773 {
 774         struct aper_size_info_fixed *current_size;
 775         u32 temp;
 776         u16 gmch_ctrl;
 777         int i;
 778
 779         current_size = A_SIZE_FIX(agp_bridge->current_size);
 780
 781         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 782         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 783
 784         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 785         gmch_ctrl |= I830_GMCH_ENABLED;
 786         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 787
 788         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 789         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 790
 791         if (agp_bridge->driver->needs_scratch_page) {
 792                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 793                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 794                 }
 795                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 796         }
 797
 798         global_cache_flush();
 799
 800         intel_i830_setup_flush();
 801         return 0;
 802 }
 803
 804 static void intel_i830_cleanup(void)
 805 {
 806         iounmap(intel_private.registers);
 807 }
 808
 809 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 810                                      int type)
 811 {
 812         int i, j, num_entries;
 813         void *temp;
 814         int ret = -EINVAL;
 815         int mask_type;
 816
 817         if (mem->page_count == 0)
 818                 goto out;
 819
 820         temp = agp_bridge->current_size;
 821         num_entries = A_SIZE_FIX(temp)->num_entries;
 822
 823         if (pg_start < intel_private.gtt_entries) {
 824                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 825                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 826                            pg_start, intel_private.gtt_entries);
 827
 828                 dev_info(&intel_private.pcidev->dev,
 829                          "trying to insert into local/stolen memory\n");
 830                 goto out_err;
 831         }
 832
 833         if ((pg_start + mem->page_count) > num_entries)
 834                 goto out_err;
 835
 836         /* The i830 can't check the GTT for entries since its read only,
 837          * depend on the caller to make the correct offset decisions.
 838          */
 839
 840         if (type != mem->type)
 841                 goto out_err;
 842
 843         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 844
 845         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 846             mask_type != INTEL_AGP_CACHED_MEMORY)
 847                 goto out_err;
 848
 849         if (!mem->is_flushed)
 850                 global_cache_flush();
 851
 852         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 853                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 854                                                        mem->pages[i], mask_type),
 855                        intel_private.registers+I810_PTE_BASE+(j*4));
 856         }
 857         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 858         agp_bridge->driver->tlb_flush(mem);
 859
 860 out:
 861         ret = 0;
 862 out_err:
 863         mem->is_flushed = true;
 864         return ret;
 865 }
 866
 867 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 868                                      int type)
 869 {
 870         int i;
 871
 872         if (mem->page_count == 0)
 873                 return 0;
 874
 875         if (pg_start < intel_private.gtt_entries) {
 876                 dev_info(&intel_private.pcidev->dev,
 877                          "trying to disable local/stolen memory\n");
 878                 return -EINVAL;
 879         }
 880
 881         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 882                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 883         }
 884         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 885
 886         agp_bridge->driver->tlb_flush(mem);
 887         return 0;
 888 }
 889
 890 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
 891 {
 892         if (type == AGP_PHYS_MEMORY)
 893                 return alloc_agpphysmem_i8xx(pg_count, type);
 894         /* always return NULL for other allocation types for now */
 895         return NULL;
 896 }
 897
 898 static int intel_alloc_chipset_flush_resource(void)
 899 {
 900         int ret;
 901         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
 902                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
 903                                      pcibios_align_resource, agp_bridge->dev);
 904
 905         return ret;
 906 }
 907
 908 static void intel_i915_setup_chipset_flush(void)
 909 {
 910         int ret;
 911         u32 temp;
 912
 913         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
 914         if (!(temp & 0x1)) {
 915                 intel_alloc_chipset_flush_resource();
 916                 intel_private.resource_valid = 1;
 917                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 918         } else {
 919                 temp &= ~1;
 920
 921                 intel_private.resource_valid = 1;
 922                 intel_private.ifp_resource.start = temp;
 923                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
 924                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 925                 /* some BIOSes reserve this area in a pnp some don't */
 926                 if (ret)
 927                         intel_private.resource_valid = 0;
 928         }
 929 }
 930
 931 static void intel_i965_g33_setup_chipset_flush(void)
 932 {
 933         u32 temp_hi, temp_lo;
 934         int ret;
 935
 936         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
 937         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
 938
 939         if (!(temp_lo & 0x1)) {
 940
 941                 intel_alloc_chipset_flush_resource();
 942
 943                 intel_private.resource_valid = 1;
 944                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
 945                         upper_32_bits(intel_private.ifp_resource.start));
 946                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
 947         } else {
 948                 u64 l64;
 949
 950                 temp_lo &= ~0x1;
 951                 l64 = ((u64)temp_hi << 32) | temp_lo;
 952
 953                 intel_private.resource_valid = 1;
 954                 intel_private.ifp_resource.start = l64;
 955                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
 956                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
 957                 /* some BIOSes reserve this area in a pnp some don't */
 958                 if (ret)
 959                         intel_private.resource_valid = 0;
 960         }
 961 }
 962
 963 static void intel_i9xx_setup_flush(void)
 964 {
 965         /* return if already configured */
 966         if (intel_private.ifp_resource.start)
 967                 return;
 968
 969         /* setup a resource for this object */
 970         intel_private.ifp_resource.name = "Intel Flush Page";
 971         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 972
 973         /* Setup chipset flush for 915 */
 974         if (IS_I965 || IS_G33 || IS_G4X) {
 975                 intel_i965_g33_setup_chipset_flush();
 976         } else {
 977                 intel_i915_setup_chipset_flush();
 978         }
 979
 980         if (intel_private.ifp_resource.start) {
 981                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
 982                 if (!intel_private.i9xx_flush_page)
 983                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
 984         }
 985 }
 986
 987 static int intel_i915_configure(void)
 988 {
 989         struct aper_size_info_fixed *current_size;
 990         u32 temp;
 991         u16 gmch_ctrl;
 992         int i;
 993
 994         current_size = A_SIZE_FIX(agp_bridge->current_size);
 995
 996         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 997
 998         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 999
1000         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1001         gmch_ctrl |= I830_GMCH_ENABLED;
1002         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1003
1004         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1005         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1006
1007         if (agp_bridge->driver->needs_scratch_page) {
1008                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1009                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1010                 }
1011                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1012         }
1013
1014         global_cache_flush();
1015
1016         intel_i9xx_setup_flush();
1017
1018         return 0;
1019 }
1020
1021 static void intel_i915_cleanup(void)
1022 {
1023         if (intel_private.i9xx_flush_page)
1024                 iounmap(intel_private.i9xx_flush_page);
1025         if (intel_private.resource_valid)
1026                 release_resource(&intel_private.ifp_resource);
1027         intel_private.ifp_resource.start = 0;
1028         intel_private.resource_valid = 0;
1029         iounmap(intel_private.gtt);
1030         iounmap(intel_private.registers);
1031 }
1032
1033 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1034 {
1035         if (intel_private.i9xx_flush_page)
1036                 writel(1, intel_private.i9xx_flush_page);
1037 }
1038
1039 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1040                                      int type)
1041 {
1042         int i, j, num_entries;
1043         void *temp;
1044         int ret = -EINVAL;
1045         int mask_type;
1046
1047         if (mem->page_count == 0)
1048                 goto out;
1049
1050         temp = agp_bridge->current_size;
1051         num_entries = A_SIZE_FIX(temp)->num_entries;
1052
1053         if (pg_start < intel_private.gtt_entries) {
1054                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1055                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1056                            pg_start, intel_private.gtt_entries);
1057
1058                 dev_info(&intel_private.pcidev->dev,
1059                          "trying to insert into local/stolen memory\n");
1060                 goto out_err;
1061         }
1062
1063         if ((pg_start + mem->page_count) > num_entries)
1064                 goto out_err;
1065
1066         /* The i915 can't check the GTT for entries since its read only,
1067          * depend on the caller to make the correct offset decisions.
1068          */
1069
1070         if (type != mem->type)
1071                 goto out_err;
1072
1073         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1074
1075         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1076             mask_type != INTEL_AGP_CACHED_MEMORY)
1077                 goto out_err;
1078
1079         if (!mem->is_flushed)
1080                 global_cache_flush();
1081
1082         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1083                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1084                                                        mem->pages[i], mask_type), intel_private.gtt+j);
1085         }
1086
1087         readl(intel_private.gtt+j-1);
1088         agp_bridge->driver->tlb_flush(mem);
1089
1090  out:
1091         ret = 0;
1092  out_err:
1093         mem->is_flushed = true;
1094         return ret;
1095 }
1096
1097 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1098                                      int type)
1099 {
1100         int i;
1101
1102         if (mem->page_count == 0)
1103                 return 0;
1104
1105         if (pg_start < intel_private.gtt_entries) {
1106                 dev_info(&intel_private.pcidev->dev,
1107                          "trying to disable local/stolen memory\n");
1108                 return -EINVAL;
1109         }
1110
1111         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1112                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1113
1114         readl(intel_private.gtt+i-1);
1115
1116         agp_bridge->driver->tlb_flush(mem);
1117         return 0;
1118 }
1119
1120 /* Return the aperture size by just checking the resource length.  The effect
1121  * described in the spec of the MSAC registers is just changing of the
1122  * resource size.
1123  */
1124 static int intel_i9xx_fetch_size(void)
1125 {
1126         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1127         int aper_size; /* size in megabytes */
1128         int i;
1129
1130         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1131
1132         for (i = 0; i < num_sizes; i++) {
1133                 if (aper_size == intel_i830_sizes[i].size) {
1134                         agp_bridge->current_size = intel_i830_sizes + i;
1135                         agp_bridge->previous_size = agp_bridge->current_size;
1136                         return aper_size;
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 /* The intel i915 automatically initializes the agp aperture during POST.
1144  * Use the memory already set aside for in the GTT.
1145  */
1146 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1147 {
1148         int page_order;
1149         struct aper_size_info_fixed *size;
1150         int num_entries;
1151         u32 temp, temp2;
1152         int gtt_map_size = 256 * 1024;
1153
1154         size = agp_bridge->current_size;
1155         page_order = size->page_order;
1156         num_entries = size->num_entries;
1157         agp_bridge->gatt_table_real = NULL;
1158
1159         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1160         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1161
1162         if (IS_G33)
1163             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1164         intel_private.gtt = ioremap(temp2, gtt_map_size);
1165         if (!intel_private.gtt)
1166                 return -ENOMEM;
1167
1168         temp &= 0xfff80000;
1169
1170         intel_private.registers = ioremap(temp, 128 * 4096);
1171         if (!intel_private.registers) {
1172                 iounmap(intel_private.gtt);
1173                 return -ENOMEM;
1174         }
1175
1176         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1177         global_cache_flush();   /* FIXME: ? */
1178
1179         /* we have to call this as early as possible after the MMIO base address is known */
1180         intel_i830_init_gtt_entries();
1181
1182         agp_bridge->gatt_table = NULL;
1183
1184         agp_bridge->gatt_bus_addr = temp;
1185
1186         return 0;
1187 }
1188
1189 /*
1190  * The i965 supports 36-bit physical addresses, but to keep
1191  * the format of the GTT the same, the bits that don't fit
1192  * in a 32-bit word are shifted down to bits 4..7.
1193  *
1194  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1195  * is always zero on 32-bit architectures, so no need to make
1196  * this conditional.
1197  */
1198 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1199                                             struct page *page, int type)
1200 {
1201         dma_addr_t addr = phys_to_gart(page_to_phys(page));
1202         /* Shift high bits down */
1203         addr |= (addr >> 28) & 0xf0;
1204
1205         /* Type checking must be done elsewhere */
1206         return addr | bridge->driver->masks[type].mask;
1207 }
1208
1209 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1210 {
1211         switch (agp_bridge->dev->device) {
1212         case PCI_DEVICE_ID_INTEL_GM45_HB:
1213         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1214         case PCI_DEVICE_ID_INTEL_Q45_HB:
1215         case PCI_DEVICE_ID_INTEL_G45_HB:
1216         case PCI_DEVICE_ID_INTEL_G41_HB:
1217         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1218         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1219                 *gtt_offset = *gtt_size = MB(2);
1220                 break;
1221         default:
1222                 *gtt_offset = *gtt_size = KB(512);
1223         }
1224 }
1225
1226 /* The intel i965 automatically initializes the agp aperture during POST.
1227  * Use the memory already set aside for in the GTT.
1228  */
1229 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1230 {
1231         int page_order;
1232         struct aper_size_info_fixed *size;
1233         int num_entries;
1234         u32 temp;
1235         int gtt_offset, gtt_size;
1236
1237         size = agp_bridge->current_size;
1238         page_order = size->page_order;
1239         num_entries = size->num_entries;
1240         agp_bridge->gatt_table_real = NULL;
1241
1242         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1243
1244         temp &= 0xfff00000;
1245
1246         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1247
1248         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1249
1250         if (!intel_private.gtt)
1251                 return -ENOMEM;
1252
1253         intel_private.registers = ioremap(temp, 128 * 4096);
1254         if (!intel_private.registers) {
1255                 iounmap(intel_private.gtt);
1256                 return -ENOMEM;
1257         }
1258
1259         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1260         global_cache_flush();   /* FIXME: ? */
1261
1262         /* we have to call this as early as possible after the MMIO base address is known */
1263         intel_i830_init_gtt_entries();
1264
1265         agp_bridge->gatt_table = NULL;
1266
1267         agp_bridge->gatt_bus_addr = temp;
1268
1269         return 0;
1270 }
1271
1272
1273 static int intel_fetch_size(void)
1274 {
1275         int i;
1276         u16 temp;
1277         struct aper_size_info_16 *values;
1278
1279         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1280         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1281
1282         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1283                 if (temp == values[i].size_value) {
1284                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1285                         agp_bridge->aperture_size_idx = i;
1286                         return values[i].size;
1287                 }
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int __intel_8xx_fetch_size(u8 temp)
1294 {
1295         int i;
1296         struct aper_size_info_8 *values;
1297
1298         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1299
1300         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1301                 if (temp == values[i].size_value) {
1302                         agp_bridge->previous_size =
1303                                 agp_bridge->current_size = (void *) (values + i);
1304                         agp_bridge->aperture_size_idx = i;
1305                         return values[i].size;
1306                 }
1307         }
1308         return 0;
1309 }
1310
1311 static int intel_8xx_fetch_size(void)
1312 {
1313         u8 temp;
1314
1315         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1316         return __intel_8xx_fetch_size(temp);
1317 }
1318
1319 static int intel_815_fetch_size(void)
1320 {
1321         u8 temp;
1322
1323         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1324          * one non-reserved bit, so mask the others out ... */
1325         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1326         temp &= (1 << 3);
1327
1328         return __intel_8xx_fetch_size(temp);
1329 }
1330
1331 static void intel_tlbflush(struct agp_memory *mem)
1332 {
1333         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1334         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1335 }
1336
1337
1338 static void intel_8xx_tlbflush(struct agp_memory *mem)
1339 {
1340         u32 temp;
1341         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1342         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1343         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1344         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1345 }
1346
1347
1348 static void intel_cleanup(void)
1349 {
1350         u16 temp;
1351         struct aper_size_info_16 *previous_size;
1352
1353         previous_size = A_SIZE_16(agp_bridge->previous_size);
1354         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1355         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1356         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1357 }
1358
1359
1360 static void intel_8xx_cleanup(void)
1361 {
1362         u16 temp;
1363         struct aper_size_info_8 *previous_size;
1364
1365         previous_size = A_SIZE_8(agp_bridge->previous_size);
1366         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1367         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1368         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1369 }
1370
1371
1372 static int intel_configure(void)
1373 {
1374         u32 temp;
1375         u16 temp2;
1376         struct aper_size_info_16 *current_size;
1377
1378         current_size = A_SIZE_16(agp_bridge->current_size);
1379
1380         /* aperture size */
1381         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1382
1383         /* address to map to */
1384         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1385         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1386
1387         /* attbase - aperture base */
1388         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1389
1390         /* agpctrl */
1391         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1392
1393         /* paccfg/nbxcfg */
1394         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1395         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1396                         (temp2 & ~(1 << 10)) | (1 << 9));
1397         /* clear any possible error conditions */
1398         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1399         return 0;
1400 }
1401
1402 static int intel_815_configure(void)
1403 {
1404         u32 temp, addr;
1405         u8 temp2;
1406         struct aper_size_info_8 *current_size;
1407
1408         /* attbase - aperture base */
1409         /* the Intel 815 chipset spec. says that bits 29-31 in the
1410         * ATTBASE register are reserved -> try not to write them */
1411         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1412                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1413                 return -EINVAL;
1414         }
1415
1416         current_size = A_SIZE_8(agp_bridge->current_size);
1417
1418         /* aperture size */
1419         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1420                         current_size->size_value);
1421
1422         /* address to map to */
1423         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1424         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1425
1426         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1427         addr &= INTEL_815_ATTBASE_MASK;
1428         addr |= agp_bridge->gatt_bus_addr;
1429         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1430
1431         /* agpctrl */
1432         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1433
1434         /* apcont */
1435         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1436         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1437
1438         /* clear any possible error conditions */
1439         /* Oddness : this chipset seems to have no ERRSTS register ! */
1440         return 0;
1441 }
1442
1443 static void intel_820_tlbflush(struct agp_memory *mem)
1444 {
1445         return;
1446 }
1447
1448 static void intel_820_cleanup(void)
1449 {
1450         u8 temp;
1451         struct aper_size_info_8 *previous_size;
1452
1453         previous_size = A_SIZE_8(agp_bridge->previous_size);
1454         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1455         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1456                         temp & ~(1 << 1));
1457         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1458                         previous_size->size_value);
1459 }
1460
1461
1462 static int intel_820_configure(void)
1463 {
1464         u32 temp;
1465         u8 temp2;
1466         struct aper_size_info_8 *current_size;
1467
1468         current_size = A_SIZE_8(agp_bridge->current_size);
1469
1470         /* aperture size */
1471         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1472
1473         /* address to map to */
1474         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1475         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1476
1477         /* attbase - aperture base */
1478         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1479
1480         /* agpctrl */
1481         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1482
1483         /* global enable aperture access */
1484         /* This flag is not accessed through MCHCFG register as in */
1485         /* i850 chipset. */
1486         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1487         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1488         /* clear any possible AGP-related error conditions */
1489         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1490         return 0;
1491 }
1492
1493 static int intel_840_configure(void)
1494 {
1495         u32 temp;
1496         u16 temp2;
1497         struct aper_size_info_8 *current_size;
1498
1499         current_size = A_SIZE_8(agp_bridge->current_size);
1500
1501         /* aperture size */
1502         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1503
1504         /* address to map to */
1505         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1506         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1507
1508         /* attbase - aperture base */
1509         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1510
1511         /* agpctrl */
1512         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1513
1514         /* mcgcfg */
1515         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1516         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1517         /* clear any possible error conditions */
1518         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1519         return 0;
1520 }
1521
1522 static int intel_845_configure(void)
1523 {
1524         u32 temp;
1525         u8 temp2;
1526         struct aper_size_info_8 *current_size;
1527
1528         current_size = A_SIZE_8(agp_bridge->current_size);
1529
1530         /* aperture size */
1531         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1532
1533         if (agp_bridge->apbase_config != 0) {
1534                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1535                                        agp_bridge->apbase_config);
1536         } else {
1537                 /* address to map to */
1538                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1539                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1540                 agp_bridge->apbase_config = temp;
1541         }
1542
1543         /* attbase - aperture base */
1544         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1545
1546         /* agpctrl */
1547         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1548
1549         /* agpm */
1550         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1551         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1552         /* clear any possible error conditions */
1553         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1554
1555         intel_i830_setup_flush();
1556         return 0;
1557 }
1558
1559 static int intel_850_configure(void)
1560 {
1561         u32 temp;
1562         u16 temp2;
1563         struct aper_size_info_8 *current_size;
1564
1565         current_size = A_SIZE_8(agp_bridge->current_size);
1566
1567         /* aperture size */
1568         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1569
1570         /* address to map to */
1571         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1572         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1573
1574         /* attbase - aperture base */
1575         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1576
1577         /* agpctrl */
1578         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1579
1580         /* mcgcfg */
1581         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1582         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1583         /* clear any possible AGP-related error conditions */
1584         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1585         return 0;
1586 }
1587
1588 static int intel_860_configure(void)
1589 {
1590         u32 temp;
1591         u16 temp2;
1592         struct aper_size_info_8 *current_size;
1593
1594         current_size = A_SIZE_8(agp_bridge->current_size);
1595
1596         /* aperture size */
1597         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1598
1599         /* address to map to */
1600         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1601         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1602
1603         /* attbase - aperture base */
1604         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1605
1606         /* agpctrl */
1607         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1608
1609         /* mcgcfg */
1610         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1611         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1612         /* clear any possible AGP-related error conditions */
1613         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1614         return 0;
1615 }
1616
1617 static int intel_830mp_configure(void)
1618 {
1619         u32 temp;
1620         u16 temp2;
1621         struct aper_size_info_8 *current_size;
1622
1623         current_size = A_SIZE_8(agp_bridge->current_size);
1624
1625         /* aperture size */
1626         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1627
1628         /* address to map to */
1629         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1630         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1631
1632         /* attbase - aperture base */
1633         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1634
1635         /* agpctrl */
1636         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1637
1638         /* gmch */
1639         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1640         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1641         /* clear any possible AGP-related error conditions */
1642         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1643         return 0;
1644 }
1645
1646 static int intel_7505_configure(void)
1647 {
1648         u32 temp;
1649         u16 temp2;
1650         struct aper_size_info_8 *current_size;
1651
1652         current_size = A_SIZE_8(agp_bridge->current_size);
1653
1654         /* aperture size */
1655         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1656
1657         /* address to map to */
1658         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1659         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1660
1661         /* attbase - aperture base */
1662         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1663
1664         /* agpctrl */
1665         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1666
1667         /* mchcfg */
1668         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1669         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1670
1671         return 0;
1672 }
1673
1674 /* Setup function */
1675 static const struct gatt_mask intel_generic_masks[] =
1676 {
1677         {.mask = 0x00000017, .type = 0}
1678 };
1679
1680 static const struct aper_size_info_8 intel_815_sizes[2] =
1681 {
1682         {64, 16384, 4, 0},
1683         {32, 8192, 3, 8},
1684 };
1685
1686 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1687 {
1688         {256, 65536, 6, 0},
1689         {128, 32768, 5, 32},
1690         {64, 16384, 4, 48},
1691         {32, 8192, 3, 56},
1692         {16, 4096, 2, 60},
1693         {8, 2048, 1, 62},
1694         {4, 1024, 0, 63}
1695 };
1696
1697 static const struct aper_size_info_16 intel_generic_sizes[7] =
1698 {
1699         {256, 65536, 6, 0},
1700         {128, 32768, 5, 32},
1701         {64, 16384, 4, 48},
1702         {32, 8192, 3, 56},
1703         {16, 4096, 2, 60},
1704         {8, 2048, 1, 62},
1705         {4, 1024, 0, 63}
1706 };
1707
1708 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1709 {
1710         {256, 65536, 6, 0},
1711         {128, 32768, 5, 32},
1712         {64, 16384, 4, 48},
1713         {32, 8192, 3, 56}
1714 };
1715
1716 static const struct agp_bridge_driver intel_generic_driver = {
1717         .owner                  = THIS_MODULE,
1718         .aperture_sizes         = intel_generic_sizes,
1719         .size_type              = U16_APER_SIZE,
1720         .num_aperture_sizes     = 7,
1721         .configure              = intel_configure,
1722         .fetch_size             = intel_fetch_size,
1723         .cleanup                = intel_cleanup,
1724         .tlb_flush              = intel_tlbflush,
1725         .mask_memory            = agp_generic_mask_memory,
1726         .masks                  = intel_generic_masks,
1727         .agp_enable             = agp_generic_enable,
1728         .cache_flush            = global_cache_flush,
1729         .create_gatt_table      = agp_generic_create_gatt_table,
1730         .free_gatt_table        = agp_generic_free_gatt_table,
1731         .insert_memory          = agp_generic_insert_memory,
1732         .remove_memory          = agp_generic_remove_memory,
1733         .alloc_by_type          = agp_generic_alloc_by_type,
1734         .free_by_type           = agp_generic_free_by_type,
1735         .agp_alloc_page         = agp_generic_alloc_page,
1736         .agp_alloc_pages        = agp_generic_alloc_pages,
1737         .agp_destroy_page       = agp_generic_destroy_page,
1738         .agp_destroy_pages      = agp_generic_destroy_pages,
1739         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1740 };
1741
1742 static const struct agp_bridge_driver intel_810_driver = {
1743         .owner                  = THIS_MODULE,
1744         .aperture_sizes         = intel_i810_sizes,
1745         .size_type              = FIXED_APER_SIZE,
1746         .num_aperture_sizes     = 2,
1747         .needs_scratch_page     = true,
1748         .configure              = intel_i810_configure,
1749         .fetch_size             = intel_i810_fetch_size,
1750         .cleanup                = intel_i810_cleanup,
1751         .tlb_flush              = intel_i810_tlbflush,
1752         .mask_memory            = intel_i810_mask_memory,
1753         .masks                  = intel_i810_masks,
1754         .agp_enable             = intel_i810_agp_enable,
1755         .cache_flush            = global_cache_flush,
1756         .create_gatt_table      = agp_generic_create_gatt_table,
1757         .free_gatt_table        = agp_generic_free_gatt_table,
1758         .insert_memory          = intel_i810_insert_entries,
1759         .remove_memory          = intel_i810_remove_entries,
1760         .alloc_by_type          = intel_i810_alloc_by_type,
1761         .free_by_type           = intel_i810_free_by_type,
1762         .agp_alloc_page         = agp_generic_alloc_page,
1763         .agp_alloc_pages        = agp_generic_alloc_pages,
1764         .agp_destroy_page       = agp_generic_destroy_page,
1765         .agp_destroy_pages      = agp_generic_destroy_pages,
1766         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1767 };
1768
1769 static const struct agp_bridge_driver intel_815_driver = {
1770         .owner                  = THIS_MODULE,
1771         .aperture_sizes         = intel_815_sizes,
1772         .size_type              = U8_APER_SIZE,
1773         .num_aperture_sizes     = 2,
1774         .configure              = intel_815_configure,
1775         .fetch_size             = intel_815_fetch_size,
1776         .cleanup                = intel_8xx_cleanup,
1777         .tlb_flush              = intel_8xx_tlbflush,
1778         .mask_memory            = agp_generic_mask_memory,
1779         .masks                  = intel_generic_masks,
1780         .agp_enable             = agp_generic_enable,
1781         .cache_flush            = global_cache_flush,
1782         .create_gatt_table      = agp_generic_create_gatt_table,
1783         .free_gatt_table        = agp_generic_free_gatt_table,
1784         .insert_memory          = agp_generic_insert_memory,
1785         .remove_memory          = agp_generic_remove_memory,
1786         .alloc_by_type          = agp_generic_alloc_by_type,
1787         .free_by_type           = agp_generic_free_by_type,
1788         .agp_alloc_page         = agp_generic_alloc_page,
1789         .agp_alloc_pages        = agp_generic_alloc_pages,
1790         .agp_destroy_page       = agp_generic_destroy_page,
1791         .agp_destroy_pages      = agp_generic_destroy_pages,
1792         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1793 };
1794
1795 static const struct agp_bridge_driver intel_830_driver = {
1796         .owner                  = THIS_MODULE,
1797         .aperture_sizes         = intel_i830_sizes,
1798         .size_type              = FIXED_APER_SIZE,
1799         .num_aperture_sizes     = 4,
1800         .needs_scratch_page     = true,
1801         .configure              = intel_i830_configure,
1802         .fetch_size             = intel_i830_fetch_size,
1803         .cleanup                = intel_i830_cleanup,
1804         .tlb_flush              = intel_i810_tlbflush,
1805         .mask_memory            = intel_i810_mask_memory,
1806         .masks                  = intel_i810_masks,
1807         .agp_enable             = intel_i810_agp_enable,
1808         .cache_flush            = global_cache_flush,
1809         .create_gatt_table      = intel_i830_create_gatt_table,
1810         .free_gatt_table        = intel_i830_free_gatt_table,
1811         .insert_memory          = intel_i830_insert_entries,
1812         .remove_memory          = intel_i830_remove_entries,
1813         .alloc_by_type          = intel_i830_alloc_by_type,
1814         .free_by_type           = intel_i810_free_by_type,
1815         .agp_alloc_page         = agp_generic_alloc_page,
1816         .agp_alloc_pages        = agp_generic_alloc_pages,
1817         .agp_destroy_page       = agp_generic_destroy_page,
1818         .agp_destroy_pages      = agp_generic_destroy_pages,
1819         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1820         .chipset_flush          = intel_i830_chipset_flush,
1821 };
1822
1823 static const struct agp_bridge_driver intel_820_driver = {
1824         .owner                  = THIS_MODULE,
1825         .aperture_sizes         = intel_8xx_sizes,
1826         .size_type              = U8_APER_SIZE,
1827         .num_aperture_sizes     = 7,
1828         .configure              = intel_820_configure,
1829         .fetch_size             = intel_8xx_fetch_size,
1830         .cleanup                = intel_820_cleanup,
1831         .tlb_flush              = intel_820_tlbflush,
1832         .mask_memory            = agp_generic_mask_memory,
1833         .masks                  = intel_generic_masks,
1834         .agp_enable             = agp_generic_enable,
1835         .cache_flush            = global_cache_flush,
1836         .create_gatt_table      = agp_generic_create_gatt_table,
1837         .free_gatt_table        = agp_generic_free_gatt_table,
1838         .insert_memory          = agp_generic_insert_memory,
1839         .remove_memory          = agp_generic_remove_memory,
1840         .alloc_by_type          = agp_generic_alloc_by_type,
1841         .free_by_type           = agp_generic_free_by_type,
1842         .agp_alloc_page         = agp_generic_alloc_page,
1843         .agp_alloc_pages        = agp_generic_alloc_pages,
1844         .agp_destroy_page       = agp_generic_destroy_page,
1845         .agp_destroy_pages      = agp_generic_destroy_pages,
1846         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1847 };
1848
1849 static const struct agp_bridge_driver intel_830mp_driver = {
1850         .owner                  = THIS_MODULE,
1851         .aperture_sizes         = intel_830mp_sizes,
1852         .size_type              = U8_APER_SIZE,
1853         .num_aperture_sizes     = 4,
1854         .configure              = intel_830mp_configure,
1855         .fetch_size             = intel_8xx_fetch_size,
1856         .cleanup                = intel_8xx_cleanup,
1857         .tlb_flush              = intel_8xx_tlbflush,
1858         .mask_memory            = agp_generic_mask_memory,
1859         .masks                  = intel_generic_masks,
1860         .agp_enable             = agp_generic_enable,
1861         .cache_flush            = global_cache_flush,
1862         .create_gatt_table      = agp_generic_create_gatt_table,
1863         .free_gatt_table        = agp_generic_free_gatt_table,
1864         .insert_memory          = agp_generic_insert_memory,
1865         .remove_memory          = agp_generic_remove_memory,
1866         .alloc_by_type          = agp_generic_alloc_by_type,
1867         .free_by_type           = agp_generic_free_by_type,
1868         .agp_alloc_page         = agp_generic_alloc_page,
1869         .agp_alloc_pages        = agp_generic_alloc_pages,
1870         .agp_destroy_page       = agp_generic_destroy_page,
1871         .agp_destroy_pages      = agp_generic_destroy_pages,
1872         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1873 };
1874
1875 static const struct agp_bridge_driver intel_840_driver = {
1876         .owner                  = THIS_MODULE,
1877         .aperture_sizes         = intel_8xx_sizes,
1878         .size_type              = U8_APER_SIZE,
1879         .num_aperture_sizes     = 7,
1880         .configure              = intel_840_configure,
1881         .fetch_size             = intel_8xx_fetch_size,
1882         .cleanup                = intel_8xx_cleanup,
1883         .tlb_flush              = intel_8xx_tlbflush,
1884         .mask_memory            = agp_generic_mask_memory,
1885         .masks                  = intel_generic_masks,
1886         .agp_enable             = agp_generic_enable,
1887         .cache_flush            = global_cache_flush,
1888         .create_gatt_table      = agp_generic_create_gatt_table,
1889         .free_gatt_table        = agp_generic_free_gatt_table,
1890         .insert_memory          = agp_generic_insert_memory,
1891         .remove_memory          = agp_generic_remove_memory,
1892         .alloc_by_type          = agp_generic_alloc_by_type,
1893         .free_by_type           = agp_generic_free_by_type,
1894         .agp_alloc_page         = agp_generic_alloc_page,
1895         .agp_alloc_pages        = agp_generic_alloc_pages,
1896         .agp_destroy_page       = agp_generic_destroy_page,
1897         .agp_destroy_pages      = agp_generic_destroy_pages,
1898         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1899 };
1900
1901 static const struct agp_bridge_driver intel_845_driver = {
1902         .owner                  = THIS_MODULE,
1903         .aperture_sizes         = intel_8xx_sizes,
1904         .size_type              = U8_APER_SIZE,
1905         .num_aperture_sizes     = 7,
1906         .configure              = intel_845_configure,
1907         .fetch_size             = intel_8xx_fetch_size,
1908         .cleanup                = intel_8xx_cleanup,
1909         .tlb_flush              = intel_8xx_tlbflush,
1910         .mask_memory            = agp_generic_mask_memory,
1911         .masks                  = intel_generic_masks,
1912         .agp_enable             = agp_generic_enable,
1913         .cache_flush            = global_cache_flush,
1914         .create_gatt_table      = agp_generic_create_gatt_table,
1915         .free_gatt_table        = agp_generic_free_gatt_table,
1916         .insert_memory          = agp_generic_insert_memory,
1917         .remove_memory          = agp_generic_remove_memory,
1918         .alloc_by_type          = agp_generic_alloc_by_type,
1919         .free_by_type           = agp_generic_free_by_type,
1920         .agp_alloc_page         = agp_generic_alloc_page,
1921         .agp_alloc_pages        = agp_generic_alloc_pages,
1922         .agp_destroy_page       = agp_generic_destroy_page,
1923         .agp_destroy_pages      = agp_generic_destroy_pages,
1924         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1925         .chipset_flush          = intel_i830_chipset_flush,
1926 };
1927
1928 static const struct agp_bridge_driver intel_850_driver = {
1929         .owner                  = THIS_MODULE,
1930         .aperture_sizes         = intel_8xx_sizes,
1931         .size_type              = U8_APER_SIZE,
1932         .num_aperture_sizes     = 7,
1933         .configure              = intel_850_configure,
1934         .fetch_size             = intel_8xx_fetch_size,
1935         .cleanup                = intel_8xx_cleanup,
1936         .tlb_flush              = intel_8xx_tlbflush,
1937         .mask_memory            = agp_generic_mask_memory,
1938         .masks                  = intel_generic_masks,
1939         .agp_enable             = agp_generic_enable,
1940         .cache_flush            = global_cache_flush,
1941         .create_gatt_table      = agp_generic_create_gatt_table,
1942         .free_gatt_table        = agp_generic_free_gatt_table,
1943         .insert_memory          = agp_generic_insert_memory,
1944         .remove_memory          = agp_generic_remove_memory,
1945         .alloc_by_type          = agp_generic_alloc_by_type,
1946         .free_by_type           = agp_generic_free_by_type,
1947         .agp_alloc_page         = agp_generic_alloc_page,
1948         .agp_alloc_pages        = agp_generic_alloc_pages,
1949         .agp_destroy_page       = agp_generic_destroy_page,
1950         .agp_destroy_pages      = agp_generic_destroy_pages,
1951         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1952 };
1953
1954 static const struct agp_bridge_driver intel_860_driver = {
1955         .owner                  = THIS_MODULE,
1956         .aperture_sizes         = intel_8xx_sizes,
1957         .size_type              = U8_APER_SIZE,
1958         .num_aperture_sizes     = 7,
1959         .configure              = intel_860_configure,
1960         .fetch_size             = intel_8xx_fetch_size,
1961         .cleanup                = intel_8xx_cleanup,
1962         .tlb_flush              = intel_8xx_tlbflush,
1963         .mask_memory            = agp_generic_mask_memory,
1964         .masks                  = intel_generic_masks,
1965         .agp_enable             = agp_generic_enable,
1966         .cache_flush            = global_cache_flush,
1967         .create_gatt_table      = agp_generic_create_gatt_table,
1968         .free_gatt_table        = agp_generic_free_gatt_table,
1969         .insert_memory          = agp_generic_insert_memory,
1970         .remove_memory          = agp_generic_remove_memory,
1971         .alloc_by_type          = agp_generic_alloc_by_type,
1972         .free_by_type           = agp_generic_free_by_type,
1973         .agp_alloc_page         = agp_generic_alloc_page,
1974         .agp_alloc_pages        = agp_generic_alloc_pages,
1975         .agp_destroy_page       = agp_generic_destroy_page,
1976         .agp_destroy_pages      = agp_generic_destroy_pages,
1977         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1978 };
1979
1980 static const struct agp_bridge_driver intel_915_driver = {
1981         .owner                  = THIS_MODULE,
1982         .aperture_sizes         = intel_i830_sizes,
1983         .size_type              = FIXED_APER_SIZE,
1984         .num_aperture_sizes     = 4,
1985         .needs_scratch_page     = true,
1986         .configure              = intel_i915_configure,
1987         .fetch_size             = intel_i9xx_fetch_size,
1988         .cleanup                = intel_i915_cleanup,
1989         .tlb_flush              = intel_i810_tlbflush,
1990         .mask_memory            = intel_i810_mask_memory,
1991         .masks                  = intel_i810_masks,
1992         .agp_enable             = intel_i810_agp_enable,
1993         .cache_flush            = global_cache_flush,
1994         .create_gatt_table      = intel_i915_create_gatt_table,
1995         .free_gatt_table        = intel_i830_free_gatt_table,
1996         .insert_memory          = intel_i915_insert_entries,
1997         .remove_memory          = intel_i915_remove_entries,
1998         .alloc_by_type          = intel_i830_alloc_by_type,
1999         .free_by_type           = intel_i810_free_by_type,
2000         .agp_alloc_page         = agp_generic_alloc_page,
2001         .agp_alloc_pages        = agp_generic_alloc_pages,
2002         .agp_destroy_page       = agp_generic_destroy_page,
2003         .agp_destroy_pages      = agp_generic_destroy_pages,
2004         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2005         .chipset_flush          = intel_i915_chipset_flush,
2006 };
2007
2008 static const struct agp_bridge_driver intel_i965_driver = {
2009         .owner                  = THIS_MODULE,
2010         .aperture_sizes         = intel_i830_sizes,
2011         .size_type              = FIXED_APER_SIZE,
2012         .num_aperture_sizes     = 4,
2013         .needs_scratch_page     = true,
2014         .configure              = intel_i915_configure,
2015         .fetch_size             = intel_i9xx_fetch_size,
2016         .cleanup                = intel_i915_cleanup,
2017         .tlb_flush              = intel_i810_tlbflush,
2018         .mask_memory            = intel_i965_mask_memory,
2019         .masks                  = intel_i810_masks,
2020         .agp_enable             = intel_i810_agp_enable,
2021         .cache_flush            = global_cache_flush,
2022         .create_gatt_table      = intel_i965_create_gatt_table,
2023         .free_gatt_table        = intel_i830_free_gatt_table,
2024         .insert_memory          = intel_i915_insert_entries,
2025         .remove_memory          = intel_i915_remove_entries,
2026         .alloc_by_type          = intel_i830_alloc_by_type,
2027         .free_by_type           = intel_i810_free_by_type,
2028         .agp_alloc_page         = agp_generic_alloc_page,
2029         .agp_alloc_pages        = agp_generic_alloc_pages,
2030         .agp_destroy_page       = agp_generic_destroy_page,
2031         .agp_destroy_pages      = agp_generic_destroy_pages,
2032         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2033         .chipset_flush          = intel_i915_chipset_flush,
2034 };
2035
2036 static const struct agp_bridge_driver intel_7505_driver = {
2037         .owner                  = THIS_MODULE,
2038         .aperture_sizes         = intel_8xx_sizes,
2039         .size_type              = U8_APER_SIZE,
2040         .num_aperture_sizes     = 7,
2041         .configure              = intel_7505_configure,
2042         .fetch_size             = intel_8xx_fetch_size,
2043         .cleanup                = intel_8xx_cleanup,
2044         .tlb_flush              = intel_8xx_tlbflush,
2045         .mask_memory            = agp_generic_mask_memory,
2046         .masks                  = intel_generic_masks,
2047         .agp_enable             = agp_generic_enable,
2048         .cache_flush            = global_cache_flush,
2049         .create_gatt_table      = agp_generic_create_gatt_table,
2050         .free_gatt_table        = agp_generic_free_gatt_table,
2051         .insert_memory          = agp_generic_insert_memory,
2052         .remove_memory          = agp_generic_remove_memory,
2053         .alloc_by_type          = agp_generic_alloc_by_type,
2054         .free_by_type           = agp_generic_free_by_type,
2055         .agp_alloc_page         = agp_generic_alloc_page,
2056         .agp_alloc_pages        = agp_generic_alloc_pages,
2057         .agp_destroy_page       = agp_generic_destroy_page,
2058         .agp_destroy_pages      = agp_generic_destroy_pages,
2059         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2060 };
2061
2062 static const struct agp_bridge_driver intel_g33_driver = {
2063         .owner                  = THIS_MODULE,
2064         .aperture_sizes         = intel_i830_sizes,
2065         .size_type              = FIXED_APER_SIZE,
2066         .num_aperture_sizes     = 4,
2067         .needs_scratch_page     = true,
2068         .configure              = intel_i915_configure,
2069         .fetch_size             = intel_i9xx_fetch_size,
2070         .cleanup                = intel_i915_cleanup,
2071         .tlb_flush              = intel_i810_tlbflush,
2072         .mask_memory            = intel_i965_mask_memory,
2073         .masks                  = intel_i810_masks,
2074         .agp_enable             = intel_i810_agp_enable,
2075         .cache_flush            = global_cache_flush,
2076         .create_gatt_table      = intel_i915_create_gatt_table,
2077         .free_gatt_table        = intel_i830_free_gatt_table,
2078         .insert_memory          = intel_i915_insert_entries,
2079         .remove_memory          = intel_i915_remove_entries,
2080         .alloc_by_type          = intel_i830_alloc_by_type,
2081         .free_by_type           = intel_i810_free_by_type,
2082         .agp_alloc_page         = agp_generic_alloc_page,
2083         .agp_alloc_pages        = agp_generic_alloc_pages,
2084         .agp_destroy_page       = agp_generic_destroy_page,
2085         .agp_destroy_pages      = agp_generic_destroy_pages,
2086         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2087         .chipset_flush          = intel_i915_chipset_flush,
2088 };
2089
2090 static int find_gmch(u16 device)
2091 {
2092         struct pci_dev *gmch_device;
2093
2094         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2095         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2096                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2097                                              device, gmch_device);
2098         }
2099
2100         if (!gmch_device)
2101                 return 0;
2102
2103         intel_private.pcidev = gmch_device;
2104         return 1;
2105 }
2106
2107 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2108  * driver and gmch_driver must be non-null, and find_gmch will determine
2109  * which one should be used if a gmch_chip_id is present.
2110  */
2111 static const struct intel_driver_description {
2112         unsigned int chip_id;
2113         unsigned int gmch_chip_id;
2114         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2115         char *name;
2116         const struct agp_bridge_driver *driver;
2117         const struct agp_bridge_driver *gmch_driver;
2118 } intel_agp_chipsets[] = {
2119         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2120         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2121         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2122         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2123                 NULL, &intel_810_driver },
2124         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2125                 NULL, &intel_810_driver },
2126         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2127                 NULL, &intel_810_driver },
2128         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2129                 &intel_815_driver, &intel_810_driver },
2130         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2131         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2132         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2133                 &intel_830mp_driver, &intel_830_driver },
2134         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2135         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2136         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2137                 &intel_845_driver, &intel_830_driver },
2138         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2139         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2140                 &intel_845_driver, &intel_830_driver },
2141         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2142         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2143                 &intel_845_driver, &intel_830_driver },
2144         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2145         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2146                 &intel_845_driver, &intel_830_driver },
2147         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2148         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2149                 NULL, &intel_915_driver },
2150         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2151                 NULL, &intel_915_driver },
2152         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2153                 NULL, &intel_915_driver },
2154         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2155                 NULL, &intel_915_driver },
2156         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2157                 NULL, &intel_915_driver },
2158         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2159                 NULL, &intel_915_driver },
2160         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2161                 NULL, &intel_i965_driver },
2162         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2163                 NULL, &intel_i965_driver },
2164         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2165                 NULL, &intel_i965_driver },
2166         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2167                 NULL, &intel_i965_driver },
2168         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2169                 NULL, &intel_i965_driver },
2170         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2171                 NULL, &intel_i965_driver },
2172         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2173         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2174         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2175                 NULL, &intel_g33_driver },
2176         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2177                 NULL, &intel_g33_driver },
2178         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2179                 NULL, &intel_g33_driver },
2180         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2181                 NULL, &intel_g33_driver },
2182         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2183                 NULL, &intel_g33_driver },
2184         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2185             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2186         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2187             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2188         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2189             "Q45/Q43", NULL, &intel_i965_driver },
2190         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2191             "G45/G43", NULL, &intel_i965_driver },
2192         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2193             "G41", NULL, &intel_i965_driver },
2194         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2195             "IGDNG/D", NULL, &intel_i965_driver },
2196         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2197             "IGDNG/M", NULL, &intel_i965_driver },
2198         { 0, 0, 0, NULL, NULL, NULL }
2199 };
2200
2201 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2202                                      const struct pci_device_id *ent)
2203 {
2204         struct agp_bridge_data *bridge;
2205         u8 cap_ptr = 0;
2206         struct resource *r;
2207         int i;
2208
2209         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2210
2211         bridge = agp_alloc_bridge();
2212         if (!bridge)
2213                 return -ENOMEM;
2214
2215         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2216                 /* In case that multiple models of gfx chip may
2217                    stand on same host bridge type, this can be
2218                    sure we detect the right IGD. */
2219                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2220                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2221                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2222                                 bridge->driver =
2223                                         intel_agp_chipsets[i].gmch_driver;
2224                                 break;
2225                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2226                                 continue;
2227                         } else {
2228                                 bridge->driver = intel_agp_chipsets[i].driver;
2229                                 break;
2230                         }
2231                 }
2232         }
2233
2234         if (intel_agp_chipsets[i].name == NULL) {
2235                 if (cap_ptr)
2236                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2237                                  pdev->vendor, pdev->device);
2238                 agp_put_bridge(bridge);
2239                 return -ENODEV;
2240         }
2241
2242         if (bridge->driver == NULL) {
2243                 /* bridge has no AGP and no IGD detected */
2244                 if (cap_ptr)
2245                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2246                                  intel_agp_chipsets[i].gmch_chip_id);
2247                 agp_put_bridge(bridge);
2248                 return -ENODEV;
2249         }
2250
2251         bridge->dev = pdev;
2252         bridge->capndx = cap_ptr;
2253         bridge->dev_private_data = &intel_private;
2254
2255         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2256
2257         /*
2258         * The following fixes the case where the BIOS has "forgotten" to
2259         * provide an address range for the GART.
2260         * 20030610 - hamish@zot.org
2261         */
2262         r = &pdev->resource[0];
2263         if (!r->start && r->end) {
2264                 if (pci_assign_resource(pdev, 0)) {
2265                         dev_err(&pdev->dev, "can't assign resource 0\n");
2266                         agp_put_bridge(bridge);
2267                         return -ENODEV;
2268                 }
2269         }
2270
2271         /*
2272         * If the device has not been properly setup, the following will catch
2273         * the problem and should stop the system from crashing.
2274         * 20030610 - hamish@zot.org
2275         */
2276         if (pci_enable_device(pdev)) {
2277                 dev_err(&pdev->dev, "can't enable PCI device\n");
2278                 agp_put_bridge(bridge);
2279                 return -ENODEV;
2280         }
2281
2282         /* Fill in the mode register */
2283         if (cap_ptr) {
2284                 pci_read_config_dword(pdev,
2285                                 bridge->capndx+PCI_AGP_STATUS,
2286                                 &bridge->mode);
2287         }
2288
2289         pci_set_drvdata(pdev, bridge);
2290         return agp_add_bridge(bridge);
2291 }
2292
2293 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2294 {
2295         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2296
2297         agp_remove_bridge(bridge);
2298
2299         if (intel_private.pcidev)
2300                 pci_dev_put(intel_private.pcidev);
2301
2302         agp_put_bridge(bridge);
2303 }
2304
2305 #ifdef CONFIG_PM
2306 static int agp_intel_resume(struct pci_dev *pdev)
2307 {
2308         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2309         int ret_val;
2310
2311         pci_restore_state(pdev);
2312
2313         /* We should restore our graphics device's config space,
2314          * as host bridge (00:00) resumes before graphics device (02:00),
2315          * then our access to its pci space can work right.
2316          */
2317         if (intel_private.pcidev)
2318                 pci_restore_state(intel_private.pcidev);
2319
2320         if (bridge->driver == &intel_generic_driver)
2321                 intel_configure();
2322         else if (bridge->driver == &intel_850_driver)
2323                 intel_850_configure();
2324         else if (bridge->driver == &intel_845_driver)
2325                 intel_845_configure();
2326         else if (bridge->driver == &intel_830mp_driver)
2327                 intel_830mp_configure();
2328         else if (bridge->driver == &intel_915_driver)
2329                 intel_i915_configure();
2330         else if (bridge->driver == &intel_830_driver)
2331                 intel_i830_configure();
2332         else if (bridge->driver == &intel_810_driver)
2333                 intel_i810_configure();
2334         else if (bridge->driver == &intel_i965_driver)
2335                 intel_i915_configure();
2336
2337         ret_val = agp_rebind_memory();
2338         if (ret_val != 0)
2339                 return ret_val;
2340
2341         return 0;
2342 }
2343 #endif
2344
2345 static struct pci_device_id agp_intel_pci_table[] = {
2346 #define ID(x)                                           \
2347         {                                               \
2348         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2349         .class_mask     = ~0,                           \
2350         .vendor         = PCI_VENDOR_ID_INTEL,          \
2351         .device         = x,                            \
2352         .subvendor      = PCI_ANY_ID,                   \
2353         .subdevice      = PCI_ANY_ID,                   \
2354         }
2355         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2356         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2357         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2358         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2359         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2360         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2361         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2362         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2363         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2364         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2365         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2366         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2367         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2368         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2369         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2370         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2371         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2372         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2373         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2374         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2375         ID(PCI_DEVICE_ID_INTEL_7505_0),
2376         ID(PCI_DEVICE_ID_INTEL_7205_0),
2377         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2378         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2379         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2380         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2381         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2382         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2383         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2384         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2385         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2386         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2387         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2388         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2389         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2390         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2391         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2392         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2393         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2394         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2395         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2396         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2397         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2398         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2399         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2400         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2401         { }
2402 };
2403
2404 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2405
2406 static struct pci_driver agp_intel_pci_driver = {
2407         .name           = "agpgart-intel",
2408         .id_table       = agp_intel_pci_table,
2409         .probe          = agp_intel_probe,
2410         .remove         = __devexit_p(agp_intel_remove),
2411 #ifdef CONFIG_PM
2412         .resume         = agp_intel_resume,
2413 #endif
2414 };
2415
2416 static int __init agp_intel_init(void)
2417 {
2418         if (agp_off)
2419                 return -EINVAL;
2420         return pci_register_driver(&agp_intel_pci_driver);
2421 }
2422
2423 static void __exit agp_intel_cleanup(void)
2424 {
2425         pci_unregister_driver(&agp_intel_pci_driver);
2426 }
2427
2428 module_init(agp_intel_init);
2429 module_exit(agp_intel_cleanup);
2430
2431 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2432 MODULE_LICENSE("GPL and additional rights");