2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] =
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nosntf] =
128 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_yes_fbs] =
136 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
180 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
181 AHCI_HFLAG_32BIT_ONLY),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_pmp_retry_srst_ops,
187 [board_ahci_sb700] = /* for SB700 and SB800 */
189 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_vt8251] =
197 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_vt8251_ops,
205 static const struct pci_device_id ahci_pci_tbl[] = {
207 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
208 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
209 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
210 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
211 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
212 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
213 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
216 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
217 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
220 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
222 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
236 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
239 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
249 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
254 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
257 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
260 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
274 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
275 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
282 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
283 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
298 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
302 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
307 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
308 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
309 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
312 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
313 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
316 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
317 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
322 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
323 /* AMD is using RAID class only for ahci controllers */
324 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
325 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
328 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
329 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
332 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
419 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
420 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
422 /* ST Microelectronics */
423 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
426 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
427 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
428 { PCI_DEVICE(0x1b4b, 0x9123),
429 .class = PCI_CLASS_STORAGE_SATA_AHCI,
430 .class_mask = 0xffffff,
431 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
432 { PCI_DEVICE(0x1b4b, 0x9125),
433 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
434 { PCI_DEVICE(0x1b4b, 0x917a),
435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
436 { PCI_DEVICE(0x1b4b, 0x9192),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
438 { PCI_DEVICE(0x1b4b, 0x91a3),
439 .driver_data = board_ahci_yes_fbs },
442 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
445 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
446 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
447 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
448 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
451 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
453 /* Generic, PCI class code for AHCI */
454 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
455 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
457 { } /* terminate list */
461 static struct pci_driver ahci_pci_driver = {
463 .id_table = ahci_pci_tbl,
464 .probe = ahci_init_one,
465 .remove = ata_pci_remove_one,
467 .suspend = ahci_pci_device_suspend,
468 .resume = ahci_pci_device_resume,
472 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
473 static int marvell_enable;
475 static int marvell_enable = 1;
477 module_param(marvell_enable, int, 0644);
478 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
481 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
482 struct ahci_host_priv *hpriv)
484 unsigned int force_port_map = 0;
485 unsigned int mask_port_map = 0;
487 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
488 dev_info(&pdev->dev, "JMB361 has only one port\n");
493 * Temporary Marvell 6145 hack: PATA port presence
494 * is asserted through the standard AHCI port
495 * presence register, as bit 4 (counting from 0)
497 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
498 if (pdev->device == 0x6121)
503 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
506 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
510 static int ahci_pci_reset_controller(struct ata_host *host)
512 struct pci_dev *pdev = to_pci_dev(host->dev);
514 ahci_reset_controller(host);
516 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
517 struct ahci_host_priv *hpriv = host->private_data;
521 pci_read_config_word(pdev, 0x92, &tmp16);
522 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
523 tmp16 |= hpriv->port_map;
524 pci_write_config_word(pdev, 0x92, tmp16);
531 static void ahci_pci_init_controller(struct ata_host *host)
533 struct ahci_host_priv *hpriv = host->private_data;
534 struct pci_dev *pdev = to_pci_dev(host->dev);
535 void __iomem *port_mmio;
539 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
540 if (pdev->device == 0x6121)
544 port_mmio = __ahci_port_base(host, mv);
546 writel(0, port_mmio + PORT_IRQ_MASK);
549 tmp = readl(port_mmio + PORT_IRQ_STAT);
550 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
552 writel(tmp, port_mmio + PORT_IRQ_STAT);
555 ahci_init_controller(host);
558 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
559 unsigned long deadline)
561 struct ata_port *ap = link->ap;
567 ahci_stop_engine(ap);
569 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
570 deadline, &online, NULL);
572 ahci_start_engine(ap);
574 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
576 /* vt8251 doesn't clear BSY on signature FIS reception,
577 * request follow-up softreset.
579 return online ? -EAGAIN : rc;
582 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
583 unsigned long deadline)
585 struct ata_port *ap = link->ap;
586 struct ahci_port_priv *pp = ap->private_data;
587 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
588 struct ata_taskfile tf;
592 ahci_stop_engine(ap);
594 /* clear D2H reception area to properly wait for D2H FIS */
595 ata_tf_init(link->device, &tf);
597 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
599 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
600 deadline, &online, NULL);
602 ahci_start_engine(ap);
604 /* The pseudo configuration device on SIMG4726 attached to
605 * ASUS P5W-DH Deluxe doesn't send signature FIS after
606 * hardreset if no device is attached to the first downstream
607 * port && the pseudo device locks up on SRST w/ PMP==0. To
608 * work around this, wait for !BSY only briefly. If BSY isn't
609 * cleared, perform CLO and proceed to IDENTIFY (achieved by
610 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
612 * Wait for two seconds. Devices attached to downstream port
613 * which can't process the following IDENTIFY after this will
614 * have to be reset again. For most cases, this should
615 * suffice while making probing snappish enough.
618 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
621 ahci_kick_engine(ap);
627 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
629 struct ata_host *host = dev_get_drvdata(&pdev->dev);
630 struct ahci_host_priv *hpriv = host->private_data;
631 void __iomem *mmio = hpriv->mmio;
634 if (mesg.event & PM_EVENT_SUSPEND &&
635 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
637 "BIOS update required for suspend/resume\n");
641 if (mesg.event & PM_EVENT_SLEEP) {
642 /* AHCI spec rev1.1 section 8.3.3:
643 * Software must disable interrupts prior to requesting a
644 * transition of the HBA to D3 state.
646 ctl = readl(mmio + HOST_CTL);
648 writel(ctl, mmio + HOST_CTL);
649 readl(mmio + HOST_CTL); /* flush */
652 return ata_pci_device_suspend(pdev, mesg);
655 static int ahci_pci_device_resume(struct pci_dev *pdev)
657 struct ata_host *host = dev_get_drvdata(&pdev->dev);
660 rc = ata_pci_device_do_resume(pdev);
664 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
665 rc = ahci_pci_reset_controller(host);
669 ahci_pci_init_controller(host);
672 ata_host_resume(host);
678 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
683 * If the device fixup already set the dma_mask to some non-standard
684 * value, don't extend it here. This happens on STA2X11, for example.
686 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
690 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
691 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
693 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
696 "64-bit DMA enable failed\n");
701 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
703 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
706 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
709 "32-bit consistent DMA enable failed\n");
716 static void ahci_pci_print_info(struct ata_host *host)
718 struct pci_dev *pdev = to_pci_dev(host->dev);
722 pci_read_config_word(pdev, 0x0a, &cc);
723 if (cc == PCI_CLASS_STORAGE_IDE)
725 else if (cc == PCI_CLASS_STORAGE_SATA)
727 else if (cc == PCI_CLASS_STORAGE_RAID)
732 ahci_print_info(host, scc_s);
735 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
736 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
737 * support PMP and the 4726 either directly exports the device
738 * attached to the first downstream port or acts as a hardware storage
739 * controller and emulate a single ATA device (can be RAID 0/1 or some
740 * other configuration).
742 * When there's no device attached to the first downstream port of the
743 * 4726, "Config Disk" appears, which is a pseudo ATA device to
744 * configure the 4726. However, ATA emulation of the device is very
745 * lame. It doesn't send signature D2H Reg FIS after the initial
746 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
748 * The following function works around the problem by always using
749 * hardreset on the port and not depending on receiving signature FIS
750 * afterward. If signature FIS isn't received soon, ATA class is
751 * assumed without follow-up softreset.
753 static void ahci_p5wdh_workaround(struct ata_host *host)
755 static struct dmi_system_id sysids[] = {
757 .ident = "P5W DH Deluxe",
759 DMI_MATCH(DMI_SYS_VENDOR,
760 "ASUSTEK COMPUTER INC"),
761 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
766 struct pci_dev *pdev = to_pci_dev(host->dev);
768 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
769 dmi_check_system(sysids)) {
770 struct ata_port *ap = host->ports[1];
773 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
775 ap->ops = &ahci_p5wdh_ops;
776 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
780 /* only some SB600 ahci controllers can do 64bit DMA */
781 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
783 static const struct dmi_system_id sysids[] = {
785 * The oldest version known to be broken is 0901 and
786 * working is 1501 which was released on 2007-10-26.
787 * Enable 64bit DMA on 1501 and anything newer.
789 * Please read bko#9412 for more info.
792 .ident = "ASUS M2A-VM",
794 DMI_MATCH(DMI_BOARD_VENDOR,
795 "ASUSTeK Computer INC."),
796 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
798 .driver_data = "20071026", /* yyyymmdd */
801 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
804 * BIOS versions earlier than 1.5 had the Manufacturer DMI
805 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
806 * This spelling mistake was fixed in BIOS version 1.5, so
807 * 1.5 and later have the Manufacturer as
808 * "MICRO-STAR INTERNATIONAL CO.,LTD".
809 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
811 * BIOS versions earlier than 1.9 had a Board Product Name
812 * DMI field of "MS-7376". This was changed to be
813 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
814 * match on DMI_BOARD_NAME of "MS-7376".
817 .ident = "MSI K9A2 Platinum",
819 DMI_MATCH(DMI_BOARD_VENDOR,
821 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
825 * All BIOS versions for the Asus M3A support 64bit DMA.
826 * (all release versions from 0301 to 1206 were tested)
831 DMI_MATCH(DMI_BOARD_VENDOR,
832 "ASUSTeK Computer INC."),
833 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
838 const struct dmi_system_id *match;
839 int year, month, date;
842 match = dmi_first_match(sysids);
843 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
847 if (!match->driver_data)
850 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
851 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
853 if (strcmp(buf, match->driver_data) >= 0)
857 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
863 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
867 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
869 static const struct dmi_system_id broken_systems[] = {
871 .ident = "HP Compaq nx6310",
873 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
874 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
876 /* PCI slot number of the controller */
877 .driver_data = (void *)0x1FUL,
880 .ident = "HP Compaq 6720s",
882 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
883 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
885 /* PCI slot number of the controller */
886 .driver_data = (void *)0x1FUL,
889 { } /* terminate list */
891 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
894 unsigned long slot = (unsigned long)dmi->driver_data;
895 /* apply the quirk only to on-board controllers */
896 return slot == PCI_SLOT(pdev->devfn);
902 static bool ahci_broken_suspend(struct pci_dev *pdev)
904 static const struct dmi_system_id sysids[] = {
906 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
907 * to the harddisk doesn't become online after
908 * resuming from STR. Warn and fail suspend.
910 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
912 * Use dates instead of versions to match as HP is
913 * apparently recycling both product and version
916 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME,
923 "HP Pavilion dv4 Notebook PC"),
925 .driver_data = "20090105", /* F.30 */
930 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
931 DMI_MATCH(DMI_PRODUCT_NAME,
932 "HP Pavilion dv5 Notebook PC"),
934 .driver_data = "20090506", /* F.16 */
939 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
940 DMI_MATCH(DMI_PRODUCT_NAME,
941 "HP Pavilion dv6 Notebook PC"),
943 .driver_data = "20090423", /* F.21 */
948 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
949 DMI_MATCH(DMI_PRODUCT_NAME,
950 "HP HDX18 Notebook PC"),
952 .driver_data = "20090430", /* F.23 */
955 * Acer eMachines G725 has the same problem. BIOS
956 * V1.03 is known to be broken. V3.04 is known to
957 * work. Between, there are V1.06, V2.06 and V3.03
958 * that we don't have much idea about. For now,
959 * blacklist anything older than V3.04.
961 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
966 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
967 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
969 .driver_data = "20091216", /* V3.04 */
971 { } /* terminate list */
973 const struct dmi_system_id *dmi = dmi_first_match(sysids);
974 int year, month, date;
977 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
980 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
981 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
983 return strcmp(buf, dmi->driver_data) < 0;
986 static bool ahci_broken_online(struct pci_dev *pdev)
988 #define ENCODE_BUSDEVFN(bus, slot, func) \
989 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
990 static const struct dmi_system_id sysids[] = {
992 * There are several gigabyte boards which use
993 * SIMG5723s configured as hardware RAID. Certain
994 * 5723 firmware revisions shipped there keep the link
995 * online but fail to answer properly to SRST or
996 * IDENTIFY when no device is attached downstream
997 * causing libata to retry quite a few times leading
998 * to excessive detection delay.
1000 * As these firmwares respond to the second reset try
1001 * with invalid device signature, considering unknown
1002 * sig as offline works around the problem acceptably.
1005 .ident = "EP45-DQ6",
1007 DMI_MATCH(DMI_BOARD_VENDOR,
1008 "Gigabyte Technology Co., Ltd."),
1009 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1011 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1014 .ident = "EP45-DS5",
1016 DMI_MATCH(DMI_BOARD_VENDOR,
1017 "Gigabyte Technology Co., Ltd."),
1018 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1020 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1022 { } /* terminate list */
1024 #undef ENCODE_BUSDEVFN
1025 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1031 val = (unsigned long)dmi->driver_data;
1033 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1036 #ifdef CONFIG_ATA_ACPI
1037 static void ahci_gtf_filter_workaround(struct ata_host *host)
1039 static const struct dmi_system_id sysids[] = {
1041 * Aspire 3810T issues a bunch of SATA enable commands
1042 * via _GTF including an invalid one and one which is
1043 * rejected by the device. Among the successful ones
1044 * is FPDMA non-zero offset enable which when enabled
1045 * only on the drive side leads to NCQ command
1046 * failures. Filter it out.
1049 .ident = "Aspire 3810T",
1051 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1054 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1058 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1059 unsigned int filter;
1065 filter = (unsigned long)dmi->driver_data;
1066 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1067 filter, dmi->ident);
1069 for (i = 0; i < host->n_ports; i++) {
1070 struct ata_port *ap = host->ports[i];
1071 struct ata_link *link;
1072 struct ata_device *dev;
1074 ata_for_each_link(link, ap, EDGE)
1075 ata_for_each_dev(dev, link, ALL)
1076 dev->gtf_filter |= filter;
1080 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1084 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1086 unsigned int board_id = ent->driver_data;
1087 struct ata_port_info pi = ahci_port_info[board_id];
1088 const struct ata_port_info *ppi[] = { &pi, NULL };
1089 struct device *dev = &pdev->dev;
1090 struct ahci_host_priv *hpriv;
1091 struct ata_host *host;
1093 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1097 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1099 ata_print_version_once(&pdev->dev, DRV_VERSION);
1101 /* The AHCI driver can only drive the SATA ports, the PATA driver
1102 can drive them all so if both drivers are selected make sure
1103 AHCI stays out of the way */
1104 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1108 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1109 * ahci, use ata_generic instead.
1111 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1112 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1113 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1114 pdev->subsystem_device == 0xcb89)
1117 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1118 * At the moment, we can only use the AHCI mode. Let the users know
1119 * that for SAS drives they're out of luck.
1121 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1122 dev_info(&pdev->dev,
1123 "PDC42819 can only drive SATA devices with this driver\n");
1125 /* Both Connext and Enmotus devices use non-standard BARs */
1126 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1127 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1128 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1129 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1131 /* acquire resources */
1132 rc = pcim_enable_device(pdev);
1136 /* AHCI controllers often implement SFF compatible interface.
1137 * Grab all PCI BARs just in case.
1139 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1141 pcim_pin_device(pdev);
1145 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1146 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1149 /* ICH6s share the same PCI ID for both piix and ahci
1150 * modes. Enabling ahci mode while MAP indicates
1151 * combined mode is a bad idea. Yield to ata_piix.
1153 pci_read_config_byte(pdev, ICH_MAP, &map);
1155 dev_info(&pdev->dev,
1156 "controller is in combined mode, can't enable AHCI mode\n");
1161 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1164 hpriv->flags |= (unsigned long)pi.private_data;
1166 /* MCP65 revision A1 and A2 can't do MSI */
1167 if (board_id == board_ahci_mcp65 &&
1168 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1169 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1171 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1172 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1173 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1175 /* only some SB600s can do 64bit DMA */
1176 if (ahci_sb600_enable_64bit(pdev))
1177 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1179 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1182 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1184 /* save initial config */
1185 ahci_pci_save_initial_config(pdev, hpriv);
1188 if (hpriv->cap & HOST_CAP_NCQ) {
1189 pi.flags |= ATA_FLAG_NCQ;
1191 * Auto-activate optimization is supposed to be
1192 * supported on all AHCI controllers indicating NCQ
1193 * capability, but it seems to be broken on some
1194 * chipsets including NVIDIAs.
1196 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1197 pi.flags |= ATA_FLAG_FPDMA_AA;
1200 if (hpriv->cap & HOST_CAP_PMP)
1201 pi.flags |= ATA_FLAG_PMP;
1203 ahci_set_em_messages(hpriv, &pi);
1205 if (ahci_broken_system_poweroff(pdev)) {
1206 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1207 dev_info(&pdev->dev,
1208 "quirky BIOS, skipping spindown on poweroff\n");
1211 if (ahci_broken_suspend(pdev)) {
1212 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1213 dev_warn(&pdev->dev,
1214 "BIOS update required for suspend/resume\n");
1217 if (ahci_broken_online(pdev)) {
1218 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1219 dev_info(&pdev->dev,
1220 "online status unreliable, applying workaround\n");
1223 /* CAP.NP sometimes indicate the index of the last enabled
1224 * port, at other times, that of the last possible port, so
1225 * determining the maximum port number requires looking at
1226 * both CAP.NP and port_map.
1228 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1230 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1233 host->private_data = hpriv;
1235 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1236 host->flags |= ATA_HOST_PARALLEL_SCAN;
1238 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1240 if (pi.flags & ATA_FLAG_EM)
1241 ahci_reset_em(host);
1243 for (i = 0; i < host->n_ports; i++) {
1244 struct ata_port *ap = host->ports[i];
1246 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1247 ata_port_pbar_desc(ap, ahci_pci_bar,
1248 0x100 + ap->port_no * 0x80, "port");
1250 /* set enclosure management message type */
1251 if (ap->flags & ATA_FLAG_EM)
1252 ap->em_message_type = hpriv->em_msg_type;
1255 /* disabled/not-implemented port */
1256 if (!(hpriv->port_map & (1 << i)))
1257 ap->ops = &ata_dummy_port_ops;
1260 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1261 ahci_p5wdh_workaround(host);
1263 /* apply gtf filter quirk */
1264 ahci_gtf_filter_workaround(host);
1266 /* initialize adapter */
1267 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1271 rc = ahci_pci_reset_controller(host);
1275 ahci_pci_init_controller(host);
1276 ahci_pci_print_info(host);
1278 pci_set_master(pdev);
1279 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1283 static int __init ahci_init(void)
1285 return pci_register_driver(&ahci_pci_driver);
1288 static void __exit ahci_exit(void)
1290 pci_unregister_driver(&ahci_pci_driver);
1294 MODULE_AUTHOR("Jeff Garzik");
1295 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1296 MODULE_LICENSE("GPL");
1297 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1298 MODULE_VERSION(DRV_VERSION);
1300 module_init(ahci_init);
1301 module_exit(ahci_exit);