2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
76 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
86 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
95 static int ahci_pci_device_resume(struct pci_dev *pdev);
98 static struct scsi_host_template ahci_sht = {
102 static struct ata_port_operations ahci_vt8251_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_vt8251_hardreset,
107 static struct ata_port_operations ahci_p5wdh_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_p5wdh_hardreset,
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] =
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_nomsi] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_noncq] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_nosntf] =
152 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_yes_fbs] =
160 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_avn_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = /* for SB700 and SB800 */
219 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
225 [board_ahci_vt8251] =
227 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_vt8251_ops,
235 static const struct pci_device_id ahci_pci_tbl[] = {
237 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
238 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
239 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
240 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
241 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
242 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
243 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
245 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
247 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
249 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
251 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
252 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
265 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
266 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
268 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
278 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
279 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
280 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
281 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
282 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
283 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
284 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
285 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
286 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
287 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
288 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
289 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
290 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
291 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
292 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
293 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
294 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
295 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
296 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
297 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
298 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
299 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
300 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
301 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
302 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
303 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
309 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
310 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
311 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
312 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
313 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
316 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
317 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
318 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
319 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
320 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
321 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
322 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
323 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
328 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
329 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
330 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
331 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
332 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
333 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
334 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
335 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
336 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
337 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
338 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
339 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
340 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
341 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
342 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
343 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
345 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
346 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
347 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
348 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
349 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
350 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
353 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
354 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
355 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
356 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
357 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
358 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
359 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
360 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
361 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
362 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
363 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
364 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
365 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
366 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
367 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
368 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
370 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
371 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
372 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
373 /* JMicron 362B and 362C have an AHCI function with IDE class code */
374 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
375 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
378 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
379 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
380 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
381 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
382 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
383 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
384 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
387 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
388 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
389 /* AMD is using RAID class only for ahci controllers */
390 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
394 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
395 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
398 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
399 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
400 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
401 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
407 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
408 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
419 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
420 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
421 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
422 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
423 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
424 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
425 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
426 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
427 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
428 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
429 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
430 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
431 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
432 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
433 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
434 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
435 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
436 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
437 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
438 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
439 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
440 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
441 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
442 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
443 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
444 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
445 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
447 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
448 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
449 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
450 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
451 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
452 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
453 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
454 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
455 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
456 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
457 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
459 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
460 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
461 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
462 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
463 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
464 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
465 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
466 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
467 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
468 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
469 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
470 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
471 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
472 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
473 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
474 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
475 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
476 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
477 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
478 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
479 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
480 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
481 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
484 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
485 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
486 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
488 /* ST Microelectronics */
489 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
492 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
493 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
494 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
495 .class = PCI_CLASS_STORAGE_SATA_AHCI,
496 .class_mask = 0xffffff,
497 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
498 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
499 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
500 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
501 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
502 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
503 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
504 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
505 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
506 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
507 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
508 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
509 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
510 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
511 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
512 .driver_data = board_ahci_yes_fbs },
513 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
514 .driver_data = board_ahci_yes_fbs },
515 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
516 .driver_data = board_ahci_yes_fbs },
517 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
518 .driver_data = board_ahci_yes_fbs },
519 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
520 .driver_data = board_ahci_yes_fbs },
523 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
524 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
527 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
528 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
529 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
530 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
533 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
534 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
536 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
537 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
540 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
542 /* Generic, PCI class code for AHCI */
543 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
544 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
546 { } /* terminate list */
550 static struct pci_driver ahci_pci_driver = {
552 .id_table = ahci_pci_tbl,
553 .probe = ahci_init_one,
554 .remove = ata_pci_remove_one,
556 .suspend = ahci_pci_device_suspend,
557 .resume = ahci_pci_device_resume,
561 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
562 static int marvell_enable;
564 static int marvell_enable = 1;
566 module_param(marvell_enable, int, 0644);
567 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
570 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
571 struct ahci_host_priv *hpriv)
573 unsigned int force_port_map = 0;
574 unsigned int mask_port_map = 0;
576 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
577 dev_info(&pdev->dev, "JMB361 has only one port\n");
582 * Temporary Marvell 6145 hack: PATA port presence
583 * is asserted through the standard AHCI port
584 * presence register, as bit 4 (counting from 0)
586 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
587 if (pdev->device == 0x6121)
592 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
595 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
599 static int ahci_pci_reset_controller(struct ata_host *host)
601 struct pci_dev *pdev = to_pci_dev(host->dev);
603 ahci_reset_controller(host);
605 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
606 struct ahci_host_priv *hpriv = host->private_data;
610 pci_read_config_word(pdev, 0x92, &tmp16);
611 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
612 tmp16 |= hpriv->port_map;
613 pci_write_config_word(pdev, 0x92, tmp16);
620 static void ahci_pci_init_controller(struct ata_host *host)
622 struct ahci_host_priv *hpriv = host->private_data;
623 struct pci_dev *pdev = to_pci_dev(host->dev);
624 void __iomem *port_mmio;
628 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
629 if (pdev->device == 0x6121)
633 port_mmio = __ahci_port_base(host, mv);
635 writel(0, port_mmio + PORT_IRQ_MASK);
638 tmp = readl(port_mmio + PORT_IRQ_STAT);
639 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
641 writel(tmp, port_mmio + PORT_IRQ_STAT);
644 ahci_init_controller(host);
647 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
648 unsigned long deadline)
650 struct ata_port *ap = link->ap;
656 ahci_stop_engine(ap);
658 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
659 deadline, &online, NULL);
661 ahci_start_engine(ap);
663 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
665 /* vt8251 doesn't clear BSY on signature FIS reception,
666 * request follow-up softreset.
668 return online ? -EAGAIN : rc;
671 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
672 unsigned long deadline)
674 struct ata_port *ap = link->ap;
675 struct ahci_port_priv *pp = ap->private_data;
676 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
677 struct ata_taskfile tf;
681 ahci_stop_engine(ap);
683 /* clear D2H reception area to properly wait for D2H FIS */
684 ata_tf_init(link->device, &tf);
686 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
688 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
689 deadline, &online, NULL);
691 ahci_start_engine(ap);
693 /* The pseudo configuration device on SIMG4726 attached to
694 * ASUS P5W-DH Deluxe doesn't send signature FIS after
695 * hardreset if no device is attached to the first downstream
696 * port && the pseudo device locks up on SRST w/ PMP==0. To
697 * work around this, wait for !BSY only briefly. If BSY isn't
698 * cleared, perform CLO and proceed to IDENTIFY (achieved by
699 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
701 * Wait for two seconds. Devices attached to downstream port
702 * which can't process the following IDENTIFY after this will
703 * have to be reset again. For most cases, this should
704 * suffice while making probing snappish enough.
707 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
710 ahci_kick_engine(ap);
716 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
718 * It has been observed with some SSDs that the timing of events in the
719 * link synchronization phase can leave the port in a state that can not
720 * be recovered by a SATA-hard-reset alone. The failing signature is
721 * SStatus.DET stuck at 1 ("Device presence detected but Phy
722 * communication not established"). It was found that unloading and
723 * reloading the driver when this problem occurs allows the drive
724 * connection to be recovered (DET advanced to 0x3). The critical
725 * component of reloading the driver is that the port state machines are
726 * reset by bouncing "port enable" in the AHCI PCS configuration
727 * register. So, reproduce that effect by bouncing a port whenever we
728 * see DET==1 after a reset.
730 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
731 unsigned long deadline)
733 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
734 struct ata_port *ap = link->ap;
735 struct ahci_port_priv *pp = ap->private_data;
736 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
737 unsigned long tmo = deadline - jiffies;
738 struct ata_taskfile tf;
744 ahci_stop_engine(ap);
746 for (i = 0; i < 2; i++) {
749 int port = ap->port_no;
750 struct ata_host *host = ap->host;
751 struct pci_dev *pdev = to_pci_dev(host->dev);
753 /* clear D2H reception area to properly wait for D2H FIS */
754 ata_tf_init(link->device, &tf);
755 tf.command = ATA_BUSY;
756 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
758 rc = sata_link_hardreset(link, timing, deadline, &online,
761 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
762 (sstatus & 0xf) != 1)
765 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
768 pci_read_config_word(pdev, 0x92, &val);
770 pci_write_config_word(pdev, 0x92, val);
771 ata_msleep(ap, 1000);
773 pci_write_config_word(pdev, 0x92, val);
777 ahci_start_engine(ap);
780 *class = ahci_dev_classify(ap);
782 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
788 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
790 struct ata_host *host = dev_get_drvdata(&pdev->dev);
791 struct ahci_host_priv *hpriv = host->private_data;
792 void __iomem *mmio = hpriv->mmio;
795 if (mesg.event & PM_EVENT_SUSPEND &&
796 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
798 "BIOS update required for suspend/resume\n");
802 if (mesg.event & PM_EVENT_SLEEP) {
803 /* AHCI spec rev1.1 section 8.3.3:
804 * Software must disable interrupts prior to requesting a
805 * transition of the HBA to D3 state.
807 ctl = readl(mmio + HOST_CTL);
809 writel(ctl, mmio + HOST_CTL);
810 readl(mmio + HOST_CTL); /* flush */
813 return ata_pci_device_suspend(pdev, mesg);
816 static int ahci_pci_device_resume(struct pci_dev *pdev)
818 struct ata_host *host = dev_get_drvdata(&pdev->dev);
821 rc = ata_pci_device_do_resume(pdev);
825 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
826 rc = ahci_pci_reset_controller(host);
830 ahci_pci_init_controller(host);
833 ata_host_resume(host);
839 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
844 * If the device fixup already set the dma_mask to some non-standard
845 * value, don't extend it here. This happens on STA2X11, for example.
847 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
851 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
852 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
854 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
857 "64-bit DMA enable failed\n");
862 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
864 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
867 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
870 "32-bit consistent DMA enable failed\n");
877 static void ahci_pci_print_info(struct ata_host *host)
879 struct pci_dev *pdev = to_pci_dev(host->dev);
883 pci_read_config_word(pdev, 0x0a, &cc);
884 if (cc == PCI_CLASS_STORAGE_IDE)
886 else if (cc == PCI_CLASS_STORAGE_SATA)
888 else if (cc == PCI_CLASS_STORAGE_RAID)
893 ahci_print_info(host, scc_s);
896 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
897 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
898 * support PMP and the 4726 either directly exports the device
899 * attached to the first downstream port or acts as a hardware storage
900 * controller and emulate a single ATA device (can be RAID 0/1 or some
901 * other configuration).
903 * When there's no device attached to the first downstream port of the
904 * 4726, "Config Disk" appears, which is a pseudo ATA device to
905 * configure the 4726. However, ATA emulation of the device is very
906 * lame. It doesn't send signature D2H Reg FIS after the initial
907 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
909 * The following function works around the problem by always using
910 * hardreset on the port and not depending on receiving signature FIS
911 * afterward. If signature FIS isn't received soon, ATA class is
912 * assumed without follow-up softreset.
914 static void ahci_p5wdh_workaround(struct ata_host *host)
916 static struct dmi_system_id sysids[] = {
918 .ident = "P5W DH Deluxe",
920 DMI_MATCH(DMI_SYS_VENDOR,
921 "ASUSTEK COMPUTER INC"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
927 struct pci_dev *pdev = to_pci_dev(host->dev);
929 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
930 dmi_check_system(sysids)) {
931 struct ata_port *ap = host->ports[1];
934 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
936 ap->ops = &ahci_p5wdh_ops;
937 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
941 /* only some SB600 ahci controllers can do 64bit DMA */
942 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
944 static const struct dmi_system_id sysids[] = {
946 * The oldest version known to be broken is 0901 and
947 * working is 1501 which was released on 2007-10-26.
948 * Enable 64bit DMA on 1501 and anything newer.
950 * Please read bko#9412 for more info.
953 .ident = "ASUS M2A-VM",
955 DMI_MATCH(DMI_BOARD_VENDOR,
956 "ASUSTeK Computer INC."),
957 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
959 .driver_data = "20071026", /* yyyymmdd */
962 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
965 * BIOS versions earlier than 1.5 had the Manufacturer DMI
966 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
967 * This spelling mistake was fixed in BIOS version 1.5, so
968 * 1.5 and later have the Manufacturer as
969 * "MICRO-STAR INTERNATIONAL CO.,LTD".
970 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
972 * BIOS versions earlier than 1.9 had a Board Product Name
973 * DMI field of "MS-7376". This was changed to be
974 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
975 * match on DMI_BOARD_NAME of "MS-7376".
978 .ident = "MSI K9A2 Platinum",
980 DMI_MATCH(DMI_BOARD_VENDOR,
982 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
986 * All BIOS versions for the Asus M3A support 64bit DMA.
987 * (all release versions from 0301 to 1206 were tested)
992 DMI_MATCH(DMI_BOARD_VENDOR,
993 "ASUSTeK Computer INC."),
994 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
999 const struct dmi_system_id *match;
1000 int year, month, date;
1003 match = dmi_first_match(sysids);
1004 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1008 if (!match->driver_data)
1011 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1012 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1014 if (strcmp(buf, match->driver_data) >= 0)
1017 dev_warn(&pdev->dev,
1018 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1024 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1028 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1030 static const struct dmi_system_id broken_systems[] = {
1032 .ident = "HP Compaq nx6310",
1034 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1037 /* PCI slot number of the controller */
1038 .driver_data = (void *)0x1FUL,
1041 .ident = "HP Compaq 6720s",
1043 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1044 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1046 /* PCI slot number of the controller */
1047 .driver_data = (void *)0x1FUL,
1050 { } /* terminate list */
1052 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1055 unsigned long slot = (unsigned long)dmi->driver_data;
1056 /* apply the quirk only to on-board controllers */
1057 return slot == PCI_SLOT(pdev->devfn);
1063 static bool ahci_broken_suspend(struct pci_dev *pdev)
1065 static const struct dmi_system_id sysids[] = {
1067 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1068 * to the harddisk doesn't become online after
1069 * resuming from STR. Warn and fail suspend.
1071 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1073 * Use dates instead of versions to match as HP is
1074 * apparently recycling both product and version
1077 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1082 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1083 DMI_MATCH(DMI_PRODUCT_NAME,
1084 "HP Pavilion dv4 Notebook PC"),
1086 .driver_data = "20090105", /* F.30 */
1091 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1092 DMI_MATCH(DMI_PRODUCT_NAME,
1093 "HP Pavilion dv5 Notebook PC"),
1095 .driver_data = "20090506", /* F.16 */
1100 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1101 DMI_MATCH(DMI_PRODUCT_NAME,
1102 "HP Pavilion dv6 Notebook PC"),
1104 .driver_data = "20090423", /* F.21 */
1109 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1110 DMI_MATCH(DMI_PRODUCT_NAME,
1111 "HP HDX18 Notebook PC"),
1113 .driver_data = "20090430", /* F.23 */
1116 * Acer eMachines G725 has the same problem. BIOS
1117 * V1.03 is known to be broken. V3.04 is known to
1118 * work. Between, there are V1.06, V2.06 and V3.03
1119 * that we don't have much idea about. For now,
1120 * blacklist anything older than V3.04.
1122 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1127 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1128 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1130 .driver_data = "20091216", /* V3.04 */
1132 { } /* terminate list */
1134 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1135 int year, month, date;
1138 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1141 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1142 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1144 return strcmp(buf, dmi->driver_data) < 0;
1147 static bool ahci_broken_online(struct pci_dev *pdev)
1149 #define ENCODE_BUSDEVFN(bus, slot, func) \
1150 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1151 static const struct dmi_system_id sysids[] = {
1153 * There are several gigabyte boards which use
1154 * SIMG5723s configured as hardware RAID. Certain
1155 * 5723 firmware revisions shipped there keep the link
1156 * online but fail to answer properly to SRST or
1157 * IDENTIFY when no device is attached downstream
1158 * causing libata to retry quite a few times leading
1159 * to excessive detection delay.
1161 * As these firmwares respond to the second reset try
1162 * with invalid device signature, considering unknown
1163 * sig as offline works around the problem acceptably.
1166 .ident = "EP45-DQ6",
1168 DMI_MATCH(DMI_BOARD_VENDOR,
1169 "Gigabyte Technology Co., Ltd."),
1170 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1172 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1175 .ident = "EP45-DS5",
1177 DMI_MATCH(DMI_BOARD_VENDOR,
1178 "Gigabyte Technology Co., Ltd."),
1179 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1181 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1183 { } /* terminate list */
1185 #undef ENCODE_BUSDEVFN
1186 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1192 val = (unsigned long)dmi->driver_data;
1194 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1197 #ifdef CONFIG_ATA_ACPI
1198 static void ahci_gtf_filter_workaround(struct ata_host *host)
1200 static const struct dmi_system_id sysids[] = {
1202 * Aspire 3810T issues a bunch of SATA enable commands
1203 * via _GTF including an invalid one and one which is
1204 * rejected by the device. Among the successful ones
1205 * is FPDMA non-zero offset enable which when enabled
1206 * only on the drive side leads to NCQ command
1207 * failures. Filter it out.
1210 .ident = "Aspire 3810T",
1212 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1213 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1215 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1219 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1220 unsigned int filter;
1226 filter = (unsigned long)dmi->driver_data;
1227 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1228 filter, dmi->ident);
1230 for (i = 0; i < host->n_ports; i++) {
1231 struct ata_port *ap = host->ports[i];
1232 struct ata_link *link;
1233 struct ata_device *dev;
1235 ata_for_each_link(link, ap, EDGE)
1236 ata_for_each_dev(dev, link, ALL)
1237 dev->gtf_filter |= filter;
1241 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1245 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1247 unsigned int board_id = ent->driver_data;
1248 struct ata_port_info pi = ahci_port_info[board_id];
1249 const struct ata_port_info *ppi[] = { &pi, NULL };
1250 struct device *dev = &pdev->dev;
1251 struct ahci_host_priv *hpriv;
1252 struct ata_host *host;
1254 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1258 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1260 ata_print_version_once(&pdev->dev, DRV_VERSION);
1262 /* The AHCI driver can only drive the SATA ports, the PATA driver
1263 can drive them all so if both drivers are selected make sure
1264 AHCI stays out of the way */
1265 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1269 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1270 * ahci, use ata_generic instead.
1272 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1273 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1274 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1275 pdev->subsystem_device == 0xcb89)
1278 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1279 * At the moment, we can only use the AHCI mode. Let the users know
1280 * that for SAS drives they're out of luck.
1282 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1283 dev_info(&pdev->dev,
1284 "PDC42819 can only drive SATA devices with this driver\n");
1286 /* Both Connext and Enmotus devices use non-standard BARs */
1287 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1288 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1289 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1290 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1292 /* acquire resources */
1293 rc = pcim_enable_device(pdev);
1297 /* AHCI controllers often implement SFF compatible interface.
1298 * Grab all PCI BARs just in case.
1300 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1302 pcim_pin_device(pdev);
1306 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1307 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1310 /* ICH6s share the same PCI ID for both piix and ahci
1311 * modes. Enabling ahci mode while MAP indicates
1312 * combined mode is a bad idea. Yield to ata_piix.
1314 pci_read_config_byte(pdev, ICH_MAP, &map);
1316 dev_info(&pdev->dev,
1317 "controller is in combined mode, can't enable AHCI mode\n");
1322 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1325 hpriv->flags |= (unsigned long)pi.private_data;
1327 /* MCP65 revision A1 and A2 can't do MSI */
1328 if (board_id == board_ahci_mcp65 &&
1329 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1330 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1332 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1333 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1334 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1336 /* only some SB600s can do 64bit DMA */
1337 if (ahci_sb600_enable_64bit(pdev))
1338 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1340 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1343 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1345 /* save initial config */
1346 ahci_pci_save_initial_config(pdev, hpriv);
1349 if (hpriv->cap & HOST_CAP_NCQ) {
1350 pi.flags |= ATA_FLAG_NCQ;
1352 * Auto-activate optimization is supposed to be
1353 * supported on all AHCI controllers indicating NCQ
1354 * capability, but it seems to be broken on some
1355 * chipsets including NVIDIAs.
1357 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1358 pi.flags |= ATA_FLAG_FPDMA_AA;
1361 if (hpriv->cap & HOST_CAP_PMP)
1362 pi.flags |= ATA_FLAG_PMP;
1364 ahci_set_em_messages(hpriv, &pi);
1366 if (ahci_broken_system_poweroff(pdev)) {
1367 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1368 dev_info(&pdev->dev,
1369 "quirky BIOS, skipping spindown on poweroff\n");
1372 if (ahci_broken_suspend(pdev)) {
1373 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1374 dev_warn(&pdev->dev,
1375 "BIOS update required for suspend/resume\n");
1378 if (ahci_broken_online(pdev)) {
1379 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1380 dev_info(&pdev->dev,
1381 "online status unreliable, applying workaround\n");
1384 /* CAP.NP sometimes indicate the index of the last enabled
1385 * port, at other times, that of the last possible port, so
1386 * determining the maximum port number requires looking at
1387 * both CAP.NP and port_map.
1389 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1391 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1394 host->private_data = hpriv;
1396 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1397 host->flags |= ATA_HOST_PARALLEL_SCAN;
1399 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1401 if (pi.flags & ATA_FLAG_EM)
1402 ahci_reset_em(host);
1404 for (i = 0; i < host->n_ports; i++) {
1405 struct ata_port *ap = host->ports[i];
1407 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1408 ata_port_pbar_desc(ap, ahci_pci_bar,
1409 0x100 + ap->port_no * 0x80, "port");
1411 /* set enclosure management message type */
1412 if (ap->flags & ATA_FLAG_EM)
1413 ap->em_message_type = hpriv->em_msg_type;
1416 /* disabled/not-implemented port */
1417 if (!(hpriv->port_map & (1 << i)))
1418 ap->ops = &ata_dummy_port_ops;
1421 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1422 ahci_p5wdh_workaround(host);
1424 /* apply gtf filter quirk */
1425 ahci_gtf_filter_workaround(host);
1427 /* initialize adapter */
1428 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1432 rc = ahci_pci_reset_controller(host);
1436 ahci_pci_init_controller(host);
1437 ahci_pci_print_info(host);
1439 pci_set_master(pdev);
1440 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1444 static int __init ahci_init(void)
1446 return pci_register_driver(&ahci_pci_driver);
1449 static void __exit ahci_exit(void)
1451 pci_unregister_driver(&ahci_pci_driver);
1455 MODULE_AUTHOR("Jeff Garzik");
1456 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1457 MODULE_LICENSE("GPL");
1458 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1459 MODULE_VERSION(DRV_VERSION);
1461 module_init(ahci_init);
1462 module_exit(ahci_exit);