2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] =
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nosntf] =
128 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_yes_fbs] =
136 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
180 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
181 AHCI_HFLAG_32BIT_ONLY),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_pmp_retry_srst_ops,
187 [board_ahci_sb700] = /* for SB700 and SB800 */
189 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_vt8251] =
197 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_vt8251_ops,
205 static const struct pci_device_id ahci_pci_tbl[] = {
207 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
208 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
209 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
210 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
211 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
212 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
213 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
216 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
217 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
220 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
222 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
236 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
239 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
249 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
254 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
257 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
260 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
274 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
275 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
278 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
282 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
283 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
298 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
302 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
306 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
307 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
308 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
309 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
311 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
312 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
313 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
316 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
317 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
318 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
325 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
326 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
327 /* AMD is using RAID class only for ahci controllers */
328 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
329 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
332 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
333 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
336 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426 /* ST Microelectronics */
427 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
430 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
431 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
433 .class = PCI_CLASS_STORAGE_SATA_AHCI,
434 .class_mask = 0xffffff,
435 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
438 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
439 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
440 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
442 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
443 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
444 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
446 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
447 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
448 .driver_data = board_ahci_yes_fbs },
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
450 .driver_data = board_ahci_yes_fbs },
453 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
456 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
457 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
458 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
459 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
462 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
464 /* Generic, PCI class code for AHCI */
465 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
466 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
468 { } /* terminate list */
472 static struct pci_driver ahci_pci_driver = {
474 .id_table = ahci_pci_tbl,
475 .probe = ahci_init_one,
476 .remove = ata_pci_remove_one,
478 .suspend = ahci_pci_device_suspend,
479 .resume = ahci_pci_device_resume,
483 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
484 static int marvell_enable;
486 static int marvell_enable = 1;
488 module_param(marvell_enable, int, 0644);
489 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
492 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
493 struct ahci_host_priv *hpriv)
495 unsigned int force_port_map = 0;
496 unsigned int mask_port_map = 0;
498 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
499 dev_info(&pdev->dev, "JMB361 has only one port\n");
504 * Temporary Marvell 6145 hack: PATA port presence
505 * is asserted through the standard AHCI port
506 * presence register, as bit 4 (counting from 0)
508 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
509 if (pdev->device == 0x6121)
514 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
517 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
521 static int ahci_pci_reset_controller(struct ata_host *host)
523 struct pci_dev *pdev = to_pci_dev(host->dev);
525 ahci_reset_controller(host);
527 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
528 struct ahci_host_priv *hpriv = host->private_data;
532 pci_read_config_word(pdev, 0x92, &tmp16);
533 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
534 tmp16 |= hpriv->port_map;
535 pci_write_config_word(pdev, 0x92, tmp16);
542 static void ahci_pci_init_controller(struct ata_host *host)
544 struct ahci_host_priv *hpriv = host->private_data;
545 struct pci_dev *pdev = to_pci_dev(host->dev);
546 void __iomem *port_mmio;
550 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
551 if (pdev->device == 0x6121)
555 port_mmio = __ahci_port_base(host, mv);
557 writel(0, port_mmio + PORT_IRQ_MASK);
560 tmp = readl(port_mmio + PORT_IRQ_STAT);
561 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
563 writel(tmp, port_mmio + PORT_IRQ_STAT);
566 ahci_init_controller(host);
569 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
570 unsigned long deadline)
572 struct ata_port *ap = link->ap;
578 ahci_stop_engine(ap);
580 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
581 deadline, &online, NULL);
583 ahci_start_engine(ap);
585 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
587 /* vt8251 doesn't clear BSY on signature FIS reception,
588 * request follow-up softreset.
590 return online ? -EAGAIN : rc;
593 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
594 unsigned long deadline)
596 struct ata_port *ap = link->ap;
597 struct ahci_port_priv *pp = ap->private_data;
598 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
599 struct ata_taskfile tf;
603 ahci_stop_engine(ap);
605 /* clear D2H reception area to properly wait for D2H FIS */
606 ata_tf_init(link->device, &tf);
608 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
610 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
611 deadline, &online, NULL);
613 ahci_start_engine(ap);
615 /* The pseudo configuration device on SIMG4726 attached to
616 * ASUS P5W-DH Deluxe doesn't send signature FIS after
617 * hardreset if no device is attached to the first downstream
618 * port && the pseudo device locks up on SRST w/ PMP==0. To
619 * work around this, wait for !BSY only briefly. If BSY isn't
620 * cleared, perform CLO and proceed to IDENTIFY (achieved by
621 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
623 * Wait for two seconds. Devices attached to downstream port
624 * which can't process the following IDENTIFY after this will
625 * have to be reset again. For most cases, this should
626 * suffice while making probing snappish enough.
629 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
632 ahci_kick_engine(ap);
638 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
640 struct ata_host *host = dev_get_drvdata(&pdev->dev);
641 struct ahci_host_priv *hpriv = host->private_data;
642 void __iomem *mmio = hpriv->mmio;
645 if (mesg.event & PM_EVENT_SUSPEND &&
646 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
648 "BIOS update required for suspend/resume\n");
652 if (mesg.event & PM_EVENT_SLEEP) {
653 /* AHCI spec rev1.1 section 8.3.3:
654 * Software must disable interrupts prior to requesting a
655 * transition of the HBA to D3 state.
657 ctl = readl(mmio + HOST_CTL);
659 writel(ctl, mmio + HOST_CTL);
660 readl(mmio + HOST_CTL); /* flush */
663 return ata_pci_device_suspend(pdev, mesg);
666 static int ahci_pci_device_resume(struct pci_dev *pdev)
668 struct ata_host *host = dev_get_drvdata(&pdev->dev);
671 rc = ata_pci_device_do_resume(pdev);
675 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
676 rc = ahci_pci_reset_controller(host);
680 ahci_pci_init_controller(host);
683 ata_host_resume(host);
689 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
694 * If the device fixup already set the dma_mask to some non-standard
695 * value, don't extend it here. This happens on STA2X11, for example.
697 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
701 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
702 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
704 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
707 "64-bit DMA enable failed\n");
712 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
714 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
717 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
720 "32-bit consistent DMA enable failed\n");
727 static void ahci_pci_print_info(struct ata_host *host)
729 struct pci_dev *pdev = to_pci_dev(host->dev);
733 pci_read_config_word(pdev, 0x0a, &cc);
734 if (cc == PCI_CLASS_STORAGE_IDE)
736 else if (cc == PCI_CLASS_STORAGE_SATA)
738 else if (cc == PCI_CLASS_STORAGE_RAID)
743 ahci_print_info(host, scc_s);
746 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
747 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
748 * support PMP and the 4726 either directly exports the device
749 * attached to the first downstream port or acts as a hardware storage
750 * controller and emulate a single ATA device (can be RAID 0/1 or some
751 * other configuration).
753 * When there's no device attached to the first downstream port of the
754 * 4726, "Config Disk" appears, which is a pseudo ATA device to
755 * configure the 4726. However, ATA emulation of the device is very
756 * lame. It doesn't send signature D2H Reg FIS after the initial
757 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
759 * The following function works around the problem by always using
760 * hardreset on the port and not depending on receiving signature FIS
761 * afterward. If signature FIS isn't received soon, ATA class is
762 * assumed without follow-up softreset.
764 static void ahci_p5wdh_workaround(struct ata_host *host)
766 static struct dmi_system_id sysids[] = {
768 .ident = "P5W DH Deluxe",
770 DMI_MATCH(DMI_SYS_VENDOR,
771 "ASUSTEK COMPUTER INC"),
772 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
777 struct pci_dev *pdev = to_pci_dev(host->dev);
779 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
780 dmi_check_system(sysids)) {
781 struct ata_port *ap = host->ports[1];
784 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
786 ap->ops = &ahci_p5wdh_ops;
787 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
791 /* only some SB600 ahci controllers can do 64bit DMA */
792 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
794 static const struct dmi_system_id sysids[] = {
796 * The oldest version known to be broken is 0901 and
797 * working is 1501 which was released on 2007-10-26.
798 * Enable 64bit DMA on 1501 and anything newer.
800 * Please read bko#9412 for more info.
803 .ident = "ASUS M2A-VM",
805 DMI_MATCH(DMI_BOARD_VENDOR,
806 "ASUSTeK Computer INC."),
807 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
809 .driver_data = "20071026", /* yyyymmdd */
812 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
815 * BIOS versions earlier than 1.5 had the Manufacturer DMI
816 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
817 * This spelling mistake was fixed in BIOS version 1.5, so
818 * 1.5 and later have the Manufacturer as
819 * "MICRO-STAR INTERNATIONAL CO.,LTD".
820 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
822 * BIOS versions earlier than 1.9 had a Board Product Name
823 * DMI field of "MS-7376". This was changed to be
824 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
825 * match on DMI_BOARD_NAME of "MS-7376".
828 .ident = "MSI K9A2 Platinum",
830 DMI_MATCH(DMI_BOARD_VENDOR,
832 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
836 * All BIOS versions for the Asus M3A support 64bit DMA.
837 * (all release versions from 0301 to 1206 were tested)
842 DMI_MATCH(DMI_BOARD_VENDOR,
843 "ASUSTeK Computer INC."),
844 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
849 const struct dmi_system_id *match;
850 int year, month, date;
853 match = dmi_first_match(sysids);
854 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
858 if (!match->driver_data)
861 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
862 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
864 if (strcmp(buf, match->driver_data) >= 0)
868 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
874 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
878 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
880 static const struct dmi_system_id broken_systems[] = {
882 .ident = "HP Compaq nx6310",
884 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
885 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
887 /* PCI slot number of the controller */
888 .driver_data = (void *)0x1FUL,
891 .ident = "HP Compaq 6720s",
893 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
894 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
896 /* PCI slot number of the controller */
897 .driver_data = (void *)0x1FUL,
900 { } /* terminate list */
902 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
905 unsigned long slot = (unsigned long)dmi->driver_data;
906 /* apply the quirk only to on-board controllers */
907 return slot == PCI_SLOT(pdev->devfn);
913 static bool ahci_broken_suspend(struct pci_dev *pdev)
915 static const struct dmi_system_id sysids[] = {
917 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
918 * to the harddisk doesn't become online after
919 * resuming from STR. Warn and fail suspend.
921 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
923 * Use dates instead of versions to match as HP is
924 * apparently recycling both product and version
927 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
932 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
933 DMI_MATCH(DMI_PRODUCT_NAME,
934 "HP Pavilion dv4 Notebook PC"),
936 .driver_data = "20090105", /* F.30 */
941 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
942 DMI_MATCH(DMI_PRODUCT_NAME,
943 "HP Pavilion dv5 Notebook PC"),
945 .driver_data = "20090506", /* F.16 */
950 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
951 DMI_MATCH(DMI_PRODUCT_NAME,
952 "HP Pavilion dv6 Notebook PC"),
954 .driver_data = "20090423", /* F.21 */
959 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
960 DMI_MATCH(DMI_PRODUCT_NAME,
961 "HP HDX18 Notebook PC"),
963 .driver_data = "20090430", /* F.23 */
966 * Acer eMachines G725 has the same problem. BIOS
967 * V1.03 is known to be broken. V3.04 is known to
968 * work. Between, there are V1.06, V2.06 and V3.03
969 * that we don't have much idea about. For now,
970 * blacklist anything older than V3.04.
972 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
977 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
978 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
980 .driver_data = "20091216", /* V3.04 */
982 { } /* terminate list */
984 const struct dmi_system_id *dmi = dmi_first_match(sysids);
985 int year, month, date;
988 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
991 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
992 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
994 return strcmp(buf, dmi->driver_data) < 0;
997 static bool ahci_broken_online(struct pci_dev *pdev)
999 #define ENCODE_BUSDEVFN(bus, slot, func) \
1000 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1001 static const struct dmi_system_id sysids[] = {
1003 * There are several gigabyte boards which use
1004 * SIMG5723s configured as hardware RAID. Certain
1005 * 5723 firmware revisions shipped there keep the link
1006 * online but fail to answer properly to SRST or
1007 * IDENTIFY when no device is attached downstream
1008 * causing libata to retry quite a few times leading
1009 * to excessive detection delay.
1011 * As these firmwares respond to the second reset try
1012 * with invalid device signature, considering unknown
1013 * sig as offline works around the problem acceptably.
1016 .ident = "EP45-DQ6",
1018 DMI_MATCH(DMI_BOARD_VENDOR,
1019 "Gigabyte Technology Co., Ltd."),
1020 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1022 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1025 .ident = "EP45-DS5",
1027 DMI_MATCH(DMI_BOARD_VENDOR,
1028 "Gigabyte Technology Co., Ltd."),
1029 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1031 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1033 { } /* terminate list */
1035 #undef ENCODE_BUSDEVFN
1036 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1042 val = (unsigned long)dmi->driver_data;
1044 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1047 #ifdef CONFIG_ATA_ACPI
1048 static void ahci_gtf_filter_workaround(struct ata_host *host)
1050 static const struct dmi_system_id sysids[] = {
1052 * Aspire 3810T issues a bunch of SATA enable commands
1053 * via _GTF including an invalid one and one which is
1054 * rejected by the device. Among the successful ones
1055 * is FPDMA non-zero offset enable which when enabled
1056 * only on the drive side leads to NCQ command
1057 * failures. Filter it out.
1060 .ident = "Aspire 3810T",
1062 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1065 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1069 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1070 unsigned int filter;
1076 filter = (unsigned long)dmi->driver_data;
1077 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1078 filter, dmi->ident);
1080 for (i = 0; i < host->n_ports; i++) {
1081 struct ata_port *ap = host->ports[i];
1082 struct ata_link *link;
1083 struct ata_device *dev;
1085 ata_for_each_link(link, ap, EDGE)
1086 ata_for_each_dev(dev, link, ALL)
1087 dev->gtf_filter |= filter;
1091 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1095 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1097 unsigned int board_id = ent->driver_data;
1098 struct ata_port_info pi = ahci_port_info[board_id];
1099 const struct ata_port_info *ppi[] = { &pi, NULL };
1100 struct device *dev = &pdev->dev;
1101 struct ahci_host_priv *hpriv;
1102 struct ata_host *host;
1104 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1108 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1110 ata_print_version_once(&pdev->dev, DRV_VERSION);
1112 /* The AHCI driver can only drive the SATA ports, the PATA driver
1113 can drive them all so if both drivers are selected make sure
1114 AHCI stays out of the way */
1115 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1119 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1120 * ahci, use ata_generic instead.
1122 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1123 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1124 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1125 pdev->subsystem_device == 0xcb89)
1128 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1129 * At the moment, we can only use the AHCI mode. Let the users know
1130 * that for SAS drives they're out of luck.
1132 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1133 dev_info(&pdev->dev,
1134 "PDC42819 can only drive SATA devices with this driver\n");
1136 /* Both Connext and Enmotus devices use non-standard BARs */
1137 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1138 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1139 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1140 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1142 /* acquire resources */
1143 rc = pcim_enable_device(pdev);
1147 /* AHCI controllers often implement SFF compatible interface.
1148 * Grab all PCI BARs just in case.
1150 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1152 pcim_pin_device(pdev);
1156 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1157 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1160 /* ICH6s share the same PCI ID for both piix and ahci
1161 * modes. Enabling ahci mode while MAP indicates
1162 * combined mode is a bad idea. Yield to ata_piix.
1164 pci_read_config_byte(pdev, ICH_MAP, &map);
1166 dev_info(&pdev->dev,
1167 "controller is in combined mode, can't enable AHCI mode\n");
1172 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1175 hpriv->flags |= (unsigned long)pi.private_data;
1177 /* MCP65 revision A1 and A2 can't do MSI */
1178 if (board_id == board_ahci_mcp65 &&
1179 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1180 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1182 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1183 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1184 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1186 /* only some SB600s can do 64bit DMA */
1187 if (ahci_sb600_enable_64bit(pdev))
1188 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1190 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1193 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1195 /* save initial config */
1196 ahci_pci_save_initial_config(pdev, hpriv);
1199 if (hpriv->cap & HOST_CAP_NCQ) {
1200 pi.flags |= ATA_FLAG_NCQ;
1202 * Auto-activate optimization is supposed to be
1203 * supported on all AHCI controllers indicating NCQ
1204 * capability, but it seems to be broken on some
1205 * chipsets including NVIDIAs.
1207 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1208 pi.flags |= ATA_FLAG_FPDMA_AA;
1211 if (hpriv->cap & HOST_CAP_PMP)
1212 pi.flags |= ATA_FLAG_PMP;
1214 ahci_set_em_messages(hpriv, &pi);
1216 if (ahci_broken_system_poweroff(pdev)) {
1217 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1218 dev_info(&pdev->dev,
1219 "quirky BIOS, skipping spindown on poweroff\n");
1222 if (ahci_broken_suspend(pdev)) {
1223 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1224 dev_warn(&pdev->dev,
1225 "BIOS update required for suspend/resume\n");
1228 if (ahci_broken_online(pdev)) {
1229 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1230 dev_info(&pdev->dev,
1231 "online status unreliable, applying workaround\n");
1234 /* CAP.NP sometimes indicate the index of the last enabled
1235 * port, at other times, that of the last possible port, so
1236 * determining the maximum port number requires looking at
1237 * both CAP.NP and port_map.
1239 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1241 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1244 host->private_data = hpriv;
1246 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1247 host->flags |= ATA_HOST_PARALLEL_SCAN;
1249 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1251 if (pi.flags & ATA_FLAG_EM)
1252 ahci_reset_em(host);
1254 for (i = 0; i < host->n_ports; i++) {
1255 struct ata_port *ap = host->ports[i];
1257 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1258 ata_port_pbar_desc(ap, ahci_pci_bar,
1259 0x100 + ap->port_no * 0x80, "port");
1261 /* set enclosure management message type */
1262 if (ap->flags & ATA_FLAG_EM)
1263 ap->em_message_type = hpriv->em_msg_type;
1266 /* disabled/not-implemented port */
1267 if (!(hpriv->port_map & (1 << i)))
1268 ap->ops = &ata_dummy_port_ops;
1271 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1272 ahci_p5wdh_workaround(host);
1274 /* apply gtf filter quirk */
1275 ahci_gtf_filter_workaround(host);
1277 /* initialize adapter */
1278 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1282 rc = ahci_pci_reset_controller(host);
1286 ahci_pci_init_controller(host);
1287 ahci_pci_print_info(host);
1289 pci_set_master(pdev);
1290 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1294 static int __init ahci_init(void)
1296 return pci_register_driver(&ahci_pci_driver);
1299 static void __exit ahci_exit(void)
1301 pci_unregister_driver(&ahci_pci_driver);
1305 MODULE_AUTHOR("Jeff Garzik");
1306 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1307 MODULE_LICENSE("GPL");
1308 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1309 MODULE_VERSION(DRV_VERSION);
1311 module_init(ahci_init);
1312 module_exit(ahci_exit);